1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
114 /* required last entry */
117 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
119 #ifdef CONFIG_IXGBE_DCA
120 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
122 static struct notifier_block dca_notifier
= {
123 .notifier_call
= ixgbe_notify_dca
,
129 #ifdef CONFIG_PCI_IOV
130 static unsigned int max_vfs
;
131 module_param(max_vfs
, uint
, 0);
132 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
133 "per physical function");
134 #endif /* CONFIG_PCI_IOV */
136 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
137 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
138 MODULE_LICENSE("GPL");
139 MODULE_VERSION(DRV_VERSION
);
141 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
143 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
145 struct ixgbe_hw
*hw
= &adapter
->hw
;
150 #ifdef CONFIG_PCI_IOV
151 /* disable iov and allow time for transactions to clear */
152 pci_disable_sriov(adapter
->pdev
);
155 /* turn off device IOV mode */
156 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
157 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
158 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
159 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
160 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
161 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
163 /* set default pool back to 0 */
164 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
165 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
166 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
168 /* take a breather then clean up driver data */
171 kfree(adapter
->vfinfo
);
172 adapter
->vfinfo
= NULL
;
174 adapter
->num_vfs
= 0;
175 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
178 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
182 /* Let firmware take over control of h/w */
183 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
184 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
185 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
188 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
192 /* Let firmware know the driver has taken over */
193 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
194 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
195 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
199 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
200 * @adapter: pointer to adapter struct
201 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
202 * @queue: queue to map the corresponding interrupt to
203 * @msix_vector: the vector to map to the corresponding queue
206 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
207 u8 queue
, u8 msix_vector
)
210 struct ixgbe_hw
*hw
= &adapter
->hw
;
211 switch (hw
->mac
.type
) {
212 case ixgbe_mac_82598EB
:
213 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
216 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
217 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
218 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
219 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
220 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
222 case ixgbe_mac_82599EB
:
223 if (direction
== -1) {
225 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
226 index
= ((queue
& 1) * 8);
227 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
228 ivar
&= ~(0xFF << index
);
229 ivar
|= (msix_vector
<< index
);
230 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
233 /* tx or rx causes */
234 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
235 index
= ((16 * (queue
& 1)) + (8 * direction
));
236 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
237 ivar
&= ~(0xFF << index
);
238 ivar
|= (msix_vector
<< index
);
239 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
247 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
252 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
253 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
254 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
256 mask
= (qmask
& 0xFFFFFFFF);
257 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
258 mask
= (qmask
>> 32);
259 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
263 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
264 struct ixgbe_tx_buffer
267 if (tx_buffer_info
->dma
) {
268 if (tx_buffer_info
->mapped_as_page
)
269 pci_unmap_page(adapter
->pdev
,
271 tx_buffer_info
->length
,
274 pci_unmap_single(adapter
->pdev
,
276 tx_buffer_info
->length
,
278 tx_buffer_info
->dma
= 0;
280 if (tx_buffer_info
->skb
) {
281 dev_kfree_skb_any(tx_buffer_info
->skb
);
282 tx_buffer_info
->skb
= NULL
;
284 tx_buffer_info
->time_stamp
= 0;
285 /* tx_buffer_info must be completely set up in the transmit path */
289 * ixgbe_tx_is_paused - check if the tx ring is paused
290 * @adapter: the ixgbe adapter
291 * @tx_ring: the corresponding tx_ring
293 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
294 * corresponding TC of this tx_ring when checking TFCS.
296 * Returns : true if paused
298 static inline bool ixgbe_tx_is_paused(struct ixgbe_adapter
*adapter
,
299 struct ixgbe_ring
*tx_ring
)
301 u32 txoff
= IXGBE_TFCS_TXOFF
;
303 #ifdef CONFIG_IXGBE_DCB
304 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
306 int reg_idx
= tx_ring
->reg_idx
;
307 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
309 switch (adapter
->hw
.mac
.type
) {
310 case ixgbe_mac_82598EB
:
312 txoff
= IXGBE_TFCS_TXOFF0
;
314 case ixgbe_mac_82599EB
:
316 txoff
= IXGBE_TFCS_TXOFF
;
320 if (tc
== 2) /* TC2, TC3 */
321 tc
+= (reg_idx
- 64) >> 4;
322 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
323 tc
+= 1 + ((reg_idx
- 96) >> 3);
324 } else if (dcb_i
== 4) {
328 tc
+= (reg_idx
- 64) >> 5;
329 if (tc
== 2) /* TC2, TC3 */
330 tc
+= (reg_idx
- 96) >> 4;
340 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
343 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
344 struct ixgbe_ring
*tx_ring
,
347 struct ixgbe_hw
*hw
= &adapter
->hw
;
349 /* Detect a transmit hang in hardware, this serializes the
350 * check with the clearing of time_stamp and movement of eop */
351 adapter
->detect_tx_hung
= false;
352 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
353 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
354 !ixgbe_tx_is_paused(adapter
, tx_ring
)) {
355 /* detected Tx unit hang */
356 union ixgbe_adv_tx_desc
*tx_desc
;
357 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
358 DPRINTK(DRV
, ERR
, "Detected Tx Unit Hang\n"
360 " TDH, TDT <%x>, <%x>\n"
361 " next_to_use <%x>\n"
362 " next_to_clean <%x>\n"
363 "tx_buffer_info[next_to_clean]\n"
364 " time_stamp <%lx>\n"
366 tx_ring
->queue_index
,
367 IXGBE_READ_REG(hw
, tx_ring
->head
),
368 IXGBE_READ_REG(hw
, tx_ring
->tail
),
369 tx_ring
->next_to_use
, eop
,
370 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
377 #define IXGBE_MAX_TXD_PWR 14
378 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
380 /* Tx Descriptors needed, worst case */
381 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
382 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
383 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
384 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
386 static void ixgbe_tx_timeout(struct net_device
*netdev
);
389 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
390 * @q_vector: structure containing interrupt and ring information
391 * @tx_ring: tx ring to clean
393 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
394 struct ixgbe_ring
*tx_ring
)
396 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
397 struct net_device
*netdev
= adapter
->netdev
;
398 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
399 struct ixgbe_tx_buffer
*tx_buffer_info
;
400 unsigned int i
, eop
, count
= 0;
401 unsigned int total_bytes
= 0, total_packets
= 0;
403 i
= tx_ring
->next_to_clean
;
404 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
405 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
407 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
408 (count
< tx_ring
->work_limit
)) {
409 bool cleaned
= false;
410 for ( ; !cleaned
; count
++) {
412 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
413 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
414 cleaned
= (i
== eop
);
415 skb
= tx_buffer_info
->skb
;
417 if (cleaned
&& skb
) {
418 unsigned int segs
, bytecount
;
419 unsigned int hlen
= skb_headlen(skb
);
421 /* gso_segs is currently only valid for tcp */
422 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
424 /* adjust for FCoE Sequence Offload */
425 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
426 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
428 hlen
= skb_transport_offset(skb
) +
429 sizeof(struct fc_frame_header
) +
430 sizeof(struct fcoe_crc_eof
);
431 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
432 skb_shinfo(skb
)->gso_size
);
434 #endif /* IXGBE_FCOE */
435 /* multiply data chunks by size of headers */
436 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
437 total_packets
+= segs
;
438 total_bytes
+= bytecount
;
441 ixgbe_unmap_and_free_tx_resource(adapter
,
444 tx_desc
->wb
.status
= 0;
447 if (i
== tx_ring
->count
)
451 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
452 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
455 tx_ring
->next_to_clean
= i
;
457 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
458 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
459 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
460 /* Make sure that anybody stopping the queue after this
461 * sees the new next_to_clean.
464 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
465 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
466 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
467 ++tx_ring
->restart_queue
;
471 if (adapter
->detect_tx_hung
) {
472 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
473 /* schedule immediate reset if we believe we hung */
475 "tx hang %d detected, resetting adapter\n",
476 adapter
->tx_timeout_count
+ 1);
477 ixgbe_tx_timeout(adapter
->netdev
);
481 /* re-arm the interrupt */
482 if (count
>= tx_ring
->work_limit
)
483 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
485 tx_ring
->total_bytes
+= total_bytes
;
486 tx_ring
->total_packets
+= total_packets
;
487 tx_ring
->stats
.packets
+= total_packets
;
488 tx_ring
->stats
.bytes
+= total_bytes
;
489 return (count
< tx_ring
->work_limit
);
492 #ifdef CONFIG_IXGBE_DCA
493 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
494 struct ixgbe_ring
*rx_ring
)
498 int q
= rx_ring
->reg_idx
;
500 if (rx_ring
->cpu
!= cpu
) {
501 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
502 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
503 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
504 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
505 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
506 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
507 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
508 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
510 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
511 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
512 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
513 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
514 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
515 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
521 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
522 struct ixgbe_ring
*tx_ring
)
526 int q
= tx_ring
->reg_idx
;
527 struct ixgbe_hw
*hw
= &adapter
->hw
;
529 if (tx_ring
->cpu
!= cpu
) {
530 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
531 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
532 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
533 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
534 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
535 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
536 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
537 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
538 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
539 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
540 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
541 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
542 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
549 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
553 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
556 /* always use CB2 mode, difference is masked in the CB driver */
557 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
559 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
560 adapter
->tx_ring
[i
]->cpu
= -1;
561 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
563 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
564 adapter
->rx_ring
[i
]->cpu
= -1;
565 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
569 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
571 struct net_device
*netdev
= dev_get_drvdata(dev
);
572 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
573 unsigned long event
= *(unsigned long *)data
;
576 case DCA_PROVIDER_ADD
:
577 /* if we're already enabled, don't do it again */
578 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
580 if (dca_add_requester(dev
) == 0) {
581 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
582 ixgbe_setup_dca(adapter
);
585 /* Fall Through since DCA is disabled. */
586 case DCA_PROVIDER_REMOVE
:
587 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
588 dca_remove_requester(dev
);
589 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
590 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
598 #endif /* CONFIG_IXGBE_DCA */
600 * ixgbe_receive_skb - Send a completed packet up the stack
601 * @adapter: board private structure
602 * @skb: packet to send up
603 * @status: hardware indication of status of receive
604 * @rx_ring: rx descriptor ring (for a specific queue) to setup
605 * @rx_desc: rx descriptor
607 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
608 struct sk_buff
*skb
, u8 status
,
609 struct ixgbe_ring
*ring
,
610 union ixgbe_adv_rx_desc
*rx_desc
)
612 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
613 struct napi_struct
*napi
= &q_vector
->napi
;
614 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
615 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
617 skb_record_rx_queue(skb
, ring
->queue_index
);
618 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
619 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
620 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
622 napi_gro_receive(napi
, skb
);
624 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
625 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
632 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
633 * @adapter: address of board private structure
634 * @status_err: hardware indication of status of receive
635 * @skb: skb currently being received and modified
637 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
638 union ixgbe_adv_rx_desc
*rx_desc
,
641 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
643 skb
->ip_summed
= CHECKSUM_NONE
;
645 /* Rx csum disabled */
646 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
649 /* if IP and error */
650 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
651 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
652 adapter
->hw_csum_rx_error
++;
656 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
659 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
660 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
663 * 82599 errata, UDP frames with a 0 checksum can be marked as
666 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
667 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
670 adapter
->hw_csum_rx_error
++;
674 /* It must be a TCP or UDP packet with a valid checksum */
675 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
678 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
679 struct ixgbe_ring
*rx_ring
, u32 val
)
682 * Force memory writes to complete before letting h/w
683 * know there are new descriptors to fetch. (Only
684 * applicable for weak-ordered memory model archs,
688 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
692 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
693 * @adapter: address of board private structure
695 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
696 struct ixgbe_ring
*rx_ring
,
699 struct pci_dev
*pdev
= adapter
->pdev
;
700 union ixgbe_adv_rx_desc
*rx_desc
;
701 struct ixgbe_rx_buffer
*bi
;
704 i
= rx_ring
->next_to_use
;
705 bi
= &rx_ring
->rx_buffer_info
[i
];
707 while (cleaned_count
--) {
708 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
711 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
713 bi
->page
= alloc_page(GFP_ATOMIC
);
715 adapter
->alloc_rx_page_failed
++;
720 /* use a half page if we're re-using */
721 bi
->page_offset
^= (PAGE_SIZE
/ 2);
724 bi
->page_dma
= pci_map_page(pdev
, bi
->page
,
732 /* netdev_alloc_skb reserves 32 bytes up front!! */
733 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
734 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
737 adapter
->alloc_rx_buff_failed
++;
741 /* advance the data pointer to the next cache line */
742 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
746 bi
->dma
= pci_map_single(pdev
, skb
->data
,
750 /* Refresh the desc even if buffer_addrs didn't change because
751 * each write-back erases this info. */
752 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
753 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
754 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
756 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
760 if (i
== rx_ring
->count
)
762 bi
= &rx_ring
->rx_buffer_info
[i
];
766 if (rx_ring
->next_to_use
!= i
) {
767 rx_ring
->next_to_use
= i
;
769 i
= (rx_ring
->count
- 1);
771 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
775 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
777 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
780 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
782 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
785 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
787 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
788 IXGBE_RXDADV_RSCCNT_MASK
) >>
789 IXGBE_RXDADV_RSCCNT_SHIFT
;
793 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
794 * @skb: pointer to the last skb in the rsc queue
795 * @count: pointer to number of packets coalesced in this context
797 * This function changes a queue full of hw rsc buffers into a completed
798 * packet. It uses the ->prev pointers to find the first packet and then
799 * turns it into the frag list owner.
801 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
804 unsigned int frag_list_size
= 0;
807 struct sk_buff
*prev
= skb
->prev
;
808 frag_list_size
+= skb
->len
;
814 skb_shinfo(skb
)->frag_list
= skb
->next
;
816 skb
->len
+= frag_list_size
;
817 skb
->data_len
+= frag_list_size
;
818 skb
->truesize
+= frag_list_size
;
822 struct ixgbe_rsc_cb
{
826 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
828 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
829 struct ixgbe_ring
*rx_ring
,
830 int *work_done
, int work_to_do
)
832 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
833 struct net_device
*netdev
= adapter
->netdev
;
834 struct pci_dev
*pdev
= adapter
->pdev
;
835 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
836 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
838 unsigned int i
, rsc_count
= 0;
841 bool cleaned
= false;
842 int cleaned_count
= 0;
843 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
846 #endif /* IXGBE_FCOE */
848 i
= rx_ring
->next_to_clean
;
849 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
850 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
851 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
853 while (staterr
& IXGBE_RXD_STAT_DD
) {
855 if (*work_done
>= work_to_do
)
859 rmb(); /* read descriptor and rx_buffer_info after status DD */
860 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
861 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
862 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
863 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
864 if (len
> IXGBE_RX_HDR_SIZE
)
865 len
= IXGBE_RX_HDR_SIZE
;
866 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
868 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
872 skb
= rx_buffer_info
->skb
;
874 rx_buffer_info
->skb
= NULL
;
876 if (rx_buffer_info
->dma
) {
877 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
878 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
881 * When HWRSC is enabled, delay unmapping
882 * of the first packet. It carries the
883 * header information, HW may still
884 * access the header after the writeback.
885 * Only unmap it when EOP is reached
887 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
889 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
892 rx_buffer_info
->dma
= 0;
897 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
898 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
899 rx_buffer_info
->page_dma
= 0;
900 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
901 rx_buffer_info
->page
,
902 rx_buffer_info
->page_offset
,
905 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
906 (page_count(rx_buffer_info
->page
) != 1))
907 rx_buffer_info
->page
= NULL
;
909 get_page(rx_buffer_info
->page
);
911 skb
->len
+= upper_len
;
912 skb
->data_len
+= upper_len
;
913 skb
->truesize
+= upper_len
;
917 if (i
== rx_ring
->count
)
920 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
924 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
925 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
928 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
929 IXGBE_RXDADV_NEXTP_SHIFT
;
930 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
932 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
935 if (staterr
& IXGBE_RXD_STAT_EOP
) {
937 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
938 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
939 if (IXGBE_RSC_CB(skb
)->dma
) {
940 pci_unmap_single(pdev
, IXGBE_RSC_CB(skb
)->dma
,
943 IXGBE_RSC_CB(skb
)->dma
= 0;
945 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
946 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
948 rx_ring
->rsc_count
++;
949 rx_ring
->rsc_flush
++;
951 rx_ring
->stats
.packets
++;
952 rx_ring
->stats
.bytes
+= skb
->len
;
954 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
955 rx_buffer_info
->skb
= next_buffer
->skb
;
956 rx_buffer_info
->dma
= next_buffer
->dma
;
957 next_buffer
->skb
= skb
;
958 next_buffer
->dma
= 0;
960 skb
->next
= next_buffer
->skb
;
961 skb
->next
->prev
= skb
;
963 rx_ring
->non_eop_descs
++;
967 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
968 dev_kfree_skb_irq(skb
);
972 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
974 /* probably a little skewed due to removing CRC */
975 total_rx_bytes
+= skb
->len
;
978 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
980 /* if ddp, not passing to ULD unless for FCP_RSP or error */
981 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
982 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
986 #endif /* IXGBE_FCOE */
987 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
990 rx_desc
->wb
.upper
.status_error
= 0;
992 /* return some buffers to hardware, one at a time is too slow */
993 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
994 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
998 /* use prefetched values */
1000 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1002 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1005 rx_ring
->next_to_clean
= i
;
1006 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1009 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1012 /* include DDPed FCoE data */
1013 if (ddp_bytes
> 0) {
1016 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1017 sizeof(struct fc_frame_header
) -
1018 sizeof(struct fcoe_crc_eof
);
1021 total_rx_bytes
+= ddp_bytes
;
1022 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1024 #endif /* IXGBE_FCOE */
1026 rx_ring
->total_packets
+= total_rx_packets
;
1027 rx_ring
->total_bytes
+= total_rx_bytes
;
1028 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1029 netdev
->stats
.rx_packets
+= total_rx_packets
;
1034 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1036 * ixgbe_configure_msix - Configure MSI-X hardware
1037 * @adapter: board private structure
1039 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1042 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1044 struct ixgbe_q_vector
*q_vector
;
1045 int i
, j
, q_vectors
, v_idx
, r_idx
;
1048 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1051 * Populate the IVAR table and set the ITR values to the
1052 * corresponding register.
1054 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1055 q_vector
= adapter
->q_vector
[v_idx
];
1056 /* XXX for_each_set_bit(...) */
1057 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1058 adapter
->num_rx_queues
);
1060 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1061 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1062 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1063 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1064 adapter
->num_rx_queues
,
1067 r_idx
= find_first_bit(q_vector
->txr_idx
,
1068 adapter
->num_tx_queues
);
1070 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1071 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1072 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1073 r_idx
= find_next_bit(q_vector
->txr_idx
,
1074 adapter
->num_tx_queues
,
1078 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1080 q_vector
->eitr
= adapter
->tx_eitr_param
;
1081 else if (q_vector
->rxr_count
)
1083 q_vector
->eitr
= adapter
->rx_eitr_param
;
1085 ixgbe_write_eitr(q_vector
);
1088 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1089 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1091 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1092 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1093 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1095 /* set up to autoclear timer, and the vectors */
1096 mask
= IXGBE_EIMS_ENABLE_MASK
;
1097 if (adapter
->num_vfs
)
1098 mask
&= ~(IXGBE_EIMS_OTHER
|
1099 IXGBE_EIMS_MAILBOX
|
1102 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1103 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1106 enum latency_range
{
1110 latency_invalid
= 255
1114 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1115 * @adapter: pointer to adapter
1116 * @eitr: eitr setting (ints per sec) to give last timeslice
1117 * @itr_setting: current throttle rate in ints/second
1118 * @packets: the number of packets during this measurement interval
1119 * @bytes: the number of bytes during this measurement interval
1121 * Stores a new ITR value based on packets and byte
1122 * counts during the last interrupt. The advantage of per interrupt
1123 * computation is faster updates and more accurate ITR for the current
1124 * traffic pattern. Constants in this function were computed
1125 * based on theoretical maximum wire speed and thresholds were set based
1126 * on testing data as well as attempting to minimize response time
1127 * while increasing bulk throughput.
1128 * this functionality is controlled by the InterruptThrottleRate module
1129 * parameter (see ixgbe_param.c)
1131 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1132 u32 eitr
, u8 itr_setting
,
1133 int packets
, int bytes
)
1135 unsigned int retval
= itr_setting
;
1140 goto update_itr_done
;
1143 /* simple throttlerate management
1144 * 0-20MB/s lowest (100000 ints/s)
1145 * 20-100MB/s low (20000 ints/s)
1146 * 100-1249MB/s bulk (8000 ints/s)
1148 /* what was last interrupt timeslice? */
1149 timepassed_us
= 1000000/eitr
;
1150 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1152 switch (itr_setting
) {
1153 case lowest_latency
:
1154 if (bytes_perint
> adapter
->eitr_low
)
1155 retval
= low_latency
;
1158 if (bytes_perint
> adapter
->eitr_high
)
1159 retval
= bulk_latency
;
1160 else if (bytes_perint
<= adapter
->eitr_low
)
1161 retval
= lowest_latency
;
1164 if (bytes_perint
<= adapter
->eitr_high
)
1165 retval
= low_latency
;
1174 * ixgbe_write_eitr - write EITR register in hardware specific way
1175 * @q_vector: structure containing interrupt and ring information
1177 * This function is made to be called by ethtool and by the driver
1178 * when it needs to update EITR registers at runtime. Hardware
1179 * specific quirks/differences are taken care of here.
1181 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1183 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1184 struct ixgbe_hw
*hw
= &adapter
->hw
;
1185 int v_idx
= q_vector
->v_idx
;
1186 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1188 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1189 /* must write high and low 16 bits to reset counter */
1190 itr_reg
|= (itr_reg
<< 16);
1191 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1193 * set the WDIS bit to not clear the timer bits and cause an
1194 * immediate assertion of the interrupt
1196 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1198 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1201 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1203 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1205 u8 current_itr
, ret_itr
;
1207 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1209 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1210 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1211 tx_ring
= adapter
->tx_ring
[r_idx
];
1212 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1214 tx_ring
->total_packets
,
1215 tx_ring
->total_bytes
);
1216 /* if the result for this queue would decrease interrupt
1217 * rate for this vector then use that result */
1218 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1219 q_vector
->tx_itr
- 1 : ret_itr
);
1220 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1224 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1225 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1226 rx_ring
= adapter
->rx_ring
[r_idx
];
1227 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1229 rx_ring
->total_packets
,
1230 rx_ring
->total_bytes
);
1231 /* if the result for this queue would decrease interrupt
1232 * rate for this vector then use that result */
1233 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1234 q_vector
->rx_itr
- 1 : ret_itr
);
1235 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1239 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1241 switch (current_itr
) {
1242 /* counts and packets in update_itr are dependent on these numbers */
1243 case lowest_latency
:
1247 new_itr
= 20000; /* aka hwitr = ~200 */
1255 if (new_itr
!= q_vector
->eitr
) {
1256 /* do an exponential smoothing */
1257 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1259 /* save the algorithm value here, not the smoothed one */
1260 q_vector
->eitr
= new_itr
;
1262 ixgbe_write_eitr(q_vector
);
1268 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1270 struct ixgbe_hw
*hw
= &adapter
->hw
;
1272 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1273 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1274 DPRINTK(PROBE
, CRIT
, "Fan has stopped, replace the adapter\n");
1275 /* write to clear the interrupt */
1276 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1280 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1282 struct ixgbe_hw
*hw
= &adapter
->hw
;
1284 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1285 /* Clear the interrupt */
1286 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1287 schedule_work(&adapter
->multispeed_fiber_task
);
1288 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1289 /* Clear the interrupt */
1290 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1291 schedule_work(&adapter
->sfp_config_module_task
);
1293 /* Interrupt isn't for us... */
1298 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1300 struct ixgbe_hw
*hw
= &adapter
->hw
;
1303 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1304 adapter
->link_check_timeout
= jiffies
;
1305 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1306 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1307 IXGBE_WRITE_FLUSH(hw
);
1308 schedule_work(&adapter
->watchdog_task
);
1312 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1314 struct net_device
*netdev
= data
;
1315 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1316 struct ixgbe_hw
*hw
= &adapter
->hw
;
1320 * Workaround for Silicon errata. Use clear-by-write instead
1321 * of clear-by-read. Reading with EICS will return the
1322 * interrupt causes without clearing, which later be done
1323 * with the write to EICR.
1325 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1326 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1328 if (eicr
& IXGBE_EICR_LSC
)
1329 ixgbe_check_lsc(adapter
);
1331 if (eicr
& IXGBE_EICR_MAILBOX
)
1332 ixgbe_msg_task(adapter
);
1334 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1335 ixgbe_check_fan_failure(adapter
, eicr
);
1337 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1338 ixgbe_check_sfp_event(adapter
, eicr
);
1340 /* Handle Flow Director Full threshold interrupt */
1341 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1343 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1344 /* Disable transmits before FDIR Re-initialization */
1345 netif_tx_stop_all_queues(netdev
);
1346 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1347 struct ixgbe_ring
*tx_ring
=
1348 adapter
->tx_ring
[i
];
1349 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1350 &tx_ring
->reinit_state
))
1351 schedule_work(&adapter
->fdir_reinit_task
);
1355 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1356 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1361 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1366 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1367 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1368 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1370 mask
= (qmask
& 0xFFFFFFFF);
1371 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1372 mask
= (qmask
>> 32);
1373 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1375 /* skip the flush */
1378 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1383 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1384 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1385 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1387 mask
= (qmask
& 0xFFFFFFFF);
1388 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1389 mask
= (qmask
>> 32);
1390 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1392 /* skip the flush */
1395 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1397 struct ixgbe_q_vector
*q_vector
= data
;
1398 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1399 struct ixgbe_ring
*tx_ring
;
1402 if (!q_vector
->txr_count
)
1405 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1406 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1407 tx_ring
= adapter
->tx_ring
[r_idx
];
1408 tx_ring
->total_bytes
= 0;
1409 tx_ring
->total_packets
= 0;
1410 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1414 /* EIAM disabled interrupts (on this vector) for us */
1415 napi_schedule(&q_vector
->napi
);
1421 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1423 * @data: pointer to our q_vector struct for this interrupt vector
1425 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1427 struct ixgbe_q_vector
*q_vector
= data
;
1428 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1429 struct ixgbe_ring
*rx_ring
;
1433 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1434 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1435 rx_ring
= adapter
->rx_ring
[r_idx
];
1436 rx_ring
->total_bytes
= 0;
1437 rx_ring
->total_packets
= 0;
1438 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1442 if (!q_vector
->rxr_count
)
1445 /* disable interrupts on this vector only */
1446 /* EIAM disabled interrupts (on this vector) for us */
1447 napi_schedule(&q_vector
->napi
);
1452 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1454 struct ixgbe_q_vector
*q_vector
= data
;
1455 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1456 struct ixgbe_ring
*ring
;
1460 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1463 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1464 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1465 ring
= adapter
->tx_ring
[r_idx
];
1466 ring
->total_bytes
= 0;
1467 ring
->total_packets
= 0;
1468 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1472 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1473 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1474 ring
= adapter
->rx_ring
[r_idx
];
1475 ring
->total_bytes
= 0;
1476 ring
->total_packets
= 0;
1477 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1481 /* EIAM disabled interrupts (on this vector) for us */
1482 napi_schedule(&q_vector
->napi
);
1488 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1489 * @napi: napi struct with our devices info in it
1490 * @budget: amount of work driver is allowed to do this pass, in packets
1492 * This function is optimized for cleaning one queue only on a single
1495 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1497 struct ixgbe_q_vector
*q_vector
=
1498 container_of(napi
, struct ixgbe_q_vector
, napi
);
1499 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1500 struct ixgbe_ring
*rx_ring
= NULL
;
1504 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1505 rx_ring
= adapter
->rx_ring
[r_idx
];
1506 #ifdef CONFIG_IXGBE_DCA
1507 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1508 ixgbe_update_rx_dca(adapter
, rx_ring
);
1511 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1513 /* If all Rx work done, exit the polling mode */
1514 if (work_done
< budget
) {
1515 napi_complete(napi
);
1516 if (adapter
->rx_itr_setting
& 1)
1517 ixgbe_set_itr_msix(q_vector
);
1518 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1519 ixgbe_irq_enable_queues(adapter
,
1520 ((u64
)1 << q_vector
->v_idx
));
1527 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1528 * @napi: napi struct with our devices info in it
1529 * @budget: amount of work driver is allowed to do this pass, in packets
1531 * This function will clean more than one rx queue associated with a
1534 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1536 struct ixgbe_q_vector
*q_vector
=
1537 container_of(napi
, struct ixgbe_q_vector
, napi
);
1538 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1539 struct ixgbe_ring
*ring
= NULL
;
1540 int work_done
= 0, i
;
1542 bool tx_clean_complete
= true;
1544 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1545 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1546 ring
= adapter
->tx_ring
[r_idx
];
1547 #ifdef CONFIG_IXGBE_DCA
1548 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1549 ixgbe_update_tx_dca(adapter
, ring
);
1551 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1552 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1556 /* attempt to distribute budget to each queue fairly, but don't allow
1557 * the budget to go below 1 because we'll exit polling */
1558 budget
/= (q_vector
->rxr_count
?: 1);
1559 budget
= max(budget
, 1);
1560 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1561 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1562 ring
= adapter
->rx_ring
[r_idx
];
1563 #ifdef CONFIG_IXGBE_DCA
1564 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1565 ixgbe_update_rx_dca(adapter
, ring
);
1567 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1568 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1572 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1573 ring
= adapter
->rx_ring
[r_idx
];
1574 /* If all Rx work done, exit the polling mode */
1575 if (work_done
< budget
) {
1576 napi_complete(napi
);
1577 if (adapter
->rx_itr_setting
& 1)
1578 ixgbe_set_itr_msix(q_vector
);
1579 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1580 ixgbe_irq_enable_queues(adapter
,
1581 ((u64
)1 << q_vector
->v_idx
));
1589 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1590 * @napi: napi struct with our devices info in it
1591 * @budget: amount of work driver is allowed to do this pass, in packets
1593 * This function is optimized for cleaning one queue only on a single
1596 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1598 struct ixgbe_q_vector
*q_vector
=
1599 container_of(napi
, struct ixgbe_q_vector
, napi
);
1600 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1601 struct ixgbe_ring
*tx_ring
= NULL
;
1605 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1606 tx_ring
= adapter
->tx_ring
[r_idx
];
1607 #ifdef CONFIG_IXGBE_DCA
1608 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1609 ixgbe_update_tx_dca(adapter
, tx_ring
);
1612 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
1615 /* If all Tx work done, exit the polling mode */
1616 if (work_done
< budget
) {
1617 napi_complete(napi
);
1618 if (adapter
->tx_itr_setting
& 1)
1619 ixgbe_set_itr_msix(q_vector
);
1620 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1621 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
1627 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
1630 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1632 set_bit(r_idx
, q_vector
->rxr_idx
);
1633 q_vector
->rxr_count
++;
1636 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
1639 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
1641 set_bit(t_idx
, q_vector
->txr_idx
);
1642 q_vector
->txr_count
++;
1646 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1647 * @adapter: board private structure to initialize
1648 * @vectors: allotted vector count for descriptor rings
1650 * This function maps descriptor rings to the queue-specific vectors
1651 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1652 * one vector per ring/queue, but on a constrained vector budget, we
1653 * group the rings as "efficiently" as possible. You would add new
1654 * mapping configurations in here.
1656 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
1660 int rxr_idx
= 0, txr_idx
= 0;
1661 int rxr_remaining
= adapter
->num_rx_queues
;
1662 int txr_remaining
= adapter
->num_tx_queues
;
1667 /* No mapping required if MSI-X is disabled. */
1668 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
1672 * The ideal configuration...
1673 * We have enough vectors to map one per queue.
1675 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
1676 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
1677 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
1679 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
1680 map_vector_to_txq(adapter
, v_start
, txr_idx
);
1686 * If we don't have enough vectors for a 1-to-1
1687 * mapping, we'll have to group them so there are
1688 * multiple queues per vector.
1690 /* Re-adjusting *qpv takes care of the remainder. */
1691 for (i
= v_start
; i
< vectors
; i
++) {
1692 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
1693 for (j
= 0; j
< rqpv
; j
++) {
1694 map_vector_to_rxq(adapter
, i
, rxr_idx
);
1699 for (i
= v_start
; i
< vectors
; i
++) {
1700 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
1701 for (j
= 0; j
< tqpv
; j
++) {
1702 map_vector_to_txq(adapter
, i
, txr_idx
);
1713 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1714 * @adapter: board private structure
1716 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1717 * interrupts from the kernel.
1719 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
1721 struct net_device
*netdev
= adapter
->netdev
;
1722 irqreturn_t (*handler
)(int, void *);
1723 int i
, vector
, q_vectors
, err
;
1726 /* Decrement for Other and TCP Timer vectors */
1727 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1729 /* Map the Tx/Rx rings to the vectors we were allotted. */
1730 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
1734 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1735 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1736 &ixgbe_msix_clean_many)
1737 for (vector
= 0; vector
< q_vectors
; vector
++) {
1738 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
1740 if(handler
== &ixgbe_msix_clean_rx
) {
1741 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1742 netdev
->name
, "rx", ri
++);
1744 else if(handler
== &ixgbe_msix_clean_tx
) {
1745 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1746 netdev
->name
, "tx", ti
++);
1749 sprintf(adapter
->name
[vector
], "%s-%s-%d",
1750 netdev
->name
, "TxRx", vector
);
1752 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1753 handler
, 0, adapter
->name
[vector
],
1754 adapter
->q_vector
[vector
]);
1757 "request_irq failed for MSIX interrupt "
1758 "Error: %d\n", err
);
1759 goto free_queue_irqs
;
1763 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
1764 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
1765 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
1768 "request_irq for msix_lsc failed: %d\n", err
);
1769 goto free_queue_irqs
;
1775 for (i
= vector
- 1; i
>= 0; i
--)
1776 free_irq(adapter
->msix_entries
[--vector
].vector
,
1777 adapter
->q_vector
[i
]);
1778 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
1779 pci_disable_msix(adapter
->pdev
);
1780 kfree(adapter
->msix_entries
);
1781 adapter
->msix_entries
= NULL
;
1786 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
1788 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1790 u32 new_itr
= q_vector
->eitr
;
1791 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
1792 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
1794 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1796 tx_ring
->total_packets
,
1797 tx_ring
->total_bytes
);
1798 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
1800 rx_ring
->total_packets
,
1801 rx_ring
->total_bytes
);
1803 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1805 switch (current_itr
) {
1806 /* counts and packets in update_itr are dependent on these numbers */
1807 case lowest_latency
:
1811 new_itr
= 20000; /* aka hwitr = ~200 */
1820 if (new_itr
!= q_vector
->eitr
) {
1821 /* do an exponential smoothing */
1822 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1824 /* save the algorithm value here, not the smoothed one */
1825 q_vector
->eitr
= new_itr
;
1827 ixgbe_write_eitr(q_vector
);
1834 * ixgbe_irq_enable - Enable default interrupt generation settings
1835 * @adapter: board private structure
1837 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
1841 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
1842 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
1843 mask
|= IXGBE_EIMS_GPI_SDP1
;
1844 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1845 mask
|= IXGBE_EIMS_ECC
;
1846 mask
|= IXGBE_EIMS_GPI_SDP1
;
1847 mask
|= IXGBE_EIMS_GPI_SDP2
;
1848 if (adapter
->num_vfs
)
1849 mask
|= IXGBE_EIMS_MAILBOX
;
1851 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
1852 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
1853 mask
|= IXGBE_EIMS_FLOW_DIR
;
1855 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1856 ixgbe_irq_enable_queues(adapter
, ~0);
1857 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1859 if (adapter
->num_vfs
> 32) {
1860 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
1861 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
1866 * ixgbe_intr - legacy mode Interrupt Handler
1867 * @irq: interrupt number
1868 * @data: pointer to a network interface device structure
1870 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
1872 struct net_device
*netdev
= data
;
1873 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1874 struct ixgbe_hw
*hw
= &adapter
->hw
;
1875 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
1879 * Workaround for silicon errata. Mask the interrupts
1880 * before the read of EICR.
1882 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
1884 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1885 * therefore no explict interrupt disable is necessary */
1886 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
1888 /* shared interrupt alert!
1889 * make sure interrupts are enabled because the read will
1890 * have disabled interrupts due to EIAM */
1891 ixgbe_irq_enable(adapter
);
1892 return IRQ_NONE
; /* Not our interrupt */
1895 if (eicr
& IXGBE_EICR_LSC
)
1896 ixgbe_check_lsc(adapter
);
1898 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
1899 ixgbe_check_sfp_event(adapter
, eicr
);
1901 ixgbe_check_fan_failure(adapter
, eicr
);
1903 if (napi_schedule_prep(&(q_vector
->napi
))) {
1904 adapter
->tx_ring
[0]->total_packets
= 0;
1905 adapter
->tx_ring
[0]->total_bytes
= 0;
1906 adapter
->rx_ring
[0]->total_packets
= 0;
1907 adapter
->rx_ring
[0]->total_bytes
= 0;
1908 /* would disable interrupts here but EIAM disabled it */
1909 __napi_schedule(&(q_vector
->napi
));
1915 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
1917 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1919 for (i
= 0; i
< q_vectors
; i
++) {
1920 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
1921 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
1922 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
1923 q_vector
->rxr_count
= 0;
1924 q_vector
->txr_count
= 0;
1929 * ixgbe_request_irq - initialize interrupts
1930 * @adapter: board private structure
1932 * Attempts to configure interrupts using the best available
1933 * capabilities of the hardware and kernel.
1935 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
1937 struct net_device
*netdev
= adapter
->netdev
;
1940 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1941 err
= ixgbe_request_msix_irqs(adapter
);
1942 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
1943 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
1944 netdev
->name
, netdev
);
1946 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
1947 netdev
->name
, netdev
);
1951 DPRINTK(PROBE
, ERR
, "request_irq failed, Error %d\n", err
);
1956 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
1958 struct net_device
*netdev
= adapter
->netdev
;
1960 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1963 q_vectors
= adapter
->num_msix_vectors
;
1966 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
1969 for (; i
>= 0; i
--) {
1970 free_irq(adapter
->msix_entries
[i
].vector
,
1971 adapter
->q_vector
[i
]);
1974 ixgbe_reset_q_vectors(adapter
);
1976 free_irq(adapter
->pdev
->irq
, netdev
);
1981 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1982 * @adapter: board private structure
1984 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
1986 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1987 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
1989 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
1990 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
1991 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
1992 if (adapter
->num_vfs
> 32)
1993 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
1995 IXGBE_WRITE_FLUSH(&adapter
->hw
);
1996 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
1998 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
1999 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2001 synchronize_irq(adapter
->pdev
->irq
);
2006 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2009 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2011 struct ixgbe_hw
*hw
= &adapter
->hw
;
2013 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2014 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2016 ixgbe_set_ivar(adapter
, 0, 0, 0);
2017 ixgbe_set_ivar(adapter
, 1, 0, 0);
2019 map_vector_to_rxq(adapter
, 0, 0);
2020 map_vector_to_txq(adapter
, 0, 0);
2022 DPRINTK(HW
, INFO
, "Legacy interrupt IVAR setup done\n");
2026 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2027 * @adapter: board private structure
2029 * Configure the Tx unit of the MAC after a reset.
2031 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2034 struct ixgbe_hw
*hw
= &adapter
->hw
;
2035 u32 i
, j
, tdlen
, txctrl
;
2037 /* Setup the HW Tx Head and Tail descriptor pointers */
2038 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2039 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
2042 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2043 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2044 (tdba
& DMA_BIT_MASK(32)));
2045 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2046 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2047 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2048 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2049 adapter
->tx_ring
[i
]->head
= IXGBE_TDH(j
);
2050 adapter
->tx_ring
[i
]->tail
= IXGBE_TDT(j
);
2052 * Disable Tx Head Writeback RO bit, since this hoses
2053 * bookkeeping if things aren't delivered in order.
2055 switch (hw
->mac
.type
) {
2056 case ixgbe_mac_82598EB
:
2057 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2059 case ixgbe_mac_82599EB
:
2061 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2064 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2065 switch (hw
->mac
.type
) {
2066 case ixgbe_mac_82598EB
:
2067 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2069 case ixgbe_mac_82599EB
:
2071 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2076 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2080 /* disable the arbiter while setting MTQC */
2081 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2082 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2083 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2085 /* set transmit pool layout */
2086 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2087 switch (adapter
->flags
& mask
) {
2089 case (IXGBE_FLAG_SRIOV_ENABLED
):
2090 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2091 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2094 case (IXGBE_FLAG_DCB_ENABLED
):
2095 /* We enable 8 traffic classes, DCB only */
2096 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2097 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2101 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2105 /* re-eable the arbiter */
2106 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2107 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2111 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2113 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2114 struct ixgbe_ring
*rx_ring
)
2118 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2120 index
= rx_ring
->reg_idx
;
2121 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2123 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2124 index
= index
& mask
;
2126 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2128 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2129 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2131 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2132 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2134 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2135 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2136 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2138 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2140 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2142 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2143 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2144 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2147 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2150 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2155 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2158 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2159 #ifdef CONFIG_IXGBE_DCB
2160 | IXGBE_FLAG_DCB_ENABLED
2162 | IXGBE_FLAG_SRIOV_ENABLED
2166 case (IXGBE_FLAG_RSS_ENABLED
):
2167 mrqc
= IXGBE_MRQC_RSSEN
;
2169 case (IXGBE_FLAG_SRIOV_ENABLED
):
2170 mrqc
= IXGBE_MRQC_VMDQEN
;
2172 #ifdef CONFIG_IXGBE_DCB
2173 case (IXGBE_FLAG_DCB_ENABLED
):
2174 mrqc
= IXGBE_MRQC_RT8TCEN
;
2176 #endif /* CONFIG_IXGBE_DCB */
2185 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2186 * @adapter: address of board private structure
2187 * @index: index of ring to set
2189 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2191 struct ixgbe_ring
*rx_ring
;
2192 struct ixgbe_hw
*hw
= &adapter
->hw
;
2197 rx_ring
= adapter
->rx_ring
[index
];
2198 j
= rx_ring
->reg_idx
;
2199 rx_buf_len
= rx_ring
->rx_buf_len
;
2200 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2201 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2203 * we must limit the number of descriptors so that the
2204 * total size of max desc * buf_len is not greater
2207 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2208 #if (MAX_SKB_FRAGS > 16)
2209 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2210 #elif (MAX_SKB_FRAGS > 8)
2211 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2212 #elif (MAX_SKB_FRAGS > 4)
2213 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2215 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2218 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2219 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2220 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2221 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2223 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2225 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2229 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2230 * @adapter: board private structure
2232 * Configure the Rx unit of the MAC after a reset.
2234 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2237 struct ixgbe_hw
*hw
= &adapter
->hw
;
2238 struct ixgbe_ring
*rx_ring
;
2239 struct net_device
*netdev
= adapter
->netdev
;
2240 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2242 u32 rdlen
, rxctrl
, rxcsum
;
2243 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2244 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2245 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2247 u32 reta
= 0, mrqc
= 0;
2251 /* Decide whether to use packet split mode or not */
2252 /* Do not use packet split if we're in SR-IOV Mode */
2253 if (!adapter
->num_vfs
)
2254 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2256 /* Set the RX buffer length according to the mode */
2257 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2258 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2259 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2260 /* PSRTYPE must be initialized in 82599 */
2261 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2262 IXGBE_PSRTYPE_UDPHDR
|
2263 IXGBE_PSRTYPE_IPV4HDR
|
2264 IXGBE_PSRTYPE_IPV6HDR
|
2265 IXGBE_PSRTYPE_L2HDR
;
2267 IXGBE_PSRTYPE(adapter
->num_vfs
),
2271 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2272 (netdev
->mtu
<= ETH_DATA_LEN
))
2273 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2275 rx_buf_len
= ALIGN(max_frame
, 1024);
2278 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2279 fctrl
|= IXGBE_FCTRL_BAM
;
2280 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2281 fctrl
|= IXGBE_FCTRL_PMCF
;
2282 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2284 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2285 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2286 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2288 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2290 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2291 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2293 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2295 rdlen
= adapter
->rx_ring
[0]->count
* sizeof(union ixgbe_adv_rx_desc
);
2296 /* disable receives while setting up the descriptors */
2297 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2298 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2301 * Setup the HW Rx Head and Tail Descriptor Pointers and
2302 * the Base and Length of the Rx Descriptor Ring
2304 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2305 rx_ring
= adapter
->rx_ring
[i
];
2306 rdba
= rx_ring
->dma
;
2307 j
= rx_ring
->reg_idx
;
2308 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2309 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2310 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2311 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2312 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2313 rx_ring
->head
= IXGBE_RDH(j
);
2314 rx_ring
->tail
= IXGBE_RDT(j
);
2315 rx_ring
->rx_buf_len
= rx_buf_len
;
2317 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2318 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2320 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2323 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2324 struct ixgbe_ring_feature
*f
;
2325 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2326 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2327 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2328 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2329 rx_ring
->rx_buf_len
=
2330 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2334 #endif /* IXGBE_FCOE */
2335 ixgbe_configure_srrctl(adapter
, rx_ring
);
2338 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2340 * For VMDq support of different descriptor types or
2341 * buffer sizes through the use of multiple SRRCTL
2342 * registers, RDRXCTL.MVMEN must be set to 1
2344 * also, the manual doesn't mention it clearly but DCA hints
2345 * will only use queue 0's tags unless this bit is set. Side
2346 * effects of setting this bit are only that SRRCTL must be
2347 * fully programmed [0..15]
2349 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2350 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2351 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2354 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2356 u32 reg_offset
, vf_shift
;
2357 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2358 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2359 | IXGBE_VT_CTL_REPLEN
;
2360 vt_reg_bits
|= (adapter
->num_vfs
<<
2361 IXGBE_VT_CTL_POOL_SHIFT
);
2362 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2363 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2365 vf_shift
= adapter
->num_vfs
% 32;
2366 reg_offset
= adapter
->num_vfs
/ 32;
2367 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2368 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2369 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2370 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2371 /* Enable only the PF's pool for Tx/Rx */
2372 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2373 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2374 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2375 ixgbe_set_vmolr(hw
, adapter
->num_vfs
);
2378 /* Program MRQC for the distribution of queues */
2379 mrqc
= ixgbe_setup_mrqc(adapter
);
2381 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2382 /* Fill out redirection table */
2383 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2384 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2386 /* reta = 4-byte sliding window of
2387 * 0x00..(indices-1)(indices-1)00..etc. */
2388 reta
= (reta
<< 8) | (j
* 0x11);
2390 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2393 /* Fill out hash function seeds */
2394 for (i
= 0; i
< 10; i
++)
2395 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2397 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2398 mrqc
|= IXGBE_MRQC_RSSEN
;
2399 /* Perform hash on these packet types */
2400 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2401 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2402 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2403 | IXGBE_MRQC_RSS_FIELD_IPV6
2404 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2405 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
;
2407 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2409 if (adapter
->num_vfs
) {
2412 /* Map PF MAC address in RAR Entry 0 to first pool
2414 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2416 /* Set up VF register offsets for selected VT Mode, i.e.
2417 * 64 VFs for SR-IOV */
2418 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2419 reg
|= IXGBE_GCR_EXT_SRIOV
;
2420 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2423 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2425 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2426 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2427 /* Disable indicating checksum in descriptor, enables
2429 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2431 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2432 /* Enable IPv4 payload checksum for UDP fragments
2433 * if PCSD is not set */
2434 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2437 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2439 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2440 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2441 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2442 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2443 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2446 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2447 /* Enable 82599 HW-RSC */
2448 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2449 ixgbe_configure_rscctl(adapter
, i
);
2451 /* Disable RSC for ACK packets */
2452 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2453 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2457 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2459 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2460 struct ixgbe_hw
*hw
= &adapter
->hw
;
2461 int pool_ndx
= adapter
->num_vfs
;
2463 /* add VID to filter table */
2464 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2467 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2469 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2470 struct ixgbe_hw
*hw
= &adapter
->hw
;
2471 int pool_ndx
= adapter
->num_vfs
;
2473 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2474 ixgbe_irq_disable(adapter
);
2476 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2478 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2479 ixgbe_irq_enable(adapter
);
2481 /* remove VID from filter table */
2482 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2485 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2486 struct vlan_group
*grp
)
2488 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2492 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2493 ixgbe_irq_disable(adapter
);
2494 adapter
->vlgrp
= grp
;
2497 * For a DCB driver, always enable VLAN tag stripping so we can
2498 * still receive traffic from a DCB-enabled host even if we're
2501 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_VLNCTRL
);
2503 /* Disable CFI check */
2504 ctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2506 /* enable VLAN tag stripping */
2507 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2508 ctrl
|= IXGBE_VLNCTRL_VME
;
2509 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2510 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2512 j
= adapter
->rx_ring
[i
]->reg_idx
;
2513 ctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_RXDCTL(j
));
2514 ctrl
|= IXGBE_RXDCTL_VME
;
2515 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_RXDCTL(j
), ctrl
);
2519 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_VLNCTRL
, ctrl
);
2521 ixgbe_vlan_rx_add_vid(netdev
, 0);
2523 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2524 ixgbe_irq_enable(adapter
);
2527 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2529 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2531 if (adapter
->vlgrp
) {
2533 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2534 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2536 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2541 static u8
*ixgbe_addr_list_itr(struct ixgbe_hw
*hw
, u8
**mc_addr_ptr
, u32
*vmdq
)
2543 struct dev_mc_list
*mc_ptr
;
2544 u8
*addr
= *mc_addr_ptr
;
2547 mc_ptr
= container_of(addr
, struct dev_mc_list
, dmi_addr
[0]);
2549 *mc_addr_ptr
= mc_ptr
->next
->dmi_addr
;
2551 *mc_addr_ptr
= NULL
;
2557 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2558 * @netdev: network interface device structure
2560 * The set_rx_method entry point is called whenever the unicast/multicast
2561 * address list or the network interface flags are updated. This routine is
2562 * responsible for configuring the hardware for proper unicast, multicast and
2565 void ixgbe_set_rx_mode(struct net_device
*netdev
)
2567 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2568 struct ixgbe_hw
*hw
= &adapter
->hw
;
2570 u8
*addr_list
= NULL
;
2573 /* Check for Promiscuous and All Multicast modes */
2575 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
2576 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2578 if (netdev
->flags
& IFF_PROMISC
) {
2579 hw
->addr_ctrl
.user_set_promisc
= 1;
2580 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2581 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2583 if (netdev
->flags
& IFF_ALLMULTI
) {
2584 fctrl
|= IXGBE_FCTRL_MPE
;
2585 fctrl
&= ~IXGBE_FCTRL_UPE
;
2587 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
2589 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2590 hw
->addr_ctrl
.user_set_promisc
= 0;
2593 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
2594 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2596 /* reprogram secondary unicast list */
2597 hw
->mac
.ops
.update_uc_addr_list(hw
, netdev
);
2599 /* reprogram multicast list */
2600 addr_count
= netdev_mc_count(netdev
);
2602 addr_list
= netdev
->mc_list
->dmi_addr
;
2603 hw
->mac
.ops
.update_mc_addr_list(hw
, addr_list
, addr_count
,
2604 ixgbe_addr_list_itr
);
2605 if (adapter
->num_vfs
)
2606 ixgbe_restore_vf_multicasts(adapter
);
2609 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
2612 struct ixgbe_q_vector
*q_vector
;
2613 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2615 /* legacy and MSI only use one vector */
2616 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2619 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2620 struct napi_struct
*napi
;
2621 q_vector
= adapter
->q_vector
[q_idx
];
2622 napi
= &q_vector
->napi
;
2623 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2624 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
2625 if (q_vector
->txr_count
== 1)
2626 napi
->poll
= &ixgbe_clean_txonly
;
2627 else if (q_vector
->rxr_count
== 1)
2628 napi
->poll
= &ixgbe_clean_rxonly
;
2636 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
2639 struct ixgbe_q_vector
*q_vector
;
2640 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2642 /* legacy and MSI only use one vector */
2643 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2646 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
2647 q_vector
= adapter
->q_vector
[q_idx
];
2648 napi_disable(&q_vector
->napi
);
2652 #ifdef CONFIG_IXGBE_DCB
2654 * ixgbe_configure_dcb - Configure DCB hardware
2655 * @adapter: ixgbe adapter struct
2657 * This is called by the driver on open to configure the DCB hardware.
2658 * This is also called by the gennetlink interface when reconfiguring
2661 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
2663 struct ixgbe_hw
*hw
= &adapter
->hw
;
2664 u32 txdctl
, vlnctrl
;
2667 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
2668 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
2669 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
2671 /* reconfigure the hardware */
2672 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
2674 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2675 j
= adapter
->tx_ring
[i
]->reg_idx
;
2676 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2677 /* PThresh workaround for Tx hang with DFP enabled. */
2679 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2681 /* Enable VLAN tag insert/strip */
2682 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2683 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2684 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2685 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2686 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2687 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2688 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2689 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2690 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2691 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2692 j
= adapter
->rx_ring
[i
]->reg_idx
;
2693 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2694 vlnctrl
|= IXGBE_RXDCTL_VME
;
2695 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2698 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
2702 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
2704 struct net_device
*netdev
= adapter
->netdev
;
2705 struct ixgbe_hw
*hw
= &adapter
->hw
;
2708 ixgbe_set_rx_mode(netdev
);
2710 ixgbe_restore_vlan(adapter
);
2711 #ifdef CONFIG_IXGBE_DCB
2712 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2713 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2714 netif_set_gso_max_size(netdev
, 32768);
2716 netif_set_gso_max_size(netdev
, 65536);
2717 ixgbe_configure_dcb(adapter
);
2719 netif_set_gso_max_size(netdev
, 65536);
2722 netif_set_gso_max_size(netdev
, 65536);
2726 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
2727 ixgbe_configure_fcoe(adapter
);
2729 #endif /* IXGBE_FCOE */
2730 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
2731 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2732 adapter
->tx_ring
[i
]->atr_sample_rate
=
2733 adapter
->atr_sample_rate
;
2734 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
2735 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
2736 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
2739 ixgbe_configure_tx(adapter
);
2740 ixgbe_configure_rx(adapter
);
2741 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2742 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
2743 (adapter
->rx_ring
[i
]->count
- 1));
2746 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
2748 switch (hw
->phy
.type
) {
2749 case ixgbe_phy_sfp_avago
:
2750 case ixgbe_phy_sfp_ftl
:
2751 case ixgbe_phy_sfp_intel
:
2752 case ixgbe_phy_sfp_unknown
:
2753 case ixgbe_phy_tw_tyco
:
2754 case ixgbe_phy_tw_unknown
:
2762 * ixgbe_sfp_link_config - set up SFP+ link
2763 * @adapter: pointer to private adapter struct
2765 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
2767 struct ixgbe_hw
*hw
= &adapter
->hw
;
2769 if (hw
->phy
.multispeed_fiber
) {
2771 * In multispeed fiber setups, the device may not have
2772 * had a physical connection when the driver loaded.
2773 * If that's the case, the initial link configuration
2774 * couldn't get the MAC into 10G or 1G mode, so we'll
2775 * never have a link status change interrupt fire.
2776 * We need to try and force an autonegotiation
2777 * session, then bring up link.
2779 hw
->mac
.ops
.setup_sfp(hw
);
2780 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
2781 schedule_work(&adapter
->multispeed_fiber_task
);
2784 * Direct Attach Cu and non-multispeed fiber modules
2785 * still need to be configured properly prior to
2788 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
2789 schedule_work(&adapter
->sfp_config_module_task
);
2794 * ixgbe_non_sfp_link_config - set up non-SFP+ link
2795 * @hw: pointer to private hardware struct
2797 * Returns 0 on success, negative on failure
2799 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
2802 bool negotiation
, link_up
= false;
2803 u32 ret
= IXGBE_ERR_LINK_SETUP
;
2805 if (hw
->mac
.ops
.check_link
)
2806 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
2811 if (hw
->mac
.ops
.get_link_capabilities
)
2812 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
2816 if (hw
->mac
.ops
.setup_link
)
2817 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
2822 #define IXGBE_MAX_RX_DESC_POLL 10
2823 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
2826 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
2829 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
2830 if (IXGBE_READ_REG(&adapter
->hw
,
2831 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
2836 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
2837 DPRINTK(DRV
, ERR
, "RXDCTL.ENABLE on Rx queue %d "
2838 "not set within the polling period\n", rxr
);
2840 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
2841 (adapter
->rx_ring
[rxr
]->count
- 1));
2844 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
2846 struct net_device
*netdev
= adapter
->netdev
;
2847 struct ixgbe_hw
*hw
= &adapter
->hw
;
2849 int num_rx_rings
= adapter
->num_rx_queues
;
2851 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2852 u32 txdctl
, rxdctl
, mhadd
;
2857 ixgbe_get_hw_control(adapter
);
2859 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
2860 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
2861 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2862 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
2863 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
2868 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2869 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
2870 gpie
|= IXGBE_GPIE_VTMODE_64
;
2872 /* XXX: to interrupt immediately for EICS writes, enable this */
2873 /* gpie |= IXGBE_GPIE_EIMEN; */
2874 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2877 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2879 * use EIAM to auto-mask when MSI-X interrupt is asserted
2880 * this saves a register write for every interrupt
2882 switch (hw
->mac
.type
) {
2883 case ixgbe_mac_82598EB
:
2884 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2887 case ixgbe_mac_82599EB
:
2888 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
2889 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
2893 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2894 * specifically only auto mask tx and rx interrupts */
2895 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
2898 /* Enable fan failure interrupt if media type is copper */
2899 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
2900 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2901 gpie
|= IXGBE_SDP1_GPIEN
;
2902 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2905 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2906 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
2907 gpie
|= IXGBE_SDP1_GPIEN
;
2908 gpie
|= IXGBE_SDP2_GPIEN
;
2909 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
2913 /* adjust max frame to be able to do baby jumbo for FCoE */
2914 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
2915 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
2916 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2918 #endif /* IXGBE_FCOE */
2919 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
2920 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
2921 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
2922 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
2924 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
2927 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2928 j
= adapter
->tx_ring
[i
]->reg_idx
;
2929 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2930 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2931 txdctl
|= (8 << 16);
2932 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2935 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2936 /* DMATXCTL.EN must be set after all Tx queue config is done */
2937 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2938 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2939 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2941 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2942 j
= adapter
->tx_ring
[i
]->reg_idx
;
2943 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2944 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2945 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
2946 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2948 /* poll for Tx Enable ready */
2951 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
2952 } while (--wait_loop
&&
2953 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2955 DPRINTK(DRV
, ERR
, "Could not enable "
2956 "Tx Queue %d\n", j
);
2960 for (i
= 0; i
< num_rx_rings
; i
++) {
2961 j
= adapter
->rx_ring
[i
]->reg_idx
;
2962 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2963 /* enable PTHRESH=32 descriptors (half the internal cache)
2964 * and HTHRESH=0 descriptors (to minimize latency on fetch),
2965 * this also removes a pesky rx_no_buffer_count increment */
2967 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
2968 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
2969 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2970 ixgbe_rx_desc_queue_enable(adapter
, i
);
2972 /* enable all receives */
2973 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2974 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2975 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
2977 rxdctl
|= IXGBE_RXCTRL_RXEN
;
2978 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
2980 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
2981 ixgbe_configure_msix(adapter
);
2983 ixgbe_configure_msi_and_legacy(adapter
);
2985 /* enable the optics */
2986 if (hw
->phy
.multispeed_fiber
)
2987 hw
->mac
.ops
.enable_tx_laser(hw
);
2989 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
2990 ixgbe_napi_enable_all(adapter
);
2992 /* clear any pending interrupts, may auto mask */
2993 IXGBE_READ_REG(hw
, IXGBE_EICR
);
2995 ixgbe_irq_enable(adapter
);
2998 * If this adapter has a fan, check to see if we had a failure
2999 * before we enabled the interrupt.
3001 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3002 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3003 if (esdp
& IXGBE_ESDP_SDP1
)
3005 "Fan has stopped, replace the adapter\n");
3009 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3010 * arrived before interrupts were enabled but after probe. Such
3011 * devices wouldn't have their type identified yet. We need to
3012 * kick off the SFP+ module setup first, then try to bring up link.
3013 * If we're not hot-pluggable SFP+, we just need to configure link
3016 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3017 err
= hw
->phy
.ops
.identify(hw
);
3018 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3020 * Take the device down and schedule the sfp tasklet
3021 * which will unregister_netdev and log it.
3023 ixgbe_down(adapter
);
3024 schedule_work(&adapter
->sfp_config_module_task
);
3029 if (ixgbe_is_sfp(hw
)) {
3030 ixgbe_sfp_link_config(adapter
);
3032 err
= ixgbe_non_sfp_link_config(hw
);
3034 DPRINTK(PROBE
, ERR
, "link_config FAILED %d\n", err
);
3037 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3038 set_bit(__IXGBE_FDIR_INIT_DONE
,
3039 &(adapter
->tx_ring
[i
]->reinit_state
));
3041 /* enable transmits */
3042 netif_tx_start_all_queues(netdev
);
3044 /* bring the link up in the watchdog, this could race with our first
3045 * link up interrupt but shouldn't be a problem */
3046 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3047 adapter
->link_check_timeout
= jiffies
;
3048 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3050 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3051 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3052 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3053 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3058 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3060 WARN_ON(in_interrupt());
3061 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3063 ixgbe_down(adapter
);
3065 * If SR-IOV enabled then wait a bit before bringing the adapter
3066 * back up to give the VFs time to respond to the reset. The
3067 * two second wait is based upon the watchdog timer cycle in
3070 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3073 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3076 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3078 /* hardware has been reset, we need to reload some things */
3079 ixgbe_configure(adapter
);
3081 return ixgbe_up_complete(adapter
);
3084 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3086 struct ixgbe_hw
*hw
= &adapter
->hw
;
3089 err
= hw
->mac
.ops
.init_hw(hw
);
3092 case IXGBE_ERR_SFP_NOT_PRESENT
:
3094 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3095 dev_err(&adapter
->pdev
->dev
, "master disable timed out\n");
3097 case IXGBE_ERR_EEPROM_VERSION
:
3098 /* We are running on a pre-production device, log a warning */
3099 dev_warn(&adapter
->pdev
->dev
, "This device is a pre-production "
3100 "adapter/LOM. Please be aware there may be issues "
3101 "associated with your hardware. If you are "
3102 "experiencing problems please contact your Intel or "
3103 "hardware representative who provided you with this "
3107 dev_err(&adapter
->pdev
->dev
, "Hardware Error: %d\n", err
);
3110 /* reprogram the RAR[0] in case user changed it. */
3111 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3116 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3117 * @adapter: board private structure
3118 * @rx_ring: ring to free buffers from
3120 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3121 struct ixgbe_ring
*rx_ring
)
3123 struct pci_dev
*pdev
= adapter
->pdev
;
3127 /* Free all the Rx ring sk_buffs */
3129 for (i
= 0; i
< rx_ring
->count
; i
++) {
3130 struct ixgbe_rx_buffer
*rx_buffer_info
;
3132 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3133 if (rx_buffer_info
->dma
) {
3134 pci_unmap_single(pdev
, rx_buffer_info
->dma
,
3135 rx_ring
->rx_buf_len
,
3136 PCI_DMA_FROMDEVICE
);
3137 rx_buffer_info
->dma
= 0;
3139 if (rx_buffer_info
->skb
) {
3140 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3141 rx_buffer_info
->skb
= NULL
;
3143 struct sk_buff
*this = skb
;
3144 if (IXGBE_RSC_CB(this)->dma
) {
3145 pci_unmap_single(pdev
, IXGBE_RSC_CB(this)->dma
,
3146 rx_ring
->rx_buf_len
,
3147 PCI_DMA_FROMDEVICE
);
3148 IXGBE_RSC_CB(this)->dma
= 0;
3151 dev_kfree_skb(this);
3154 if (!rx_buffer_info
->page
)
3156 if (rx_buffer_info
->page_dma
) {
3157 pci_unmap_page(pdev
, rx_buffer_info
->page_dma
,
3158 PAGE_SIZE
/ 2, PCI_DMA_FROMDEVICE
);
3159 rx_buffer_info
->page_dma
= 0;
3161 put_page(rx_buffer_info
->page
);
3162 rx_buffer_info
->page
= NULL
;
3163 rx_buffer_info
->page_offset
= 0;
3166 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3167 memset(rx_ring
->rx_buffer_info
, 0, size
);
3169 /* Zero out the descriptor ring */
3170 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3172 rx_ring
->next_to_clean
= 0;
3173 rx_ring
->next_to_use
= 0;
3176 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3178 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3182 * ixgbe_clean_tx_ring - Free Tx Buffers
3183 * @adapter: board private structure
3184 * @tx_ring: ring to be cleaned
3186 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3187 struct ixgbe_ring
*tx_ring
)
3189 struct ixgbe_tx_buffer
*tx_buffer_info
;
3193 /* Free all the Tx ring sk_buffs */
3195 for (i
= 0; i
< tx_ring
->count
; i
++) {
3196 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3197 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3200 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3201 memset(tx_ring
->tx_buffer_info
, 0, size
);
3203 /* Zero out the descriptor ring */
3204 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3206 tx_ring
->next_to_use
= 0;
3207 tx_ring
->next_to_clean
= 0;
3210 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3212 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3216 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3217 * @adapter: board private structure
3219 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3223 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3224 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3228 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3229 * @adapter: board private structure
3231 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3235 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3236 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3239 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3241 struct net_device
*netdev
= adapter
->netdev
;
3242 struct ixgbe_hw
*hw
= &adapter
->hw
;
3247 /* signal that we are down to the interrupt handler */
3248 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3250 /* power down the optics */
3251 if (hw
->phy
.multispeed_fiber
)
3252 hw
->mac
.ops
.disable_tx_laser(hw
);
3254 /* disable receive for all VFs and wait one second */
3255 if (adapter
->num_vfs
) {
3256 /* ping all the active vfs to let them know we are going down */
3257 ixgbe_ping_all_vfs(adapter
);
3259 /* Disable all VFTE/VFRE TX/RX */
3260 ixgbe_disable_tx_rx(adapter
);
3262 /* Mark all the VFs as inactive */
3263 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3264 adapter
->vfinfo
[i
].clear_to_send
= 0;
3267 /* disable receives */
3268 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3269 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3271 netif_tx_disable(netdev
);
3273 IXGBE_WRITE_FLUSH(hw
);
3276 netif_tx_stop_all_queues(netdev
);
3278 ixgbe_irq_disable(adapter
);
3280 ixgbe_napi_disable_all(adapter
);
3282 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3283 del_timer_sync(&adapter
->sfp_timer
);
3284 del_timer_sync(&adapter
->watchdog_timer
);
3285 cancel_work_sync(&adapter
->watchdog_task
);
3287 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3288 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3289 cancel_work_sync(&adapter
->fdir_reinit_task
);
3291 /* disable transmits in the hardware now that interrupts are off */
3292 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3293 j
= adapter
->tx_ring
[i
]->reg_idx
;
3294 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3295 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3296 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3298 /* Disable the Tx DMA engine on 82599 */
3299 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3300 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3301 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3302 ~IXGBE_DMATXCTL_TE
));
3304 netif_carrier_off(netdev
);
3306 /* clear n-tuple filters that are cached */
3307 ethtool_ntuple_flush(netdev
);
3309 if (!pci_channel_offline(adapter
->pdev
))
3310 ixgbe_reset(adapter
);
3311 ixgbe_clean_all_tx_rings(adapter
);
3312 ixgbe_clean_all_rx_rings(adapter
);
3314 #ifdef CONFIG_IXGBE_DCA
3315 /* since we reset the hardware DCA settings were cleared */
3316 ixgbe_setup_dca(adapter
);
3321 * ixgbe_poll - NAPI Rx polling callback
3322 * @napi: structure for representing this polling device
3323 * @budget: how many packets driver is allowed to clean
3325 * This function is used for legacy and MSI, NAPI mode
3327 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3329 struct ixgbe_q_vector
*q_vector
=
3330 container_of(napi
, struct ixgbe_q_vector
, napi
);
3331 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3332 int tx_clean_complete
, work_done
= 0;
3334 #ifdef CONFIG_IXGBE_DCA
3335 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3336 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3337 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3341 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3342 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3344 if (!tx_clean_complete
)
3347 /* If budget not fully consumed, exit the polling mode */
3348 if (work_done
< budget
) {
3349 napi_complete(napi
);
3350 if (adapter
->rx_itr_setting
& 1)
3351 ixgbe_set_itr(adapter
);
3352 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3353 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3359 * ixgbe_tx_timeout - Respond to a Tx Hang
3360 * @netdev: network interface device structure
3362 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3364 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3366 /* Do the reset outside of interrupt context */
3367 schedule_work(&adapter
->reset_task
);
3370 static void ixgbe_reset_task(struct work_struct
*work
)
3372 struct ixgbe_adapter
*adapter
;
3373 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3375 /* If we're already down or resetting, just bail */
3376 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3377 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3380 adapter
->tx_timeout_count
++;
3382 ixgbe_reinit_locked(adapter
);
3385 #ifdef CONFIG_IXGBE_DCB
3386 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3389 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3391 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3395 adapter
->num_rx_queues
= f
->indices
;
3396 adapter
->num_tx_queues
= f
->indices
;
3404 * ixgbe_set_rss_queues: Allocate queues for RSS
3405 * @adapter: board private structure to initialize
3407 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3408 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3411 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3414 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3416 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3418 adapter
->num_rx_queues
= f
->indices
;
3419 adapter
->num_tx_queues
= f
->indices
;
3429 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3430 * @adapter: board private structure to initialize
3432 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3433 * to the original CPU that initiated the Tx session. This runs in addition
3434 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3435 * Rx load across CPUs using RSS.
3438 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3441 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3443 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3446 /* Flow Director must have RSS enabled */
3447 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3448 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3449 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3450 adapter
->num_tx_queues
= f_fdir
->indices
;
3451 adapter
->num_rx_queues
= f_fdir
->indices
;
3454 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3455 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3462 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3463 * @adapter: board private structure to initialize
3465 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3466 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3467 * rx queues out of the max number of rx queues, instead, it is used as the
3468 * index of the first rx queue used by FCoE.
3471 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3474 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3476 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3477 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3478 adapter
->num_rx_queues
= 1;
3479 adapter
->num_tx_queues
= 1;
3480 #ifdef CONFIG_IXGBE_DCB
3481 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3482 DPRINTK(PROBE
, INFO
, "FCoE enabled with DCB \n");
3483 ixgbe_set_dcb_queues(adapter
);
3486 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3487 DPRINTK(PROBE
, INFO
, "FCoE enabled with RSS \n");
3488 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3489 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3490 ixgbe_set_fdir_queues(adapter
);
3492 ixgbe_set_rss_queues(adapter
);
3494 /* adding FCoE rx rings to the end */
3495 f
->mask
= adapter
->num_rx_queues
;
3496 adapter
->num_rx_queues
+= f
->indices
;
3497 adapter
->num_tx_queues
+= f
->indices
;
3505 #endif /* IXGBE_FCOE */
3507 * ixgbe_set_sriov_queues: Allocate queues for IOV use
3508 * @adapter: board private structure to initialize
3510 * IOV doesn't actually use anything, so just NAK the
3511 * request for now and let the other queue routines
3512 * figure out what to do.
3514 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
3520 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3521 * @adapter: board private structure to initialize
3523 * This is the top level queue allocation routine. The order here is very
3524 * important, starting with the "most" number of features turned on at once,
3525 * and ending with the smallest set of features. This way large combinations
3526 * can be allocated if they're turned on, and smaller combinations are the
3527 * fallthrough conditions.
3530 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
3532 /* Start with base case */
3533 adapter
->num_rx_queues
= 1;
3534 adapter
->num_tx_queues
= 1;
3535 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
3536 adapter
->num_rx_queues_per_pool
= 1;
3538 if (ixgbe_set_sriov_queues(adapter
))
3542 if (ixgbe_set_fcoe_queues(adapter
))
3545 #endif /* IXGBE_FCOE */
3546 #ifdef CONFIG_IXGBE_DCB
3547 if (ixgbe_set_dcb_queues(adapter
))
3551 if (ixgbe_set_fdir_queues(adapter
))
3554 if (ixgbe_set_rss_queues(adapter
))
3557 /* fallback to base case */
3558 adapter
->num_rx_queues
= 1;
3559 adapter
->num_tx_queues
= 1;
3562 /* Notify the stack of the (possibly) reduced Tx Queue count. */
3563 adapter
->netdev
->real_num_tx_queues
= adapter
->num_tx_queues
;
3566 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
3569 int err
, vector_threshold
;
3571 /* We'll want at least 3 (vector_threshold):
3574 * 3) Other (Link Status Change, etc.)
3575 * 4) TCP Timer (optional)
3577 vector_threshold
= MIN_MSIX_COUNT
;
3579 /* The more we get, the more we will assign to Tx/Rx Cleanup
3580 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3581 * Right now, we simply care about how many we'll get; we'll
3582 * set them up later while requesting irq's.
3584 while (vectors
>= vector_threshold
) {
3585 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
3587 if (!err
) /* Success in acquiring all requested vectors. */
3590 vectors
= 0; /* Nasty failure, quit now */
3591 else /* err == number of vectors we should try again with */
3595 if (vectors
< vector_threshold
) {
3596 /* Can't allocate enough MSI-X interrupts? Oh well.
3597 * This just means we'll go with either a single MSI
3598 * vector or fall back to legacy interrupts.
3600 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI-X interrupts\n");
3601 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
3602 kfree(adapter
->msix_entries
);
3603 adapter
->msix_entries
= NULL
;
3605 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
3607 * Adjust for only the vectors we'll use, which is minimum
3608 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3609 * vectors we were allocated.
3611 adapter
->num_msix_vectors
= min(vectors
,
3612 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
3617 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3618 * @adapter: board private structure to initialize
3620 * Cache the descriptor ring offsets for RSS to the assigned rings.
3623 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
3628 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3629 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3630 adapter
->rx_ring
[i
]->reg_idx
= i
;
3631 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3632 adapter
->tx_ring
[i
]->reg_idx
= i
;
3641 #ifdef CONFIG_IXGBE_DCB
3643 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3644 * @adapter: board private structure to initialize
3646 * Cache the descriptor ring offsets for DCB to the assigned rings.
3649 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
3653 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
3655 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3656 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
3657 /* the number of queues is assumed to be symmetric */
3658 for (i
= 0; i
< dcb_i
; i
++) {
3659 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
3660 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
3663 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
3666 * Tx TC0 starts at: descriptor queue 0
3667 * Tx TC1 starts at: descriptor queue 32
3668 * Tx TC2 starts at: descriptor queue 64
3669 * Tx TC3 starts at: descriptor queue 80
3670 * Tx TC4 starts at: descriptor queue 96
3671 * Tx TC5 starts at: descriptor queue 104
3672 * Tx TC6 starts at: descriptor queue 112
3673 * Tx TC7 starts at: descriptor queue 120
3675 * Rx TC0-TC7 are offset by 16 queues each
3677 for (i
= 0; i
< 3; i
++) {
3678 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
3679 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3681 for ( ; i
< 5; i
++) {
3682 adapter
->tx_ring
[i
]->reg_idx
=
3684 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3686 for ( ; i
< dcb_i
; i
++) {
3687 adapter
->tx_ring
[i
]->reg_idx
=
3689 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
3693 } else if (dcb_i
== 4) {
3695 * Tx TC0 starts at: descriptor queue 0
3696 * Tx TC1 starts at: descriptor queue 64
3697 * Tx TC2 starts at: descriptor queue 96
3698 * Tx TC3 starts at: descriptor queue 112
3700 * Rx TC0-TC3 are offset by 32 queues each
3702 adapter
->tx_ring
[0]->reg_idx
= 0;
3703 adapter
->tx_ring
[1]->reg_idx
= 64;
3704 adapter
->tx_ring
[2]->reg_idx
= 96;
3705 adapter
->tx_ring
[3]->reg_idx
= 112;
3706 for (i
= 0 ; i
< dcb_i
; i
++)
3707 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
3725 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3726 * @adapter: board private structure to initialize
3728 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3731 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
3736 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3737 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3738 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
3739 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3740 adapter
->rx_ring
[i
]->reg_idx
= i
;
3741 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3742 adapter
->tx_ring
[i
]->reg_idx
= i
;
3751 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3752 * @adapter: board private structure to initialize
3754 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3757 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
3759 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
3761 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3763 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3764 #ifdef CONFIG_IXGBE_DCB
3765 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3766 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
3768 ixgbe_cache_ring_dcb(adapter
);
3769 /* find out queues in TC for FCoE */
3770 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3771 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
3773 * In 82599, the number of Tx queues for each traffic
3774 * class for both 8-TC and 4-TC modes are:
3775 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3776 * 8 TCs: 32 32 16 16 8 8 8 8
3777 * 4 TCs: 64 64 32 32
3778 * We have max 8 queues for FCoE, where 8 the is
3779 * FCoE redirection table size. If TC for FCoE is
3780 * less than or equal to TC3, we have enough queues
3781 * to add max of 8 queues for FCoE, so we start FCoE
3782 * tx descriptor from the next one, i.e., reg_idx + 1.
3783 * If TC for FCoE is above TC3, implying 8 TC mode,
3784 * and we need 8 for FCoE, we have to take all queues
3785 * in that traffic class for FCoE.
3787 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
3790 #endif /* CONFIG_IXGBE_DCB */
3791 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3792 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3793 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3794 ixgbe_cache_ring_fdir(adapter
);
3796 ixgbe_cache_ring_rss(adapter
);
3798 fcoe_rx_i
= f
->mask
;
3799 fcoe_tx_i
= f
->mask
;
3801 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
3802 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
3803 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
3810 #endif /* IXGBE_FCOE */
3812 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
3813 * @adapter: board private structure to initialize
3815 * SR-IOV doesn't use any descriptor rings but changes the default if
3816 * no other mapping is used.
3819 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
3821 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3822 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
3823 if (adapter
->num_vfs
)
3830 * ixgbe_cache_ring_register - Descriptor ring to register mapping
3831 * @adapter: board private structure to initialize
3833 * Once we know the feature-set enabled for the device, we'll cache
3834 * the register offset the descriptor ring is assigned to.
3836 * Note, the order the various feature calls is important. It must start with
3837 * the "most" features enabled at the same time, then trickle down to the
3838 * least amount of features turned on at once.
3840 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
3842 /* start with default case */
3843 adapter
->rx_ring
[0]->reg_idx
= 0;
3844 adapter
->tx_ring
[0]->reg_idx
= 0;
3846 if (ixgbe_cache_ring_sriov(adapter
))
3850 if (ixgbe_cache_ring_fcoe(adapter
))
3853 #endif /* IXGBE_FCOE */
3854 #ifdef CONFIG_IXGBE_DCB
3855 if (ixgbe_cache_ring_dcb(adapter
))
3859 if (ixgbe_cache_ring_fdir(adapter
))
3862 if (ixgbe_cache_ring_rss(adapter
))
3867 * ixgbe_alloc_queues - Allocate memory for all rings
3868 * @adapter: board private structure to initialize
3870 * We allocate one ring per queue at run-time since we don't know the
3871 * number of queues at compile-time. The polling_netdev array is
3872 * intended for Multiqueue, but should work fine with a single queue.
3874 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
3877 int orig_node
= adapter
->node
;
3879 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3880 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
3881 if (orig_node
== -1) {
3882 int cur_node
= next_online_node(adapter
->node
);
3883 if (cur_node
== MAX_NUMNODES
)
3884 cur_node
= first_online_node
;
3885 adapter
->node
= cur_node
;
3887 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3890 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3892 goto err_tx_ring_allocation
;
3893 ring
->count
= adapter
->tx_ring_count
;
3894 ring
->queue_index
= i
;
3895 ring
->numa_node
= adapter
->node
;
3897 adapter
->tx_ring
[i
] = ring
;
3900 /* Restore the adapter's original node */
3901 adapter
->node
= orig_node
;
3903 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3904 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
3905 if (orig_node
== -1) {
3906 int cur_node
= next_online_node(adapter
->node
);
3907 if (cur_node
== MAX_NUMNODES
)
3908 cur_node
= first_online_node
;
3909 adapter
->node
= cur_node
;
3911 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
3914 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
3916 goto err_rx_ring_allocation
;
3917 ring
->count
= adapter
->rx_ring_count
;
3918 ring
->queue_index
= i
;
3919 ring
->numa_node
= adapter
->node
;
3921 adapter
->rx_ring
[i
] = ring
;
3924 /* Restore the adapter's original node */
3925 adapter
->node
= orig_node
;
3927 ixgbe_cache_ring_register(adapter
);
3931 err_rx_ring_allocation
:
3932 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3933 kfree(adapter
->tx_ring
[i
]);
3934 err_tx_ring_allocation
:
3939 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3940 * @adapter: board private structure to initialize
3942 * Attempt to configure the interrupts using the best available
3943 * capabilities of the hardware and the kernel.
3945 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
3947 struct ixgbe_hw
*hw
= &adapter
->hw
;
3949 int vector
, v_budget
;
3952 * It's easy to be greedy for MSI-X vectors, but it really
3953 * doesn't do us much good if we have a lot more vectors
3954 * than CPU's. So let's be conservative and only ask for
3955 * (roughly) the same number of vectors as there are CPU's.
3957 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
3958 (int)num_online_cpus()) + NON_Q_VECTORS
;
3961 * At the same time, hardware can only support a maximum of
3962 * hw.mac->max_msix_vectors vectors. With features
3963 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3964 * descriptor queues supported by our device. Thus, we cap it off in
3965 * those rare cases where the cpu count also exceeds our vector limit.
3967 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
3969 /* A failure in MSI-X entry allocation isn't fatal, but it does
3970 * mean we disable MSI-X capabilities of the adapter. */
3971 adapter
->msix_entries
= kcalloc(v_budget
,
3972 sizeof(struct msix_entry
), GFP_KERNEL
);
3973 if (adapter
->msix_entries
) {
3974 for (vector
= 0; vector
< v_budget
; vector
++)
3975 adapter
->msix_entries
[vector
].entry
= vector
;
3977 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
3979 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3983 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
3984 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
3985 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3986 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3987 adapter
->atr_sample_rate
= 0;
3988 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3989 ixgbe_disable_sriov(adapter
);
3991 ixgbe_set_num_queues(adapter
);
3993 err
= pci_enable_msi(adapter
->pdev
);
3995 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
3997 DPRINTK(HW
, DEBUG
, "Unable to allocate MSI interrupt, "
3998 "falling back to legacy. Error: %d\n", err
);
4008 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4009 * @adapter: board private structure to initialize
4011 * We allocate one q_vector per queue interrupt. If allocation fails we
4014 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4016 int q_idx
, num_q_vectors
;
4017 struct ixgbe_q_vector
*q_vector
;
4019 int (*poll
)(struct napi_struct
*, int);
4021 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4022 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4023 napi_vectors
= adapter
->num_rx_queues
;
4024 poll
= &ixgbe_clean_rxtx_many
;
4031 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4032 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4033 GFP_KERNEL
, adapter
->node
);
4035 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4039 q_vector
->adapter
= adapter
;
4040 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4041 q_vector
->eitr
= adapter
->tx_eitr_param
;
4043 q_vector
->eitr
= adapter
->rx_eitr_param
;
4044 q_vector
->v_idx
= q_idx
;
4045 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4046 adapter
->q_vector
[q_idx
] = q_vector
;
4054 q_vector
= adapter
->q_vector
[q_idx
];
4055 netif_napi_del(&q_vector
->napi
);
4057 adapter
->q_vector
[q_idx
] = NULL
;
4063 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4064 * @adapter: board private structure to initialize
4066 * This function frees the memory allocated to the q_vectors. In addition if
4067 * NAPI is enabled it will delete any references to the NAPI struct prior
4068 * to freeing the q_vector.
4070 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4072 int q_idx
, num_q_vectors
;
4074 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4075 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4079 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4080 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4081 adapter
->q_vector
[q_idx
] = NULL
;
4082 netif_napi_del(&q_vector
->napi
);
4087 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4089 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4090 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4091 pci_disable_msix(adapter
->pdev
);
4092 kfree(adapter
->msix_entries
);
4093 adapter
->msix_entries
= NULL
;
4094 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4095 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4096 pci_disable_msi(adapter
->pdev
);
4102 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4103 * @adapter: board private structure to initialize
4105 * We determine which interrupt scheme to use based on...
4106 * - Kernel support (MSI, MSI-X)
4107 * - which can be user-defined (via MODULE_PARAM)
4108 * - Hardware queue count (num_*_queues)
4109 * - defined by miscellaneous hardware support/features (RSS, etc.)
4111 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4115 /* Number of supported queues */
4116 ixgbe_set_num_queues(adapter
);
4118 err
= ixgbe_set_interrupt_capability(adapter
);
4120 DPRINTK(PROBE
, ERR
, "Unable to setup interrupt capabilities\n");
4121 goto err_set_interrupt
;
4124 err
= ixgbe_alloc_q_vectors(adapter
);
4126 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queue "
4128 goto err_alloc_q_vectors
;
4131 err
= ixgbe_alloc_queues(adapter
);
4133 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for queues\n");
4134 goto err_alloc_queues
;
4137 DPRINTK(DRV
, INFO
, "Multiqueue %s: Rx Queue count = %u, "
4138 "Tx Queue count = %u\n",
4139 (adapter
->num_rx_queues
> 1) ? "Enabled" :
4140 "Disabled", adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4142 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4147 ixgbe_free_q_vectors(adapter
);
4148 err_alloc_q_vectors
:
4149 ixgbe_reset_interrupt_capability(adapter
);
4155 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4156 * @adapter: board private structure to clear interrupt scheme on
4158 * We go through and clear interrupt specific resources and reset the structure
4159 * to pre-load conditions
4161 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4165 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4166 kfree(adapter
->tx_ring
[i
]);
4167 adapter
->tx_ring
[i
] = NULL
;
4169 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4170 kfree(adapter
->rx_ring
[i
]);
4171 adapter
->rx_ring
[i
] = NULL
;
4174 ixgbe_free_q_vectors(adapter
);
4175 ixgbe_reset_interrupt_capability(adapter
);
4179 * ixgbe_sfp_timer - worker thread to find a missing module
4180 * @data: pointer to our adapter struct
4182 static void ixgbe_sfp_timer(unsigned long data
)
4184 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4187 * Do the sfp_timer outside of interrupt context due to the
4188 * delays that sfp+ detection requires
4190 schedule_work(&adapter
->sfp_task
);
4194 * ixgbe_sfp_task - worker thread to find a missing module
4195 * @work: pointer to work_struct containing our data
4197 static void ixgbe_sfp_task(struct work_struct
*work
)
4199 struct ixgbe_adapter
*adapter
= container_of(work
,
4200 struct ixgbe_adapter
,
4202 struct ixgbe_hw
*hw
= &adapter
->hw
;
4204 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4205 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4206 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4207 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4209 ret
= hw
->phy
.ops
.reset(hw
);
4210 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4211 dev_err(&adapter
->pdev
->dev
, "failed to initialize "
4212 "because an unsupported SFP+ module type "
4214 "Reload the driver after installing a "
4215 "supported module.\n");
4216 unregister_netdev(adapter
->netdev
);
4218 DPRINTK(PROBE
, INFO
, "detected SFP+: %d\n",
4221 /* don't need this routine any more */
4222 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4226 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4227 mod_timer(&adapter
->sfp_timer
,
4228 round_jiffies(jiffies
+ (2 * HZ
)));
4232 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4233 * @adapter: board private structure to initialize
4235 * ixgbe_sw_init initializes the Adapter private data structure.
4236 * Fields are initialized based on PCI device information and
4237 * OS network device settings (MTU size).
4239 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4241 struct ixgbe_hw
*hw
= &adapter
->hw
;
4242 struct pci_dev
*pdev
= adapter
->pdev
;
4243 struct net_device
*dev
= adapter
->netdev
;
4245 #ifdef CONFIG_IXGBE_DCB
4247 struct tc_configuration
*tc
;
4250 /* PCI config space info */
4252 hw
->vendor_id
= pdev
->vendor
;
4253 hw
->device_id
= pdev
->device
;
4254 hw
->revision_id
= pdev
->revision
;
4255 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4256 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4258 /* Set capability flags */
4259 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4260 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4261 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4262 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4263 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4264 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4265 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4266 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4267 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4268 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4269 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4270 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4271 if (dev
->features
& NETIF_F_NTUPLE
) {
4272 /* Flow Director perfect filter enabled */
4273 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4274 adapter
->atr_sample_rate
= 0;
4275 spin_lock_init(&adapter
->fdir_perfect_lock
);
4277 /* Flow Director hash filters enabled */
4278 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4279 adapter
->atr_sample_rate
= 20;
4281 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4282 IXGBE_MAX_FDIR_INDICES
;
4283 adapter
->fdir_pballoc
= 0;
4285 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4286 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4287 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4288 #ifdef CONFIG_IXGBE_DCB
4289 /* Default traffic class to use for FCoE */
4290 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4292 #endif /* IXGBE_FCOE */
4295 #ifdef CONFIG_IXGBE_DCB
4296 /* Configure DCB traffic classes */
4297 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4298 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4299 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4300 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4301 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4302 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4303 tc
->dcb_pfc
= pfc_disabled
;
4305 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4306 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4307 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4308 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4309 adapter
->dcb_cfg
.round_robin_enable
= false;
4310 adapter
->dcb_set_bitmap
= 0x00;
4311 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4312 adapter
->ring_feature
[RING_F_DCB
].indices
);
4316 /* default flow control settings */
4317 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4318 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4320 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4322 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4323 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4324 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4325 hw
->fc
.send_xon
= true;
4326 hw
->fc
.disable_fc_autoneg
= false;
4328 /* enable itr by default in dynamic mode */
4329 adapter
->rx_itr_setting
= 1;
4330 adapter
->rx_eitr_param
= 20000;
4331 adapter
->tx_itr_setting
= 1;
4332 adapter
->tx_eitr_param
= 10000;
4334 /* set defaults for eitr in MegaBytes */
4335 adapter
->eitr_low
= 10;
4336 adapter
->eitr_high
= 20;
4338 /* set default ring sizes */
4339 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4340 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4342 /* initialize eeprom parameters */
4343 if (ixgbe_init_eeprom_params_generic(hw
)) {
4344 dev_err(&pdev
->dev
, "EEPROM initialization failed\n");
4348 /* enable rx csum by default */
4349 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4351 /* get assigned NUMA node */
4352 adapter
->node
= dev_to_node(&pdev
->dev
);
4354 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4360 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4361 * @adapter: board private structure
4362 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4364 * Return 0 on success, negative on failure
4366 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4367 struct ixgbe_ring
*tx_ring
)
4369 struct pci_dev
*pdev
= adapter
->pdev
;
4372 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4373 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4374 if (!tx_ring
->tx_buffer_info
)
4375 tx_ring
->tx_buffer_info
= vmalloc(size
);
4376 if (!tx_ring
->tx_buffer_info
)
4378 memset(tx_ring
->tx_buffer_info
, 0, size
);
4380 /* round up to nearest 4K */
4381 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4382 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4384 tx_ring
->desc
= pci_alloc_consistent(pdev
, tx_ring
->size
,
4389 tx_ring
->next_to_use
= 0;
4390 tx_ring
->next_to_clean
= 0;
4391 tx_ring
->work_limit
= tx_ring
->count
;
4395 vfree(tx_ring
->tx_buffer_info
);
4396 tx_ring
->tx_buffer_info
= NULL
;
4397 DPRINTK(PROBE
, ERR
, "Unable to allocate memory for the transmit "
4398 "descriptor ring\n");
4403 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4404 * @adapter: board private structure
4406 * If this function returns with an error, then it's possible one or
4407 * more of the rings is populated (while the rest are not). It is the
4408 * callers duty to clean those orphaned rings.
4410 * Return 0 on success, negative on failure
4412 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4416 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4417 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4420 DPRINTK(PROBE
, ERR
, "Allocation for Tx Queue %u failed\n", i
);
4428 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4429 * @adapter: board private structure
4430 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4432 * Returns 0 on success, negative on failure
4434 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4435 struct ixgbe_ring
*rx_ring
)
4437 struct pci_dev
*pdev
= adapter
->pdev
;
4440 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4441 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4442 if (!rx_ring
->rx_buffer_info
)
4443 rx_ring
->rx_buffer_info
= vmalloc(size
);
4444 if (!rx_ring
->rx_buffer_info
) {
4446 "vmalloc allocation failed for the rx desc ring\n");
4449 memset(rx_ring
->rx_buffer_info
, 0, size
);
4451 /* Round up to nearest 4K */
4452 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4453 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4455 rx_ring
->desc
= pci_alloc_consistent(pdev
, rx_ring
->size
, &rx_ring
->dma
);
4457 if (!rx_ring
->desc
) {
4459 "Memory allocation failed for the rx desc ring\n");
4460 vfree(rx_ring
->rx_buffer_info
);
4464 rx_ring
->next_to_clean
= 0;
4465 rx_ring
->next_to_use
= 0;
4474 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4475 * @adapter: board private structure
4477 * If this function returns with an error, then it's possible one or
4478 * more of the rings is populated (while the rest are not). It is the
4479 * callers duty to clean those orphaned rings.
4481 * Return 0 on success, negative on failure
4484 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4488 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4489 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4492 DPRINTK(PROBE
, ERR
, "Allocation for Rx Queue %u failed\n", i
);
4500 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4501 * @adapter: board private structure
4502 * @tx_ring: Tx descriptor ring for a specific queue
4504 * Free all transmit software resources
4506 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
4507 struct ixgbe_ring
*tx_ring
)
4509 struct pci_dev
*pdev
= adapter
->pdev
;
4511 ixgbe_clean_tx_ring(adapter
, tx_ring
);
4513 vfree(tx_ring
->tx_buffer_info
);
4514 tx_ring
->tx_buffer_info
= NULL
;
4516 pci_free_consistent(pdev
, tx_ring
->size
, tx_ring
->desc
, tx_ring
->dma
);
4518 tx_ring
->desc
= NULL
;
4522 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4523 * @adapter: board private structure
4525 * Free all transmit software resources
4527 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
4531 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4532 if (adapter
->tx_ring
[i
]->desc
)
4533 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4537 * ixgbe_free_rx_resources - Free Rx Resources
4538 * @adapter: board private structure
4539 * @rx_ring: ring to clean the resources from
4541 * Free all receive software resources
4543 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
4544 struct ixgbe_ring
*rx_ring
)
4546 struct pci_dev
*pdev
= adapter
->pdev
;
4548 ixgbe_clean_rx_ring(adapter
, rx_ring
);
4550 vfree(rx_ring
->rx_buffer_info
);
4551 rx_ring
->rx_buffer_info
= NULL
;
4553 pci_free_consistent(pdev
, rx_ring
->size
, rx_ring
->desc
, rx_ring
->dma
);
4555 rx_ring
->desc
= NULL
;
4559 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4560 * @adapter: board private structure
4562 * Free all receive software resources
4564 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
4568 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4569 if (adapter
->rx_ring
[i
]->desc
)
4570 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4574 * ixgbe_change_mtu - Change the Maximum Transfer Unit
4575 * @netdev: network interface device structure
4576 * @new_mtu: new value for maximum frame size
4578 * Returns 0 on success, negative on failure
4580 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
4582 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4583 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
4585 /* MTU < 68 is an error and causes problems on some kernels */
4586 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
4589 DPRINTK(PROBE
, INFO
, "changing MTU from %d to %d\n",
4590 netdev
->mtu
, new_mtu
);
4591 /* must set new MTU before calling down or up */
4592 netdev
->mtu
= new_mtu
;
4594 if (netif_running(netdev
))
4595 ixgbe_reinit_locked(adapter
);
4601 * ixgbe_open - Called when a network interface is made active
4602 * @netdev: network interface device structure
4604 * Returns 0 on success, negative value on failure
4606 * The open entry point is called when a network interface is made
4607 * active by the system (IFF_UP). At this point all resources needed
4608 * for transmit and receive operations are allocated, the interrupt
4609 * handler is registered with the OS, the watchdog timer is started,
4610 * and the stack is notified that the interface is ready.
4612 static int ixgbe_open(struct net_device
*netdev
)
4614 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4617 /* disallow open during test */
4618 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
4621 netif_carrier_off(netdev
);
4623 /* allocate transmit descriptors */
4624 err
= ixgbe_setup_all_tx_resources(adapter
);
4628 /* allocate receive descriptors */
4629 err
= ixgbe_setup_all_rx_resources(adapter
);
4633 ixgbe_configure(adapter
);
4635 err
= ixgbe_request_irq(adapter
);
4639 err
= ixgbe_up_complete(adapter
);
4643 netif_tx_start_all_queues(netdev
);
4648 ixgbe_release_hw_control(adapter
);
4649 ixgbe_free_irq(adapter
);
4652 ixgbe_free_all_rx_resources(adapter
);
4654 ixgbe_free_all_tx_resources(adapter
);
4655 ixgbe_reset(adapter
);
4661 * ixgbe_close - Disables a network interface
4662 * @netdev: network interface device structure
4664 * Returns 0, this is not allowed to fail
4666 * The close entry point is called when an interface is de-activated
4667 * by the OS. The hardware is still under the drivers control, but
4668 * needs to be disabled. A global MAC reset is issued to stop the
4669 * hardware, and all transmit and receive resources are freed.
4671 static int ixgbe_close(struct net_device
*netdev
)
4673 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4675 ixgbe_down(adapter
);
4676 ixgbe_free_irq(adapter
);
4678 ixgbe_free_all_tx_resources(adapter
);
4679 ixgbe_free_all_rx_resources(adapter
);
4681 ixgbe_release_hw_control(adapter
);
4687 static int ixgbe_resume(struct pci_dev
*pdev
)
4689 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4690 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4693 pci_set_power_state(pdev
, PCI_D0
);
4694 pci_restore_state(pdev
);
4696 * pci_restore_state clears dev->state_saved so call
4697 * pci_save_state to restore it.
4699 pci_save_state(pdev
);
4701 err
= pci_enable_device_mem(pdev
);
4703 printk(KERN_ERR
"ixgbe: Cannot enable PCI device from "
4707 pci_set_master(pdev
);
4709 pci_wake_from_d3(pdev
, false);
4711 err
= ixgbe_init_interrupt_scheme(adapter
);
4713 printk(KERN_ERR
"ixgbe: Cannot initialize interrupts for "
4718 ixgbe_reset(adapter
);
4720 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
4722 if (netif_running(netdev
)) {
4723 err
= ixgbe_open(adapter
->netdev
);
4728 netif_device_attach(netdev
);
4732 #endif /* CONFIG_PM */
4734 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
4736 struct net_device
*netdev
= pci_get_drvdata(pdev
);
4737 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4738 struct ixgbe_hw
*hw
= &adapter
->hw
;
4740 u32 wufc
= adapter
->wol
;
4745 netif_device_detach(netdev
);
4747 if (netif_running(netdev
)) {
4748 ixgbe_down(adapter
);
4749 ixgbe_free_irq(adapter
);
4750 ixgbe_free_all_tx_resources(adapter
);
4751 ixgbe_free_all_rx_resources(adapter
);
4753 ixgbe_clear_interrupt_scheme(adapter
);
4756 retval
= pci_save_state(pdev
);
4762 ixgbe_set_rx_mode(netdev
);
4764 /* turn on all-multi mode if wake on multicast is enabled */
4765 if (wufc
& IXGBE_WUFC_MC
) {
4766 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
4767 fctrl
|= IXGBE_FCTRL_MPE
;
4768 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
4771 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
4772 ctrl
|= IXGBE_CTRL_GIO_DIS
;
4773 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
4775 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
4777 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
4778 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
4781 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
4782 pci_wake_from_d3(pdev
, true);
4784 pci_wake_from_d3(pdev
, false);
4786 *enable_wake
= !!wufc
;
4788 ixgbe_release_hw_control(adapter
);
4790 pci_disable_device(pdev
);
4796 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
4801 retval
= __ixgbe_shutdown(pdev
, &wake
);
4806 pci_prepare_to_sleep(pdev
);
4808 pci_wake_from_d3(pdev
, false);
4809 pci_set_power_state(pdev
, PCI_D3hot
);
4814 #endif /* CONFIG_PM */
4816 static void ixgbe_shutdown(struct pci_dev
*pdev
)
4820 __ixgbe_shutdown(pdev
, &wake
);
4822 if (system_state
== SYSTEM_POWER_OFF
) {
4823 pci_wake_from_d3(pdev
, wake
);
4824 pci_set_power_state(pdev
, PCI_D3hot
);
4829 * ixgbe_update_stats - Update the board statistics counters.
4830 * @adapter: board private structure
4832 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
4834 struct net_device
*netdev
= adapter
->netdev
;
4835 struct ixgbe_hw
*hw
= &adapter
->hw
;
4837 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
4838 u64 non_eop_descs
= 0, restart_queue
= 0;
4840 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
4843 for (i
= 0; i
< 16; i
++)
4844 adapter
->hw_rx_no_dma_resources
+=
4845 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4846 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4847 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
4848 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
4850 adapter
->rsc_total_count
= rsc_count
;
4851 adapter
->rsc_total_flush
= rsc_flush
;
4854 /* gather some stats to the adapter struct that are per queue */
4855 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4856 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
4857 adapter
->restart_queue
= restart_queue
;
4859 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4860 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
4861 adapter
->non_eop_descs
= non_eop_descs
;
4863 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
4864 for (i
= 0; i
< 8; i
++) {
4865 /* for packet buffers not used, the register should read 0 */
4866 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
4868 adapter
->stats
.mpc
[i
] += mpc
;
4869 total_mpc
+= adapter
->stats
.mpc
[i
];
4870 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4871 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
4872 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
4873 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
4874 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
4875 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
4876 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4877 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4878 IXGBE_PXONRXCNT(i
));
4879 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4880 IXGBE_PXOFFRXCNT(i
));
4881 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
4883 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
4885 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
4888 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
4890 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
4893 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
4894 /* work around hardware counting issue */
4895 adapter
->stats
.gprc
-= missed_rx
;
4897 /* 82598 hardware only has a 32 bit counter in the high register */
4898 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4900 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
4901 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
4902 adapter
->stats
.gorc
+= (tmp
<< 32);
4903 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
4904 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
4905 adapter
->stats
.gotc
+= (tmp
<< 32);
4906 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
4907 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
4908 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
4909 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
4910 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
4911 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
4913 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
4914 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
4915 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
4916 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
4917 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
4918 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
4919 #endif /* IXGBE_FCOE */
4921 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
4922 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
4923 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
4924 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
4925 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
4927 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
4928 adapter
->stats
.bprc
+= bprc
;
4929 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
4930 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
4931 adapter
->stats
.mprc
-= bprc
;
4932 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
4933 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
4934 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
4935 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
4936 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
4937 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
4938 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
4939 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
4940 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
4941 adapter
->stats
.lxontxc
+= lxon
;
4942 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
4943 adapter
->stats
.lxofftxc
+= lxoff
;
4944 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4945 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
4946 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
4948 * 82598 errata - tx of flow control packets is included in tx counters
4950 xon_off_tot
= lxon
+ lxoff
;
4951 adapter
->stats
.gptc
-= xon_off_tot
;
4952 adapter
->stats
.mptc
-= xon_off_tot
;
4953 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
4954 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
4955 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
4956 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
4957 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
4958 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
4959 adapter
->stats
.ptc64
-= xon_off_tot
;
4960 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
4961 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
4962 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
4963 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
4964 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
4965 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
4967 /* Fill out the OS statistics structure */
4968 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
4971 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
4972 adapter
->stats
.rlec
;
4973 netdev
->stats
.rx_dropped
= 0;
4974 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
4975 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
4976 netdev
->stats
.rx_missed_errors
= total_mpc
;
4980 * ixgbe_watchdog - Timer Call-back
4981 * @data: pointer to adapter cast into an unsigned long
4983 static void ixgbe_watchdog(unsigned long data
)
4985 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4986 struct ixgbe_hw
*hw
= &adapter
->hw
;
4991 * Do the watchdog outside of interrupt context due to the lovely
4992 * delays that some of the newer hardware requires
4995 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
4996 goto watchdog_short_circuit
;
4998 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5000 * for legacy and MSI interrupts don't set any bits
5001 * that are enabled for EIAM, because this operation
5002 * would set *both* EIMS and EICS for any bit in EIAM
5004 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5005 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5006 goto watchdog_reschedule
;
5009 /* get one bit for every active tx/rx interrupt vector */
5010 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5011 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5012 if (qv
->rxr_count
|| qv
->txr_count
)
5013 eics
|= ((u64
)1 << i
);
5016 /* Cause software interrupt to ensure rx rings are cleaned */
5017 ixgbe_irq_rearm_queues(adapter
, eics
);
5019 watchdog_reschedule
:
5020 /* Reset the timer */
5021 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5023 watchdog_short_circuit
:
5024 schedule_work(&adapter
->watchdog_task
);
5028 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5029 * @work: pointer to work_struct containing our data
5031 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5033 struct ixgbe_adapter
*adapter
= container_of(work
,
5034 struct ixgbe_adapter
,
5035 multispeed_fiber_task
);
5036 struct ixgbe_hw
*hw
= &adapter
->hw
;
5040 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5041 autoneg
= hw
->phy
.autoneg_advertised
;
5042 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5043 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5044 hw
->mac
.autotry_restart
= false;
5045 if (hw
->mac
.ops
.setup_link
)
5046 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5047 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5048 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5052 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5053 * @work: pointer to work_struct containing our data
5055 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5057 struct ixgbe_adapter
*adapter
= container_of(work
,
5058 struct ixgbe_adapter
,
5059 sfp_config_module_task
);
5060 struct ixgbe_hw
*hw
= &adapter
->hw
;
5063 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5065 /* Time for electrical oscillations to settle down */
5067 err
= hw
->phy
.ops
.identify_sfp(hw
);
5069 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5070 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
5071 "an unsupported SFP+ module type was detected.\n"
5072 "Reload the driver after installing a supported "
5074 unregister_netdev(adapter
->netdev
);
5077 hw
->mac
.ops
.setup_sfp(hw
);
5079 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5080 /* This will also work for DA Twinax connections */
5081 schedule_work(&adapter
->multispeed_fiber_task
);
5082 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5086 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5087 * @work: pointer to work_struct containing our data
5089 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5091 struct ixgbe_adapter
*adapter
= container_of(work
,
5092 struct ixgbe_adapter
,
5094 struct ixgbe_hw
*hw
= &adapter
->hw
;
5097 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5098 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5099 set_bit(__IXGBE_FDIR_INIT_DONE
,
5100 &(adapter
->tx_ring
[i
]->reinit_state
));
5102 DPRINTK(PROBE
, ERR
, "failed to finish FDIR re-initialization, "
5103 "ignored adding FDIR ATR filters \n");
5105 /* Done FDIR Re-initialization, enable transmits */
5106 netif_tx_start_all_queues(adapter
->netdev
);
5109 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5112 * ixgbe_watchdog_task - worker thread to bring link up
5113 * @work: pointer to work_struct containing our data
5115 static void ixgbe_watchdog_task(struct work_struct
*work
)
5117 struct ixgbe_adapter
*adapter
= container_of(work
,
5118 struct ixgbe_adapter
,
5120 struct net_device
*netdev
= adapter
->netdev
;
5121 struct ixgbe_hw
*hw
= &adapter
->hw
;
5125 struct ixgbe_ring
*tx_ring
;
5126 int some_tx_pending
= 0;
5128 mutex_lock(&ixgbe_watchdog_lock
);
5130 link_up
= adapter
->link_up
;
5131 link_speed
= adapter
->link_speed
;
5133 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5134 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5137 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5138 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5139 hw
->mac
.ops
.fc_enable(hw
, i
);
5141 hw
->mac
.ops
.fc_enable(hw
, 0);
5144 hw
->mac
.ops
.fc_enable(hw
, 0);
5149 time_after(jiffies
, (adapter
->link_check_timeout
+
5150 IXGBE_TRY_LINK_TIMEOUT
))) {
5151 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5152 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5154 adapter
->link_up
= link_up
;
5155 adapter
->link_speed
= link_speed
;
5159 if (!netif_carrier_ok(netdev
)) {
5160 bool flow_rx
, flow_tx
;
5162 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5163 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5164 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5165 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5166 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5168 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5169 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5170 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5171 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5174 printk(KERN_INFO
"ixgbe: %s NIC Link is Up %s, "
5175 "Flow Control: %s\n",
5177 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5179 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5180 "1 Gbps" : "unknown speed")),
5181 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5183 (flow_tx
? "TX" : "None"))));
5185 netif_carrier_on(netdev
);
5187 /* Force detection of hung controller */
5188 adapter
->detect_tx_hung
= true;
5191 adapter
->link_up
= false;
5192 adapter
->link_speed
= 0;
5193 if (netif_carrier_ok(netdev
)) {
5194 printk(KERN_INFO
"ixgbe: %s NIC Link is Down\n",
5196 netif_carrier_off(netdev
);
5200 if (!netif_carrier_ok(netdev
)) {
5201 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5202 tx_ring
= adapter
->tx_ring
[i
];
5203 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5204 some_tx_pending
= 1;
5209 if (some_tx_pending
) {
5210 /* We've lost link, so the controller stops DMA,
5211 * but we've got queued Tx work that's never going
5212 * to get done, so reset controller to flush Tx.
5213 * (Do the reset outside of interrupt context).
5215 schedule_work(&adapter
->reset_task
);
5219 ixgbe_update_stats(adapter
);
5220 mutex_unlock(&ixgbe_watchdog_lock
);
5223 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5224 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5225 u32 tx_flags
, u8
*hdr_len
)
5227 struct ixgbe_adv_tx_context_desc
*context_desc
;
5230 struct ixgbe_tx_buffer
*tx_buffer_info
;
5231 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5232 u32 mss_l4len_idx
, l4len
;
5234 if (skb_is_gso(skb
)) {
5235 if (skb_header_cloned(skb
)) {
5236 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5240 l4len
= tcp_hdrlen(skb
);
5243 if (skb
->protocol
== htons(ETH_P_IP
)) {
5244 struct iphdr
*iph
= ip_hdr(skb
);
5247 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5251 } else if (skb_is_gso_v6(skb
)) {
5252 ipv6_hdr(skb
)->payload_len
= 0;
5253 tcp_hdr(skb
)->check
=
5254 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5255 &ipv6_hdr(skb
)->daddr
,
5259 i
= tx_ring
->next_to_use
;
5261 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5262 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5264 /* VLAN MACLEN IPLEN */
5265 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5267 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5268 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5269 IXGBE_ADVTXD_MACLEN_SHIFT
);
5270 *hdr_len
+= skb_network_offset(skb
);
5272 (skb_transport_header(skb
) - skb_network_header(skb
));
5274 (skb_transport_header(skb
) - skb_network_header(skb
));
5275 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5276 context_desc
->seqnum_seed
= 0;
5278 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5279 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5280 IXGBE_ADVTXD_DTYP_CTXT
);
5282 if (skb
->protocol
== htons(ETH_P_IP
))
5283 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5284 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5285 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5289 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5290 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5291 /* use index 1 for TSO */
5292 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5293 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5295 tx_buffer_info
->time_stamp
= jiffies
;
5296 tx_buffer_info
->next_to_watch
= i
;
5299 if (i
== tx_ring
->count
)
5301 tx_ring
->next_to_use
= i
;
5308 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5309 struct ixgbe_ring
*tx_ring
,
5310 struct sk_buff
*skb
, u32 tx_flags
)
5312 struct ixgbe_adv_tx_context_desc
*context_desc
;
5314 struct ixgbe_tx_buffer
*tx_buffer_info
;
5315 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5317 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5318 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5319 i
= tx_ring
->next_to_use
;
5320 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5321 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5323 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5325 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5326 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5327 IXGBE_ADVTXD_MACLEN_SHIFT
);
5328 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5329 vlan_macip_lens
|= (skb_transport_header(skb
) -
5330 skb_network_header(skb
));
5332 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5333 context_desc
->seqnum_seed
= 0;
5335 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5336 IXGBE_ADVTXD_DTYP_CTXT
);
5338 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5341 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5342 const struct vlan_ethhdr
*vhdr
=
5343 (const struct vlan_ethhdr
*)skb
->data
;
5345 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5347 protocol
= skb
->protocol
;
5351 case cpu_to_be16(ETH_P_IP
):
5352 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5353 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5355 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5356 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5358 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5360 case cpu_to_be16(ETH_P_IPV6
):
5361 /* XXX what about other V6 headers?? */
5362 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5364 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5365 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5367 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5370 if (unlikely(net_ratelimit())) {
5371 DPRINTK(PROBE
, WARNING
,
5372 "partial checksum but proto=%x!\n",
5379 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5380 /* use index zero for tx checksum offload */
5381 context_desc
->mss_l4len_idx
= 0;
5383 tx_buffer_info
->time_stamp
= jiffies
;
5384 tx_buffer_info
->next_to_watch
= i
;
5387 if (i
== tx_ring
->count
)
5389 tx_ring
->next_to_use
= i
;
5397 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5398 struct ixgbe_ring
*tx_ring
,
5399 struct sk_buff
*skb
, u32 tx_flags
,
5402 struct pci_dev
*pdev
= adapter
->pdev
;
5403 struct ixgbe_tx_buffer
*tx_buffer_info
;
5405 unsigned int total
= skb
->len
;
5406 unsigned int offset
= 0, size
, count
= 0, i
;
5407 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5410 i
= tx_ring
->next_to_use
;
5412 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5413 /* excluding fcoe_crc_eof for FCoE */
5414 total
-= sizeof(struct fcoe_crc_eof
);
5416 len
= min(skb_headlen(skb
), total
);
5418 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5419 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5421 tx_buffer_info
->length
= size
;
5422 tx_buffer_info
->mapped_as_page
= false;
5423 tx_buffer_info
->dma
= pci_map_single(pdev
,
5425 size
, PCI_DMA_TODEVICE
);
5426 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5428 tx_buffer_info
->time_stamp
= jiffies
;
5429 tx_buffer_info
->next_to_watch
= i
;
5438 if (i
== tx_ring
->count
)
5443 for (f
= 0; f
< nr_frags
; f
++) {
5444 struct skb_frag_struct
*frag
;
5446 frag
= &skb_shinfo(skb
)->frags
[f
];
5447 len
= min((unsigned int)frag
->size
, total
);
5448 offset
= frag
->page_offset
;
5452 if (i
== tx_ring
->count
)
5455 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5456 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5458 tx_buffer_info
->length
= size
;
5459 tx_buffer_info
->dma
= pci_map_page(adapter
->pdev
,
5463 tx_buffer_info
->mapped_as_page
= true;
5464 if (pci_dma_mapping_error(pdev
, tx_buffer_info
->dma
))
5466 tx_buffer_info
->time_stamp
= jiffies
;
5467 tx_buffer_info
->next_to_watch
= i
;
5478 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5479 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5484 dev_err(&pdev
->dev
, "TX DMA map failed\n");
5486 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5487 tx_buffer_info
->dma
= 0;
5488 tx_buffer_info
->time_stamp
= 0;
5489 tx_buffer_info
->next_to_watch
= 0;
5493 /* clear timestamp and dma mappings for remaining portion of packet */
5496 i
+= tx_ring
->count
;
5498 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5499 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
5505 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
5506 struct ixgbe_ring
*tx_ring
,
5507 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
5509 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
5510 struct ixgbe_tx_buffer
*tx_buffer_info
;
5511 u32 olinfo_status
= 0, cmd_type_len
= 0;
5513 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
5515 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
5517 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
5519 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5520 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
5522 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
5523 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5525 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5526 IXGBE_ADVTXD_POPTS_SHIFT
;
5528 /* use index 1 context for tso */
5529 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5530 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
5531 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
5532 IXGBE_ADVTXD_POPTS_SHIFT
;
5534 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
5535 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
5536 IXGBE_ADVTXD_POPTS_SHIFT
;
5538 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5539 olinfo_status
|= IXGBE_ADVTXD_CC
;
5540 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5541 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
5542 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
5545 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
5547 i
= tx_ring
->next_to_use
;
5549 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5550 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
5551 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
5552 tx_desc
->read
.cmd_type_len
=
5553 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
5554 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
5556 if (i
== tx_ring
->count
)
5560 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
5563 * Force memory writes to complete before letting h/w
5564 * know there are new descriptors to fetch. (Only
5565 * applicable for weak-ordered memory model archs,
5570 tx_ring
->next_to_use
= i
;
5571 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
5574 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
5575 int queue
, u32 tx_flags
)
5577 /* Right now, we support IPv4 only */
5578 struct ixgbe_atr_input atr_input
;
5580 struct iphdr
*iph
= ip_hdr(skb
);
5581 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
5582 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
5583 u32 src_ipv4_addr
, dst_ipv4_addr
;
5586 /* check if we're UDP or TCP */
5587 if (iph
->protocol
== IPPROTO_TCP
) {
5589 src_port
= th
->source
;
5590 dst_port
= th
->dest
;
5591 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
5592 /* l4type IPv4 type is 0, no need to assign */
5594 /* Unsupported L4 header, just bail here */
5598 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
5600 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
5601 IXGBE_TX_FLAGS_VLAN_SHIFT
;
5602 src_ipv4_addr
= iph
->saddr
;
5603 dst_ipv4_addr
= iph
->daddr
;
5604 flex_bytes
= eth
->h_proto
;
5606 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
5607 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
5608 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
5609 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
5610 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
5611 /* src and dst are inverted, think how the receiver sees them */
5612 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
5613 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
5615 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5616 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
5619 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5620 struct ixgbe_ring
*tx_ring
, int size
)
5622 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
5623 /* Herbert's original patch had:
5624 * smp_mb__after_netif_stop_queue();
5625 * but since that doesn't exist yet, just open code it. */
5628 /* We need to check again in a case another CPU has just
5629 * made room available. */
5630 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
5633 /* A reprieve! - use start_queue because it doesn't call schedule */
5634 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
5635 ++tx_ring
->restart_queue
;
5639 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
5640 struct ixgbe_ring
*tx_ring
, int size
)
5642 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
5644 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
5647 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
5649 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5650 int txq
= smp_processor_id();
5652 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
5653 while (unlikely(txq
>= dev
->real_num_tx_queues
))
5654 txq
-= dev
->real_num_tx_queues
;
5659 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
5660 ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
5661 (skb
->protocol
== htons(ETH_P_FIP
)))) {
5662 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
5663 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
5667 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5668 if (skb
->priority
== TC_PRIO_CONTROL
)
5669 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
5671 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
5676 return skb_tx_hash(dev
, skb
);
5679 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
5680 struct net_device
*netdev
)
5682 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5683 struct ixgbe_ring
*tx_ring
;
5684 struct netdev_queue
*txq
;
5686 unsigned int tx_flags
= 0;
5692 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
5693 tx_flags
|= vlan_tx_tag_get(skb
);
5694 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5695 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
5696 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5698 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5699 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5700 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5701 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
5702 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
5703 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
5706 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
5709 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
5710 #ifdef CONFIG_IXGBE_DCB
5711 /* for FCoE with DCB, we force the priority to what
5712 * was specified by the switch */
5713 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
5714 (skb
->protocol
== htons(ETH_P_FIP
))) {
5715 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
5716 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5717 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
5718 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
5721 /* flag for FCoE offloads */
5722 if (skb
->protocol
== htons(ETH_P_FCOE
))
5723 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
5727 /* four things can cause us to need a context descriptor */
5728 if (skb_is_gso(skb
) ||
5729 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
5730 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
5731 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
5734 count
+= TXD_USE_COUNT(skb_headlen(skb
));
5735 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
5736 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
5738 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
5740 return NETDEV_TX_BUSY
;
5743 first
= tx_ring
->next_to_use
;
5744 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
5746 /* setup tx offload for FCoE */
5747 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5749 dev_kfree_skb_any(skb
);
5750 return NETDEV_TX_OK
;
5753 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
5754 #endif /* IXGBE_FCOE */
5756 if (skb
->protocol
== htons(ETH_P_IP
))
5757 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
5758 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
5760 dev_kfree_skb_any(skb
);
5761 return NETDEV_TX_OK
;
5765 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
5766 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
5767 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
5768 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
5771 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
5773 /* add the ATR filter if ATR is on */
5774 if (tx_ring
->atr_sample_rate
) {
5775 ++tx_ring
->atr_count
;
5776 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
5777 test_bit(__IXGBE_FDIR_INIT_DONE
,
5778 &tx_ring
->reinit_state
)) {
5779 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
5781 tx_ring
->atr_count
= 0;
5784 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
5785 txq
->tx_bytes
+= skb
->len
;
5787 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
5789 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
5792 dev_kfree_skb_any(skb
);
5793 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
5794 tx_ring
->next_to_use
= first
;
5797 return NETDEV_TX_OK
;
5801 * ixgbe_set_mac - Change the Ethernet Address of the NIC
5802 * @netdev: network interface device structure
5803 * @p: pointer to an address structure
5805 * Returns 0 on success, negative on failure
5807 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
5809 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5810 struct ixgbe_hw
*hw
= &adapter
->hw
;
5811 struct sockaddr
*addr
= p
;
5813 if (!is_valid_ether_addr(addr
->sa_data
))
5814 return -EADDRNOTAVAIL
;
5816 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
5817 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
5819 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
5826 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
5828 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5829 struct ixgbe_hw
*hw
= &adapter
->hw
;
5833 if (prtad
!= hw
->phy
.mdio
.prtad
)
5835 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
5841 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
5842 u16 addr
, u16 value
)
5844 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5845 struct ixgbe_hw
*hw
= &adapter
->hw
;
5847 if (prtad
!= hw
->phy
.mdio
.prtad
)
5849 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
5852 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
5854 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5856 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
5860 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5862 * @netdev: network interface device structure
5864 * Returns non-zero on failure
5866 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
5869 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5870 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5872 if (is_valid_ether_addr(mac
->san_addr
)) {
5874 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5881 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5883 * @netdev: network interface device structure
5885 * Returns non-zero on failure
5887 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
5890 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
5891 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
5893 if (is_valid_ether_addr(mac
->san_addr
)) {
5895 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
5901 #ifdef CONFIG_NET_POLL_CONTROLLER
5903 * Polling 'interrupt' - used by things like netconsole to send skbs
5904 * without having to re-enable interrupts. It's not called while
5905 * the interrupt routine is executing.
5907 static void ixgbe_netpoll(struct net_device
*netdev
)
5909 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5912 /* if interface is down do nothing */
5913 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5916 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
5917 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5918 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5919 for (i
= 0; i
< num_q_vectors
; i
++) {
5920 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
5921 ixgbe_msix_clean_many(0, q_vector
);
5924 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
5926 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
5930 static const struct net_device_ops ixgbe_netdev_ops
= {
5931 .ndo_open
= ixgbe_open
,
5932 .ndo_stop
= ixgbe_close
,
5933 .ndo_start_xmit
= ixgbe_xmit_frame
,
5934 .ndo_select_queue
= ixgbe_select_queue
,
5935 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
5936 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
5937 .ndo_validate_addr
= eth_validate_addr
,
5938 .ndo_set_mac_address
= ixgbe_set_mac
,
5939 .ndo_change_mtu
= ixgbe_change_mtu
,
5940 .ndo_tx_timeout
= ixgbe_tx_timeout
,
5941 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
5942 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
5943 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
5944 .ndo_do_ioctl
= ixgbe_ioctl
,
5945 #ifdef CONFIG_NET_POLL_CONTROLLER
5946 .ndo_poll_controller
= ixgbe_netpoll
,
5949 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
5950 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
5951 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
5952 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
5953 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
5954 #endif /* IXGBE_FCOE */
5957 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
5958 const struct ixgbe_info
*ii
)
5960 #ifdef CONFIG_PCI_IOV
5961 struct ixgbe_hw
*hw
= &adapter
->hw
;
5964 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
5967 /* The 82599 supports up to 64 VFs per physical function
5968 * but this implementation limits allocation to 63 so that
5969 * basic networking resources are still available to the
5972 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
5973 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
5974 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
5977 "Failed to enable PCI sriov: %d\n", err
);
5980 /* If call to enable VFs succeeded then allocate memory
5981 * for per VF control structures.
5984 kcalloc(adapter
->num_vfs
,
5985 sizeof(struct vf_data_storage
), GFP_KERNEL
);
5986 if (adapter
->vfinfo
) {
5987 /* Now that we're sure SR-IOV is enabled
5988 * and memory allocated set up the mailbox parameters
5990 ixgbe_init_mbx_params_pf(hw
);
5991 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
5992 sizeof(hw
->mbx
.ops
));
5994 /* Disable RSC when in SR-IOV mode */
5995 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
5996 IXGBE_FLAG2_RSC_ENABLED
);
6002 "Unable to allocate memory for VF "
6003 "Data Storage - SRIOV disabled\n");
6004 pci_disable_sriov(adapter
->pdev
);
6007 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6008 adapter
->num_vfs
= 0;
6009 #endif /* CONFIG_PCI_IOV */
6013 * ixgbe_probe - Device Initialization Routine
6014 * @pdev: PCI device information struct
6015 * @ent: entry in ixgbe_pci_tbl
6017 * Returns 0 on success, negative on failure
6019 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6020 * The OS initialization, configuring of the adapter private structure,
6021 * and a hardware reset occur.
6023 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6024 const struct pci_device_id
*ent
)
6026 struct net_device
*netdev
;
6027 struct ixgbe_adapter
*adapter
= NULL
;
6028 struct ixgbe_hw
*hw
;
6029 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6030 static int cards_found
;
6031 int i
, err
, pci_using_dac
;
6032 unsigned int indices
= num_possible_cpus();
6038 err
= pci_enable_device_mem(pdev
);
6042 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)) &&
6043 !pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64))) {
6046 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
6048 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
6050 dev_err(&pdev
->dev
, "No usable DMA "
6051 "configuration, aborting\n");
6058 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6059 IORESOURCE_MEM
), ixgbe_driver_name
);
6062 "pci_request_selected_regions failed 0x%x\n", err
);
6066 pci_enable_pcie_error_reporting(pdev
);
6068 pci_set_master(pdev
);
6069 pci_save_state(pdev
);
6071 if (ii
->mac
== ixgbe_mac_82598EB
)
6072 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6074 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6076 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6078 indices
+= min_t(unsigned int, num_possible_cpus(),
6079 IXGBE_MAX_FCOE_INDICES
);
6081 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6084 goto err_alloc_etherdev
;
6087 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6089 pci_set_drvdata(pdev
, netdev
);
6090 adapter
= netdev_priv(netdev
);
6092 adapter
->netdev
= netdev
;
6093 adapter
->pdev
= pdev
;
6096 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6098 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6099 pci_resource_len(pdev
, 0));
6105 for (i
= 1; i
<= 5; i
++) {
6106 if (pci_resource_len(pdev
, i
) == 0)
6110 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6111 ixgbe_set_ethtool_ops(netdev
);
6112 netdev
->watchdog_timeo
= 5 * HZ
;
6113 strcpy(netdev
->name
, pci_name(pdev
));
6115 adapter
->bd_number
= cards_found
;
6118 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6119 hw
->mac
.type
= ii
->mac
;
6122 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6123 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6124 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6125 if (!(eec
& (1 << 8)))
6126 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6129 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6130 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6131 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6132 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6133 hw
->phy
.mdio
.mmds
= 0;
6134 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6135 hw
->phy
.mdio
.dev
= netdev
;
6136 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6137 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6139 /* set up this timer and work struct before calling get_invariants
6140 * which might start the timer
6142 init_timer(&adapter
->sfp_timer
);
6143 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6144 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6146 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6148 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6149 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6151 /* a new SFP+ module arrival, called from GPI SDP2 context */
6152 INIT_WORK(&adapter
->sfp_config_module_task
,
6153 ixgbe_sfp_config_module_task
);
6155 ii
->get_invariants(hw
);
6157 /* setup the private structure */
6158 err
= ixgbe_sw_init(adapter
);
6162 /* Make it possible the adapter to be woken up via WOL */
6163 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6164 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6167 * If there is a fan on this device and it has failed log the
6170 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6171 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6172 if (esdp
& IXGBE_ESDP_SDP1
)
6173 DPRINTK(PROBE
, CRIT
,
6174 "Fan has stopped, replace the adapter\n");
6177 /* reset_hw fills in the perm_addr as well */
6178 err
= hw
->mac
.ops
.reset_hw(hw
);
6179 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6180 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6182 * Start a kernel thread to watch for a module to arrive.
6183 * Only do this for 82598, since 82599 will generate
6184 * interrupts on module arrival.
6186 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6187 mod_timer(&adapter
->sfp_timer
,
6188 round_jiffies(jiffies
+ (2 * HZ
)));
6190 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6191 dev_err(&adapter
->pdev
->dev
, "failed to initialize because "
6192 "an unsupported SFP+ module type was detected.\n"
6193 "Reload the driver after installing a supported "
6197 dev_err(&adapter
->pdev
->dev
, "HW Init failed: %d\n", err
);
6201 ixgbe_probe_vf(adapter
, ii
);
6203 netdev
->features
= NETIF_F_SG
|
6205 NETIF_F_HW_VLAN_TX
|
6206 NETIF_F_HW_VLAN_RX
|
6207 NETIF_F_HW_VLAN_FILTER
;
6209 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6210 netdev
->features
|= NETIF_F_TSO
;
6211 netdev
->features
|= NETIF_F_TSO6
;
6212 netdev
->features
|= NETIF_F_GRO
;
6214 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6215 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6217 netdev
->vlan_features
|= NETIF_F_TSO
;
6218 netdev
->vlan_features
|= NETIF_F_TSO6
;
6219 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6220 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6221 netdev
->vlan_features
|= NETIF_F_SG
;
6223 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6224 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6225 IXGBE_FLAG_DCB_ENABLED
);
6226 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6227 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6229 #ifdef CONFIG_IXGBE_DCB
6230 netdev
->dcbnl_ops
= &dcbnl_ops
;
6234 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6235 if (hw
->mac
.ops
.get_device_caps
) {
6236 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6237 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6238 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6241 #endif /* IXGBE_FCOE */
6243 netdev
->features
|= NETIF_F_HIGHDMA
;
6245 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6246 netdev
->features
|= NETIF_F_LRO
;
6248 /* make sure the EEPROM is good */
6249 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6250 dev_err(&pdev
->dev
, "The EEPROM Checksum Is Not Valid\n");
6255 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6256 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6258 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6259 dev_err(&pdev
->dev
, "invalid MAC address\n");
6264 /* power down the optics */
6265 if (hw
->phy
.multispeed_fiber
)
6266 hw
->mac
.ops
.disable_tx_laser(hw
);
6268 init_timer(&adapter
->watchdog_timer
);
6269 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6270 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6272 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6273 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6275 err
= ixgbe_init_interrupt_scheme(adapter
);
6279 switch (pdev
->device
) {
6280 case IXGBE_DEV_ID_82599_KX4
:
6281 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6282 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6288 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6290 /* pick up the PCI bus settings for reporting later */
6291 hw
->mac
.ops
.get_bus_info(hw
);
6293 /* print bus type/speed/width info */
6294 dev_info(&pdev
->dev
, "(PCI Express:%s:%s) %pM\n",
6295 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6296 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6297 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6298 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6299 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6302 ixgbe_read_pba_num_generic(hw
, &part_num
);
6303 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6304 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
6305 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6306 (part_num
>> 8), (part_num
& 0xff));
6308 dev_info(&pdev
->dev
, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6309 hw
->mac
.type
, hw
->phy
.type
,
6310 (part_num
>> 8), (part_num
& 0xff));
6312 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6313 dev_warn(&pdev
->dev
, "PCI-Express bandwidth available for "
6314 "this card is not sufficient for optimal "
6316 dev_warn(&pdev
->dev
, "For optimal performance a x8 "
6317 "PCI-Express slot is required.\n");
6320 /* save off EEPROM version number */
6321 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6323 /* reset the hardware with the new settings */
6324 err
= hw
->mac
.ops
.start_hw(hw
);
6326 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6327 /* We are running on a pre-production device, log a warning */
6328 dev_warn(&pdev
->dev
, "This device is a pre-production "
6329 "adapter/LOM. Please be aware there may be issues "
6330 "associated with your hardware. If you are "
6331 "experiencing problems please contact your Intel or "
6332 "hardware representative who provided you with this "
6335 strcpy(netdev
->name
, "eth%d");
6336 err
= register_netdev(netdev
);
6340 /* carrier off reporting is important to ethtool even BEFORE open */
6341 netif_carrier_off(netdev
);
6343 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6344 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6345 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6347 #ifdef CONFIG_IXGBE_DCA
6348 if (dca_add_requester(&pdev
->dev
) == 0) {
6349 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6350 ixgbe_setup_dca(adapter
);
6353 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6354 DPRINTK(PROBE
, INFO
, "IOV is enabled with %d VFs\n",
6356 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6357 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6360 /* add san mac addr to netdev */
6361 ixgbe_add_sanmac_netdev(netdev
);
6363 dev_info(&pdev
->dev
, "Intel(R) 10 Gigabit Network Connection\n");
6368 ixgbe_release_hw_control(adapter
);
6369 ixgbe_clear_interrupt_scheme(adapter
);
6372 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6373 ixgbe_disable_sriov(adapter
);
6374 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6375 del_timer_sync(&adapter
->sfp_timer
);
6376 cancel_work_sync(&adapter
->sfp_task
);
6377 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6378 cancel_work_sync(&adapter
->sfp_config_module_task
);
6379 iounmap(hw
->hw_addr
);
6381 free_netdev(netdev
);
6383 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6387 pci_disable_device(pdev
);
6392 * ixgbe_remove - Device Removal Routine
6393 * @pdev: PCI device information struct
6395 * ixgbe_remove is called by the PCI subsystem to alert the driver
6396 * that it should release a PCI device. The could be caused by a
6397 * Hot-Plug event, or because the driver is going to be removed from
6400 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6402 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6403 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6405 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6406 /* clear the module not found bit to make sure the worker won't
6409 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6410 del_timer_sync(&adapter
->watchdog_timer
);
6412 del_timer_sync(&adapter
->sfp_timer
);
6413 cancel_work_sync(&adapter
->watchdog_task
);
6414 cancel_work_sync(&adapter
->sfp_task
);
6415 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6416 cancel_work_sync(&adapter
->sfp_config_module_task
);
6417 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6418 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6419 cancel_work_sync(&adapter
->fdir_reinit_task
);
6420 flush_scheduled_work();
6422 #ifdef CONFIG_IXGBE_DCA
6423 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6424 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6425 dca_remove_requester(&pdev
->dev
);
6426 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6431 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6432 ixgbe_cleanup_fcoe(adapter
);
6434 #endif /* IXGBE_FCOE */
6436 /* remove the added san mac */
6437 ixgbe_del_sanmac_netdev(netdev
);
6439 if (netdev
->reg_state
== NETREG_REGISTERED
)
6440 unregister_netdev(netdev
);
6442 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6443 ixgbe_disable_sriov(adapter
);
6445 ixgbe_clear_interrupt_scheme(adapter
);
6447 ixgbe_release_hw_control(adapter
);
6449 iounmap(adapter
->hw
.hw_addr
);
6450 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6453 DPRINTK(PROBE
, INFO
, "complete\n");
6455 free_netdev(netdev
);
6457 pci_disable_pcie_error_reporting(pdev
);
6459 pci_disable_device(pdev
);
6463 * ixgbe_io_error_detected - called when PCI error is detected
6464 * @pdev: Pointer to PCI device
6465 * @state: The current pci connection state
6467 * This function is called after a PCI bus error affecting
6468 * this device has been detected.
6470 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6471 pci_channel_state_t state
)
6473 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6474 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6476 netif_device_detach(netdev
);
6478 if (state
== pci_channel_io_perm_failure
)
6479 return PCI_ERS_RESULT_DISCONNECT
;
6481 if (netif_running(netdev
))
6482 ixgbe_down(adapter
);
6483 pci_disable_device(pdev
);
6485 /* Request a slot reset. */
6486 return PCI_ERS_RESULT_NEED_RESET
;
6490 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6491 * @pdev: Pointer to PCI device
6493 * Restart the card from scratch, as if from a cold-boot.
6495 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
6497 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6498 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6499 pci_ers_result_t result
;
6502 if (pci_enable_device_mem(pdev
)) {
6504 "Cannot re-enable PCI device after reset.\n");
6505 result
= PCI_ERS_RESULT_DISCONNECT
;
6507 pci_set_master(pdev
);
6508 pci_restore_state(pdev
);
6509 pci_save_state(pdev
);
6511 pci_wake_from_d3(pdev
, false);
6513 ixgbe_reset(adapter
);
6514 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6515 result
= PCI_ERS_RESULT_RECOVERED
;
6518 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
6521 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err
);
6522 /* non-fatal, continue */
6529 * ixgbe_io_resume - called when traffic can start flowing again.
6530 * @pdev: Pointer to PCI device
6532 * This callback is called when the error recovery driver tells us that
6533 * its OK to resume normal operation.
6535 static void ixgbe_io_resume(struct pci_dev
*pdev
)
6537 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6538 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6540 if (netif_running(netdev
)) {
6541 if (ixgbe_up(adapter
)) {
6542 DPRINTK(PROBE
, INFO
, "ixgbe_up failed after reset\n");
6547 netif_device_attach(netdev
);
6550 static struct pci_error_handlers ixgbe_err_handler
= {
6551 .error_detected
= ixgbe_io_error_detected
,
6552 .slot_reset
= ixgbe_io_slot_reset
,
6553 .resume
= ixgbe_io_resume
,
6556 static struct pci_driver ixgbe_driver
= {
6557 .name
= ixgbe_driver_name
,
6558 .id_table
= ixgbe_pci_tbl
,
6559 .probe
= ixgbe_probe
,
6560 .remove
= __devexit_p(ixgbe_remove
),
6562 .suspend
= ixgbe_suspend
,
6563 .resume
= ixgbe_resume
,
6565 .shutdown
= ixgbe_shutdown
,
6566 .err_handler
= &ixgbe_err_handler
6570 * ixgbe_init_module - Driver Registration Routine
6572 * ixgbe_init_module is the first routine called when the driver is
6573 * loaded. All it does is register with the PCI subsystem.
6575 static int __init
ixgbe_init_module(void)
6578 printk(KERN_INFO
"%s: %s - version %s\n", ixgbe_driver_name
,
6579 ixgbe_driver_string
, ixgbe_driver_version
);
6581 printk(KERN_INFO
"%s: %s\n", ixgbe_driver_name
, ixgbe_copyright
);
6583 #ifdef CONFIG_IXGBE_DCA
6584 dca_register_notify(&dca_notifier
);
6587 ret
= pci_register_driver(&ixgbe_driver
);
6591 module_init(ixgbe_init_module
);
6594 * ixgbe_exit_module - Driver Exit Cleanup Routine
6596 * ixgbe_exit_module is called just before the driver is removed
6599 static void __exit
ixgbe_exit_module(void)
6601 #ifdef CONFIG_IXGBE_DCA
6602 dca_unregister_notify(&dca_notifier
);
6604 pci_unregister_driver(&ixgbe_driver
);
6607 #ifdef CONFIG_IXGBE_DCA
6608 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
6613 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
6614 __ixgbe_notify_dca
);
6616 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
6619 #endif /* CONFIG_IXGBE_DCA */
6622 * ixgbe_get_hw_dev_name - return device name string
6623 * used by hardware layer to print debugging information
6625 char *ixgbe_get_hw_dev_name(struct ixgbe_hw
*hw
)
6627 struct ixgbe_adapter
*adapter
= hw
->back
;
6628 return adapter
->netdev
->name
;
6632 module_exit(ixgbe_exit_module
);