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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
45
46 #include "ixgbe.h"
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
50
51 char ixgbe_driver_name[] = "ixgbe";
52 static const char ixgbe_driver_string[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
54
55 #define DRV_VERSION "2.0.84-k2"
56 const char ixgbe_driver_version[] = DRV_VERSION;
57 static char ixgbe_copyright[] = "Copyright (c) 1999-2010 Intel Corporation.";
58
59 static const struct ixgbe_info *ixgbe_info_tbl[] = {
60 [board_82598] = &ixgbe_82598_info,
61 [board_82599] = &ixgbe_82599_info,
62 };
63
64 /* ixgbe_pci_tbl - PCI Device ID Table
65 *
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
68 *
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
71 */
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
76 board_82598 },
77 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
78 board_82598 },
79 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
80 board_82598 },
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
98 board_82599 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
100 board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
102 board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
104 board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
114 board_82599 },
115
116 /* required last entry */
117 {0, }
118 };
119 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
120
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
123 void *p);
124 static struct notifier_block dca_notifier = {
125 .notifier_call = ixgbe_notify_dca,
126 .next = NULL,
127 .priority = 0
128 };
129 #endif
130
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs;
133 module_param(max_vfs, uint, 0);
134 MODULE_PARM_DESC(max_vfs,
135 "Maximum number of virtual functions to allocate per physical function");
136 #endif /* CONFIG_PCI_IOV */
137
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION);
142
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
144
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
146 {
147 struct ixgbe_hw *hw = &adapter->hw;
148 u32 gcr;
149 u32 gpie;
150 u32 vmdctl;
151
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter->pdev);
155 #endif
156
157 /* turn off device IOV mode */
158 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
159 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
160 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
161 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
162 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
163 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
164
165 /* set default pool back to 0 */
166 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
167 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
168 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
169
170 /* take a breather then clean up driver data */
171 msleep(100);
172
173 kfree(adapter->vfinfo);
174 adapter->vfinfo = NULL;
175
176 adapter->num_vfs = 0;
177 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
178 }
179
180 struct ixgbe_reg_info {
181 u32 ofs;
182 char *name;
183 };
184
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
186
187 /* General Registers */
188 {IXGBE_CTRL, "CTRL"},
189 {IXGBE_STATUS, "STATUS"},
190 {IXGBE_CTRL_EXT, "CTRL_EXT"},
191
192 /* Interrupt Registers */
193 {IXGBE_EICR, "EICR"},
194
195 /* RX Registers */
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
204
205 /* TX Registers */
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
212
213 /* List Terminator */
214 {}
215 };
216
217
218 /*
219 * ixgbe_regdump - register printout routine
220 */
221 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
222 {
223 int i = 0, j = 0;
224 char rname[16];
225 u32 regs[64];
226
227 switch (reginfo->ofs) {
228 case IXGBE_SRRCTL(0):
229 for (i = 0; i < 64; i++)
230 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
231 break;
232 case IXGBE_DCA_RXCTRL(0):
233 for (i = 0; i < 64; i++)
234 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
235 break;
236 case IXGBE_RDLEN(0):
237 for (i = 0; i < 64; i++)
238 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
239 break;
240 case IXGBE_RDH(0):
241 for (i = 0; i < 64; i++)
242 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
243 break;
244 case IXGBE_RDT(0):
245 for (i = 0; i < 64; i++)
246 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
247 break;
248 case IXGBE_RXDCTL(0):
249 for (i = 0; i < 64; i++)
250 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
251 break;
252 case IXGBE_RDBAL(0):
253 for (i = 0; i < 64; i++)
254 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
255 break;
256 case IXGBE_RDBAH(0):
257 for (i = 0; i < 64; i++)
258 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
259 break;
260 case IXGBE_TDBAL(0):
261 for (i = 0; i < 64; i++)
262 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
263 break;
264 case IXGBE_TDBAH(0):
265 for (i = 0; i < 64; i++)
266 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
267 break;
268 case IXGBE_TDLEN(0):
269 for (i = 0; i < 64; i++)
270 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
271 break;
272 case IXGBE_TDH(0):
273 for (i = 0; i < 64; i++)
274 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
275 break;
276 case IXGBE_TDT(0):
277 for (i = 0; i < 64; i++)
278 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
279 break;
280 case IXGBE_TXDCTL(0):
281 for (i = 0; i < 64; i++)
282 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
283 break;
284 default:
285 pr_info("%-15s %08x\n", reginfo->name,
286 IXGBE_READ_REG(hw, reginfo->ofs));
287 return;
288 }
289
290 for (i = 0; i < 8; i++) {
291 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
292 pr_err("%-15s", rname);
293 for (j = 0; j < 8; j++)
294 pr_cont(" %08x", regs[i*8+j]);
295 pr_cont("\n");
296 }
297
298 }
299
300 /*
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
302 */
303 static void ixgbe_dump(struct ixgbe_adapter *adapter)
304 {
305 struct net_device *netdev = adapter->netdev;
306 struct ixgbe_hw *hw = &adapter->hw;
307 struct ixgbe_reg_info *reginfo;
308 int n = 0;
309 struct ixgbe_ring *tx_ring;
310 struct ixgbe_tx_buffer *tx_buffer_info;
311 union ixgbe_adv_tx_desc *tx_desc;
312 struct my_u0 { u64 a; u64 b; } *u0;
313 struct ixgbe_ring *rx_ring;
314 union ixgbe_adv_rx_desc *rx_desc;
315 struct ixgbe_rx_buffer *rx_buffer_info;
316 u32 staterr;
317 int i = 0;
318
319 if (!netif_msg_hw(adapter))
320 return;
321
322 /* Print netdevice Info */
323 if (netdev) {
324 dev_info(&adapter->pdev->dev, "Net device Info\n");
325 pr_info("Device Name state "
326 "trans_start last_rx\n");
327 pr_info("%-15s %016lX %016lX %016lX\n",
328 netdev->name,
329 netdev->state,
330 netdev->trans_start,
331 netdev->last_rx);
332 }
333
334 /* Print Registers */
335 dev_info(&adapter->pdev->dev, "Register Dump\n");
336 pr_info(" Register Name Value\n");
337 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
338 reginfo->name; reginfo++) {
339 ixgbe_regdump(hw, reginfo);
340 }
341
342 /* Print TX Ring Summary */
343 if (!netdev || !netif_running(netdev))
344 goto exit;
345
346 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
347 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
348 for (n = 0; n < adapter->num_tx_queues; n++) {
349 tx_ring = adapter->tx_ring[n];
350 tx_buffer_info =
351 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
352 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
353 n, tx_ring->next_to_use, tx_ring->next_to_clean,
354 (u64)tx_buffer_info->dma,
355 tx_buffer_info->length,
356 tx_buffer_info->next_to_watch,
357 (u64)tx_buffer_info->time_stamp);
358 }
359
360 /* Print TX Rings */
361 if (!netif_msg_tx_done(adapter))
362 goto rx_ring_summary;
363
364 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
365
366 /* Transmit Descriptor Formats
367 *
368 * Advanced Transmit Descriptor
369 * +--------------------------------------------------------------+
370 * 0 | Buffer Address [63:0] |
371 * +--------------------------------------------------------------+
372 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
373 * +--------------------------------------------------------------+
374 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
375 */
376
377 for (n = 0; n < adapter->num_tx_queues; n++) {
378 tx_ring = adapter->tx_ring[n];
379 pr_info("------------------------------------\n");
380 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
381 pr_info("------------------------------------\n");
382 pr_info("T [desc] [address 63:0 ] "
383 "[PlPOIdStDDt Ln] [bi->dma ] "
384 "leng ntw timestamp bi->skb\n");
385
386 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
387 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
388 tx_buffer_info = &tx_ring->tx_buffer_info[i];
389 u0 = (struct my_u0 *)tx_desc;
390 pr_info("T [0x%03X] %016llX %016llX %016llX"
391 " %04X %3X %016llX %p", i,
392 le64_to_cpu(u0->a),
393 le64_to_cpu(u0->b),
394 (u64)tx_buffer_info->dma,
395 tx_buffer_info->length,
396 tx_buffer_info->next_to_watch,
397 (u64)tx_buffer_info->time_stamp,
398 tx_buffer_info->skb);
399 if (i == tx_ring->next_to_use &&
400 i == tx_ring->next_to_clean)
401 pr_cont(" NTC/U\n");
402 else if (i == tx_ring->next_to_use)
403 pr_cont(" NTU\n");
404 else if (i == tx_ring->next_to_clean)
405 pr_cont(" NTC\n");
406 else
407 pr_cont("\n");
408
409 if (netif_msg_pktdata(adapter) &&
410 tx_buffer_info->dma != 0)
411 print_hex_dump(KERN_INFO, "",
412 DUMP_PREFIX_ADDRESS, 16, 1,
413 phys_to_virt(tx_buffer_info->dma),
414 tx_buffer_info->length, true);
415 }
416 }
417
418 /* Print RX Rings Summary */
419 rx_ring_summary:
420 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
421 pr_info("Queue [NTU] [NTC]\n");
422 for (n = 0; n < adapter->num_rx_queues; n++) {
423 rx_ring = adapter->rx_ring[n];
424 pr_info("%5d %5X %5X\n",
425 n, rx_ring->next_to_use, rx_ring->next_to_clean);
426 }
427
428 /* Print RX Rings */
429 if (!netif_msg_rx_status(adapter))
430 goto exit;
431
432 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
433
434 /* Advanced Receive Descriptor (Read) Format
435 * 63 1 0
436 * +-----------------------------------------------------+
437 * 0 | Packet Buffer Address [63:1] |A0/NSE|
438 * +----------------------------------------------+------+
439 * 8 | Header Buffer Address [63:1] | DD |
440 * +-----------------------------------------------------+
441 *
442 *
443 * Advanced Receive Descriptor (Write-Back) Format
444 *
445 * 63 48 47 32 31 30 21 20 16 15 4 3 0
446 * +------------------------------------------------------+
447 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
448 * | Checksum Ident | | | | Type | Type |
449 * +------------------------------------------------------+
450 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
451 * +------------------------------------------------------+
452 * 63 48 47 32 31 20 19 0
453 */
454 for (n = 0; n < adapter->num_rx_queues; n++) {
455 rx_ring = adapter->rx_ring[n];
456 pr_info("------------------------------------\n");
457 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
458 pr_info("------------------------------------\n");
459 pr_info("R [desc] [ PktBuf A0] "
460 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
461 "<-- Adv Rx Read format\n");
462 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
463 "[vl er S cks ln] ---------------- [bi->skb] "
464 "<-- Adv Rx Write-Back format\n");
465
466 for (i = 0; i < rx_ring->count; i++) {
467 rx_buffer_info = &rx_ring->rx_buffer_info[i];
468 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
469 u0 = (struct my_u0 *)rx_desc;
470 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
471 if (staterr & IXGBE_RXD_STAT_DD) {
472 /* Descriptor Done */
473 pr_info("RWB[0x%03X] %016llX "
474 "%016llX ---------------- %p", i,
475 le64_to_cpu(u0->a),
476 le64_to_cpu(u0->b),
477 rx_buffer_info->skb);
478 } else {
479 pr_info("R [0x%03X] %016llX "
480 "%016llX %016llX %p", i,
481 le64_to_cpu(u0->a),
482 le64_to_cpu(u0->b),
483 (u64)rx_buffer_info->dma,
484 rx_buffer_info->skb);
485
486 if (netif_msg_pktdata(adapter)) {
487 print_hex_dump(KERN_INFO, "",
488 DUMP_PREFIX_ADDRESS, 16, 1,
489 phys_to_virt(rx_buffer_info->dma),
490 rx_ring->rx_buf_len, true);
491
492 if (rx_ring->rx_buf_len
493 < IXGBE_RXBUFFER_2048)
494 print_hex_dump(KERN_INFO, "",
495 DUMP_PREFIX_ADDRESS, 16, 1,
496 phys_to_virt(
497 rx_buffer_info->page_dma +
498 rx_buffer_info->page_offset
499 ),
500 PAGE_SIZE/2, true);
501 }
502 }
503
504 if (i == rx_ring->next_to_use)
505 pr_cont(" NTU\n");
506 else if (i == rx_ring->next_to_clean)
507 pr_cont(" NTC\n");
508 else
509 pr_cont("\n");
510
511 }
512 }
513
514 exit:
515 return;
516 }
517
518 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
519 {
520 u32 ctrl_ext;
521
522 /* Let firmware take over control of h/w */
523 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
524 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
525 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
526 }
527
528 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
529 {
530 u32 ctrl_ext;
531
532 /* Let firmware know the driver has taken over */
533 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
534 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
535 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
536 }
537
538 /*
539 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
540 * @adapter: pointer to adapter struct
541 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
542 * @queue: queue to map the corresponding interrupt to
543 * @msix_vector: the vector to map to the corresponding queue
544 *
545 */
546 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
547 u8 queue, u8 msix_vector)
548 {
549 u32 ivar, index;
550 struct ixgbe_hw *hw = &adapter->hw;
551 switch (hw->mac.type) {
552 case ixgbe_mac_82598EB:
553 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
554 if (direction == -1)
555 direction = 0;
556 index = (((direction * 64) + queue) >> 2) & 0x1F;
557 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
558 ivar &= ~(0xFF << (8 * (queue & 0x3)));
559 ivar |= (msix_vector << (8 * (queue & 0x3)));
560 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
561 break;
562 case ixgbe_mac_82599EB:
563 if (direction == -1) {
564 /* other causes */
565 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
566 index = ((queue & 1) * 8);
567 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
568 ivar &= ~(0xFF << index);
569 ivar |= (msix_vector << index);
570 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
571 break;
572 } else {
573 /* tx or rx causes */
574 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
575 index = ((16 * (queue & 1)) + (8 * direction));
576 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
577 ivar &= ~(0xFF << index);
578 ivar |= (msix_vector << index);
579 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
580 break;
581 }
582 default:
583 break;
584 }
585 }
586
587 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
588 u64 qmask)
589 {
590 u32 mask;
591
592 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
593 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
594 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
595 } else {
596 mask = (qmask & 0xFFFFFFFF);
597 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
598 mask = (qmask >> 32);
599 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
600 }
601 }
602
603 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
604 struct ixgbe_tx_buffer
605 *tx_buffer_info)
606 {
607 if (tx_buffer_info->dma) {
608 if (tx_buffer_info->mapped_as_page)
609 dma_unmap_page(&adapter->pdev->dev,
610 tx_buffer_info->dma,
611 tx_buffer_info->length,
612 DMA_TO_DEVICE);
613 else
614 dma_unmap_single(&adapter->pdev->dev,
615 tx_buffer_info->dma,
616 tx_buffer_info->length,
617 DMA_TO_DEVICE);
618 tx_buffer_info->dma = 0;
619 }
620 if (tx_buffer_info->skb) {
621 dev_kfree_skb_any(tx_buffer_info->skb);
622 tx_buffer_info->skb = NULL;
623 }
624 tx_buffer_info->time_stamp = 0;
625 /* tx_buffer_info must be completely set up in the transmit path */
626 }
627
628 /**
629 * ixgbe_tx_xon_state - check the tx ring xon state
630 * @adapter: the ixgbe adapter
631 * @tx_ring: the corresponding tx_ring
632 *
633 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
634 * corresponding TC of this tx_ring when checking TFCS.
635 *
636 * Returns : true if in xon state (currently not paused)
637 */
638 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter *adapter,
639 struct ixgbe_ring *tx_ring)
640 {
641 u32 txoff = IXGBE_TFCS_TXOFF;
642
643 #ifdef CONFIG_IXGBE_DCB
644 if (adapter->dcb_cfg.pfc_mode_enable) {
645 int tc;
646 int reg_idx = tx_ring->reg_idx;
647 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
648
649 switch (adapter->hw.mac.type) {
650 case ixgbe_mac_82598EB:
651 tc = reg_idx >> 2;
652 txoff = IXGBE_TFCS_TXOFF0;
653 break;
654 case ixgbe_mac_82599EB:
655 tc = 0;
656 txoff = IXGBE_TFCS_TXOFF;
657 if (dcb_i == 8) {
658 /* TC0, TC1 */
659 tc = reg_idx >> 5;
660 if (tc == 2) /* TC2, TC3 */
661 tc += (reg_idx - 64) >> 4;
662 else if (tc == 3) /* TC4, TC5, TC6, TC7 */
663 tc += 1 + ((reg_idx - 96) >> 3);
664 } else if (dcb_i == 4) {
665 /* TC0, TC1 */
666 tc = reg_idx >> 6;
667 if (tc == 1) {
668 tc += (reg_idx - 64) >> 5;
669 if (tc == 2) /* TC2, TC3 */
670 tc += (reg_idx - 96) >> 4;
671 }
672 }
673 break;
674 default:
675 tc = 0;
676 }
677 txoff <<= tc;
678 }
679 #endif
680 return IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & txoff;
681 }
682
683 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
684 struct ixgbe_ring *tx_ring,
685 unsigned int eop)
686 {
687 struct ixgbe_hw *hw = &adapter->hw;
688
689 /* Detect a transmit hang in hardware, this serializes the
690 * check with the clearing of time_stamp and movement of eop */
691 adapter->detect_tx_hung = false;
692 if (tx_ring->tx_buffer_info[eop].time_stamp &&
693 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
694 ixgbe_tx_xon_state(adapter, tx_ring)) {
695 /* detected Tx unit hang */
696 union ixgbe_adv_tx_desc *tx_desc;
697 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
698 e_err(drv, "Detected Tx Unit Hang\n"
699 " Tx Queue <%d>\n"
700 " TDH, TDT <%x>, <%x>\n"
701 " next_to_use <%x>\n"
702 " next_to_clean <%x>\n"
703 "tx_buffer_info[next_to_clean]\n"
704 " time_stamp <%lx>\n"
705 " jiffies <%lx>\n",
706 tx_ring->queue_index,
707 IXGBE_READ_REG(hw, tx_ring->head),
708 IXGBE_READ_REG(hw, tx_ring->tail),
709 tx_ring->next_to_use, eop,
710 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
711 return true;
712 }
713
714 return false;
715 }
716
717 #define IXGBE_MAX_TXD_PWR 14
718 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
719
720 /* Tx Descriptors needed, worst case */
721 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
722 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
723 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
724 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
725
726 static void ixgbe_tx_timeout(struct net_device *netdev);
727
728 /**
729 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
730 * @q_vector: structure containing interrupt and ring information
731 * @tx_ring: tx ring to clean
732 **/
733 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
734 struct ixgbe_ring *tx_ring)
735 {
736 struct ixgbe_adapter *adapter = q_vector->adapter;
737 struct net_device *netdev = adapter->netdev;
738 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
739 struct ixgbe_tx_buffer *tx_buffer_info;
740 unsigned int i, eop, count = 0;
741 unsigned int total_bytes = 0, total_packets = 0;
742
743 i = tx_ring->next_to_clean;
744 eop = tx_ring->tx_buffer_info[i].next_to_watch;
745 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
746
747 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
748 (count < tx_ring->work_limit)) {
749 bool cleaned = false;
750 rmb(); /* read buffer_info after eop_desc */
751 for ( ; !cleaned; count++) {
752 struct sk_buff *skb;
753 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
754 tx_buffer_info = &tx_ring->tx_buffer_info[i];
755 cleaned = (i == eop);
756 skb = tx_buffer_info->skb;
757
758 if (cleaned && skb) {
759 unsigned int segs, bytecount;
760 unsigned int hlen = skb_headlen(skb);
761
762 /* gso_segs is currently only valid for tcp */
763 segs = skb_shinfo(skb)->gso_segs ?: 1;
764 #ifdef IXGBE_FCOE
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
767 && skb_is_gso(skb)
768 && vlan_get_protocol(skb) ==
769 htons(ETH_P_FCOE)) {
770 hlen = skb_transport_offset(skb) +
771 sizeof(struct fc_frame_header) +
772 sizeof(struct fcoe_crc_eof);
773 segs = DIV_ROUND_UP(skb->len - hlen,
774 skb_shinfo(skb)->gso_size);
775 }
776 #endif /* IXGBE_FCOE */
777 /* multiply data chunks by size of headers */
778 bytecount = ((segs - 1) * hlen) + skb->len;
779 total_packets += segs;
780 total_bytes += bytecount;
781 }
782
783 ixgbe_unmap_and_free_tx_resource(adapter,
784 tx_buffer_info);
785
786 tx_desc->wb.status = 0;
787
788 i++;
789 if (i == tx_ring->count)
790 i = 0;
791 }
792
793 eop = tx_ring->tx_buffer_info[i].next_to_watch;
794 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
795 }
796
797 tx_ring->next_to_clean = i;
798
799 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
800 if (unlikely(count && netif_carrier_ok(netdev) &&
801 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
802 /* Make sure that anybody stopping the queue after this
803 * sees the new next_to_clean.
804 */
805 smp_mb();
806 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
807 !test_bit(__IXGBE_DOWN, &adapter->state)) {
808 netif_wake_subqueue(netdev, tx_ring->queue_index);
809 ++tx_ring->restart_queue;
810 }
811 }
812
813 if (adapter->detect_tx_hung) {
814 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
815 /* schedule immediate reset if we believe we hung */
816 e_info(probe, "tx hang %d detected, resetting "
817 "adapter\n", adapter->tx_timeout_count + 1);
818 ixgbe_tx_timeout(adapter->netdev);
819 }
820 }
821
822 /* re-arm the interrupt */
823 if (count >= tx_ring->work_limit)
824 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
825
826 tx_ring->total_bytes += total_bytes;
827 tx_ring->total_packets += total_packets;
828 u64_stats_update_begin(&tx_ring->syncp);
829 tx_ring->stats.packets += total_packets;
830 tx_ring->stats.bytes += total_bytes;
831 u64_stats_update_end(&tx_ring->syncp);
832 return count < tx_ring->work_limit;
833 }
834
835 #ifdef CONFIG_IXGBE_DCA
836 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
837 struct ixgbe_ring *rx_ring)
838 {
839 u32 rxctrl;
840 int cpu = get_cpu();
841 int q = rx_ring->reg_idx;
842
843 if (rx_ring->cpu != cpu) {
844 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
845 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
846 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
847 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
848 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
849 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
850 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
851 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
852 }
853 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
854 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
855 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
856 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
857 IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
859 rx_ring->cpu = cpu;
860 }
861 put_cpu();
862 }
863
864 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
865 struct ixgbe_ring *tx_ring)
866 {
867 u32 txctrl;
868 int cpu = get_cpu();
869 int q = tx_ring->reg_idx;
870 struct ixgbe_hw *hw = &adapter->hw;
871
872 if (tx_ring->cpu != cpu) {
873 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
874 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(q));
875 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
876 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
877 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
878 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(q), txctrl);
879 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
880 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(q));
881 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
882 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
883 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
884 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
885 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(q), txctrl);
886 }
887 tx_ring->cpu = cpu;
888 }
889 put_cpu();
890 }
891
892 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
893 {
894 int i;
895
896 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
897 return;
898
899 /* always use CB2 mode, difference is masked in the CB driver */
900 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
901
902 for (i = 0; i < adapter->num_tx_queues; i++) {
903 adapter->tx_ring[i]->cpu = -1;
904 ixgbe_update_tx_dca(adapter, adapter->tx_ring[i]);
905 }
906 for (i = 0; i < adapter->num_rx_queues; i++) {
907 adapter->rx_ring[i]->cpu = -1;
908 ixgbe_update_rx_dca(adapter, adapter->rx_ring[i]);
909 }
910 }
911
912 static int __ixgbe_notify_dca(struct device *dev, void *data)
913 {
914 struct net_device *netdev = dev_get_drvdata(dev);
915 struct ixgbe_adapter *adapter = netdev_priv(netdev);
916 unsigned long event = *(unsigned long *)data;
917
918 switch (event) {
919 case DCA_PROVIDER_ADD:
920 /* if we're already enabled, don't do it again */
921 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
922 break;
923 if (dca_add_requester(dev) == 0) {
924 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
925 ixgbe_setup_dca(adapter);
926 break;
927 }
928 /* Fall Through since DCA is disabled. */
929 case DCA_PROVIDER_REMOVE:
930 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
931 dca_remove_requester(dev);
932 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
933 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
934 }
935 break;
936 }
937
938 return 0;
939 }
940
941 #endif /* CONFIG_IXGBE_DCA */
942 /**
943 * ixgbe_receive_skb - Send a completed packet up the stack
944 * @adapter: board private structure
945 * @skb: packet to send up
946 * @status: hardware indication of status of receive
947 * @rx_ring: rx descriptor ring (for a specific queue) to setup
948 * @rx_desc: rx descriptor
949 **/
950 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
951 struct sk_buff *skb, u8 status,
952 struct ixgbe_ring *ring,
953 union ixgbe_adv_rx_desc *rx_desc)
954 {
955 struct ixgbe_adapter *adapter = q_vector->adapter;
956 struct napi_struct *napi = &q_vector->napi;
957 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
958 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
959
960 if (is_vlan && (tag & VLAN_VID_MASK))
961 __vlan_hwaccel_put_tag(skb, tag);
962
963 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
964 napi_gro_receive(napi, skb);
965 else
966 netif_rx(skb);
967 }
968
969 /**
970 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
971 * @adapter: address of board private structure
972 * @status_err: hardware indication of status of receive
973 * @skb: skb currently being received and modified
974 **/
975 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
976 union ixgbe_adv_rx_desc *rx_desc,
977 struct sk_buff *skb)
978 {
979 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
980
981 skb_checksum_none_assert(skb);
982
983 /* Rx csum disabled */
984 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
985 return;
986
987 /* if IP and error */
988 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
989 (status_err & IXGBE_RXDADV_ERR_IPE)) {
990 adapter->hw_csum_rx_error++;
991 return;
992 }
993
994 if (!(status_err & IXGBE_RXD_STAT_L4CS))
995 return;
996
997 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
998 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
999
1000 /*
1001 * 82599 errata, UDP frames with a 0 checksum can be marked as
1002 * checksum errors.
1003 */
1004 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1005 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1006 return;
1007
1008 adapter->hw_csum_rx_error++;
1009 return;
1010 }
1011
1012 /* It must be a TCP or UDP packet with a valid checksum */
1013 skb->ip_summed = CHECKSUM_UNNECESSARY;
1014 }
1015
1016 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
1017 struct ixgbe_ring *rx_ring, u32 val)
1018 {
1019 /*
1020 * Force memory writes to complete before letting h/w
1021 * know there are new descriptors to fetch. (Only
1022 * applicable for weak-ordered memory model archs,
1023 * such as IA-64).
1024 */
1025 wmb();
1026 IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
1027 }
1028
1029 /**
1030 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1031 * @adapter: address of board private structure
1032 **/
1033 void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
1034 struct ixgbe_ring *rx_ring,
1035 int cleaned_count)
1036 {
1037 struct net_device *netdev = adapter->netdev;
1038 struct pci_dev *pdev = adapter->pdev;
1039 union ixgbe_adv_rx_desc *rx_desc;
1040 struct ixgbe_rx_buffer *bi;
1041 unsigned int i;
1042 unsigned int bufsz = rx_ring->rx_buf_len;
1043
1044 i = rx_ring->next_to_use;
1045 bi = &rx_ring->rx_buffer_info[i];
1046
1047 while (cleaned_count--) {
1048 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1049
1050 if (!bi->page_dma &&
1051 (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
1052 if (!bi->page) {
1053 bi->page = netdev_alloc_page(netdev);
1054 if (!bi->page) {
1055 adapter->alloc_rx_page_failed++;
1056 goto no_buffers;
1057 }
1058 bi->page_offset = 0;
1059 } else {
1060 /* use a half page if we're re-using */
1061 bi->page_offset ^= (PAGE_SIZE / 2);
1062 }
1063
1064 bi->page_dma = dma_map_page(&pdev->dev, bi->page,
1065 bi->page_offset,
1066 (PAGE_SIZE / 2),
1067 DMA_FROM_DEVICE);
1068 }
1069
1070 if (!bi->skb) {
1071 struct sk_buff *skb = netdev_alloc_skb_ip_align(netdev,
1072 bufsz);
1073 bi->skb = skb;
1074
1075 if (!skb) {
1076 adapter->alloc_rx_buff_failed++;
1077 goto no_buffers;
1078 }
1079 /* initialize queue mapping */
1080 skb_record_rx_queue(skb, rx_ring->queue_index);
1081 }
1082
1083 if (!bi->dma) {
1084 bi->dma = dma_map_single(&pdev->dev,
1085 bi->skb->data,
1086 rx_ring->rx_buf_len,
1087 DMA_FROM_DEVICE);
1088 }
1089 /* Refresh the desc even if buffer_addrs didn't change because
1090 * each write-back erases this info. */
1091 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1092 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1093 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1094 } else {
1095 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1096 rx_desc->read.hdr_addr = 0;
1097 }
1098
1099 i++;
1100 if (i == rx_ring->count)
1101 i = 0;
1102 bi = &rx_ring->rx_buffer_info[i];
1103 }
1104
1105 no_buffers:
1106 if (rx_ring->next_to_use != i) {
1107 rx_ring->next_to_use = i;
1108 if (i-- == 0)
1109 i = (rx_ring->count - 1);
1110
1111 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
1112 }
1113 }
1114
1115 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
1116 {
1117 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
1118 }
1119
1120 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
1121 {
1122 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1123 }
1124
1125 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
1126 {
1127 return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1128 IXGBE_RXDADV_RSCCNT_MASK) >>
1129 IXGBE_RXDADV_RSCCNT_SHIFT;
1130 }
1131
1132 /**
1133 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134 * @skb: pointer to the last skb in the rsc queue
1135 * @count: pointer to number of packets coalesced in this context
1136 *
1137 * This function changes a queue full of hw rsc buffers into a completed
1138 * packet. It uses the ->prev pointers to find the first packet and then
1139 * turns it into the frag list owner.
1140 **/
1141 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb,
1142 u64 *count)
1143 {
1144 unsigned int frag_list_size = 0;
1145
1146 while (skb->prev) {
1147 struct sk_buff *prev = skb->prev;
1148 frag_list_size += skb->len;
1149 skb->prev = NULL;
1150 skb = prev;
1151 *count += 1;
1152 }
1153
1154 skb_shinfo(skb)->frag_list = skb->next;
1155 skb->next = NULL;
1156 skb->len += frag_list_size;
1157 skb->data_len += frag_list_size;
1158 skb->truesize += frag_list_size;
1159 return skb;
1160 }
1161
1162 struct ixgbe_rsc_cb {
1163 dma_addr_t dma;
1164 bool delay_unmap;
1165 };
1166
1167 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1168
1169 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1170 struct ixgbe_ring *rx_ring,
1171 int *work_done, int work_to_do)
1172 {
1173 struct ixgbe_adapter *adapter = q_vector->adapter;
1174 struct pci_dev *pdev = adapter->pdev;
1175 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1176 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1177 struct sk_buff *skb;
1178 unsigned int i, rsc_count = 0;
1179 u32 len, staterr;
1180 u16 hdr_info;
1181 bool cleaned = false;
1182 int cleaned_count = 0;
1183 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1184 #ifdef IXGBE_FCOE
1185 int ddp_bytes = 0;
1186 #endif /* IXGBE_FCOE */
1187
1188 i = rx_ring->next_to_clean;
1189 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1190 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1191 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1192
1193 while (staterr & IXGBE_RXD_STAT_DD) {
1194 u32 upper_len = 0;
1195 if (*work_done >= work_to_do)
1196 break;
1197 (*work_done)++;
1198
1199 rmb(); /* read descriptor and rx_buffer_info after status DD */
1200 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1201 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
1202 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1203 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1204 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1205 if ((len > IXGBE_RX_HDR_SIZE) ||
1206 (upper_len && !(hdr_info & IXGBE_RXDADV_SPH)))
1207 len = IXGBE_RX_HDR_SIZE;
1208 } else {
1209 len = le16_to_cpu(rx_desc->wb.upper.length);
1210 }
1211
1212 cleaned = true;
1213 skb = rx_buffer_info->skb;
1214 prefetch(skb->data);
1215 rx_buffer_info->skb = NULL;
1216
1217 if (rx_buffer_info->dma) {
1218 if ((adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
1219 (!(staterr & IXGBE_RXD_STAT_EOP)) &&
1220 (!(skb->prev))) {
1221 /*
1222 * When HWRSC is enabled, delay unmapping
1223 * of the first packet. It carries the
1224 * header information, HW may still
1225 * access the header after the writeback.
1226 * Only unmap it when EOP is reached
1227 */
1228 IXGBE_RSC_CB(skb)->delay_unmap = true;
1229 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1230 } else {
1231 dma_unmap_single(&pdev->dev,
1232 rx_buffer_info->dma,
1233 rx_ring->rx_buf_len,
1234 DMA_FROM_DEVICE);
1235 }
1236 rx_buffer_info->dma = 0;
1237 skb_put(skb, len);
1238 }
1239
1240 if (upper_len) {
1241 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
1242 PAGE_SIZE / 2, DMA_FROM_DEVICE);
1243 rx_buffer_info->page_dma = 0;
1244 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1245 rx_buffer_info->page,
1246 rx_buffer_info->page_offset,
1247 upper_len);
1248
1249 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
1250 (page_count(rx_buffer_info->page) != 1))
1251 rx_buffer_info->page = NULL;
1252 else
1253 get_page(rx_buffer_info->page);
1254
1255 skb->len += upper_len;
1256 skb->data_len += upper_len;
1257 skb->truesize += upper_len;
1258 }
1259
1260 i++;
1261 if (i == rx_ring->count)
1262 i = 0;
1263
1264 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1265 prefetch(next_rxd);
1266 cleaned_count++;
1267
1268 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
1269 rsc_count = ixgbe_get_rsc_count(rx_desc);
1270
1271 if (rsc_count) {
1272 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1273 IXGBE_RXDADV_NEXTP_SHIFT;
1274 next_buffer = &rx_ring->rx_buffer_info[nextp];
1275 } else {
1276 next_buffer = &rx_ring->rx_buffer_info[i];
1277 }
1278
1279 if (staterr & IXGBE_RXD_STAT_EOP) {
1280 if (skb->prev)
1281 skb = ixgbe_transform_rsc_queue(skb,
1282 &(rx_ring->rsc_count));
1283 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
1284 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1285 dma_unmap_single(&pdev->dev,
1286 IXGBE_RSC_CB(skb)->dma,
1287 rx_ring->rx_buf_len,
1288 DMA_FROM_DEVICE);
1289 IXGBE_RSC_CB(skb)->dma = 0;
1290 IXGBE_RSC_CB(skb)->delay_unmap = false;
1291 }
1292 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)
1293 rx_ring->rsc_count +=
1294 skb_shinfo(skb)->nr_frags;
1295 else
1296 rx_ring->rsc_count++;
1297 rx_ring->rsc_flush++;
1298 }
1299 u64_stats_update_begin(&rx_ring->syncp);
1300 rx_ring->stats.packets++;
1301 rx_ring->stats.bytes += skb->len;
1302 u64_stats_update_end(&rx_ring->syncp);
1303 } else {
1304 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1305 rx_buffer_info->skb = next_buffer->skb;
1306 rx_buffer_info->dma = next_buffer->dma;
1307 next_buffer->skb = skb;
1308 next_buffer->dma = 0;
1309 } else {
1310 skb->next = next_buffer->skb;
1311 skb->next->prev = skb;
1312 }
1313 rx_ring->non_eop_descs++;
1314 goto next_desc;
1315 }
1316
1317 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1318 dev_kfree_skb_irq(skb);
1319 goto next_desc;
1320 }
1321
1322 ixgbe_rx_checksum(adapter, rx_desc, skb);
1323
1324 /* probably a little skewed due to removing CRC */
1325 total_rx_bytes += skb->len;
1326 total_rx_packets++;
1327
1328 skb->protocol = eth_type_trans(skb, adapter->netdev);
1329 #ifdef IXGBE_FCOE
1330 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1331 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1332 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1333 if (!ddp_bytes)
1334 goto next_desc;
1335 }
1336 #endif /* IXGBE_FCOE */
1337 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1338
1339 next_desc:
1340 rx_desc->wb.upper.status_error = 0;
1341
1342 /* return some buffers to hardware, one at a time is too slow */
1343 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1344 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1345 cleaned_count = 0;
1346 }
1347
1348 /* use prefetched values */
1349 rx_desc = next_rxd;
1350 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1351
1352 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1353 }
1354
1355 rx_ring->next_to_clean = i;
1356 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1357
1358 if (cleaned_count)
1359 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
1360
1361 #ifdef IXGBE_FCOE
1362 /* include DDPed FCoE data */
1363 if (ddp_bytes > 0) {
1364 unsigned int mss;
1365
1366 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
1367 sizeof(struct fc_frame_header) -
1368 sizeof(struct fcoe_crc_eof);
1369 if (mss > 512)
1370 mss &= ~511;
1371 total_rx_bytes += ddp_bytes;
1372 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1373 }
1374 #endif /* IXGBE_FCOE */
1375
1376 rx_ring->total_packets += total_rx_packets;
1377 rx_ring->total_bytes += total_rx_bytes;
1378
1379 return cleaned;
1380 }
1381
1382 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1383 /**
1384 * ixgbe_configure_msix - Configure MSI-X hardware
1385 * @adapter: board private structure
1386 *
1387 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1388 * interrupts.
1389 **/
1390 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1391 {
1392 struct ixgbe_q_vector *q_vector;
1393 int i, j, q_vectors, v_idx, r_idx;
1394 u32 mask;
1395
1396 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1397
1398 /*
1399 * Populate the IVAR table and set the ITR values to the
1400 * corresponding register.
1401 */
1402 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1403 q_vector = adapter->q_vector[v_idx];
1404 /* XXX for_each_set_bit(...) */
1405 r_idx = find_first_bit(q_vector->rxr_idx,
1406 adapter->num_rx_queues);
1407
1408 for (i = 0; i < q_vector->rxr_count; i++) {
1409 j = adapter->rx_ring[r_idx]->reg_idx;
1410 ixgbe_set_ivar(adapter, 0, j, v_idx);
1411 r_idx = find_next_bit(q_vector->rxr_idx,
1412 adapter->num_rx_queues,
1413 r_idx + 1);
1414 }
1415 r_idx = find_first_bit(q_vector->txr_idx,
1416 adapter->num_tx_queues);
1417
1418 for (i = 0; i < q_vector->txr_count; i++) {
1419 j = adapter->tx_ring[r_idx]->reg_idx;
1420 ixgbe_set_ivar(adapter, 1, j, v_idx);
1421 r_idx = find_next_bit(q_vector->txr_idx,
1422 adapter->num_tx_queues,
1423 r_idx + 1);
1424 }
1425
1426 if (q_vector->txr_count && !q_vector->rxr_count)
1427 /* tx only */
1428 q_vector->eitr = adapter->tx_eitr_param;
1429 else if (q_vector->rxr_count)
1430 /* rx or mixed */
1431 q_vector->eitr = adapter->rx_eitr_param;
1432
1433 ixgbe_write_eitr(q_vector);
1434 /* If Flow Director is enabled, set interrupt affinity */
1435 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
1436 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)) {
1437 /*
1438 * Allocate the affinity_hint cpumask, assign the mask
1439 * for this vector, and set our affinity_hint for
1440 * this irq.
1441 */
1442 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1443 GFP_KERNEL))
1444 return;
1445 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1446 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1447 q_vector->affinity_mask);
1448 }
1449 }
1450
1451 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
1452 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1453 v_idx);
1454 else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
1455 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1456 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1457
1458 /* set up to autoclear timer, and the vectors */
1459 mask = IXGBE_EIMS_ENABLE_MASK;
1460 if (adapter->num_vfs)
1461 mask &= ~(IXGBE_EIMS_OTHER |
1462 IXGBE_EIMS_MAILBOX |
1463 IXGBE_EIMS_LSC);
1464 else
1465 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1466 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1467 }
1468
1469 enum latency_range {
1470 lowest_latency = 0,
1471 low_latency = 1,
1472 bulk_latency = 2,
1473 latency_invalid = 255
1474 };
1475
1476 /**
1477 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1478 * @adapter: pointer to adapter
1479 * @eitr: eitr setting (ints per sec) to give last timeslice
1480 * @itr_setting: current throttle rate in ints/second
1481 * @packets: the number of packets during this measurement interval
1482 * @bytes: the number of bytes during this measurement interval
1483 *
1484 * Stores a new ITR value based on packets and byte
1485 * counts during the last interrupt. The advantage of per interrupt
1486 * computation is faster updates and more accurate ITR for the current
1487 * traffic pattern. Constants in this function were computed
1488 * based on theoretical maximum wire speed and thresholds were set based
1489 * on testing data as well as attempting to minimize response time
1490 * while increasing bulk throughput.
1491 * this functionality is controlled by the InterruptThrottleRate module
1492 * parameter (see ixgbe_param.c)
1493 **/
1494 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1495 u32 eitr, u8 itr_setting,
1496 int packets, int bytes)
1497 {
1498 unsigned int retval = itr_setting;
1499 u32 timepassed_us;
1500 u64 bytes_perint;
1501
1502 if (packets == 0)
1503 goto update_itr_done;
1504
1505
1506 /* simple throttlerate management
1507 * 0-20MB/s lowest (100000 ints/s)
1508 * 20-100MB/s low (20000 ints/s)
1509 * 100-1249MB/s bulk (8000 ints/s)
1510 */
1511 /* what was last interrupt timeslice? */
1512 timepassed_us = 1000000/eitr;
1513 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1514
1515 switch (itr_setting) {
1516 case lowest_latency:
1517 if (bytes_perint > adapter->eitr_low)
1518 retval = low_latency;
1519 break;
1520 case low_latency:
1521 if (bytes_perint > adapter->eitr_high)
1522 retval = bulk_latency;
1523 else if (bytes_perint <= adapter->eitr_low)
1524 retval = lowest_latency;
1525 break;
1526 case bulk_latency:
1527 if (bytes_perint <= adapter->eitr_high)
1528 retval = low_latency;
1529 break;
1530 }
1531
1532 update_itr_done:
1533 return retval;
1534 }
1535
1536 /**
1537 * ixgbe_write_eitr - write EITR register in hardware specific way
1538 * @q_vector: structure containing interrupt and ring information
1539 *
1540 * This function is made to be called by ethtool and by the driver
1541 * when it needs to update EITR registers at runtime. Hardware
1542 * specific quirks/differences are taken care of here.
1543 */
1544 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1545 {
1546 struct ixgbe_adapter *adapter = q_vector->adapter;
1547 struct ixgbe_hw *hw = &adapter->hw;
1548 int v_idx = q_vector->v_idx;
1549 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1550
1551 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1552 /* must write high and low 16 bits to reset counter */
1553 itr_reg |= (itr_reg << 16);
1554 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1555 /*
1556 * 82599 can support a value of zero, so allow it for
1557 * max interrupt rate, but there is an errata where it can
1558 * not be zero with RSC
1559 */
1560 if (itr_reg == 8 &&
1561 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1562 itr_reg = 0;
1563
1564 /*
1565 * set the WDIS bit to not clear the timer bits and cause an
1566 * immediate assertion of the interrupt
1567 */
1568 itr_reg |= IXGBE_EITR_CNT_WDIS;
1569 }
1570 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1571 }
1572
1573 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1574 {
1575 struct ixgbe_adapter *adapter = q_vector->adapter;
1576 u32 new_itr;
1577 u8 current_itr, ret_itr;
1578 int i, r_idx;
1579 struct ixgbe_ring *rx_ring, *tx_ring;
1580
1581 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1582 for (i = 0; i < q_vector->txr_count; i++) {
1583 tx_ring = adapter->tx_ring[r_idx];
1584 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1585 q_vector->tx_itr,
1586 tx_ring->total_packets,
1587 tx_ring->total_bytes);
1588 /* if the result for this queue would decrease interrupt
1589 * rate for this vector then use that result */
1590 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1591 q_vector->tx_itr - 1 : ret_itr);
1592 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1593 r_idx + 1);
1594 }
1595
1596 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1597 for (i = 0; i < q_vector->rxr_count; i++) {
1598 rx_ring = adapter->rx_ring[r_idx];
1599 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1600 q_vector->rx_itr,
1601 rx_ring->total_packets,
1602 rx_ring->total_bytes);
1603 /* if the result for this queue would decrease interrupt
1604 * rate for this vector then use that result */
1605 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1606 q_vector->rx_itr - 1 : ret_itr);
1607 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1608 r_idx + 1);
1609 }
1610
1611 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1612
1613 switch (current_itr) {
1614 /* counts and packets in update_itr are dependent on these numbers */
1615 case lowest_latency:
1616 new_itr = 100000;
1617 break;
1618 case low_latency:
1619 new_itr = 20000; /* aka hwitr = ~200 */
1620 break;
1621 case bulk_latency:
1622 default:
1623 new_itr = 8000;
1624 break;
1625 }
1626
1627 if (new_itr != q_vector->eitr) {
1628 /* do an exponential smoothing */
1629 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1630
1631 /* save the algorithm value here, not the smoothed one */
1632 q_vector->eitr = new_itr;
1633
1634 ixgbe_write_eitr(q_vector);
1635 }
1636 }
1637
1638 /**
1639 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1640 * @work: pointer to work_struct containing our data
1641 **/
1642 static void ixgbe_check_overtemp_task(struct work_struct *work)
1643 {
1644 struct ixgbe_adapter *adapter = container_of(work,
1645 struct ixgbe_adapter,
1646 check_overtemp_task);
1647 struct ixgbe_hw *hw = &adapter->hw;
1648 u32 eicr = adapter->interrupt_event;
1649
1650 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
1651 return;
1652
1653 switch (hw->device_id) {
1654 case IXGBE_DEV_ID_82599_T3_LOM: {
1655 u32 autoneg;
1656 bool link_up = false;
1657
1658 if (hw->mac.ops.check_link)
1659 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1660
1661 if (((eicr & IXGBE_EICR_GPI_SDP0) && (!link_up)) ||
1662 (eicr & IXGBE_EICR_LSC))
1663 /* Check if this is due to overtemp */
1664 if (hw->phy.ops.check_overtemp(hw) == IXGBE_ERR_OVERTEMP)
1665 break;
1666 return;
1667 }
1668 default:
1669 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1670 return;
1671 break;
1672 }
1673 e_crit(drv,
1674 "Network adapter has been stopped because it has over heated. "
1675 "Restart the computer. If the problem persists, "
1676 "power off the system and replace the adapter\n");
1677 /* write to clear the interrupt */
1678 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP0);
1679 }
1680
1681 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1682 {
1683 struct ixgbe_hw *hw = &adapter->hw;
1684
1685 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1686 (eicr & IXGBE_EICR_GPI_SDP1)) {
1687 e_crit(probe, "Fan has stopped, replace the adapter\n");
1688 /* write to clear the interrupt */
1689 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1690 }
1691 }
1692
1693 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1694 {
1695 struct ixgbe_hw *hw = &adapter->hw;
1696
1697 if (eicr & IXGBE_EICR_GPI_SDP1) {
1698 /* Clear the interrupt */
1699 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1700 schedule_work(&adapter->multispeed_fiber_task);
1701 } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1702 /* Clear the interrupt */
1703 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1704 schedule_work(&adapter->sfp_config_module_task);
1705 } else {
1706 /* Interrupt isn't for us... */
1707 return;
1708 }
1709 }
1710
1711 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1712 {
1713 struct ixgbe_hw *hw = &adapter->hw;
1714
1715 adapter->lsc_int++;
1716 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1717 adapter->link_check_timeout = jiffies;
1718 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1719 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1720 IXGBE_WRITE_FLUSH(hw);
1721 schedule_work(&adapter->watchdog_task);
1722 }
1723 }
1724
1725 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1726 {
1727 struct net_device *netdev = data;
1728 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1729 struct ixgbe_hw *hw = &adapter->hw;
1730 u32 eicr;
1731
1732 /*
1733 * Workaround for Silicon errata. Use clear-by-write instead
1734 * of clear-by-read. Reading with EICS will return the
1735 * interrupt causes without clearing, which later be done
1736 * with the write to EICR.
1737 */
1738 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1739 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1740
1741 if (eicr & IXGBE_EICR_LSC)
1742 ixgbe_check_lsc(adapter);
1743
1744 if (eicr & IXGBE_EICR_MAILBOX)
1745 ixgbe_msg_task(adapter);
1746
1747 if (hw->mac.type == ixgbe_mac_82598EB)
1748 ixgbe_check_fan_failure(adapter, eicr);
1749
1750 if (hw->mac.type == ixgbe_mac_82599EB) {
1751 ixgbe_check_sfp_event(adapter, eicr);
1752 adapter->interrupt_event = eicr;
1753 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1754 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
1755 schedule_work(&adapter->check_overtemp_task);
1756
1757 /* Handle Flow Director Full threshold interrupt */
1758 if (eicr & IXGBE_EICR_FLOW_DIR) {
1759 int i;
1760 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1761 /* Disable transmits before FDIR Re-initialization */
1762 netif_tx_stop_all_queues(netdev);
1763 for (i = 0; i < adapter->num_tx_queues; i++) {
1764 struct ixgbe_ring *tx_ring =
1765 adapter->tx_ring[i];
1766 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1767 &tx_ring->reinit_state))
1768 schedule_work(&adapter->fdir_reinit_task);
1769 }
1770 }
1771 }
1772 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1773 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1774
1775 return IRQ_HANDLED;
1776 }
1777
1778 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1779 u64 qmask)
1780 {
1781 u32 mask;
1782
1783 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1784 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1785 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1786 } else {
1787 mask = (qmask & 0xFFFFFFFF);
1788 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1789 mask = (qmask >> 32);
1790 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1791 }
1792 /* skip the flush */
1793 }
1794
1795 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1796 u64 qmask)
1797 {
1798 u32 mask;
1799
1800 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1801 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1802 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1803 } else {
1804 mask = (qmask & 0xFFFFFFFF);
1805 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1806 mask = (qmask >> 32);
1807 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1808 }
1809 /* skip the flush */
1810 }
1811
1812 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1813 {
1814 struct ixgbe_q_vector *q_vector = data;
1815 struct ixgbe_adapter *adapter = q_vector->adapter;
1816 struct ixgbe_ring *tx_ring;
1817 int i, r_idx;
1818
1819 if (!q_vector->txr_count)
1820 return IRQ_HANDLED;
1821
1822 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1823 for (i = 0; i < q_vector->txr_count; i++) {
1824 tx_ring = adapter->tx_ring[r_idx];
1825 tx_ring->total_bytes = 0;
1826 tx_ring->total_packets = 0;
1827 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1828 r_idx + 1);
1829 }
1830
1831 /* EIAM disabled interrupts (on this vector) for us */
1832 napi_schedule(&q_vector->napi);
1833
1834 return IRQ_HANDLED;
1835 }
1836
1837 /**
1838 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1839 * @irq: unused
1840 * @data: pointer to our q_vector struct for this interrupt vector
1841 **/
1842 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1843 {
1844 struct ixgbe_q_vector *q_vector = data;
1845 struct ixgbe_adapter *adapter = q_vector->adapter;
1846 struct ixgbe_ring *rx_ring;
1847 int r_idx;
1848 int i;
1849
1850 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1851 for (i = 0; i < q_vector->rxr_count; i++) {
1852 rx_ring = adapter->rx_ring[r_idx];
1853 rx_ring->total_bytes = 0;
1854 rx_ring->total_packets = 0;
1855 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1856 r_idx + 1);
1857 }
1858
1859 if (!q_vector->rxr_count)
1860 return IRQ_HANDLED;
1861
1862 /* disable interrupts on this vector only */
1863 /* EIAM disabled interrupts (on this vector) for us */
1864 napi_schedule(&q_vector->napi);
1865
1866 return IRQ_HANDLED;
1867 }
1868
1869 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1870 {
1871 struct ixgbe_q_vector *q_vector = data;
1872 struct ixgbe_adapter *adapter = q_vector->adapter;
1873 struct ixgbe_ring *ring;
1874 int r_idx;
1875 int i;
1876
1877 if (!q_vector->txr_count && !q_vector->rxr_count)
1878 return IRQ_HANDLED;
1879
1880 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1881 for (i = 0; i < q_vector->txr_count; i++) {
1882 ring = adapter->tx_ring[r_idx];
1883 ring->total_bytes = 0;
1884 ring->total_packets = 0;
1885 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1886 r_idx + 1);
1887 }
1888
1889 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1890 for (i = 0; i < q_vector->rxr_count; i++) {
1891 ring = adapter->rx_ring[r_idx];
1892 ring->total_bytes = 0;
1893 ring->total_packets = 0;
1894 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1895 r_idx + 1);
1896 }
1897
1898 /* EIAM disabled interrupts (on this vector) for us */
1899 napi_schedule(&q_vector->napi);
1900
1901 return IRQ_HANDLED;
1902 }
1903
1904 /**
1905 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1906 * @napi: napi struct with our devices info in it
1907 * @budget: amount of work driver is allowed to do this pass, in packets
1908 *
1909 * This function is optimized for cleaning one queue only on a single
1910 * q_vector!!!
1911 **/
1912 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1913 {
1914 struct ixgbe_q_vector *q_vector =
1915 container_of(napi, struct ixgbe_q_vector, napi);
1916 struct ixgbe_adapter *adapter = q_vector->adapter;
1917 struct ixgbe_ring *rx_ring = NULL;
1918 int work_done = 0;
1919 long r_idx;
1920
1921 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1922 rx_ring = adapter->rx_ring[r_idx];
1923 #ifdef CONFIG_IXGBE_DCA
1924 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1925 ixgbe_update_rx_dca(adapter, rx_ring);
1926 #endif
1927
1928 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1929
1930 /* If all Rx work done, exit the polling mode */
1931 if (work_done < budget) {
1932 napi_complete(napi);
1933 if (adapter->rx_itr_setting & 1)
1934 ixgbe_set_itr_msix(q_vector);
1935 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1936 ixgbe_irq_enable_queues(adapter,
1937 ((u64)1 << q_vector->v_idx));
1938 }
1939
1940 return work_done;
1941 }
1942
1943 /**
1944 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1945 * @napi: napi struct with our devices info in it
1946 * @budget: amount of work driver is allowed to do this pass, in packets
1947 *
1948 * This function will clean more than one rx queue associated with a
1949 * q_vector.
1950 **/
1951 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1952 {
1953 struct ixgbe_q_vector *q_vector =
1954 container_of(napi, struct ixgbe_q_vector, napi);
1955 struct ixgbe_adapter *adapter = q_vector->adapter;
1956 struct ixgbe_ring *ring = NULL;
1957 int work_done = 0, i;
1958 long r_idx;
1959 bool tx_clean_complete = true;
1960
1961 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1962 for (i = 0; i < q_vector->txr_count; i++) {
1963 ring = adapter->tx_ring[r_idx];
1964 #ifdef CONFIG_IXGBE_DCA
1965 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1966 ixgbe_update_tx_dca(adapter, ring);
1967 #endif
1968 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1969 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1970 r_idx + 1);
1971 }
1972
1973 /* attempt to distribute budget to each queue fairly, but don't allow
1974 * the budget to go below 1 because we'll exit polling */
1975 budget /= (q_vector->rxr_count ?: 1);
1976 budget = max(budget, 1);
1977 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1978 for (i = 0; i < q_vector->rxr_count; i++) {
1979 ring = adapter->rx_ring[r_idx];
1980 #ifdef CONFIG_IXGBE_DCA
1981 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1982 ixgbe_update_rx_dca(adapter, ring);
1983 #endif
1984 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1985 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1986 r_idx + 1);
1987 }
1988
1989 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1990 ring = adapter->rx_ring[r_idx];
1991 /* If all Rx work done, exit the polling mode */
1992 if (work_done < budget) {
1993 napi_complete(napi);
1994 if (adapter->rx_itr_setting & 1)
1995 ixgbe_set_itr_msix(q_vector);
1996 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1997 ixgbe_irq_enable_queues(adapter,
1998 ((u64)1 << q_vector->v_idx));
1999 return 0;
2000 }
2001
2002 return work_done;
2003 }
2004
2005 /**
2006 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2007 * @napi: napi struct with our devices info in it
2008 * @budget: amount of work driver is allowed to do this pass, in packets
2009 *
2010 * This function is optimized for cleaning one queue only on a single
2011 * q_vector!!!
2012 **/
2013 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2014 {
2015 struct ixgbe_q_vector *q_vector =
2016 container_of(napi, struct ixgbe_q_vector, napi);
2017 struct ixgbe_adapter *adapter = q_vector->adapter;
2018 struct ixgbe_ring *tx_ring = NULL;
2019 int work_done = 0;
2020 long r_idx;
2021
2022 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2023 tx_ring = adapter->tx_ring[r_idx];
2024 #ifdef CONFIG_IXGBE_DCA
2025 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2026 ixgbe_update_tx_dca(adapter, tx_ring);
2027 #endif
2028
2029 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2030 work_done = budget;
2031
2032 /* If all Tx work done, exit the polling mode */
2033 if (work_done < budget) {
2034 napi_complete(napi);
2035 if (adapter->tx_itr_setting & 1)
2036 ixgbe_set_itr_msix(q_vector);
2037 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2038 ixgbe_irq_enable_queues(adapter,
2039 ((u64)1 << q_vector->v_idx));
2040 }
2041
2042 return work_done;
2043 }
2044
2045 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2046 int r_idx)
2047 {
2048 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2049
2050 set_bit(r_idx, q_vector->rxr_idx);
2051 q_vector->rxr_count++;
2052 }
2053
2054 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2055 int t_idx)
2056 {
2057 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2058
2059 set_bit(t_idx, q_vector->txr_idx);
2060 q_vector->txr_count++;
2061 }
2062
2063 /**
2064 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2065 * @adapter: board private structure to initialize
2066 * @vectors: allotted vector count for descriptor rings
2067 *
2068 * This function maps descriptor rings to the queue-specific vectors
2069 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2070 * one vector per ring/queue, but on a constrained vector budget, we
2071 * group the rings as "efficiently" as possible. You would add new
2072 * mapping configurations in here.
2073 **/
2074 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
2075 int vectors)
2076 {
2077 int v_start = 0;
2078 int rxr_idx = 0, txr_idx = 0;
2079 int rxr_remaining = adapter->num_rx_queues;
2080 int txr_remaining = adapter->num_tx_queues;
2081 int i, j;
2082 int rqpv, tqpv;
2083 int err = 0;
2084
2085 /* No mapping required if MSI-X is disabled. */
2086 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2087 goto out;
2088
2089 /*
2090 * The ideal configuration...
2091 * We have enough vectors to map one per queue.
2092 */
2093 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2094 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2095 map_vector_to_rxq(adapter, v_start, rxr_idx);
2096
2097 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2098 map_vector_to_txq(adapter, v_start, txr_idx);
2099
2100 goto out;
2101 }
2102
2103 /*
2104 * If we don't have enough vectors for a 1-to-1
2105 * mapping, we'll have to group them so there are
2106 * multiple queues per vector.
2107 */
2108 /* Re-adjusting *qpv takes care of the remainder. */
2109 for (i = v_start; i < vectors; i++) {
2110 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
2111 for (j = 0; j < rqpv; j++) {
2112 map_vector_to_rxq(adapter, i, rxr_idx);
2113 rxr_idx++;
2114 rxr_remaining--;
2115 }
2116 }
2117 for (i = v_start; i < vectors; i++) {
2118 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
2119 for (j = 0; j < tqpv; j++) {
2120 map_vector_to_txq(adapter, i, txr_idx);
2121 txr_idx++;
2122 txr_remaining--;
2123 }
2124 }
2125
2126 out:
2127 return err;
2128 }
2129
2130 /**
2131 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2132 * @adapter: board private structure
2133 *
2134 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2135 * interrupts from the kernel.
2136 **/
2137 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2138 {
2139 struct net_device *netdev = adapter->netdev;
2140 irqreturn_t (*handler)(int, void *);
2141 int i, vector, q_vectors, err;
2142 int ri = 0, ti = 0;
2143
2144 /* Decrement for Other and TCP Timer vectors */
2145 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2146
2147 /* Map the Tx/Rx rings to the vectors we were allotted. */
2148 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
2149 if (err)
2150 goto out;
2151
2152 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2153 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2154 &ixgbe_msix_clean_many)
2155 for (vector = 0; vector < q_vectors; vector++) {
2156 handler = SET_HANDLER(adapter->q_vector[vector]);
2157
2158 if (handler == &ixgbe_msix_clean_rx) {
2159 sprintf(adapter->name[vector], "%s-%s-%d",
2160 netdev->name, "rx", ri++);
2161 } else if (handler == &ixgbe_msix_clean_tx) {
2162 sprintf(adapter->name[vector], "%s-%s-%d",
2163 netdev->name, "tx", ti++);
2164 } else
2165 sprintf(adapter->name[vector], "%s-%s-%d",
2166 netdev->name, "TxRx", vector);
2167
2168 err = request_irq(adapter->msix_entries[vector].vector,
2169 handler, 0, adapter->name[vector],
2170 adapter->q_vector[vector]);
2171 if (err) {
2172 e_err(probe, "request_irq failed for MSIX interrupt "
2173 "Error: %d\n", err);
2174 goto free_queue_irqs;
2175 }
2176 }
2177
2178 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
2179 err = request_irq(adapter->msix_entries[vector].vector,
2180 ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
2181 if (err) {
2182 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2183 goto free_queue_irqs;
2184 }
2185
2186 return 0;
2187
2188 free_queue_irqs:
2189 for (i = vector - 1; i >= 0; i--)
2190 free_irq(adapter->msix_entries[--vector].vector,
2191 adapter->q_vector[i]);
2192 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2193 pci_disable_msix(adapter->pdev);
2194 kfree(adapter->msix_entries);
2195 adapter->msix_entries = NULL;
2196 out:
2197 return err;
2198 }
2199
2200 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2201 {
2202 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2203 u8 current_itr;
2204 u32 new_itr = q_vector->eitr;
2205 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2206 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2207
2208 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2209 q_vector->tx_itr,
2210 tx_ring->total_packets,
2211 tx_ring->total_bytes);
2212 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2213 q_vector->rx_itr,
2214 rx_ring->total_packets,
2215 rx_ring->total_bytes);
2216
2217 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2218
2219 switch (current_itr) {
2220 /* counts and packets in update_itr are dependent on these numbers */
2221 case lowest_latency:
2222 new_itr = 100000;
2223 break;
2224 case low_latency:
2225 new_itr = 20000; /* aka hwitr = ~200 */
2226 break;
2227 case bulk_latency:
2228 new_itr = 8000;
2229 break;
2230 default:
2231 break;
2232 }
2233
2234 if (new_itr != q_vector->eitr) {
2235 /* do an exponential smoothing */
2236 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
2237
2238 /* save the algorithm value here, not the smoothed one */
2239 q_vector->eitr = new_itr;
2240
2241 ixgbe_write_eitr(q_vector);
2242 }
2243 }
2244
2245 /**
2246 * ixgbe_irq_enable - Enable default interrupt generation settings
2247 * @adapter: board private structure
2248 **/
2249 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2250 bool flush)
2251 {
2252 u32 mask;
2253
2254 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2255 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2256 mask |= IXGBE_EIMS_GPI_SDP0;
2257 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2258 mask |= IXGBE_EIMS_GPI_SDP1;
2259 if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2260 mask |= IXGBE_EIMS_ECC;
2261 mask |= IXGBE_EIMS_GPI_SDP1;
2262 mask |= IXGBE_EIMS_GPI_SDP2;
2263 if (adapter->num_vfs)
2264 mask |= IXGBE_EIMS_MAILBOX;
2265 }
2266 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2267 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2268 mask |= IXGBE_EIMS_FLOW_DIR;
2269
2270 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2271 if (queues)
2272 ixgbe_irq_enable_queues(adapter, ~0);
2273 if (flush)
2274 IXGBE_WRITE_FLUSH(&adapter->hw);
2275
2276 if (adapter->num_vfs > 32) {
2277 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2278 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2279 }
2280 }
2281
2282 /**
2283 * ixgbe_intr - legacy mode Interrupt Handler
2284 * @irq: interrupt number
2285 * @data: pointer to a network interface device structure
2286 **/
2287 static irqreturn_t ixgbe_intr(int irq, void *data)
2288 {
2289 struct net_device *netdev = data;
2290 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2291 struct ixgbe_hw *hw = &adapter->hw;
2292 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2293 u32 eicr;
2294
2295 /*
2296 * Workaround for silicon errata on 82598. Mask the interrupts
2297 * before the read of EICR.
2298 */
2299 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2300
2301 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2302 * therefore no explict interrupt disable is necessary */
2303 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2304 if (!eicr) {
2305 /*
2306 * shared interrupt alert!
2307 * make sure interrupts are enabled because the read will
2308 * have disabled interrupts due to EIAM
2309 * finish the workaround of silicon errata on 82598. Unmask
2310 * the interrupt that we masked before the EICR read.
2311 */
2312 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2313 ixgbe_irq_enable(adapter, true, true);
2314 return IRQ_NONE; /* Not our interrupt */
2315 }
2316
2317 if (eicr & IXGBE_EICR_LSC)
2318 ixgbe_check_lsc(adapter);
2319
2320 if (hw->mac.type == ixgbe_mac_82599EB)
2321 ixgbe_check_sfp_event(adapter, eicr);
2322
2323 ixgbe_check_fan_failure(adapter, eicr);
2324 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2325 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC)))
2326 schedule_work(&adapter->check_overtemp_task);
2327
2328 if (napi_schedule_prep(&(q_vector->napi))) {
2329 adapter->tx_ring[0]->total_packets = 0;
2330 adapter->tx_ring[0]->total_bytes = 0;
2331 adapter->rx_ring[0]->total_packets = 0;
2332 adapter->rx_ring[0]->total_bytes = 0;
2333 /* would disable interrupts here but EIAM disabled it */
2334 __napi_schedule(&(q_vector->napi));
2335 }
2336
2337 /*
2338 * re-enable link(maybe) and non-queue interrupts, no flush.
2339 * ixgbe_poll will re-enable the queue interrupts
2340 */
2341
2342 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2343 ixgbe_irq_enable(adapter, false, false);
2344
2345 return IRQ_HANDLED;
2346 }
2347
2348 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2349 {
2350 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2351
2352 for (i = 0; i < q_vectors; i++) {
2353 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2354 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2355 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2356 q_vector->rxr_count = 0;
2357 q_vector->txr_count = 0;
2358 }
2359 }
2360
2361 /**
2362 * ixgbe_request_irq - initialize interrupts
2363 * @adapter: board private structure
2364 *
2365 * Attempts to configure interrupts using the best available
2366 * capabilities of the hardware and kernel.
2367 **/
2368 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2369 {
2370 struct net_device *netdev = adapter->netdev;
2371 int err;
2372
2373 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2374 err = ixgbe_request_msix_irqs(adapter);
2375 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2376 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2377 netdev->name, netdev);
2378 } else {
2379 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2380 netdev->name, netdev);
2381 }
2382
2383 if (err)
2384 e_err(probe, "request_irq failed, Error %d\n", err);
2385
2386 return err;
2387 }
2388
2389 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2390 {
2391 struct net_device *netdev = adapter->netdev;
2392
2393 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2394 int i, q_vectors;
2395
2396 q_vectors = adapter->num_msix_vectors;
2397
2398 i = q_vectors - 1;
2399 free_irq(adapter->msix_entries[i].vector, netdev);
2400
2401 i--;
2402 for (; i >= 0; i--) {
2403 free_irq(adapter->msix_entries[i].vector,
2404 adapter->q_vector[i]);
2405 }
2406
2407 ixgbe_reset_q_vectors(adapter);
2408 } else {
2409 free_irq(adapter->pdev->irq, netdev);
2410 }
2411 }
2412
2413 /**
2414 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2415 * @adapter: board private structure
2416 **/
2417 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2418 {
2419 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2420 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2421 } else {
2422 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2424 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2425 if (adapter->num_vfs > 32)
2426 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2427 }
2428 IXGBE_WRITE_FLUSH(&adapter->hw);
2429 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2430 int i;
2431 for (i = 0; i < adapter->num_msix_vectors; i++)
2432 synchronize_irq(adapter->msix_entries[i].vector);
2433 } else {
2434 synchronize_irq(adapter->pdev->irq);
2435 }
2436 }
2437
2438 /**
2439 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2440 *
2441 **/
2442 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2443 {
2444 struct ixgbe_hw *hw = &adapter->hw;
2445
2446 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2447 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2448
2449 ixgbe_set_ivar(adapter, 0, 0, 0);
2450 ixgbe_set_ivar(adapter, 1, 0, 0);
2451
2452 map_vector_to_rxq(adapter, 0, 0);
2453 map_vector_to_txq(adapter, 0, 0);
2454
2455 e_info(hw, "Legacy interrupt IVAR setup done\n");
2456 }
2457
2458 /**
2459 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2460 * @adapter: board private structure
2461 * @ring: structure containing ring specific data
2462 *
2463 * Configure the Tx descriptor ring after a reset.
2464 **/
2465 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2466 struct ixgbe_ring *ring)
2467 {
2468 struct ixgbe_hw *hw = &adapter->hw;
2469 u64 tdba = ring->dma;
2470 int wait_loop = 10;
2471 u32 txdctl;
2472 u16 reg_idx = ring->reg_idx;
2473
2474 /* disable queue to avoid issues while updating state */
2475 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2476 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2477 txdctl & ~IXGBE_TXDCTL_ENABLE);
2478 IXGBE_WRITE_FLUSH(hw);
2479
2480 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2481 (tdba & DMA_BIT_MASK(32)));
2482 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2483 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2484 ring->count * sizeof(union ixgbe_adv_tx_desc));
2485 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2486 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2487 ring->head = IXGBE_TDH(reg_idx);
2488 ring->tail = IXGBE_TDT(reg_idx);
2489
2490 /* configure fetching thresholds */
2491 if (adapter->rx_itr_setting == 0) {
2492 /* cannot set wthresh when itr==0 */
2493 txdctl &= ~0x007F0000;
2494 } else {
2495 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2496 txdctl |= (8 << 16);
2497 }
2498 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2499 /* PThresh workaround for Tx hang with DFP enabled. */
2500 txdctl |= 32;
2501 }
2502
2503 /* reinitialize flowdirector state */
2504 set_bit(__IXGBE_FDIR_INIT_DONE, &ring->reinit_state);
2505
2506 /* enable queue */
2507 txdctl |= IXGBE_TXDCTL_ENABLE;
2508 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2509
2510 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2511 if (hw->mac.type == ixgbe_mac_82598EB &&
2512 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2513 return;
2514
2515 /* poll to verify queue is enabled */
2516 do {
2517 msleep(1);
2518 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2519 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2520 if (!wait_loop)
2521 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2522 }
2523
2524 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2525 {
2526 struct ixgbe_hw *hw = &adapter->hw;
2527 u32 rttdcs;
2528 u32 mask;
2529
2530 if (hw->mac.type == ixgbe_mac_82598EB)
2531 return;
2532
2533 /* disable the arbiter while setting MTQC */
2534 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2535 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2536 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2537
2538 /* set transmit pool layout */
2539 mask = (IXGBE_FLAG_SRIOV_ENABLED | IXGBE_FLAG_DCB_ENABLED);
2540 switch (adapter->flags & mask) {
2541
2542 case (IXGBE_FLAG_SRIOV_ENABLED):
2543 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2544 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2545 break;
2546
2547 case (IXGBE_FLAG_DCB_ENABLED):
2548 /* We enable 8 traffic classes, DCB only */
2549 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2550 (IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ));
2551 break;
2552
2553 default:
2554 IXGBE_WRITE_REG(hw, IXGBE_MTQC, IXGBE_MTQC_64Q_1PB);
2555 break;
2556 }
2557
2558 /* re-enable the arbiter */
2559 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2560 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2561 }
2562
2563 /**
2564 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2565 * @adapter: board private structure
2566 *
2567 * Configure the Tx unit of the MAC after a reset.
2568 **/
2569 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2570 {
2571 struct ixgbe_hw *hw = &adapter->hw;
2572 u32 dmatxctl;
2573 u32 i;
2574
2575 ixgbe_setup_mtqc(adapter);
2576
2577 if (hw->mac.type != ixgbe_mac_82598EB) {
2578 /* DMATXCTL.EN must be before Tx queues are enabled */
2579 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2580 dmatxctl |= IXGBE_DMATXCTL_TE;
2581 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2582 }
2583
2584 /* Setup the HW Tx Head and Tail descriptor pointers */
2585 for (i = 0; i < adapter->num_tx_queues; i++)
2586 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2587 }
2588
2589 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2590
2591 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2592 struct ixgbe_ring *rx_ring)
2593 {
2594 u32 srrctl;
2595 int index;
2596 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2597
2598 index = rx_ring->reg_idx;
2599 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2600 unsigned long mask;
2601 mask = (unsigned long) feature[RING_F_RSS].mask;
2602 index = index & mask;
2603 }
2604 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
2605
2606 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2607 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2608 if (adapter->num_vfs)
2609 srrctl |= IXGBE_SRRCTL_DROP_EN;
2610
2611 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2612 IXGBE_SRRCTL_BSIZEHDR_MASK;
2613
2614 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2615 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2616 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2617 #else
2618 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2619 #endif
2620 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2621 } else {
2622 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2623 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2624 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2625 }
2626
2627 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
2628 }
2629
2630 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2631 {
2632 struct ixgbe_hw *hw = &adapter->hw;
2633 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2634 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2635 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2636 u32 mrqc = 0, reta = 0;
2637 u32 rxcsum;
2638 int i, j;
2639 int mask;
2640
2641 /* Fill out hash function seeds */
2642 for (i = 0; i < 10; i++)
2643 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2644
2645 /* Fill out redirection table */
2646 for (i = 0, j = 0; i < 128; i++, j++) {
2647 if (j == adapter->ring_feature[RING_F_RSS].indices)
2648 j = 0;
2649 /* reta = 4-byte sliding window of
2650 * 0x00..(indices-1)(indices-1)00..etc. */
2651 reta = (reta << 8) | (j * 0x11);
2652 if ((i & 3) == 3)
2653 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2654 }
2655
2656 /* Disable indicating checksum in descriptor, enables RSS hash */
2657 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2658 rxcsum |= IXGBE_RXCSUM_PCSD;
2659 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2660
2661 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
2662 mask = adapter->flags & IXGBE_FLAG_RSS_ENABLED;
2663 else
2664 mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2665 #ifdef CONFIG_IXGBE_DCB
2666 | IXGBE_FLAG_DCB_ENABLED
2667 #endif
2668 | IXGBE_FLAG_SRIOV_ENABLED
2669 );
2670
2671 switch (mask) {
2672 case (IXGBE_FLAG_RSS_ENABLED):
2673 mrqc = IXGBE_MRQC_RSSEN;
2674 break;
2675 case (IXGBE_FLAG_SRIOV_ENABLED):
2676 mrqc = IXGBE_MRQC_VMDQEN;
2677 break;
2678 #ifdef CONFIG_IXGBE_DCB
2679 case (IXGBE_FLAG_DCB_ENABLED):
2680 mrqc = IXGBE_MRQC_RT8TCEN;
2681 break;
2682 #endif /* CONFIG_IXGBE_DCB */
2683 default:
2684 break;
2685 }
2686
2687 /* Perform hash on these packet types */
2688 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2689 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2690 | IXGBE_MRQC_RSS_FIELD_IPV6
2691 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2692
2693 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2694 }
2695
2696 /**
2697 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2698 * @adapter: address of board private structure
2699 * @index: index of ring to set
2700 **/
2701 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2702 struct ixgbe_ring *ring)
2703 {
2704 struct ixgbe_hw *hw = &adapter->hw;
2705 u32 rscctrl;
2706 int rx_buf_len;
2707 u16 reg_idx = ring->reg_idx;
2708
2709 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
2710 return;
2711
2712 rx_buf_len = ring->rx_buf_len;
2713 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2714 rscctrl |= IXGBE_RSCCTL_RSCEN;
2715 /*
2716 * we must limit the number of descriptors so that the
2717 * total size of max desc * buf_len is not greater
2718 * than 65535
2719 */
2720 if (ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2721 #if (MAX_SKB_FRAGS > 16)
2722 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2723 #elif (MAX_SKB_FRAGS > 8)
2724 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2725 #elif (MAX_SKB_FRAGS > 4)
2726 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2727 #else
2728 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2729 #endif
2730 } else {
2731 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2732 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2733 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2734 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2735 else
2736 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2737 }
2738 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2739 }
2740
2741 /**
2742 * ixgbe_set_uta - Set unicast filter table address
2743 * @adapter: board private structure
2744 *
2745 * The unicast table address is a register array of 32-bit registers.
2746 * The table is meant to be used in a way similar to how the MTA is used
2747 * however due to certain limitations in the hardware it is necessary to
2748 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2749 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
2750 **/
2751 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
2752 {
2753 struct ixgbe_hw *hw = &adapter->hw;
2754 int i;
2755
2756 /* The UTA table only exists on 82599 hardware and newer */
2757 if (hw->mac.type < ixgbe_mac_82599EB)
2758 return;
2759
2760 /* we only need to do this if VMDq is enabled */
2761 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2762 return;
2763
2764 for (i = 0; i < 128; i++)
2765 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
2766 }
2767
2768 #define IXGBE_MAX_RX_DESC_POLL 10
2769 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2770 struct ixgbe_ring *ring)
2771 {
2772 struct ixgbe_hw *hw = &adapter->hw;
2773 int reg_idx = ring->reg_idx;
2774 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
2775 u32 rxdctl;
2776
2777 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2778 if (hw->mac.type == ixgbe_mac_82598EB &&
2779 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2780 return;
2781
2782 do {
2783 msleep(1);
2784 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2785 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
2786
2787 if (!wait_loop) {
2788 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
2789 "the polling period\n", reg_idx);
2790 }
2791 }
2792
2793 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *ring)
2795 {
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u64 rdba = ring->dma;
2798 u32 rxdctl;
2799 u16 reg_idx = ring->reg_idx;
2800
2801 /* disable queue to avoid issues while updating state */
2802 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
2803 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx),
2804 rxdctl & ~IXGBE_RXDCTL_ENABLE);
2805 IXGBE_WRITE_FLUSH(hw);
2806
2807 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
2808 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
2809 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
2810 ring->count * sizeof(union ixgbe_adv_rx_desc));
2811 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
2812 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
2813 ring->head = IXGBE_RDH(reg_idx);
2814 ring->tail = IXGBE_RDT(reg_idx);
2815
2816 ixgbe_configure_srrctl(adapter, ring);
2817 ixgbe_configure_rscctl(adapter, ring);
2818
2819 if (hw->mac.type == ixgbe_mac_82598EB) {
2820 /*
2821 * enable cache line friendly hardware writes:
2822 * PTHRESH=32 descriptors (half the internal cache),
2823 * this also removes ugly rx_no_buffer_count increment
2824 * HTHRESH=4 descriptors (to minimize latency on fetch)
2825 * WTHRESH=8 burst writeback up to two cache lines
2826 */
2827 rxdctl &= ~0x3FFFFF;
2828 rxdctl |= 0x080420;
2829 }
2830
2831 /* enable receive descriptor ring */
2832 rxdctl |= IXGBE_RXDCTL_ENABLE;
2833 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
2834
2835 ixgbe_rx_desc_queue_enable(adapter, ring);
2836 ixgbe_alloc_rx_buffers(adapter, ring, IXGBE_DESC_UNUSED(ring));
2837 }
2838
2839 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
2840 {
2841 struct ixgbe_hw *hw = &adapter->hw;
2842 int p;
2843
2844 /* PSRTYPE must be initialized in non 82598 adapters */
2845 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2846 IXGBE_PSRTYPE_UDPHDR |
2847 IXGBE_PSRTYPE_IPV4HDR |
2848 IXGBE_PSRTYPE_L2HDR |
2849 IXGBE_PSRTYPE_IPV6HDR;
2850
2851 if (hw->mac.type == ixgbe_mac_82598EB)
2852 return;
2853
2854 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
2855 psrtype |= (adapter->num_rx_queues_per_pool << 29);
2856
2857 for (p = 0; p < adapter->num_rx_pools; p++)
2858 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
2859 psrtype);
2860 }
2861
2862 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
2863 {
2864 struct ixgbe_hw *hw = &adapter->hw;
2865 u32 gcr_ext;
2866 u32 vt_reg_bits;
2867 u32 reg_offset, vf_shift;
2868 u32 vmdctl;
2869
2870 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
2871 return;
2872
2873 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
2874 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
2875 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
2876 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
2877
2878 vf_shift = adapter->num_vfs % 32;
2879 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
2880
2881 /* Enable only the PF's pool for Tx/Rx */
2882 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
2883 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
2884 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
2885 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
2886 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2887
2888 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
2889 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
2890
2891 /*
2892 * Set up VF register offsets for selected VT Mode,
2893 * i.e. 32 or 64 VFs for SR-IOV
2894 */
2895 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
2896 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
2897 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
2898 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
2899
2900 /* enable Tx loopback for VF/PF communication */
2901 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
2902 }
2903
2904 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
2905 {
2906 struct ixgbe_hw *hw = &adapter->hw;
2907 struct net_device *netdev = adapter->netdev;
2908 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2909 int rx_buf_len;
2910 struct ixgbe_ring *rx_ring;
2911 int i;
2912 u32 mhadd, hlreg0;
2913
2914 /* Decide whether to use packet split mode or not */
2915 /* Do not use packet split if we're in SR-IOV Mode */
2916 if (!adapter->num_vfs)
2917 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
2918
2919 /* Set the RX buffer length according to the mode */
2920 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2921 rx_buf_len = IXGBE_RX_HDR_SIZE;
2922 } else {
2923 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2924 (netdev->mtu <= ETH_DATA_LEN))
2925 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2926 else
2927 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
2928 }
2929
2930 #ifdef IXGBE_FCOE
2931 /* adjust max frame to be able to do baby jumbo for FCoE */
2932 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
2933 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2934 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2935
2936 #endif /* IXGBE_FCOE */
2937 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2938 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2939 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2940 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2941
2942 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2943 }
2944
2945 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2946 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
2947 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2948 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2949
2950 /*
2951 * Setup the HW Rx Head and Tail Descriptor Pointers and
2952 * the Base and Length of the Rx Descriptor Ring
2953 */
2954 for (i = 0; i < adapter->num_rx_queues; i++) {
2955 rx_ring = adapter->rx_ring[i];
2956 rx_ring->rx_buf_len = rx_buf_len;
2957
2958 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2959 rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2960 else
2961 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2962
2963 #ifdef IXGBE_FCOE
2964 if (netdev->features & NETIF_F_FCOE_MTU) {
2965 struct ixgbe_ring_feature *f;
2966 f = &adapter->ring_feature[RING_F_FCOE];
2967 if ((i >= f->mask) && (i < f->mask + f->indices)) {
2968 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2969 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2970 rx_ring->rx_buf_len =
2971 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2972 }
2973 }
2974 #endif /* IXGBE_FCOE */
2975 }
2976
2977 }
2978
2979 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
2980 {
2981 struct ixgbe_hw *hw = &adapter->hw;
2982 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2983
2984 switch (hw->mac.type) {
2985 case ixgbe_mac_82598EB:
2986 /*
2987 * For VMDq support of different descriptor types or
2988 * buffer sizes through the use of multiple SRRCTL
2989 * registers, RDRXCTL.MVMEN must be set to 1
2990 *
2991 * also, the manual doesn't mention it clearly but DCA hints
2992 * will only use queue 0's tags unless this bit is set. Side
2993 * effects of setting this bit are only that SRRCTL must be
2994 * fully programmed [0..15]
2995 */
2996 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2997 break;
2998 case ixgbe_mac_82599EB:
2999 /* Disable RSC for ACK packets */
3000 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3001 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3002 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3003 /* hardware requires some bits to be set by default */
3004 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3005 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3006 break;
3007 default:
3008 /* We should do nothing since we don't know this hardware */
3009 return;
3010 }
3011
3012 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3013 }
3014
3015 /**
3016 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3017 * @adapter: board private structure
3018 *
3019 * Configure the Rx unit of the MAC after a reset.
3020 **/
3021 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3022 {
3023 struct ixgbe_hw *hw = &adapter->hw;
3024 int i;
3025 u32 rxctrl;
3026
3027 /* disable receives while setting up the descriptors */
3028 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3029 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3030
3031 ixgbe_setup_psrtype(adapter);
3032 ixgbe_setup_rdrxctl(adapter);
3033
3034 /* Program registers for the distribution of queues */
3035 ixgbe_setup_mrqc(adapter);
3036
3037 ixgbe_set_uta(adapter);
3038
3039 /* set_rx_buffer_len must be called before ring initialization */
3040 ixgbe_set_rx_buffer_len(adapter);
3041
3042 /*
3043 * Setup the HW Rx Head and Tail Descriptor Pointers and
3044 * the Base and Length of the Rx Descriptor Ring
3045 */
3046 for (i = 0; i < adapter->num_rx_queues; i++)
3047 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3048
3049 /* disable drop enable for 82598 parts */
3050 if (hw->mac.type == ixgbe_mac_82598EB)
3051 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3052
3053 /* enable all receives */
3054 rxctrl |= IXGBE_RXCTRL_RXEN;
3055 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3056 }
3057
3058 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3059 {
3060 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3061 struct ixgbe_hw *hw = &adapter->hw;
3062 int pool_ndx = adapter->num_vfs;
3063
3064 /* add VID to filter table */
3065 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3066 set_bit(vid, adapter->active_vlans);
3067 }
3068
3069 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3070 {
3071 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3072 struct ixgbe_hw *hw = &adapter->hw;
3073 int pool_ndx = adapter->num_vfs;
3074
3075 /* remove VID from filter table */
3076 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3077 clear_bit(vid, adapter->active_vlans);
3078 }
3079
3080 /**
3081 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3082 * @adapter: driver data
3083 */
3084 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3085 {
3086 struct ixgbe_hw *hw = &adapter->hw;
3087 u32 vlnctrl;
3088
3089 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3090 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3091 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3092 }
3093
3094 /**
3095 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3096 * @adapter: driver data
3097 */
3098 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3099 {
3100 struct ixgbe_hw *hw = &adapter->hw;
3101 u32 vlnctrl;
3102
3103 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3104 vlnctrl |= IXGBE_VLNCTRL_VFE;
3105 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3106 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3107 }
3108
3109 /**
3110 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3111 * @adapter: driver data
3112 */
3113 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3114 {
3115 struct ixgbe_hw *hw = &adapter->hw;
3116 u32 vlnctrl;
3117 int i, j;
3118
3119 switch (hw->mac.type) {
3120 case ixgbe_mac_82598EB:
3121 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3122 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3123 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3124 break;
3125 case ixgbe_mac_82599EB:
3126 for (i = 0; i < adapter->num_rx_queues; i++) {
3127 j = adapter->rx_ring[i]->reg_idx;
3128 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3129 vlnctrl &= ~IXGBE_RXDCTL_VME;
3130 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3131 }
3132 break;
3133 default:
3134 break;
3135 }
3136 }
3137
3138 /**
3139 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3140 * @adapter: driver data
3141 */
3142 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3143 {
3144 struct ixgbe_hw *hw = &adapter->hw;
3145 u32 vlnctrl;
3146 int i, j;
3147
3148 switch (hw->mac.type) {
3149 case ixgbe_mac_82598EB:
3150 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3151 vlnctrl |= IXGBE_VLNCTRL_VME;
3152 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3153 break;
3154 case ixgbe_mac_82599EB:
3155 for (i = 0; i < adapter->num_rx_queues; i++) {
3156 j = adapter->rx_ring[i]->reg_idx;
3157 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3158 vlnctrl |= IXGBE_RXDCTL_VME;
3159 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3160 }
3161 break;
3162 default:
3163 break;
3164 }
3165 }
3166
3167 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3168 {
3169 u16 vid;
3170
3171 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3172
3173 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3174 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3175 }
3176
3177 /**
3178 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3179 * @netdev: network interface device structure
3180 *
3181 * Writes unicast address list to the RAR table.
3182 * Returns: -ENOMEM on failure/insufficient address space
3183 * 0 on no addresses written
3184 * X on writing X addresses to the RAR table
3185 **/
3186 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3187 {
3188 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3189 struct ixgbe_hw *hw = &adapter->hw;
3190 unsigned int vfn = adapter->num_vfs;
3191 unsigned int rar_entries = hw->mac.num_rar_entries - (vfn + 1);
3192 int count = 0;
3193
3194 /* return ENOMEM indicating insufficient memory for addresses */
3195 if (netdev_uc_count(netdev) > rar_entries)
3196 return -ENOMEM;
3197
3198 if (!netdev_uc_empty(netdev) && rar_entries) {
3199 struct netdev_hw_addr *ha;
3200 /* return error if we do not support writing to RAR table */
3201 if (!hw->mac.ops.set_rar)
3202 return -ENOMEM;
3203
3204 netdev_for_each_uc_addr(ha, netdev) {
3205 if (!rar_entries)
3206 break;
3207 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3208 vfn, IXGBE_RAH_AV);
3209 count++;
3210 }
3211 }
3212 /* write the addresses in reverse order to avoid write combining */
3213 for (; rar_entries > 0 ; rar_entries--)
3214 hw->mac.ops.clear_rar(hw, rar_entries);
3215
3216 return count;
3217 }
3218
3219 /**
3220 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3221 * @netdev: network interface device structure
3222 *
3223 * The set_rx_method entry point is called whenever the unicast/multicast
3224 * address list or the network interface flags are updated. This routine is
3225 * responsible for configuring the hardware for proper unicast, multicast and
3226 * promiscuous mode.
3227 **/
3228 void ixgbe_set_rx_mode(struct net_device *netdev)
3229 {
3230 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3231 struct ixgbe_hw *hw = &adapter->hw;
3232 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3233 int count;
3234
3235 /* Check for Promiscuous and All Multicast modes */
3236
3237 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3238
3239 /* set all bits that we expect to always be set */
3240 fctrl |= IXGBE_FCTRL_BAM;
3241 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3242 fctrl |= IXGBE_FCTRL_PMCF;
3243
3244 /* clear the bits we are changing the status of */
3245 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3246
3247 if (netdev->flags & IFF_PROMISC) {
3248 hw->addr_ctrl.user_set_promisc = true;
3249 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3250 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3251 /* don't hardware filter vlans in promisc mode */
3252 ixgbe_vlan_filter_disable(adapter);
3253 } else {
3254 if (netdev->flags & IFF_ALLMULTI) {
3255 fctrl |= IXGBE_FCTRL_MPE;
3256 vmolr |= IXGBE_VMOLR_MPE;
3257 } else {
3258 /*
3259 * Write addresses to the MTA, if the attempt fails
3260 * then we should just turn on promiscous mode so
3261 * that we can at least receive multicast traffic
3262 */
3263 hw->mac.ops.update_mc_addr_list(hw, netdev);
3264 vmolr |= IXGBE_VMOLR_ROMPE;
3265 }
3266 ixgbe_vlan_filter_enable(adapter);
3267 hw->addr_ctrl.user_set_promisc = false;
3268 /*
3269 * Write addresses to available RAR registers, if there is not
3270 * sufficient space to store all the addresses then enable
3271 * unicast promiscous mode
3272 */
3273 count = ixgbe_write_uc_addr_list(netdev);
3274 if (count < 0) {
3275 fctrl |= IXGBE_FCTRL_UPE;
3276 vmolr |= IXGBE_VMOLR_ROPE;
3277 }
3278 }
3279
3280 if (adapter->num_vfs) {
3281 ixgbe_restore_vf_multicasts(adapter);
3282 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3283 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3284 IXGBE_VMOLR_ROPE);
3285 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3286 }
3287
3288 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3289
3290 if (netdev->features & NETIF_F_HW_VLAN_RX)
3291 ixgbe_vlan_strip_enable(adapter);
3292 else
3293 ixgbe_vlan_strip_disable(adapter);
3294 }
3295
3296 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3297 {
3298 int q_idx;
3299 struct ixgbe_q_vector *q_vector;
3300 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3301
3302 /* legacy and MSI only use one vector */
3303 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3304 q_vectors = 1;
3305
3306 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3307 struct napi_struct *napi;
3308 q_vector = adapter->q_vector[q_idx];
3309 napi = &q_vector->napi;
3310 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3311 if (!q_vector->rxr_count || !q_vector->txr_count) {
3312 if (q_vector->txr_count == 1)
3313 napi->poll = &ixgbe_clean_txonly;
3314 else if (q_vector->rxr_count == 1)
3315 napi->poll = &ixgbe_clean_rxonly;
3316 }
3317 }
3318
3319 napi_enable(napi);
3320 }
3321 }
3322
3323 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3324 {
3325 int q_idx;
3326 struct ixgbe_q_vector *q_vector;
3327 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3328
3329 /* legacy and MSI only use one vector */
3330 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3331 q_vectors = 1;
3332
3333 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3334 q_vector = adapter->q_vector[q_idx];
3335 napi_disable(&q_vector->napi);
3336 }
3337 }
3338
3339 #ifdef CONFIG_IXGBE_DCB
3340 /*
3341 * ixgbe_configure_dcb - Configure DCB hardware
3342 * @adapter: ixgbe adapter struct
3343 *
3344 * This is called by the driver on open to configure the DCB hardware.
3345 * This is also called by the gennetlink interface when reconfiguring
3346 * the DCB state.
3347 */
3348 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3349 {
3350 struct ixgbe_hw *hw = &adapter->hw;
3351 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3352 u32 txdctl;
3353 int i, j;
3354
3355 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3357 netif_set_gso_max_size(adapter->netdev, 65536);
3358 return;
3359 }
3360
3361 if (hw->mac.type == ixgbe_mac_82598EB)
3362 netif_set_gso_max_size(adapter->netdev, 32768);
3363
3364 #ifdef CONFIG_FCOE
3365 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3366 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3367 #endif
3368
3369 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
3370 DCB_TX_CONFIG);
3371 ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, max_frame,
3372 DCB_RX_CONFIG);
3373
3374 /* reconfigure the hardware */
3375 ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
3376
3377 for (i = 0; i < adapter->num_tx_queues; i++) {
3378 j = adapter->tx_ring[i]->reg_idx;
3379 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3380 /* PThresh workaround for Tx hang with DFP enabled. */
3381 txdctl |= 32;
3382 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
3383 }
3384 /* Enable VLAN tag insert/strip */
3385 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3386
3387 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3388 }
3389
3390 #endif
3391 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3392 {
3393 struct net_device *netdev = adapter->netdev;
3394 struct ixgbe_hw *hw = &adapter->hw;
3395 int i;
3396
3397 #ifdef CONFIG_IXGBE_DCB
3398 ixgbe_configure_dcb(adapter);
3399 #endif
3400
3401 ixgbe_set_rx_mode(netdev);
3402 ixgbe_restore_vlan(adapter);
3403
3404 #ifdef IXGBE_FCOE
3405 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3406 ixgbe_configure_fcoe(adapter);
3407
3408 #endif /* IXGBE_FCOE */
3409 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3410 for (i = 0; i < adapter->num_tx_queues; i++)
3411 adapter->tx_ring[i]->atr_sample_rate =
3412 adapter->atr_sample_rate;
3413 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3414 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3415 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
3416 }
3417 ixgbe_configure_virtualization(adapter);
3418
3419 ixgbe_configure_tx(adapter);
3420 ixgbe_configure_rx(adapter);
3421 }
3422
3423 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3424 {
3425 switch (hw->phy.type) {
3426 case ixgbe_phy_sfp_avago:
3427 case ixgbe_phy_sfp_ftl:
3428 case ixgbe_phy_sfp_intel:
3429 case ixgbe_phy_sfp_unknown:
3430 case ixgbe_phy_sfp_passive_tyco:
3431 case ixgbe_phy_sfp_passive_unknown:
3432 case ixgbe_phy_sfp_active_unknown:
3433 case ixgbe_phy_sfp_ftl_active:
3434 return true;
3435 default:
3436 return false;
3437 }
3438 }
3439
3440 /**
3441 * ixgbe_sfp_link_config - set up SFP+ link
3442 * @adapter: pointer to private adapter struct
3443 **/
3444 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3445 {
3446 struct ixgbe_hw *hw = &adapter->hw;
3447
3448 if (hw->phy.multispeed_fiber) {
3449 /*
3450 * In multispeed fiber setups, the device may not have
3451 * had a physical connection when the driver loaded.
3452 * If that's the case, the initial link configuration
3453 * couldn't get the MAC into 10G or 1G mode, so we'll
3454 * never have a link status change interrupt fire.
3455 * We need to try and force an autonegotiation
3456 * session, then bring up link.
3457 */
3458 hw->mac.ops.setup_sfp(hw);
3459 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
3460 schedule_work(&adapter->multispeed_fiber_task);
3461 } else {
3462 /*
3463 * Direct Attach Cu and non-multispeed fiber modules
3464 * still need to be configured properly prior to
3465 * attempting link.
3466 */
3467 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
3468 schedule_work(&adapter->sfp_config_module_task);
3469 }
3470 }
3471
3472 /**
3473 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3474 * @hw: pointer to private hardware struct
3475 *
3476 * Returns 0 on success, negative on failure
3477 **/
3478 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3479 {
3480 u32 autoneg;
3481 bool negotiation, link_up = false;
3482 u32 ret = IXGBE_ERR_LINK_SETUP;
3483
3484 if (hw->mac.ops.check_link)
3485 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3486
3487 if (ret)
3488 goto link_cfg_out;
3489
3490 if (hw->mac.ops.get_link_capabilities)
3491 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3492 &negotiation);
3493 if (ret)
3494 goto link_cfg_out;
3495
3496 if (hw->mac.ops.setup_link)
3497 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3498 link_cfg_out:
3499 return ret;
3500 }
3501
3502 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3503 {
3504 struct ixgbe_hw *hw = &adapter->hw;
3505 u32 gpie = 0;
3506
3507 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3508 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3509 IXGBE_GPIE_OCD;
3510 gpie |= IXGBE_GPIE_EIAME;
3511 /*
3512 * use EIAM to auto-mask when MSI-X interrupt is asserted
3513 * this saves a register write for every interrupt
3514 */
3515 switch (hw->mac.type) {
3516 case ixgbe_mac_82598EB:
3517 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3518 break;
3519 default:
3520 case ixgbe_mac_82599EB:
3521 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3522 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3523 break;
3524 }
3525 } else {
3526 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3527 * specifically only auto mask tx and rx interrupts */
3528 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3529 }
3530
3531 /* XXX: to interrupt immediately for EICS writes, enable this */
3532 /* gpie |= IXGBE_GPIE_EIMEN; */
3533
3534 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3535 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3536 gpie |= IXGBE_GPIE_VTMODE_64;
3537 }
3538
3539 /* Enable fan failure interrupt */
3540 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3541 gpie |= IXGBE_SDP1_GPIEN;
3542
3543 if (hw->mac.type == ixgbe_mac_82599EB)
3544 gpie |= IXGBE_SDP1_GPIEN;
3545 gpie |= IXGBE_SDP2_GPIEN;
3546
3547 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3548 }
3549
3550 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3551 {
3552 struct ixgbe_hw *hw = &adapter->hw;
3553 int err;
3554 u32 ctrl_ext;
3555
3556 ixgbe_get_hw_control(adapter);
3557 ixgbe_setup_gpie(adapter);
3558
3559 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3560 ixgbe_configure_msix(adapter);
3561 else
3562 ixgbe_configure_msi_and_legacy(adapter);
3563
3564 /* enable the optics */
3565 if (hw->phy.multispeed_fiber)
3566 hw->mac.ops.enable_tx_laser(hw);
3567
3568 clear_bit(__IXGBE_DOWN, &adapter->state);
3569 ixgbe_napi_enable_all(adapter);
3570
3571 /* clear any pending interrupts, may auto mask */
3572 IXGBE_READ_REG(hw, IXGBE_EICR);
3573 ixgbe_irq_enable(adapter, true, true);
3574
3575 /*
3576 * If this adapter has a fan, check to see if we had a failure
3577 * before we enabled the interrupt.
3578 */
3579 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3580 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3581 if (esdp & IXGBE_ESDP_SDP1)
3582 e_crit(drv, "Fan has stopped, replace the adapter\n");
3583 }
3584
3585 /*
3586 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3587 * arrived before interrupts were enabled but after probe. Such
3588 * devices wouldn't have their type identified yet. We need to
3589 * kick off the SFP+ module setup first, then try to bring up link.
3590 * If we're not hot-pluggable SFP+, we just need to configure link
3591 * and bring it up.
3592 */
3593 if (hw->phy.type == ixgbe_phy_unknown) {
3594 err = hw->phy.ops.identify(hw);
3595 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3596 /*
3597 * Take the device down and schedule the sfp tasklet
3598 * which will unregister_netdev and log it.
3599 */
3600 ixgbe_down(adapter);
3601 schedule_work(&adapter->sfp_config_module_task);
3602 return err;
3603 }
3604 }
3605
3606 if (ixgbe_is_sfp(hw)) {
3607 ixgbe_sfp_link_config(adapter);
3608 } else {
3609 err = ixgbe_non_sfp_link_config(hw);
3610 if (err)
3611 e_err(probe, "link_config FAILED %d\n", err);
3612 }
3613
3614 /* enable transmits */
3615 netif_tx_start_all_queues(adapter->netdev);
3616
3617 /* bring the link up in the watchdog, this could race with our first
3618 * link up interrupt but shouldn't be a problem */
3619 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3620 adapter->link_check_timeout = jiffies;
3621 mod_timer(&adapter->watchdog_timer, jiffies);
3622
3623 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3624 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3625 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3626 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3627
3628 return 0;
3629 }
3630
3631 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3632 {
3633 WARN_ON(in_interrupt());
3634 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3635 msleep(1);
3636 ixgbe_down(adapter);
3637 /*
3638 * If SR-IOV enabled then wait a bit before bringing the adapter
3639 * back up to give the VFs time to respond to the reset. The
3640 * two second wait is based upon the watchdog timer cycle in
3641 * the VF driver.
3642 */
3643 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3644 msleep(2000);
3645 ixgbe_up(adapter);
3646 clear_bit(__IXGBE_RESETTING, &adapter->state);
3647 }
3648
3649 int ixgbe_up(struct ixgbe_adapter *adapter)
3650 {
3651 /* hardware has been reset, we need to reload some things */
3652 ixgbe_configure(adapter);
3653
3654 return ixgbe_up_complete(adapter);
3655 }
3656
3657 void ixgbe_reset(struct ixgbe_adapter *adapter)
3658 {
3659 struct ixgbe_hw *hw = &adapter->hw;
3660 int err;
3661
3662 err = hw->mac.ops.init_hw(hw);
3663 switch (err) {
3664 case 0:
3665 case IXGBE_ERR_SFP_NOT_PRESENT:
3666 break;
3667 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
3668 e_dev_err("master disable timed out\n");
3669 break;
3670 case IXGBE_ERR_EEPROM_VERSION:
3671 /* We are running on a pre-production device, log a warning */
3672 e_dev_warn("This device is a pre-production adapter/LOM. "
3673 "Please be aware there may be issuesassociated with "
3674 "your hardware. If you are experiencing problems "
3675 "please contact your Intel or hardware "
3676 "representative who provided you with this "
3677 "hardware.\n");
3678 break;
3679 default:
3680 e_dev_err("Hardware Error: %d\n", err);
3681 }
3682
3683 /* reprogram the RAR[0] in case user changed it. */
3684 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
3685 IXGBE_RAH_AV);
3686 }
3687
3688 /**
3689 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3690 * @adapter: board private structure
3691 * @rx_ring: ring to free buffers from
3692 **/
3693 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
3694 struct ixgbe_ring *rx_ring)
3695 {
3696 struct pci_dev *pdev = adapter->pdev;
3697 unsigned long size;
3698 unsigned int i;
3699
3700 /* ring already cleared, nothing to do */
3701 if (!rx_ring->rx_buffer_info)
3702 return;
3703
3704 /* Free all the Rx ring sk_buffs */
3705 for (i = 0; i < rx_ring->count; i++) {
3706 struct ixgbe_rx_buffer *rx_buffer_info;
3707
3708 rx_buffer_info = &rx_ring->rx_buffer_info[i];
3709 if (rx_buffer_info->dma) {
3710 dma_unmap_single(&pdev->dev, rx_buffer_info->dma,
3711 rx_ring->rx_buf_len,
3712 DMA_FROM_DEVICE);
3713 rx_buffer_info->dma = 0;
3714 }
3715 if (rx_buffer_info->skb) {
3716 struct sk_buff *skb = rx_buffer_info->skb;
3717 rx_buffer_info->skb = NULL;
3718 do {
3719 struct sk_buff *this = skb;
3720 if (IXGBE_RSC_CB(this)->delay_unmap) {
3721 dma_unmap_single(&pdev->dev,
3722 IXGBE_RSC_CB(this)->dma,
3723 rx_ring->rx_buf_len,
3724 DMA_FROM_DEVICE);
3725 IXGBE_RSC_CB(this)->dma = 0;
3726 IXGBE_RSC_CB(skb)->delay_unmap = false;
3727 }
3728 skb = skb->prev;
3729 dev_kfree_skb(this);
3730 } while (skb);
3731 }
3732 if (!rx_buffer_info->page)
3733 continue;
3734 if (rx_buffer_info->page_dma) {
3735 dma_unmap_page(&pdev->dev, rx_buffer_info->page_dma,
3736 PAGE_SIZE / 2, DMA_FROM_DEVICE);
3737 rx_buffer_info->page_dma = 0;
3738 }
3739 put_page(rx_buffer_info->page);
3740 rx_buffer_info->page = NULL;
3741 rx_buffer_info->page_offset = 0;
3742 }
3743
3744 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3745 memset(rx_ring->rx_buffer_info, 0, size);
3746
3747 /* Zero out the descriptor ring */
3748 memset(rx_ring->desc, 0, rx_ring->size);
3749
3750 rx_ring->next_to_clean = 0;
3751 rx_ring->next_to_use = 0;
3752
3753 if (rx_ring->head)
3754 writel(0, adapter->hw.hw_addr + rx_ring->head);
3755 if (rx_ring->tail)
3756 writel(0, adapter->hw.hw_addr + rx_ring->tail);
3757 }
3758
3759 /**
3760 * ixgbe_clean_tx_ring - Free Tx Buffers
3761 * @adapter: board private structure
3762 * @tx_ring: ring to be cleaned
3763 **/
3764 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
3765 struct ixgbe_ring *tx_ring)
3766 {
3767 struct ixgbe_tx_buffer *tx_buffer_info;
3768 unsigned long size;
3769 unsigned int i;
3770
3771 /* ring already cleared, nothing to do */
3772 if (!tx_ring->tx_buffer_info)
3773 return;
3774
3775 /* Free all the Tx ring sk_buffs */
3776 for (i = 0; i < tx_ring->count; i++) {
3777 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3778 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
3779 }
3780
3781 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3782 memset(tx_ring->tx_buffer_info, 0, size);
3783
3784 /* Zero out the descriptor ring */
3785 memset(tx_ring->desc, 0, tx_ring->size);
3786
3787 tx_ring->next_to_use = 0;
3788 tx_ring->next_to_clean = 0;
3789
3790 if (tx_ring->head)
3791 writel(0, adapter->hw.hw_addr + tx_ring->head);
3792 if (tx_ring->tail)
3793 writel(0, adapter->hw.hw_addr + tx_ring->tail);
3794 }
3795
3796 /**
3797 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3798 * @adapter: board private structure
3799 **/
3800 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
3801 {
3802 int i;
3803
3804 for (i = 0; i < adapter->num_rx_queues; i++)
3805 ixgbe_clean_rx_ring(adapter, adapter->rx_ring[i]);
3806 }
3807
3808 /**
3809 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3810 * @adapter: board private structure
3811 **/
3812 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
3813 {
3814 int i;
3815
3816 for (i = 0; i < adapter->num_tx_queues; i++)
3817 ixgbe_clean_tx_ring(adapter, adapter->tx_ring[i]);
3818 }
3819
3820 void ixgbe_down(struct ixgbe_adapter *adapter)
3821 {
3822 struct net_device *netdev = adapter->netdev;
3823 struct ixgbe_hw *hw = &adapter->hw;
3824 u32 rxctrl;
3825 u32 txdctl;
3826 int i, j;
3827 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3828
3829 /* signal that we are down to the interrupt handler */
3830 set_bit(__IXGBE_DOWN, &adapter->state);
3831
3832 /* disable receive for all VFs and wait one second */
3833 if (adapter->num_vfs) {
3834 /* ping all the active vfs to let them know we are going down */
3835 ixgbe_ping_all_vfs(adapter);
3836
3837 /* Disable all VFTE/VFRE TX/RX */
3838 ixgbe_disable_tx_rx(adapter);
3839
3840 /* Mark all the VFs as inactive */
3841 for (i = 0 ; i < adapter->num_vfs; i++)
3842 adapter->vfinfo[i].clear_to_send = 0;
3843 }
3844
3845 /* disable receives */
3846 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3847 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3848
3849 IXGBE_WRITE_FLUSH(hw);
3850 msleep(10);
3851
3852 netif_tx_stop_all_queues(netdev);
3853
3854 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3855 del_timer_sync(&adapter->sfp_timer);
3856 del_timer_sync(&adapter->watchdog_timer);
3857 cancel_work_sync(&adapter->watchdog_task);
3858
3859 netif_carrier_off(netdev);
3860 netif_tx_disable(netdev);
3861
3862 ixgbe_irq_disable(adapter);
3863
3864 ixgbe_napi_disable_all(adapter);
3865
3866 /* Cleanup the affinity_hint CPU mask memory and callback */
3867 for (i = 0; i < num_q_vectors; i++) {
3868 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
3869 /* clear the affinity_mask in the IRQ descriptor */
3870 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
3871 /* release the CPU mask memory */
3872 free_cpumask_var(q_vector->affinity_mask);
3873 }
3874
3875 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3876 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3877 cancel_work_sync(&adapter->fdir_reinit_task);
3878
3879 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3880 cancel_work_sync(&adapter->check_overtemp_task);
3881
3882 /* disable transmits in the hardware now that interrupts are off */
3883 for (i = 0; i < adapter->num_tx_queues; i++) {
3884 j = adapter->tx_ring[i]->reg_idx;
3885 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
3886 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
3887 (txdctl & ~IXGBE_TXDCTL_ENABLE));
3888 }
3889 /* Disable the Tx DMA engine on 82599 */
3890 if (hw->mac.type == ixgbe_mac_82599EB)
3891 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
3892 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
3893 ~IXGBE_DMATXCTL_TE));
3894
3895 /* power down the optics */
3896 if (hw->phy.multispeed_fiber)
3897 hw->mac.ops.disable_tx_laser(hw);
3898
3899 /* clear n-tuple filters that are cached */
3900 ethtool_ntuple_flush(netdev);
3901
3902 if (!pci_channel_offline(adapter->pdev))
3903 ixgbe_reset(adapter);
3904 ixgbe_clean_all_tx_rings(adapter);
3905 ixgbe_clean_all_rx_rings(adapter);
3906
3907 #ifdef CONFIG_IXGBE_DCA
3908 /* since we reset the hardware DCA settings were cleared */
3909 ixgbe_setup_dca(adapter);
3910 #endif
3911 }
3912
3913 /**
3914 * ixgbe_poll - NAPI Rx polling callback
3915 * @napi: structure for representing this polling device
3916 * @budget: how many packets driver is allowed to clean
3917 *
3918 * This function is used for legacy and MSI, NAPI mode
3919 **/
3920 static int ixgbe_poll(struct napi_struct *napi, int budget)
3921 {
3922 struct ixgbe_q_vector *q_vector =
3923 container_of(napi, struct ixgbe_q_vector, napi);
3924 struct ixgbe_adapter *adapter = q_vector->adapter;
3925 int tx_clean_complete, work_done = 0;
3926
3927 #ifdef CONFIG_IXGBE_DCA
3928 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3929 ixgbe_update_tx_dca(adapter, adapter->tx_ring[0]);
3930 ixgbe_update_rx_dca(adapter, adapter->rx_ring[0]);
3931 }
3932 #endif
3933
3934 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
3935 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
3936
3937 if (!tx_clean_complete)
3938 work_done = budget;
3939
3940 /* If budget not fully consumed, exit the polling mode */
3941 if (work_done < budget) {
3942 napi_complete(napi);
3943 if (adapter->rx_itr_setting & 1)
3944 ixgbe_set_itr(adapter);
3945 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3946 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
3947 }
3948 return work_done;
3949 }
3950
3951 /**
3952 * ixgbe_tx_timeout - Respond to a Tx Hang
3953 * @netdev: network interface device structure
3954 **/
3955 static void ixgbe_tx_timeout(struct net_device *netdev)
3956 {
3957 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3958
3959 /* Do the reset outside of interrupt context */
3960 schedule_work(&adapter->reset_task);
3961 }
3962
3963 static void ixgbe_reset_task(struct work_struct *work)
3964 {
3965 struct ixgbe_adapter *adapter;
3966 adapter = container_of(work, struct ixgbe_adapter, reset_task);
3967
3968 /* If we're already down or resetting, just bail */
3969 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3970 test_bit(__IXGBE_RESETTING, &adapter->state))
3971 return;
3972
3973 adapter->tx_timeout_count++;
3974
3975 ixgbe_dump(adapter);
3976 netdev_err(adapter->netdev, "Reset adapter\n");
3977 ixgbe_reinit_locked(adapter);
3978 }
3979
3980 #ifdef CONFIG_IXGBE_DCB
3981 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3982 {
3983 bool ret = false;
3984 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3985
3986 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3987 return ret;
3988
3989 f->mask = 0x7 << 3;
3990 adapter->num_rx_queues = f->indices;
3991 adapter->num_tx_queues = f->indices;
3992 ret = true;
3993
3994 return ret;
3995 }
3996 #endif
3997
3998 /**
3999 * ixgbe_set_rss_queues: Allocate queues for RSS
4000 * @adapter: board private structure to initialize
4001 *
4002 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4003 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4004 *
4005 **/
4006 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4007 {
4008 bool ret = false;
4009 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4010
4011 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4012 f->mask = 0xF;
4013 adapter->num_rx_queues = f->indices;
4014 adapter->num_tx_queues = f->indices;
4015 ret = true;
4016 } else {
4017 ret = false;
4018 }
4019
4020 return ret;
4021 }
4022
4023 /**
4024 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4025 * @adapter: board private structure to initialize
4026 *
4027 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4028 * to the original CPU that initiated the Tx session. This runs in addition
4029 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4030 * Rx load across CPUs using RSS.
4031 *
4032 **/
4033 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4034 {
4035 bool ret = false;
4036 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4037
4038 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4039 f_fdir->mask = 0;
4040
4041 /* Flow Director must have RSS enabled */
4042 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4043 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
4044 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
4045 adapter->num_tx_queues = f_fdir->indices;
4046 adapter->num_rx_queues = f_fdir->indices;
4047 ret = true;
4048 } else {
4049 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4050 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4051 }
4052 return ret;
4053 }
4054
4055 #ifdef IXGBE_FCOE
4056 /**
4057 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4058 * @adapter: board private structure to initialize
4059 *
4060 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4061 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4062 * rx queues out of the max number of rx queues, instead, it is used as the
4063 * index of the first rx queue used by FCoE.
4064 *
4065 **/
4066 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4067 {
4068 bool ret = false;
4069 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4070
4071 f->indices = min((int)num_online_cpus(), f->indices);
4072 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4073 adapter->num_rx_queues = 1;
4074 adapter->num_tx_queues = 1;
4075 #ifdef CONFIG_IXGBE_DCB
4076 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4077 e_info(probe, "FCoE enabled with DCB\n");
4078 ixgbe_set_dcb_queues(adapter);
4079 }
4080 #endif
4081 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4082 e_info(probe, "FCoE enabled with RSS\n");
4083 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4084 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4085 ixgbe_set_fdir_queues(adapter);
4086 else
4087 ixgbe_set_rss_queues(adapter);
4088 }
4089 /* adding FCoE rx rings to the end */
4090 f->mask = adapter->num_rx_queues;
4091 adapter->num_rx_queues += f->indices;
4092 adapter->num_tx_queues += f->indices;
4093
4094 ret = true;
4095 }
4096
4097 return ret;
4098 }
4099
4100 #endif /* IXGBE_FCOE */
4101 /**
4102 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4103 * @adapter: board private structure to initialize
4104 *
4105 * IOV doesn't actually use anything, so just NAK the
4106 * request for now and let the other queue routines
4107 * figure out what to do.
4108 */
4109 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4110 {
4111 return false;
4112 }
4113
4114 /*
4115 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4116 * @adapter: board private structure to initialize
4117 *
4118 * This is the top level queue allocation routine. The order here is very
4119 * important, starting with the "most" number of features turned on at once,
4120 * and ending with the smallest set of features. This way large combinations
4121 * can be allocated if they're turned on, and smaller combinations are the
4122 * fallthrough conditions.
4123 *
4124 **/
4125 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4126 {
4127 /* Start with base case */
4128 adapter->num_rx_queues = 1;
4129 adapter->num_tx_queues = 1;
4130 adapter->num_rx_pools = adapter->num_rx_queues;
4131 adapter->num_rx_queues_per_pool = 1;
4132
4133 if (ixgbe_set_sriov_queues(adapter))
4134 goto done;
4135
4136 #ifdef IXGBE_FCOE
4137 if (ixgbe_set_fcoe_queues(adapter))
4138 goto done;
4139
4140 #endif /* IXGBE_FCOE */
4141 #ifdef CONFIG_IXGBE_DCB
4142 if (ixgbe_set_dcb_queues(adapter))
4143 goto done;
4144
4145 #endif
4146 if (ixgbe_set_fdir_queues(adapter))
4147 goto done;
4148
4149 if (ixgbe_set_rss_queues(adapter))
4150 goto done;
4151
4152 /* fallback to base case */
4153 adapter->num_rx_queues = 1;
4154 adapter->num_tx_queues = 1;
4155
4156 done:
4157 /* Notify the stack of the (possibly) reduced queue counts. */
4158 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4159 return netif_set_real_num_rx_queues(adapter->netdev,
4160 adapter->num_rx_queues);
4161 }
4162
4163 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4164 int vectors)
4165 {
4166 int err, vector_threshold;
4167
4168 /* We'll want at least 3 (vector_threshold):
4169 * 1) TxQ[0] Cleanup
4170 * 2) RxQ[0] Cleanup
4171 * 3) Other (Link Status Change, etc.)
4172 * 4) TCP Timer (optional)
4173 */
4174 vector_threshold = MIN_MSIX_COUNT;
4175
4176 /* The more we get, the more we will assign to Tx/Rx Cleanup
4177 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4178 * Right now, we simply care about how many we'll get; we'll
4179 * set them up later while requesting irq's.
4180 */
4181 while (vectors >= vector_threshold) {
4182 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4183 vectors);
4184 if (!err) /* Success in acquiring all requested vectors. */
4185 break;
4186 else if (err < 0)
4187 vectors = 0; /* Nasty failure, quit now */
4188 else /* err == number of vectors we should try again with */
4189 vectors = err;
4190 }
4191
4192 if (vectors < vector_threshold) {
4193 /* Can't allocate enough MSI-X interrupts? Oh well.
4194 * This just means we'll go with either a single MSI
4195 * vector or fall back to legacy interrupts.
4196 */
4197 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4198 "Unable to allocate MSI-X interrupts\n");
4199 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4200 kfree(adapter->msix_entries);
4201 adapter->msix_entries = NULL;
4202 } else {
4203 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4204 /*
4205 * Adjust for only the vectors we'll use, which is minimum
4206 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4207 * vectors we were allocated.
4208 */
4209 adapter->num_msix_vectors = min(vectors,
4210 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4211 }
4212 }
4213
4214 /**
4215 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4216 * @adapter: board private structure to initialize
4217 *
4218 * Cache the descriptor ring offsets for RSS to the assigned rings.
4219 *
4220 **/
4221 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4222 {
4223 int i;
4224 bool ret = false;
4225
4226 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4227 for (i = 0; i < adapter->num_rx_queues; i++)
4228 adapter->rx_ring[i]->reg_idx = i;
4229 for (i = 0; i < adapter->num_tx_queues; i++)
4230 adapter->tx_ring[i]->reg_idx = i;
4231 ret = true;
4232 } else {
4233 ret = false;
4234 }
4235
4236 return ret;
4237 }
4238
4239 #ifdef CONFIG_IXGBE_DCB
4240 /**
4241 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4242 * @adapter: board private structure to initialize
4243 *
4244 * Cache the descriptor ring offsets for DCB to the assigned rings.
4245 *
4246 **/
4247 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4248 {
4249 int i;
4250 bool ret = false;
4251 int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
4252
4253 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4254 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
4255 /* the number of queues is assumed to be symmetric */
4256 for (i = 0; i < dcb_i; i++) {
4257 adapter->rx_ring[i]->reg_idx = i << 3;
4258 adapter->tx_ring[i]->reg_idx = i << 2;
4259 }
4260 ret = true;
4261 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
4262 if (dcb_i == 8) {
4263 /*
4264 * Tx TC0 starts at: descriptor queue 0
4265 * Tx TC1 starts at: descriptor queue 32
4266 * Tx TC2 starts at: descriptor queue 64
4267 * Tx TC3 starts at: descriptor queue 80
4268 * Tx TC4 starts at: descriptor queue 96
4269 * Tx TC5 starts at: descriptor queue 104
4270 * Tx TC6 starts at: descriptor queue 112
4271 * Tx TC7 starts at: descriptor queue 120
4272 *
4273 * Rx TC0-TC7 are offset by 16 queues each
4274 */
4275 for (i = 0; i < 3; i++) {
4276 adapter->tx_ring[i]->reg_idx = i << 5;
4277 adapter->rx_ring[i]->reg_idx = i << 4;
4278 }
4279 for ( ; i < 5; i++) {
4280 adapter->tx_ring[i]->reg_idx =
4281 ((i + 2) << 4);
4282 adapter->rx_ring[i]->reg_idx = i << 4;
4283 }
4284 for ( ; i < dcb_i; i++) {
4285 adapter->tx_ring[i]->reg_idx =
4286 ((i + 8) << 3);
4287 adapter->rx_ring[i]->reg_idx = i << 4;
4288 }
4289
4290 ret = true;
4291 } else if (dcb_i == 4) {
4292 /*
4293 * Tx TC0 starts at: descriptor queue 0
4294 * Tx TC1 starts at: descriptor queue 64
4295 * Tx TC2 starts at: descriptor queue 96
4296 * Tx TC3 starts at: descriptor queue 112
4297 *
4298 * Rx TC0-TC3 are offset by 32 queues each
4299 */
4300 adapter->tx_ring[0]->reg_idx = 0;
4301 adapter->tx_ring[1]->reg_idx = 64;
4302 adapter->tx_ring[2]->reg_idx = 96;
4303 adapter->tx_ring[3]->reg_idx = 112;
4304 for (i = 0 ; i < dcb_i; i++)
4305 adapter->rx_ring[i]->reg_idx = i << 5;
4306
4307 ret = true;
4308 } else {
4309 ret = false;
4310 }
4311 } else {
4312 ret = false;
4313 }
4314 } else {
4315 ret = false;
4316 }
4317
4318 return ret;
4319 }
4320 #endif
4321
4322 /**
4323 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4324 * @adapter: board private structure to initialize
4325 *
4326 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4327 *
4328 **/
4329 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4330 {
4331 int i;
4332 bool ret = false;
4333
4334 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
4335 ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4336 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
4337 for (i = 0; i < adapter->num_rx_queues; i++)
4338 adapter->rx_ring[i]->reg_idx = i;
4339 for (i = 0; i < adapter->num_tx_queues; i++)
4340 adapter->tx_ring[i]->reg_idx = i;
4341 ret = true;
4342 }
4343
4344 return ret;
4345 }
4346
4347 #ifdef IXGBE_FCOE
4348 /**
4349 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4350 * @adapter: board private structure to initialize
4351 *
4352 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4353 *
4354 */
4355 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4356 {
4357 int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
4358 bool ret = false;
4359 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4360
4361 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4362 #ifdef CONFIG_IXGBE_DCB
4363 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4364 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
4365
4366 ixgbe_cache_ring_dcb(adapter);
4367 /* find out queues in TC for FCoE */
4368 fcoe_rx_i = adapter->rx_ring[fcoe->tc]->reg_idx + 1;
4369 fcoe_tx_i = adapter->tx_ring[fcoe->tc]->reg_idx + 1;
4370 /*
4371 * In 82599, the number of Tx queues for each traffic
4372 * class for both 8-TC and 4-TC modes are:
4373 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4374 * 8 TCs: 32 32 16 16 8 8 8 8
4375 * 4 TCs: 64 64 32 32
4376 * We have max 8 queues for FCoE, where 8 the is
4377 * FCoE redirection table size. If TC for FCoE is
4378 * less than or equal to TC3, we have enough queues
4379 * to add max of 8 queues for FCoE, so we start FCoE
4380 * tx descriptor from the next one, i.e., reg_idx + 1.
4381 * If TC for FCoE is above TC3, implying 8 TC mode,
4382 * and we need 8 for FCoE, we have to take all queues
4383 * in that traffic class for FCoE.
4384 */
4385 if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
4386 fcoe_tx_i--;
4387 }
4388 #endif /* CONFIG_IXGBE_DCB */
4389 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4390 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
4391 (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
4392 ixgbe_cache_ring_fdir(adapter);
4393 else
4394 ixgbe_cache_ring_rss(adapter);
4395
4396 fcoe_rx_i = f->mask;
4397 fcoe_tx_i = f->mask;
4398 }
4399 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4400 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4401 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4402 }
4403 ret = true;
4404 }
4405 return ret;
4406 }
4407
4408 #endif /* IXGBE_FCOE */
4409 /**
4410 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4411 * @adapter: board private structure to initialize
4412 *
4413 * SR-IOV doesn't use any descriptor rings but changes the default if
4414 * no other mapping is used.
4415 *
4416 */
4417 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4418 {
4419 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4420 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4421 if (adapter->num_vfs)
4422 return true;
4423 else
4424 return false;
4425 }
4426
4427 /**
4428 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4429 * @adapter: board private structure to initialize
4430 *
4431 * Once we know the feature-set enabled for the device, we'll cache
4432 * the register offset the descriptor ring is assigned to.
4433 *
4434 * Note, the order the various feature calls is important. It must start with
4435 * the "most" features enabled at the same time, then trickle down to the
4436 * least amount of features turned on at once.
4437 **/
4438 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4439 {
4440 /* start with default case */
4441 adapter->rx_ring[0]->reg_idx = 0;
4442 adapter->tx_ring[0]->reg_idx = 0;
4443
4444 if (ixgbe_cache_ring_sriov(adapter))
4445 return;
4446
4447 #ifdef IXGBE_FCOE
4448 if (ixgbe_cache_ring_fcoe(adapter))
4449 return;
4450
4451 #endif /* IXGBE_FCOE */
4452 #ifdef CONFIG_IXGBE_DCB
4453 if (ixgbe_cache_ring_dcb(adapter))
4454 return;
4455
4456 #endif
4457 if (ixgbe_cache_ring_fdir(adapter))
4458 return;
4459
4460 if (ixgbe_cache_ring_rss(adapter))
4461 return;
4462 }
4463
4464 /**
4465 * ixgbe_alloc_queues - Allocate memory for all rings
4466 * @adapter: board private structure to initialize
4467 *
4468 * We allocate one ring per queue at run-time since we don't know the
4469 * number of queues at compile-time. The polling_netdev array is
4470 * intended for Multiqueue, but should work fine with a single queue.
4471 **/
4472 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4473 {
4474 int i;
4475 int orig_node = adapter->node;
4476
4477 for (i = 0; i < adapter->num_tx_queues; i++) {
4478 struct ixgbe_ring *ring = adapter->tx_ring[i];
4479 if (orig_node == -1) {
4480 int cur_node = next_online_node(adapter->node);
4481 if (cur_node == MAX_NUMNODES)
4482 cur_node = first_online_node;
4483 adapter->node = cur_node;
4484 }
4485 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4486 adapter->node);
4487 if (!ring)
4488 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4489 if (!ring)
4490 goto err_tx_ring_allocation;
4491 ring->count = adapter->tx_ring_count;
4492 ring->queue_index = i;
4493 ring->numa_node = adapter->node;
4494
4495 adapter->tx_ring[i] = ring;
4496 }
4497
4498 /* Restore the adapter's original node */
4499 adapter->node = orig_node;
4500
4501 for (i = 0; i < adapter->num_rx_queues; i++) {
4502 struct ixgbe_ring *ring = adapter->rx_ring[i];
4503 if (orig_node == -1) {
4504 int cur_node = next_online_node(adapter->node);
4505 if (cur_node == MAX_NUMNODES)
4506 cur_node = first_online_node;
4507 adapter->node = cur_node;
4508 }
4509 ring = kzalloc_node(sizeof(struct ixgbe_ring), GFP_KERNEL,
4510 adapter->node);
4511 if (!ring)
4512 ring = kzalloc(sizeof(struct ixgbe_ring), GFP_KERNEL);
4513 if (!ring)
4514 goto err_rx_ring_allocation;
4515 ring->count = adapter->rx_ring_count;
4516 ring->queue_index = i;
4517 ring->numa_node = adapter->node;
4518
4519 adapter->rx_ring[i] = ring;
4520 }
4521
4522 /* Restore the adapter's original node */
4523 adapter->node = orig_node;
4524
4525 ixgbe_cache_ring_register(adapter);
4526
4527 return 0;
4528
4529 err_rx_ring_allocation:
4530 for (i = 0; i < adapter->num_tx_queues; i++)
4531 kfree(adapter->tx_ring[i]);
4532 err_tx_ring_allocation:
4533 return -ENOMEM;
4534 }
4535
4536 /**
4537 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4538 * @adapter: board private structure to initialize
4539 *
4540 * Attempt to configure the interrupts using the best available
4541 * capabilities of the hardware and the kernel.
4542 **/
4543 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4544 {
4545 struct ixgbe_hw *hw = &adapter->hw;
4546 int err = 0;
4547 int vector, v_budget;
4548
4549 /*
4550 * It's easy to be greedy for MSI-X vectors, but it really
4551 * doesn't do us much good if we have a lot more vectors
4552 * than CPU's. So let's be conservative and only ask for
4553 * (roughly) the same number of vectors as there are CPU's.
4554 */
4555 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4556 (int)num_online_cpus()) + NON_Q_VECTORS;
4557
4558 /*
4559 * At the same time, hardware can only support a maximum of
4560 * hw.mac->max_msix_vectors vectors. With features
4561 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4562 * descriptor queues supported by our device. Thus, we cap it off in
4563 * those rare cases where the cpu count also exceeds our vector limit.
4564 */
4565 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4566
4567 /* A failure in MSI-X entry allocation isn't fatal, but it does
4568 * mean we disable MSI-X capabilities of the adapter. */
4569 adapter->msix_entries = kcalloc(v_budget,
4570 sizeof(struct msix_entry), GFP_KERNEL);
4571 if (adapter->msix_entries) {
4572 for (vector = 0; vector < v_budget; vector++)
4573 adapter->msix_entries[vector].entry = vector;
4574
4575 ixgbe_acquire_msix_vectors(adapter, v_budget);
4576
4577 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4578 goto out;
4579 }
4580
4581 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4582 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4583 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4584 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4585 adapter->atr_sample_rate = 0;
4586 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4587 ixgbe_disable_sriov(adapter);
4588
4589 err = ixgbe_set_num_queues(adapter);
4590 if (err)
4591 return err;
4592
4593 err = pci_enable_msi(adapter->pdev);
4594 if (!err) {
4595 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4596 } else {
4597 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4598 "Unable to allocate MSI interrupt, "
4599 "falling back to legacy. Error: %d\n", err);
4600 /* reset err */
4601 err = 0;
4602 }
4603
4604 out:
4605 return err;
4606 }
4607
4608 /**
4609 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4610 * @adapter: board private structure to initialize
4611 *
4612 * We allocate one q_vector per queue interrupt. If allocation fails we
4613 * return -ENOMEM.
4614 **/
4615 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4616 {
4617 int q_idx, num_q_vectors;
4618 struct ixgbe_q_vector *q_vector;
4619 int napi_vectors;
4620 int (*poll)(struct napi_struct *, int);
4621
4622 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4623 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4624 napi_vectors = adapter->num_rx_queues;
4625 poll = &ixgbe_clean_rxtx_many;
4626 } else {
4627 num_q_vectors = 1;
4628 napi_vectors = 1;
4629 poll = &ixgbe_poll;
4630 }
4631
4632 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4633 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4634 GFP_KERNEL, adapter->node);
4635 if (!q_vector)
4636 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4637 GFP_KERNEL);
4638 if (!q_vector)
4639 goto err_out;
4640 q_vector->adapter = adapter;
4641 if (q_vector->txr_count && !q_vector->rxr_count)
4642 q_vector->eitr = adapter->tx_eitr_param;
4643 else
4644 q_vector->eitr = adapter->rx_eitr_param;
4645 q_vector->v_idx = q_idx;
4646 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4647 adapter->q_vector[q_idx] = q_vector;
4648 }
4649
4650 return 0;
4651
4652 err_out:
4653 while (q_idx) {
4654 q_idx--;
4655 q_vector = adapter->q_vector[q_idx];
4656 netif_napi_del(&q_vector->napi);
4657 kfree(q_vector);
4658 adapter->q_vector[q_idx] = NULL;
4659 }
4660 return -ENOMEM;
4661 }
4662
4663 /**
4664 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4665 * @adapter: board private structure to initialize
4666 *
4667 * This function frees the memory allocated to the q_vectors. In addition if
4668 * NAPI is enabled it will delete any references to the NAPI struct prior
4669 * to freeing the q_vector.
4670 **/
4671 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4672 {
4673 int q_idx, num_q_vectors;
4674
4675 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4676 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4677 else
4678 num_q_vectors = 1;
4679
4680 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4681 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4682 adapter->q_vector[q_idx] = NULL;
4683 netif_napi_del(&q_vector->napi);
4684 kfree(q_vector);
4685 }
4686 }
4687
4688 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4689 {
4690 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4691 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4692 pci_disable_msix(adapter->pdev);
4693 kfree(adapter->msix_entries);
4694 adapter->msix_entries = NULL;
4695 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4696 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4697 pci_disable_msi(adapter->pdev);
4698 }
4699 }
4700
4701 /**
4702 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4703 * @adapter: board private structure to initialize
4704 *
4705 * We determine which interrupt scheme to use based on...
4706 * - Kernel support (MSI, MSI-X)
4707 * - which can be user-defined (via MODULE_PARAM)
4708 * - Hardware queue count (num_*_queues)
4709 * - defined by miscellaneous hardware support/features (RSS, etc.)
4710 **/
4711 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
4712 {
4713 int err;
4714
4715 /* Number of supported queues */
4716 err = ixgbe_set_num_queues(adapter);
4717 if (err)
4718 return err;
4719
4720 err = ixgbe_set_interrupt_capability(adapter);
4721 if (err) {
4722 e_dev_err("Unable to setup interrupt capabilities\n");
4723 goto err_set_interrupt;
4724 }
4725
4726 err = ixgbe_alloc_q_vectors(adapter);
4727 if (err) {
4728 e_dev_err("Unable to allocate memory for queue vectors\n");
4729 goto err_alloc_q_vectors;
4730 }
4731
4732 err = ixgbe_alloc_queues(adapter);
4733 if (err) {
4734 e_dev_err("Unable to allocate memory for queues\n");
4735 goto err_alloc_queues;
4736 }
4737
4738 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4739 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
4740 adapter->num_rx_queues, adapter->num_tx_queues);
4741
4742 set_bit(__IXGBE_DOWN, &adapter->state);
4743
4744 return 0;
4745
4746 err_alloc_queues:
4747 ixgbe_free_q_vectors(adapter);
4748 err_alloc_q_vectors:
4749 ixgbe_reset_interrupt_capability(adapter);
4750 err_set_interrupt:
4751 return err;
4752 }
4753
4754 /**
4755 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4756 * @adapter: board private structure to clear interrupt scheme on
4757 *
4758 * We go through and clear interrupt specific resources and reset the structure
4759 * to pre-load conditions
4760 **/
4761 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
4762 {
4763 int i;
4764
4765 for (i = 0; i < adapter->num_tx_queues; i++) {
4766 kfree(adapter->tx_ring[i]);
4767 adapter->tx_ring[i] = NULL;
4768 }
4769 for (i = 0; i < adapter->num_rx_queues; i++) {
4770 kfree(adapter->rx_ring[i]);
4771 adapter->rx_ring[i] = NULL;
4772 }
4773
4774 ixgbe_free_q_vectors(adapter);
4775 ixgbe_reset_interrupt_capability(adapter);
4776 }
4777
4778 /**
4779 * ixgbe_sfp_timer - worker thread to find a missing module
4780 * @data: pointer to our adapter struct
4781 **/
4782 static void ixgbe_sfp_timer(unsigned long data)
4783 {
4784 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4785
4786 /*
4787 * Do the sfp_timer outside of interrupt context due to the
4788 * delays that sfp+ detection requires
4789 */
4790 schedule_work(&adapter->sfp_task);
4791 }
4792
4793 /**
4794 * ixgbe_sfp_task - worker thread to find a missing module
4795 * @work: pointer to work_struct containing our data
4796 **/
4797 static void ixgbe_sfp_task(struct work_struct *work)
4798 {
4799 struct ixgbe_adapter *adapter = container_of(work,
4800 struct ixgbe_adapter,
4801 sfp_task);
4802 struct ixgbe_hw *hw = &adapter->hw;
4803
4804 if ((hw->phy.type == ixgbe_phy_nl) &&
4805 (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
4806 s32 ret = hw->phy.ops.identify_sfp(hw);
4807 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
4808 goto reschedule;
4809 ret = hw->phy.ops.reset(hw);
4810 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4811 e_dev_err("failed to initialize because an unsupported "
4812 "SFP+ module type was detected.\n");
4813 e_dev_err("Reload the driver after installing a "
4814 "supported module.\n");
4815 unregister_netdev(adapter->netdev);
4816 } else {
4817 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
4818 }
4819 /* don't need this routine any more */
4820 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
4821 }
4822 return;
4823 reschedule:
4824 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
4825 mod_timer(&adapter->sfp_timer,
4826 round_jiffies(jiffies + (2 * HZ)));
4827 }
4828
4829 /**
4830 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4831 * @adapter: board private structure to initialize
4832 *
4833 * ixgbe_sw_init initializes the Adapter private data structure.
4834 * Fields are initialized based on PCI device information and
4835 * OS network device settings (MTU size).
4836 **/
4837 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
4838 {
4839 struct ixgbe_hw *hw = &adapter->hw;
4840 struct pci_dev *pdev = adapter->pdev;
4841 struct net_device *dev = adapter->netdev;
4842 unsigned int rss;
4843 #ifdef CONFIG_IXGBE_DCB
4844 int j;
4845 struct tc_configuration *tc;
4846 #endif
4847
4848 /* PCI config space info */
4849
4850 hw->vendor_id = pdev->vendor;
4851 hw->device_id = pdev->device;
4852 hw->revision_id = pdev->revision;
4853 hw->subsystem_vendor_id = pdev->subsystem_vendor;
4854 hw->subsystem_device_id = pdev->subsystem_device;
4855
4856 /* Set capability flags */
4857 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
4858 adapter->ring_feature[RING_F_RSS].indices = rss;
4859 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
4860 adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
4861 if (hw->mac.type == ixgbe_mac_82598EB) {
4862 if (hw->device_id == IXGBE_DEV_ID_82598AT)
4863 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
4864 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
4865 } else if (hw->mac.type == ixgbe_mac_82599EB) {
4866 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
4867 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
4868 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
4869 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
4870 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
4871 if (dev->features & NETIF_F_NTUPLE) {
4872 /* Flow Director perfect filter enabled */
4873 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
4874 adapter->atr_sample_rate = 0;
4875 spin_lock_init(&adapter->fdir_perfect_lock);
4876 } else {
4877 /* Flow Director hash filters enabled */
4878 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
4879 adapter->atr_sample_rate = 20;
4880 }
4881 adapter->ring_feature[RING_F_FDIR].indices =
4882 IXGBE_MAX_FDIR_INDICES;
4883 adapter->fdir_pballoc = 0;
4884 #ifdef IXGBE_FCOE
4885 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
4886 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
4887 adapter->ring_feature[RING_F_FCOE].indices = 0;
4888 #ifdef CONFIG_IXGBE_DCB
4889 /* Default traffic class to use for FCoE */
4890 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
4891 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
4892 #endif
4893 #endif /* IXGBE_FCOE */
4894 }
4895
4896 #ifdef CONFIG_IXGBE_DCB
4897 /* Configure DCB traffic classes */
4898 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
4899 tc = &adapter->dcb_cfg.tc_config[j];
4900 tc->path[DCB_TX_CONFIG].bwg_id = 0;
4901 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
4902 tc->path[DCB_RX_CONFIG].bwg_id = 0;
4903 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
4904 tc->dcb_pfc = pfc_disabled;
4905 }
4906 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
4907 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
4908 adapter->dcb_cfg.rx_pba_cfg = pba_equal;
4909 adapter->dcb_cfg.pfc_mode_enable = false;
4910 adapter->dcb_cfg.round_robin_enable = false;
4911 adapter->dcb_set_bitmap = 0x00;
4912 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
4913 adapter->ring_feature[RING_F_DCB].indices);
4914
4915 #endif
4916
4917 /* default flow control settings */
4918 hw->fc.requested_mode = ixgbe_fc_full;
4919 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
4920 #ifdef CONFIG_DCB
4921 adapter->last_lfc_mode = hw->fc.current_mode;
4922 #endif
4923 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
4924 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
4925 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
4926 hw->fc.send_xon = true;
4927 hw->fc.disable_fc_autoneg = false;
4928
4929 /* enable itr by default in dynamic mode */
4930 adapter->rx_itr_setting = 1;
4931 adapter->rx_eitr_param = 20000;
4932 adapter->tx_itr_setting = 1;
4933 adapter->tx_eitr_param = 10000;
4934
4935 /* set defaults for eitr in MegaBytes */
4936 adapter->eitr_low = 10;
4937 adapter->eitr_high = 20;
4938
4939 /* set default ring sizes */
4940 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
4941 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
4942
4943 /* initialize eeprom parameters */
4944 if (ixgbe_init_eeprom_params_generic(hw)) {
4945 e_dev_err("EEPROM initialization failed\n");
4946 return -EIO;
4947 }
4948
4949 /* enable rx csum by default */
4950 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
4951
4952 /* get assigned NUMA node */
4953 adapter->node = dev_to_node(&pdev->dev);
4954
4955 set_bit(__IXGBE_DOWN, &adapter->state);
4956
4957 return 0;
4958 }
4959
4960 /**
4961 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4962 * @adapter: board private structure
4963 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4964 *
4965 * Return 0 on success, negative on failure
4966 **/
4967 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
4968 struct ixgbe_ring *tx_ring)
4969 {
4970 struct pci_dev *pdev = adapter->pdev;
4971 int size;
4972
4973 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4974 tx_ring->tx_buffer_info = vmalloc_node(size, tx_ring->numa_node);
4975 if (!tx_ring->tx_buffer_info)
4976 tx_ring->tx_buffer_info = vmalloc(size);
4977 if (!tx_ring->tx_buffer_info)
4978 goto err;
4979 memset(tx_ring->tx_buffer_info, 0, size);
4980
4981 /* round up to nearest 4K */
4982 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
4983 tx_ring->size = ALIGN(tx_ring->size, 4096);
4984
4985 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size,
4986 &tx_ring->dma, GFP_KERNEL);
4987 if (!tx_ring->desc)
4988 goto err;
4989
4990 tx_ring->next_to_use = 0;
4991 tx_ring->next_to_clean = 0;
4992 tx_ring->work_limit = tx_ring->count;
4993 return 0;
4994
4995 err:
4996 vfree(tx_ring->tx_buffer_info);
4997 tx_ring->tx_buffer_info = NULL;
4998 e_err(probe, "Unable to allocate memory for the Tx descriptor ring\n");
4999 return -ENOMEM;
5000 }
5001
5002 /**
5003 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5004 * @adapter: board private structure
5005 *
5006 * If this function returns with an error, then it's possible one or
5007 * more of the rings is populated (while the rest are not). It is the
5008 * callers duty to clean those orphaned rings.
5009 *
5010 * Return 0 on success, negative on failure
5011 **/
5012 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5013 {
5014 int i, err = 0;
5015
5016 for (i = 0; i < adapter->num_tx_queues; i++) {
5017 err = ixgbe_setup_tx_resources(adapter, adapter->tx_ring[i]);
5018 if (!err)
5019 continue;
5020 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5021 break;
5022 }
5023
5024 return err;
5025 }
5026
5027 /**
5028 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5029 * @adapter: board private structure
5030 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5031 *
5032 * Returns 0 on success, negative on failure
5033 **/
5034 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
5035 struct ixgbe_ring *rx_ring)
5036 {
5037 struct pci_dev *pdev = adapter->pdev;
5038 int size;
5039
5040 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5041 rx_ring->rx_buffer_info = vmalloc_node(size, adapter->node);
5042 if (!rx_ring->rx_buffer_info)
5043 rx_ring->rx_buffer_info = vmalloc(size);
5044 if (!rx_ring->rx_buffer_info) {
5045 e_err(probe, "vmalloc allocation failed for the Rx "
5046 "descriptor ring\n");
5047 goto alloc_failed;
5048 }
5049 memset(rx_ring->rx_buffer_info, 0, size);
5050
5051 /* Round up to nearest 4K */
5052 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5053 rx_ring->size = ALIGN(rx_ring->size, 4096);
5054
5055 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size,
5056 &rx_ring->dma, GFP_KERNEL);
5057
5058 if (!rx_ring->desc) {
5059 e_err(probe, "Memory allocation failed for the Rx "
5060 "descriptor ring\n");
5061 vfree(rx_ring->rx_buffer_info);
5062 goto alloc_failed;
5063 }
5064
5065 rx_ring->next_to_clean = 0;
5066 rx_ring->next_to_use = 0;
5067
5068 return 0;
5069
5070 alloc_failed:
5071 return -ENOMEM;
5072 }
5073
5074 /**
5075 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5076 * @adapter: board private structure
5077 *
5078 * If this function returns with an error, then it's possible one or
5079 * more of the rings is populated (while the rest are not). It is the
5080 * callers duty to clean those orphaned rings.
5081 *
5082 * Return 0 on success, negative on failure
5083 **/
5084
5085 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5086 {
5087 int i, err = 0;
5088
5089 for (i = 0; i < adapter->num_rx_queues; i++) {
5090 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
5091 if (!err)
5092 continue;
5093 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5094 break;
5095 }
5096
5097 return err;
5098 }
5099
5100 /**
5101 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5102 * @adapter: board private structure
5103 * @tx_ring: Tx descriptor ring for a specific queue
5104 *
5105 * Free all transmit software resources
5106 **/
5107 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
5108 struct ixgbe_ring *tx_ring)
5109 {
5110 struct pci_dev *pdev = adapter->pdev;
5111
5112 ixgbe_clean_tx_ring(adapter, tx_ring);
5113
5114 vfree(tx_ring->tx_buffer_info);
5115 tx_ring->tx_buffer_info = NULL;
5116
5117 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc,
5118 tx_ring->dma);
5119
5120 tx_ring->desc = NULL;
5121 }
5122
5123 /**
5124 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5125 * @adapter: board private structure
5126 *
5127 * Free all transmit software resources
5128 **/
5129 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5130 {
5131 int i;
5132
5133 for (i = 0; i < adapter->num_tx_queues; i++)
5134 if (adapter->tx_ring[i]->desc)
5135 ixgbe_free_tx_resources(adapter, adapter->tx_ring[i]);
5136 }
5137
5138 /**
5139 * ixgbe_free_rx_resources - Free Rx Resources
5140 * @adapter: board private structure
5141 * @rx_ring: ring to clean the resources from
5142 *
5143 * Free all receive software resources
5144 **/
5145 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
5146 struct ixgbe_ring *rx_ring)
5147 {
5148 struct pci_dev *pdev = adapter->pdev;
5149
5150 ixgbe_clean_rx_ring(adapter, rx_ring);
5151
5152 vfree(rx_ring->rx_buffer_info);
5153 rx_ring->rx_buffer_info = NULL;
5154
5155 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc,
5156 rx_ring->dma);
5157
5158 rx_ring->desc = NULL;
5159 }
5160
5161 /**
5162 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5163 * @adapter: board private structure
5164 *
5165 * Free all receive software resources
5166 **/
5167 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5168 {
5169 int i;
5170
5171 for (i = 0; i < adapter->num_rx_queues; i++)
5172 if (adapter->rx_ring[i]->desc)
5173 ixgbe_free_rx_resources(adapter, adapter->rx_ring[i]);
5174 }
5175
5176 /**
5177 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5178 * @netdev: network interface device structure
5179 * @new_mtu: new value for maximum frame size
5180 *
5181 * Returns 0 on success, negative on failure
5182 **/
5183 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5184 {
5185 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5186 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5187
5188 /* MTU < 68 is an error and causes problems on some kernels */
5189 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5190 return -EINVAL;
5191
5192 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5193 /* must set new MTU before calling down or up */
5194 netdev->mtu = new_mtu;
5195
5196 if (netif_running(netdev))
5197 ixgbe_reinit_locked(adapter);
5198
5199 return 0;
5200 }
5201
5202 /**
5203 * ixgbe_open - Called when a network interface is made active
5204 * @netdev: network interface device structure
5205 *
5206 * Returns 0 on success, negative value on failure
5207 *
5208 * The open entry point is called when a network interface is made
5209 * active by the system (IFF_UP). At this point all resources needed
5210 * for transmit and receive operations are allocated, the interrupt
5211 * handler is registered with the OS, the watchdog timer is started,
5212 * and the stack is notified that the interface is ready.
5213 **/
5214 static int ixgbe_open(struct net_device *netdev)
5215 {
5216 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5217 int err;
5218
5219 /* disallow open during test */
5220 if (test_bit(__IXGBE_TESTING, &adapter->state))
5221 return -EBUSY;
5222
5223 netif_carrier_off(netdev);
5224
5225 /* allocate transmit descriptors */
5226 err = ixgbe_setup_all_tx_resources(adapter);
5227 if (err)
5228 goto err_setup_tx;
5229
5230 /* allocate receive descriptors */
5231 err = ixgbe_setup_all_rx_resources(adapter);
5232 if (err)
5233 goto err_setup_rx;
5234
5235 ixgbe_configure(adapter);
5236
5237 err = ixgbe_request_irq(adapter);
5238 if (err)
5239 goto err_req_irq;
5240
5241 err = ixgbe_up_complete(adapter);
5242 if (err)
5243 goto err_up;
5244
5245 netif_tx_start_all_queues(netdev);
5246
5247 return 0;
5248
5249 err_up:
5250 ixgbe_release_hw_control(adapter);
5251 ixgbe_free_irq(adapter);
5252 err_req_irq:
5253 err_setup_rx:
5254 ixgbe_free_all_rx_resources(adapter);
5255 err_setup_tx:
5256 ixgbe_free_all_tx_resources(adapter);
5257 ixgbe_reset(adapter);
5258
5259 return err;
5260 }
5261
5262 /**
5263 * ixgbe_close - Disables a network interface
5264 * @netdev: network interface device structure
5265 *
5266 * Returns 0, this is not allowed to fail
5267 *
5268 * The close entry point is called when an interface is de-activated
5269 * by the OS. The hardware is still under the drivers control, but
5270 * needs to be disabled. A global MAC reset is issued to stop the
5271 * hardware, and all transmit and receive resources are freed.
5272 **/
5273 static int ixgbe_close(struct net_device *netdev)
5274 {
5275 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5276
5277 ixgbe_down(adapter);
5278 ixgbe_free_irq(adapter);
5279
5280 ixgbe_free_all_tx_resources(adapter);
5281 ixgbe_free_all_rx_resources(adapter);
5282
5283 ixgbe_release_hw_control(adapter);
5284
5285 return 0;
5286 }
5287
5288 #ifdef CONFIG_PM
5289 static int ixgbe_resume(struct pci_dev *pdev)
5290 {
5291 struct net_device *netdev = pci_get_drvdata(pdev);
5292 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5293 u32 err;
5294
5295 pci_set_power_state(pdev, PCI_D0);
5296 pci_restore_state(pdev);
5297 /*
5298 * pci_restore_state clears dev->state_saved so call
5299 * pci_save_state to restore it.
5300 */
5301 pci_save_state(pdev);
5302
5303 err = pci_enable_device_mem(pdev);
5304 if (err) {
5305 e_dev_err("Cannot enable PCI device from suspend\n");
5306 return err;
5307 }
5308 pci_set_master(pdev);
5309
5310 pci_wake_from_d3(pdev, false);
5311
5312 err = ixgbe_init_interrupt_scheme(adapter);
5313 if (err) {
5314 e_dev_err("Cannot initialize interrupts for device\n");
5315 return err;
5316 }
5317
5318 ixgbe_reset(adapter);
5319
5320 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5321
5322 if (netif_running(netdev)) {
5323 err = ixgbe_open(adapter->netdev);
5324 if (err)
5325 return err;
5326 }
5327
5328 netif_device_attach(netdev);
5329
5330 return 0;
5331 }
5332 #endif /* CONFIG_PM */
5333
5334 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5335 {
5336 struct net_device *netdev = pci_get_drvdata(pdev);
5337 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5338 struct ixgbe_hw *hw = &adapter->hw;
5339 u32 ctrl, fctrl;
5340 u32 wufc = adapter->wol;
5341 #ifdef CONFIG_PM
5342 int retval = 0;
5343 #endif
5344
5345 netif_device_detach(netdev);
5346
5347 if (netif_running(netdev)) {
5348 ixgbe_down(adapter);
5349 ixgbe_free_irq(adapter);
5350 ixgbe_free_all_tx_resources(adapter);
5351 ixgbe_free_all_rx_resources(adapter);
5352 }
5353
5354 #ifdef CONFIG_PM
5355 retval = pci_save_state(pdev);
5356 if (retval)
5357 return retval;
5358
5359 #endif
5360 if (wufc) {
5361 ixgbe_set_rx_mode(netdev);
5362
5363 /* turn on all-multi mode if wake on multicast is enabled */
5364 if (wufc & IXGBE_WUFC_MC) {
5365 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5366 fctrl |= IXGBE_FCTRL_MPE;
5367 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5368 }
5369
5370 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5371 ctrl |= IXGBE_CTRL_GIO_DIS;
5372 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5373
5374 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5375 } else {
5376 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5377 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5378 }
5379
5380 if (wufc && hw->mac.type == ixgbe_mac_82599EB)
5381 pci_wake_from_d3(pdev, true);
5382 else
5383 pci_wake_from_d3(pdev, false);
5384
5385 *enable_wake = !!wufc;
5386
5387 ixgbe_clear_interrupt_scheme(adapter);
5388
5389 ixgbe_release_hw_control(adapter);
5390
5391 pci_disable_device(pdev);
5392
5393 return 0;
5394 }
5395
5396 #ifdef CONFIG_PM
5397 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5398 {
5399 int retval;
5400 bool wake;
5401
5402 retval = __ixgbe_shutdown(pdev, &wake);
5403 if (retval)
5404 return retval;
5405
5406 if (wake) {
5407 pci_prepare_to_sleep(pdev);
5408 } else {
5409 pci_wake_from_d3(pdev, false);
5410 pci_set_power_state(pdev, PCI_D3hot);
5411 }
5412
5413 return 0;
5414 }
5415 #endif /* CONFIG_PM */
5416
5417 static void ixgbe_shutdown(struct pci_dev *pdev)
5418 {
5419 bool wake;
5420
5421 __ixgbe_shutdown(pdev, &wake);
5422
5423 if (system_state == SYSTEM_POWER_OFF) {
5424 pci_wake_from_d3(pdev, wake);
5425 pci_set_power_state(pdev, PCI_D3hot);
5426 }
5427 }
5428
5429 /**
5430 * ixgbe_update_stats - Update the board statistics counters.
5431 * @adapter: board private structure
5432 **/
5433 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5434 {
5435 struct net_device *netdev = adapter->netdev;
5436 struct ixgbe_hw *hw = &adapter->hw;
5437 u64 total_mpc = 0;
5438 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5439 u64 non_eop_descs = 0, restart_queue = 0;
5440 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5441
5442 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5443 test_bit(__IXGBE_RESETTING, &adapter->state))
5444 return;
5445
5446 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5447 u64 rsc_count = 0;
5448 u64 rsc_flush = 0;
5449 for (i = 0; i < 16; i++)
5450 adapter->hw_rx_no_dma_resources +=
5451 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5452 for (i = 0; i < adapter->num_rx_queues; i++) {
5453 rsc_count += adapter->rx_ring[i]->rsc_count;
5454 rsc_flush += adapter->rx_ring[i]->rsc_flush;
5455 }
5456 adapter->rsc_total_count = rsc_count;
5457 adapter->rsc_total_flush = rsc_flush;
5458 }
5459
5460 /* gather some stats to the adapter struct that are per queue */
5461 for (i = 0; i < adapter->num_tx_queues; i++)
5462 restart_queue += adapter->tx_ring[i]->restart_queue;
5463 adapter->restart_queue = restart_queue;
5464
5465 for (i = 0; i < adapter->num_rx_queues; i++)
5466 non_eop_descs += adapter->rx_ring[i]->non_eop_descs;
5467 adapter->non_eop_descs = non_eop_descs;
5468
5469 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5470 for (i = 0; i < 8; i++) {
5471 /* for packet buffers not used, the register should read 0 */
5472 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5473 missed_rx += mpc;
5474 hwstats->mpc[i] += mpc;
5475 total_mpc += hwstats->mpc[i];
5476 if (hw->mac.type == ixgbe_mac_82598EB)
5477 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5478 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5479 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5480 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5481 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5482 if (hw->mac.type == ixgbe_mac_82599EB) {
5483 hwstats->pxonrxc[i] +=
5484 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5485 hwstats->pxoffrxc[i] +=
5486 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
5487 hwstats->qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5488 } else {
5489 hwstats->pxonrxc[i] +=
5490 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5491 hwstats->pxoffrxc[i] +=
5492 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
5493 }
5494 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5495 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5496 }
5497 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5498 /* work around hardware counting issue */
5499 hwstats->gprc -= missed_rx;
5500
5501 /* 82598 hardware only has a 32 bit counter in the high register */
5502 if (hw->mac.type == ixgbe_mac_82599EB) {
5503 u64 tmp;
5504 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5505 tmp = IXGBE_READ_REG(hw, IXGBE_GORCH) & 0xF;
5506 /* 4 high bits of GORC */
5507 hwstats->gorc += (tmp << 32);
5508 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5509 tmp = IXGBE_READ_REG(hw, IXGBE_GOTCH) & 0xF;
5510 /* 4 high bits of GOTC */
5511 hwstats->gotc += (tmp << 32);
5512 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5513 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5514 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5515 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
5516 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5517 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5518 #ifdef IXGBE_FCOE
5519 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5520 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5521 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5522 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5523 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5524 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5525 #endif /* IXGBE_FCOE */
5526 } else {
5527 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5528 hwstats->lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
5529 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5530 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5531 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5532 }
5533 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5534 hwstats->bprc += bprc;
5535 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5536 if (hw->mac.type == ixgbe_mac_82598EB)
5537 hwstats->mprc -= bprc;
5538 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5539 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5540 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5541 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5542 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5543 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5544 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5545 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5546 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5547 hwstats->lxontxc += lxon;
5548 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5549 hwstats->lxofftxc += lxoff;
5550 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5551 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5552 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5553 /*
5554 * 82598 errata - tx of flow control packets is included in tx counters
5555 */
5556 xon_off_tot = lxon + lxoff;
5557 hwstats->gptc -= xon_off_tot;
5558 hwstats->mptc -= xon_off_tot;
5559 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5560 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5561 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5562 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5563 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5564 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5565 hwstats->ptc64 -= xon_off_tot;
5566 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5567 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5568 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5569 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5570 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5571 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5572
5573 /* Fill out the OS statistics structure */
5574 netdev->stats.multicast = hwstats->mprc;
5575
5576 /* Rx Errors */
5577 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5578 netdev->stats.rx_dropped = 0;
5579 netdev->stats.rx_length_errors = hwstats->rlec;
5580 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5581 netdev->stats.rx_missed_errors = total_mpc;
5582 }
5583
5584 /**
5585 * ixgbe_watchdog - Timer Call-back
5586 * @data: pointer to adapter cast into an unsigned long
5587 **/
5588 static void ixgbe_watchdog(unsigned long data)
5589 {
5590 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
5591 struct ixgbe_hw *hw = &adapter->hw;
5592 u64 eics = 0;
5593 int i;
5594
5595 /*
5596 * Do the watchdog outside of interrupt context due to the lovely
5597 * delays that some of the newer hardware requires
5598 */
5599
5600 if (test_bit(__IXGBE_DOWN, &adapter->state))
5601 goto watchdog_short_circuit;
5602
5603 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5604 /*
5605 * for legacy and MSI interrupts don't set any bits
5606 * that are enabled for EIAM, because this operation
5607 * would set *both* EIMS and EICS for any bit in EIAM
5608 */
5609 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5610 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5611 goto watchdog_reschedule;
5612 }
5613
5614 /* get one bit for every active tx/rx interrupt vector */
5615 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5616 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5617 if (qv->rxr_count || qv->txr_count)
5618 eics |= ((u64)1 << i);
5619 }
5620
5621 /* Cause software interrupt to ensure rx rings are cleaned */
5622 ixgbe_irq_rearm_queues(adapter, eics);
5623
5624 watchdog_reschedule:
5625 /* Reset the timer */
5626 mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
5627
5628 watchdog_short_circuit:
5629 schedule_work(&adapter->watchdog_task);
5630 }
5631
5632 /**
5633 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5634 * @work: pointer to work_struct containing our data
5635 **/
5636 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
5637 {
5638 struct ixgbe_adapter *adapter = container_of(work,
5639 struct ixgbe_adapter,
5640 multispeed_fiber_task);
5641 struct ixgbe_hw *hw = &adapter->hw;
5642 u32 autoneg;
5643 bool negotiation;
5644
5645 adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
5646 autoneg = hw->phy.autoneg_advertised;
5647 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
5648 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
5649 hw->mac.autotry_restart = false;
5650 if (hw->mac.ops.setup_link)
5651 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
5652 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5653 adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
5654 }
5655
5656 /**
5657 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5658 * @work: pointer to work_struct containing our data
5659 **/
5660 static void ixgbe_sfp_config_module_task(struct work_struct *work)
5661 {
5662 struct ixgbe_adapter *adapter = container_of(work,
5663 struct ixgbe_adapter,
5664 sfp_config_module_task);
5665 struct ixgbe_hw *hw = &adapter->hw;
5666 u32 err;
5667
5668 adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
5669
5670 /* Time for electrical oscillations to settle down */
5671 msleep(100);
5672 err = hw->phy.ops.identify_sfp(hw);
5673
5674 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5675 e_dev_err("failed to initialize because an unsupported SFP+ "
5676 "module type was detected.\n");
5677 e_dev_err("Reload the driver after installing a supported "
5678 "module.\n");
5679 unregister_netdev(adapter->netdev);
5680 return;
5681 }
5682 hw->mac.ops.setup_sfp(hw);
5683
5684 if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
5685 /* This will also work for DA Twinax connections */
5686 schedule_work(&adapter->multispeed_fiber_task);
5687 adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
5688 }
5689
5690 /**
5691 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5692 * @work: pointer to work_struct containing our data
5693 **/
5694 static void ixgbe_fdir_reinit_task(struct work_struct *work)
5695 {
5696 struct ixgbe_adapter *adapter = container_of(work,
5697 struct ixgbe_adapter,
5698 fdir_reinit_task);
5699 struct ixgbe_hw *hw = &adapter->hw;
5700 int i;
5701
5702 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5703 for (i = 0; i < adapter->num_tx_queues; i++)
5704 set_bit(__IXGBE_FDIR_INIT_DONE,
5705 &(adapter->tx_ring[i]->reinit_state));
5706 } else {
5707 e_err(probe, "failed to finish FDIR re-initialization, "
5708 "ignored adding FDIR ATR filters\n");
5709 }
5710 /* Done FDIR Re-initialization, enable transmits */
5711 netif_tx_start_all_queues(adapter->netdev);
5712 }
5713
5714 static DEFINE_MUTEX(ixgbe_watchdog_lock);
5715
5716 /**
5717 * ixgbe_watchdog_task - worker thread to bring link up
5718 * @work: pointer to work_struct containing our data
5719 **/
5720 static void ixgbe_watchdog_task(struct work_struct *work)
5721 {
5722 struct ixgbe_adapter *adapter = container_of(work,
5723 struct ixgbe_adapter,
5724 watchdog_task);
5725 struct net_device *netdev = adapter->netdev;
5726 struct ixgbe_hw *hw = &adapter->hw;
5727 u32 link_speed;
5728 bool link_up;
5729 int i;
5730 struct ixgbe_ring *tx_ring;
5731 int some_tx_pending = 0;
5732
5733 mutex_lock(&ixgbe_watchdog_lock);
5734
5735 link_up = adapter->link_up;
5736 link_speed = adapter->link_speed;
5737
5738 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
5739 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5740 if (link_up) {
5741 #ifdef CONFIG_DCB
5742 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5743 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5744 hw->mac.ops.fc_enable(hw, i);
5745 } else {
5746 hw->mac.ops.fc_enable(hw, 0);
5747 }
5748 #else
5749 hw->mac.ops.fc_enable(hw, 0);
5750 #endif
5751 }
5752
5753 if (link_up ||
5754 time_after(jiffies, (adapter->link_check_timeout +
5755 IXGBE_TRY_LINK_TIMEOUT))) {
5756 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5757 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5758 }
5759 adapter->link_up = link_up;
5760 adapter->link_speed = link_speed;
5761 }
5762
5763 if (link_up) {
5764 if (!netif_carrier_ok(netdev)) {
5765 bool flow_rx, flow_tx;
5766
5767 if (hw->mac.type == ixgbe_mac_82599EB) {
5768 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
5769 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
5770 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
5771 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
5772 } else {
5773 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5774 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
5775 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
5776 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
5777 }
5778
5779 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
5780 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
5781 "10 Gbps" :
5782 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
5783 "1 Gbps" : "unknown speed")),
5784 ((flow_rx && flow_tx) ? "RX/TX" :
5785 (flow_rx ? "RX" :
5786 (flow_tx ? "TX" : "None"))));
5787
5788 netif_carrier_on(netdev);
5789 } else {
5790 /* Force detection of hung controller */
5791 adapter->detect_tx_hung = true;
5792 }
5793 } else {
5794 adapter->link_up = false;
5795 adapter->link_speed = 0;
5796 if (netif_carrier_ok(netdev)) {
5797 e_info(drv, "NIC Link is Down\n");
5798 netif_carrier_off(netdev);
5799 }
5800 }
5801
5802 if (!netif_carrier_ok(netdev)) {
5803 for (i = 0; i < adapter->num_tx_queues; i++) {
5804 tx_ring = adapter->tx_ring[i];
5805 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
5806 some_tx_pending = 1;
5807 break;
5808 }
5809 }
5810
5811 if (some_tx_pending) {
5812 /* We've lost link, so the controller stops DMA,
5813 * but we've got queued Tx work that's never going
5814 * to get done, so reset controller to flush Tx.
5815 * (Do the reset outside of interrupt context).
5816 */
5817 schedule_work(&adapter->reset_task);
5818 }
5819 }
5820
5821 ixgbe_update_stats(adapter);
5822 mutex_unlock(&ixgbe_watchdog_lock);
5823 }
5824
5825 static int ixgbe_tso(struct ixgbe_adapter *adapter,
5826 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
5827 u32 tx_flags, u8 *hdr_len, __be16 protocol)
5828 {
5829 struct ixgbe_adv_tx_context_desc *context_desc;
5830 unsigned int i;
5831 int err;
5832 struct ixgbe_tx_buffer *tx_buffer_info;
5833 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
5834 u32 mss_l4len_idx, l4len;
5835
5836 if (skb_is_gso(skb)) {
5837 if (skb_header_cloned(skb)) {
5838 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
5839 if (err)
5840 return err;
5841 }
5842 l4len = tcp_hdrlen(skb);
5843 *hdr_len += l4len;
5844
5845 if (protocol == htons(ETH_P_IP)) {
5846 struct iphdr *iph = ip_hdr(skb);
5847 iph->tot_len = 0;
5848 iph->check = 0;
5849 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5850 iph->daddr, 0,
5851 IPPROTO_TCP,
5852 0);
5853 } else if (skb_is_gso_v6(skb)) {
5854 ipv6_hdr(skb)->payload_len = 0;
5855 tcp_hdr(skb)->check =
5856 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
5857 &ipv6_hdr(skb)->daddr,
5858 0, IPPROTO_TCP, 0);
5859 }
5860
5861 i = tx_ring->next_to_use;
5862
5863 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5864 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5865
5866 /* VLAN MACLEN IPLEN */
5867 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5868 vlan_macip_lens |=
5869 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5870 vlan_macip_lens |= ((skb_network_offset(skb)) <<
5871 IXGBE_ADVTXD_MACLEN_SHIFT);
5872 *hdr_len += skb_network_offset(skb);
5873 vlan_macip_lens |=
5874 (skb_transport_header(skb) - skb_network_header(skb));
5875 *hdr_len +=
5876 (skb_transport_header(skb) - skb_network_header(skb));
5877 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5878 context_desc->seqnum_seed = 0;
5879
5880 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5881 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
5882 IXGBE_ADVTXD_DTYP_CTXT);
5883
5884 if (protocol == htons(ETH_P_IP))
5885 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
5886 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5887 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5888
5889 /* MSS L4LEN IDX */
5890 mss_l4len_idx =
5891 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
5892 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
5893 /* use index 1 for TSO */
5894 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5895 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
5896
5897 tx_buffer_info->time_stamp = jiffies;
5898 tx_buffer_info->next_to_watch = i;
5899
5900 i++;
5901 if (i == tx_ring->count)
5902 i = 0;
5903 tx_ring->next_to_use = i;
5904
5905 return true;
5906 }
5907 return false;
5908 }
5909
5910 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5911 __be16 protocol)
5912 {
5913 u32 rtn = 0;
5914
5915 switch (protocol) {
5916 case cpu_to_be16(ETH_P_IP):
5917 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
5918 switch (ip_hdr(skb)->protocol) {
5919 case IPPROTO_TCP:
5920 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5921 break;
5922 case IPPROTO_SCTP:
5923 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5924 break;
5925 }
5926 break;
5927 case cpu_to_be16(ETH_P_IPV6):
5928 /* XXX what about other V6 headers?? */
5929 switch (ipv6_hdr(skb)->nexthdr) {
5930 case IPPROTO_TCP:
5931 rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
5932 break;
5933 case IPPROTO_SCTP:
5934 rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
5935 break;
5936 }
5937 break;
5938 default:
5939 if (unlikely(net_ratelimit()))
5940 e_warn(probe, "partial checksum but proto=%x!\n",
5941 protocol);
5942 break;
5943 }
5944
5945 return rtn;
5946 }
5947
5948 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
5949 struct ixgbe_ring *tx_ring,
5950 struct sk_buff *skb, u32 tx_flags,
5951 __be16 protocol)
5952 {
5953 struct ixgbe_adv_tx_context_desc *context_desc;
5954 unsigned int i;
5955 struct ixgbe_tx_buffer *tx_buffer_info;
5956 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
5957
5958 if (skb->ip_summed == CHECKSUM_PARTIAL ||
5959 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
5960 i = tx_ring->next_to_use;
5961 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5962 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
5963
5964 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
5965 vlan_macip_lens |=
5966 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
5967 vlan_macip_lens |= (skb_network_offset(skb) <<
5968 IXGBE_ADVTXD_MACLEN_SHIFT);
5969 if (skb->ip_summed == CHECKSUM_PARTIAL)
5970 vlan_macip_lens |= (skb_transport_header(skb) -
5971 skb_network_header(skb));
5972
5973 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
5974 context_desc->seqnum_seed = 0;
5975
5976 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
5977 IXGBE_ADVTXD_DTYP_CTXT);
5978
5979 if (skb->ip_summed == CHECKSUM_PARTIAL)
5980 type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
5981
5982 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
5983 /* use index zero for tx checksum offload */
5984 context_desc->mss_l4len_idx = 0;
5985
5986 tx_buffer_info->time_stamp = jiffies;
5987 tx_buffer_info->next_to_watch = i;
5988
5989 i++;
5990 if (i == tx_ring->count)
5991 i = 0;
5992 tx_ring->next_to_use = i;
5993
5994 return true;
5995 }
5996
5997 return false;
5998 }
5999
6000 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6001 struct ixgbe_ring *tx_ring,
6002 struct sk_buff *skb, u32 tx_flags,
6003 unsigned int first)
6004 {
6005 struct pci_dev *pdev = adapter->pdev;
6006 struct ixgbe_tx_buffer *tx_buffer_info;
6007 unsigned int len;
6008 unsigned int total = skb->len;
6009 unsigned int offset = 0, size, count = 0, i;
6010 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6011 unsigned int f;
6012
6013 i = tx_ring->next_to_use;
6014
6015 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6016 /* excluding fcoe_crc_eof for FCoE */
6017 total -= sizeof(struct fcoe_crc_eof);
6018
6019 len = min(skb_headlen(skb), total);
6020 while (len) {
6021 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6022 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6023
6024 tx_buffer_info->length = size;
6025 tx_buffer_info->mapped_as_page = false;
6026 tx_buffer_info->dma = dma_map_single(&pdev->dev,
6027 skb->data + offset,
6028 size, DMA_TO_DEVICE);
6029 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6030 goto dma_error;
6031 tx_buffer_info->time_stamp = jiffies;
6032 tx_buffer_info->next_to_watch = i;
6033
6034 len -= size;
6035 total -= size;
6036 offset += size;
6037 count++;
6038
6039 if (len) {
6040 i++;
6041 if (i == tx_ring->count)
6042 i = 0;
6043 }
6044 }
6045
6046 for (f = 0; f < nr_frags; f++) {
6047 struct skb_frag_struct *frag;
6048
6049 frag = &skb_shinfo(skb)->frags[f];
6050 len = min((unsigned int)frag->size, total);
6051 offset = frag->page_offset;
6052
6053 while (len) {
6054 i++;
6055 if (i == tx_ring->count)
6056 i = 0;
6057
6058 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6059 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6060
6061 tx_buffer_info->length = size;
6062 tx_buffer_info->dma = dma_map_page(&adapter->pdev->dev,
6063 frag->page,
6064 offset, size,
6065 DMA_TO_DEVICE);
6066 tx_buffer_info->mapped_as_page = true;
6067 if (dma_mapping_error(&pdev->dev, tx_buffer_info->dma))
6068 goto dma_error;
6069 tx_buffer_info->time_stamp = jiffies;
6070 tx_buffer_info->next_to_watch = i;
6071
6072 len -= size;
6073 total -= size;
6074 offset += size;
6075 count++;
6076 }
6077 if (total == 0)
6078 break;
6079 }
6080
6081 tx_ring->tx_buffer_info[i].skb = skb;
6082 tx_ring->tx_buffer_info[first].next_to_watch = i;
6083
6084 return count;
6085
6086 dma_error:
6087 e_dev_err("TX DMA map failed\n");
6088
6089 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6090 tx_buffer_info->dma = 0;
6091 tx_buffer_info->time_stamp = 0;
6092 tx_buffer_info->next_to_watch = 0;
6093 if (count)
6094 count--;
6095
6096 /* clear timestamp and dma mappings for remaining portion of packet */
6097 while (count--) {
6098 if (i == 0)
6099 i += tx_ring->count;
6100 i--;
6101 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6102 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
6103 }
6104
6105 return 0;
6106 }
6107
6108 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
6109 struct ixgbe_ring *tx_ring,
6110 int tx_flags, int count, u32 paylen, u8 hdr_len)
6111 {
6112 union ixgbe_adv_tx_desc *tx_desc = NULL;
6113 struct ixgbe_tx_buffer *tx_buffer_info;
6114 u32 olinfo_status = 0, cmd_type_len = 0;
6115 unsigned int i;
6116 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6117
6118 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6119
6120 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6121
6122 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6123 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6124
6125 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6126 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6127
6128 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6129 IXGBE_ADVTXD_POPTS_SHIFT;
6130
6131 /* use index 1 context for tso */
6132 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6133 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6134 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6135 IXGBE_ADVTXD_POPTS_SHIFT;
6136
6137 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6138 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6139 IXGBE_ADVTXD_POPTS_SHIFT;
6140
6141 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6142 olinfo_status |= IXGBE_ADVTXD_CC;
6143 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6144 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6145 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6146 }
6147
6148 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6149
6150 i = tx_ring->next_to_use;
6151 while (count--) {
6152 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6153 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6154 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6155 tx_desc->read.cmd_type_len =
6156 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6157 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6158 i++;
6159 if (i == tx_ring->count)
6160 i = 0;
6161 }
6162
6163 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6164
6165 /*
6166 * Force memory writes to complete before letting h/w
6167 * know there are new descriptors to fetch. (Only
6168 * applicable for weak-ordered memory model archs,
6169 * such as IA-64).
6170 */
6171 wmb();
6172
6173 tx_ring->next_to_use = i;
6174 writel(i, adapter->hw.hw_addr + tx_ring->tail);
6175 }
6176
6177 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6178 int queue, u32 tx_flags, __be16 protocol)
6179 {
6180 struct ixgbe_atr_input atr_input;
6181 struct tcphdr *th;
6182 struct iphdr *iph = ip_hdr(skb);
6183 struct ethhdr *eth = (struct ethhdr *)skb->data;
6184 u16 vlan_id, src_port, dst_port, flex_bytes;
6185 u32 src_ipv4_addr, dst_ipv4_addr;
6186 u8 l4type = 0;
6187
6188 /* Right now, we support IPv4 only */
6189 if (protocol != htons(ETH_P_IP))
6190 return;
6191 /* check if we're UDP or TCP */
6192 if (iph->protocol == IPPROTO_TCP) {
6193 th = tcp_hdr(skb);
6194 src_port = th->source;
6195 dst_port = th->dest;
6196 l4type |= IXGBE_ATR_L4TYPE_TCP;
6197 /* l4type IPv4 type is 0, no need to assign */
6198 } else {
6199 /* Unsupported L4 header, just bail here */
6200 return;
6201 }
6202
6203 memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
6204
6205 vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
6206 IXGBE_TX_FLAGS_VLAN_SHIFT;
6207 src_ipv4_addr = iph->saddr;
6208 dst_ipv4_addr = iph->daddr;
6209 flex_bytes = eth->h_proto;
6210
6211 ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
6212 ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
6213 ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
6214 ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
6215 ixgbe_atr_set_l4type_82599(&atr_input, l4type);
6216 /* src and dst are inverted, think how the receiver sees them */
6217 ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
6218 ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
6219
6220 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6221 ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
6222 }
6223
6224 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
6225 struct ixgbe_ring *tx_ring, int size)
6226 {
6227 netif_stop_subqueue(netdev, tx_ring->queue_index);
6228 /* Herbert's original patch had:
6229 * smp_mb__after_netif_stop_queue();
6230 * but since that doesn't exist yet, just open code it. */
6231 smp_mb();
6232
6233 /* We need to check again in a case another CPU has just
6234 * made room available. */
6235 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6236 return -EBUSY;
6237
6238 /* A reprieve! - use start_queue because it doesn't call schedule */
6239 netif_start_subqueue(netdev, tx_ring->queue_index);
6240 ++tx_ring->restart_queue;
6241 return 0;
6242 }
6243
6244 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
6245 struct ixgbe_ring *tx_ring, int size)
6246 {
6247 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6248 return 0;
6249 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
6250 }
6251
6252 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6253 {
6254 struct ixgbe_adapter *adapter = netdev_priv(dev);
6255 int txq = smp_processor_id();
6256 #ifdef IXGBE_FCOE
6257 __be16 protocol;
6258
6259 protocol = vlan_get_protocol(skb);
6260
6261 if ((protocol == htons(ETH_P_FCOE)) ||
6262 (protocol == htons(ETH_P_FIP))) {
6263 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
6264 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6265 txq += adapter->ring_feature[RING_F_FCOE].mask;
6266 return txq;
6267 #ifdef CONFIG_IXGBE_DCB
6268 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6269 txq = adapter->fcoe.up;
6270 return txq;
6271 #endif
6272 }
6273 }
6274 #endif
6275
6276 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6277 while (unlikely(txq >= dev->real_num_tx_queues))
6278 txq -= dev->real_num_tx_queues;
6279 return txq;
6280 }
6281
6282 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6283 if (skb->priority == TC_PRIO_CONTROL)
6284 txq = adapter->ring_feature[RING_F_DCB].indices-1;
6285 else
6286 txq = (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK)
6287 >> 13;
6288 return txq;
6289 }
6290
6291 return skb_tx_hash(dev, skb);
6292 }
6293
6294 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb, struct net_device *netdev,
6295 struct ixgbe_adapter *adapter,
6296 struct ixgbe_ring *tx_ring)
6297 {
6298 struct netdev_queue *txq;
6299 unsigned int first;
6300 unsigned int tx_flags = 0;
6301 u8 hdr_len = 0;
6302 int tso;
6303 int count = 0;
6304 unsigned int f;
6305 __be16 protocol;
6306
6307 protocol = vlan_get_protocol(skb);
6308
6309 if (vlan_tx_tag_present(skb)) {
6310 tx_flags |= vlan_tx_tag_get(skb);
6311 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6312 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6313 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6314 }
6315 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6316 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6317 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6318 skb->priority != TC_PRIO_CONTROL) {
6319 tx_flags |= ((skb->queue_mapping & 0x7) << 13);
6320 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6321 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6322 }
6323
6324 #ifdef IXGBE_FCOE
6325 /* for FCoE with DCB, we force the priority to what
6326 * was specified by the switch */
6327 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6328 (protocol == htons(ETH_P_FCOE) ||
6329 protocol == htons(ETH_P_FIP))) {
6330 #ifdef CONFIG_IXGBE_DCB
6331 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6332 tx_flags &= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6333 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6334 tx_flags |= ((adapter->fcoe.up << 13)
6335 << IXGBE_TX_FLAGS_VLAN_SHIFT);
6336 }
6337 #endif
6338 /* flag for FCoE offloads */
6339 if (protocol == htons(ETH_P_FCOE))
6340 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6341 }
6342 #endif
6343
6344 /* four things can cause us to need a context descriptor */
6345 if (skb_is_gso(skb) ||
6346 (skb->ip_summed == CHECKSUM_PARTIAL) ||
6347 (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6348 (tx_flags & IXGBE_TX_FLAGS_FCOE))
6349 count++;
6350
6351 count += TXD_USE_COUNT(skb_headlen(skb));
6352 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6353 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6354
6355 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
6356 adapter->tx_busy++;
6357 return NETDEV_TX_BUSY;
6358 }
6359
6360 first = tx_ring->next_to_use;
6361 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6362 #ifdef IXGBE_FCOE
6363 /* setup tx offload for FCoE */
6364 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6365 if (tso < 0) {
6366 dev_kfree_skb_any(skb);
6367 return NETDEV_TX_OK;
6368 }
6369 if (tso)
6370 tx_flags |= IXGBE_TX_FLAGS_FSO;
6371 #endif /* IXGBE_FCOE */
6372 } else {
6373 if (protocol == htons(ETH_P_IP))
6374 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6375 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6376 protocol);
6377 if (tso < 0) {
6378 dev_kfree_skb_any(skb);
6379 return NETDEV_TX_OK;
6380 }
6381
6382 if (tso)
6383 tx_flags |= IXGBE_TX_FLAGS_TSO;
6384 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6385 protocol) &&
6386 (skb->ip_summed == CHECKSUM_PARTIAL))
6387 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6388 }
6389
6390 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
6391 if (count) {
6392 /* add the ATR filter if ATR is on */
6393 if (tx_ring->atr_sample_rate) {
6394 ++tx_ring->atr_count;
6395 if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
6396 test_bit(__IXGBE_FDIR_INIT_DONE,
6397 &tx_ring->reinit_state)) {
6398 ixgbe_atr(adapter, skb, tx_ring->queue_index,
6399 tx_flags, protocol);
6400 tx_ring->atr_count = 0;
6401 }
6402 }
6403 txq = netdev_get_tx_queue(netdev, tx_ring->queue_index);
6404 txq->tx_bytes += skb->len;
6405 txq->tx_packets++;
6406 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
6407 hdr_len);
6408 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
6409
6410 } else {
6411 dev_kfree_skb_any(skb);
6412 tx_ring->tx_buffer_info[first].time_stamp = 0;
6413 tx_ring->next_to_use = first;
6414 }
6415
6416 return NETDEV_TX_OK;
6417 }
6418
6419 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6420 {
6421 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6422 struct ixgbe_ring *tx_ring;
6423
6424 tx_ring = adapter->tx_ring[skb->queue_mapping];
6425 return ixgbe_xmit_frame_ring(skb, netdev, adapter, tx_ring);
6426 }
6427
6428 /**
6429 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6430 * @netdev: network interface device structure
6431 * @p: pointer to an address structure
6432 *
6433 * Returns 0 on success, negative on failure
6434 **/
6435 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6436 {
6437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6438 struct ixgbe_hw *hw = &adapter->hw;
6439 struct sockaddr *addr = p;
6440
6441 if (!is_valid_ether_addr(addr->sa_data))
6442 return -EADDRNOTAVAIL;
6443
6444 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6445 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6446
6447 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6448 IXGBE_RAH_AV);
6449
6450 return 0;
6451 }
6452
6453 static int
6454 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6455 {
6456 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6457 struct ixgbe_hw *hw = &adapter->hw;
6458 u16 value;
6459 int rc;
6460
6461 if (prtad != hw->phy.mdio.prtad)
6462 return -EINVAL;
6463 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6464 if (!rc)
6465 rc = value;
6466 return rc;
6467 }
6468
6469 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6470 u16 addr, u16 value)
6471 {
6472 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6473 struct ixgbe_hw *hw = &adapter->hw;
6474
6475 if (prtad != hw->phy.mdio.prtad)
6476 return -EINVAL;
6477 return hw->phy.ops.write_reg(hw, addr, devad, value);
6478 }
6479
6480 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6481 {
6482 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6483
6484 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6485 }
6486
6487 /**
6488 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6489 * netdev->dev_addrs
6490 * @netdev: network interface device structure
6491 *
6492 * Returns non-zero on failure
6493 **/
6494 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6495 {
6496 int err = 0;
6497 struct ixgbe_adapter *adapter = netdev_priv(dev);
6498 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6499
6500 if (is_valid_ether_addr(mac->san_addr)) {
6501 rtnl_lock();
6502 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6503 rtnl_unlock();
6504 }
6505 return err;
6506 }
6507
6508 /**
6509 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6510 * netdev->dev_addrs
6511 * @netdev: network interface device structure
6512 *
6513 * Returns non-zero on failure
6514 **/
6515 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
6516 {
6517 int err = 0;
6518 struct ixgbe_adapter *adapter = netdev_priv(dev);
6519 struct ixgbe_mac_info *mac = &adapter->hw.mac;
6520
6521 if (is_valid_ether_addr(mac->san_addr)) {
6522 rtnl_lock();
6523 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
6524 rtnl_unlock();
6525 }
6526 return err;
6527 }
6528
6529 #ifdef CONFIG_NET_POLL_CONTROLLER
6530 /*
6531 * Polling 'interrupt' - used by things like netconsole to send skbs
6532 * without having to re-enable interrupts. It's not called while
6533 * the interrupt routine is executing.
6534 */
6535 static void ixgbe_netpoll(struct net_device *netdev)
6536 {
6537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6538 int i;
6539
6540 /* if interface is down do nothing */
6541 if (test_bit(__IXGBE_DOWN, &adapter->state))
6542 return;
6543
6544 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
6545 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
6546 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
6547 for (i = 0; i < num_q_vectors; i++) {
6548 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
6549 ixgbe_msix_clean_many(0, q_vector);
6550 }
6551 } else {
6552 ixgbe_intr(adapter->pdev->irq, netdev);
6553 }
6554 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
6555 }
6556 #endif
6557
6558 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
6559 struct rtnl_link_stats64 *stats)
6560 {
6561 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6562 int i;
6563
6564 /* accurate rx/tx bytes/packets stats */
6565 dev_txq_stats_fold(netdev, stats);
6566 for (i = 0; i < adapter->num_rx_queues; i++) {
6567 struct ixgbe_ring *ring = adapter->rx_ring[i];
6568 u64 bytes, packets;
6569 unsigned int start;
6570
6571 do {
6572 start = u64_stats_fetch_begin_bh(&ring->syncp);
6573 packets = ring->stats.packets;
6574 bytes = ring->stats.bytes;
6575 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
6576 stats->rx_packets += packets;
6577 stats->rx_bytes += bytes;
6578 }
6579
6580 /* following stats updated by ixgbe_watchdog_task() */
6581 stats->multicast = netdev->stats.multicast;
6582 stats->rx_errors = netdev->stats.rx_errors;
6583 stats->rx_length_errors = netdev->stats.rx_length_errors;
6584 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
6585 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
6586 return stats;
6587 }
6588
6589
6590 static const struct net_device_ops ixgbe_netdev_ops = {
6591 .ndo_open = ixgbe_open,
6592 .ndo_stop = ixgbe_close,
6593 .ndo_start_xmit = ixgbe_xmit_frame,
6594 .ndo_select_queue = ixgbe_select_queue,
6595 .ndo_set_rx_mode = ixgbe_set_rx_mode,
6596 .ndo_set_multicast_list = ixgbe_set_rx_mode,
6597 .ndo_validate_addr = eth_validate_addr,
6598 .ndo_set_mac_address = ixgbe_set_mac,
6599 .ndo_change_mtu = ixgbe_change_mtu,
6600 .ndo_tx_timeout = ixgbe_tx_timeout,
6601 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
6602 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
6603 .ndo_do_ioctl = ixgbe_ioctl,
6604 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
6605 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
6606 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
6607 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
6608 .ndo_get_stats64 = ixgbe_get_stats64,
6609 #ifdef CONFIG_NET_POLL_CONTROLLER
6610 .ndo_poll_controller = ixgbe_netpoll,
6611 #endif
6612 #ifdef IXGBE_FCOE
6613 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
6614 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
6615 .ndo_fcoe_enable = ixgbe_fcoe_enable,
6616 .ndo_fcoe_disable = ixgbe_fcoe_disable,
6617 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
6618 #endif /* IXGBE_FCOE */
6619 };
6620
6621 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
6622 const struct ixgbe_info *ii)
6623 {
6624 #ifdef CONFIG_PCI_IOV
6625 struct ixgbe_hw *hw = &adapter->hw;
6626 int err;
6627
6628 if (hw->mac.type != ixgbe_mac_82599EB || !max_vfs)
6629 return;
6630
6631 /* The 82599 supports up to 64 VFs per physical function
6632 * but this implementation limits allocation to 63 so that
6633 * basic networking resources are still available to the
6634 * physical function
6635 */
6636 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
6637 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
6638 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
6639 if (err) {
6640 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
6641 goto err_novfs;
6642 }
6643 /* If call to enable VFs succeeded then allocate memory
6644 * for per VF control structures.
6645 */
6646 adapter->vfinfo =
6647 kcalloc(adapter->num_vfs,
6648 sizeof(struct vf_data_storage), GFP_KERNEL);
6649 if (adapter->vfinfo) {
6650 /* Now that we're sure SR-IOV is enabled
6651 * and memory allocated set up the mailbox parameters
6652 */
6653 ixgbe_init_mbx_params_pf(hw);
6654 memcpy(&hw->mbx.ops, ii->mbx_ops,
6655 sizeof(hw->mbx.ops));
6656
6657 /* Disable RSC when in SR-IOV mode */
6658 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
6659 IXGBE_FLAG2_RSC_ENABLED);
6660 return;
6661 }
6662
6663 /* Oh oh */
6664 e_err(probe, "Unable to allocate memory for VF Data Storage - "
6665 "SRIOV disabled\n");
6666 pci_disable_sriov(adapter->pdev);
6667
6668 err_novfs:
6669 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
6670 adapter->num_vfs = 0;
6671 #endif /* CONFIG_PCI_IOV */
6672 }
6673
6674 /**
6675 * ixgbe_probe - Device Initialization Routine
6676 * @pdev: PCI device information struct
6677 * @ent: entry in ixgbe_pci_tbl
6678 *
6679 * Returns 0 on success, negative on failure
6680 *
6681 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6682 * The OS initialization, configuring of the adapter private structure,
6683 * and a hardware reset occur.
6684 **/
6685 static int __devinit ixgbe_probe(struct pci_dev *pdev,
6686 const struct pci_device_id *ent)
6687 {
6688 struct net_device *netdev;
6689 struct ixgbe_adapter *adapter = NULL;
6690 struct ixgbe_hw *hw;
6691 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
6692 static int cards_found;
6693 int i, err, pci_using_dac;
6694 unsigned int indices = num_possible_cpus();
6695 #ifdef IXGBE_FCOE
6696 u16 device_caps;
6697 #endif
6698 u32 part_num, eec;
6699
6700 /* Catch broken hardware that put the wrong VF device ID in
6701 * the PCIe SR-IOV capability.
6702 */
6703 if (pdev->is_virtfn) {
6704 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
6705 pci_name(pdev), pdev->vendor, pdev->device);
6706 return -EINVAL;
6707 }
6708
6709 err = pci_enable_device_mem(pdev);
6710 if (err)
6711 return err;
6712
6713 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
6714 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
6715 pci_using_dac = 1;
6716 } else {
6717 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
6718 if (err) {
6719 err = dma_set_coherent_mask(&pdev->dev,
6720 DMA_BIT_MASK(32));
6721 if (err) {
6722 dev_err(&pdev->dev,
6723 "No usable DMA configuration, aborting\n");
6724 goto err_dma;
6725 }
6726 }
6727 pci_using_dac = 0;
6728 }
6729
6730 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
6731 IORESOURCE_MEM), ixgbe_driver_name);
6732 if (err) {
6733 dev_err(&pdev->dev,
6734 "pci_request_selected_regions failed 0x%x\n", err);
6735 goto err_pci_reg;
6736 }
6737
6738 pci_enable_pcie_error_reporting(pdev);
6739
6740 pci_set_master(pdev);
6741 pci_save_state(pdev);
6742
6743 if (ii->mac == ixgbe_mac_82598EB)
6744 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
6745 else
6746 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
6747
6748 indices = max_t(unsigned int, indices, IXGBE_MAX_DCB_INDICES);
6749 #ifdef IXGBE_FCOE
6750 indices += min_t(unsigned int, num_possible_cpus(),
6751 IXGBE_MAX_FCOE_INDICES);
6752 #endif
6753 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
6754 if (!netdev) {
6755 err = -ENOMEM;
6756 goto err_alloc_etherdev;
6757 }
6758
6759 SET_NETDEV_DEV(netdev, &pdev->dev);
6760
6761 pci_set_drvdata(pdev, netdev);
6762 adapter = netdev_priv(netdev);
6763
6764 adapter->netdev = netdev;
6765 adapter->pdev = pdev;
6766 hw = &adapter->hw;
6767 hw->back = adapter;
6768 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
6769
6770 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
6771 pci_resource_len(pdev, 0));
6772 if (!hw->hw_addr) {
6773 err = -EIO;
6774 goto err_ioremap;
6775 }
6776
6777 for (i = 1; i <= 5; i++) {
6778 if (pci_resource_len(pdev, i) == 0)
6779 continue;
6780 }
6781
6782 netdev->netdev_ops = &ixgbe_netdev_ops;
6783 ixgbe_set_ethtool_ops(netdev);
6784 netdev->watchdog_timeo = 5 * HZ;
6785 strcpy(netdev->name, pci_name(pdev));
6786
6787 adapter->bd_number = cards_found;
6788
6789 /* Setup hw api */
6790 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
6791 hw->mac.type = ii->mac;
6792
6793 /* EEPROM */
6794 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
6795 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
6796 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6797 if (!(eec & (1 << 8)))
6798 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
6799
6800 /* PHY */
6801 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
6802 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
6803 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6804 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
6805 hw->phy.mdio.mmds = 0;
6806 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
6807 hw->phy.mdio.dev = netdev;
6808 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
6809 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
6810
6811 /* set up this timer and work struct before calling get_invariants
6812 * which might start the timer
6813 */
6814 init_timer(&adapter->sfp_timer);
6815 adapter->sfp_timer.function = ixgbe_sfp_timer;
6816 adapter->sfp_timer.data = (unsigned long) adapter;
6817
6818 INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
6819
6820 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6821 INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
6822
6823 /* a new SFP+ module arrival, called from GPI SDP2 context */
6824 INIT_WORK(&adapter->sfp_config_module_task,
6825 ixgbe_sfp_config_module_task);
6826
6827 ii->get_invariants(hw);
6828
6829 /* setup the private structure */
6830 err = ixgbe_sw_init(adapter);
6831 if (err)
6832 goto err_sw_init;
6833
6834 /* Make it possible the adapter to be woken up via WOL */
6835 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6837
6838 /*
6839 * If there is a fan on this device and it has failed log the
6840 * failure.
6841 */
6842 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
6843 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
6844 if (esdp & IXGBE_ESDP_SDP1)
6845 e_crit(probe, "Fan has stopped, replace the adapter\n");
6846 }
6847
6848 /* reset_hw fills in the perm_addr as well */
6849 hw->phy.reset_if_overtemp = true;
6850 err = hw->mac.ops.reset_hw(hw);
6851 hw->phy.reset_if_overtemp = false;
6852 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
6853 hw->mac.type == ixgbe_mac_82598EB) {
6854 /*
6855 * Start a kernel thread to watch for a module to arrive.
6856 * Only do this for 82598, since 82599 will generate
6857 * interrupts on module arrival.
6858 */
6859 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
6860 mod_timer(&adapter->sfp_timer,
6861 round_jiffies(jiffies + (2 * HZ)));
6862 err = 0;
6863 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
6864 e_dev_err("failed to initialize because an unsupported SFP+ "
6865 "module type was detected.\n");
6866 e_dev_err("Reload the driver after installing a supported "
6867 "module.\n");
6868 goto err_sw_init;
6869 } else if (err) {
6870 e_dev_err("HW Init failed: %d\n", err);
6871 goto err_sw_init;
6872 }
6873
6874 ixgbe_probe_vf(adapter, ii);
6875
6876 netdev->features = NETIF_F_SG |
6877 NETIF_F_IP_CSUM |
6878 NETIF_F_HW_VLAN_TX |
6879 NETIF_F_HW_VLAN_RX |
6880 NETIF_F_HW_VLAN_FILTER;
6881
6882 netdev->features |= NETIF_F_IPV6_CSUM;
6883 netdev->features |= NETIF_F_TSO;
6884 netdev->features |= NETIF_F_TSO6;
6885 netdev->features |= NETIF_F_GRO;
6886
6887 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
6888 netdev->features |= NETIF_F_SCTP_CSUM;
6889
6890 netdev->vlan_features |= NETIF_F_TSO;
6891 netdev->vlan_features |= NETIF_F_TSO6;
6892 netdev->vlan_features |= NETIF_F_IP_CSUM;
6893 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
6894 netdev->vlan_features |= NETIF_F_SG;
6895
6896 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
6897 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
6898 IXGBE_FLAG_DCB_ENABLED);
6899 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
6900 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
6901
6902 #ifdef CONFIG_IXGBE_DCB
6903 netdev->dcbnl_ops = &dcbnl_ops;
6904 #endif
6905
6906 #ifdef IXGBE_FCOE
6907 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6908 if (hw->mac.ops.get_device_caps) {
6909 hw->mac.ops.get_device_caps(hw, &device_caps);
6910 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
6911 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6912 }
6913 }
6914 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
6915 netdev->vlan_features |= NETIF_F_FCOE_CRC;
6916 netdev->vlan_features |= NETIF_F_FSO;
6917 netdev->vlan_features |= NETIF_F_FCOE_MTU;
6918 }
6919 #endif /* IXGBE_FCOE */
6920 if (pci_using_dac) {
6921 netdev->features |= NETIF_F_HIGHDMA;
6922 netdev->vlan_features |= NETIF_F_HIGHDMA;
6923 }
6924
6925 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
6926 netdev->features |= NETIF_F_LRO;
6927
6928 /* make sure the EEPROM is good */
6929 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
6930 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6931 err = -EIO;
6932 goto err_eeprom;
6933 }
6934
6935 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
6936 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
6937
6938 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
6939 e_dev_err("invalid MAC address\n");
6940 err = -EIO;
6941 goto err_eeprom;
6942 }
6943
6944 /* power down the optics */
6945 if (hw->phy.multispeed_fiber)
6946 hw->mac.ops.disable_tx_laser(hw);
6947
6948 init_timer(&adapter->watchdog_timer);
6949 adapter->watchdog_timer.function = ixgbe_watchdog;
6950 adapter->watchdog_timer.data = (unsigned long)adapter;
6951
6952 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
6953 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
6954
6955 err = ixgbe_init_interrupt_scheme(adapter);
6956 if (err)
6957 goto err_sw_init;
6958
6959 switch (pdev->device) {
6960 case IXGBE_DEV_ID_82599_KX4:
6961 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
6962 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
6963 break;
6964 default:
6965 adapter->wol = 0;
6966 break;
6967 }
6968 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
6969
6970 /* pick up the PCI bus settings for reporting later */
6971 hw->mac.ops.get_bus_info(hw);
6972
6973 /* print bus type/speed/width info */
6974 e_dev_info("(PCI Express:%s:%s) %pM\n",
6975 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0Gb/s" :
6976 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5Gb/s" :
6977 "Unknown"),
6978 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
6979 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
6980 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
6981 "Unknown"),
6982 netdev->dev_addr);
6983 ixgbe_read_pba_num_generic(hw, &part_num);
6984 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
6985 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6986 "PBA No: %06x-%03x\n",
6987 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
6988 (part_num >> 8), (part_num & 0xff));
6989 else
6990 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6991 hw->mac.type, hw->phy.type,
6992 (part_num >> 8), (part_num & 0xff));
6993
6994 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
6995 e_dev_warn("PCI-Express bandwidth available for this card is "
6996 "not sufficient for optimal performance.\n");
6997 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6998 "is required.\n");
6999 }
7000
7001 /* save off EEPROM version number */
7002 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7003
7004 /* reset the hardware with the new settings */
7005 err = hw->mac.ops.start_hw(hw);
7006
7007 if (err == IXGBE_ERR_EEPROM_VERSION) {
7008 /* We are running on a pre-production device, log a warning */
7009 e_dev_warn("This device is a pre-production adapter/LOM. "
7010 "Please be aware there may be issues associated "
7011 "with your hardware. If you are experiencing "
7012 "problems please contact your Intel or hardware "
7013 "representative who provided you with this "
7014 "hardware.\n");
7015 }
7016 strcpy(netdev->name, "eth%d");
7017 err = register_netdev(netdev);
7018 if (err)
7019 goto err_register;
7020
7021 /* carrier off reporting is important to ethtool even BEFORE open */
7022 netif_carrier_off(netdev);
7023
7024 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7025 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7026 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
7027
7028 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
7029 INIT_WORK(&adapter->check_overtemp_task,
7030 ixgbe_check_overtemp_task);
7031 #ifdef CONFIG_IXGBE_DCA
7032 if (dca_add_requester(&pdev->dev) == 0) {
7033 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7034 ixgbe_setup_dca(adapter);
7035 }
7036 #endif
7037 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7038 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7039 for (i = 0; i < adapter->num_vfs; i++)
7040 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7041 }
7042
7043 /* add san mac addr to netdev */
7044 ixgbe_add_sanmac_netdev(netdev);
7045
7046 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7047 cards_found++;
7048 return 0;
7049
7050 err_register:
7051 ixgbe_release_hw_control(adapter);
7052 ixgbe_clear_interrupt_scheme(adapter);
7053 err_sw_init:
7054 err_eeprom:
7055 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7056 ixgbe_disable_sriov(adapter);
7057 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7058 del_timer_sync(&adapter->sfp_timer);
7059 cancel_work_sync(&adapter->sfp_task);
7060 cancel_work_sync(&adapter->multispeed_fiber_task);
7061 cancel_work_sync(&adapter->sfp_config_module_task);
7062 iounmap(hw->hw_addr);
7063 err_ioremap:
7064 free_netdev(netdev);
7065 err_alloc_etherdev:
7066 pci_release_selected_regions(pdev,
7067 pci_select_bars(pdev, IORESOURCE_MEM));
7068 err_pci_reg:
7069 err_dma:
7070 pci_disable_device(pdev);
7071 return err;
7072 }
7073
7074 /**
7075 * ixgbe_remove - Device Removal Routine
7076 * @pdev: PCI device information struct
7077 *
7078 * ixgbe_remove is called by the PCI subsystem to alert the driver
7079 * that it should release a PCI device. The could be caused by a
7080 * Hot-Plug event, or because the driver is going to be removed from
7081 * memory.
7082 **/
7083 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7084 {
7085 struct net_device *netdev = pci_get_drvdata(pdev);
7086 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7087
7088 set_bit(__IXGBE_DOWN, &adapter->state);
7089 /* clear the module not found bit to make sure the worker won't
7090 * reschedule
7091 */
7092 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
7093 del_timer_sync(&adapter->watchdog_timer);
7094
7095 del_timer_sync(&adapter->sfp_timer);
7096 cancel_work_sync(&adapter->watchdog_task);
7097 cancel_work_sync(&adapter->sfp_task);
7098 cancel_work_sync(&adapter->multispeed_fiber_task);
7099 cancel_work_sync(&adapter->sfp_config_module_task);
7100 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
7101 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
7102 cancel_work_sync(&adapter->fdir_reinit_task);
7103 flush_scheduled_work();
7104
7105 #ifdef CONFIG_IXGBE_DCA
7106 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7107 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7108 dca_remove_requester(&pdev->dev);
7109 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7110 }
7111
7112 #endif
7113 #ifdef IXGBE_FCOE
7114 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7115 ixgbe_cleanup_fcoe(adapter);
7116
7117 #endif /* IXGBE_FCOE */
7118
7119 /* remove the added san mac */
7120 ixgbe_del_sanmac_netdev(netdev);
7121
7122 if (netdev->reg_state == NETREG_REGISTERED)
7123 unregister_netdev(netdev);
7124
7125 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7126 ixgbe_disable_sriov(adapter);
7127
7128 ixgbe_clear_interrupt_scheme(adapter);
7129
7130 ixgbe_release_hw_control(adapter);
7131
7132 iounmap(adapter->hw.hw_addr);
7133 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7134 IORESOURCE_MEM));
7135
7136 e_dev_info("complete\n");
7137
7138 free_netdev(netdev);
7139
7140 pci_disable_pcie_error_reporting(pdev);
7141
7142 pci_disable_device(pdev);
7143 }
7144
7145 /**
7146 * ixgbe_io_error_detected - called when PCI error is detected
7147 * @pdev: Pointer to PCI device
7148 * @state: The current pci connection state
7149 *
7150 * This function is called after a PCI bus error affecting
7151 * this device has been detected.
7152 */
7153 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7154 pci_channel_state_t state)
7155 {
7156 struct net_device *netdev = pci_get_drvdata(pdev);
7157 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7158
7159 netif_device_detach(netdev);
7160
7161 if (state == pci_channel_io_perm_failure)
7162 return PCI_ERS_RESULT_DISCONNECT;
7163
7164 if (netif_running(netdev))
7165 ixgbe_down(adapter);
7166 pci_disable_device(pdev);
7167
7168 /* Request a slot reset. */
7169 return PCI_ERS_RESULT_NEED_RESET;
7170 }
7171
7172 /**
7173 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7174 * @pdev: Pointer to PCI device
7175 *
7176 * Restart the card from scratch, as if from a cold-boot.
7177 */
7178 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7179 {
7180 struct net_device *netdev = pci_get_drvdata(pdev);
7181 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7182 pci_ers_result_t result;
7183 int err;
7184
7185 if (pci_enable_device_mem(pdev)) {
7186 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7187 result = PCI_ERS_RESULT_DISCONNECT;
7188 } else {
7189 pci_set_master(pdev);
7190 pci_restore_state(pdev);
7191 pci_save_state(pdev);
7192
7193 pci_wake_from_d3(pdev, false);
7194
7195 ixgbe_reset(adapter);
7196 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7197 result = PCI_ERS_RESULT_RECOVERED;
7198 }
7199
7200 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7201 if (err) {
7202 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7203 "failed 0x%0x\n", err);
7204 /* non-fatal, continue */
7205 }
7206
7207 return result;
7208 }
7209
7210 /**
7211 * ixgbe_io_resume - called when traffic can start flowing again.
7212 * @pdev: Pointer to PCI device
7213 *
7214 * This callback is called when the error recovery driver tells us that
7215 * its OK to resume normal operation.
7216 */
7217 static void ixgbe_io_resume(struct pci_dev *pdev)
7218 {
7219 struct net_device *netdev = pci_get_drvdata(pdev);
7220 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7221
7222 if (netif_running(netdev)) {
7223 if (ixgbe_up(adapter)) {
7224 e_info(probe, "ixgbe_up failed after reset\n");
7225 return;
7226 }
7227 }
7228
7229 netif_device_attach(netdev);
7230 }
7231
7232 static struct pci_error_handlers ixgbe_err_handler = {
7233 .error_detected = ixgbe_io_error_detected,
7234 .slot_reset = ixgbe_io_slot_reset,
7235 .resume = ixgbe_io_resume,
7236 };
7237
7238 static struct pci_driver ixgbe_driver = {
7239 .name = ixgbe_driver_name,
7240 .id_table = ixgbe_pci_tbl,
7241 .probe = ixgbe_probe,
7242 .remove = __devexit_p(ixgbe_remove),
7243 #ifdef CONFIG_PM
7244 .suspend = ixgbe_suspend,
7245 .resume = ixgbe_resume,
7246 #endif
7247 .shutdown = ixgbe_shutdown,
7248 .err_handler = &ixgbe_err_handler
7249 };
7250
7251 /**
7252 * ixgbe_init_module - Driver Registration Routine
7253 *
7254 * ixgbe_init_module is the first routine called when the driver is
7255 * loaded. All it does is register with the PCI subsystem.
7256 **/
7257 static int __init ixgbe_init_module(void)
7258 {
7259 int ret;
7260 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7261 pr_info("%s\n", ixgbe_copyright);
7262
7263 #ifdef CONFIG_IXGBE_DCA
7264 dca_register_notify(&dca_notifier);
7265 #endif
7266
7267 ret = pci_register_driver(&ixgbe_driver);
7268 return ret;
7269 }
7270
7271 module_init(ixgbe_init_module);
7272
7273 /**
7274 * ixgbe_exit_module - Driver Exit Cleanup Routine
7275 *
7276 * ixgbe_exit_module is called just before the driver is removed
7277 * from memory.
7278 **/
7279 static void __exit ixgbe_exit_module(void)
7280 {
7281 #ifdef CONFIG_IXGBE_DCA
7282 dca_unregister_notify(&dca_notifier);
7283 #endif
7284 pci_unregister_driver(&ixgbe_driver);
7285 }
7286
7287 #ifdef CONFIG_IXGBE_DCA
7288 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7289 void *p)
7290 {
7291 int ret_val;
7292
7293 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7294 __ixgbe_notify_dca);
7295
7296 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7297 }
7298
7299 #endif /* CONFIG_IXGBE_DCA */
7300
7301 /**
7302 * ixgbe_get_hw_dev return device
7303 * used by hardware layer to print debugging information
7304 **/
7305 struct net_device *ixgbe_get_hw_dev(struct ixgbe_hw *hw)
7306 {
7307 struct ixgbe_adapter *adapter = hw->back;
7308 return adapter->netdev;
7309 }
7310
7311 module_exit(ixgbe_exit_module);
7312
7313 /* ixgbe_main.c */
Linux kernel - Deliverables
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