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Merge phase #3 (IOMMU) of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_main.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/ipv6.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #include <linux/ethtool.h>
41 #include <linux/if_vlan.h>
42
43 #include "ixgbe.h"
44 #include "ixgbe_common.h"
45
46 char ixgbe_driver_name[] = "ixgbe";
47 static const char ixgbe_driver_string[] =
48 "Intel(R) 10 Gigabit PCI Express Network Driver";
49
50 #define DRV_VERSION "1.3.30-k2"
51 const char ixgbe_driver_version[] = DRV_VERSION;
52 static char ixgbe_copyright[] = "Copyright (c) 1999-2007 Intel Corporation.";
53
54 static const struct ixgbe_info *ixgbe_info_tbl[] = {
55 [board_82598] = &ixgbe_82598_info,
56 };
57
58 /* ixgbe_pci_tbl - PCI Device ID Table
59 *
60 * Wildcard entries (PCI_ANY_ID) should come last
61 * Last entry must be all 0s
62 *
63 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
64 * Class, Class Mask, private data (not used) }
65 */
66 static struct pci_device_id ixgbe_pci_tbl[] = {
67 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
68 board_82598 },
69 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
70 board_82598 },
71 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
72 board_82598 },
73 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
74 board_82598 },
75 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
76 board_82598 },
77
78 /* required last entry */
79 {0, }
80 };
81 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
82
83 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
84 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
85 void *p);
86 static struct notifier_block dca_notifier = {
87 .notifier_call = ixgbe_notify_dca,
88 .next = NULL,
89 .priority = 0
90 };
91 #endif
92
93 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
94 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
95 MODULE_LICENSE("GPL");
96 MODULE_VERSION(DRV_VERSION);
97
98 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
99
100 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
101 {
102 u32 ctrl_ext;
103
104 /* Let firmware take over control of h/w */
105 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
106 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
107 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
108 }
109
110 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
111 {
112 u32 ctrl_ext;
113
114 /* Let firmware know the driver has taken over */
115 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
116 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
117 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
118 }
119
120 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, u16 int_alloc_entry,
121 u8 msix_vector)
122 {
123 u32 ivar, index;
124
125 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
126 index = (int_alloc_entry >> 2) & 0x1F;
127 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR(index));
128 ivar &= ~(0xFF << (8 * (int_alloc_entry & 0x3)));
129 ivar |= (msix_vector << (8 * (int_alloc_entry & 0x3)));
130 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR(index), ivar);
131 }
132
133 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
134 struct ixgbe_tx_buffer
135 *tx_buffer_info)
136 {
137 if (tx_buffer_info->dma) {
138 pci_unmap_page(adapter->pdev, tx_buffer_info->dma,
139 tx_buffer_info->length, PCI_DMA_TODEVICE);
140 tx_buffer_info->dma = 0;
141 }
142 if (tx_buffer_info->skb) {
143 dev_kfree_skb_any(tx_buffer_info->skb);
144 tx_buffer_info->skb = NULL;
145 }
146 /* tx_buffer_info must be completely set up in the transmit path */
147 }
148
149 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
150 struct ixgbe_ring *tx_ring,
151 unsigned int eop)
152 {
153 struct ixgbe_hw *hw = &adapter->hw;
154 u32 head, tail;
155
156 /* Detect a transmit hang in hardware, this serializes the
157 * check with the clearing of time_stamp and movement of eop */
158 head = IXGBE_READ_REG(hw, tx_ring->head);
159 tail = IXGBE_READ_REG(hw, tx_ring->tail);
160 adapter->detect_tx_hung = false;
161 if ((head != tail) &&
162 tx_ring->tx_buffer_info[eop].time_stamp &&
163 time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
164 !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
165 /* detected Tx unit hang */
166 union ixgbe_adv_tx_desc *tx_desc;
167 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
168 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
169 " Tx Queue <%d>\n"
170 " TDH, TDT <%x>, <%x>\n"
171 " next_to_use <%x>\n"
172 " next_to_clean <%x>\n"
173 "tx_buffer_info[next_to_clean]\n"
174 " time_stamp <%lx>\n"
175 " jiffies <%lx>\n",
176 tx_ring->queue_index,
177 head, tail,
178 tx_ring->next_to_use, eop,
179 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
180 return true;
181 }
182
183 return false;
184 }
185
186 #define IXGBE_MAX_TXD_PWR 14
187 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
188
189 /* Tx Descriptors needed, worst case */
190 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
191 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
192 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
193 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
194
195 #define GET_TX_HEAD_FROM_RING(ring) (\
196 *(volatile u32 *) \
197 ((union ixgbe_adv_tx_desc *)(ring)->desc + (ring)->count))
198 static void ixgbe_tx_timeout(struct net_device *netdev);
199
200 /**
201 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
202 * @adapter: board private structure
203 * @tx_ring: tx ring to clean
204 **/
205 static bool ixgbe_clean_tx_irq(struct ixgbe_adapter *adapter,
206 struct ixgbe_ring *tx_ring)
207 {
208 union ixgbe_adv_tx_desc *tx_desc;
209 struct ixgbe_tx_buffer *tx_buffer_info;
210 struct net_device *netdev = adapter->netdev;
211 struct sk_buff *skb;
212 unsigned int i;
213 u32 head, oldhead;
214 unsigned int count = 0;
215 unsigned int total_bytes = 0, total_packets = 0;
216
217 rmb();
218 head = GET_TX_HEAD_FROM_RING(tx_ring);
219 head = le32_to_cpu(head);
220 i = tx_ring->next_to_clean;
221 while (1) {
222 while (i != head) {
223 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
224 tx_buffer_info = &tx_ring->tx_buffer_info[i];
225 skb = tx_buffer_info->skb;
226
227 if (skb) {
228 unsigned int segs, bytecount;
229
230 /* gso_segs is currently only valid for tcp */
231 segs = skb_shinfo(skb)->gso_segs ?: 1;
232 /* multiply data chunks by size of headers */
233 bytecount = ((segs - 1) * skb_headlen(skb)) +
234 skb->len;
235 total_packets += segs;
236 total_bytes += bytecount;
237 }
238
239 ixgbe_unmap_and_free_tx_resource(adapter,
240 tx_buffer_info);
241
242 i++;
243 if (i == tx_ring->count)
244 i = 0;
245
246 count++;
247 if (count == tx_ring->count)
248 goto done_cleaning;
249 }
250 oldhead = head;
251 rmb();
252 head = GET_TX_HEAD_FROM_RING(tx_ring);
253 head = le32_to_cpu(head);
254 if (head == oldhead)
255 goto done_cleaning;
256 } /* while (1) */
257
258 done_cleaning:
259 tx_ring->next_to_clean = i;
260
261 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
262 if (unlikely(count && netif_carrier_ok(netdev) &&
263 (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
264 /* Make sure that anybody stopping the queue after this
265 * sees the new next_to_clean.
266 */
267 smp_mb();
268 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
269 !test_bit(__IXGBE_DOWN, &adapter->state)) {
270 netif_wake_subqueue(netdev, tx_ring->queue_index);
271 ++adapter->restart_queue;
272 }
273 }
274
275 if (adapter->detect_tx_hung) {
276 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
277 /* schedule immediate reset if we believe we hung */
278 DPRINTK(PROBE, INFO,
279 "tx hang %d detected, resetting adapter\n",
280 adapter->tx_timeout_count + 1);
281 ixgbe_tx_timeout(adapter->netdev);
282 }
283 }
284
285 /* re-arm the interrupt */
286 if ((total_packets >= tx_ring->work_limit) ||
287 (count == tx_ring->count))
288 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, tx_ring->v_idx);
289
290 tx_ring->total_bytes += total_bytes;
291 tx_ring->total_packets += total_packets;
292 tx_ring->stats.bytes += total_bytes;
293 tx_ring->stats.packets += total_packets;
294 adapter->net_stats.tx_bytes += total_bytes;
295 adapter->net_stats.tx_packets += total_packets;
296 return (total_packets ? true : false);
297 }
298
299 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
300 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
301 struct ixgbe_ring *rx_ring)
302 {
303 u32 rxctrl;
304 int cpu = get_cpu();
305 int q = rx_ring - adapter->rx_ring;
306
307 if (rx_ring->cpu != cpu) {
308 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
309 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
310 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
311 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
312 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
313 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
314 rx_ring->cpu = cpu;
315 }
316 put_cpu();
317 }
318
319 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
320 struct ixgbe_ring *tx_ring)
321 {
322 u32 txctrl;
323 int cpu = get_cpu();
324 int q = tx_ring - adapter->tx_ring;
325
326 if (tx_ring->cpu != cpu) {
327 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
328 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
329 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
330 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
332 tx_ring->cpu = cpu;
333 }
334 put_cpu();
335 }
336
337 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
338 {
339 int i;
340
341 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
342 return;
343
344 for (i = 0; i < adapter->num_tx_queues; i++) {
345 adapter->tx_ring[i].cpu = -1;
346 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
347 }
348 for (i = 0; i < adapter->num_rx_queues; i++) {
349 adapter->rx_ring[i].cpu = -1;
350 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
351 }
352 }
353
354 static int __ixgbe_notify_dca(struct device *dev, void *data)
355 {
356 struct net_device *netdev = dev_get_drvdata(dev);
357 struct ixgbe_adapter *adapter = netdev_priv(netdev);
358 unsigned long event = *(unsigned long *)data;
359
360 switch (event) {
361 case DCA_PROVIDER_ADD:
362 /* if we're already enabled, don't do it again */
363 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
364 break;
365 /* Always use CB2 mode, difference is masked
366 * in the CB driver. */
367 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
368 if (dca_add_requester(dev) == 0) {
369 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
370 ixgbe_setup_dca(adapter);
371 break;
372 }
373 /* Fall Through since DCA is disabled. */
374 case DCA_PROVIDER_REMOVE:
375 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
376 dca_remove_requester(dev);
377 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
378 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
379 }
380 break;
381 }
382
383 return 0;
384 }
385
386 #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
387 /**
388 * ixgbe_receive_skb - Send a completed packet up the stack
389 * @adapter: board private structure
390 * @skb: packet to send up
391 * @status: hardware indication of status of receive
392 * @rx_ring: rx descriptor ring (for a specific queue) to setup
393 * @rx_desc: rx descriptor
394 **/
395 static void ixgbe_receive_skb(struct ixgbe_adapter *adapter,
396 struct sk_buff *skb, u8 status,
397 struct ixgbe_ring *ring,
398 union ixgbe_adv_rx_desc *rx_desc)
399 {
400 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
401 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
402
403 if (adapter->netdev->features & NETIF_F_LRO &&
404 skb->ip_summed == CHECKSUM_UNNECESSARY) {
405 if (adapter->vlgrp && is_vlan)
406 lro_vlan_hwaccel_receive_skb(&ring->lro_mgr, skb,
407 adapter->vlgrp, tag,
408 rx_desc);
409 else
410 lro_receive_skb(&ring->lro_mgr, skb, rx_desc);
411 ring->lro_used = true;
412 } else {
413 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
414 if (adapter->vlgrp && is_vlan)
415 vlan_hwaccel_receive_skb(skb, adapter->vlgrp, tag);
416 else
417 netif_receive_skb(skb);
418 } else {
419 if (adapter->vlgrp && is_vlan)
420 vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
421 else
422 netif_rx(skb);
423 }
424 }
425 }
426
427 /**
428 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
429 * @adapter: address of board private structure
430 * @status_err: hardware indication of status of receive
431 * @skb: skb currently being received and modified
432 **/
433 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
434 u32 status_err, struct sk_buff *skb)
435 {
436 skb->ip_summed = CHECKSUM_NONE;
437
438 /* Rx csum disabled */
439 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
440 return;
441
442 /* if IP and error */
443 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
444 (status_err & IXGBE_RXDADV_ERR_IPE)) {
445 adapter->hw_csum_rx_error++;
446 return;
447 }
448
449 if (!(status_err & IXGBE_RXD_STAT_L4CS))
450 return;
451
452 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
453 adapter->hw_csum_rx_error++;
454 return;
455 }
456
457 /* It must be a TCP or UDP packet with a valid checksum */
458 skb->ip_summed = CHECKSUM_UNNECESSARY;
459 adapter->hw_csum_rx_good++;
460 }
461
462 /**
463 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
464 * @adapter: address of board private structure
465 **/
466 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
467 struct ixgbe_ring *rx_ring,
468 int cleaned_count)
469 {
470 struct pci_dev *pdev = adapter->pdev;
471 union ixgbe_adv_rx_desc *rx_desc;
472 struct ixgbe_rx_buffer *bi;
473 unsigned int i;
474 unsigned int bufsz = rx_ring->rx_buf_len + NET_IP_ALIGN;
475
476 i = rx_ring->next_to_use;
477 bi = &rx_ring->rx_buffer_info[i];
478
479 while (cleaned_count--) {
480 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
481
482 if (!bi->page_dma &&
483 (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)) {
484 if (!bi->page) {
485 bi->page = alloc_page(GFP_ATOMIC);
486 if (!bi->page) {
487 adapter->alloc_rx_page_failed++;
488 goto no_buffers;
489 }
490 bi->page_offset = 0;
491 } else {
492 /* use a half page if we're re-using */
493 bi->page_offset ^= (PAGE_SIZE / 2);
494 }
495
496 bi->page_dma = pci_map_page(pdev, bi->page,
497 bi->page_offset,
498 (PAGE_SIZE / 2),
499 PCI_DMA_FROMDEVICE);
500 }
501
502 if (!bi->skb) {
503 struct sk_buff *skb = netdev_alloc_skb(adapter->netdev,
504 bufsz);
505
506 if (!skb) {
507 adapter->alloc_rx_buff_failed++;
508 goto no_buffers;
509 }
510
511 /*
512 * Make buffer alignment 2 beyond a 16 byte boundary
513 * this will result in a 16 byte aligned IP header after
514 * the 14 byte MAC header is removed
515 */
516 skb_reserve(skb, NET_IP_ALIGN);
517
518 bi->skb = skb;
519 bi->dma = pci_map_single(pdev, skb->data, bufsz,
520 PCI_DMA_FROMDEVICE);
521 }
522 /* Refresh the desc even if buffer_addrs didn't change because
523 * each write-back erases this info. */
524 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
525 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
526 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
527 } else {
528 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
529 }
530
531 i++;
532 if (i == rx_ring->count)
533 i = 0;
534 bi = &rx_ring->rx_buffer_info[i];
535 }
536
537 no_buffers:
538 if (rx_ring->next_to_use != i) {
539 rx_ring->next_to_use = i;
540 if (i-- == 0)
541 i = (rx_ring->count - 1);
542
543 /*
544 * Force memory writes to complete before letting h/w
545 * know there are new descriptors to fetch. (Only
546 * applicable for weak-ordered memory model archs,
547 * such as IA-64).
548 */
549 wmb();
550 writel(i, adapter->hw.hw_addr + rx_ring->tail);
551 }
552 }
553
554 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
555 {
556 return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
557 }
558
559 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
560 {
561 return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
562 }
563
564 static bool ixgbe_clean_rx_irq(struct ixgbe_adapter *adapter,
565 struct ixgbe_ring *rx_ring,
566 int *work_done, int work_to_do)
567 {
568 struct pci_dev *pdev = adapter->pdev;
569 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
570 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
571 struct sk_buff *skb;
572 unsigned int i;
573 u32 len, staterr;
574 u16 hdr_info;
575 bool cleaned = false;
576 int cleaned_count = 0;
577 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
578
579 i = rx_ring->next_to_clean;
580 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
581 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
582 rx_buffer_info = &rx_ring->rx_buffer_info[i];
583
584 while (staterr & IXGBE_RXD_STAT_DD) {
585 u32 upper_len = 0;
586 if (*work_done >= work_to_do)
587 break;
588 (*work_done)++;
589
590 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
591 hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
592 len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
593 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
594 if (hdr_info & IXGBE_RXDADV_SPH)
595 adapter->rx_hdr_split++;
596 if (len > IXGBE_RX_HDR_SIZE)
597 len = IXGBE_RX_HDR_SIZE;
598 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
599 } else {
600 len = le16_to_cpu(rx_desc->wb.upper.length);
601 }
602
603 cleaned = true;
604 skb = rx_buffer_info->skb;
605 prefetch(skb->data - NET_IP_ALIGN);
606 rx_buffer_info->skb = NULL;
607
608 if (len && !skb_shinfo(skb)->nr_frags) {
609 pci_unmap_single(pdev, rx_buffer_info->dma,
610 rx_ring->rx_buf_len + NET_IP_ALIGN,
611 PCI_DMA_FROMDEVICE);
612 skb_put(skb, len);
613 }
614
615 if (upper_len) {
616 pci_unmap_page(pdev, rx_buffer_info->page_dma,
617 PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
618 rx_buffer_info->page_dma = 0;
619 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
620 rx_buffer_info->page,
621 rx_buffer_info->page_offset,
622 upper_len);
623
624 if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
625 (page_count(rx_buffer_info->page) != 1))
626 rx_buffer_info->page = NULL;
627 else
628 get_page(rx_buffer_info->page);
629
630 skb->len += upper_len;
631 skb->data_len += upper_len;
632 skb->truesize += upper_len;
633 }
634
635 i++;
636 if (i == rx_ring->count)
637 i = 0;
638 next_buffer = &rx_ring->rx_buffer_info[i];
639
640 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
641 prefetch(next_rxd);
642
643 cleaned_count++;
644 if (staterr & IXGBE_RXD_STAT_EOP) {
645 rx_ring->stats.packets++;
646 rx_ring->stats.bytes += skb->len;
647 } else {
648 rx_buffer_info->skb = next_buffer->skb;
649 rx_buffer_info->dma = next_buffer->dma;
650 next_buffer->skb = skb;
651 next_buffer->dma = 0;
652 adapter->non_eop_descs++;
653 goto next_desc;
654 }
655
656 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
657 dev_kfree_skb_irq(skb);
658 goto next_desc;
659 }
660
661 ixgbe_rx_checksum(adapter, staterr, skb);
662
663 /* probably a little skewed due to removing CRC */
664 total_rx_bytes += skb->len;
665 total_rx_packets++;
666
667 skb->protocol = eth_type_trans(skb, adapter->netdev);
668 ixgbe_receive_skb(adapter, skb, staterr, rx_ring, rx_desc);
669 adapter->netdev->last_rx = jiffies;
670
671 next_desc:
672 rx_desc->wb.upper.status_error = 0;
673
674 /* return some buffers to hardware, one at a time is too slow */
675 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
676 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
677 cleaned_count = 0;
678 }
679
680 /* use prefetched values */
681 rx_desc = next_rxd;
682 rx_buffer_info = next_buffer;
683
684 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
685 }
686
687 if (rx_ring->lro_used) {
688 lro_flush_all(&rx_ring->lro_mgr);
689 rx_ring->lro_used = false;
690 }
691
692 rx_ring->next_to_clean = i;
693 cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
694
695 if (cleaned_count)
696 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
697
698 rx_ring->total_packets += total_rx_packets;
699 rx_ring->total_bytes += total_rx_bytes;
700 adapter->net_stats.rx_bytes += total_rx_bytes;
701 adapter->net_stats.rx_packets += total_rx_packets;
702
703 return cleaned;
704 }
705
706 static int ixgbe_clean_rxonly(struct napi_struct *, int);
707 /**
708 * ixgbe_configure_msix - Configure MSI-X hardware
709 * @adapter: board private structure
710 *
711 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
712 * interrupts.
713 **/
714 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
715 {
716 struct ixgbe_q_vector *q_vector;
717 int i, j, q_vectors, v_idx, r_idx;
718 u32 mask;
719
720 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
721
722 /* Populate the IVAR table and set the ITR values to the
723 * corresponding register.
724 */
725 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
726 q_vector = &adapter->q_vector[v_idx];
727 /* XXX for_each_bit(...) */
728 r_idx = find_first_bit(q_vector->rxr_idx,
729 adapter->num_rx_queues);
730
731 for (i = 0; i < q_vector->rxr_count; i++) {
732 j = adapter->rx_ring[r_idx].reg_idx;
733 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(j), v_idx);
734 r_idx = find_next_bit(q_vector->rxr_idx,
735 adapter->num_rx_queues,
736 r_idx + 1);
737 }
738 r_idx = find_first_bit(q_vector->txr_idx,
739 adapter->num_tx_queues);
740
741 for (i = 0; i < q_vector->txr_count; i++) {
742 j = adapter->tx_ring[r_idx].reg_idx;
743 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(j), v_idx);
744 r_idx = find_next_bit(q_vector->txr_idx,
745 adapter->num_tx_queues,
746 r_idx + 1);
747 }
748
749 /* if this is a tx only vector halve the interrupt rate */
750 if (q_vector->txr_count && !q_vector->rxr_count)
751 q_vector->eitr = (adapter->eitr_param >> 1);
752 else
753 /* rx only */
754 q_vector->eitr = adapter->eitr_param;
755
756 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx),
757 EITR_INTS_PER_SEC_TO_REG(q_vector->eitr));
758 }
759
760 ixgbe_set_ivar(adapter, IXGBE_IVAR_OTHER_CAUSES_INDEX, v_idx);
761 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
762
763 /* set up to autoclear timer, and the vectors */
764 mask = IXGBE_EIMS_ENABLE_MASK;
765 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
766 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
767 }
768
769 enum latency_range {
770 lowest_latency = 0,
771 low_latency = 1,
772 bulk_latency = 2,
773 latency_invalid = 255
774 };
775
776 /**
777 * ixgbe_update_itr - update the dynamic ITR value based on statistics
778 * @adapter: pointer to adapter
779 * @eitr: eitr setting (ints per sec) to give last timeslice
780 * @itr_setting: current throttle rate in ints/second
781 * @packets: the number of packets during this measurement interval
782 * @bytes: the number of bytes during this measurement interval
783 *
784 * Stores a new ITR value based on packets and byte
785 * counts during the last interrupt. The advantage of per interrupt
786 * computation is faster updates and more accurate ITR for the current
787 * traffic pattern. Constants in this function were computed
788 * based on theoretical maximum wire speed and thresholds were set based
789 * on testing data as well as attempting to minimize response time
790 * while increasing bulk throughput.
791 * this functionality is controlled by the InterruptThrottleRate module
792 * parameter (see ixgbe_param.c)
793 **/
794 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
795 u32 eitr, u8 itr_setting,
796 int packets, int bytes)
797 {
798 unsigned int retval = itr_setting;
799 u32 timepassed_us;
800 u64 bytes_perint;
801
802 if (packets == 0)
803 goto update_itr_done;
804
805
806 /* simple throttlerate management
807 * 0-20MB/s lowest (100000 ints/s)
808 * 20-100MB/s low (20000 ints/s)
809 * 100-1249MB/s bulk (8000 ints/s)
810 */
811 /* what was last interrupt timeslice? */
812 timepassed_us = 1000000/eitr;
813 bytes_perint = bytes / timepassed_us; /* bytes/usec */
814
815 switch (itr_setting) {
816 case lowest_latency:
817 if (bytes_perint > adapter->eitr_low)
818 retval = low_latency;
819 break;
820 case low_latency:
821 if (bytes_perint > adapter->eitr_high)
822 retval = bulk_latency;
823 else if (bytes_perint <= adapter->eitr_low)
824 retval = lowest_latency;
825 break;
826 case bulk_latency:
827 if (bytes_perint <= adapter->eitr_high)
828 retval = low_latency;
829 break;
830 }
831
832 update_itr_done:
833 return retval;
834 }
835
836 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
837 {
838 struct ixgbe_adapter *adapter = q_vector->adapter;
839 struct ixgbe_hw *hw = &adapter->hw;
840 u32 new_itr;
841 u8 current_itr, ret_itr;
842 int i, r_idx, v_idx = ((void *)q_vector - (void *)(adapter->q_vector)) /
843 sizeof(struct ixgbe_q_vector);
844 struct ixgbe_ring *rx_ring, *tx_ring;
845
846 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
847 for (i = 0; i < q_vector->txr_count; i++) {
848 tx_ring = &(adapter->tx_ring[r_idx]);
849 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
850 q_vector->tx_itr,
851 tx_ring->total_packets,
852 tx_ring->total_bytes);
853 /* if the result for this queue would decrease interrupt
854 * rate for this vector then use that result */
855 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
856 q_vector->tx_itr - 1 : ret_itr);
857 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
858 r_idx + 1);
859 }
860
861 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
862 for (i = 0; i < q_vector->rxr_count; i++) {
863 rx_ring = &(adapter->rx_ring[r_idx]);
864 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
865 q_vector->rx_itr,
866 rx_ring->total_packets,
867 rx_ring->total_bytes);
868 /* if the result for this queue would decrease interrupt
869 * rate for this vector then use that result */
870 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
871 q_vector->rx_itr - 1 : ret_itr);
872 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
873 r_idx + 1);
874 }
875
876 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
877
878 switch (current_itr) {
879 /* counts and packets in update_itr are dependent on these numbers */
880 case lowest_latency:
881 new_itr = 100000;
882 break;
883 case low_latency:
884 new_itr = 20000; /* aka hwitr = ~200 */
885 break;
886 case bulk_latency:
887 default:
888 new_itr = 8000;
889 break;
890 }
891
892 if (new_itr != q_vector->eitr) {
893 u32 itr_reg;
894 /* do an exponential smoothing */
895 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
896 q_vector->eitr = new_itr;
897 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
898 /* must write high and low 16 bits to reset counter */
899 DPRINTK(TX_ERR, DEBUG, "writing eitr(%d): %08X\n", v_idx,
900 itr_reg);
901 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg | (itr_reg)<<16);
902 }
903
904 return;
905 }
906
907
908 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
909 {
910 struct ixgbe_hw *hw = &adapter->hw;
911
912 adapter->lsc_int++;
913 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
914 adapter->link_check_timeout = jiffies;
915 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
916 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
917 schedule_work(&adapter->watchdog_task);
918 }
919 }
920
921 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
922 {
923 struct net_device *netdev = data;
924 struct ixgbe_adapter *adapter = netdev_priv(netdev);
925 struct ixgbe_hw *hw = &adapter->hw;
926 u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
927
928 if (eicr & IXGBE_EICR_LSC)
929 ixgbe_check_lsc(adapter);
930
931 if (!test_bit(__IXGBE_DOWN, &adapter->state))
932 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
933
934 return IRQ_HANDLED;
935 }
936
937 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
938 {
939 struct ixgbe_q_vector *q_vector = data;
940 struct ixgbe_adapter *adapter = q_vector->adapter;
941 struct ixgbe_ring *tx_ring;
942 int i, r_idx;
943
944 if (!q_vector->txr_count)
945 return IRQ_HANDLED;
946
947 r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
948 for (i = 0; i < q_vector->txr_count; i++) {
949 tx_ring = &(adapter->tx_ring[r_idx]);
950 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
951 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
952 ixgbe_update_tx_dca(adapter, tx_ring);
953 #endif
954 tx_ring->total_bytes = 0;
955 tx_ring->total_packets = 0;
956 ixgbe_clean_tx_irq(adapter, tx_ring);
957 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
958 r_idx + 1);
959 }
960
961 return IRQ_HANDLED;
962 }
963
964 /**
965 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
966 * @irq: unused
967 * @data: pointer to our q_vector struct for this interrupt vector
968 **/
969 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
970 {
971 struct ixgbe_q_vector *q_vector = data;
972 struct ixgbe_adapter *adapter = q_vector->adapter;
973 struct ixgbe_ring *rx_ring;
974 int r_idx;
975 int i;
976
977 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
978 for (i = 0; i < q_vector->rxr_count; i++) {
979 rx_ring = &(adapter->rx_ring[r_idx]);
980 rx_ring->total_bytes = 0;
981 rx_ring->total_packets = 0;
982 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
983 r_idx + 1);
984 }
985
986 if (!q_vector->rxr_count)
987 return IRQ_HANDLED;
988
989 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
990 rx_ring = &(adapter->rx_ring[r_idx]);
991 /* disable interrupts on this vector only */
992 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, rx_ring->v_idx);
993 netif_rx_schedule(adapter->netdev, &q_vector->napi);
994
995 return IRQ_HANDLED;
996 }
997
998 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
999 {
1000 ixgbe_msix_clean_rx(irq, data);
1001 ixgbe_msix_clean_tx(irq, data);
1002
1003 return IRQ_HANDLED;
1004 }
1005
1006 /**
1007 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1008 * @napi: napi struct with our devices info in it
1009 * @budget: amount of work driver is allowed to do this pass, in packets
1010 *
1011 * This function is optimized for cleaning one queue only on a single
1012 * q_vector!!!
1013 **/
1014 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1015 {
1016 struct ixgbe_q_vector *q_vector =
1017 container_of(napi, struct ixgbe_q_vector, napi);
1018 struct ixgbe_adapter *adapter = q_vector->adapter;
1019 struct ixgbe_ring *rx_ring = NULL;
1020 int work_done = 0;
1021 long r_idx;
1022
1023 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1024 rx_ring = &(adapter->rx_ring[r_idx]);
1025 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1026 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1027 ixgbe_update_rx_dca(adapter, rx_ring);
1028 #endif
1029
1030 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1031
1032 /* If all Rx work done, exit the polling mode */
1033 if (work_done < budget) {
1034 netif_rx_complete(adapter->netdev, napi);
1035 if (adapter->itr_setting & 3)
1036 ixgbe_set_itr_msix(q_vector);
1037 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1038 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, rx_ring->v_idx);
1039 }
1040
1041 return work_done;
1042 }
1043
1044 /**
1045 * ixgbe_clean_rxonly_many - msix (aka one shot) rx clean routine
1046 * @napi: napi struct with our devices info in it
1047 * @budget: amount of work driver is allowed to do this pass, in packets
1048 *
1049 * This function will clean more than one rx queue associated with a
1050 * q_vector.
1051 **/
1052 static int ixgbe_clean_rxonly_many(struct napi_struct *napi, int budget)
1053 {
1054 struct ixgbe_q_vector *q_vector =
1055 container_of(napi, struct ixgbe_q_vector, napi);
1056 struct ixgbe_adapter *adapter = q_vector->adapter;
1057 struct ixgbe_ring *rx_ring = NULL;
1058 int work_done = 0, i;
1059 long r_idx;
1060 u16 enable_mask = 0;
1061
1062 /* attempt to distribute budget to each queue fairly, but don't allow
1063 * the budget to go below 1 because we'll exit polling */
1064 budget /= (q_vector->rxr_count ?: 1);
1065 budget = max(budget, 1);
1066 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1067 for (i = 0; i < q_vector->rxr_count; i++) {
1068 rx_ring = &(adapter->rx_ring[r_idx]);
1069 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
1070 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1071 ixgbe_update_rx_dca(adapter, rx_ring);
1072 #endif
1073 ixgbe_clean_rx_irq(adapter, rx_ring, &work_done, budget);
1074 enable_mask |= rx_ring->v_idx;
1075 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1076 r_idx + 1);
1077 }
1078
1079 r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1080 rx_ring = &(adapter->rx_ring[r_idx]);
1081 /* If all Rx work done, exit the polling mode */
1082 if (work_done < budget) {
1083 netif_rx_complete(adapter->netdev, napi);
1084 if (adapter->itr_setting & 3)
1085 ixgbe_set_itr_msix(q_vector);
1086 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1087 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, enable_mask);
1088 return 0;
1089 }
1090
1091 return work_done;
1092 }
1093 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1094 int r_idx)
1095 {
1096 a->q_vector[v_idx].adapter = a;
1097 set_bit(r_idx, a->q_vector[v_idx].rxr_idx);
1098 a->q_vector[v_idx].rxr_count++;
1099 a->rx_ring[r_idx].v_idx = 1 << v_idx;
1100 }
1101
1102 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1103 int r_idx)
1104 {
1105 a->q_vector[v_idx].adapter = a;
1106 set_bit(r_idx, a->q_vector[v_idx].txr_idx);
1107 a->q_vector[v_idx].txr_count++;
1108 a->tx_ring[r_idx].v_idx = 1 << v_idx;
1109 }
1110
1111 /**
1112 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1113 * @adapter: board private structure to initialize
1114 * @vectors: allotted vector count for descriptor rings
1115 *
1116 * This function maps descriptor rings to the queue-specific vectors
1117 * we were allotted through the MSI-X enabling code. Ideally, we'd have
1118 * one vector per ring/queue, but on a constrained vector budget, we
1119 * group the rings as "efficiently" as possible. You would add new
1120 * mapping configurations in here.
1121 **/
1122 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1123 int vectors)
1124 {
1125 int v_start = 0;
1126 int rxr_idx = 0, txr_idx = 0;
1127 int rxr_remaining = adapter->num_rx_queues;
1128 int txr_remaining = adapter->num_tx_queues;
1129 int i, j;
1130 int rqpv, tqpv;
1131 int err = 0;
1132
1133 /* No mapping required if MSI-X is disabled. */
1134 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1135 goto out;
1136
1137 /*
1138 * The ideal configuration...
1139 * We have enough vectors to map one per queue.
1140 */
1141 if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1142 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1143 map_vector_to_rxq(adapter, v_start, rxr_idx);
1144
1145 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1146 map_vector_to_txq(adapter, v_start, txr_idx);
1147
1148 goto out;
1149 }
1150
1151 /*
1152 * If we don't have enough vectors for a 1-to-1
1153 * mapping, we'll have to group them so there are
1154 * multiple queues per vector.
1155 */
1156 /* Re-adjusting *qpv takes care of the remainder. */
1157 for (i = v_start; i < vectors; i++) {
1158 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1159 for (j = 0; j < rqpv; j++) {
1160 map_vector_to_rxq(adapter, i, rxr_idx);
1161 rxr_idx++;
1162 rxr_remaining--;
1163 }
1164 }
1165 for (i = v_start; i < vectors; i++) {
1166 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1167 for (j = 0; j < tqpv; j++) {
1168 map_vector_to_txq(adapter, i, txr_idx);
1169 txr_idx++;
1170 txr_remaining--;
1171 }
1172 }
1173
1174 out:
1175 return err;
1176 }
1177
1178 /**
1179 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1180 * @adapter: board private structure
1181 *
1182 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1183 * interrupts from the kernel.
1184 **/
1185 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1186 {
1187 struct net_device *netdev = adapter->netdev;
1188 irqreturn_t (*handler)(int, void *);
1189 int i, vector, q_vectors, err;
1190
1191 /* Decrement for Other and TCP Timer vectors */
1192 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1193
1194 /* Map the Tx/Rx rings to the vectors we were allotted. */
1195 err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1196 if (err)
1197 goto out;
1198
1199 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1200 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1201 &ixgbe_msix_clean_many)
1202 for (vector = 0; vector < q_vectors; vector++) {
1203 handler = SET_HANDLER(&adapter->q_vector[vector]);
1204 sprintf(adapter->name[vector], "%s:v%d-%s",
1205 netdev->name, vector,
1206 (handler == &ixgbe_msix_clean_rx) ? "Rx" :
1207 ((handler == &ixgbe_msix_clean_tx) ? "Tx" : "TxRx"));
1208 err = request_irq(adapter->msix_entries[vector].vector,
1209 handler, 0, adapter->name[vector],
1210 &(adapter->q_vector[vector]));
1211 if (err) {
1212 DPRINTK(PROBE, ERR,
1213 "request_irq failed for MSIX interrupt "
1214 "Error: %d\n", err);
1215 goto free_queue_irqs;
1216 }
1217 }
1218
1219 sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1220 err = request_irq(adapter->msix_entries[vector].vector,
1221 &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1222 if (err) {
1223 DPRINTK(PROBE, ERR,
1224 "request_irq for msix_lsc failed: %d\n", err);
1225 goto free_queue_irqs;
1226 }
1227
1228 return 0;
1229
1230 free_queue_irqs:
1231 for (i = vector - 1; i >= 0; i--)
1232 free_irq(adapter->msix_entries[--vector].vector,
1233 &(adapter->q_vector[i]));
1234 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1235 pci_disable_msix(adapter->pdev);
1236 kfree(adapter->msix_entries);
1237 adapter->msix_entries = NULL;
1238 out:
1239 return err;
1240 }
1241
1242 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1243 {
1244 struct ixgbe_hw *hw = &adapter->hw;
1245 struct ixgbe_q_vector *q_vector = adapter->q_vector;
1246 u8 current_itr;
1247 u32 new_itr = q_vector->eitr;
1248 struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1249 struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1250
1251 q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1252 q_vector->tx_itr,
1253 tx_ring->total_packets,
1254 tx_ring->total_bytes);
1255 q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1256 q_vector->rx_itr,
1257 rx_ring->total_packets,
1258 rx_ring->total_bytes);
1259
1260 current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1261
1262 switch (current_itr) {
1263 /* counts and packets in update_itr are dependent on these numbers */
1264 case lowest_latency:
1265 new_itr = 100000;
1266 break;
1267 case low_latency:
1268 new_itr = 20000; /* aka hwitr = ~200 */
1269 break;
1270 case bulk_latency:
1271 new_itr = 8000;
1272 break;
1273 default:
1274 break;
1275 }
1276
1277 if (new_itr != q_vector->eitr) {
1278 u32 itr_reg;
1279 /* do an exponential smoothing */
1280 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1281 q_vector->eitr = new_itr;
1282 itr_reg = EITR_INTS_PER_SEC_TO_REG(new_itr);
1283 /* must write high and low 16 bits to reset counter */
1284 IXGBE_WRITE_REG(hw, IXGBE_EITR(0), itr_reg | (itr_reg)<<16);
1285 }
1286
1287 return;
1288 }
1289
1290 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter);
1291
1292 /**
1293 * ixgbe_intr - legacy mode Interrupt Handler
1294 * @irq: interrupt number
1295 * @data: pointer to a network interface device structure
1296 * @pt_regs: CPU registers structure
1297 **/
1298 static irqreturn_t ixgbe_intr(int irq, void *data)
1299 {
1300 struct net_device *netdev = data;
1301 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1302 struct ixgbe_hw *hw = &adapter->hw;
1303 u32 eicr;
1304
1305 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1306 * therefore no explict interrupt disable is necessary */
1307 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1308 if (!eicr) {
1309 /* shared interrupt alert!
1310 * make sure interrupts are enabled because the read will
1311 * have disabled interrupts due to EIAM */
1312 ixgbe_irq_enable(adapter);
1313 return IRQ_NONE; /* Not our interrupt */
1314 }
1315
1316 if (eicr & IXGBE_EICR_LSC)
1317 ixgbe_check_lsc(adapter);
1318
1319 if (netif_rx_schedule_prep(netdev, &adapter->q_vector[0].napi)) {
1320 adapter->tx_ring[0].total_packets = 0;
1321 adapter->tx_ring[0].total_bytes = 0;
1322 adapter->rx_ring[0].total_packets = 0;
1323 adapter->rx_ring[0].total_bytes = 0;
1324 /* would disable interrupts here but EIAM disabled it */
1325 __netif_rx_schedule(netdev, &adapter->q_vector[0].napi);
1326 }
1327
1328 return IRQ_HANDLED;
1329 }
1330
1331 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1332 {
1333 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1334
1335 for (i = 0; i < q_vectors; i++) {
1336 struct ixgbe_q_vector *q_vector = &adapter->q_vector[i];
1337 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1338 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1339 q_vector->rxr_count = 0;
1340 q_vector->txr_count = 0;
1341 }
1342 }
1343
1344 /**
1345 * ixgbe_request_irq - initialize interrupts
1346 * @adapter: board private structure
1347 *
1348 * Attempts to configure interrupts using the best available
1349 * capabilities of the hardware and kernel.
1350 **/
1351 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1352 {
1353 struct net_device *netdev = adapter->netdev;
1354 int err;
1355
1356 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1357 err = ixgbe_request_msix_irqs(adapter);
1358 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1359 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1360 netdev->name, netdev);
1361 } else {
1362 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1363 netdev->name, netdev);
1364 }
1365
1366 if (err)
1367 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1368
1369 return err;
1370 }
1371
1372 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1373 {
1374 struct net_device *netdev = adapter->netdev;
1375
1376 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1377 int i, q_vectors;
1378
1379 q_vectors = adapter->num_msix_vectors;
1380
1381 i = q_vectors - 1;
1382 free_irq(adapter->msix_entries[i].vector, netdev);
1383
1384 i--;
1385 for (; i >= 0; i--) {
1386 free_irq(adapter->msix_entries[i].vector,
1387 &(adapter->q_vector[i]));
1388 }
1389
1390 ixgbe_reset_q_vectors(adapter);
1391 } else {
1392 free_irq(adapter->pdev->irq, netdev);
1393 }
1394 }
1395
1396 /**
1397 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1398 * @adapter: board private structure
1399 **/
1400 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1401 {
1402 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1403 IXGBE_WRITE_FLUSH(&adapter->hw);
1404 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1405 int i;
1406 for (i = 0; i < adapter->num_msix_vectors; i++)
1407 synchronize_irq(adapter->msix_entries[i].vector);
1408 } else {
1409 synchronize_irq(adapter->pdev->irq);
1410 }
1411 }
1412
1413 /**
1414 * ixgbe_irq_enable - Enable default interrupt generation settings
1415 * @adapter: board private structure
1416 **/
1417 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1418 {
1419 u32 mask;
1420 mask = IXGBE_EIMS_ENABLE_MASK;
1421 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1422 IXGBE_WRITE_FLUSH(&adapter->hw);
1423 }
1424
1425 /**
1426 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1427 *
1428 **/
1429 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1430 {
1431 struct ixgbe_hw *hw = &adapter->hw;
1432
1433 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1434 EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1435
1436 ixgbe_set_ivar(adapter, IXGBE_IVAR_RX_QUEUE(0), 0);
1437 ixgbe_set_ivar(adapter, IXGBE_IVAR_TX_QUEUE(0), 0);
1438
1439 map_vector_to_rxq(adapter, 0, 0);
1440 map_vector_to_txq(adapter, 0, 0);
1441
1442 DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1443 }
1444
1445 /**
1446 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1447 * @adapter: board private structure
1448 *
1449 * Configure the Tx unit of the MAC after a reset.
1450 **/
1451 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1452 {
1453 u64 tdba, tdwba;
1454 struct ixgbe_hw *hw = &adapter->hw;
1455 u32 i, j, tdlen, txctrl;
1456
1457 /* Setup the HW Tx Head and Tail descriptor pointers */
1458 for (i = 0; i < adapter->num_tx_queues; i++) {
1459 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1460 j = ring->reg_idx;
1461 tdba = ring->dma;
1462 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1463 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1464 (tdba & DMA_32BIT_MASK));
1465 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1466 tdwba = ring->dma +
1467 (ring->count * sizeof(union ixgbe_adv_tx_desc));
1468 tdwba |= IXGBE_TDWBAL_HEAD_WB_ENABLE;
1469 IXGBE_WRITE_REG(hw, IXGBE_TDWBAL(j), tdwba & DMA_32BIT_MASK);
1470 IXGBE_WRITE_REG(hw, IXGBE_TDWBAH(j), (tdwba >> 32));
1471 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1472 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1473 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1474 adapter->tx_ring[i].head = IXGBE_TDH(j);
1475 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1476 /* Disable Tx Head Writeback RO bit, since this hoses
1477 * bookkeeping if things aren't delivered in order.
1478 */
1479 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1480 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1481 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1482 }
1483 }
1484
1485 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1486
1487 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter, int index)
1488 {
1489 struct ixgbe_ring *rx_ring;
1490 u32 srrctl;
1491 int queue0;
1492 unsigned long mask;
1493
1494 /* program one srrctl register per VMDq index */
1495 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
1496 long shift, len;
1497 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1498 len = sizeof(adapter->ring_feature[RING_F_VMDQ].mask) * 8;
1499 shift = find_first_bit(&mask, len);
1500 queue0 = index & mask;
1501 index = (index & mask) >> shift;
1502 /* program one srrctl per RSS queue since RDRXCTL.MVMEN is enabled */
1503 } else {
1504 mask = (unsigned long) adapter->ring_feature[RING_F_RSS].mask;
1505 queue0 = index & mask;
1506 index = index & mask;
1507 }
1508
1509 rx_ring = &adapter->rx_ring[queue0];
1510
1511 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1512
1513 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1514 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1515
1516 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1517 srrctl |= IXGBE_RXBUFFER_2048 >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1518 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1519 srrctl |= ((IXGBE_RX_HDR_SIZE <<
1520 IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1521 IXGBE_SRRCTL_BSIZEHDR_MASK);
1522 } else {
1523 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1524
1525 if (rx_ring->rx_buf_len == MAXIMUM_ETHERNET_VLAN_SIZE)
1526 srrctl |= IXGBE_RXBUFFER_2048 >>
1527 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1528 else
1529 srrctl |= rx_ring->rx_buf_len >>
1530 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1531 }
1532 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1533 }
1534
1535 /**
1536 * ixgbe_get_skb_hdr - helper function for LRO header processing
1537 * @skb: pointer to sk_buff to be added to LRO packet
1538 * @iphdr: pointer to ip header structure
1539 * @tcph: pointer to tcp header structure
1540 * @hdr_flags: pointer to header flags
1541 * @priv: private data
1542 **/
1543 static int ixgbe_get_skb_hdr(struct sk_buff *skb, void **iphdr, void **tcph,
1544 u64 *hdr_flags, void *priv)
1545 {
1546 union ixgbe_adv_rx_desc *rx_desc = priv;
1547
1548 /* Verify that this is a valid IPv4 TCP packet */
1549 if (!((ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_IPV4) &&
1550 (ixgbe_get_pkt_info(rx_desc) & IXGBE_RXDADV_PKTTYPE_TCP)))
1551 return -1;
1552
1553 /* Set network headers */
1554 skb_reset_network_header(skb);
1555 skb_set_transport_header(skb, ip_hdrlen(skb));
1556 *iphdr = ip_hdr(skb);
1557 *tcph = tcp_hdr(skb);
1558 *hdr_flags = LRO_IPV4 | LRO_TCP;
1559 return 0;
1560 }
1561
1562 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
1563 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
1564
1565 /**
1566 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1567 * @adapter: board private structure
1568 *
1569 * Configure the Rx unit of the MAC after a reset.
1570 **/
1571 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1572 {
1573 u64 rdba;
1574 struct ixgbe_hw *hw = &adapter->hw;
1575 struct net_device *netdev = adapter->netdev;
1576 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1577 int i, j;
1578 u32 rdlen, rxctrl, rxcsum;
1579 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1580 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1581 0x6A3E67EA, 0x14364D17, 0x3BED200D};
1582 u32 fctrl, hlreg0;
1583 u32 pages;
1584 u32 reta = 0, mrqc;
1585 u32 rdrxctl;
1586 int rx_buf_len;
1587
1588 /* Decide whether to use packet split mode or not */
1589 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1590
1591 /* Set the RX buffer length according to the mode */
1592 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
1593 rx_buf_len = IXGBE_RX_HDR_SIZE;
1594 } else {
1595 if (netdev->mtu <= ETH_DATA_LEN)
1596 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
1597 else
1598 rx_buf_len = ALIGN(max_frame, 1024);
1599 }
1600
1601 fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
1602 fctrl |= IXGBE_FCTRL_BAM;
1603 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
1604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
1605
1606 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
1607 if (adapter->netdev->mtu <= ETH_DATA_LEN)
1608 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
1609 else
1610 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
1611 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
1612
1613 pages = PAGE_USE_COUNT(adapter->netdev->mtu);
1614
1615 rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
1616 /* disable receives while setting up the descriptors */
1617 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1618 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
1619
1620 /* Setup the HW Rx Head and Tail Descriptor Pointers and
1621 * the Base and Length of the Rx Descriptor Ring */
1622 for (i = 0; i < adapter->num_rx_queues; i++) {
1623 rdba = adapter->rx_ring[i].dma;
1624 j = adapter->rx_ring[i].reg_idx;
1625 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_32BIT_MASK));
1626 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
1627 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
1628 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
1629 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
1630 adapter->rx_ring[i].head = IXGBE_RDH(j);
1631 adapter->rx_ring[i].tail = IXGBE_RDT(j);
1632 adapter->rx_ring[i].rx_buf_len = rx_buf_len;
1633 /* Intitial LRO Settings */
1634 adapter->rx_ring[i].lro_mgr.max_aggr = IXGBE_MAX_LRO_AGGREGATE;
1635 adapter->rx_ring[i].lro_mgr.max_desc = IXGBE_MAX_LRO_DESCRIPTORS;
1636 adapter->rx_ring[i].lro_mgr.get_skb_header = ixgbe_get_skb_hdr;
1637 adapter->rx_ring[i].lro_mgr.features = LRO_F_EXTRACT_VLAN_ID;
1638 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1639 adapter->rx_ring[i].lro_mgr.features |= LRO_F_NAPI;
1640 adapter->rx_ring[i].lro_mgr.dev = adapter->netdev;
1641 adapter->rx_ring[i].lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1642 adapter->rx_ring[i].lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1643
1644 ixgbe_configure_srrctl(adapter, j);
1645 }
1646
1647 /*
1648 * For VMDq support of different descriptor types or
1649 * buffer sizes through the use of multiple SRRCTL
1650 * registers, RDRXCTL.MVMEN must be set to 1
1651 *
1652 * also, the manual doesn't mention it clearly but DCA hints
1653 * will only use queue 0's tags unless this bit is set. Side
1654 * effects of setting this bit are only that SRRCTL must be
1655 * fully programmed [0..15]
1656 */
1657 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
1658 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
1659 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
1660
1661
1662 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
1663 /* Fill out redirection table */
1664 for (i = 0, j = 0; i < 128; i++, j++) {
1665 if (j == adapter->ring_feature[RING_F_RSS].indices)
1666 j = 0;
1667 /* reta = 4-byte sliding window of
1668 * 0x00..(indices-1)(indices-1)00..etc. */
1669 reta = (reta << 8) | (j * 0x11);
1670 if ((i & 3) == 3)
1671 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
1672 }
1673
1674 /* Fill out hash function seeds */
1675 for (i = 0; i < 10; i++)
1676 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
1677
1678 mrqc = IXGBE_MRQC_RSSEN
1679 /* Perform hash on these packet types */
1680 | IXGBE_MRQC_RSS_FIELD_IPV4
1681 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
1682 | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
1683 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP
1684 | IXGBE_MRQC_RSS_FIELD_IPV6_EX
1685 | IXGBE_MRQC_RSS_FIELD_IPV6
1686 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
1687 | IXGBE_MRQC_RSS_FIELD_IPV6_UDP
1688 | IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP;
1689 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
1690 }
1691
1692 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
1693
1694 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
1695 adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
1696 /* Disable indicating checksum in descriptor, enables
1697 * RSS hash */
1698 rxcsum |= IXGBE_RXCSUM_PCSD;
1699 }
1700 if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
1701 /* Enable IPv4 payload checksum for UDP fragments
1702 * if PCSD is not set */
1703 rxcsum |= IXGBE_RXCSUM_IPPCSE;
1704 }
1705
1706 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
1707 }
1708
1709 static void ixgbe_vlan_rx_register(struct net_device *netdev,
1710 struct vlan_group *grp)
1711 {
1712 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713 u32 ctrl;
1714
1715 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1716 ixgbe_irq_disable(adapter);
1717 adapter->vlgrp = grp;
1718
1719 if (grp) {
1720 /* enable VLAN tag insert/strip */
1721 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
1722 ctrl |= IXGBE_VLNCTRL_VME;
1723 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
1724 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
1725 }
1726
1727 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1728 ixgbe_irq_enable(adapter);
1729 }
1730
1731 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
1732 {
1733 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1734 struct ixgbe_hw *hw = &adapter->hw;
1735
1736 /* add VID to filter table */
1737 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
1738 }
1739
1740 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
1741 {
1742 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1743 struct ixgbe_hw *hw = &adapter->hw;
1744
1745 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1746 ixgbe_irq_disable(adapter);
1747
1748 vlan_group_set_device(adapter->vlgrp, vid, NULL);
1749
1750 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1751 ixgbe_irq_enable(adapter);
1752
1753 /* remove VID from filter table */
1754 hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
1755 }
1756
1757 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
1758 {
1759 ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
1760
1761 if (adapter->vlgrp) {
1762 u16 vid;
1763 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
1764 if (!vlan_group_get_device(adapter->vlgrp, vid))
1765 continue;
1766 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
1767 }
1768 }
1769 }
1770
1771 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
1772 {
1773 struct dev_mc_list *mc_ptr;
1774 u8 *addr = *mc_addr_ptr;
1775 *vmdq = 0;
1776
1777 mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
1778 if (mc_ptr->next)
1779 *mc_addr_ptr = mc_ptr->next->dmi_addr;
1780 else
1781 *mc_addr_ptr = NULL;
1782
1783 return addr;
1784 }
1785
1786 /**
1787 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
1788 * @netdev: network interface device structure
1789 *
1790 * The set_rx_method entry point is called whenever the unicast/multicast
1791 * address list or the network interface flags are updated. This routine is
1792 * responsible for configuring the hardware for proper unicast, multicast and
1793 * promiscuous mode.
1794 **/
1795 static void ixgbe_set_rx_mode(struct net_device *netdev)
1796 {
1797 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1798 struct ixgbe_hw *hw = &adapter->hw;
1799 u32 fctrl, vlnctrl;
1800 u8 *addr_list = NULL;
1801 int addr_count = 0;
1802
1803 /* Check for Promiscuous and All Multicast modes */
1804
1805 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
1806 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
1807
1808 if (netdev->flags & IFF_PROMISC) {
1809 hw->addr_ctrl.user_set_promisc = 1;
1810 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1811 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
1812 } else {
1813 if (netdev->flags & IFF_ALLMULTI) {
1814 fctrl |= IXGBE_FCTRL_MPE;
1815 fctrl &= ~IXGBE_FCTRL_UPE;
1816 } else {
1817 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
1818 }
1819 vlnctrl |= IXGBE_VLNCTRL_VFE;
1820 hw->addr_ctrl.user_set_promisc = 0;
1821 }
1822
1823 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
1824 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
1825
1826 /* reprogram secondary unicast list */
1827 addr_count = netdev->uc_count;
1828 if (addr_count)
1829 addr_list = netdev->uc_list->dmi_addr;
1830 hw->mac.ops.update_uc_addr_list(hw, addr_list, addr_count,
1831 ixgbe_addr_list_itr);
1832
1833 /* reprogram multicast list */
1834 addr_count = netdev->mc_count;
1835 if (addr_count)
1836 addr_list = netdev->mc_list->dmi_addr;
1837 hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
1838 ixgbe_addr_list_itr);
1839 }
1840
1841 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
1842 {
1843 int q_idx;
1844 struct ixgbe_q_vector *q_vector;
1845 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1846
1847 /* legacy and MSI only use one vector */
1848 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1849 q_vectors = 1;
1850
1851 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1852 struct napi_struct *napi;
1853 q_vector = &adapter->q_vector[q_idx];
1854 if (!q_vector->rxr_count)
1855 continue;
1856 napi = &q_vector->napi;
1857 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) &&
1858 (q_vector->rxr_count > 1))
1859 napi->poll = &ixgbe_clean_rxonly_many;
1860
1861 napi_enable(napi);
1862 }
1863 }
1864
1865 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
1866 {
1867 int q_idx;
1868 struct ixgbe_q_vector *q_vector;
1869 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1870
1871 /* legacy and MSI only use one vector */
1872 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1873 q_vectors = 1;
1874
1875 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
1876 q_vector = &adapter->q_vector[q_idx];
1877 if (!q_vector->rxr_count)
1878 continue;
1879 napi_disable(&q_vector->napi);
1880 }
1881 }
1882
1883 static void ixgbe_configure(struct ixgbe_adapter *adapter)
1884 {
1885 struct net_device *netdev = adapter->netdev;
1886 int i;
1887
1888 ixgbe_set_rx_mode(netdev);
1889
1890 ixgbe_restore_vlan(adapter);
1891
1892 ixgbe_configure_tx(adapter);
1893 ixgbe_configure_rx(adapter);
1894 for (i = 0; i < adapter->num_rx_queues; i++)
1895 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
1896 (adapter->rx_ring[i].count - 1));
1897 }
1898
1899 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
1900 {
1901 struct net_device *netdev = adapter->netdev;
1902 struct ixgbe_hw *hw = &adapter->hw;
1903 int i, j = 0;
1904 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1905 u32 txdctl, rxdctl, mhadd;
1906 u32 gpie;
1907
1908 ixgbe_get_hw_control(adapter);
1909
1910 if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
1911 (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
1912 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1913 gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
1914 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
1915 } else {
1916 /* MSI only */
1917 gpie = 0;
1918 }
1919 /* XXX: to interrupt immediately for EICS writes, enable this */
1920 /* gpie |= IXGBE_GPIE_EIMEN; */
1921 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
1922 }
1923
1924 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
1925 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
1926 * specifically only auto mask tx and rx interrupts */
1927 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
1928 }
1929
1930 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
1931 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
1932 mhadd &= ~IXGBE_MHADD_MFS_MASK;
1933 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
1934
1935 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
1936 }
1937
1938 for (i = 0; i < adapter->num_tx_queues; i++) {
1939 j = adapter->tx_ring[i].reg_idx;
1940 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
1941 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
1942 txdctl |= (8 << 16);
1943 txdctl |= IXGBE_TXDCTL_ENABLE;
1944 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
1945 }
1946
1947 for (i = 0; i < adapter->num_rx_queues; i++) {
1948 j = adapter->rx_ring[i].reg_idx;
1949 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
1950 /* enable PTHRESH=32 descriptors (half the internal cache)
1951 * and HTHRESH=0 descriptors (to minimize latency on fetch),
1952 * this also removes a pesky rx_no_buffer_count increment */
1953 rxdctl |= 0x0020;
1954 rxdctl |= IXGBE_RXDCTL_ENABLE;
1955 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
1956 }
1957 /* enable all receives */
1958 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1959 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
1960 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxdctl);
1961
1962 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1963 ixgbe_configure_msix(adapter);
1964 else
1965 ixgbe_configure_msi_and_legacy(adapter);
1966
1967 clear_bit(__IXGBE_DOWN, &adapter->state);
1968 ixgbe_napi_enable_all(adapter);
1969
1970 /* clear any pending interrupts, may auto mask */
1971 IXGBE_READ_REG(hw, IXGBE_EICR);
1972
1973 ixgbe_irq_enable(adapter);
1974
1975 /* bring the link up in the watchdog, this could race with our first
1976 * link up interrupt but shouldn't be a problem */
1977 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1978 adapter->link_check_timeout = jiffies;
1979 mod_timer(&adapter->watchdog_timer, jiffies);
1980 return 0;
1981 }
1982
1983 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
1984 {
1985 WARN_ON(in_interrupt());
1986 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
1987 msleep(1);
1988 ixgbe_down(adapter);
1989 ixgbe_up(adapter);
1990 clear_bit(__IXGBE_RESETTING, &adapter->state);
1991 }
1992
1993 int ixgbe_up(struct ixgbe_adapter *adapter)
1994 {
1995 /* hardware has been reset, we need to reload some things */
1996 ixgbe_configure(adapter);
1997
1998 return ixgbe_up_complete(adapter);
1999 }
2000
2001 void ixgbe_reset(struct ixgbe_adapter *adapter)
2002 {
2003 struct ixgbe_hw *hw = &adapter->hw;
2004 if (hw->mac.ops.init_hw(hw))
2005 dev_err(&adapter->pdev->dev, "Hardware Error\n");
2006
2007 /* reprogram the RAR[0] in case user changed it. */
2008 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2009
2010 }
2011
2012 /**
2013 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2014 * @adapter: board private structure
2015 * @rx_ring: ring to free buffers from
2016 **/
2017 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2018 struct ixgbe_ring *rx_ring)
2019 {
2020 struct pci_dev *pdev = adapter->pdev;
2021 unsigned long size;
2022 unsigned int i;
2023
2024 /* Free all the Rx ring sk_buffs */
2025
2026 for (i = 0; i < rx_ring->count; i++) {
2027 struct ixgbe_rx_buffer *rx_buffer_info;
2028
2029 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2030 if (rx_buffer_info->dma) {
2031 pci_unmap_single(pdev, rx_buffer_info->dma,
2032 rx_ring->rx_buf_len,
2033 PCI_DMA_FROMDEVICE);
2034 rx_buffer_info->dma = 0;
2035 }
2036 if (rx_buffer_info->skb) {
2037 dev_kfree_skb(rx_buffer_info->skb);
2038 rx_buffer_info->skb = NULL;
2039 }
2040 if (!rx_buffer_info->page)
2041 continue;
2042 pci_unmap_page(pdev, rx_buffer_info->page_dma, PAGE_SIZE / 2,
2043 PCI_DMA_FROMDEVICE);
2044 rx_buffer_info->page_dma = 0;
2045 put_page(rx_buffer_info->page);
2046 rx_buffer_info->page = NULL;
2047 rx_buffer_info->page_offset = 0;
2048 }
2049
2050 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2051 memset(rx_ring->rx_buffer_info, 0, size);
2052
2053 /* Zero out the descriptor ring */
2054 memset(rx_ring->desc, 0, rx_ring->size);
2055
2056 rx_ring->next_to_clean = 0;
2057 rx_ring->next_to_use = 0;
2058
2059 writel(0, adapter->hw.hw_addr + rx_ring->head);
2060 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2061 }
2062
2063 /**
2064 * ixgbe_clean_tx_ring - Free Tx Buffers
2065 * @adapter: board private structure
2066 * @tx_ring: ring to be cleaned
2067 **/
2068 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2069 struct ixgbe_ring *tx_ring)
2070 {
2071 struct ixgbe_tx_buffer *tx_buffer_info;
2072 unsigned long size;
2073 unsigned int i;
2074
2075 /* Free all the Tx ring sk_buffs */
2076
2077 for (i = 0; i < tx_ring->count; i++) {
2078 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2079 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2080 }
2081
2082 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2083 memset(tx_ring->tx_buffer_info, 0, size);
2084
2085 /* Zero out the descriptor ring */
2086 memset(tx_ring->desc, 0, tx_ring->size);
2087
2088 tx_ring->next_to_use = 0;
2089 tx_ring->next_to_clean = 0;
2090
2091 writel(0, adapter->hw.hw_addr + tx_ring->head);
2092 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2093 }
2094
2095 /**
2096 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2097 * @adapter: board private structure
2098 **/
2099 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2100 {
2101 int i;
2102
2103 for (i = 0; i < adapter->num_rx_queues; i++)
2104 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2105 }
2106
2107 /**
2108 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2109 * @adapter: board private structure
2110 **/
2111 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2112 {
2113 int i;
2114
2115 for (i = 0; i < adapter->num_tx_queues; i++)
2116 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2117 }
2118
2119 void ixgbe_down(struct ixgbe_adapter *adapter)
2120 {
2121 struct net_device *netdev = adapter->netdev;
2122 struct ixgbe_hw *hw = &adapter->hw;
2123 u32 rxctrl;
2124 u32 txdctl;
2125 int i, j;
2126
2127 /* signal that we are down to the interrupt handler */
2128 set_bit(__IXGBE_DOWN, &adapter->state);
2129
2130 /* disable receives */
2131 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2132 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2133
2134 netif_tx_disable(netdev);
2135
2136 IXGBE_WRITE_FLUSH(hw);
2137 msleep(10);
2138
2139 netif_tx_stop_all_queues(netdev);
2140
2141 ixgbe_irq_disable(adapter);
2142
2143 ixgbe_napi_disable_all(adapter);
2144
2145 del_timer_sync(&adapter->watchdog_timer);
2146 cancel_work_sync(&adapter->watchdog_task);
2147
2148 /* disable transmits in the hardware now that interrupts are off */
2149 for (i = 0; i < adapter->num_tx_queues; i++) {
2150 j = adapter->tx_ring[i].reg_idx;
2151 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2152 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2153 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2154 }
2155
2156 netif_carrier_off(netdev);
2157
2158 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2159 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2160 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
2161 dca_remove_requester(&adapter->pdev->dev);
2162 }
2163
2164 #endif
2165 if (!pci_channel_offline(adapter->pdev))
2166 ixgbe_reset(adapter);
2167 ixgbe_clean_all_tx_rings(adapter);
2168 ixgbe_clean_all_rx_rings(adapter);
2169
2170 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2171 /* since we reset the hardware DCA settings were cleared */
2172 if (dca_add_requester(&adapter->pdev->dev) == 0) {
2173 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
2174 /* always use CB2 mode, difference is masked
2175 * in the CB driver */
2176 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
2177 ixgbe_setup_dca(adapter);
2178 }
2179 #endif
2180 }
2181
2182 /**
2183 * ixgbe_poll - NAPI Rx polling callback
2184 * @napi: structure for representing this polling device
2185 * @budget: how many packets driver is allowed to clean
2186 *
2187 * This function is used for legacy and MSI, NAPI mode
2188 **/
2189 static int ixgbe_poll(struct napi_struct *napi, int budget)
2190 {
2191 struct ixgbe_q_vector *q_vector = container_of(napi,
2192 struct ixgbe_q_vector, napi);
2193 struct ixgbe_adapter *adapter = q_vector->adapter;
2194 int tx_cleaned, work_done = 0;
2195
2196 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
2197 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2198 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2199 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2200 }
2201 #endif
2202
2203 tx_cleaned = ixgbe_clean_tx_irq(adapter, adapter->tx_ring);
2204 ixgbe_clean_rx_irq(adapter, adapter->rx_ring, &work_done, budget);
2205
2206 if (tx_cleaned)
2207 work_done = budget;
2208
2209 /* If budget not fully consumed, exit the polling mode */
2210 if (work_done < budget) {
2211 netif_rx_complete(adapter->netdev, napi);
2212 if (adapter->itr_setting & 3)
2213 ixgbe_set_itr(adapter);
2214 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2215 ixgbe_irq_enable(adapter);
2216 }
2217 return work_done;
2218 }
2219
2220 /**
2221 * ixgbe_tx_timeout - Respond to a Tx Hang
2222 * @netdev: network interface device structure
2223 **/
2224 static void ixgbe_tx_timeout(struct net_device *netdev)
2225 {
2226 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2227
2228 /* Do the reset outside of interrupt context */
2229 schedule_work(&adapter->reset_task);
2230 }
2231
2232 static void ixgbe_reset_task(struct work_struct *work)
2233 {
2234 struct ixgbe_adapter *adapter;
2235 adapter = container_of(work, struct ixgbe_adapter, reset_task);
2236
2237 adapter->tx_timeout_count++;
2238
2239 ixgbe_reinit_locked(adapter);
2240 }
2241
2242 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
2243 {
2244 int nrq = 1, ntq = 1;
2245 int feature_mask = 0, rss_i, rss_m;
2246
2247 /* Number of supported queues */
2248 switch (adapter->hw.mac.type) {
2249 case ixgbe_mac_82598EB:
2250 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2251 rss_m = 0;
2252 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2253
2254 switch (adapter->flags & feature_mask) {
2255 case (IXGBE_FLAG_RSS_ENABLED):
2256 rss_m = 0xF;
2257 nrq = rss_i;
2258 ntq = rss_i;
2259 break;
2260 case 0:
2261 default:
2262 rss_i = 0;
2263 rss_m = 0;
2264 nrq = 1;
2265 ntq = 1;
2266 break;
2267 }
2268
2269 adapter->ring_feature[RING_F_RSS].indices = rss_i;
2270 adapter->ring_feature[RING_F_RSS].mask = rss_m;
2271 break;
2272 default:
2273 nrq = 1;
2274 ntq = 1;
2275 break;
2276 }
2277
2278 adapter->num_rx_queues = nrq;
2279 adapter->num_tx_queues = ntq;
2280 }
2281
2282 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
2283 int vectors)
2284 {
2285 int err, vector_threshold;
2286
2287 /* We'll want at least 3 (vector_threshold):
2288 * 1) TxQ[0] Cleanup
2289 * 2) RxQ[0] Cleanup
2290 * 3) Other (Link Status Change, etc.)
2291 * 4) TCP Timer (optional)
2292 */
2293 vector_threshold = MIN_MSIX_COUNT;
2294
2295 /* The more we get, the more we will assign to Tx/Rx Cleanup
2296 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
2297 * Right now, we simply care about how many we'll get; we'll
2298 * set them up later while requesting irq's.
2299 */
2300 while (vectors >= vector_threshold) {
2301 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
2302 vectors);
2303 if (!err) /* Success in acquiring all requested vectors. */
2304 break;
2305 else if (err < 0)
2306 vectors = 0; /* Nasty failure, quit now */
2307 else /* err == number of vectors we should try again with */
2308 vectors = err;
2309 }
2310
2311 if (vectors < vector_threshold) {
2312 /* Can't allocate enough MSI-X interrupts? Oh well.
2313 * This just means we'll go with either a single MSI
2314 * vector or fall back to legacy interrupts.
2315 */
2316 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
2317 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2318 kfree(adapter->msix_entries);
2319 adapter->msix_entries = NULL;
2320 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2321 ixgbe_set_num_queues(adapter);
2322 } else {
2323 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
2324 adapter->num_msix_vectors = vectors;
2325 }
2326 }
2327
2328 /**
2329 * ixgbe_cache_ring_register - Descriptor ring to register mapping
2330 * @adapter: board private structure to initialize
2331 *
2332 * Once we know the feature-set enabled for the device, we'll cache
2333 * the register offset the descriptor ring is assigned to.
2334 **/
2335 static void __devinit ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
2336 {
2337 int feature_mask = 0, rss_i;
2338 int i, txr_idx, rxr_idx;
2339
2340 /* Number of supported queues */
2341 switch (adapter->hw.mac.type) {
2342 case ixgbe_mac_82598EB:
2343 rss_i = adapter->ring_feature[RING_F_RSS].indices;
2344 txr_idx = 0;
2345 rxr_idx = 0;
2346 feature_mask |= IXGBE_FLAG_RSS_ENABLED;
2347 switch (adapter->flags & feature_mask) {
2348 case (IXGBE_FLAG_RSS_ENABLED):
2349 for (i = 0; i < adapter->num_rx_queues; i++)
2350 adapter->rx_ring[i].reg_idx = i;
2351 for (i = 0; i < adapter->num_tx_queues; i++)
2352 adapter->tx_ring[i].reg_idx = i;
2353 break;
2354 case 0:
2355 default:
2356 break;
2357 }
2358 break;
2359 default:
2360 break;
2361 }
2362 }
2363
2364 /**
2365 * ixgbe_alloc_queues - Allocate memory for all rings
2366 * @adapter: board private structure to initialize
2367 *
2368 * We allocate one ring per queue at run-time since we don't know the
2369 * number of queues at compile-time. The polling_netdev array is
2370 * intended for Multiqueue, but should work fine with a single queue.
2371 **/
2372 static int __devinit ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
2373 {
2374 int i;
2375
2376 adapter->tx_ring = kcalloc(adapter->num_tx_queues,
2377 sizeof(struct ixgbe_ring), GFP_KERNEL);
2378 if (!adapter->tx_ring)
2379 goto err_tx_ring_allocation;
2380
2381 adapter->rx_ring = kcalloc(adapter->num_rx_queues,
2382 sizeof(struct ixgbe_ring), GFP_KERNEL);
2383 if (!adapter->rx_ring)
2384 goto err_rx_ring_allocation;
2385
2386 for (i = 0; i < adapter->num_tx_queues; i++) {
2387 adapter->tx_ring[i].count = adapter->tx_ring_count;
2388 adapter->tx_ring[i].queue_index = i;
2389 }
2390
2391 for (i = 0; i < adapter->num_rx_queues; i++) {
2392 adapter->rx_ring[i].count = adapter->rx_ring_count;
2393 adapter->rx_ring[i].queue_index = i;
2394 }
2395
2396 ixgbe_cache_ring_register(adapter);
2397
2398 return 0;
2399
2400 err_rx_ring_allocation:
2401 kfree(adapter->tx_ring);
2402 err_tx_ring_allocation:
2403 return -ENOMEM;
2404 }
2405
2406 /**
2407 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
2408 * @adapter: board private structure to initialize
2409 *
2410 * Attempt to configure the interrupts using the best available
2411 * capabilities of the hardware and the kernel.
2412 **/
2413 static int __devinit ixgbe_set_interrupt_capability(struct ixgbe_adapter
2414 *adapter)
2415 {
2416 int err = 0;
2417 int vector, v_budget;
2418
2419 /*
2420 * It's easy to be greedy for MSI-X vectors, but it really
2421 * doesn't do us much good if we have a lot more vectors
2422 * than CPU's. So let's be conservative and only ask for
2423 * (roughly) twice the number of vectors as there are CPU's.
2424 */
2425 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
2426 (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
2427
2428 /*
2429 * At the same time, hardware can only support a maximum of
2430 * MAX_MSIX_COUNT vectors. With features such as RSS and VMDq,
2431 * we can easily reach upwards of 64 Rx descriptor queues and
2432 * 32 Tx queues. Thus, we cap it off in those rare cases where
2433 * the cpu count also exceeds our vector limit.
2434 */
2435 v_budget = min(v_budget, MAX_MSIX_COUNT);
2436
2437 /* A failure in MSI-X entry allocation isn't fatal, but it does
2438 * mean we disable MSI-X capabilities of the adapter. */
2439 adapter->msix_entries = kcalloc(v_budget,
2440 sizeof(struct msix_entry), GFP_KERNEL);
2441 if (!adapter->msix_entries) {
2442 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
2443 ixgbe_set_num_queues(adapter);
2444 kfree(adapter->tx_ring);
2445 kfree(adapter->rx_ring);
2446 err = ixgbe_alloc_queues(adapter);
2447 if (err) {
2448 DPRINTK(PROBE, ERR, "Unable to allocate memory "
2449 "for queues\n");
2450 goto out;
2451 }
2452
2453 goto try_msi;
2454 }
2455
2456 for (vector = 0; vector < v_budget; vector++)
2457 adapter->msix_entries[vector].entry = vector;
2458
2459 ixgbe_acquire_msix_vectors(adapter, v_budget);
2460
2461 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2462 goto out;
2463
2464 try_msi:
2465 err = pci_enable_msi(adapter->pdev);
2466 if (!err) {
2467 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
2468 } else {
2469 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
2470 "falling back to legacy. Error: %d\n", err);
2471 /* reset err */
2472 err = 0;
2473 }
2474
2475 out:
2476 /* Notify the stack of the (possibly) reduced Tx Queue count. */
2477 adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
2478
2479 return err;
2480 }
2481
2482 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
2483 {
2484 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2485 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2486 pci_disable_msix(adapter->pdev);
2487 kfree(adapter->msix_entries);
2488 adapter->msix_entries = NULL;
2489 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2490 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
2491 pci_disable_msi(adapter->pdev);
2492 }
2493 return;
2494 }
2495
2496 /**
2497 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
2498 * @adapter: board private structure to initialize
2499 *
2500 * We determine which interrupt scheme to use based on...
2501 * - Kernel support (MSI, MSI-X)
2502 * - which can be user-defined (via MODULE_PARAM)
2503 * - Hardware queue count (num_*_queues)
2504 * - defined by miscellaneous hardware support/features (RSS, etc.)
2505 **/
2506 static int __devinit ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
2507 {
2508 int err;
2509
2510 /* Number of supported queues */
2511 ixgbe_set_num_queues(adapter);
2512
2513 err = ixgbe_alloc_queues(adapter);
2514 if (err) {
2515 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
2516 goto err_alloc_queues;
2517 }
2518
2519 err = ixgbe_set_interrupt_capability(adapter);
2520 if (err) {
2521 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
2522 goto err_set_interrupt;
2523 }
2524
2525 DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
2526 "Tx Queue count = %u\n",
2527 (adapter->num_rx_queues > 1) ? "Enabled" :
2528 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
2529
2530 set_bit(__IXGBE_DOWN, &adapter->state);
2531
2532 return 0;
2533
2534 err_set_interrupt:
2535 kfree(adapter->tx_ring);
2536 kfree(adapter->rx_ring);
2537 err_alloc_queues:
2538 return err;
2539 }
2540
2541 /**
2542 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
2543 * @adapter: board private structure to initialize
2544 *
2545 * ixgbe_sw_init initializes the Adapter private data structure.
2546 * Fields are initialized based on PCI device information and
2547 * OS network device settings (MTU size).
2548 **/
2549 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
2550 {
2551 struct ixgbe_hw *hw = &adapter->hw;
2552 struct pci_dev *pdev = adapter->pdev;
2553 unsigned int rss;
2554
2555 /* PCI config space info */
2556
2557 hw->vendor_id = pdev->vendor;
2558 hw->device_id = pdev->device;
2559 hw->revision_id = pdev->revision;
2560 hw->subsystem_vendor_id = pdev->subsystem_vendor;
2561 hw->subsystem_device_id = pdev->subsystem_device;
2562
2563 /* Set capability flags */
2564 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
2565 adapter->ring_feature[RING_F_RSS].indices = rss;
2566 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
2567
2568 /* default flow control settings */
2569 hw->fc.original_type = ixgbe_fc_none;
2570 hw->fc.type = ixgbe_fc_none;
2571 hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
2572 hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
2573 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
2574 hw->fc.send_xon = true;
2575
2576 /* select 10G link by default */
2577 hw->mac.link_mode_select = IXGBE_AUTOC_LMS_10G_LINK_NO_AN;
2578
2579 /* enable itr by default in dynamic mode */
2580 adapter->itr_setting = 1;
2581 adapter->eitr_param = 20000;
2582
2583 /* set defaults for eitr in MegaBytes */
2584 adapter->eitr_low = 10;
2585 adapter->eitr_high = 20;
2586
2587 /* set default ring sizes */
2588 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
2589 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
2590
2591 /* initialize eeprom parameters */
2592 if (ixgbe_init_eeprom_params_generic(hw)) {
2593 dev_err(&pdev->dev, "EEPROM initialization failed\n");
2594 return -EIO;
2595 }
2596
2597 /* enable rx csum by default */
2598 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
2599
2600 set_bit(__IXGBE_DOWN, &adapter->state);
2601
2602 return 0;
2603 }
2604
2605 /**
2606 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
2607 * @adapter: board private structure
2608 * @tx_ring: tx descriptor ring (for a specific queue) to setup
2609 *
2610 * Return 0 on success, negative on failure
2611 **/
2612 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
2613 struct ixgbe_ring *tx_ring)
2614 {
2615 struct pci_dev *pdev = adapter->pdev;
2616 int size;
2617
2618 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2619 tx_ring->tx_buffer_info = vmalloc(size);
2620 if (!tx_ring->tx_buffer_info)
2621 goto err;
2622 memset(tx_ring->tx_buffer_info, 0, size);
2623
2624 /* round up to nearest 4K */
2625 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc) +
2626 sizeof(u32);
2627 tx_ring->size = ALIGN(tx_ring->size, 4096);
2628
2629 tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
2630 &tx_ring->dma);
2631 if (!tx_ring->desc)
2632 goto err;
2633
2634 tx_ring->next_to_use = 0;
2635 tx_ring->next_to_clean = 0;
2636 tx_ring->work_limit = tx_ring->count;
2637 return 0;
2638
2639 err:
2640 vfree(tx_ring->tx_buffer_info);
2641 tx_ring->tx_buffer_info = NULL;
2642 DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
2643 "descriptor ring\n");
2644 return -ENOMEM;
2645 }
2646
2647 /**
2648 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
2649 * @adapter: board private structure
2650 *
2651 * If this function returns with an error, then it's possible one or
2652 * more of the rings is populated (while the rest are not). It is the
2653 * callers duty to clean those orphaned rings.
2654 *
2655 * Return 0 on success, negative on failure
2656 **/
2657 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
2658 {
2659 int i, err = 0;
2660
2661 for (i = 0; i < adapter->num_tx_queues; i++) {
2662 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
2663 if (!err)
2664 continue;
2665 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
2666 break;
2667 }
2668
2669 return err;
2670 }
2671
2672 /**
2673 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
2674 * @adapter: board private structure
2675 * @rx_ring: rx descriptor ring (for a specific queue) to setup
2676 *
2677 * Returns 0 on success, negative on failure
2678 **/
2679 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
2680 struct ixgbe_ring *rx_ring)
2681 {
2682 struct pci_dev *pdev = adapter->pdev;
2683 int size;
2684
2685 size = sizeof(struct net_lro_desc) * IXGBE_MAX_LRO_DESCRIPTORS;
2686 rx_ring->lro_mgr.lro_arr = vmalloc(size);
2687 if (!rx_ring->lro_mgr.lro_arr)
2688 return -ENOMEM;
2689 memset(rx_ring->lro_mgr.lro_arr, 0, size);
2690
2691 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2692 rx_ring->rx_buffer_info = vmalloc(size);
2693 if (!rx_ring->rx_buffer_info) {
2694 DPRINTK(PROBE, ERR,
2695 "vmalloc allocation failed for the rx desc ring\n");
2696 goto alloc_failed;
2697 }
2698 memset(rx_ring->rx_buffer_info, 0, size);
2699
2700 /* Round up to nearest 4K */
2701 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
2702 rx_ring->size = ALIGN(rx_ring->size, 4096);
2703
2704 rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
2705
2706 if (!rx_ring->desc) {
2707 DPRINTK(PROBE, ERR,
2708 "Memory allocation failed for the rx desc ring\n");
2709 vfree(rx_ring->rx_buffer_info);
2710 goto alloc_failed;
2711 }
2712
2713 rx_ring->next_to_clean = 0;
2714 rx_ring->next_to_use = 0;
2715
2716 return 0;
2717
2718 alloc_failed:
2719 vfree(rx_ring->lro_mgr.lro_arr);
2720 rx_ring->lro_mgr.lro_arr = NULL;
2721 return -ENOMEM;
2722 }
2723
2724 /**
2725 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
2726 * @adapter: board private structure
2727 *
2728 * If this function returns with an error, then it's possible one or
2729 * more of the rings is populated (while the rest are not). It is the
2730 * callers duty to clean those orphaned rings.
2731 *
2732 * Return 0 on success, negative on failure
2733 **/
2734
2735 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
2736 {
2737 int i, err = 0;
2738
2739 for (i = 0; i < adapter->num_rx_queues; i++) {
2740 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
2741 if (!err)
2742 continue;
2743 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
2744 break;
2745 }
2746
2747 return err;
2748 }
2749
2750 /**
2751 * ixgbe_free_tx_resources - Free Tx Resources per Queue
2752 * @adapter: board private structure
2753 * @tx_ring: Tx descriptor ring for a specific queue
2754 *
2755 * Free all transmit software resources
2756 **/
2757 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
2758 struct ixgbe_ring *tx_ring)
2759 {
2760 struct pci_dev *pdev = adapter->pdev;
2761
2762 ixgbe_clean_tx_ring(adapter, tx_ring);
2763
2764 vfree(tx_ring->tx_buffer_info);
2765 tx_ring->tx_buffer_info = NULL;
2766
2767 pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
2768
2769 tx_ring->desc = NULL;
2770 }
2771
2772 /**
2773 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
2774 * @adapter: board private structure
2775 *
2776 * Free all transmit software resources
2777 **/
2778 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
2779 {
2780 int i;
2781
2782 for (i = 0; i < adapter->num_tx_queues; i++)
2783 ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
2784 }
2785
2786 /**
2787 * ixgbe_free_rx_resources - Free Rx Resources
2788 * @adapter: board private structure
2789 * @rx_ring: ring to clean the resources from
2790 *
2791 * Free all receive software resources
2792 **/
2793 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
2794 struct ixgbe_ring *rx_ring)
2795 {
2796 struct pci_dev *pdev = adapter->pdev;
2797
2798 vfree(rx_ring->lro_mgr.lro_arr);
2799 rx_ring->lro_mgr.lro_arr = NULL;
2800
2801 ixgbe_clean_rx_ring(adapter, rx_ring);
2802
2803 vfree(rx_ring->rx_buffer_info);
2804 rx_ring->rx_buffer_info = NULL;
2805
2806 pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
2807
2808 rx_ring->desc = NULL;
2809 }
2810
2811 /**
2812 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
2813 * @adapter: board private structure
2814 *
2815 * Free all receive software resources
2816 **/
2817 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
2818 {
2819 int i;
2820
2821 for (i = 0; i < adapter->num_rx_queues; i++)
2822 ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
2823 }
2824
2825 /**
2826 * ixgbe_change_mtu - Change the Maximum Transfer Unit
2827 * @netdev: network interface device structure
2828 * @new_mtu: new value for maximum frame size
2829 *
2830 * Returns 0 on success, negative on failure
2831 **/
2832 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
2833 {
2834 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2835 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
2836
2837 /* MTU < 68 is an error and causes problems on some kernels */
2838 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
2839 return -EINVAL;
2840
2841 DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
2842 netdev->mtu, new_mtu);
2843 /* must set new MTU before calling down or up */
2844 netdev->mtu = new_mtu;
2845
2846 if (netif_running(netdev))
2847 ixgbe_reinit_locked(adapter);
2848
2849 return 0;
2850 }
2851
2852 /**
2853 * ixgbe_open - Called when a network interface is made active
2854 * @netdev: network interface device structure
2855 *
2856 * Returns 0 on success, negative value on failure
2857 *
2858 * The open entry point is called when a network interface is made
2859 * active by the system (IFF_UP). At this point all resources needed
2860 * for transmit and receive operations are allocated, the interrupt
2861 * handler is registered with the OS, the watchdog timer is started,
2862 * and the stack is notified that the interface is ready.
2863 **/
2864 static int ixgbe_open(struct net_device *netdev)
2865 {
2866 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2867 int err;
2868
2869 /* disallow open during test */
2870 if (test_bit(__IXGBE_TESTING, &adapter->state))
2871 return -EBUSY;
2872
2873 /* allocate transmit descriptors */
2874 err = ixgbe_setup_all_tx_resources(adapter);
2875 if (err)
2876 goto err_setup_tx;
2877
2878 /* allocate receive descriptors */
2879 err = ixgbe_setup_all_rx_resources(adapter);
2880 if (err)
2881 goto err_setup_rx;
2882
2883 ixgbe_configure(adapter);
2884
2885 err = ixgbe_request_irq(adapter);
2886 if (err)
2887 goto err_req_irq;
2888
2889 err = ixgbe_up_complete(adapter);
2890 if (err)
2891 goto err_up;
2892
2893 netif_tx_start_all_queues(netdev);
2894
2895 return 0;
2896
2897 err_up:
2898 ixgbe_release_hw_control(adapter);
2899 ixgbe_free_irq(adapter);
2900 err_req_irq:
2901 ixgbe_free_all_rx_resources(adapter);
2902 err_setup_rx:
2903 ixgbe_free_all_tx_resources(adapter);
2904 err_setup_tx:
2905 ixgbe_reset(adapter);
2906
2907 return err;
2908 }
2909
2910 /**
2911 * ixgbe_close - Disables a network interface
2912 * @netdev: network interface device structure
2913 *
2914 * Returns 0, this is not allowed to fail
2915 *
2916 * The close entry point is called when an interface is de-activated
2917 * by the OS. The hardware is still under the drivers control, but
2918 * needs to be disabled. A global MAC reset is issued to stop the
2919 * hardware, and all transmit and receive resources are freed.
2920 **/
2921 static int ixgbe_close(struct net_device *netdev)
2922 {
2923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2924
2925 ixgbe_down(adapter);
2926 ixgbe_free_irq(adapter);
2927
2928 ixgbe_free_all_tx_resources(adapter);
2929 ixgbe_free_all_rx_resources(adapter);
2930
2931 ixgbe_release_hw_control(adapter);
2932
2933 return 0;
2934 }
2935
2936 /**
2937 * ixgbe_napi_add_all - prep napi structs for use
2938 * @adapter: private struct
2939 * helper function to napi_add each possible q_vector->napi
2940 */
2941 static void ixgbe_napi_add_all(struct ixgbe_adapter *adapter)
2942 {
2943 int q_idx, q_vectors;
2944 int (*poll)(struct napi_struct *, int);
2945
2946 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2947 poll = &ixgbe_clean_rxonly;
2948 /* Only enable as many vectors as we have rx queues. */
2949 q_vectors = adapter->num_rx_queues;
2950 } else {
2951 poll = &ixgbe_poll;
2952 /* only one q_vector for legacy modes */
2953 q_vectors = 1;
2954 }
2955
2956 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2957 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
2958 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
2959 }
2960 }
2961
2962 static void ixgbe_napi_del_all(struct ixgbe_adapter *adapter)
2963 {
2964 int q_idx;
2965 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2966
2967 /* legacy and MSI only use one vector */
2968 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2969 q_vectors = 1;
2970
2971 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2972 struct ixgbe_q_vector *q_vector = &adapter->q_vector[q_idx];
2973 if (!q_vector->rxr_count)
2974 continue;
2975 netif_napi_del(&q_vector->napi);
2976 }
2977 }
2978
2979 #ifdef CONFIG_PM
2980 static int ixgbe_resume(struct pci_dev *pdev)
2981 {
2982 struct net_device *netdev = pci_get_drvdata(pdev);
2983 struct ixgbe_adapter *adapter = netdev_priv(netdev);
2984 u32 err;
2985
2986 pci_set_power_state(pdev, PCI_D0);
2987 pci_restore_state(pdev);
2988 err = pci_enable_device(pdev);
2989 if (err) {
2990 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
2991 "suspend\n");
2992 return err;
2993 }
2994 pci_set_master(pdev);
2995
2996 pci_enable_wake(pdev, PCI_D3hot, 0);
2997 pci_enable_wake(pdev, PCI_D3cold, 0);
2998
2999 err = ixgbe_init_interrupt_scheme(adapter);
3000 if (err) {
3001 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
3002 "device\n");
3003 return err;
3004 }
3005
3006 ixgbe_napi_add_all(adapter);
3007 ixgbe_reset(adapter);
3008
3009 if (netif_running(netdev)) {
3010 err = ixgbe_open(adapter->netdev);
3011 if (err)
3012 return err;
3013 }
3014
3015 netif_device_attach(netdev);
3016
3017 return 0;
3018 }
3019
3020 #endif /* CONFIG_PM */
3021 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
3022 {
3023 struct net_device *netdev = pci_get_drvdata(pdev);
3024 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3025 #ifdef CONFIG_PM
3026 int retval = 0;
3027 #endif
3028
3029 netif_device_detach(netdev);
3030
3031 if (netif_running(netdev)) {
3032 ixgbe_down(adapter);
3033 ixgbe_free_irq(adapter);
3034 ixgbe_free_all_tx_resources(adapter);
3035 ixgbe_free_all_rx_resources(adapter);
3036 }
3037 ixgbe_reset_interrupt_capability(adapter);
3038 ixgbe_napi_del_all(adapter);
3039 kfree(adapter->tx_ring);
3040 kfree(adapter->rx_ring);
3041
3042 #ifdef CONFIG_PM
3043 retval = pci_save_state(pdev);
3044 if (retval)
3045 return retval;
3046 #endif
3047
3048 pci_enable_wake(pdev, PCI_D3hot, 0);
3049 pci_enable_wake(pdev, PCI_D3cold, 0);
3050
3051 ixgbe_release_hw_control(adapter);
3052
3053 pci_disable_device(pdev);
3054
3055 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3056
3057 return 0;
3058 }
3059
3060 static void ixgbe_shutdown(struct pci_dev *pdev)
3061 {
3062 ixgbe_suspend(pdev, PMSG_SUSPEND);
3063 }
3064
3065 /**
3066 * ixgbe_update_stats - Update the board statistics counters.
3067 * @adapter: board private structure
3068 **/
3069 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
3070 {
3071 struct ixgbe_hw *hw = &adapter->hw;
3072 u64 total_mpc = 0;
3073 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
3074
3075 adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
3076 for (i = 0; i < 8; i++) {
3077 /* for packet buffers not used, the register should read 0 */
3078 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
3079 missed_rx += mpc;
3080 adapter->stats.mpc[i] += mpc;
3081 total_mpc += adapter->stats.mpc[i];
3082 adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
3083 }
3084 adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
3085 /* work around hardware counting issue */
3086 adapter->stats.gprc -= missed_rx;
3087
3088 /* 82598 hardware only has a 32 bit counter in the high register */
3089 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
3090 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
3091 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
3092 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
3093 adapter->stats.bprc += bprc;
3094 adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
3095 adapter->stats.mprc -= bprc;
3096 adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
3097 adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
3098 adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
3099 adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
3100 adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
3101 adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
3102 adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
3103 adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
3104 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
3105 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
3106 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
3107 adapter->stats.lxontxc += lxon;
3108 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
3109 adapter->stats.lxofftxc += lxoff;
3110 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3111 adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
3112 adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
3113 /*
3114 * 82598 errata - tx of flow control packets is included in tx counters
3115 */
3116 xon_off_tot = lxon + lxoff;
3117 adapter->stats.gptc -= xon_off_tot;
3118 adapter->stats.mptc -= xon_off_tot;
3119 adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
3120 adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
3121 adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
3122 adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
3123 adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
3124 adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
3125 adapter->stats.ptc64 -= xon_off_tot;
3126 adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
3127 adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
3128 adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
3129 adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
3130 adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
3131 adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
3132
3133 /* Fill out the OS statistics structure */
3134 adapter->net_stats.multicast = adapter->stats.mprc;
3135
3136 /* Rx Errors */
3137 adapter->net_stats.rx_errors = adapter->stats.crcerrs +
3138 adapter->stats.rlec;
3139 adapter->net_stats.rx_dropped = 0;
3140 adapter->net_stats.rx_length_errors = adapter->stats.rlec;
3141 adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
3142 adapter->net_stats.rx_missed_errors = total_mpc;
3143 }
3144
3145 /**
3146 * ixgbe_watchdog - Timer Call-back
3147 * @data: pointer to adapter cast into an unsigned long
3148 **/
3149 static void ixgbe_watchdog(unsigned long data)
3150 {
3151 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3152 struct ixgbe_hw *hw = &adapter->hw;
3153
3154 /* Do the watchdog outside of interrupt context due to the lovely
3155 * delays that some of the newer hardware requires */
3156 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
3157 /* Cause software interrupt to ensure rx rings are cleaned */
3158 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3159 u32 eics =
3160 (1 << (adapter->num_msix_vectors - NON_Q_VECTORS)) - 1;
3161 IXGBE_WRITE_REG(hw, IXGBE_EICS, eics);
3162 } else {
3163 /* For legacy and MSI interrupts don't set any bits that
3164 * are enabled for EIAM, because this operation would
3165 * set *both* EIMS and EICS for any bit in EIAM */
3166 IXGBE_WRITE_REG(hw, IXGBE_EICS,
3167 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
3168 }
3169 /* Reset the timer */
3170 mod_timer(&adapter->watchdog_timer,
3171 round_jiffies(jiffies + 2 * HZ));
3172 }
3173
3174 schedule_work(&adapter->watchdog_task);
3175 }
3176
3177 /**
3178 * ixgbe_watchdog_task - worker thread to bring link up
3179 * @work: pointer to work_struct containing our data
3180 **/
3181 static void ixgbe_watchdog_task(struct work_struct *work)
3182 {
3183 struct ixgbe_adapter *adapter = container_of(work,
3184 struct ixgbe_adapter,
3185 watchdog_task);
3186 struct net_device *netdev = adapter->netdev;
3187 struct ixgbe_hw *hw = &adapter->hw;
3188 u32 link_speed = adapter->link_speed;
3189 bool link_up = adapter->link_up;
3190
3191 adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
3192
3193 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
3194 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3195 if (link_up ||
3196 time_after(jiffies, (adapter->link_check_timeout +
3197 IXGBE_TRY_LINK_TIMEOUT))) {
3198 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
3199 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
3200 }
3201 adapter->link_up = link_up;
3202 adapter->link_speed = link_speed;
3203 }
3204
3205 if (link_up) {
3206 if (!netif_carrier_ok(netdev)) {
3207 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3208 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
3209 #define FLOW_RX (frctl & IXGBE_FCTRL_RFCE)
3210 #define FLOW_TX (rmcs & IXGBE_RMCS_TFCE_802_3X)
3211 DPRINTK(LINK, INFO, "NIC Link is Up %s, "
3212 "Flow Control: %s\n",
3213 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
3214 "10 Gbps" :
3215 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
3216 "1 Gbps" : "unknown speed")),
3217 ((FLOW_RX && FLOW_TX) ? "RX/TX" :
3218 (FLOW_RX ? "RX" :
3219 (FLOW_TX ? "TX" : "None"))));
3220
3221 netif_carrier_on(netdev);
3222 netif_tx_wake_all_queues(netdev);
3223 } else {
3224 /* Force detection of hung controller */
3225 adapter->detect_tx_hung = true;
3226 }
3227 } else {
3228 adapter->link_up = false;
3229 adapter->link_speed = 0;
3230 if (netif_carrier_ok(netdev)) {
3231 DPRINTK(LINK, INFO, "NIC Link is Down\n");
3232 netif_carrier_off(netdev);
3233 netif_tx_stop_all_queues(netdev);
3234 }
3235 }
3236
3237 ixgbe_update_stats(adapter);
3238 adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
3239 }
3240
3241 static int ixgbe_tso(struct ixgbe_adapter *adapter,
3242 struct ixgbe_ring *tx_ring, struct sk_buff *skb,
3243 u32 tx_flags, u8 *hdr_len)
3244 {
3245 struct ixgbe_adv_tx_context_desc *context_desc;
3246 unsigned int i;
3247 int err;
3248 struct ixgbe_tx_buffer *tx_buffer_info;
3249 u32 vlan_macip_lens = 0, type_tucmd_mlhl;
3250 u32 mss_l4len_idx, l4len;
3251
3252 if (skb_is_gso(skb)) {
3253 if (skb_header_cloned(skb)) {
3254 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
3255 if (err)
3256 return err;
3257 }
3258 l4len = tcp_hdrlen(skb);
3259 *hdr_len += l4len;
3260
3261 if (skb->protocol == htons(ETH_P_IP)) {
3262 struct iphdr *iph = ip_hdr(skb);
3263 iph->tot_len = 0;
3264 iph->check = 0;
3265 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
3266 iph->daddr, 0,
3267 IPPROTO_TCP,
3268 0);
3269 adapter->hw_tso_ctxt++;
3270 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
3271 ipv6_hdr(skb)->payload_len = 0;
3272 tcp_hdr(skb)->check =
3273 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3274 &ipv6_hdr(skb)->daddr,
3275 0, IPPROTO_TCP, 0);
3276 adapter->hw_tso6_ctxt++;
3277 }
3278
3279 i = tx_ring->next_to_use;
3280
3281 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3282 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3283
3284 /* VLAN MACLEN IPLEN */
3285 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3286 vlan_macip_lens |=
3287 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3288 vlan_macip_lens |= ((skb_network_offset(skb)) <<
3289 IXGBE_ADVTXD_MACLEN_SHIFT);
3290 *hdr_len += skb_network_offset(skb);
3291 vlan_macip_lens |=
3292 (skb_transport_header(skb) - skb_network_header(skb));
3293 *hdr_len +=
3294 (skb_transport_header(skb) - skb_network_header(skb));
3295 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3296 context_desc->seqnum_seed = 0;
3297
3298 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
3299 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
3300 IXGBE_ADVTXD_DTYP_CTXT);
3301
3302 if (skb->protocol == htons(ETH_P_IP))
3303 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3304 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
3305 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3306
3307 /* MSS L4LEN IDX */
3308 mss_l4len_idx =
3309 (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
3310 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
3311 /* use index 1 for TSO */
3312 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3313 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
3314
3315 tx_buffer_info->time_stamp = jiffies;
3316 tx_buffer_info->next_to_watch = i;
3317
3318 i++;
3319 if (i == tx_ring->count)
3320 i = 0;
3321 tx_ring->next_to_use = i;
3322
3323 return true;
3324 }
3325 return false;
3326 }
3327
3328 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
3329 struct ixgbe_ring *tx_ring,
3330 struct sk_buff *skb, u32 tx_flags)
3331 {
3332 struct ixgbe_adv_tx_context_desc *context_desc;
3333 unsigned int i;
3334 struct ixgbe_tx_buffer *tx_buffer_info;
3335 u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
3336
3337 if (skb->ip_summed == CHECKSUM_PARTIAL ||
3338 (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
3339 i = tx_ring->next_to_use;
3340 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3341 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
3342
3343 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3344 vlan_macip_lens |=
3345 (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
3346 vlan_macip_lens |= (skb_network_offset(skb) <<
3347 IXGBE_ADVTXD_MACLEN_SHIFT);
3348 if (skb->ip_summed == CHECKSUM_PARTIAL)
3349 vlan_macip_lens |= (skb_transport_header(skb) -
3350 skb_network_header(skb));
3351
3352 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
3353 context_desc->seqnum_seed = 0;
3354
3355 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
3356 IXGBE_ADVTXD_DTYP_CTXT);
3357
3358 if (skb->ip_summed == CHECKSUM_PARTIAL) {
3359 switch (skb->protocol) {
3360 case __constant_htons(ETH_P_IP):
3361 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
3362 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3363 type_tucmd_mlhl |=
3364 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3365 break;
3366 case __constant_htons(ETH_P_IPV6):
3367 /* XXX what about other V6 headers?? */
3368 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3369 type_tucmd_mlhl |=
3370 IXGBE_ADVTXD_TUCMD_L4T_TCP;
3371 break;
3372 default:
3373 if (unlikely(net_ratelimit())) {
3374 DPRINTK(PROBE, WARNING,
3375 "partial checksum but proto=%x!\n",
3376 skb->protocol);
3377 }
3378 break;
3379 }
3380 }
3381
3382 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
3383 /* use index zero for tx checksum offload */
3384 context_desc->mss_l4len_idx = 0;
3385
3386 tx_buffer_info->time_stamp = jiffies;
3387 tx_buffer_info->next_to_watch = i;
3388
3389 adapter->hw_csum_tx_good++;
3390 i++;
3391 if (i == tx_ring->count)
3392 i = 0;
3393 tx_ring->next_to_use = i;
3394
3395 return true;
3396 }
3397
3398 return false;
3399 }
3400
3401 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
3402 struct ixgbe_ring *tx_ring,
3403 struct sk_buff *skb, unsigned int first)
3404 {
3405 struct ixgbe_tx_buffer *tx_buffer_info;
3406 unsigned int len = skb->len;
3407 unsigned int offset = 0, size, count = 0, i;
3408 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
3409 unsigned int f;
3410
3411 len -= skb->data_len;
3412
3413 i = tx_ring->next_to_use;
3414
3415 while (len) {
3416 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3417 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3418
3419 tx_buffer_info->length = size;
3420 tx_buffer_info->dma = pci_map_single(adapter->pdev,
3421 skb->data + offset,
3422 size, PCI_DMA_TODEVICE);
3423 tx_buffer_info->time_stamp = jiffies;
3424 tx_buffer_info->next_to_watch = i;
3425
3426 len -= size;
3427 offset += size;
3428 count++;
3429 i++;
3430 if (i == tx_ring->count)
3431 i = 0;
3432 }
3433
3434 for (f = 0; f < nr_frags; f++) {
3435 struct skb_frag_struct *frag;
3436
3437 frag = &skb_shinfo(skb)->frags[f];
3438 len = frag->size;
3439 offset = frag->page_offset;
3440
3441 while (len) {
3442 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3443 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
3444
3445 tx_buffer_info->length = size;
3446 tx_buffer_info->dma = pci_map_page(adapter->pdev,
3447 frag->page,
3448 offset,
3449 size,
3450 PCI_DMA_TODEVICE);
3451 tx_buffer_info->time_stamp = jiffies;
3452 tx_buffer_info->next_to_watch = i;
3453
3454 len -= size;
3455 offset += size;
3456 count++;
3457 i++;
3458 if (i == tx_ring->count)
3459 i = 0;
3460 }
3461 }
3462 if (i == 0)
3463 i = tx_ring->count - 1;
3464 else
3465 i = i - 1;
3466 tx_ring->tx_buffer_info[i].skb = skb;
3467 tx_ring->tx_buffer_info[first].next_to_watch = i;
3468
3469 return count;
3470 }
3471
3472 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
3473 struct ixgbe_ring *tx_ring,
3474 int tx_flags, int count, u32 paylen, u8 hdr_len)
3475 {
3476 union ixgbe_adv_tx_desc *tx_desc = NULL;
3477 struct ixgbe_tx_buffer *tx_buffer_info;
3478 u32 olinfo_status = 0, cmd_type_len = 0;
3479 unsigned int i;
3480 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
3481
3482 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
3483
3484 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
3485
3486 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
3487 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
3488
3489 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
3490 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
3491
3492 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3493 IXGBE_ADVTXD_POPTS_SHIFT;
3494
3495 /* use index 1 context for tso */
3496 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
3497 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
3498 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
3499 IXGBE_ADVTXD_POPTS_SHIFT;
3500
3501 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
3502 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
3503 IXGBE_ADVTXD_POPTS_SHIFT;
3504
3505 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
3506
3507 i = tx_ring->next_to_use;
3508 while (count--) {
3509 tx_buffer_info = &tx_ring->tx_buffer_info[i];
3510 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
3511 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
3512 tx_desc->read.cmd_type_len =
3513 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
3514 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
3515 i++;
3516 if (i == tx_ring->count)
3517 i = 0;
3518 }
3519
3520 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
3521
3522 /*
3523 * Force memory writes to complete before letting h/w
3524 * know there are new descriptors to fetch. (Only
3525 * applicable for weak-ordered memory model archs,
3526 * such as IA-64).
3527 */
3528 wmb();
3529
3530 tx_ring->next_to_use = i;
3531 writel(i, adapter->hw.hw_addr + tx_ring->tail);
3532 }
3533
3534 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
3535 struct ixgbe_ring *tx_ring, int size)
3536 {
3537 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3538
3539 netif_stop_subqueue(netdev, tx_ring->queue_index);
3540 /* Herbert's original patch had:
3541 * smp_mb__after_netif_stop_queue();
3542 * but since that doesn't exist yet, just open code it. */
3543 smp_mb();
3544
3545 /* We need to check again in a case another CPU has just
3546 * made room available. */
3547 if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
3548 return -EBUSY;
3549
3550 /* A reprieve! - use start_queue because it doesn't call schedule */
3551 netif_start_subqueue(netdev, tx_ring->queue_index);
3552 ++adapter->restart_queue;
3553 return 0;
3554 }
3555
3556 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
3557 struct ixgbe_ring *tx_ring, int size)
3558 {
3559 if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
3560 return 0;
3561 return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
3562 }
3563
3564 static int ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3565 {
3566 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3567 struct ixgbe_ring *tx_ring;
3568 unsigned int first;
3569 unsigned int tx_flags = 0;
3570 u8 hdr_len = 0;
3571 int r_idx = 0, tso;
3572 int count = 0;
3573 unsigned int f;
3574
3575 r_idx = (adapter->num_tx_queues - 1) & skb->queue_mapping;
3576 tx_ring = &adapter->tx_ring[r_idx];
3577
3578 if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
3579 tx_flags |= vlan_tx_tag_get(skb);
3580 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
3581 tx_flags |= IXGBE_TX_FLAGS_VLAN;
3582 }
3583 /* three things can cause us to need a context descriptor */
3584 if (skb_is_gso(skb) ||
3585 (skb->ip_summed == CHECKSUM_PARTIAL) ||
3586 (tx_flags & IXGBE_TX_FLAGS_VLAN))
3587 count++;
3588
3589 count += TXD_USE_COUNT(skb_headlen(skb));
3590 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
3591 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
3592
3593 if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
3594 adapter->tx_busy++;
3595 return NETDEV_TX_BUSY;
3596 }
3597
3598 if (skb->protocol == htons(ETH_P_IP))
3599 tx_flags |= IXGBE_TX_FLAGS_IPV4;
3600 first = tx_ring->next_to_use;
3601 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
3602 if (tso < 0) {
3603 dev_kfree_skb_any(skb);
3604 return NETDEV_TX_OK;
3605 }
3606
3607 if (tso)
3608 tx_flags |= IXGBE_TX_FLAGS_TSO;
3609 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
3610 (skb->ip_summed == CHECKSUM_PARTIAL))
3611 tx_flags |= IXGBE_TX_FLAGS_CSUM;
3612
3613 ixgbe_tx_queue(adapter, tx_ring, tx_flags,
3614 ixgbe_tx_map(adapter, tx_ring, skb, first),
3615 skb->len, hdr_len);
3616
3617 netdev->trans_start = jiffies;
3618
3619 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
3620
3621 return NETDEV_TX_OK;
3622 }
3623
3624 /**
3625 * ixgbe_get_stats - Get System Network Statistics
3626 * @netdev: network interface device structure
3627 *
3628 * Returns the address of the device statistics structure.
3629 * The statistics are actually updated from the timer callback.
3630 **/
3631 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
3632 {
3633 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3634
3635 /* only return the current stats */
3636 return &adapter->net_stats;
3637 }
3638
3639 /**
3640 * ixgbe_set_mac - Change the Ethernet Address of the NIC
3641 * @netdev: network interface device structure
3642 * @p: pointer to an address structure
3643 *
3644 * Returns 0 on success, negative on failure
3645 **/
3646 static int ixgbe_set_mac(struct net_device *netdev, void *p)
3647 {
3648 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3649 struct ixgbe_hw *hw = &adapter->hw;
3650 struct sockaddr *addr = p;
3651
3652 if (!is_valid_ether_addr(addr->sa_data))
3653 return -EADDRNOTAVAIL;
3654
3655 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3656 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3657
3658 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
3659
3660 return 0;
3661 }
3662
3663 #ifdef CONFIG_NET_POLL_CONTROLLER
3664 /*
3665 * Polling 'interrupt' - used by things like netconsole to send skbs
3666 * without having to re-enable interrupts. It's not called while
3667 * the interrupt routine is executing.
3668 */
3669 static void ixgbe_netpoll(struct net_device *netdev)
3670 {
3671 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3672
3673 disable_irq(adapter->pdev->irq);
3674 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
3675 ixgbe_intr(adapter->pdev->irq, netdev);
3676 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
3677 enable_irq(adapter->pdev->irq);
3678 }
3679 #endif
3680
3681 /**
3682 * ixgbe_link_config - set up initial link with default speed and duplex
3683 * @hw: pointer to private hardware struct
3684 *
3685 * Returns 0 on success, negative on failure
3686 **/
3687 static int ixgbe_link_config(struct ixgbe_hw *hw)
3688 {
3689 u32 autoneg = IXGBE_LINK_SPEED_10GB_FULL;
3690
3691 /* must always autoneg for both 1G and 10G link */
3692 hw->mac.autoneg = true;
3693
3694 return hw->mac.ops.setup_link_speed(hw, autoneg, true, true);
3695 }
3696
3697 /**
3698 * ixgbe_probe - Device Initialization Routine
3699 * @pdev: PCI device information struct
3700 * @ent: entry in ixgbe_pci_tbl
3701 *
3702 * Returns 0 on success, negative on failure
3703 *
3704 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
3705 * The OS initialization, configuring of the adapter private structure,
3706 * and a hardware reset occur.
3707 **/
3708 static int __devinit ixgbe_probe(struct pci_dev *pdev,
3709 const struct pci_device_id *ent)
3710 {
3711 struct net_device *netdev;
3712 struct ixgbe_adapter *adapter = NULL;
3713 struct ixgbe_hw *hw;
3714 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
3715 static int cards_found;
3716 int i, err, pci_using_dac;
3717 u16 link_status, link_speed, link_width;
3718 u32 part_num, eec;
3719
3720 err = pci_enable_device(pdev);
3721 if (err)
3722 return err;
3723
3724 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
3725 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK)) {
3726 pci_using_dac = 1;
3727 } else {
3728 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3729 if (err) {
3730 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3731 if (err) {
3732 dev_err(&pdev->dev, "No usable DMA "
3733 "configuration, aborting\n");
3734 goto err_dma;
3735 }
3736 }
3737 pci_using_dac = 0;
3738 }
3739
3740 err = pci_request_regions(pdev, ixgbe_driver_name);
3741 if (err) {
3742 dev_err(&pdev->dev, "pci_request_regions failed 0x%x\n", err);
3743 goto err_pci_reg;
3744 }
3745
3746 pci_set_master(pdev);
3747 pci_save_state(pdev);
3748
3749 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
3750 if (!netdev) {
3751 err = -ENOMEM;
3752 goto err_alloc_etherdev;
3753 }
3754
3755 SET_NETDEV_DEV(netdev, &pdev->dev);
3756
3757 pci_set_drvdata(pdev, netdev);
3758 adapter = netdev_priv(netdev);
3759
3760 adapter->netdev = netdev;
3761 adapter->pdev = pdev;
3762 hw = &adapter->hw;
3763 hw->back = adapter;
3764 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
3765
3766 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
3767 pci_resource_len(pdev, 0));
3768 if (!hw->hw_addr) {
3769 err = -EIO;
3770 goto err_ioremap;
3771 }
3772
3773 for (i = 1; i <= 5; i++) {
3774 if (pci_resource_len(pdev, i) == 0)
3775 continue;
3776 }
3777
3778 netdev->open = &ixgbe_open;
3779 netdev->stop = &ixgbe_close;
3780 netdev->hard_start_xmit = &ixgbe_xmit_frame;
3781 netdev->get_stats = &ixgbe_get_stats;
3782 netdev->set_rx_mode = &ixgbe_set_rx_mode;
3783 netdev->set_multicast_list = &ixgbe_set_rx_mode;
3784 netdev->set_mac_address = &ixgbe_set_mac;
3785 netdev->change_mtu = &ixgbe_change_mtu;
3786 ixgbe_set_ethtool_ops(netdev);
3787 netdev->tx_timeout = &ixgbe_tx_timeout;
3788 netdev->watchdog_timeo = 5 * HZ;
3789 netdev->vlan_rx_register = ixgbe_vlan_rx_register;
3790 netdev->vlan_rx_add_vid = ixgbe_vlan_rx_add_vid;
3791 netdev->vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid;
3792 #ifdef CONFIG_NET_POLL_CONTROLLER
3793 netdev->poll_controller = ixgbe_netpoll;
3794 #endif
3795 strcpy(netdev->name, pci_name(pdev));
3796
3797 adapter->bd_number = cards_found;
3798
3799 /* Setup hw api */
3800 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
3801 hw->mac.type = ii->mac;
3802
3803 /* EEPROM */
3804 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
3805 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
3806 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
3807 if (!(eec & (1 << 8)))
3808 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
3809
3810 /* PHY */
3811 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
3812 /* phy->sfp_type = ixgbe_sfp_type_unknown; */
3813
3814 err = ii->get_invariants(hw);
3815 if (err)
3816 goto err_hw_init;
3817
3818 /* setup the private structure */
3819 err = ixgbe_sw_init(adapter);
3820 if (err)
3821 goto err_sw_init;
3822
3823 /* reset_hw fills in the perm_addr as well */
3824 err = hw->mac.ops.reset_hw(hw);
3825 if (err) {
3826 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
3827 goto err_sw_init;
3828 }
3829
3830 netdev->features = NETIF_F_SG |
3831 NETIF_F_IP_CSUM |
3832 NETIF_F_HW_VLAN_TX |
3833 NETIF_F_HW_VLAN_RX |
3834 NETIF_F_HW_VLAN_FILTER;
3835
3836 netdev->features |= NETIF_F_IPV6_CSUM;
3837 netdev->features |= NETIF_F_TSO;
3838 netdev->features |= NETIF_F_TSO6;
3839 netdev->features |= NETIF_F_LRO;
3840
3841 netdev->vlan_features |= NETIF_F_TSO;
3842 netdev->vlan_features |= NETIF_F_TSO6;
3843 netdev->vlan_features |= NETIF_F_IP_CSUM;
3844 netdev->vlan_features |= NETIF_F_SG;
3845
3846 if (pci_using_dac)
3847 netdev->features |= NETIF_F_HIGHDMA;
3848
3849 /* make sure the EEPROM is good */
3850 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
3851 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
3852 err = -EIO;
3853 goto err_eeprom;
3854 }
3855
3856 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
3857 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
3858
3859 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
3860 dev_err(&pdev->dev, "invalid MAC address\n");
3861 err = -EIO;
3862 goto err_eeprom;
3863 }
3864
3865 init_timer(&adapter->watchdog_timer);
3866 adapter->watchdog_timer.function = &ixgbe_watchdog;
3867 adapter->watchdog_timer.data = (unsigned long)adapter;
3868
3869 INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
3870 INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
3871
3872 err = ixgbe_init_interrupt_scheme(adapter);
3873 if (err)
3874 goto err_sw_init;
3875
3876 /* print bus type/speed/width info */
3877 pci_read_config_word(pdev, IXGBE_PCI_LINK_STATUS, &link_status);
3878 link_speed = link_status & IXGBE_PCI_LINK_SPEED;
3879 link_width = link_status & IXGBE_PCI_LINK_WIDTH;
3880 dev_info(&pdev->dev, "(PCI Express:%s:%s) "
3881 "%02x:%02x:%02x:%02x:%02x:%02x\n",
3882 ((link_speed == IXGBE_PCI_LINK_SPEED_5000) ? "5.0Gb/s" :
3883 (link_speed == IXGBE_PCI_LINK_SPEED_2500) ? "2.5Gb/s" :
3884 "Unknown"),
3885 ((link_width == IXGBE_PCI_LINK_WIDTH_8) ? "Width x8" :
3886 (link_width == IXGBE_PCI_LINK_WIDTH_4) ? "Width x4" :
3887 (link_width == IXGBE_PCI_LINK_WIDTH_2) ? "Width x2" :
3888 (link_width == IXGBE_PCI_LINK_WIDTH_1) ? "Width x1" :
3889 "Unknown"),
3890 netdev->dev_addr[0], netdev->dev_addr[1], netdev->dev_addr[2],
3891 netdev->dev_addr[3], netdev->dev_addr[4], netdev->dev_addr[5]);
3892 ixgbe_read_pba_num_generic(hw, &part_num);
3893 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
3894 hw->mac.type, hw->phy.type,
3895 (part_num >> 8), (part_num & 0xff));
3896
3897 if (link_width <= IXGBE_PCI_LINK_WIDTH_4) {
3898 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
3899 "this card is not sufficient for optimal "
3900 "performance.\n");
3901 dev_warn(&pdev->dev, "For optimal performance a x8 "
3902 "PCI-Express slot is required.\n");
3903 }
3904
3905 /* reset the hardware with the new settings */
3906 hw->mac.ops.start_hw(hw);
3907
3908 /* link_config depends on start_hw being called at least once */
3909 err = ixgbe_link_config(hw);
3910 if (err) {
3911 dev_err(&pdev->dev, "setup_link_speed FAILED %d\n", err);
3912 goto err_register;
3913 }
3914
3915 netif_carrier_off(netdev);
3916 netif_tx_stop_all_queues(netdev);
3917
3918 ixgbe_napi_add_all(adapter);
3919
3920 strcpy(netdev->name, "eth%d");
3921 err = register_netdev(netdev);
3922 if (err)
3923 goto err_register;
3924
3925 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3926 if (dca_add_requester(&pdev->dev) == 0) {
3927 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
3928 /* always use CB2 mode, difference is masked
3929 * in the CB driver */
3930 IXGBE_WRITE_REG(hw, IXGBE_DCA_CTRL, 2);
3931 ixgbe_setup_dca(adapter);
3932 }
3933 #endif
3934
3935 dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
3936 cards_found++;
3937 return 0;
3938
3939 err_register:
3940 ixgbe_release_hw_control(adapter);
3941 err_hw_init:
3942 err_sw_init:
3943 ixgbe_reset_interrupt_capability(adapter);
3944 err_eeprom:
3945 iounmap(hw->hw_addr);
3946 err_ioremap:
3947 free_netdev(netdev);
3948 err_alloc_etherdev:
3949 pci_release_regions(pdev);
3950 err_pci_reg:
3951 err_dma:
3952 pci_disable_device(pdev);
3953 return err;
3954 }
3955
3956 /**
3957 * ixgbe_remove - Device Removal Routine
3958 * @pdev: PCI device information struct
3959 *
3960 * ixgbe_remove is called by the PCI subsystem to alert the driver
3961 * that it should release a PCI device. The could be caused by a
3962 * Hot-Plug event, or because the driver is going to be removed from
3963 * memory.
3964 **/
3965 static void __devexit ixgbe_remove(struct pci_dev *pdev)
3966 {
3967 struct net_device *netdev = pci_get_drvdata(pdev);
3968 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3969
3970 set_bit(__IXGBE_DOWN, &adapter->state);
3971 del_timer_sync(&adapter->watchdog_timer);
3972
3973 flush_scheduled_work();
3974
3975 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
3976 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
3977 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
3978 dca_remove_requester(&pdev->dev);
3979 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
3980 }
3981
3982 #endif
3983 unregister_netdev(netdev);
3984
3985 ixgbe_reset_interrupt_capability(adapter);
3986
3987 ixgbe_release_hw_control(adapter);
3988
3989 iounmap(adapter->hw.hw_addr);
3990 pci_release_regions(pdev);
3991
3992 DPRINTK(PROBE, INFO, "complete\n");
3993 ixgbe_napi_del_all(adapter);
3994 kfree(adapter->tx_ring);
3995 kfree(adapter->rx_ring);
3996
3997 free_netdev(netdev);
3998
3999 pci_disable_device(pdev);
4000 }
4001
4002 /**
4003 * ixgbe_io_error_detected - called when PCI error is detected
4004 * @pdev: Pointer to PCI device
4005 * @state: The current pci connection state
4006 *
4007 * This function is called after a PCI bus error affecting
4008 * this device has been detected.
4009 */
4010 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
4011 pci_channel_state_t state)
4012 {
4013 struct net_device *netdev = pci_get_drvdata(pdev);
4014 struct ixgbe_adapter *adapter = netdev->priv;
4015
4016 netif_device_detach(netdev);
4017
4018 if (netif_running(netdev))
4019 ixgbe_down(adapter);
4020 pci_disable_device(pdev);
4021
4022 /* Request a slot reset. */
4023 return PCI_ERS_RESULT_NEED_RESET;
4024 }
4025
4026 /**
4027 * ixgbe_io_slot_reset - called after the pci bus has been reset.
4028 * @pdev: Pointer to PCI device
4029 *
4030 * Restart the card from scratch, as if from a cold-boot.
4031 */
4032 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
4033 {
4034 struct net_device *netdev = pci_get_drvdata(pdev);
4035 struct ixgbe_adapter *adapter = netdev->priv;
4036
4037 if (pci_enable_device(pdev)) {
4038 DPRINTK(PROBE, ERR,
4039 "Cannot re-enable PCI device after reset.\n");
4040 return PCI_ERS_RESULT_DISCONNECT;
4041 }
4042 pci_set_master(pdev);
4043 pci_restore_state(pdev);
4044
4045 pci_enable_wake(pdev, PCI_D3hot, 0);
4046 pci_enable_wake(pdev, PCI_D3cold, 0);
4047
4048 ixgbe_reset(adapter);
4049
4050 return PCI_ERS_RESULT_RECOVERED;
4051 }
4052
4053 /**
4054 * ixgbe_io_resume - called when traffic can start flowing again.
4055 * @pdev: Pointer to PCI device
4056 *
4057 * This callback is called when the error recovery driver tells us that
4058 * its OK to resume normal operation.
4059 */
4060 static void ixgbe_io_resume(struct pci_dev *pdev)
4061 {
4062 struct net_device *netdev = pci_get_drvdata(pdev);
4063 struct ixgbe_adapter *adapter = netdev->priv;
4064
4065 if (netif_running(netdev)) {
4066 if (ixgbe_up(adapter)) {
4067 DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
4068 return;
4069 }
4070 }
4071
4072 netif_device_attach(netdev);
4073 }
4074
4075 static struct pci_error_handlers ixgbe_err_handler = {
4076 .error_detected = ixgbe_io_error_detected,
4077 .slot_reset = ixgbe_io_slot_reset,
4078 .resume = ixgbe_io_resume,
4079 };
4080
4081 static struct pci_driver ixgbe_driver = {
4082 .name = ixgbe_driver_name,
4083 .id_table = ixgbe_pci_tbl,
4084 .probe = ixgbe_probe,
4085 .remove = __devexit_p(ixgbe_remove),
4086 #ifdef CONFIG_PM
4087 .suspend = ixgbe_suspend,
4088 .resume = ixgbe_resume,
4089 #endif
4090 .shutdown = ixgbe_shutdown,
4091 .err_handler = &ixgbe_err_handler
4092 };
4093
4094 /**
4095 * ixgbe_init_module - Driver Registration Routine
4096 *
4097 * ixgbe_init_module is the first routine called when the driver is
4098 * loaded. All it does is register with the PCI subsystem.
4099 **/
4100 static int __init ixgbe_init_module(void)
4101 {
4102 int ret;
4103 printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
4104 ixgbe_driver_string, ixgbe_driver_version);
4105
4106 printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
4107
4108 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4109 dca_register_notify(&dca_notifier);
4110
4111 #endif
4112 ret = pci_register_driver(&ixgbe_driver);
4113 return ret;
4114 }
4115
4116 module_init(ixgbe_init_module);
4117
4118 /**
4119 * ixgbe_exit_module - Driver Exit Cleanup Routine
4120 *
4121 * ixgbe_exit_module is called just before the driver is removed
4122 * from memory.
4123 **/
4124 static void __exit ixgbe_exit_module(void)
4125 {
4126 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4127 dca_unregister_notify(&dca_notifier);
4128 #endif
4129 pci_unregister_driver(&ixgbe_driver);
4130 }
4131
4132 #if defined(CONFIG_DCA) || defined(CONFIG_DCA_MODULE)
4133 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
4134 void *p)
4135 {
4136 int ret_val;
4137
4138 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
4139 __ixgbe_notify_dca);
4140
4141 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
4142 }
4143 #endif /* CONFIG_DCA or CONFIG_DCA_MODULE */
4144
4145 module_exit(ixgbe_exit_module);
4146
4147 /* ixgbe_main.c */
Linux kernel - Deliverables
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