1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
36 #include <linux/tcp.h>
37 #include <linux/pkt_sched.h>
38 #include <linux/ipv6.h>
39 #include <linux/slab.h>
40 #include <net/checksum.h>
41 #include <net/ip6_checksum.h>
42 #include <linux/ethtool.h>
43 #include <linux/if_vlan.h>
44 #include <scsi/fc/fc_fcoe.h>
47 #include "ixgbe_common.h"
48 #include "ixgbe_dcb_82599.h"
49 #include "ixgbe_sriov.h"
51 char ixgbe_driver_name
[] = "ixgbe";
52 static const char ixgbe_driver_string
[] =
53 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #define DRV_VERSION "2.0.62-k2"
56 const char ixgbe_driver_version
[] = DRV_VERSION
;
57 static char ixgbe_copyright
[] = "Copyright (c) 1999-2010 Intel Corporation.";
59 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
60 [board_82598
] = &ixgbe_82598_info
,
61 [board_82599
] = &ixgbe_82599_info
,
64 /* ixgbe_pci_tbl - PCI Device ID Table
66 * Wildcard entries (PCI_ANY_ID) should come last
67 * Last entry must be all 0s
69 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
70 * Class, Class Mask, private data (not used) }
72 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
73 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
75 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
77 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
79 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
116 /* required last entry */
119 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
121 #ifdef CONFIG_IXGBE_DCA
122 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
124 static struct notifier_block dca_notifier
= {
125 .notifier_call
= ixgbe_notify_dca
,
131 #ifdef CONFIG_PCI_IOV
132 static unsigned int max_vfs
;
133 module_param(max_vfs
, uint
, 0);
134 MODULE_PARM_DESC(max_vfs
, "Maximum number of virtual functions to allocate "
135 "per physical function");
136 #endif /* CONFIG_PCI_IOV */
138 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
139 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_VERSION
);
143 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
145 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
147 struct ixgbe_hw
*hw
= &adapter
->hw
;
152 #ifdef CONFIG_PCI_IOV
153 /* disable iov and allow time for transactions to clear */
154 pci_disable_sriov(adapter
->pdev
);
157 /* turn off device IOV mode */
158 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
159 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
160 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
161 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
162 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
163 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
165 /* set default pool back to 0 */
166 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
167 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
168 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
170 /* take a breather then clean up driver data */
173 kfree(adapter
->vfinfo
);
174 adapter
->vfinfo
= NULL
;
176 adapter
->num_vfs
= 0;
177 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
180 struct ixgbe_reg_info
{
185 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
187 /* General Registers */
188 {IXGBE_CTRL
, "CTRL"},
189 {IXGBE_STATUS
, "STATUS"},
190 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
192 /* Interrupt Registers */
193 {IXGBE_EICR
, "EICR"},
196 {IXGBE_SRRCTL(0), "SRRCTL"},
197 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
198 {IXGBE_RDLEN(0), "RDLEN"},
199 {IXGBE_RDH(0), "RDH"},
200 {IXGBE_RDT(0), "RDT"},
201 {IXGBE_RXDCTL(0), "RXDCTL"},
202 {IXGBE_RDBAL(0), "RDBAL"},
203 {IXGBE_RDBAH(0), "RDBAH"},
206 {IXGBE_TDBAL(0), "TDBAL"},
207 {IXGBE_TDBAH(0), "TDBAH"},
208 {IXGBE_TDLEN(0), "TDLEN"},
209 {IXGBE_TDH(0), "TDH"},
210 {IXGBE_TDT(0), "TDT"},
211 {IXGBE_TXDCTL(0), "TXDCTL"},
213 /* List Terminator */
219 * ixgbe_regdump - register printout routine
221 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
227 switch (reginfo
->ofs
) {
228 case IXGBE_SRRCTL(0):
229 for (i
= 0; i
< 64; i
++)
230 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
232 case IXGBE_DCA_RXCTRL(0):
233 for (i
= 0; i
< 64; i
++)
234 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
237 for (i
= 0; i
< 64; i
++)
238 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
241 for (i
= 0; i
< 64; i
++)
242 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
245 for (i
= 0; i
< 64; i
++)
246 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
248 case IXGBE_RXDCTL(0):
249 for (i
= 0; i
< 64; i
++)
250 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
253 for (i
= 0; i
< 64; i
++)
254 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
257 for (i
= 0; i
< 64; i
++)
258 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
261 for (i
= 0; i
< 64; i
++)
262 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
265 for (i
= 0; i
< 64; i
++)
266 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
269 for (i
= 0; i
< 64; i
++)
270 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
273 for (i
= 0; i
< 64; i
++)
274 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
277 for (i
= 0; i
< 64; i
++)
278 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
280 case IXGBE_TXDCTL(0):
281 for (i
= 0; i
< 64; i
++)
282 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
285 printk(KERN_INFO
"%-15s %08x\n", reginfo
->name
,
286 IXGBE_READ_REG(hw
, reginfo
->ofs
));
290 for (i
= 0; i
< 8; i
++) {
291 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
292 printk(KERN_ERR
"%-15s ", rname
);
293 for (j
= 0; j
< 8; j
++)
294 printk(KERN_CONT
"%08x ", regs
[i
*8+j
]);
295 printk(KERN_CONT
"\n");
301 * ixgbe_dump - Print registers, tx-rings and rx-rings
303 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
305 struct net_device
*netdev
= adapter
->netdev
;
306 struct ixgbe_hw
*hw
= &adapter
->hw
;
307 struct ixgbe_reg_info
*reginfo
;
309 struct ixgbe_ring
*tx_ring
;
310 struct ixgbe_tx_buffer
*tx_buffer_info
;
311 union ixgbe_adv_tx_desc
*tx_desc
;
312 struct my_u0
{ u64 a
; u64 b
; } *u0
;
313 struct ixgbe_ring
*rx_ring
;
314 union ixgbe_adv_rx_desc
*rx_desc
;
315 struct ixgbe_rx_buffer
*rx_buffer_info
;
319 if (!netif_msg_hw(adapter
))
322 /* Print netdevice Info */
324 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
325 printk(KERN_INFO
"Device Name state "
326 "trans_start last_rx\n");
327 printk(KERN_INFO
"%-15s %016lX %016lX %016lX\n",
334 /* Print Registers */
335 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
336 printk(KERN_INFO
" Register Name Value\n");
337 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
338 reginfo
->name
; reginfo
++) {
339 ixgbe_regdump(hw
, reginfo
);
342 /* Print TX Ring Summary */
343 if (!netdev
|| !netif_running(netdev
))
346 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
347 printk(KERN_INFO
"Queue [NTU] [NTC] [bi(ntc)->dma ] "
348 "leng ntw timestamp\n");
349 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
350 tx_ring
= adapter
->tx_ring
[n
];
352 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
353 printk(KERN_INFO
" %5d %5X %5X %016llX %04X %3X %016llX\n",
354 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
355 (u64
)tx_buffer_info
->dma
,
356 tx_buffer_info
->length
,
357 tx_buffer_info
->next_to_watch
,
358 (u64
)tx_buffer_info
->time_stamp
);
362 if (!netif_msg_tx_done(adapter
))
363 goto rx_ring_summary
;
365 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
367 /* Transmit Descriptor Formats
369 * Advanced Transmit Descriptor
370 * +--------------------------------------------------------------+
371 * 0 | Buffer Address [63:0] |
372 * +--------------------------------------------------------------+
373 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
374 * +--------------------------------------------------------------+
375 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
378 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
379 tx_ring
= adapter
->tx_ring
[n
];
380 printk(KERN_INFO
"------------------------------------\n");
381 printk(KERN_INFO
"TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
382 printk(KERN_INFO
"------------------------------------\n");
383 printk(KERN_INFO
"T [desc] [address 63:0 ] "
384 "[PlPOIdStDDt Ln] [bi->dma ] "
385 "leng ntw timestamp bi->skb\n");
387 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
388 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
389 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
390 u0
= (struct my_u0
*)tx_desc
;
391 printk(KERN_INFO
"T [0x%03X] %016llX %016llX %016llX"
392 " %04X %3X %016llX %p", i
,
395 (u64
)tx_buffer_info
->dma
,
396 tx_buffer_info
->length
,
397 tx_buffer_info
->next_to_watch
,
398 (u64
)tx_buffer_info
->time_stamp
,
399 tx_buffer_info
->skb
);
400 if (i
== tx_ring
->next_to_use
&&
401 i
== tx_ring
->next_to_clean
)
402 printk(KERN_CONT
" NTC/U\n");
403 else if (i
== tx_ring
->next_to_use
)
404 printk(KERN_CONT
" NTU\n");
405 else if (i
== tx_ring
->next_to_clean
)
406 printk(KERN_CONT
" NTC\n");
408 printk(KERN_CONT
"\n");
410 if (netif_msg_pktdata(adapter
) &&
411 tx_buffer_info
->dma
!= 0)
412 print_hex_dump(KERN_INFO
, "",
413 DUMP_PREFIX_ADDRESS
, 16, 1,
414 phys_to_virt(tx_buffer_info
->dma
),
415 tx_buffer_info
->length
, true);
419 /* Print RX Rings Summary */
421 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
422 printk(KERN_INFO
"Queue [NTU] [NTC]\n");
423 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
424 rx_ring
= adapter
->rx_ring
[n
];
425 printk(KERN_INFO
"%5d %5X %5X\n", n
,
426 rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
430 if (!netif_msg_rx_status(adapter
))
433 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
435 /* Advanced Receive Descriptor (Read) Format
437 * +-----------------------------------------------------+
438 * 0 | Packet Buffer Address [63:1] |A0/NSE|
439 * +----------------------------------------------+------+
440 * 8 | Header Buffer Address [63:1] | DD |
441 * +-----------------------------------------------------+
444 * Advanced Receive Descriptor (Write-Back) Format
446 * 63 48 47 32 31 30 21 20 16 15 4 3 0
447 * +------------------------------------------------------+
448 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
449 * | Checksum Ident | | | | Type | Type |
450 * +------------------------------------------------------+
451 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
452 * +------------------------------------------------------+
453 * 63 48 47 32 31 20 19 0
455 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
456 rx_ring
= adapter
->rx_ring
[n
];
457 printk(KERN_INFO
"------------------------------------\n");
458 printk(KERN_INFO
"RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
459 printk(KERN_INFO
"------------------------------------\n");
460 printk(KERN_INFO
"R [desc] [ PktBuf A0] "
461 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
462 "<-- Adv Rx Read format\n");
463 printk(KERN_INFO
"RWB[desc] [PcsmIpSHl PtRs] "
464 "[vl er S cks ln] ---------------- [bi->skb] "
465 "<-- Adv Rx Write-Back format\n");
467 for (i
= 0; i
< rx_ring
->count
; i
++) {
468 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
469 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
470 u0
= (struct my_u0
*)rx_desc
;
471 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
472 if (staterr
& IXGBE_RXD_STAT_DD
) {
473 /* Descriptor Done */
474 printk(KERN_INFO
"RWB[0x%03X] %016llX "
475 "%016llX ---------------- %p", i
,
478 rx_buffer_info
->skb
);
480 printk(KERN_INFO
"R [0x%03X] %016llX "
481 "%016llX %016llX %p", i
,
484 (u64
)rx_buffer_info
->dma
,
485 rx_buffer_info
->skb
);
487 if (netif_msg_pktdata(adapter
)) {
488 print_hex_dump(KERN_INFO
, "",
489 DUMP_PREFIX_ADDRESS
, 16, 1,
490 phys_to_virt(rx_buffer_info
->dma
),
491 rx_ring
->rx_buf_len
, true);
493 if (rx_ring
->rx_buf_len
494 < IXGBE_RXBUFFER_2048
)
495 print_hex_dump(KERN_INFO
, "",
496 DUMP_PREFIX_ADDRESS
, 16, 1,
498 rx_buffer_info
->page_dma
+
499 rx_buffer_info
->page_offset
505 if (i
== rx_ring
->next_to_use
)
506 printk(KERN_CONT
" NTU\n");
507 else if (i
== rx_ring
->next_to_clean
)
508 printk(KERN_CONT
" NTC\n");
510 printk(KERN_CONT
"\n");
519 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
523 /* Let firmware take over control of h/w */
524 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
525 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
526 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
529 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
533 /* Let firmware know the driver has taken over */
534 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
535 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
536 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
540 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
541 * @adapter: pointer to adapter struct
542 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
543 * @queue: queue to map the corresponding interrupt to
544 * @msix_vector: the vector to map to the corresponding queue
547 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
548 u8 queue
, u8 msix_vector
)
551 struct ixgbe_hw
*hw
= &adapter
->hw
;
552 switch (hw
->mac
.type
) {
553 case ixgbe_mac_82598EB
:
554 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
557 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
558 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
559 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
560 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
561 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
563 case ixgbe_mac_82599EB
:
564 if (direction
== -1) {
566 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
567 index
= ((queue
& 1) * 8);
568 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
569 ivar
&= ~(0xFF << index
);
570 ivar
|= (msix_vector
<< index
);
571 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
574 /* tx or rx causes */
575 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
576 index
= ((16 * (queue
& 1)) + (8 * direction
));
577 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
578 ivar
&= ~(0xFF << index
);
579 ivar
|= (msix_vector
<< index
);
580 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
588 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
593 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
594 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
595 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
597 mask
= (qmask
& 0xFFFFFFFF);
598 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
599 mask
= (qmask
>> 32);
600 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
604 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter
*adapter
,
605 struct ixgbe_tx_buffer
608 if (tx_buffer_info
->dma
) {
609 if (tx_buffer_info
->mapped_as_page
)
610 dma_unmap_page(&adapter
->pdev
->dev
,
612 tx_buffer_info
->length
,
615 dma_unmap_single(&adapter
->pdev
->dev
,
617 tx_buffer_info
->length
,
619 tx_buffer_info
->dma
= 0;
621 if (tx_buffer_info
->skb
) {
622 dev_kfree_skb_any(tx_buffer_info
->skb
);
623 tx_buffer_info
->skb
= NULL
;
625 tx_buffer_info
->time_stamp
= 0;
626 /* tx_buffer_info must be completely set up in the transmit path */
630 * ixgbe_tx_xon_state - check the tx ring xon state
631 * @adapter: the ixgbe adapter
632 * @tx_ring: the corresponding tx_ring
634 * If not in DCB mode, checks TFCS.TXOFF, otherwise, find out the
635 * corresponding TC of this tx_ring when checking TFCS.
637 * Returns : true if in xon state (currently not paused)
639 static inline bool ixgbe_tx_xon_state(struct ixgbe_adapter
*adapter
,
640 struct ixgbe_ring
*tx_ring
)
642 u32 txoff
= IXGBE_TFCS_TXOFF
;
644 #ifdef CONFIG_IXGBE_DCB
645 if (adapter
->dcb_cfg
.pfc_mode_enable
) {
647 int reg_idx
= tx_ring
->reg_idx
;
648 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
650 switch (adapter
->hw
.mac
.type
) {
651 case ixgbe_mac_82598EB
:
653 txoff
= IXGBE_TFCS_TXOFF0
;
655 case ixgbe_mac_82599EB
:
657 txoff
= IXGBE_TFCS_TXOFF
;
661 if (tc
== 2) /* TC2, TC3 */
662 tc
+= (reg_idx
- 64) >> 4;
663 else if (tc
== 3) /* TC4, TC5, TC6, TC7 */
664 tc
+= 1 + ((reg_idx
- 96) >> 3);
665 } else if (dcb_i
== 4) {
669 tc
+= (reg_idx
- 64) >> 5;
670 if (tc
== 2) /* TC2, TC3 */
671 tc
+= (reg_idx
- 96) >> 4;
681 return IXGBE_READ_REG(&adapter
->hw
, IXGBE_TFCS
) & txoff
;
684 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter
*adapter
,
685 struct ixgbe_ring
*tx_ring
,
688 struct ixgbe_hw
*hw
= &adapter
->hw
;
690 /* Detect a transmit hang in hardware, this serializes the
691 * check with the clearing of time_stamp and movement of eop */
692 adapter
->detect_tx_hung
= false;
693 if (tx_ring
->tx_buffer_info
[eop
].time_stamp
&&
694 time_after(jiffies
, tx_ring
->tx_buffer_info
[eop
].time_stamp
+ HZ
) &&
695 ixgbe_tx_xon_state(adapter
, tx_ring
)) {
696 /* detected Tx unit hang */
697 union ixgbe_adv_tx_desc
*tx_desc
;
698 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
699 e_err(drv
, "Detected Tx Unit Hang\n"
701 " TDH, TDT <%x>, <%x>\n"
702 " next_to_use <%x>\n"
703 " next_to_clean <%x>\n"
704 "tx_buffer_info[next_to_clean]\n"
705 " time_stamp <%lx>\n"
707 tx_ring
->queue_index
,
708 IXGBE_READ_REG(hw
, tx_ring
->head
),
709 IXGBE_READ_REG(hw
, tx_ring
->tail
),
710 tx_ring
->next_to_use
, eop
,
711 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
718 #define IXGBE_MAX_TXD_PWR 14
719 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
721 /* Tx Descriptors needed, worst case */
722 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
723 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
724 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
725 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
727 static void ixgbe_tx_timeout(struct net_device
*netdev
);
730 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
731 * @q_vector: structure containing interrupt and ring information
732 * @tx_ring: tx ring to clean
734 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
735 struct ixgbe_ring
*tx_ring
)
737 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
738 struct net_device
*netdev
= adapter
->netdev
;
739 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
740 struct ixgbe_tx_buffer
*tx_buffer_info
;
741 unsigned int i
, eop
, count
= 0;
742 unsigned int total_bytes
= 0, total_packets
= 0;
744 i
= tx_ring
->next_to_clean
;
745 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
746 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
748 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
749 (count
< tx_ring
->work_limit
)) {
750 bool cleaned
= false;
751 for ( ; !cleaned
; count
++) {
753 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
754 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
755 cleaned
= (i
== eop
);
756 skb
= tx_buffer_info
->skb
;
758 if (cleaned
&& skb
) {
759 unsigned int segs
, bytecount
;
760 unsigned int hlen
= skb_headlen(skb
);
762 /* gso_segs is currently only valid for tcp */
763 segs
= skb_shinfo(skb
)->gso_segs
?: 1;
765 /* adjust for FCoE Sequence Offload */
766 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
767 && (skb
->protocol
== htons(ETH_P_FCOE
)) &&
769 hlen
= skb_transport_offset(skb
) +
770 sizeof(struct fc_frame_header
) +
771 sizeof(struct fcoe_crc_eof
);
772 segs
= DIV_ROUND_UP(skb
->len
- hlen
,
773 skb_shinfo(skb
)->gso_size
);
775 #endif /* IXGBE_FCOE */
776 /* multiply data chunks by size of headers */
777 bytecount
= ((segs
- 1) * hlen
) + skb
->len
;
778 total_packets
+= segs
;
779 total_bytes
+= bytecount
;
782 ixgbe_unmap_and_free_tx_resource(adapter
,
785 tx_desc
->wb
.status
= 0;
788 if (i
== tx_ring
->count
)
792 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
793 eop_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, eop
);
796 tx_ring
->next_to_clean
= i
;
798 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
799 if (unlikely(count
&& netif_carrier_ok(netdev
) &&
800 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
801 /* Make sure that anybody stopping the queue after this
802 * sees the new next_to_clean.
805 if (__netif_subqueue_stopped(netdev
, tx_ring
->queue_index
) &&
806 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
807 netif_wake_subqueue(netdev
, tx_ring
->queue_index
);
808 ++tx_ring
->restart_queue
;
812 if (adapter
->detect_tx_hung
) {
813 if (ixgbe_check_tx_hang(adapter
, tx_ring
, i
)) {
814 /* schedule immediate reset if we believe we hung */
815 e_info(probe
, "tx hang %d detected, resetting "
816 "adapter\n", adapter
->tx_timeout_count
+ 1);
817 ixgbe_tx_timeout(adapter
->netdev
);
821 /* re-arm the interrupt */
822 if (count
>= tx_ring
->work_limit
)
823 ixgbe_irq_rearm_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
825 tx_ring
->total_bytes
+= total_bytes
;
826 tx_ring
->total_packets
+= total_packets
;
827 tx_ring
->stats
.packets
+= total_packets
;
828 tx_ring
->stats
.bytes
+= total_bytes
;
829 return (count
< tx_ring
->work_limit
);
832 #ifdef CONFIG_IXGBE_DCA
833 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
834 struct ixgbe_ring
*rx_ring
)
838 int q
= rx_ring
->reg_idx
;
840 if (rx_ring
->cpu
!= cpu
) {
841 rxctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
));
842 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
843 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
844 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
845 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
846 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
847 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
848 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
850 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
851 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
852 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
853 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN
|
854 IXGBE_DCA_RXCTRL_DESC_HSRO_EN
);
855 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_RXCTRL(q
), rxctrl
);
861 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
862 struct ixgbe_ring
*tx_ring
)
866 int q
= tx_ring
->reg_idx
;
867 struct ixgbe_hw
*hw
= &adapter
->hw
;
869 if (tx_ring
->cpu
!= cpu
) {
870 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
871 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(q
));
872 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
873 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
874 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
875 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(q
), txctrl
);
876 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
877 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
));
878 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
879 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
880 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
881 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
882 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(q
), txctrl
);
889 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
893 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
896 /* always use CB2 mode, difference is masked in the CB driver */
897 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
899 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
900 adapter
->tx_ring
[i
]->cpu
= -1;
901 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[i
]);
903 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
904 adapter
->rx_ring
[i
]->cpu
= -1;
905 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[i
]);
909 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
911 struct net_device
*netdev
= dev_get_drvdata(dev
);
912 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
913 unsigned long event
= *(unsigned long *)data
;
916 case DCA_PROVIDER_ADD
:
917 /* if we're already enabled, don't do it again */
918 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
920 if (dca_add_requester(dev
) == 0) {
921 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
922 ixgbe_setup_dca(adapter
);
925 /* Fall Through since DCA is disabled. */
926 case DCA_PROVIDER_REMOVE
:
927 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
928 dca_remove_requester(dev
);
929 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
930 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
938 #endif /* CONFIG_IXGBE_DCA */
940 * ixgbe_receive_skb - Send a completed packet up the stack
941 * @adapter: board private structure
942 * @skb: packet to send up
943 * @status: hardware indication of status of receive
944 * @rx_ring: rx descriptor ring (for a specific queue) to setup
945 * @rx_desc: rx descriptor
947 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
948 struct sk_buff
*skb
, u8 status
,
949 struct ixgbe_ring
*ring
,
950 union ixgbe_adv_rx_desc
*rx_desc
)
952 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
953 struct napi_struct
*napi
= &q_vector
->napi
;
954 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
955 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
957 skb_record_rx_queue(skb
, ring
->queue_index
);
958 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
)) {
959 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
960 vlan_gro_receive(napi
, adapter
->vlgrp
, tag
, skb
);
962 napi_gro_receive(napi
, skb
);
964 if (adapter
->vlgrp
&& is_vlan
&& (tag
& VLAN_VID_MASK
))
965 vlan_hwaccel_rx(skb
, adapter
->vlgrp
, tag
);
972 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
973 * @adapter: address of board private structure
974 * @status_err: hardware indication of status of receive
975 * @skb: skb currently being received and modified
977 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
978 union ixgbe_adv_rx_desc
*rx_desc
,
981 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
983 skb
->ip_summed
= CHECKSUM_NONE
;
985 /* Rx csum disabled */
986 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
989 /* if IP and error */
990 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
991 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
992 adapter
->hw_csum_rx_error
++;
996 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
999 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1000 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1003 * 82599 errata, UDP frames with a 0 checksum can be marked as
1006 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1007 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1010 adapter
->hw_csum_rx_error
++;
1014 /* It must be a TCP or UDP packet with a valid checksum */
1015 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1018 static inline void ixgbe_release_rx_desc(struct ixgbe_hw
*hw
,
1019 struct ixgbe_ring
*rx_ring
, u32 val
)
1022 * Force memory writes to complete before letting h/w
1023 * know there are new descriptors to fetch. (Only
1024 * applicable for weak-ordered memory model archs,
1028 IXGBE_WRITE_REG(hw
, IXGBE_RDT(rx_ring
->reg_idx
), val
);
1032 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1033 * @adapter: address of board private structure
1035 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter
*adapter
,
1036 struct ixgbe_ring
*rx_ring
,
1039 struct pci_dev
*pdev
= adapter
->pdev
;
1040 union ixgbe_adv_rx_desc
*rx_desc
;
1041 struct ixgbe_rx_buffer
*bi
;
1044 i
= rx_ring
->next_to_use
;
1045 bi
= &rx_ring
->rx_buffer_info
[i
];
1047 while (cleaned_count
--) {
1048 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1050 if (!bi
->page_dma
&&
1051 (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)) {
1053 bi
->page
= alloc_page(GFP_ATOMIC
);
1055 adapter
->alloc_rx_page_failed
++;
1058 bi
->page_offset
= 0;
1060 /* use a half page if we're re-using */
1061 bi
->page_offset
^= (PAGE_SIZE
/ 2);
1064 bi
->page_dma
= dma_map_page(&pdev
->dev
, bi
->page
,
1071 struct sk_buff
*skb
;
1072 /* netdev_alloc_skb reserves 32 bytes up front!! */
1073 uint bufsz
= rx_ring
->rx_buf_len
+ SMP_CACHE_BYTES
;
1074 skb
= netdev_alloc_skb(adapter
->netdev
, bufsz
);
1077 adapter
->alloc_rx_buff_failed
++;
1081 /* advance the data pointer to the next cache line */
1082 skb_reserve(skb
, (PTR_ALIGN(skb
->data
, SMP_CACHE_BYTES
)
1086 bi
->dma
= dma_map_single(&pdev
->dev
, skb
->data
,
1087 rx_ring
->rx_buf_len
,
1090 /* Refresh the desc even if buffer_addrs didn't change because
1091 * each write-back erases this info. */
1092 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1093 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1094 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1096 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1100 if (i
== rx_ring
->count
)
1102 bi
= &rx_ring
->rx_buffer_info
[i
];
1106 if (rx_ring
->next_to_use
!= i
) {
1107 rx_ring
->next_to_use
= i
;
1109 i
= (rx_ring
->count
- 1);
1111 ixgbe_release_rx_desc(&adapter
->hw
, rx_ring
, i
);
1115 static inline u16
ixgbe_get_hdr_info(union ixgbe_adv_rx_desc
*rx_desc
)
1117 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
;
1120 static inline u16
ixgbe_get_pkt_info(union ixgbe_adv_rx_desc
*rx_desc
)
1122 return rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1125 static inline u32
ixgbe_get_rsc_count(union ixgbe_adv_rx_desc
*rx_desc
)
1127 return (le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1128 IXGBE_RXDADV_RSCCNT_MASK
) >>
1129 IXGBE_RXDADV_RSCCNT_SHIFT
;
1133 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1134 * @skb: pointer to the last skb in the rsc queue
1135 * @count: pointer to number of packets coalesced in this context
1137 * This function changes a queue full of hw rsc buffers into a completed
1138 * packet. It uses the ->prev pointers to find the first packet and then
1139 * turns it into the frag list owner.
1141 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
,
1144 unsigned int frag_list_size
= 0;
1147 struct sk_buff
*prev
= skb
->prev
;
1148 frag_list_size
+= skb
->len
;
1154 skb_shinfo(skb
)->frag_list
= skb
->next
;
1156 skb
->len
+= frag_list_size
;
1157 skb
->data_len
+= frag_list_size
;
1158 skb
->truesize
+= frag_list_size
;
1162 struct ixgbe_rsc_cb
{
1167 #define IXGBE_RSC_CB(skb) ((struct ixgbe_rsc_cb *)(skb)->cb)
1169 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1170 struct ixgbe_ring
*rx_ring
,
1171 int *work_done
, int work_to_do
)
1173 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1174 struct net_device
*netdev
= adapter
->netdev
;
1175 struct pci_dev
*pdev
= adapter
->pdev
;
1176 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1177 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1178 struct sk_buff
*skb
;
1179 unsigned int i
, rsc_count
= 0;
1182 bool cleaned
= false;
1183 int cleaned_count
= 0;
1184 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1187 #endif /* IXGBE_FCOE */
1189 i
= rx_ring
->next_to_clean
;
1190 rx_desc
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1191 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1192 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1194 while (staterr
& IXGBE_RXD_STAT_DD
) {
1196 if (*work_done
>= work_to_do
)
1200 rmb(); /* read descriptor and rx_buffer_info after status DD */
1201 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1202 hdr_info
= le16_to_cpu(ixgbe_get_hdr_info(rx_desc
));
1203 len
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1204 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1205 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1206 if ((len
> IXGBE_RX_HDR_SIZE
) ||
1207 (upper_len
&& !(hdr_info
& IXGBE_RXDADV_SPH
)))
1208 len
= IXGBE_RX_HDR_SIZE
;
1210 len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1214 skb
= rx_buffer_info
->skb
;
1215 prefetch(skb
->data
);
1216 rx_buffer_info
->skb
= NULL
;
1218 if (rx_buffer_info
->dma
) {
1219 if ((adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
1220 (!(staterr
& IXGBE_RXD_STAT_EOP
)) &&
1223 * When HWRSC is enabled, delay unmapping
1224 * of the first packet. It carries the
1225 * header information, HW may still
1226 * access the header after the writeback.
1227 * Only unmap it when EOP is reached
1229 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1230 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1232 dma_unmap_single(&pdev
->dev
,
1233 rx_buffer_info
->dma
,
1234 rx_ring
->rx_buf_len
,
1237 rx_buffer_info
->dma
= 0;
1242 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
1243 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
1244 rx_buffer_info
->page_dma
= 0;
1245 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1246 rx_buffer_info
->page
,
1247 rx_buffer_info
->page_offset
,
1250 if ((rx_ring
->rx_buf_len
> (PAGE_SIZE
/ 2)) ||
1251 (page_count(rx_buffer_info
->page
) != 1))
1252 rx_buffer_info
->page
= NULL
;
1254 get_page(rx_buffer_info
->page
);
1256 skb
->len
+= upper_len
;
1257 skb
->data_len
+= upper_len
;
1258 skb
->truesize
+= upper_len
;
1262 if (i
== rx_ring
->count
)
1265 next_rxd
= IXGBE_RX_DESC_ADV(*rx_ring
, i
);
1269 if (adapter
->flags2
& IXGBE_FLAG2_RSC_CAPABLE
)
1270 rsc_count
= ixgbe_get_rsc_count(rx_desc
);
1273 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1274 IXGBE_RXDADV_NEXTP_SHIFT
;
1275 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1277 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1280 if (staterr
& IXGBE_RXD_STAT_EOP
) {
1282 skb
= ixgbe_transform_rsc_queue(skb
, &(rx_ring
->rsc_count
));
1283 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
1284 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1285 dma_unmap_single(&pdev
->dev
,
1286 IXGBE_RSC_CB(skb
)->dma
,
1287 rx_ring
->rx_buf_len
,
1289 IXGBE_RSC_CB(skb
)->dma
= 0;
1290 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1292 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
)
1293 rx_ring
->rsc_count
+= skb_shinfo(skb
)->nr_frags
;
1295 rx_ring
->rsc_count
++;
1296 rx_ring
->rsc_flush
++;
1298 rx_ring
->stats
.packets
++;
1299 rx_ring
->stats
.bytes
+= skb
->len
;
1301 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
1302 rx_buffer_info
->skb
= next_buffer
->skb
;
1303 rx_buffer_info
->dma
= next_buffer
->dma
;
1304 next_buffer
->skb
= skb
;
1305 next_buffer
->dma
= 0;
1307 skb
->next
= next_buffer
->skb
;
1308 skb
->next
->prev
= skb
;
1310 rx_ring
->non_eop_descs
++;
1314 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1315 dev_kfree_skb_irq(skb
);
1319 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1321 /* probably a little skewed due to removing CRC */
1322 total_rx_bytes
+= skb
->len
;
1325 skb
->protocol
= eth_type_trans(skb
, adapter
->netdev
);
1327 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1328 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1329 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1333 #endif /* IXGBE_FCOE */
1334 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1337 rx_desc
->wb
.upper
.status_error
= 0;
1339 /* return some buffers to hardware, one at a time is too slow */
1340 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1341 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1345 /* use prefetched values */
1347 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1349 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1352 rx_ring
->next_to_clean
= i
;
1353 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1356 ixgbe_alloc_rx_buffers(adapter
, rx_ring
, cleaned_count
);
1359 /* include DDPed FCoE data */
1360 if (ddp_bytes
> 0) {
1363 mss
= adapter
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1364 sizeof(struct fc_frame_header
) -
1365 sizeof(struct fcoe_crc_eof
);
1368 total_rx_bytes
+= ddp_bytes
;
1369 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1371 #endif /* IXGBE_FCOE */
1373 rx_ring
->total_packets
+= total_rx_packets
;
1374 rx_ring
->total_bytes
+= total_rx_bytes
;
1375 netdev
->stats
.rx_bytes
+= total_rx_bytes
;
1376 netdev
->stats
.rx_packets
+= total_rx_packets
;
1381 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1383 * ixgbe_configure_msix - Configure MSI-X hardware
1384 * @adapter: board private structure
1386 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1389 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1391 struct ixgbe_q_vector
*q_vector
;
1392 int i
, j
, q_vectors
, v_idx
, r_idx
;
1395 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1398 * Populate the IVAR table and set the ITR values to the
1399 * corresponding register.
1401 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1402 q_vector
= adapter
->q_vector
[v_idx
];
1403 /* XXX for_each_set_bit(...) */
1404 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1405 adapter
->num_rx_queues
);
1407 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1408 j
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1409 ixgbe_set_ivar(adapter
, 0, j
, v_idx
);
1410 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1411 adapter
->num_rx_queues
,
1414 r_idx
= find_first_bit(q_vector
->txr_idx
,
1415 adapter
->num_tx_queues
);
1417 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1418 j
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1419 ixgbe_set_ivar(adapter
, 1, j
, v_idx
);
1420 r_idx
= find_next_bit(q_vector
->txr_idx
,
1421 adapter
->num_tx_queues
,
1425 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1427 q_vector
->eitr
= adapter
->tx_eitr_param
;
1428 else if (q_vector
->rxr_count
)
1430 q_vector
->eitr
= adapter
->rx_eitr_param
;
1432 ixgbe_write_eitr(q_vector
);
1435 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
1436 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1438 else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
1439 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1440 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1442 /* set up to autoclear timer, and the vectors */
1443 mask
= IXGBE_EIMS_ENABLE_MASK
;
1444 if (adapter
->num_vfs
)
1445 mask
&= ~(IXGBE_EIMS_OTHER
|
1446 IXGBE_EIMS_MAILBOX
|
1449 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1450 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1453 enum latency_range
{
1457 latency_invalid
= 255
1461 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1462 * @adapter: pointer to adapter
1463 * @eitr: eitr setting (ints per sec) to give last timeslice
1464 * @itr_setting: current throttle rate in ints/second
1465 * @packets: the number of packets during this measurement interval
1466 * @bytes: the number of bytes during this measurement interval
1468 * Stores a new ITR value based on packets and byte
1469 * counts during the last interrupt. The advantage of per interrupt
1470 * computation is faster updates and more accurate ITR for the current
1471 * traffic pattern. Constants in this function were computed
1472 * based on theoretical maximum wire speed and thresholds were set based
1473 * on testing data as well as attempting to minimize response time
1474 * while increasing bulk throughput.
1475 * this functionality is controlled by the InterruptThrottleRate module
1476 * parameter (see ixgbe_param.c)
1478 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1479 u32 eitr
, u8 itr_setting
,
1480 int packets
, int bytes
)
1482 unsigned int retval
= itr_setting
;
1487 goto update_itr_done
;
1490 /* simple throttlerate management
1491 * 0-20MB/s lowest (100000 ints/s)
1492 * 20-100MB/s low (20000 ints/s)
1493 * 100-1249MB/s bulk (8000 ints/s)
1495 /* what was last interrupt timeslice? */
1496 timepassed_us
= 1000000/eitr
;
1497 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1499 switch (itr_setting
) {
1500 case lowest_latency
:
1501 if (bytes_perint
> adapter
->eitr_low
)
1502 retval
= low_latency
;
1505 if (bytes_perint
> adapter
->eitr_high
)
1506 retval
= bulk_latency
;
1507 else if (bytes_perint
<= adapter
->eitr_low
)
1508 retval
= lowest_latency
;
1511 if (bytes_perint
<= adapter
->eitr_high
)
1512 retval
= low_latency
;
1521 * ixgbe_write_eitr - write EITR register in hardware specific way
1522 * @q_vector: structure containing interrupt and ring information
1524 * This function is made to be called by ethtool and by the driver
1525 * when it needs to update EITR registers at runtime. Hardware
1526 * specific quirks/differences are taken care of here.
1528 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1530 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1531 struct ixgbe_hw
*hw
= &adapter
->hw
;
1532 int v_idx
= q_vector
->v_idx
;
1533 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1535 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1536 /* must write high and low 16 bits to reset counter */
1537 itr_reg
|= (itr_reg
<< 16);
1538 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
1540 * 82599 can support a value of zero, so allow it for
1541 * max interrupt rate, but there is an errata where it can
1542 * not be zero with RSC
1545 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1549 * set the WDIS bit to not clear the timer bits and cause an
1550 * immediate assertion of the interrupt
1552 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1554 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1557 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1559 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1561 u8 current_itr
, ret_itr
;
1563 struct ixgbe_ring
*rx_ring
, *tx_ring
;
1565 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1566 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1567 tx_ring
= adapter
->tx_ring
[r_idx
];
1568 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1570 tx_ring
->total_packets
,
1571 tx_ring
->total_bytes
);
1572 /* if the result for this queue would decrease interrupt
1573 * rate for this vector then use that result */
1574 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1575 q_vector
->tx_itr
- 1 : ret_itr
);
1576 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1580 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1581 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1582 rx_ring
= adapter
->rx_ring
[r_idx
];
1583 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1585 rx_ring
->total_packets
,
1586 rx_ring
->total_bytes
);
1587 /* if the result for this queue would decrease interrupt
1588 * rate for this vector then use that result */
1589 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1590 q_vector
->rx_itr
- 1 : ret_itr
);
1591 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1595 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1597 switch (current_itr
) {
1598 /* counts and packets in update_itr are dependent on these numbers */
1599 case lowest_latency
:
1603 new_itr
= 20000; /* aka hwitr = ~200 */
1611 if (new_itr
!= q_vector
->eitr
) {
1612 /* do an exponential smoothing */
1613 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
1615 /* save the algorithm value here, not the smoothed one */
1616 q_vector
->eitr
= new_itr
;
1618 ixgbe_write_eitr(q_vector
);
1623 * ixgbe_check_overtemp_task - worker thread to check over tempurature
1624 * @work: pointer to work_struct containing our data
1626 static void ixgbe_check_overtemp_task(struct work_struct
*work
)
1628 struct ixgbe_adapter
*adapter
= container_of(work
,
1629 struct ixgbe_adapter
,
1630 check_overtemp_task
);
1631 struct ixgbe_hw
*hw
= &adapter
->hw
;
1632 u32 eicr
= adapter
->interrupt_event
;
1634 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
1635 switch (hw
->device_id
) {
1636 case IXGBE_DEV_ID_82599_T3_LOM
: {
1638 bool link_up
= false;
1640 if (hw
->mac
.ops
.check_link
)
1641 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1643 if (((eicr
& IXGBE_EICR_GPI_SDP0
) && (!link_up
)) ||
1644 (eicr
& IXGBE_EICR_LSC
))
1645 /* Check if this is due to overtemp */
1646 if (hw
->phy
.ops
.check_overtemp(hw
) == IXGBE_ERR_OVERTEMP
)
1651 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1655 e_crit(drv
, "Network adapter has been stopped because it has "
1656 "over heated. Restart the computer. If the problem "
1657 "persists, power off the system and replace the "
1659 /* write to clear the interrupt */
1660 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP0
);
1664 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1666 struct ixgbe_hw
*hw
= &adapter
->hw
;
1668 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1669 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1670 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1671 /* write to clear the interrupt */
1672 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1676 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1678 struct ixgbe_hw
*hw
= &adapter
->hw
;
1680 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1681 /* Clear the interrupt */
1682 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1683 schedule_work(&adapter
->multispeed_fiber_task
);
1684 } else if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1685 /* Clear the interrupt */
1686 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1687 schedule_work(&adapter
->sfp_config_module_task
);
1689 /* Interrupt isn't for us... */
1694 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1696 struct ixgbe_hw
*hw
= &adapter
->hw
;
1699 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1700 adapter
->link_check_timeout
= jiffies
;
1701 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1702 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1703 IXGBE_WRITE_FLUSH(hw
);
1704 schedule_work(&adapter
->watchdog_task
);
1708 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1710 struct net_device
*netdev
= data
;
1711 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1712 struct ixgbe_hw
*hw
= &adapter
->hw
;
1716 * Workaround for Silicon errata. Use clear-by-write instead
1717 * of clear-by-read. Reading with EICS will return the
1718 * interrupt causes without clearing, which later be done
1719 * with the write to EICR.
1721 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1722 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1724 if (eicr
& IXGBE_EICR_LSC
)
1725 ixgbe_check_lsc(adapter
);
1727 if (eicr
& IXGBE_EICR_MAILBOX
)
1728 ixgbe_msg_task(adapter
);
1730 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
1731 ixgbe_check_fan_failure(adapter
, eicr
);
1733 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
1734 ixgbe_check_sfp_event(adapter
, eicr
);
1735 adapter
->interrupt_event
= eicr
;
1736 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1737 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
1738 schedule_work(&adapter
->check_overtemp_task
);
1740 /* Handle Flow Director Full threshold interrupt */
1741 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1743 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_FLOW_DIR
);
1744 /* Disable transmits before FDIR Re-initialization */
1745 netif_tx_stop_all_queues(netdev
);
1746 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1747 struct ixgbe_ring
*tx_ring
=
1748 adapter
->tx_ring
[i
];
1749 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE
,
1750 &tx_ring
->reinit_state
))
1751 schedule_work(&adapter
->fdir_reinit_task
);
1755 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1756 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_OTHER
);
1761 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
1766 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1767 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1768 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
1770 mask
= (qmask
& 0xFFFFFFFF);
1771 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(0), mask
);
1772 mask
= (qmask
>> 32);
1773 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS_EX(1), mask
);
1775 /* skip the flush */
1778 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
1783 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
1784 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
1785 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, mask
);
1787 mask
= (qmask
& 0xFFFFFFFF);
1788 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), mask
);
1789 mask
= (qmask
>> 32);
1790 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), mask
);
1792 /* skip the flush */
1795 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
1797 struct ixgbe_q_vector
*q_vector
= data
;
1798 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1799 struct ixgbe_ring
*tx_ring
;
1802 if (!q_vector
->txr_count
)
1805 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1806 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1807 tx_ring
= adapter
->tx_ring
[r_idx
];
1808 tx_ring
->total_bytes
= 0;
1809 tx_ring
->total_packets
= 0;
1810 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1814 /* EIAM disabled interrupts (on this vector) for us */
1815 napi_schedule(&q_vector
->napi
);
1821 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1823 * @data: pointer to our q_vector struct for this interrupt vector
1825 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
1827 struct ixgbe_q_vector
*q_vector
= data
;
1828 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1829 struct ixgbe_ring
*rx_ring
;
1833 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1834 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1835 rx_ring
= adapter
->rx_ring
[r_idx
];
1836 rx_ring
->total_bytes
= 0;
1837 rx_ring
->total_packets
= 0;
1838 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1842 if (!q_vector
->rxr_count
)
1845 /* disable interrupts on this vector only */
1846 /* EIAM disabled interrupts (on this vector) for us */
1847 napi_schedule(&q_vector
->napi
);
1852 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
1854 struct ixgbe_q_vector
*q_vector
= data
;
1855 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1856 struct ixgbe_ring
*ring
;
1860 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
1863 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1864 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1865 ring
= adapter
->tx_ring
[r_idx
];
1866 ring
->total_bytes
= 0;
1867 ring
->total_packets
= 0;
1868 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1872 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1873 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1874 ring
= adapter
->rx_ring
[r_idx
];
1875 ring
->total_bytes
= 0;
1876 ring
->total_packets
= 0;
1877 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1881 /* EIAM disabled interrupts (on this vector) for us */
1882 napi_schedule(&q_vector
->napi
);
1888 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1889 * @napi: napi struct with our devices info in it
1890 * @budget: amount of work driver is allowed to do this pass, in packets
1892 * This function is optimized for cleaning one queue only on a single
1895 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
1897 struct ixgbe_q_vector
*q_vector
=
1898 container_of(napi
, struct ixgbe_q_vector
, napi
);
1899 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1900 struct ixgbe_ring
*rx_ring
= NULL
;
1904 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1905 rx_ring
= adapter
->rx_ring
[r_idx
];
1906 #ifdef CONFIG_IXGBE_DCA
1907 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1908 ixgbe_update_rx_dca(adapter
, rx_ring
);
1911 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
1913 /* If all Rx work done, exit the polling mode */
1914 if (work_done
< budget
) {
1915 napi_complete(napi
);
1916 if (adapter
->rx_itr_setting
& 1)
1917 ixgbe_set_itr_msix(q_vector
);
1918 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1919 ixgbe_irq_enable_queues(adapter
,
1920 ((u64
)1 << q_vector
->v_idx
));
1927 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1928 * @napi: napi struct with our devices info in it
1929 * @budget: amount of work driver is allowed to do this pass, in packets
1931 * This function will clean more than one rx queue associated with a
1934 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
1936 struct ixgbe_q_vector
*q_vector
=
1937 container_of(napi
, struct ixgbe_q_vector
, napi
);
1938 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1939 struct ixgbe_ring
*ring
= NULL
;
1940 int work_done
= 0, i
;
1942 bool tx_clean_complete
= true;
1944 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1945 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1946 ring
= adapter
->tx_ring
[r_idx
];
1947 #ifdef CONFIG_IXGBE_DCA
1948 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1949 ixgbe_update_tx_dca(adapter
, ring
);
1951 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
1952 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1956 /* attempt to distribute budget to each queue fairly, but don't allow
1957 * the budget to go below 1 because we'll exit polling */
1958 budget
/= (q_vector
->rxr_count
?: 1);
1959 budget
= max(budget
, 1);
1960 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1961 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1962 ring
= adapter
->rx_ring
[r_idx
];
1963 #ifdef CONFIG_IXGBE_DCA
1964 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1965 ixgbe_update_rx_dca(adapter
, ring
);
1967 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
1968 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1972 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1973 ring
= adapter
->rx_ring
[r_idx
];
1974 /* If all Rx work done, exit the polling mode */
1975 if (work_done
< budget
) {
1976 napi_complete(napi
);
1977 if (adapter
->rx_itr_setting
& 1)
1978 ixgbe_set_itr_msix(q_vector
);
1979 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
1980 ixgbe_irq_enable_queues(adapter
,
1981 ((u64
)1 << q_vector
->v_idx
));
1989 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1990 * @napi: napi struct with our devices info in it
1991 * @budget: amount of work driver is allowed to do this pass, in packets
1993 * This function is optimized for cleaning one queue only on a single
1996 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
1998 struct ixgbe_q_vector
*q_vector
=
1999 container_of(napi
, struct ixgbe_q_vector
, napi
);
2000 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2001 struct ixgbe_ring
*tx_ring
= NULL
;
2005 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2006 tx_ring
= adapter
->tx_ring
[r_idx
];
2007 #ifdef CONFIG_IXGBE_DCA
2008 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2009 ixgbe_update_tx_dca(adapter
, tx_ring
);
2012 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2015 /* If all Tx work done, exit the polling mode */
2016 if (work_done
< budget
) {
2017 napi_complete(napi
);
2018 if (adapter
->tx_itr_setting
& 1)
2019 ixgbe_set_itr_msix(q_vector
);
2020 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2021 ixgbe_irq_enable_queues(adapter
, ((u64
)1 << q_vector
->v_idx
));
2027 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2030 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2032 set_bit(r_idx
, q_vector
->rxr_idx
);
2033 q_vector
->rxr_count
++;
2036 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2039 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2041 set_bit(t_idx
, q_vector
->txr_idx
);
2042 q_vector
->txr_count
++;
2046 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2047 * @adapter: board private structure to initialize
2048 * @vectors: allotted vector count for descriptor rings
2050 * This function maps descriptor rings to the queue-specific vectors
2051 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2052 * one vector per ring/queue, but on a constrained vector budget, we
2053 * group the rings as "efficiently" as possible. You would add new
2054 * mapping configurations in here.
2056 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
,
2060 int rxr_idx
= 0, txr_idx
= 0;
2061 int rxr_remaining
= adapter
->num_rx_queues
;
2062 int txr_remaining
= adapter
->num_tx_queues
;
2067 /* No mapping required if MSI-X is disabled. */
2068 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2072 * The ideal configuration...
2073 * We have enough vectors to map one per queue.
2075 if (vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2076 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2077 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2079 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2080 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2086 * If we don't have enough vectors for a 1-to-1
2087 * mapping, we'll have to group them so there are
2088 * multiple queues per vector.
2090 /* Re-adjusting *qpv takes care of the remainder. */
2091 for (i
= v_start
; i
< vectors
; i
++) {
2092 rqpv
= DIV_ROUND_UP(rxr_remaining
, vectors
- i
);
2093 for (j
= 0; j
< rqpv
; j
++) {
2094 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2099 for (i
= v_start
; i
< vectors
; i
++) {
2100 tqpv
= DIV_ROUND_UP(txr_remaining
, vectors
- i
);
2101 for (j
= 0; j
< tqpv
; j
++) {
2102 map_vector_to_txq(adapter
, i
, txr_idx
);
2113 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2114 * @adapter: board private structure
2116 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2117 * interrupts from the kernel.
2119 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2121 struct net_device
*netdev
= adapter
->netdev
;
2122 irqreturn_t (*handler
)(int, void *);
2123 int i
, vector
, q_vectors
, err
;
2126 /* Decrement for Other and TCP Timer vectors */
2127 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2129 /* Map the Tx/Rx rings to the vectors we were allotted. */
2130 err
= ixgbe_map_rings_to_vectors(adapter
, q_vectors
);
2134 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
2135 (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
2136 &ixgbe_msix_clean_many)
2137 for (vector
= 0; vector
< q_vectors
; vector
++) {
2138 handler
= SET_HANDLER(adapter
->q_vector
[vector
]);
2140 if(handler
== &ixgbe_msix_clean_rx
) {
2141 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2142 netdev
->name
, "rx", ri
++);
2144 else if(handler
== &ixgbe_msix_clean_tx
) {
2145 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2146 netdev
->name
, "tx", ti
++);
2149 sprintf(adapter
->name
[vector
], "%s-%s-%d",
2150 netdev
->name
, "TxRx", vector
);
2152 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2153 handler
, 0, adapter
->name
[vector
],
2154 adapter
->q_vector
[vector
]);
2156 e_err(probe
, "request_irq failed for MSIX interrupt "
2157 "Error: %d\n", err
);
2158 goto free_queue_irqs
;
2162 sprintf(adapter
->name
[vector
], "%s:lsc", netdev
->name
);
2163 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2164 ixgbe_msix_lsc
, 0, adapter
->name
[vector
], netdev
);
2166 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2167 goto free_queue_irqs
;
2173 for (i
= vector
- 1; i
>= 0; i
--)
2174 free_irq(adapter
->msix_entries
[--vector
].vector
,
2175 adapter
->q_vector
[i
]);
2176 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2177 pci_disable_msix(adapter
->pdev
);
2178 kfree(adapter
->msix_entries
);
2179 adapter
->msix_entries
= NULL
;
2184 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2186 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2188 u32 new_itr
= q_vector
->eitr
;
2189 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2190 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2192 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2194 tx_ring
->total_packets
,
2195 tx_ring
->total_bytes
);
2196 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2198 rx_ring
->total_packets
,
2199 rx_ring
->total_bytes
);
2201 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2203 switch (current_itr
) {
2204 /* counts and packets in update_itr are dependent on these numbers */
2205 case lowest_latency
:
2209 new_itr
= 20000; /* aka hwitr = ~200 */
2218 if (new_itr
!= q_vector
->eitr
) {
2219 /* do an exponential smoothing */
2220 new_itr
= ((q_vector
->eitr
* 90)/100) + ((new_itr
* 10)/100);
2222 /* save the algorithm value here, not the smoothed one */
2223 q_vector
->eitr
= new_itr
;
2225 ixgbe_write_eitr(q_vector
);
2230 * ixgbe_irq_enable - Enable default interrupt generation settings
2231 * @adapter: board private structure
2233 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
)
2237 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2238 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2239 mask
|= IXGBE_EIMS_GPI_SDP0
;
2240 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2241 mask
|= IXGBE_EIMS_GPI_SDP1
;
2242 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
2243 mask
|= IXGBE_EIMS_ECC
;
2244 mask
|= IXGBE_EIMS_GPI_SDP1
;
2245 mask
|= IXGBE_EIMS_GPI_SDP2
;
2246 if (adapter
->num_vfs
)
2247 mask
|= IXGBE_EIMS_MAILBOX
;
2249 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2250 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2251 mask
|= IXGBE_EIMS_FLOW_DIR
;
2253 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2254 ixgbe_irq_enable_queues(adapter
, ~0);
2255 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2257 if (adapter
->num_vfs
> 32) {
2258 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2259 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2264 * ixgbe_intr - legacy mode Interrupt Handler
2265 * @irq: interrupt number
2266 * @data: pointer to a network interface device structure
2268 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2270 struct net_device
*netdev
= data
;
2271 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2272 struct ixgbe_hw
*hw
= &adapter
->hw
;
2273 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2277 * Workaround for silicon errata. Mask the interrupts
2278 * before the read of EICR.
2280 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2282 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2283 * therefore no explict interrupt disable is necessary */
2284 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2286 /* shared interrupt alert!
2287 * make sure interrupts are enabled because the read will
2288 * have disabled interrupts due to EIAM */
2289 ixgbe_irq_enable(adapter
);
2290 return IRQ_NONE
; /* Not our interrupt */
2293 if (eicr
& IXGBE_EICR_LSC
)
2294 ixgbe_check_lsc(adapter
);
2296 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
2297 ixgbe_check_sfp_event(adapter
, eicr
);
2299 ixgbe_check_fan_failure(adapter
, eicr
);
2300 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2301 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
)))
2302 schedule_work(&adapter
->check_overtemp_task
);
2304 if (napi_schedule_prep(&(q_vector
->napi
))) {
2305 adapter
->tx_ring
[0]->total_packets
= 0;
2306 adapter
->tx_ring
[0]->total_bytes
= 0;
2307 adapter
->rx_ring
[0]->total_packets
= 0;
2308 adapter
->rx_ring
[0]->total_bytes
= 0;
2309 /* would disable interrupts here but EIAM disabled it */
2310 __napi_schedule(&(q_vector
->napi
));
2316 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2318 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2320 for (i
= 0; i
< q_vectors
; i
++) {
2321 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2322 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2323 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2324 q_vector
->rxr_count
= 0;
2325 q_vector
->txr_count
= 0;
2330 * ixgbe_request_irq - initialize interrupts
2331 * @adapter: board private structure
2333 * Attempts to configure interrupts using the best available
2334 * capabilities of the hardware and kernel.
2336 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2338 struct net_device
*netdev
= adapter
->netdev
;
2341 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2342 err
= ixgbe_request_msix_irqs(adapter
);
2343 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2344 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2345 netdev
->name
, netdev
);
2347 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2348 netdev
->name
, netdev
);
2352 e_err(probe
, "request_irq failed, Error %d\n", err
);
2357 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2359 struct net_device
*netdev
= adapter
->netdev
;
2361 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2364 q_vectors
= adapter
->num_msix_vectors
;
2367 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2370 for (; i
>= 0; i
--) {
2371 free_irq(adapter
->msix_entries
[i
].vector
,
2372 adapter
->q_vector
[i
]);
2375 ixgbe_reset_q_vectors(adapter
);
2377 free_irq(adapter
->pdev
->irq
, netdev
);
2382 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2383 * @adapter: board private structure
2385 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2387 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2388 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2390 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2391 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2392 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2393 if (adapter
->num_vfs
> 32)
2394 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2396 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2397 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2399 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2400 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2402 synchronize_irq(adapter
->pdev
->irq
);
2407 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2410 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2412 struct ixgbe_hw
*hw
= &adapter
->hw
;
2414 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2415 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2417 ixgbe_set_ivar(adapter
, 0, 0, 0);
2418 ixgbe_set_ivar(adapter
, 1, 0, 0);
2420 map_vector_to_rxq(adapter
, 0, 0);
2421 map_vector_to_txq(adapter
, 0, 0);
2423 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2427 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2428 * @adapter: board private structure
2430 * Configure the Tx unit of the MAC after a reset.
2432 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2435 struct ixgbe_hw
*hw
= &adapter
->hw
;
2436 u32 i
, j
, tdlen
, txctrl
;
2438 /* Setup the HW Tx Head and Tail descriptor pointers */
2439 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
2440 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
2443 tdlen
= ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
2444 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(j
),
2445 (tdba
& DMA_BIT_MASK(32)));
2446 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(j
), (tdba
>> 32));
2447 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(j
), tdlen
);
2448 IXGBE_WRITE_REG(hw
, IXGBE_TDH(j
), 0);
2449 IXGBE_WRITE_REG(hw
, IXGBE_TDT(j
), 0);
2450 adapter
->tx_ring
[i
]->head
= IXGBE_TDH(j
);
2451 adapter
->tx_ring
[i
]->tail
= IXGBE_TDT(j
);
2453 * Disable Tx Head Writeback RO bit, since this hoses
2454 * bookkeeping if things aren't delivered in order.
2456 switch (hw
->mac
.type
) {
2457 case ixgbe_mac_82598EB
:
2458 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(j
));
2460 case ixgbe_mac_82599EB
:
2462 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
));
2465 txctrl
&= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN
;
2466 switch (hw
->mac
.type
) {
2467 case ixgbe_mac_82598EB
:
2468 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(j
), txctrl
);
2470 case ixgbe_mac_82599EB
:
2472 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(j
), txctrl
);
2477 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2481 /* disable the arbiter while setting MTQC */
2482 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2483 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2484 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2486 /* set transmit pool layout */
2487 mask
= (IXGBE_FLAG_SRIOV_ENABLED
| IXGBE_FLAG_DCB_ENABLED
);
2488 switch (adapter
->flags
& mask
) {
2490 case (IXGBE_FLAG_SRIOV_ENABLED
):
2491 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2492 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2495 case (IXGBE_FLAG_DCB_ENABLED
):
2496 /* We enable 8 traffic classes, DCB only */
2497 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2498 (IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
));
2502 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, IXGBE_MTQC_64Q_1PB
);
2506 /* re-eable the arbiter */
2507 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2508 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2512 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2514 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2515 struct ixgbe_ring
*rx_ring
)
2519 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2521 index
= rx_ring
->reg_idx
;
2522 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
2524 mask
= (unsigned long) feature
[RING_F_RSS
].mask
;
2525 index
= index
& mask
;
2527 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(index
));
2529 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2530 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2532 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2533 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2535 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2536 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2537 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2539 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2541 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2543 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2544 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2545 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2548 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(index
), srrctl
);
2551 static u32
ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2556 if (!(adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
2559 mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2560 #ifdef CONFIG_IXGBE_DCB
2561 | IXGBE_FLAG_DCB_ENABLED
2563 | IXGBE_FLAG_SRIOV_ENABLED
2567 case (IXGBE_FLAG_RSS_ENABLED
):
2568 mrqc
= IXGBE_MRQC_RSSEN
;
2570 case (IXGBE_FLAG_SRIOV_ENABLED
):
2571 mrqc
= IXGBE_MRQC_VMDQEN
;
2573 #ifdef CONFIG_IXGBE_DCB
2574 case (IXGBE_FLAG_DCB_ENABLED
):
2575 mrqc
= IXGBE_MRQC_RT8TCEN
;
2577 #endif /* CONFIG_IXGBE_DCB */
2586 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2587 * @adapter: address of board private structure
2588 * @index: index of ring to set
2590 static void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
, int index
)
2592 struct ixgbe_ring
*rx_ring
;
2593 struct ixgbe_hw
*hw
= &adapter
->hw
;
2598 rx_ring
= adapter
->rx_ring
[index
];
2599 j
= rx_ring
->reg_idx
;
2600 rx_buf_len
= rx_ring
->rx_buf_len
;
2601 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(j
));
2602 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
2604 * we must limit the number of descriptors so that the
2605 * total size of max desc * buf_len is not greater
2608 if (rx_ring
->flags
& IXGBE_RING_RX_PS_ENABLED
) {
2609 #if (MAX_SKB_FRAGS > 16)
2610 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2611 #elif (MAX_SKB_FRAGS > 8)
2612 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2613 #elif (MAX_SKB_FRAGS > 4)
2614 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2616 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
2619 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
2620 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
2621 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
2622 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
2624 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
2626 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(j
), rscctrl
);
2630 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
2631 * @adapter: board private structure
2633 * Configure the Rx unit of the MAC after a reset.
2635 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
2638 struct ixgbe_hw
*hw
= &adapter
->hw
;
2639 struct ixgbe_ring
*rx_ring
;
2640 struct net_device
*netdev
= adapter
->netdev
;
2641 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
2643 u32 rdlen
, rxctrl
, rxcsum
;
2644 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2645 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2646 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2648 u32 reta
= 0, mrqc
= 0;
2652 /* Decide whether to use packet split mode or not */
2653 /* Do not use packet split if we're in SR-IOV Mode */
2654 if (!adapter
->num_vfs
)
2655 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
2657 /* Set the RX buffer length according to the mode */
2658 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
2659 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
2660 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2661 /* PSRTYPE must be initialized in 82599 */
2662 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
2663 IXGBE_PSRTYPE_UDPHDR
|
2664 IXGBE_PSRTYPE_IPV4HDR
|
2665 IXGBE_PSRTYPE_IPV6HDR
|
2666 IXGBE_PSRTYPE_L2HDR
;
2668 IXGBE_PSRTYPE(adapter
->num_vfs
),
2672 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
2673 (netdev
->mtu
<= ETH_DATA_LEN
))
2674 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
2676 rx_buf_len
= ALIGN(max_frame
, 1024);
2679 fctrl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_FCTRL
);
2680 fctrl
|= IXGBE_FCTRL_BAM
;
2681 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
2682 fctrl
|= IXGBE_FCTRL_PMCF
;
2683 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_FCTRL
, fctrl
);
2685 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
2686 if (adapter
->netdev
->mtu
<= ETH_DATA_LEN
)
2687 hlreg0
&= ~IXGBE_HLREG0_JUMBOEN
;
2689 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2691 if (netdev
->features
& NETIF_F_FCOE_MTU
)
2692 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
2694 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
2696 rdlen
= adapter
->rx_ring
[0]->count
* sizeof(union ixgbe_adv_rx_desc
);
2697 /* disable receives while setting up the descriptors */
2698 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
2699 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
2702 * Setup the HW Rx Head and Tail Descriptor Pointers and
2703 * the Base and Length of the Rx Descriptor Ring
2705 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2706 rx_ring
= adapter
->rx_ring
[i
];
2707 rdba
= rx_ring
->dma
;
2708 j
= rx_ring
->reg_idx
;
2709 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(j
), (rdba
& DMA_BIT_MASK(32)));
2710 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(j
), (rdba
>> 32));
2711 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(j
), rdlen
);
2712 IXGBE_WRITE_REG(hw
, IXGBE_RDH(j
), 0);
2713 IXGBE_WRITE_REG(hw
, IXGBE_RDT(j
), 0);
2714 rx_ring
->head
= IXGBE_RDH(j
);
2715 rx_ring
->tail
= IXGBE_RDT(j
);
2716 rx_ring
->rx_buf_len
= rx_buf_len
;
2718 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
2719 rx_ring
->flags
|= IXGBE_RING_RX_PS_ENABLED
;
2721 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2724 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
2725 struct ixgbe_ring_feature
*f
;
2726 f
= &adapter
->ring_feature
[RING_F_FCOE
];
2727 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
2728 rx_ring
->flags
&= ~IXGBE_RING_RX_PS_ENABLED
;
2729 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
2730 rx_ring
->rx_buf_len
=
2731 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
2735 #endif /* IXGBE_FCOE */
2736 ixgbe_configure_srrctl(adapter
, rx_ring
);
2739 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
2741 * For VMDq support of different descriptor types or
2742 * buffer sizes through the use of multiple SRRCTL
2743 * registers, RDRXCTL.MVMEN must be set to 1
2745 * also, the manual doesn't mention it clearly but DCA hints
2746 * will only use queue 0's tags unless this bit is set. Side
2747 * effects of setting this bit are only that SRRCTL must be
2748 * fully programmed [0..15]
2750 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2751 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
2752 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2755 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2757 u32 reg_offset
, vf_shift
;
2758 u32 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
2759 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
2760 | IXGBE_VT_CTL_REPLEN
;
2761 vt_reg_bits
|= (adapter
->num_vfs
<<
2762 IXGBE_VT_CTL_POOL_SHIFT
);
2763 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
2764 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, 0);
2766 vf_shift
= adapter
->num_vfs
% 32;
2767 reg_offset
= adapter
->num_vfs
/ 32;
2768 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(0), 0);
2769 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(1), 0);
2770 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(0), 0);
2771 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(1), 0);
2772 /* Enable only the PF's pool for Tx/Rx */
2773 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
2774 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
2775 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
2776 ixgbe_set_vmolr(hw
, adapter
->num_vfs
, true);
2779 /* Program MRQC for the distribution of queues */
2780 mrqc
= ixgbe_setup_mrqc(adapter
);
2782 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
2783 /* Fill out redirection table */
2784 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2785 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2787 /* reta = 4-byte sliding window of
2788 * 0x00..(indices-1)(indices-1)00..etc. */
2789 reta
= (reta
<< 8) | (j
* 0x11);
2791 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2794 /* Fill out hash function seeds */
2795 for (i
= 0; i
< 10; i
++)
2796 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2798 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2799 mrqc
|= IXGBE_MRQC_RSSEN
;
2800 /* Perform hash on these packet types */
2801 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2802 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2803 | IXGBE_MRQC_RSS_FIELD_IPV6
2804 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2806 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2808 if (adapter
->num_vfs
) {
2811 /* Map PF MAC address in RAR Entry 0 to first pool
2813 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
2815 /* Set up VF register offsets for selected VT Mode, i.e.
2816 * 64 VFs for SR-IOV */
2817 reg
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
2818 reg
|= IXGBE_GCR_EXT_SRIOV
;
2819 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, reg
);
2822 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2824 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
||
2825 adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
) {
2826 /* Disable indicating checksum in descriptor, enables
2828 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2830 if (!(rxcsum
& IXGBE_RXCSUM_PCSD
)) {
2831 /* Enable IPv4 payload checksum for UDP fragments
2832 * if PCSD is not set */
2833 rxcsum
|= IXGBE_RXCSUM_IPPCSE
;
2836 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2838 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
2839 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
2840 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
2841 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
2842 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
2845 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
2846 /* Enable 82599 HW-RSC */
2847 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
2848 ixgbe_configure_rscctl(adapter
, i
);
2850 /* Disable RSC for ACK packets */
2851 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
2852 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
2856 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
2858 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2859 struct ixgbe_hw
*hw
= &adapter
->hw
;
2860 int pool_ndx
= adapter
->num_vfs
;
2862 /* add VID to filter table */
2863 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
2866 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
2868 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2869 struct ixgbe_hw
*hw
= &adapter
->hw
;
2870 int pool_ndx
= adapter
->num_vfs
;
2872 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2873 ixgbe_irq_disable(adapter
);
2875 vlan_group_set_device(adapter
->vlgrp
, vid
, NULL
);
2877 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2878 ixgbe_irq_enable(adapter
);
2880 /* remove VID from filter table */
2881 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
2885 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
2886 * @adapter: driver data
2888 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
2890 struct ixgbe_hw
*hw
= &adapter
->hw
;
2891 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2894 switch (hw
->mac
.type
) {
2895 case ixgbe_mac_82598EB
:
2896 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2897 #ifdef CONFIG_IXGBE_DCB
2898 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
2899 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
2901 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2902 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2904 case ixgbe_mac_82599EB
:
2905 vlnctrl
&= ~IXGBE_VLNCTRL_VFE
;
2906 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2907 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2908 #ifdef CONFIG_IXGBE_DCB
2909 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
2912 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2913 j
= adapter
->rx_ring
[i
]->reg_idx
;
2914 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2915 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
2916 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2925 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
2926 * @adapter: driver data
2928 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
2930 struct ixgbe_hw
*hw
= &adapter
->hw
;
2931 u32 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
2934 switch (hw
->mac
.type
) {
2935 case ixgbe_mac_82598EB
:
2936 vlnctrl
|= IXGBE_VLNCTRL_VME
| IXGBE_VLNCTRL_VFE
;
2937 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2938 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2940 case ixgbe_mac_82599EB
:
2941 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
2942 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
2943 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
2944 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
2945 j
= adapter
->rx_ring
[i
]->reg_idx
;
2946 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
2947 vlnctrl
|= IXGBE_RXDCTL_VME
;
2948 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
2956 static void ixgbe_vlan_rx_register(struct net_device
*netdev
,
2957 struct vlan_group
*grp
)
2959 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2961 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2962 ixgbe_irq_disable(adapter
);
2963 adapter
->vlgrp
= grp
;
2966 * For a DCB driver, always enable VLAN tag stripping so we can
2967 * still receive traffic from a DCB-enabled host even if we're
2970 ixgbe_vlan_filter_enable(adapter
);
2972 ixgbe_vlan_rx_add_vid(netdev
, 0);
2974 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2975 ixgbe_irq_enable(adapter
);
2978 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
2980 ixgbe_vlan_rx_register(adapter
->netdev
, adapter
->vlgrp
);
2982 if (adapter
->vlgrp
) {
2984 for (vid
= 0; vid
< VLAN_GROUP_ARRAY_LEN
; vid
++) {
2985 if (!vlan_group_get_device(adapter
->vlgrp
, vid
))
2987 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
2993 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
2994 * @netdev: network interface device structure
2996 * Writes unicast address list to the RAR table.
2997 * Returns: -ENOMEM on failure/insufficient address space
2998 * 0 on no addresses written
2999 * X on writing X addresses to the RAR table
3001 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3003 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3004 struct ixgbe_hw
*hw
= &adapter
->hw
;
3005 unsigned int vfn
= adapter
->num_vfs
;
3006 unsigned int rar_entries
= hw
->mac
.num_rar_entries
- (vfn
+ 1);
3009 /* return ENOMEM indicating insufficient memory for addresses */
3010 if (netdev_uc_count(netdev
) > rar_entries
)
3013 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3014 struct netdev_hw_addr
*ha
;
3015 /* return error if we do not support writing to RAR table */
3016 if (!hw
->mac
.ops
.set_rar
)
3019 netdev_for_each_uc_addr(ha
, netdev
) {
3022 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3027 /* write the addresses in reverse order to avoid write combining */
3028 for (; rar_entries
> 0 ; rar_entries
--)
3029 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3035 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3036 * @netdev: network interface device structure
3038 * The set_rx_method entry point is called whenever the unicast/multicast
3039 * address list or the network interface flags are updated. This routine is
3040 * responsible for configuring the hardware for proper unicast, multicast and
3043 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3045 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3046 struct ixgbe_hw
*hw
= &adapter
->hw
;
3047 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3050 /* Check for Promiscuous and All Multicast modes */
3052 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3054 /* clear the bits we are changing the status of */
3055 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3057 if (netdev
->flags
& IFF_PROMISC
) {
3058 hw
->addr_ctrl
.user_set_promisc
= true;
3059 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3060 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3061 /* don't hardware filter vlans in promisc mode */
3062 ixgbe_vlan_filter_disable(adapter
);
3064 if (netdev
->flags
& IFF_ALLMULTI
) {
3065 fctrl
|= IXGBE_FCTRL_MPE
;
3066 vmolr
|= IXGBE_VMOLR_MPE
;
3069 * Write addresses to the MTA, if the attempt fails
3070 * then we should just turn on promiscous mode so
3071 * that we can at least receive multicast traffic
3073 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3074 vmolr
|= IXGBE_VMOLR_ROMPE
;
3076 ixgbe_vlan_filter_enable(adapter
);
3077 hw
->addr_ctrl
.user_set_promisc
= false;
3079 * Write addresses to available RAR registers, if there is not
3080 * sufficient space to store all the addresses then enable
3081 * unicast promiscous mode
3083 count
= ixgbe_write_uc_addr_list(netdev
);
3085 fctrl
|= IXGBE_FCTRL_UPE
;
3086 vmolr
|= IXGBE_VMOLR_ROPE
;
3090 if (adapter
->num_vfs
) {
3091 ixgbe_restore_vf_multicasts(adapter
);
3092 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3093 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3095 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3098 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3101 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3104 struct ixgbe_q_vector
*q_vector
;
3105 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3107 /* legacy and MSI only use one vector */
3108 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3111 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3112 struct napi_struct
*napi
;
3113 q_vector
= adapter
->q_vector
[q_idx
];
3114 napi
= &q_vector
->napi
;
3115 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3116 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3117 if (q_vector
->txr_count
== 1)
3118 napi
->poll
= &ixgbe_clean_txonly
;
3119 else if (q_vector
->rxr_count
== 1)
3120 napi
->poll
= &ixgbe_clean_rxonly
;
3128 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3131 struct ixgbe_q_vector
*q_vector
;
3132 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3134 /* legacy and MSI only use one vector */
3135 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3138 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3139 q_vector
= adapter
->q_vector
[q_idx
];
3140 napi_disable(&q_vector
->napi
);
3144 #ifdef CONFIG_IXGBE_DCB
3146 * ixgbe_configure_dcb - Configure DCB hardware
3147 * @adapter: ixgbe adapter struct
3149 * This is called by the driver on open to configure the DCB hardware.
3150 * This is also called by the gennetlink interface when reconfiguring
3153 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3155 struct ixgbe_hw
*hw
= &adapter
->hw
;
3159 ixgbe_dcb_check_config(&adapter
->dcb_cfg
);
3160 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_TX_CONFIG
);
3161 ixgbe_dcb_calculate_tc_credits(&adapter
->dcb_cfg
, DCB_RX_CONFIG
);
3163 /* reconfigure the hardware */
3164 ixgbe_dcb_hw_config(&adapter
->hw
, &adapter
->dcb_cfg
);
3166 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3167 j
= adapter
->tx_ring
[i
]->reg_idx
;
3168 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3169 /* PThresh workaround for Tx hang with DFP enabled. */
3171 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3173 /* Enable VLAN tag insert/strip */
3174 ixgbe_vlan_filter_enable(adapter
);
3176 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3180 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3182 struct net_device
*netdev
= adapter
->netdev
;
3183 struct ixgbe_hw
*hw
= &adapter
->hw
;
3186 ixgbe_set_rx_mode(netdev
);
3188 ixgbe_restore_vlan(adapter
);
3189 #ifdef CONFIG_IXGBE_DCB
3190 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3191 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3192 netif_set_gso_max_size(netdev
, 32768);
3194 netif_set_gso_max_size(netdev
, 65536);
3195 ixgbe_configure_dcb(adapter
);
3197 netif_set_gso_max_size(netdev
, 65536);
3200 netif_set_gso_max_size(netdev
, 65536);
3204 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3205 ixgbe_configure_fcoe(adapter
);
3207 #endif /* IXGBE_FCOE */
3208 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3209 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3210 adapter
->tx_ring
[i
]->atr_sample_rate
=
3211 adapter
->atr_sample_rate
;
3212 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3213 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3214 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3217 ixgbe_configure_tx(adapter
);
3218 ixgbe_configure_rx(adapter
);
3219 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3220 ixgbe_alloc_rx_buffers(adapter
, adapter
->rx_ring
[i
],
3221 (adapter
->rx_ring
[i
]->count
- 1));
3224 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3226 switch (hw
->phy
.type
) {
3227 case ixgbe_phy_sfp_avago
:
3228 case ixgbe_phy_sfp_ftl
:
3229 case ixgbe_phy_sfp_intel
:
3230 case ixgbe_phy_sfp_unknown
:
3231 case ixgbe_phy_sfp_passive_tyco
:
3232 case ixgbe_phy_sfp_passive_unknown
:
3233 case ixgbe_phy_sfp_active_unknown
:
3234 case ixgbe_phy_sfp_ftl_active
:
3242 * ixgbe_sfp_link_config - set up SFP+ link
3243 * @adapter: pointer to private adapter struct
3245 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3247 struct ixgbe_hw
*hw
= &adapter
->hw
;
3249 if (hw
->phy
.multispeed_fiber
) {
3251 * In multispeed fiber setups, the device may not have
3252 * had a physical connection when the driver loaded.
3253 * If that's the case, the initial link configuration
3254 * couldn't get the MAC into 10G or 1G mode, so we'll
3255 * never have a link status change interrupt fire.
3256 * We need to try and force an autonegotiation
3257 * session, then bring up link.
3259 hw
->mac
.ops
.setup_sfp(hw
);
3260 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
3261 schedule_work(&adapter
->multispeed_fiber_task
);
3264 * Direct Attach Cu and non-multispeed fiber modules
3265 * still need to be configured properly prior to
3268 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_MOD_TASK
))
3269 schedule_work(&adapter
->sfp_config_module_task
);
3274 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3275 * @hw: pointer to private hardware struct
3277 * Returns 0 on success, negative on failure
3279 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3282 bool negotiation
, link_up
= false;
3283 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3285 if (hw
->mac
.ops
.check_link
)
3286 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3291 if (hw
->mac
.ops
.get_link_capabilities
)
3292 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
3296 if (hw
->mac
.ops
.setup_link
)
3297 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3302 #define IXGBE_MAX_RX_DESC_POLL 10
3303 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3306 int j
= adapter
->rx_ring
[rxr
]->reg_idx
;
3309 for (k
= 0; k
< IXGBE_MAX_RX_DESC_POLL
; k
++) {
3310 if (IXGBE_READ_REG(&adapter
->hw
,
3311 IXGBE_RXDCTL(j
)) & IXGBE_RXDCTL_ENABLE
)
3316 if (k
>= IXGBE_MAX_RX_DESC_POLL
) {
3317 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3318 "the polling period\n", rxr
);
3320 ixgbe_release_rx_desc(&adapter
->hw
, adapter
->rx_ring
[rxr
],
3321 (adapter
->rx_ring
[rxr
]->count
- 1));
3324 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3326 struct net_device
*netdev
= adapter
->netdev
;
3327 struct ixgbe_hw
*hw
= &adapter
->hw
;
3329 int num_rx_rings
= adapter
->num_rx_queues
;
3331 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3332 u32 txdctl
, rxdctl
, mhadd
;
3337 ixgbe_get_hw_control(adapter
);
3339 if ((adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) ||
3340 (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
)) {
3341 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3342 gpie
= (IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_EIAME
|
3343 IXGBE_GPIE_PBA_SUPPORT
| IXGBE_GPIE_OCD
);
3348 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3349 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3350 gpie
|= IXGBE_GPIE_VTMODE_64
;
3352 /* XXX: to interrupt immediately for EICS writes, enable this */
3353 /* gpie |= IXGBE_GPIE_EIMEN; */
3354 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3357 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3359 * use EIAM to auto-mask when MSI-X interrupt is asserted
3360 * this saves a register write for every interrupt
3362 switch (hw
->mac
.type
) {
3363 case ixgbe_mac_82598EB
:
3364 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3367 case ixgbe_mac_82599EB
:
3368 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3369 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3373 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3374 * specifically only auto mask tx and rx interrupts */
3375 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3378 /* Enable Thermal over heat sensor interrupt */
3379 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) {
3380 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3381 gpie
|= IXGBE_SDP0_GPIEN
;
3382 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3385 /* Enable fan failure interrupt if media type is copper */
3386 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3387 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3388 gpie
|= IXGBE_SDP1_GPIEN
;
3389 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3392 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3393 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
3394 gpie
|= IXGBE_SDP1_GPIEN
;
3395 gpie
|= IXGBE_SDP2_GPIEN
;
3396 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3400 /* adjust max frame to be able to do baby jumbo for FCoE */
3401 if ((netdev
->features
& NETIF_F_FCOE_MTU
) &&
3402 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3403 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3405 #endif /* IXGBE_FCOE */
3406 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3407 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3408 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3409 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3411 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3414 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3415 j
= adapter
->tx_ring
[i
]->reg_idx
;
3416 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3417 if (adapter
->rx_itr_setting
== 0) {
3418 /* cannot set wthresh when itr==0 */
3419 txdctl
&= ~0x007F0000;
3421 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
3422 txdctl
|= (8 << 16);
3424 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3427 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3428 /* DMATXCTL.EN must be set after all Tx queue config is done */
3429 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
3430 dmatxctl
|= IXGBE_DMATXCTL_TE
;
3431 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
3433 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3434 j
= adapter
->tx_ring
[i
]->reg_idx
;
3435 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3436 txdctl
|= IXGBE_TXDCTL_ENABLE
;
3437 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
), txdctl
);
3438 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3440 /* poll for Tx Enable ready */
3443 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3444 } while (--wait_loop
&&
3445 !(txdctl
& IXGBE_TXDCTL_ENABLE
));
3447 e_err(drv
, "Could not enable Tx Queue %d\n", j
);
3451 for (i
= 0; i
< num_rx_rings
; i
++) {
3452 j
= adapter
->rx_ring
[i
]->reg_idx
;
3453 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3454 /* enable PTHRESH=32 descriptors (half the internal cache)
3455 * and HTHRESH=0 descriptors (to minimize latency on fetch),
3456 * this also removes a pesky rx_no_buffer_count increment */
3458 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3459 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), rxdctl
);
3460 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3461 ixgbe_rx_desc_queue_enable(adapter
, i
);
3463 /* enable all receives */
3464 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3465 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3466 rxdctl
|= (IXGBE_RXCTRL_DMBYPS
| IXGBE_RXCTRL_RXEN
);
3468 rxdctl
|= IXGBE_RXCTRL_RXEN
;
3469 hw
->mac
.ops
.enable_rx_dma(hw
, rxdctl
);
3471 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3472 ixgbe_configure_msix(adapter
);
3474 ixgbe_configure_msi_and_legacy(adapter
);
3476 /* enable the optics */
3477 if (hw
->phy
.multispeed_fiber
)
3478 hw
->mac
.ops
.enable_tx_laser(hw
);
3480 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3481 ixgbe_napi_enable_all(adapter
);
3483 /* clear any pending interrupts, may auto mask */
3484 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3486 ixgbe_irq_enable(adapter
);
3489 * If this adapter has a fan, check to see if we had a failure
3490 * before we enabled the interrupt.
3492 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3493 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3494 if (esdp
& IXGBE_ESDP_SDP1
)
3495 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3499 * For hot-pluggable SFP+ devices, a new SFP+ module may have
3500 * arrived before interrupts were enabled but after probe. Such
3501 * devices wouldn't have their type identified yet. We need to
3502 * kick off the SFP+ module setup first, then try to bring up link.
3503 * If we're not hot-pluggable SFP+, we just need to configure link
3506 if (hw
->phy
.type
== ixgbe_phy_unknown
) {
3507 err
= hw
->phy
.ops
.identify(hw
);
3508 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
3510 * Take the device down and schedule the sfp tasklet
3511 * which will unregister_netdev and log it.
3513 ixgbe_down(adapter
);
3514 schedule_work(&adapter
->sfp_config_module_task
);
3519 if (ixgbe_is_sfp(hw
)) {
3520 ixgbe_sfp_link_config(adapter
);
3522 err
= ixgbe_non_sfp_link_config(hw
);
3524 e_err(probe
, "link_config FAILED %d\n", err
);
3527 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3528 set_bit(__IXGBE_FDIR_INIT_DONE
,
3529 &(adapter
->tx_ring
[i
]->reinit_state
));
3531 /* enable transmits */
3532 netif_tx_start_all_queues(netdev
);
3534 /* bring the link up in the watchdog, this could race with our first
3535 * link up interrupt but shouldn't be a problem */
3536 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3537 adapter
->link_check_timeout
= jiffies
;
3538 mod_timer(&adapter
->watchdog_timer
, jiffies
);
3540 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3541 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
3542 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
3543 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
3548 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
3550 WARN_ON(in_interrupt());
3551 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
3553 ixgbe_down(adapter
);
3555 * If SR-IOV enabled then wait a bit before bringing the adapter
3556 * back up to give the VFs time to respond to the reset. The
3557 * two second wait is based upon the watchdog timer cycle in
3560 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
3563 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
3566 int ixgbe_up(struct ixgbe_adapter
*adapter
)
3568 /* hardware has been reset, we need to reload some things */
3569 ixgbe_configure(adapter
);
3571 return ixgbe_up_complete(adapter
);
3574 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
3576 struct ixgbe_hw
*hw
= &adapter
->hw
;
3579 err
= hw
->mac
.ops
.init_hw(hw
);
3582 case IXGBE_ERR_SFP_NOT_PRESENT
:
3584 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
3585 e_dev_err("master disable timed out\n");
3587 case IXGBE_ERR_EEPROM_VERSION
:
3588 /* We are running on a pre-production device, log a warning */
3589 e_dev_warn("This device is a pre-production adapter/LOM. "
3590 "Please be aware there may be issuesassociated with "
3591 "your hardware. If you are experiencing problems "
3592 "please contact your Intel or hardware "
3593 "representative who provided you with this "
3597 e_dev_err("Hardware Error: %d\n", err
);
3600 /* reprogram the RAR[0] in case user changed it. */
3601 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
3606 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
3607 * @adapter: board private structure
3608 * @rx_ring: ring to free buffers from
3610 static void ixgbe_clean_rx_ring(struct ixgbe_adapter
*adapter
,
3611 struct ixgbe_ring
*rx_ring
)
3613 struct pci_dev
*pdev
= adapter
->pdev
;
3617 /* Free all the Rx ring sk_buffs */
3619 for (i
= 0; i
< rx_ring
->count
; i
++) {
3620 struct ixgbe_rx_buffer
*rx_buffer_info
;
3622 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
3623 if (rx_buffer_info
->dma
) {
3624 dma_unmap_single(&pdev
->dev
, rx_buffer_info
->dma
,
3625 rx_ring
->rx_buf_len
,
3627 rx_buffer_info
->dma
= 0;
3629 if (rx_buffer_info
->skb
) {
3630 struct sk_buff
*skb
= rx_buffer_info
->skb
;
3631 rx_buffer_info
->skb
= NULL
;
3633 struct sk_buff
*this = skb
;
3634 if (IXGBE_RSC_CB(this)->delay_unmap
) {
3635 dma_unmap_single(&pdev
->dev
,
3636 IXGBE_RSC_CB(this)->dma
,
3637 rx_ring
->rx_buf_len
,
3639 IXGBE_RSC_CB(this)->dma
= 0;
3640 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
3643 dev_kfree_skb(this);
3646 if (!rx_buffer_info
->page
)
3648 if (rx_buffer_info
->page_dma
) {
3649 dma_unmap_page(&pdev
->dev
, rx_buffer_info
->page_dma
,
3650 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
3651 rx_buffer_info
->page_dma
= 0;
3653 put_page(rx_buffer_info
->page
);
3654 rx_buffer_info
->page
= NULL
;
3655 rx_buffer_info
->page_offset
= 0;
3658 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
3659 memset(rx_ring
->rx_buffer_info
, 0, size
);
3661 /* Zero out the descriptor ring */
3662 memset(rx_ring
->desc
, 0, rx_ring
->size
);
3664 rx_ring
->next_to_clean
= 0;
3665 rx_ring
->next_to_use
= 0;
3668 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->head
);
3670 writel(0, adapter
->hw
.hw_addr
+ rx_ring
->tail
);
3674 * ixgbe_clean_tx_ring - Free Tx Buffers
3675 * @adapter: board private structure
3676 * @tx_ring: ring to be cleaned
3678 static void ixgbe_clean_tx_ring(struct ixgbe_adapter
*adapter
,
3679 struct ixgbe_ring
*tx_ring
)
3681 struct ixgbe_tx_buffer
*tx_buffer_info
;
3685 /* Free all the Tx ring sk_buffs */
3687 for (i
= 0; i
< tx_ring
->count
; i
++) {
3688 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
3689 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
3692 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
3693 memset(tx_ring
->tx_buffer_info
, 0, size
);
3695 /* Zero out the descriptor ring */
3696 memset(tx_ring
->desc
, 0, tx_ring
->size
);
3698 tx_ring
->next_to_use
= 0;
3699 tx_ring
->next_to_clean
= 0;
3702 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->head
);
3704 writel(0, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
3708 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
3709 * @adapter: board private structure
3711 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
3715 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3716 ixgbe_clean_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3720 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
3721 * @adapter: board private structure
3723 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
3727 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3728 ixgbe_clean_tx_ring(adapter
, adapter
->tx_ring
[i
]);
3731 void ixgbe_down(struct ixgbe_adapter
*adapter
)
3733 struct net_device
*netdev
= adapter
->netdev
;
3734 struct ixgbe_hw
*hw
= &adapter
->hw
;
3739 /* signal that we are down to the interrupt handler */
3740 set_bit(__IXGBE_DOWN
, &adapter
->state
);
3742 /* disable receive for all VFs and wait one second */
3743 if (adapter
->num_vfs
) {
3744 /* ping all the active vfs to let them know we are going down */
3745 ixgbe_ping_all_vfs(adapter
);
3747 /* Disable all VFTE/VFRE TX/RX */
3748 ixgbe_disable_tx_rx(adapter
);
3750 /* Mark all the VFs as inactive */
3751 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
3752 adapter
->vfinfo
[i
].clear_to_send
= 0;
3755 /* disable receives */
3756 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3757 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3759 IXGBE_WRITE_FLUSH(hw
);
3762 netif_tx_stop_all_queues(netdev
);
3764 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
3765 del_timer_sync(&adapter
->sfp_timer
);
3766 del_timer_sync(&adapter
->watchdog_timer
);
3767 cancel_work_sync(&adapter
->watchdog_task
);
3769 netif_carrier_off(netdev
);
3770 netif_tx_disable(netdev
);
3772 ixgbe_irq_disable(adapter
);
3774 ixgbe_napi_disable_all(adapter
);
3776 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3777 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3778 cancel_work_sync(&adapter
->fdir_reinit_task
);
3780 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
3781 cancel_work_sync(&adapter
->check_overtemp_task
);
3783 /* disable transmits in the hardware now that interrupts are off */
3784 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
3785 j
= adapter
->tx_ring
[i
]->reg_idx
;
3786 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(j
));
3787 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(j
),
3788 (txdctl
& ~IXGBE_TXDCTL_ENABLE
));
3790 /* Disable the Tx DMA engine on 82599 */
3791 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3792 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
3793 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
3794 ~IXGBE_DMATXCTL_TE
));
3796 /* power down the optics */
3797 if (hw
->phy
.multispeed_fiber
)
3798 hw
->mac
.ops
.disable_tx_laser(hw
);
3800 /* clear n-tuple filters that are cached */
3801 ethtool_ntuple_flush(netdev
);
3803 if (!pci_channel_offline(adapter
->pdev
))
3804 ixgbe_reset(adapter
);
3805 ixgbe_clean_all_tx_rings(adapter
);
3806 ixgbe_clean_all_rx_rings(adapter
);
3808 #ifdef CONFIG_IXGBE_DCA
3809 /* since we reset the hardware DCA settings were cleared */
3810 ixgbe_setup_dca(adapter
);
3815 * ixgbe_poll - NAPI Rx polling callback
3816 * @napi: structure for representing this polling device
3817 * @budget: how many packets driver is allowed to clean
3819 * This function is used for legacy and MSI, NAPI mode
3821 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
3823 struct ixgbe_q_vector
*q_vector
=
3824 container_of(napi
, struct ixgbe_q_vector
, napi
);
3825 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
3826 int tx_clean_complete
, work_done
= 0;
3828 #ifdef CONFIG_IXGBE_DCA
3829 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
3830 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[0]);
3831 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[0]);
3835 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
3836 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
3838 if (!tx_clean_complete
)
3841 /* If budget not fully consumed, exit the polling mode */
3842 if (work_done
< budget
) {
3843 napi_complete(napi
);
3844 if (adapter
->rx_itr_setting
& 1)
3845 ixgbe_set_itr(adapter
);
3846 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
3847 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
3853 * ixgbe_tx_timeout - Respond to a Tx Hang
3854 * @netdev: network interface device structure
3856 static void ixgbe_tx_timeout(struct net_device
*netdev
)
3858 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3860 /* Do the reset outside of interrupt context */
3861 schedule_work(&adapter
->reset_task
);
3864 static void ixgbe_reset_task(struct work_struct
*work
)
3866 struct ixgbe_adapter
*adapter
;
3867 adapter
= container_of(work
, struct ixgbe_adapter
, reset_task
);
3869 /* If we're already down or resetting, just bail */
3870 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
3871 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
3874 adapter
->tx_timeout_count
++;
3876 ixgbe_dump(adapter
);
3877 netdev_err(adapter
->netdev
, "Reset adapter\n");
3878 ixgbe_reinit_locked(adapter
);
3881 #ifdef CONFIG_IXGBE_DCB
3882 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
3885 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_DCB
];
3887 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
3891 adapter
->num_rx_queues
= f
->indices
;
3892 adapter
->num_tx_queues
= f
->indices
;
3900 * ixgbe_set_rss_queues: Allocate queues for RSS
3901 * @adapter: board private structure to initialize
3903 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
3904 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3907 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
3910 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
3912 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3914 adapter
->num_rx_queues
= f
->indices
;
3915 adapter
->num_tx_queues
= f
->indices
;
3925 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3926 * @adapter: board private structure to initialize
3928 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3929 * to the original CPU that initiated the Tx session. This runs in addition
3930 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3931 * Rx load across CPUs using RSS.
3934 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
3937 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
3939 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
3942 /* Flow Director must have RSS enabled */
3943 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
3944 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3945 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
3946 adapter
->num_tx_queues
= f_fdir
->indices
;
3947 adapter
->num_rx_queues
= f_fdir
->indices
;
3950 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
3951 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
3958 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3959 * @adapter: board private structure to initialize
3961 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3962 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3963 * rx queues out of the max number of rx queues, instead, it is used as the
3964 * index of the first rx queue used by FCoE.
3967 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
3970 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
3972 f
->indices
= min((int)num_online_cpus(), f
->indices
);
3973 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
3974 adapter
->num_rx_queues
= 1;
3975 adapter
->num_tx_queues
= 1;
3976 #ifdef CONFIG_IXGBE_DCB
3977 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
3978 e_info(probe
, "FCoE enabled with DCB\n");
3979 ixgbe_set_dcb_queues(adapter
);
3982 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
3983 e_info(probe
, "FCoE enabled with RSS\n");
3984 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
3985 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
3986 ixgbe_set_fdir_queues(adapter
);
3988 ixgbe_set_rss_queues(adapter
);
3990 /* adding FCoE rx rings to the end */
3991 f
->mask
= adapter
->num_rx_queues
;
3992 adapter
->num_rx_queues
+= f
->indices
;
3993 adapter
->num_tx_queues
+= f
->indices
;
4001 #endif /* IXGBE_FCOE */
4003 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4004 * @adapter: board private structure to initialize
4006 * IOV doesn't actually use anything, so just NAK the
4007 * request for now and let the other queue routines
4008 * figure out what to do.
4010 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4016 * ixgbe_set_num_queues: Allocate queues for device, feature dependant
4017 * @adapter: board private structure to initialize
4019 * This is the top level queue allocation routine. The order here is very
4020 * important, starting with the "most" number of features turned on at once,
4021 * and ending with the smallest set of features. This way large combinations
4022 * can be allocated if they're turned on, and smaller combinations are the
4023 * fallthrough conditions.
4026 static void ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4028 /* Start with base case */
4029 adapter
->num_rx_queues
= 1;
4030 adapter
->num_tx_queues
= 1;
4031 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4032 adapter
->num_rx_queues_per_pool
= 1;
4034 if (ixgbe_set_sriov_queues(adapter
))
4038 if (ixgbe_set_fcoe_queues(adapter
))
4041 #endif /* IXGBE_FCOE */
4042 #ifdef CONFIG_IXGBE_DCB
4043 if (ixgbe_set_dcb_queues(adapter
))
4047 if (ixgbe_set_fdir_queues(adapter
))
4050 if (ixgbe_set_rss_queues(adapter
))
4053 /* fallback to base case */
4054 adapter
->num_rx_queues
= 1;
4055 adapter
->num_tx_queues
= 1;
4058 /* Notify the stack of the (possibly) reduced Tx Queue count. */
4059 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4062 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4065 int err
, vector_threshold
;
4067 /* We'll want at least 3 (vector_threshold):
4070 * 3) Other (Link Status Change, etc.)
4071 * 4) TCP Timer (optional)
4073 vector_threshold
= MIN_MSIX_COUNT
;
4075 /* The more we get, the more we will assign to Tx/Rx Cleanup
4076 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4077 * Right now, we simply care about how many we'll get; we'll
4078 * set them up later while requesting irq's.
4080 while (vectors
>= vector_threshold
) {
4081 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4083 if (!err
) /* Success in acquiring all requested vectors. */
4086 vectors
= 0; /* Nasty failure, quit now */
4087 else /* err == number of vectors we should try again with */
4091 if (vectors
< vector_threshold
) {
4092 /* Can't allocate enough MSI-X interrupts? Oh well.
4093 * This just means we'll go with either a single MSI
4094 * vector or fall back to legacy interrupts.
4096 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4097 "Unable to allocate MSI-X interrupts\n");
4098 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4099 kfree(adapter
->msix_entries
);
4100 adapter
->msix_entries
= NULL
;
4102 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4104 * Adjust for only the vectors we'll use, which is minimum
4105 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4106 * vectors we were allocated.
4108 adapter
->num_msix_vectors
= min(vectors
,
4109 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4114 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4115 * @adapter: board private structure to initialize
4117 * Cache the descriptor ring offsets for RSS to the assigned rings.
4120 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4125 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4126 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4127 adapter
->rx_ring
[i
]->reg_idx
= i
;
4128 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4129 adapter
->tx_ring
[i
]->reg_idx
= i
;
4138 #ifdef CONFIG_IXGBE_DCB
4140 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4141 * @adapter: board private structure to initialize
4143 * Cache the descriptor ring offsets for DCB to the assigned rings.
4146 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4150 int dcb_i
= adapter
->ring_feature
[RING_F_DCB
].indices
;
4152 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4153 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
) {
4154 /* the number of queues is assumed to be symmetric */
4155 for (i
= 0; i
< dcb_i
; i
++) {
4156 adapter
->rx_ring
[i
]->reg_idx
= i
<< 3;
4157 adapter
->tx_ring
[i
]->reg_idx
= i
<< 2;
4160 } else if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
) {
4163 * Tx TC0 starts at: descriptor queue 0
4164 * Tx TC1 starts at: descriptor queue 32
4165 * Tx TC2 starts at: descriptor queue 64
4166 * Tx TC3 starts at: descriptor queue 80
4167 * Tx TC4 starts at: descriptor queue 96
4168 * Tx TC5 starts at: descriptor queue 104
4169 * Tx TC6 starts at: descriptor queue 112
4170 * Tx TC7 starts at: descriptor queue 120
4172 * Rx TC0-TC7 are offset by 16 queues each
4174 for (i
= 0; i
< 3; i
++) {
4175 adapter
->tx_ring
[i
]->reg_idx
= i
<< 5;
4176 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4178 for ( ; i
< 5; i
++) {
4179 adapter
->tx_ring
[i
]->reg_idx
=
4181 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4183 for ( ; i
< dcb_i
; i
++) {
4184 adapter
->tx_ring
[i
]->reg_idx
=
4186 adapter
->rx_ring
[i
]->reg_idx
= i
<< 4;
4190 } else if (dcb_i
== 4) {
4192 * Tx TC0 starts at: descriptor queue 0
4193 * Tx TC1 starts at: descriptor queue 64
4194 * Tx TC2 starts at: descriptor queue 96
4195 * Tx TC3 starts at: descriptor queue 112
4197 * Rx TC0-TC3 are offset by 32 queues each
4199 adapter
->tx_ring
[0]->reg_idx
= 0;
4200 adapter
->tx_ring
[1]->reg_idx
= 64;
4201 adapter
->tx_ring
[2]->reg_idx
= 96;
4202 adapter
->tx_ring
[3]->reg_idx
= 112;
4203 for (i
= 0 ; i
< dcb_i
; i
++)
4204 adapter
->rx_ring
[i
]->reg_idx
= i
<< 5;
4222 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4223 * @adapter: board private structure to initialize
4225 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4228 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4233 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4234 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4235 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4236 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4237 adapter
->rx_ring
[i
]->reg_idx
= i
;
4238 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4239 adapter
->tx_ring
[i
]->reg_idx
= i
;
4248 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4249 * @adapter: board private structure to initialize
4251 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4254 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4256 int i
, fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4258 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4260 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4261 #ifdef CONFIG_IXGBE_DCB
4262 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
4263 struct ixgbe_fcoe
*fcoe
= &adapter
->fcoe
;
4265 ixgbe_cache_ring_dcb(adapter
);
4266 /* find out queues in TC for FCoE */
4267 fcoe_rx_i
= adapter
->rx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4268 fcoe_tx_i
= adapter
->tx_ring
[fcoe
->tc
]->reg_idx
+ 1;
4270 * In 82599, the number of Tx queues for each traffic
4271 * class for both 8-TC and 4-TC modes are:
4272 * TCs : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
4273 * 8 TCs: 32 32 16 16 8 8 8 8
4274 * 4 TCs: 64 64 32 32
4275 * We have max 8 queues for FCoE, where 8 the is
4276 * FCoE redirection table size. If TC for FCoE is
4277 * less than or equal to TC3, we have enough queues
4278 * to add max of 8 queues for FCoE, so we start FCoE
4279 * tx descriptor from the next one, i.e., reg_idx + 1.
4280 * If TC for FCoE is above TC3, implying 8 TC mode,
4281 * and we need 8 for FCoE, we have to take all queues
4282 * in that traffic class for FCoE.
4284 if ((f
->indices
== IXGBE_FCRETA_SIZE
) && (fcoe
->tc
> 3))
4287 #endif /* CONFIG_IXGBE_DCB */
4288 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4289 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4290 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4291 ixgbe_cache_ring_fdir(adapter
);
4293 ixgbe_cache_ring_rss(adapter
);
4295 fcoe_rx_i
= f
->mask
;
4296 fcoe_tx_i
= f
->mask
;
4298 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4299 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4300 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4307 #endif /* IXGBE_FCOE */
4309 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4310 * @adapter: board private structure to initialize
4312 * SR-IOV doesn't use any descriptor rings but changes the default if
4313 * no other mapping is used.
4316 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4318 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4319 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4320 if (adapter
->num_vfs
)
4327 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4328 * @adapter: board private structure to initialize
4330 * Once we know the feature-set enabled for the device, we'll cache
4331 * the register offset the descriptor ring is assigned to.
4333 * Note, the order the various feature calls is important. It must start with
4334 * the "most" features enabled at the same time, then trickle down to the
4335 * least amount of features turned on at once.
4337 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4339 /* start with default case */
4340 adapter
->rx_ring
[0]->reg_idx
= 0;
4341 adapter
->tx_ring
[0]->reg_idx
= 0;
4343 if (ixgbe_cache_ring_sriov(adapter
))
4347 if (ixgbe_cache_ring_fcoe(adapter
))
4350 #endif /* IXGBE_FCOE */
4351 #ifdef CONFIG_IXGBE_DCB
4352 if (ixgbe_cache_ring_dcb(adapter
))
4356 if (ixgbe_cache_ring_fdir(adapter
))
4359 if (ixgbe_cache_ring_rss(adapter
))
4364 * ixgbe_alloc_queues - Allocate memory for all rings
4365 * @adapter: board private structure to initialize
4367 * We allocate one ring per queue at run-time since we don't know the
4368 * number of queues at compile-time. The polling_netdev array is
4369 * intended for Multiqueue, but should work fine with a single queue.
4371 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4374 int orig_node
= adapter
->node
;
4376 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4377 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
4378 if (orig_node
== -1) {
4379 int cur_node
= next_online_node(adapter
->node
);
4380 if (cur_node
== MAX_NUMNODES
)
4381 cur_node
= first_online_node
;
4382 adapter
->node
= cur_node
;
4384 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4387 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4389 goto err_tx_ring_allocation
;
4390 ring
->count
= adapter
->tx_ring_count
;
4391 ring
->queue_index
= i
;
4392 ring
->numa_node
= adapter
->node
;
4394 adapter
->tx_ring
[i
] = ring
;
4397 /* Restore the adapter's original node */
4398 adapter
->node
= orig_node
;
4400 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4401 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
4402 if (orig_node
== -1) {
4403 int cur_node
= next_online_node(adapter
->node
);
4404 if (cur_node
== MAX_NUMNODES
)
4405 cur_node
= first_online_node
;
4406 adapter
->node
= cur_node
;
4408 ring
= kzalloc_node(sizeof(struct ixgbe_ring
), GFP_KERNEL
,
4411 ring
= kzalloc(sizeof(struct ixgbe_ring
), GFP_KERNEL
);
4413 goto err_rx_ring_allocation
;
4414 ring
->count
= adapter
->rx_ring_count
;
4415 ring
->queue_index
= i
;
4416 ring
->numa_node
= adapter
->node
;
4418 adapter
->rx_ring
[i
] = ring
;
4421 /* Restore the adapter's original node */
4422 adapter
->node
= orig_node
;
4424 ixgbe_cache_ring_register(adapter
);
4428 err_rx_ring_allocation
:
4429 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4430 kfree(adapter
->tx_ring
[i
]);
4431 err_tx_ring_allocation
:
4436 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4437 * @adapter: board private structure to initialize
4439 * Attempt to configure the interrupts using the best available
4440 * capabilities of the hardware and the kernel.
4442 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4444 struct ixgbe_hw
*hw
= &adapter
->hw
;
4446 int vector
, v_budget
;
4449 * It's easy to be greedy for MSI-X vectors, but it really
4450 * doesn't do us much good if we have a lot more vectors
4451 * than CPU's. So let's be conservative and only ask for
4452 * (roughly) the same number of vectors as there are CPU's.
4454 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4455 (int)num_online_cpus()) + NON_Q_VECTORS
;
4458 * At the same time, hardware can only support a maximum of
4459 * hw.mac->max_msix_vectors vectors. With features
4460 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4461 * descriptor queues supported by our device. Thus, we cap it off in
4462 * those rare cases where the cpu count also exceeds our vector limit.
4464 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4466 /* A failure in MSI-X entry allocation isn't fatal, but it does
4467 * mean we disable MSI-X capabilities of the adapter. */
4468 adapter
->msix_entries
= kcalloc(v_budget
,
4469 sizeof(struct msix_entry
), GFP_KERNEL
);
4470 if (adapter
->msix_entries
) {
4471 for (vector
= 0; vector
< v_budget
; vector
++)
4472 adapter
->msix_entries
[vector
].entry
= vector
;
4474 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4476 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4480 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4481 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4482 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4483 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4484 adapter
->atr_sample_rate
= 0;
4485 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4486 ixgbe_disable_sriov(adapter
);
4488 ixgbe_set_num_queues(adapter
);
4490 err
= pci_enable_msi(adapter
->pdev
);
4492 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4494 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4495 "Unable to allocate MSI interrupt, "
4496 "falling back to legacy. Error: %d\n", err
);
4506 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4507 * @adapter: board private structure to initialize
4509 * We allocate one q_vector per queue interrupt. If allocation fails we
4512 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4514 int q_idx
, num_q_vectors
;
4515 struct ixgbe_q_vector
*q_vector
;
4517 int (*poll
)(struct napi_struct
*, int);
4519 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4520 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4521 napi_vectors
= adapter
->num_rx_queues
;
4522 poll
= &ixgbe_clean_rxtx_many
;
4529 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4530 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4531 GFP_KERNEL
, adapter
->node
);
4533 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4537 q_vector
->adapter
= adapter
;
4538 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4539 q_vector
->eitr
= adapter
->tx_eitr_param
;
4541 q_vector
->eitr
= adapter
->rx_eitr_param
;
4542 q_vector
->v_idx
= q_idx
;
4543 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
4544 adapter
->q_vector
[q_idx
] = q_vector
;
4552 q_vector
= adapter
->q_vector
[q_idx
];
4553 netif_napi_del(&q_vector
->napi
);
4555 adapter
->q_vector
[q_idx
] = NULL
;
4561 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4562 * @adapter: board private structure to initialize
4564 * This function frees the memory allocated to the q_vectors. In addition if
4565 * NAPI is enabled it will delete any references to the NAPI struct prior
4566 * to freeing the q_vector.
4568 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
4570 int q_idx
, num_q_vectors
;
4572 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4573 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4577 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4578 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
4579 adapter
->q_vector
[q_idx
] = NULL
;
4580 netif_napi_del(&q_vector
->napi
);
4585 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
4587 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4588 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4589 pci_disable_msix(adapter
->pdev
);
4590 kfree(adapter
->msix_entries
);
4591 adapter
->msix_entries
= NULL
;
4592 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
4593 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
4594 pci_disable_msi(adapter
->pdev
);
4599 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4600 * @adapter: board private structure to initialize
4602 * We determine which interrupt scheme to use based on...
4603 * - Kernel support (MSI, MSI-X)
4604 * - which can be user-defined (via MODULE_PARAM)
4605 * - Hardware queue count (num_*_queues)
4606 * - defined by miscellaneous hardware support/features (RSS, etc.)
4608 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4612 /* Number of supported queues */
4613 ixgbe_set_num_queues(adapter
);
4615 err
= ixgbe_set_interrupt_capability(adapter
);
4617 e_dev_err("Unable to setup interrupt capabilities\n");
4618 goto err_set_interrupt
;
4621 err
= ixgbe_alloc_q_vectors(adapter
);
4623 e_dev_err("Unable to allocate memory for queue vectors\n");
4624 goto err_alloc_q_vectors
;
4627 err
= ixgbe_alloc_queues(adapter
);
4629 e_dev_err("Unable to allocate memory for queues\n");
4630 goto err_alloc_queues
;
4633 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
4634 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
4635 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
4637 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4642 ixgbe_free_q_vectors(adapter
);
4643 err_alloc_q_vectors
:
4644 ixgbe_reset_interrupt_capability(adapter
);
4650 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
4651 * @adapter: board private structure to clear interrupt scheme on
4653 * We go through and clear interrupt specific resources and reset the structure
4654 * to pre-load conditions
4656 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
4660 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4661 kfree(adapter
->tx_ring
[i
]);
4662 adapter
->tx_ring
[i
] = NULL
;
4664 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4665 kfree(adapter
->rx_ring
[i
]);
4666 adapter
->rx_ring
[i
] = NULL
;
4669 ixgbe_free_q_vectors(adapter
);
4670 ixgbe_reset_interrupt_capability(adapter
);
4674 * ixgbe_sfp_timer - worker thread to find a missing module
4675 * @data: pointer to our adapter struct
4677 static void ixgbe_sfp_timer(unsigned long data
)
4679 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
4682 * Do the sfp_timer outside of interrupt context due to the
4683 * delays that sfp+ detection requires
4685 schedule_work(&adapter
->sfp_task
);
4689 * ixgbe_sfp_task - worker thread to find a missing module
4690 * @work: pointer to work_struct containing our data
4692 static void ixgbe_sfp_task(struct work_struct
*work
)
4694 struct ixgbe_adapter
*adapter
= container_of(work
,
4695 struct ixgbe_adapter
,
4697 struct ixgbe_hw
*hw
= &adapter
->hw
;
4699 if ((hw
->phy
.type
== ixgbe_phy_nl
) &&
4700 (hw
->phy
.sfp_type
== ixgbe_sfp_type_not_present
)) {
4701 s32 ret
= hw
->phy
.ops
.identify_sfp(hw
);
4702 if (ret
== IXGBE_ERR_SFP_NOT_PRESENT
)
4704 ret
= hw
->phy
.ops
.reset(hw
);
4705 if (ret
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
4706 e_dev_err("failed to initialize because an unsupported "
4707 "SFP+ module type was detected.\n");
4708 e_dev_err("Reload the driver after installing a "
4709 "supported module.\n");
4710 unregister_netdev(adapter
->netdev
);
4712 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
4714 /* don't need this routine any more */
4715 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
4719 if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
))
4720 mod_timer(&adapter
->sfp_timer
,
4721 round_jiffies(jiffies
+ (2 * HZ
)));
4725 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
4726 * @adapter: board private structure to initialize
4728 * ixgbe_sw_init initializes the Adapter private data structure.
4729 * Fields are initialized based on PCI device information and
4730 * OS network device settings (MTU size).
4732 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
4734 struct ixgbe_hw
*hw
= &adapter
->hw
;
4735 struct pci_dev
*pdev
= adapter
->pdev
;
4736 struct net_device
*dev
= adapter
->netdev
;
4738 #ifdef CONFIG_IXGBE_DCB
4740 struct tc_configuration
*tc
;
4743 /* PCI config space info */
4745 hw
->vendor_id
= pdev
->vendor
;
4746 hw
->device_id
= pdev
->device
;
4747 hw
->revision_id
= pdev
->revision
;
4748 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
4749 hw
->subsystem_device_id
= pdev
->subsystem_device
;
4751 /* Set capability flags */
4752 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
4753 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
4754 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
4755 adapter
->ring_feature
[RING_F_DCB
].indices
= IXGBE_MAX_DCB_INDICES
;
4756 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
4757 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
4758 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
4759 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
4760 } else if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
4761 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
4762 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
4763 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
4764 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
4765 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
4766 if (dev
->features
& NETIF_F_NTUPLE
) {
4767 /* Flow Director perfect filter enabled */
4768 adapter
->flags
|= IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4769 adapter
->atr_sample_rate
= 0;
4770 spin_lock_init(&adapter
->fdir_perfect_lock
);
4772 /* Flow Director hash filters enabled */
4773 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4774 adapter
->atr_sample_rate
= 20;
4776 adapter
->ring_feature
[RING_F_FDIR
].indices
=
4777 IXGBE_MAX_FDIR_INDICES
;
4778 adapter
->fdir_pballoc
= 0;
4780 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
4781 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
4782 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
4783 #ifdef CONFIG_IXGBE_DCB
4784 /* Default traffic class to use for FCoE */
4785 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
4787 #endif /* IXGBE_FCOE */
4790 #ifdef CONFIG_IXGBE_DCB
4791 /* Configure DCB traffic classes */
4792 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
4793 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
4794 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
4795 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4796 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
4797 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
4798 tc
->dcb_pfc
= pfc_disabled
;
4800 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
4801 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
4802 adapter
->dcb_cfg
.rx_pba_cfg
= pba_equal
;
4803 adapter
->dcb_cfg
.pfc_mode_enable
= false;
4804 adapter
->dcb_cfg
.round_robin_enable
= false;
4805 adapter
->dcb_set_bitmap
= 0x00;
4806 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
4807 adapter
->ring_feature
[RING_F_DCB
].indices
);
4811 /* default flow control settings */
4812 hw
->fc
.requested_mode
= ixgbe_fc_full
;
4813 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
4815 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
4817 hw
->fc
.high_water
= IXGBE_DEFAULT_FCRTH
;
4818 hw
->fc
.low_water
= IXGBE_DEFAULT_FCRTL
;
4819 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
4820 hw
->fc
.send_xon
= true;
4821 hw
->fc
.disable_fc_autoneg
= false;
4823 /* enable itr by default in dynamic mode */
4824 adapter
->rx_itr_setting
= 1;
4825 adapter
->rx_eitr_param
= 20000;
4826 adapter
->tx_itr_setting
= 1;
4827 adapter
->tx_eitr_param
= 10000;
4829 /* set defaults for eitr in MegaBytes */
4830 adapter
->eitr_low
= 10;
4831 adapter
->eitr_high
= 20;
4833 /* set default ring sizes */
4834 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
4835 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
4837 /* initialize eeprom parameters */
4838 if (ixgbe_init_eeprom_params_generic(hw
)) {
4839 e_dev_err("EEPROM initialization failed\n");
4843 /* enable rx csum by default */
4844 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
4846 /* get assigned NUMA node */
4847 adapter
->node
= dev_to_node(&pdev
->dev
);
4849 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4855 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
4856 * @adapter: board private structure
4857 * @tx_ring: tx descriptor ring (for a specific queue) to setup
4859 * Return 0 on success, negative on failure
4861 int ixgbe_setup_tx_resources(struct ixgbe_adapter
*adapter
,
4862 struct ixgbe_ring
*tx_ring
)
4864 struct pci_dev
*pdev
= adapter
->pdev
;
4867 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4868 tx_ring
->tx_buffer_info
= vmalloc_node(size
, tx_ring
->numa_node
);
4869 if (!tx_ring
->tx_buffer_info
)
4870 tx_ring
->tx_buffer_info
= vmalloc(size
);
4871 if (!tx_ring
->tx_buffer_info
)
4873 memset(tx_ring
->tx_buffer_info
, 0, size
);
4875 /* round up to nearest 4K */
4876 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
4877 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
4879 tx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, tx_ring
->size
,
4880 &tx_ring
->dma
, GFP_KERNEL
);
4884 tx_ring
->next_to_use
= 0;
4885 tx_ring
->next_to_clean
= 0;
4886 tx_ring
->work_limit
= tx_ring
->count
;
4890 vfree(tx_ring
->tx_buffer_info
);
4891 tx_ring
->tx_buffer_info
= NULL
;
4892 e_err(probe
, "Unable to allocate memory for the Tx descriptor ring\n");
4897 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
4898 * @adapter: board private structure
4900 * If this function returns with an error, then it's possible one or
4901 * more of the rings is populated (while the rest are not). It is the
4902 * callers duty to clean those orphaned rings.
4904 * Return 0 on success, negative on failure
4906 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
4910 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4911 err
= ixgbe_setup_tx_resources(adapter
, adapter
->tx_ring
[i
]);
4914 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
4922 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
4923 * @adapter: board private structure
4924 * @rx_ring: rx descriptor ring (for a specific queue) to setup
4926 * Returns 0 on success, negative on failure
4928 int ixgbe_setup_rx_resources(struct ixgbe_adapter
*adapter
,
4929 struct ixgbe_ring
*rx_ring
)
4931 struct pci_dev
*pdev
= adapter
->pdev
;
4934 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4935 rx_ring
->rx_buffer_info
= vmalloc_node(size
, adapter
->node
);
4936 if (!rx_ring
->rx_buffer_info
)
4937 rx_ring
->rx_buffer_info
= vmalloc(size
);
4938 if (!rx_ring
->rx_buffer_info
) {
4939 e_err(probe
, "vmalloc allocation failed for the Rx "
4940 "descriptor ring\n");
4943 memset(rx_ring
->rx_buffer_info
, 0, size
);
4945 /* Round up to nearest 4K */
4946 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
4947 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
4949 rx_ring
->desc
= dma_alloc_coherent(&pdev
->dev
, rx_ring
->size
,
4950 &rx_ring
->dma
, GFP_KERNEL
);
4952 if (!rx_ring
->desc
) {
4953 e_err(probe
, "Memory allocation failed for the Rx "
4954 "descriptor ring\n");
4955 vfree(rx_ring
->rx_buffer_info
);
4959 rx_ring
->next_to_clean
= 0;
4960 rx_ring
->next_to_use
= 0;
4969 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4970 * @adapter: board private structure
4972 * If this function returns with an error, then it's possible one or
4973 * more of the rings is populated (while the rest are not). It is the
4974 * callers duty to clean those orphaned rings.
4976 * Return 0 on success, negative on failure
4979 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
4983 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
4984 err
= ixgbe_setup_rx_resources(adapter
, adapter
->rx_ring
[i
]);
4987 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
4995 * ixgbe_free_tx_resources - Free Tx Resources per Queue
4996 * @adapter: board private structure
4997 * @tx_ring: Tx descriptor ring for a specific queue
4999 * Free all transmit software resources
5001 void ixgbe_free_tx_resources(struct ixgbe_adapter
*adapter
,
5002 struct ixgbe_ring
*tx_ring
)
5004 struct pci_dev
*pdev
= adapter
->pdev
;
5006 ixgbe_clean_tx_ring(adapter
, tx_ring
);
5008 vfree(tx_ring
->tx_buffer_info
);
5009 tx_ring
->tx_buffer_info
= NULL
;
5011 dma_free_coherent(&pdev
->dev
, tx_ring
->size
, tx_ring
->desc
,
5014 tx_ring
->desc
= NULL
;
5018 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5019 * @adapter: board private structure
5021 * Free all transmit software resources
5023 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5027 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5028 if (adapter
->tx_ring
[i
]->desc
)
5029 ixgbe_free_tx_resources(adapter
, adapter
->tx_ring
[i
]);
5033 * ixgbe_free_rx_resources - Free Rx Resources
5034 * @adapter: board private structure
5035 * @rx_ring: ring to clean the resources from
5037 * Free all receive software resources
5039 void ixgbe_free_rx_resources(struct ixgbe_adapter
*adapter
,
5040 struct ixgbe_ring
*rx_ring
)
5042 struct pci_dev
*pdev
= adapter
->pdev
;
5044 ixgbe_clean_rx_ring(adapter
, rx_ring
);
5046 vfree(rx_ring
->rx_buffer_info
);
5047 rx_ring
->rx_buffer_info
= NULL
;
5049 dma_free_coherent(&pdev
->dev
, rx_ring
->size
, rx_ring
->desc
,
5052 rx_ring
->desc
= NULL
;
5056 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5057 * @adapter: board private structure
5059 * Free all receive software resources
5061 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5065 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5066 if (adapter
->rx_ring
[i
]->desc
)
5067 ixgbe_free_rx_resources(adapter
, adapter
->rx_ring
[i
]);
5071 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5072 * @netdev: network interface device structure
5073 * @new_mtu: new value for maximum frame size
5075 * Returns 0 on success, negative on failure
5077 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5079 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5080 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5082 /* MTU < 68 is an error and causes problems on some kernels */
5083 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5086 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5087 /* must set new MTU before calling down or up */
5088 netdev
->mtu
= new_mtu
;
5090 if (netif_running(netdev
))
5091 ixgbe_reinit_locked(adapter
);
5097 * ixgbe_open - Called when a network interface is made active
5098 * @netdev: network interface device structure
5100 * Returns 0 on success, negative value on failure
5102 * The open entry point is called when a network interface is made
5103 * active by the system (IFF_UP). At this point all resources needed
5104 * for transmit and receive operations are allocated, the interrupt
5105 * handler is registered with the OS, the watchdog timer is started,
5106 * and the stack is notified that the interface is ready.
5108 static int ixgbe_open(struct net_device
*netdev
)
5110 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5113 /* disallow open during test */
5114 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5117 netif_carrier_off(netdev
);
5119 /* allocate transmit descriptors */
5120 err
= ixgbe_setup_all_tx_resources(adapter
);
5124 /* allocate receive descriptors */
5125 err
= ixgbe_setup_all_rx_resources(adapter
);
5129 ixgbe_configure(adapter
);
5131 err
= ixgbe_request_irq(adapter
);
5135 err
= ixgbe_up_complete(adapter
);
5139 netif_tx_start_all_queues(netdev
);
5144 ixgbe_release_hw_control(adapter
);
5145 ixgbe_free_irq(adapter
);
5148 ixgbe_free_all_rx_resources(adapter
);
5150 ixgbe_free_all_tx_resources(adapter
);
5151 ixgbe_reset(adapter
);
5157 * ixgbe_close - Disables a network interface
5158 * @netdev: network interface device structure
5160 * Returns 0, this is not allowed to fail
5162 * The close entry point is called when an interface is de-activated
5163 * by the OS. The hardware is still under the drivers control, but
5164 * needs to be disabled. A global MAC reset is issued to stop the
5165 * hardware, and all transmit and receive resources are freed.
5167 static int ixgbe_close(struct net_device
*netdev
)
5169 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5171 ixgbe_down(adapter
);
5172 ixgbe_free_irq(adapter
);
5174 ixgbe_free_all_tx_resources(adapter
);
5175 ixgbe_free_all_rx_resources(adapter
);
5177 ixgbe_release_hw_control(adapter
);
5183 static int ixgbe_resume(struct pci_dev
*pdev
)
5185 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5186 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5189 pci_set_power_state(pdev
, PCI_D0
);
5190 pci_restore_state(pdev
);
5192 * pci_restore_state clears dev->state_saved so call
5193 * pci_save_state to restore it.
5195 pci_save_state(pdev
);
5197 err
= pci_enable_device_mem(pdev
);
5199 e_dev_err("Cannot enable PCI device from suspend\n");
5202 pci_set_master(pdev
);
5204 pci_wake_from_d3(pdev
, false);
5206 err
= ixgbe_init_interrupt_scheme(adapter
);
5208 e_dev_err("Cannot initialize interrupts for device\n");
5212 ixgbe_reset(adapter
);
5214 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5216 if (netif_running(netdev
)) {
5217 err
= ixgbe_open(adapter
->netdev
);
5222 netif_device_attach(netdev
);
5226 #endif /* CONFIG_PM */
5228 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5230 struct net_device
*netdev
= pci_get_drvdata(pdev
);
5231 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5232 struct ixgbe_hw
*hw
= &adapter
->hw
;
5234 u32 wufc
= adapter
->wol
;
5239 netif_device_detach(netdev
);
5241 if (netif_running(netdev
)) {
5242 ixgbe_down(adapter
);
5243 ixgbe_free_irq(adapter
);
5244 ixgbe_free_all_tx_resources(adapter
);
5245 ixgbe_free_all_rx_resources(adapter
);
5249 retval
= pci_save_state(pdev
);
5255 ixgbe_set_rx_mode(netdev
);
5257 /* turn on all-multi mode if wake on multicast is enabled */
5258 if (wufc
& IXGBE_WUFC_MC
) {
5259 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5260 fctrl
|= IXGBE_FCTRL_MPE
;
5261 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5264 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5265 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5266 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5268 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5270 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5271 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5274 if (wufc
&& hw
->mac
.type
== ixgbe_mac_82599EB
)
5275 pci_wake_from_d3(pdev
, true);
5277 pci_wake_from_d3(pdev
, false);
5279 *enable_wake
= !!wufc
;
5281 ixgbe_clear_interrupt_scheme(adapter
);
5283 ixgbe_release_hw_control(adapter
);
5285 pci_disable_device(pdev
);
5291 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5296 retval
= __ixgbe_shutdown(pdev
, &wake
);
5301 pci_prepare_to_sleep(pdev
);
5303 pci_wake_from_d3(pdev
, false);
5304 pci_set_power_state(pdev
, PCI_D3hot
);
5309 #endif /* CONFIG_PM */
5311 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5315 __ixgbe_shutdown(pdev
, &wake
);
5317 if (system_state
== SYSTEM_POWER_OFF
) {
5318 pci_wake_from_d3(pdev
, wake
);
5319 pci_set_power_state(pdev
, PCI_D3hot
);
5324 * ixgbe_update_stats - Update the board statistics counters.
5325 * @adapter: board private structure
5327 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5329 struct net_device
*netdev
= adapter
->netdev
;
5330 struct ixgbe_hw
*hw
= &adapter
->hw
;
5332 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5333 u64 non_eop_descs
= 0, restart_queue
= 0;
5335 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5336 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5339 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5342 for (i
= 0; i
< 16; i
++)
5343 adapter
->hw_rx_no_dma_resources
+=
5344 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5345 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5346 rsc_count
+= adapter
->rx_ring
[i
]->rsc_count
;
5347 rsc_flush
+= adapter
->rx_ring
[i
]->rsc_flush
;
5349 adapter
->rsc_total_count
= rsc_count
;
5350 adapter
->rsc_total_flush
= rsc_flush
;
5353 /* gather some stats to the adapter struct that are per queue */
5354 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5355 restart_queue
+= adapter
->tx_ring
[i
]->restart_queue
;
5356 adapter
->restart_queue
= restart_queue
;
5358 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5359 non_eop_descs
+= adapter
->rx_ring
[i
]->non_eop_descs
;
5360 adapter
->non_eop_descs
= non_eop_descs
;
5362 adapter
->stats
.crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5363 for (i
= 0; i
< 8; i
++) {
5364 /* for packet buffers not used, the register should read 0 */
5365 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5367 adapter
->stats
.mpc
[i
] += mpc
;
5368 total_mpc
+= adapter
->stats
.mpc
[i
];
5369 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5370 adapter
->stats
.rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5371 adapter
->stats
.qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5372 adapter
->stats
.qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5373 adapter
->stats
.qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5374 adapter
->stats
.qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5375 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5376 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5377 IXGBE_PXONRXCNT(i
));
5378 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5379 IXGBE_PXOFFRXCNT(i
));
5380 adapter
->stats
.qprdc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5382 adapter
->stats
.pxonrxc
[i
] += IXGBE_READ_REG(hw
,
5384 adapter
->stats
.pxoffrxc
[i
] += IXGBE_READ_REG(hw
,
5387 adapter
->stats
.pxontxc
[i
] += IXGBE_READ_REG(hw
,
5389 adapter
->stats
.pxofftxc
[i
] += IXGBE_READ_REG(hw
,
5392 adapter
->stats
.gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5393 /* work around hardware counting issue */
5394 adapter
->stats
.gprc
-= missed_rx
;
5396 /* 82598 hardware only has a 32 bit counter in the high register */
5397 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5399 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5400 tmp
= IXGBE_READ_REG(hw
, IXGBE_GORCH
) & 0xF; /* 4 high bits of GORC */
5401 adapter
->stats
.gorc
+= (tmp
<< 32);
5402 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5403 tmp
= IXGBE_READ_REG(hw
, IXGBE_GOTCH
) & 0xF; /* 4 high bits of GOTC */
5404 adapter
->stats
.gotc
+= (tmp
<< 32);
5405 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5406 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5407 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5408 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
5409 adapter
->stats
.fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5410 adapter
->stats
.fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5412 adapter
->stats
.fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5413 adapter
->stats
.fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5414 adapter
->stats
.fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5415 adapter
->stats
.fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5416 adapter
->stats
.fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5417 adapter
->stats
.fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5418 #endif /* IXGBE_FCOE */
5420 adapter
->stats
.lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5421 adapter
->stats
.lxoffrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
5422 adapter
->stats
.gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5423 adapter
->stats
.gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5424 adapter
->stats
.tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5426 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5427 adapter
->stats
.bprc
+= bprc
;
5428 adapter
->stats
.mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5429 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5430 adapter
->stats
.mprc
-= bprc
;
5431 adapter
->stats
.roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5432 adapter
->stats
.prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5433 adapter
->stats
.prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5434 adapter
->stats
.prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5435 adapter
->stats
.prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5436 adapter
->stats
.prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5437 adapter
->stats
.prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5438 adapter
->stats
.rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5439 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5440 adapter
->stats
.lxontxc
+= lxon
;
5441 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5442 adapter
->stats
.lxofftxc
+= lxoff
;
5443 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5444 adapter
->stats
.gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5445 adapter
->stats
.mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5447 * 82598 errata - tx of flow control packets is included in tx counters
5449 xon_off_tot
= lxon
+ lxoff
;
5450 adapter
->stats
.gptc
-= xon_off_tot
;
5451 adapter
->stats
.mptc
-= xon_off_tot
;
5452 adapter
->stats
.gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5453 adapter
->stats
.ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5454 adapter
->stats
.rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5455 adapter
->stats
.rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5456 adapter
->stats
.tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5457 adapter
->stats
.ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5458 adapter
->stats
.ptc64
-= xon_off_tot
;
5459 adapter
->stats
.ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5460 adapter
->stats
.ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5461 adapter
->stats
.ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5462 adapter
->stats
.ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5463 adapter
->stats
.ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5464 adapter
->stats
.bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5466 /* Fill out the OS statistics structure */
5467 netdev
->stats
.multicast
= adapter
->stats
.mprc
;
5470 netdev
->stats
.rx_errors
= adapter
->stats
.crcerrs
+
5471 adapter
->stats
.rlec
;
5472 netdev
->stats
.rx_dropped
= 0;
5473 netdev
->stats
.rx_length_errors
= adapter
->stats
.rlec
;
5474 netdev
->stats
.rx_crc_errors
= adapter
->stats
.crcerrs
;
5475 netdev
->stats
.rx_missed_errors
= total_mpc
;
5479 * ixgbe_watchdog - Timer Call-back
5480 * @data: pointer to adapter cast into an unsigned long
5482 static void ixgbe_watchdog(unsigned long data
)
5484 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
5485 struct ixgbe_hw
*hw
= &adapter
->hw
;
5490 * Do the watchdog outside of interrupt context due to the lovely
5491 * delays that some of the newer hardware requires
5494 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5495 goto watchdog_short_circuit
;
5497 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
5499 * for legacy and MSI interrupts don't set any bits
5500 * that are enabled for EIAM, because this operation
5501 * would set *both* EIMS and EICS for any bit in EIAM
5503 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
5504 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
5505 goto watchdog_reschedule
;
5508 /* get one bit for every active tx/rx interrupt vector */
5509 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
5510 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
5511 if (qv
->rxr_count
|| qv
->txr_count
)
5512 eics
|= ((u64
)1 << i
);
5515 /* Cause software interrupt to ensure rx rings are cleaned */
5516 ixgbe_irq_rearm_queues(adapter
, eics
);
5518 watchdog_reschedule
:
5519 /* Reset the timer */
5520 mod_timer(&adapter
->watchdog_timer
, round_jiffies(jiffies
+ 2 * HZ
));
5522 watchdog_short_circuit
:
5523 schedule_work(&adapter
->watchdog_task
);
5527 * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
5528 * @work: pointer to work_struct containing our data
5530 static void ixgbe_multispeed_fiber_task(struct work_struct
*work
)
5532 struct ixgbe_adapter
*adapter
= container_of(work
,
5533 struct ixgbe_adapter
,
5534 multispeed_fiber_task
);
5535 struct ixgbe_hw
*hw
= &adapter
->hw
;
5539 adapter
->flags
|= IXGBE_FLAG_IN_SFP_LINK_TASK
;
5540 autoneg
= hw
->phy
.autoneg_advertised
;
5541 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
5542 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
5543 hw
->mac
.autotry_restart
= false;
5544 if (hw
->mac
.ops
.setup_link
)
5545 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
5546 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
5547 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_LINK_TASK
;
5551 * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
5552 * @work: pointer to work_struct containing our data
5554 static void ixgbe_sfp_config_module_task(struct work_struct
*work
)
5556 struct ixgbe_adapter
*adapter
= container_of(work
,
5557 struct ixgbe_adapter
,
5558 sfp_config_module_task
);
5559 struct ixgbe_hw
*hw
= &adapter
->hw
;
5562 adapter
->flags
|= IXGBE_FLAG_IN_SFP_MOD_TASK
;
5564 /* Time for electrical oscillations to settle down */
5566 err
= hw
->phy
.ops
.identify_sfp(hw
);
5568 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
5569 e_dev_err("failed to initialize because an unsupported SFP+ "
5570 "module type was detected.\n");
5571 e_dev_err("Reload the driver after installing a supported "
5573 unregister_netdev(adapter
->netdev
);
5576 hw
->mac
.ops
.setup_sfp(hw
);
5578 if (!(adapter
->flags
& IXGBE_FLAG_IN_SFP_LINK_TASK
))
5579 /* This will also work for DA Twinax connections */
5580 schedule_work(&adapter
->multispeed_fiber_task
);
5581 adapter
->flags
&= ~IXGBE_FLAG_IN_SFP_MOD_TASK
;
5585 * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
5586 * @work: pointer to work_struct containing our data
5588 static void ixgbe_fdir_reinit_task(struct work_struct
*work
)
5590 struct ixgbe_adapter
*adapter
= container_of(work
,
5591 struct ixgbe_adapter
,
5593 struct ixgbe_hw
*hw
= &adapter
->hw
;
5596 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5597 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5598 set_bit(__IXGBE_FDIR_INIT_DONE
,
5599 &(adapter
->tx_ring
[i
]->reinit_state
));
5601 e_err(probe
, "failed to finish FDIR re-initialization, "
5602 "ignored adding FDIR ATR filters\n");
5604 /* Done FDIR Re-initialization, enable transmits */
5605 netif_tx_start_all_queues(adapter
->netdev
);
5608 static DEFINE_MUTEX(ixgbe_watchdog_lock
);
5611 * ixgbe_watchdog_task - worker thread to bring link up
5612 * @work: pointer to work_struct containing our data
5614 static void ixgbe_watchdog_task(struct work_struct
*work
)
5616 struct ixgbe_adapter
*adapter
= container_of(work
,
5617 struct ixgbe_adapter
,
5619 struct net_device
*netdev
= adapter
->netdev
;
5620 struct ixgbe_hw
*hw
= &adapter
->hw
;
5624 struct ixgbe_ring
*tx_ring
;
5625 int some_tx_pending
= 0;
5627 mutex_lock(&ixgbe_watchdog_lock
);
5629 link_up
= adapter
->link_up
;
5630 link_speed
= adapter
->link_speed
;
5632 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
) {
5633 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
5636 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
5637 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
5638 hw
->mac
.ops
.fc_enable(hw
, i
);
5640 hw
->mac
.ops
.fc_enable(hw
, 0);
5643 hw
->mac
.ops
.fc_enable(hw
, 0);
5648 time_after(jiffies
, (adapter
->link_check_timeout
+
5649 IXGBE_TRY_LINK_TIMEOUT
))) {
5650 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
5651 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
5653 adapter
->link_up
= link_up
;
5654 adapter
->link_speed
= link_speed
;
5658 if (!netif_carrier_ok(netdev
)) {
5659 bool flow_rx
, flow_tx
;
5661 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
5662 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
5663 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
5664 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
5665 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
5667 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5668 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
5669 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
5670 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
5673 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
5674 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
5676 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
5677 "1 Gbps" : "unknown speed")),
5678 ((flow_rx
&& flow_tx
) ? "RX/TX" :
5680 (flow_tx
? "TX" : "None"))));
5682 netif_carrier_on(netdev
);
5684 /* Force detection of hung controller */
5685 adapter
->detect_tx_hung
= true;
5688 adapter
->link_up
= false;
5689 adapter
->link_speed
= 0;
5690 if (netif_carrier_ok(netdev
)) {
5691 e_info(drv
, "NIC Link is Down\n");
5692 netif_carrier_off(netdev
);
5696 if (!netif_carrier_ok(netdev
)) {
5697 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5698 tx_ring
= adapter
->tx_ring
[i
];
5699 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
5700 some_tx_pending
= 1;
5705 if (some_tx_pending
) {
5706 /* We've lost link, so the controller stops DMA,
5707 * but we've got queued Tx work that's never going
5708 * to get done, so reset controller to flush Tx.
5709 * (Do the reset outside of interrupt context).
5711 schedule_work(&adapter
->reset_task
);
5715 ixgbe_update_stats(adapter
);
5716 mutex_unlock(&ixgbe_watchdog_lock
);
5719 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
5720 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
5721 u32 tx_flags
, u8
*hdr_len
)
5723 struct ixgbe_adv_tx_context_desc
*context_desc
;
5726 struct ixgbe_tx_buffer
*tx_buffer_info
;
5727 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
5728 u32 mss_l4len_idx
, l4len
;
5730 if (skb_is_gso(skb
)) {
5731 if (skb_header_cloned(skb
)) {
5732 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
5736 l4len
= tcp_hdrlen(skb
);
5739 if (skb
->protocol
== htons(ETH_P_IP
)) {
5740 struct iphdr
*iph
= ip_hdr(skb
);
5743 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
5747 } else if (skb_is_gso_v6(skb
)) {
5748 ipv6_hdr(skb
)->payload_len
= 0;
5749 tcp_hdr(skb
)->check
=
5750 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
5751 &ipv6_hdr(skb
)->daddr
,
5755 i
= tx_ring
->next_to_use
;
5757 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5758 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5760 /* VLAN MACLEN IPLEN */
5761 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5763 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5764 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
5765 IXGBE_ADVTXD_MACLEN_SHIFT
);
5766 *hdr_len
+= skb_network_offset(skb
);
5768 (skb_transport_header(skb
) - skb_network_header(skb
));
5770 (skb_transport_header(skb
) - skb_network_header(skb
));
5771 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5772 context_desc
->seqnum_seed
= 0;
5774 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
5775 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
5776 IXGBE_ADVTXD_DTYP_CTXT
);
5778 if (skb
->protocol
== htons(ETH_P_IP
))
5779 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5780 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5781 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5785 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
5786 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
5787 /* use index 1 for TSO */
5788 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
5789 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
5791 tx_buffer_info
->time_stamp
= jiffies
;
5792 tx_buffer_info
->next_to_watch
= i
;
5795 if (i
== tx_ring
->count
)
5797 tx_ring
->next_to_use
= i
;
5804 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
5805 struct ixgbe_ring
*tx_ring
,
5806 struct sk_buff
*skb
, u32 tx_flags
)
5808 struct ixgbe_adv_tx_context_desc
*context_desc
;
5810 struct ixgbe_tx_buffer
*tx_buffer_info
;
5811 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
5813 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
5814 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
5815 i
= tx_ring
->next_to_use
;
5816 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5817 context_desc
= IXGBE_TX_CTXTDESC_ADV(*tx_ring
, i
);
5819 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
5821 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
5822 vlan_macip_lens
|= (skb_network_offset(skb
) <<
5823 IXGBE_ADVTXD_MACLEN_SHIFT
);
5824 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
5825 vlan_macip_lens
|= (skb_transport_header(skb
) -
5826 skb_network_header(skb
));
5828 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
5829 context_desc
->seqnum_seed
= 0;
5831 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
5832 IXGBE_ADVTXD_DTYP_CTXT
);
5834 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
5837 if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
)) {
5838 const struct vlan_ethhdr
*vhdr
=
5839 (const struct vlan_ethhdr
*)skb
->data
;
5841 protocol
= vhdr
->h_vlan_encapsulated_proto
;
5843 protocol
= skb
->protocol
;
5847 case cpu_to_be16(ETH_P_IP
):
5848 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
5849 if (ip_hdr(skb
)->protocol
== IPPROTO_TCP
)
5851 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5852 else if (ip_hdr(skb
)->protocol
== IPPROTO_SCTP
)
5854 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5856 case cpu_to_be16(ETH_P_IPV6
):
5857 /* XXX what about other V6 headers?? */
5858 if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_TCP
)
5860 IXGBE_ADVTXD_TUCMD_L4T_TCP
;
5861 else if (ipv6_hdr(skb
)->nexthdr
== IPPROTO_SCTP
)
5863 IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
5866 if (unlikely(net_ratelimit())) {
5867 e_warn(probe
, "partial checksum "
5875 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
5876 /* use index zero for tx checksum offload */
5877 context_desc
->mss_l4len_idx
= 0;
5879 tx_buffer_info
->time_stamp
= jiffies
;
5880 tx_buffer_info
->next_to_watch
= i
;
5883 if (i
== tx_ring
->count
)
5885 tx_ring
->next_to_use
= i
;
5893 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
5894 struct ixgbe_ring
*tx_ring
,
5895 struct sk_buff
*skb
, u32 tx_flags
,
5898 struct pci_dev
*pdev
= adapter
->pdev
;
5899 struct ixgbe_tx_buffer
*tx_buffer_info
;
5901 unsigned int total
= skb
->len
;
5902 unsigned int offset
= 0, size
, count
= 0, i
;
5903 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
5906 i
= tx_ring
->next_to_use
;
5908 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
5909 /* excluding fcoe_crc_eof for FCoE */
5910 total
-= sizeof(struct fcoe_crc_eof
);
5912 len
= min(skb_headlen(skb
), total
);
5914 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5915 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5917 tx_buffer_info
->length
= size
;
5918 tx_buffer_info
->mapped_as_page
= false;
5919 tx_buffer_info
->dma
= dma_map_single(&pdev
->dev
,
5921 size
, DMA_TO_DEVICE
);
5922 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5924 tx_buffer_info
->time_stamp
= jiffies
;
5925 tx_buffer_info
->next_to_watch
= i
;
5934 if (i
== tx_ring
->count
)
5939 for (f
= 0; f
< nr_frags
; f
++) {
5940 struct skb_frag_struct
*frag
;
5942 frag
= &skb_shinfo(skb
)->frags
[f
];
5943 len
= min((unsigned int)frag
->size
, total
);
5944 offset
= frag
->page_offset
;
5948 if (i
== tx_ring
->count
)
5951 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5952 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
5954 tx_buffer_info
->length
= size
;
5955 tx_buffer_info
->dma
= dma_map_page(&adapter
->pdev
->dev
,
5959 tx_buffer_info
->mapped_as_page
= true;
5960 if (dma_mapping_error(&pdev
->dev
, tx_buffer_info
->dma
))
5962 tx_buffer_info
->time_stamp
= jiffies
;
5963 tx_buffer_info
->next_to_watch
= i
;
5974 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
5975 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
5980 e_dev_err("TX DMA map failed\n");
5982 /* clear timestamp and dma mappings for failed tx_buffer_info map */
5983 tx_buffer_info
->dma
= 0;
5984 tx_buffer_info
->time_stamp
= 0;
5985 tx_buffer_info
->next_to_watch
= 0;
5989 /* clear timestamp and dma mappings for remaining portion of packet */
5992 i
+= tx_ring
->count
;
5994 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
5995 ixgbe_unmap_and_free_tx_resource(adapter
, tx_buffer_info
);
6001 static void ixgbe_tx_queue(struct ixgbe_adapter
*adapter
,
6002 struct ixgbe_ring
*tx_ring
,
6003 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6005 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6006 struct ixgbe_tx_buffer
*tx_buffer_info
;
6007 u32 olinfo_status
= 0, cmd_type_len
= 0;
6009 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6011 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6013 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6015 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6016 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6018 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6019 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6021 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6022 IXGBE_ADVTXD_POPTS_SHIFT
;
6024 /* use index 1 context for tso */
6025 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6026 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6027 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6028 IXGBE_ADVTXD_POPTS_SHIFT
;
6030 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6031 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6032 IXGBE_ADVTXD_POPTS_SHIFT
;
6034 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6035 olinfo_status
|= IXGBE_ADVTXD_CC
;
6036 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6037 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6038 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6041 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6043 i
= tx_ring
->next_to_use
;
6045 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6046 tx_desc
= IXGBE_TX_DESC_ADV(*tx_ring
, i
);
6047 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6048 tx_desc
->read
.cmd_type_len
=
6049 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6050 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6052 if (i
== tx_ring
->count
)
6056 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6059 * Force memory writes to complete before letting h/w
6060 * know there are new descriptors to fetch. (Only
6061 * applicable for weak-ordered memory model archs,
6066 tx_ring
->next_to_use
= i
;
6067 writel(i
, adapter
->hw
.hw_addr
+ tx_ring
->tail
);
6070 static void ixgbe_atr(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6071 int queue
, u32 tx_flags
)
6073 struct ixgbe_atr_input atr_input
;
6075 struct iphdr
*iph
= ip_hdr(skb
);
6076 struct ethhdr
*eth
= (struct ethhdr
*)skb
->data
;
6077 u16 vlan_id
, src_port
, dst_port
, flex_bytes
;
6078 u32 src_ipv4_addr
, dst_ipv4_addr
;
6081 /* Right now, we support IPv4 only */
6082 if (skb
->protocol
!= htons(ETH_P_IP
))
6084 /* check if we're UDP or TCP */
6085 if (iph
->protocol
== IPPROTO_TCP
) {
6087 src_port
= th
->source
;
6088 dst_port
= th
->dest
;
6089 l4type
|= IXGBE_ATR_L4TYPE_TCP
;
6090 /* l4type IPv4 type is 0, no need to assign */
6092 /* Unsupported L4 header, just bail here */
6096 memset(&atr_input
, 0, sizeof(struct ixgbe_atr_input
));
6098 vlan_id
= (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
) >>
6099 IXGBE_TX_FLAGS_VLAN_SHIFT
;
6100 src_ipv4_addr
= iph
->saddr
;
6101 dst_ipv4_addr
= iph
->daddr
;
6102 flex_bytes
= eth
->h_proto
;
6104 ixgbe_atr_set_vlan_id_82599(&atr_input
, vlan_id
);
6105 ixgbe_atr_set_src_port_82599(&atr_input
, dst_port
);
6106 ixgbe_atr_set_dst_port_82599(&atr_input
, src_port
);
6107 ixgbe_atr_set_flex_byte_82599(&atr_input
, flex_bytes
);
6108 ixgbe_atr_set_l4type_82599(&atr_input
, l4type
);
6109 /* src and dst are inverted, think how the receiver sees them */
6110 ixgbe_atr_set_src_ipv4_82599(&atr_input
, dst_ipv4_addr
);
6111 ixgbe_atr_set_dst_ipv4_82599(&atr_input
, src_ipv4_addr
);
6113 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6114 ixgbe_fdir_add_signature_filter_82599(&adapter
->hw
, &atr_input
, queue
);
6117 static int __ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6118 struct ixgbe_ring
*tx_ring
, int size
)
6120 netif_stop_subqueue(netdev
, tx_ring
->queue_index
);
6121 /* Herbert's original patch had:
6122 * smp_mb__after_netif_stop_queue();
6123 * but since that doesn't exist yet, just open code it. */
6126 /* We need to check again in a case another CPU has just
6127 * made room available. */
6128 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6131 /* A reprieve! - use start_queue because it doesn't call schedule */
6132 netif_start_subqueue(netdev
, tx_ring
->queue_index
);
6133 ++tx_ring
->restart_queue
;
6137 static int ixgbe_maybe_stop_tx(struct net_device
*netdev
,
6138 struct ixgbe_ring
*tx_ring
, int size
)
6140 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6142 return __ixgbe_maybe_stop_tx(netdev
, tx_ring
, size
);
6145 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6147 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6148 int txq
= smp_processor_id();
6150 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6151 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6152 txq
-= dev
->real_num_tx_queues
;
6157 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
6158 ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6159 (skb
->protocol
== htons(ETH_P_FIP
)))) {
6160 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6161 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6165 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6166 if (skb
->priority
== TC_PRIO_CONTROL
)
6167 txq
= adapter
->ring_feature
[RING_F_DCB
].indices
-1;
6169 txq
= (skb
->vlan_tci
& IXGBE_TX_FLAGS_VLAN_PRIO_MASK
)
6174 return skb_tx_hash(dev
, skb
);
6177 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
,
6178 struct net_device
*netdev
)
6180 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6181 struct ixgbe_ring
*tx_ring
;
6182 struct netdev_queue
*txq
;
6184 unsigned int tx_flags
= 0;
6190 if (adapter
->vlgrp
&& vlan_tx_tag_present(skb
)) {
6191 tx_flags
|= vlan_tx_tag_get(skb
);
6192 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6193 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6194 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6196 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6197 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6198 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6199 skb
->priority
!= TC_PRIO_CONTROL
) {
6200 tx_flags
|= ((skb
->queue_mapping
& 0x7) << 13);
6201 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6202 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6205 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6208 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
6209 #ifdef CONFIG_IXGBE_DCB
6210 /* for FCoE with DCB, we force the priority to what
6211 * was specified by the switch */
6212 if ((skb
->protocol
== htons(ETH_P_FCOE
)) ||
6213 (skb
->protocol
== htons(ETH_P_FIP
))) {
6214 tx_flags
&= ~(IXGBE_TX_FLAGS_VLAN_PRIO_MASK
6215 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6216 tx_flags
|= ((adapter
->fcoe
.up
<< 13)
6217 << IXGBE_TX_FLAGS_VLAN_SHIFT
);
6220 /* flag for FCoE offloads */
6221 if (skb
->protocol
== htons(ETH_P_FCOE
))
6222 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6226 /* four things can cause us to need a context descriptor */
6227 if (skb_is_gso(skb
) ||
6228 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6229 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6230 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6233 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6234 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6235 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6237 if (ixgbe_maybe_stop_tx(netdev
, tx_ring
, count
)) {
6239 return NETDEV_TX_BUSY
;
6242 first
= tx_ring
->next_to_use
;
6243 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6245 /* setup tx offload for FCoE */
6246 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6248 dev_kfree_skb_any(skb
);
6249 return NETDEV_TX_OK
;
6252 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6253 #endif /* IXGBE_FCOE */
6255 if (skb
->protocol
== htons(ETH_P_IP
))
6256 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6257 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6259 dev_kfree_skb_any(skb
);
6260 return NETDEV_TX_OK
;
6264 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6265 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
) &&
6266 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6267 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6270 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
);
6272 /* add the ATR filter if ATR is on */
6273 if (tx_ring
->atr_sample_rate
) {
6274 ++tx_ring
->atr_count
;
6275 if ((tx_ring
->atr_count
>= tx_ring
->atr_sample_rate
) &&
6276 test_bit(__IXGBE_FDIR_INIT_DONE
,
6277 &tx_ring
->reinit_state
)) {
6278 ixgbe_atr(adapter
, skb
, tx_ring
->queue_index
,
6280 tx_ring
->atr_count
= 0;
6283 txq
= netdev_get_tx_queue(netdev
, tx_ring
->queue_index
);
6284 txq
->tx_bytes
+= skb
->len
;
6286 ixgbe_tx_queue(adapter
, tx_ring
, tx_flags
, count
, skb
->len
,
6288 ixgbe_maybe_stop_tx(netdev
, tx_ring
, DESC_NEEDED
);
6291 dev_kfree_skb_any(skb
);
6292 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6293 tx_ring
->next_to_use
= first
;
6296 return NETDEV_TX_OK
;
6300 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6301 * @netdev: network interface device structure
6302 * @p: pointer to an address structure
6304 * Returns 0 on success, negative on failure
6306 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
6308 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6309 struct ixgbe_hw
*hw
= &adapter
->hw
;
6310 struct sockaddr
*addr
= p
;
6312 if (!is_valid_ether_addr(addr
->sa_data
))
6313 return -EADDRNOTAVAIL
;
6315 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
6316 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
6318 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
6325 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
6327 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6328 struct ixgbe_hw
*hw
= &adapter
->hw
;
6332 if (prtad
!= hw
->phy
.mdio
.prtad
)
6334 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
6340 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
6341 u16 addr
, u16 value
)
6343 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6344 struct ixgbe_hw
*hw
= &adapter
->hw
;
6346 if (prtad
!= hw
->phy
.mdio
.prtad
)
6348 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
6351 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
6353 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6355 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
6359 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6361 * @netdev: network interface device structure
6363 * Returns non-zero on failure
6365 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
6368 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6369 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6371 if (is_valid_ether_addr(mac
->san_addr
)) {
6373 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6380 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
6382 * @netdev: network interface device structure
6384 * Returns non-zero on failure
6386 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
6389 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6390 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
6392 if (is_valid_ether_addr(mac
->san_addr
)) {
6394 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
6400 #ifdef CONFIG_NET_POLL_CONTROLLER
6402 * Polling 'interrupt' - used by things like netconsole to send skbs
6403 * without having to re-enable interrupts. It's not called while
6404 * the interrupt routine is executing.
6406 static void ixgbe_netpoll(struct net_device
*netdev
)
6408 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6411 /* if interface is down do nothing */
6412 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6415 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
6416 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
6417 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
6418 for (i
= 0; i
< num_q_vectors
; i
++) {
6419 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
6420 ixgbe_msix_clean_many(0, q_vector
);
6423 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
6425 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
6429 static const struct net_device_ops ixgbe_netdev_ops
= {
6430 .ndo_open
= ixgbe_open
,
6431 .ndo_stop
= ixgbe_close
,
6432 .ndo_start_xmit
= ixgbe_xmit_frame
,
6433 .ndo_select_queue
= ixgbe_select_queue
,
6434 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
6435 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
6436 .ndo_validate_addr
= eth_validate_addr
,
6437 .ndo_set_mac_address
= ixgbe_set_mac
,
6438 .ndo_change_mtu
= ixgbe_change_mtu
,
6439 .ndo_tx_timeout
= ixgbe_tx_timeout
,
6440 .ndo_vlan_rx_register
= ixgbe_vlan_rx_register
,
6441 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
6442 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
6443 .ndo_do_ioctl
= ixgbe_ioctl
,
6444 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
6445 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
6446 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
6447 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
6448 #ifdef CONFIG_NET_POLL_CONTROLLER
6449 .ndo_poll_controller
= ixgbe_netpoll
,
6452 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
6453 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
6454 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
6455 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
6456 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
6457 #endif /* IXGBE_FCOE */
6460 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
6461 const struct ixgbe_info
*ii
)
6463 #ifdef CONFIG_PCI_IOV
6464 struct ixgbe_hw
*hw
= &adapter
->hw
;
6467 if (hw
->mac
.type
!= ixgbe_mac_82599EB
|| !max_vfs
)
6470 /* The 82599 supports up to 64 VFs per physical function
6471 * but this implementation limits allocation to 63 so that
6472 * basic networking resources are still available to the
6475 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
6476 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
6477 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
6479 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
6482 /* If call to enable VFs succeeded then allocate memory
6483 * for per VF control structures.
6486 kcalloc(adapter
->num_vfs
,
6487 sizeof(struct vf_data_storage
), GFP_KERNEL
);
6488 if (adapter
->vfinfo
) {
6489 /* Now that we're sure SR-IOV is enabled
6490 * and memory allocated set up the mailbox parameters
6492 ixgbe_init_mbx_params_pf(hw
);
6493 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
6494 sizeof(hw
->mbx
.ops
));
6496 /* Disable RSC when in SR-IOV mode */
6497 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
6498 IXGBE_FLAG2_RSC_ENABLED
);
6503 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
6504 "SRIOV disabled\n");
6505 pci_disable_sriov(adapter
->pdev
);
6508 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
6509 adapter
->num_vfs
= 0;
6510 #endif /* CONFIG_PCI_IOV */
6514 * ixgbe_probe - Device Initialization Routine
6515 * @pdev: PCI device information struct
6516 * @ent: entry in ixgbe_pci_tbl
6518 * Returns 0 on success, negative on failure
6520 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
6521 * The OS initialization, configuring of the adapter private structure,
6522 * and a hardware reset occur.
6524 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
6525 const struct pci_device_id
*ent
)
6527 struct net_device
*netdev
;
6528 struct ixgbe_adapter
*adapter
= NULL
;
6529 struct ixgbe_hw
*hw
;
6530 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
6531 static int cards_found
;
6532 int i
, err
, pci_using_dac
;
6533 unsigned int indices
= num_possible_cpus();
6539 err
= pci_enable_device_mem(pdev
);
6543 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
6544 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
6547 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
6549 err
= dma_set_coherent_mask(&pdev
->dev
,
6552 e_dev_err("No usable DMA configuration, "
6560 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
6561 IORESOURCE_MEM
), ixgbe_driver_name
);
6563 e_dev_err("pci_request_selected_regions failed 0x%x\n", err
);
6567 pci_enable_pcie_error_reporting(pdev
);
6569 pci_set_master(pdev
);
6570 pci_save_state(pdev
);
6572 if (ii
->mac
== ixgbe_mac_82598EB
)
6573 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
6575 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
6577 indices
= max_t(unsigned int, indices
, IXGBE_MAX_DCB_INDICES
);
6579 indices
+= min_t(unsigned int, num_possible_cpus(),
6580 IXGBE_MAX_FCOE_INDICES
);
6582 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
6585 goto err_alloc_etherdev
;
6588 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6590 pci_set_drvdata(pdev
, netdev
);
6591 adapter
= netdev_priv(netdev
);
6593 adapter
->netdev
= netdev
;
6594 adapter
->pdev
= pdev
;
6597 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
6599 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
6600 pci_resource_len(pdev
, 0));
6606 for (i
= 1; i
<= 5; i
++) {
6607 if (pci_resource_len(pdev
, i
) == 0)
6611 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
6612 ixgbe_set_ethtool_ops(netdev
);
6613 netdev
->watchdog_timeo
= 5 * HZ
;
6614 strcpy(netdev
->name
, pci_name(pdev
));
6616 adapter
->bd_number
= cards_found
;
6619 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
6620 hw
->mac
.type
= ii
->mac
;
6623 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
6624 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
6625 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
6626 if (!(eec
& (1 << 8)))
6627 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
6630 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
6631 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
6632 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
6633 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
6634 hw
->phy
.mdio
.mmds
= 0;
6635 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
6636 hw
->phy
.mdio
.dev
= netdev
;
6637 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
6638 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
6640 /* set up this timer and work struct before calling get_invariants
6641 * which might start the timer
6643 init_timer(&adapter
->sfp_timer
);
6644 adapter
->sfp_timer
.function
= &ixgbe_sfp_timer
;
6645 adapter
->sfp_timer
.data
= (unsigned long) adapter
;
6647 INIT_WORK(&adapter
->sfp_task
, ixgbe_sfp_task
);
6649 /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
6650 INIT_WORK(&adapter
->multispeed_fiber_task
, ixgbe_multispeed_fiber_task
);
6652 /* a new SFP+ module arrival, called from GPI SDP2 context */
6653 INIT_WORK(&adapter
->sfp_config_module_task
,
6654 ixgbe_sfp_config_module_task
);
6656 ii
->get_invariants(hw
);
6658 /* setup the private structure */
6659 err
= ixgbe_sw_init(adapter
);
6663 /* Make it possible the adapter to be woken up via WOL */
6664 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6665 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
6668 * If there is a fan on this device and it has failed log the
6671 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
6672 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
6673 if (esdp
& IXGBE_ESDP_SDP1
)
6674 e_crit(probe
, "Fan has stopped, replace the adapter\n");
6677 /* reset_hw fills in the perm_addr as well */
6678 hw
->phy
.reset_if_overtemp
= true;
6679 err
= hw
->mac
.ops
.reset_hw(hw
);
6680 hw
->phy
.reset_if_overtemp
= false;
6681 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
6682 hw
->mac
.type
== ixgbe_mac_82598EB
) {
6684 * Start a kernel thread to watch for a module to arrive.
6685 * Only do this for 82598, since 82599 will generate
6686 * interrupts on module arrival.
6688 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6689 mod_timer(&adapter
->sfp_timer
,
6690 round_jiffies(jiffies
+ (2 * HZ
)));
6692 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
6693 e_dev_err("failed to initialize because an unsupported SFP+ "
6694 "module type was detected.\n");
6695 e_dev_err("Reload the driver after installing a supported "
6699 e_dev_err("HW Init failed: %d\n", err
);
6703 ixgbe_probe_vf(adapter
, ii
);
6705 netdev
->features
= NETIF_F_SG
|
6707 NETIF_F_HW_VLAN_TX
|
6708 NETIF_F_HW_VLAN_RX
|
6709 NETIF_F_HW_VLAN_FILTER
;
6711 netdev
->features
|= NETIF_F_IPV6_CSUM
;
6712 netdev
->features
|= NETIF_F_TSO
;
6713 netdev
->features
|= NETIF_F_TSO6
;
6714 netdev
->features
|= NETIF_F_GRO
;
6716 if (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
)
6717 netdev
->features
|= NETIF_F_SCTP_CSUM
;
6719 netdev
->vlan_features
|= NETIF_F_TSO
;
6720 netdev
->vlan_features
|= NETIF_F_TSO6
;
6721 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
6722 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
6723 netdev
->vlan_features
|= NETIF_F_SG
;
6725 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6726 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
6727 IXGBE_FLAG_DCB_ENABLED
);
6728 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)
6729 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
6731 #ifdef CONFIG_IXGBE_DCB
6732 netdev
->dcbnl_ops
= &dcbnl_ops
;
6736 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
6737 if (hw
->mac
.ops
.get_device_caps
) {
6738 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
6739 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
6740 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
6743 #endif /* IXGBE_FCOE */
6745 netdev
->features
|= NETIF_F_HIGHDMA
;
6747 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
6748 netdev
->features
|= NETIF_F_LRO
;
6750 /* make sure the EEPROM is good */
6751 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
6752 e_dev_err("The EEPROM Checksum Is Not Valid\n");
6757 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6758 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
6760 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
6761 e_dev_err("invalid MAC address\n");
6766 /* power down the optics */
6767 if (hw
->phy
.multispeed_fiber
)
6768 hw
->mac
.ops
.disable_tx_laser(hw
);
6770 init_timer(&adapter
->watchdog_timer
);
6771 adapter
->watchdog_timer
.function
= &ixgbe_watchdog
;
6772 adapter
->watchdog_timer
.data
= (unsigned long)adapter
;
6774 INIT_WORK(&adapter
->reset_task
, ixgbe_reset_task
);
6775 INIT_WORK(&adapter
->watchdog_task
, ixgbe_watchdog_task
);
6777 err
= ixgbe_init_interrupt_scheme(adapter
);
6781 switch (pdev
->device
) {
6782 case IXGBE_DEV_ID_82599_KX4
:
6783 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
6784 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
6790 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
6792 /* pick up the PCI bus settings for reporting later */
6793 hw
->mac
.ops
.get_bus_info(hw
);
6795 /* print bus type/speed/width info */
6796 e_dev_info("(PCI Express:%s:%s) %pM\n",
6797 ((hw
->bus
.speed
== ixgbe_bus_speed_5000
) ? "5.0Gb/s":
6798 (hw
->bus
.speed
== ixgbe_bus_speed_2500
) ? "2.5Gb/s":"Unknown"),
6799 ((hw
->bus
.width
== ixgbe_bus_width_pcie_x8
) ? "Width x8" :
6800 (hw
->bus
.width
== ixgbe_bus_width_pcie_x4
) ? "Width x4" :
6801 (hw
->bus
.width
== ixgbe_bus_width_pcie_x1
) ? "Width x1" :
6804 ixgbe_read_pba_num_generic(hw
, &part_num
);
6805 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
6806 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, "
6807 "PBA No: %06x-%03x\n",
6808 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
6809 (part_num
>> 8), (part_num
& 0xff));
6811 e_dev_info("MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
6812 hw
->mac
.type
, hw
->phy
.type
,
6813 (part_num
>> 8), (part_num
& 0xff));
6815 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
6816 e_dev_warn("PCI-Express bandwidth available for this card is "
6817 "not sufficient for optimal performance.\n");
6818 e_dev_warn("For optimal performance a x8 PCI-Express slot "
6822 /* save off EEPROM version number */
6823 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
6825 /* reset the hardware with the new settings */
6826 err
= hw
->mac
.ops
.start_hw(hw
);
6828 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
6829 /* We are running on a pre-production device, log a warning */
6830 e_dev_warn("This device is a pre-production adapter/LOM. "
6831 "Please be aware there may be issues associated "
6832 "with your hardware. If you are experiencing "
6833 "problems please contact your Intel or hardware "
6834 "representative who provided you with this "
6837 strcpy(netdev
->name
, "eth%d");
6838 err
= register_netdev(netdev
);
6842 /* carrier off reporting is important to ethtool even BEFORE open */
6843 netif_carrier_off(netdev
);
6845 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6846 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6847 INIT_WORK(&adapter
->fdir_reinit_task
, ixgbe_fdir_reinit_task
);
6849 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
6850 INIT_WORK(&adapter
->check_overtemp_task
, ixgbe_check_overtemp_task
);
6851 #ifdef CONFIG_IXGBE_DCA
6852 if (dca_add_requester(&pdev
->dev
) == 0) {
6853 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
6854 ixgbe_setup_dca(adapter
);
6857 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
6858 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
6859 for (i
= 0; i
< adapter
->num_vfs
; i
++)
6860 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
6863 /* add san mac addr to netdev */
6864 ixgbe_add_sanmac_netdev(netdev
);
6866 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
6871 ixgbe_release_hw_control(adapter
);
6872 ixgbe_clear_interrupt_scheme(adapter
);
6875 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6876 ixgbe_disable_sriov(adapter
);
6877 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6878 del_timer_sync(&adapter
->sfp_timer
);
6879 cancel_work_sync(&adapter
->sfp_task
);
6880 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6881 cancel_work_sync(&adapter
->sfp_config_module_task
);
6882 iounmap(hw
->hw_addr
);
6884 free_netdev(netdev
);
6886 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6890 pci_disable_device(pdev
);
6895 * ixgbe_remove - Device Removal Routine
6896 * @pdev: PCI device information struct
6898 * ixgbe_remove is called by the PCI subsystem to alert the driver
6899 * that it should release a PCI device. The could be caused by a
6900 * Hot-Plug event, or because the driver is going to be removed from
6903 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
6905 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6906 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6908 set_bit(__IXGBE_DOWN
, &adapter
->state
);
6909 /* clear the module not found bit to make sure the worker won't
6912 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND
, &adapter
->state
);
6913 del_timer_sync(&adapter
->watchdog_timer
);
6915 del_timer_sync(&adapter
->sfp_timer
);
6916 cancel_work_sync(&adapter
->watchdog_task
);
6917 cancel_work_sync(&adapter
->sfp_task
);
6918 cancel_work_sync(&adapter
->multispeed_fiber_task
);
6919 cancel_work_sync(&adapter
->sfp_config_module_task
);
6920 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
6921 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
6922 cancel_work_sync(&adapter
->fdir_reinit_task
);
6923 flush_scheduled_work();
6925 #ifdef CONFIG_IXGBE_DCA
6926 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
6927 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
6928 dca_remove_requester(&pdev
->dev
);
6929 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
6934 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
6935 ixgbe_cleanup_fcoe(adapter
);
6937 #endif /* IXGBE_FCOE */
6939 /* remove the added san mac */
6940 ixgbe_del_sanmac_netdev(netdev
);
6942 if (netdev
->reg_state
== NETREG_REGISTERED
)
6943 unregister_netdev(netdev
);
6945 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
6946 ixgbe_disable_sriov(adapter
);
6948 ixgbe_clear_interrupt_scheme(adapter
);
6950 ixgbe_release_hw_control(adapter
);
6952 iounmap(adapter
->hw
.hw_addr
);
6953 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
6956 e_dev_info("complete\n");
6958 free_netdev(netdev
);
6960 pci_disable_pcie_error_reporting(pdev
);
6962 pci_disable_device(pdev
);
6966 * ixgbe_io_error_detected - called when PCI error is detected
6967 * @pdev: Pointer to PCI device
6968 * @state: The current pci connection state
6970 * This function is called after a PCI bus error affecting
6971 * this device has been detected.
6973 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
6974 pci_channel_state_t state
)
6976 struct net_device
*netdev
= pci_get_drvdata(pdev
);
6977 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6979 netif_device_detach(netdev
);
6981 if (state
== pci_channel_io_perm_failure
)
6982 return PCI_ERS_RESULT_DISCONNECT
;
6984 if (netif_running(netdev
))
6985 ixgbe_down(adapter
);
6986 pci_disable_device(pdev
);
6988 /* Request a slot reset. */
6989 return PCI_ERS_RESULT_NEED_RESET
;
6993 * ixgbe_io_slot_reset - called after the pci bus has been reset.
6994 * @pdev: Pointer to PCI device
6996 * Restart the card from scratch, as if from a cold-boot.
6998 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7000 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7001 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7002 pci_ers_result_t result
;
7005 if (pci_enable_device_mem(pdev
)) {
7006 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7007 result
= PCI_ERS_RESULT_DISCONNECT
;
7009 pci_set_master(pdev
);
7010 pci_restore_state(pdev
);
7011 pci_save_state(pdev
);
7013 pci_wake_from_d3(pdev
, false);
7015 ixgbe_reset(adapter
);
7016 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7017 result
= PCI_ERS_RESULT_RECOVERED
;
7020 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7022 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7023 "failed 0x%0x\n", err
);
7024 /* non-fatal, continue */
7031 * ixgbe_io_resume - called when traffic can start flowing again.
7032 * @pdev: Pointer to PCI device
7034 * This callback is called when the error recovery driver tells us that
7035 * its OK to resume normal operation.
7037 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7039 struct net_device
*netdev
= pci_get_drvdata(pdev
);
7040 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7042 if (netif_running(netdev
)) {
7043 if (ixgbe_up(adapter
)) {
7044 e_info(probe
, "ixgbe_up failed after reset\n");
7049 netif_device_attach(netdev
);
7052 static struct pci_error_handlers ixgbe_err_handler
= {
7053 .error_detected
= ixgbe_io_error_detected
,
7054 .slot_reset
= ixgbe_io_slot_reset
,
7055 .resume
= ixgbe_io_resume
,
7058 static struct pci_driver ixgbe_driver
= {
7059 .name
= ixgbe_driver_name
,
7060 .id_table
= ixgbe_pci_tbl
,
7061 .probe
= ixgbe_probe
,
7062 .remove
= __devexit_p(ixgbe_remove
),
7064 .suspend
= ixgbe_suspend
,
7065 .resume
= ixgbe_resume
,
7067 .shutdown
= ixgbe_shutdown
,
7068 .err_handler
= &ixgbe_err_handler
7072 * ixgbe_init_module - Driver Registration Routine
7074 * ixgbe_init_module is the first routine called when the driver is
7075 * loaded. All it does is register with the PCI subsystem.
7077 static int __init
ixgbe_init_module(void)
7080 pr_info("%s - version %s\n", ixgbe_driver_string
,
7081 ixgbe_driver_version
);
7082 pr_info("%s\n", ixgbe_copyright
);
7084 #ifdef CONFIG_IXGBE_DCA
7085 dca_register_notify(&dca_notifier
);
7088 ret
= pci_register_driver(&ixgbe_driver
);
7092 module_init(ixgbe_init_module
);
7095 * ixgbe_exit_module - Driver Exit Cleanup Routine
7097 * ixgbe_exit_module is called just before the driver is removed
7100 static void __exit
ixgbe_exit_module(void)
7102 #ifdef CONFIG_IXGBE_DCA
7103 dca_unregister_notify(&dca_notifier
);
7105 pci_unregister_driver(&ixgbe_driver
);
7108 #ifdef CONFIG_IXGBE_DCA
7109 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7114 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7115 __ixgbe_notify_dca
);
7117 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7120 #endif /* CONFIG_IXGBE_DCA */
7123 * ixgbe_get_hw_dev return device
7124 * used by hardware layer to print debugging information
7126 struct net_device
*ixgbe_get_hw_dev(struct ixgbe_hw
*hw
)
7128 struct ixgbe_adapter
*adapter
= hw
->back
;
7129 return adapter
->netdev
;
7132 module_exit(ixgbe_exit_module
);