1 /*******************************************************************************
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
35 #include <linux/interrupt.h>
37 #include <linux/tcp.h>
38 #include <linux/pkt_sched.h>
39 #include <linux/ipv6.h>
40 #include <linux/slab.h>
41 #include <net/checksum.h>
42 #include <net/ip6_checksum.h>
43 #include <linux/ethtool.h>
44 #include <linux/if_vlan.h>
45 #include <linux/prefetch.h>
46 #include <scsi/fc/fc_fcoe.h>
49 #include "ixgbe_common.h"
50 #include "ixgbe_dcb_82599.h"
51 #include "ixgbe_sriov.h"
53 char ixgbe_driver_name
[] = "ixgbe";
54 static const char ixgbe_driver_string
[] =
55 "Intel(R) 10 Gigabit PCI Express Network Driver";
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k" __stringify(KFIX)
62 const char ixgbe_driver_version
[] = DRV_VERSION
;
63 static const char ixgbe_copyright
[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
66 static const struct ixgbe_info
*ixgbe_info_tbl
[] = {
67 [board_82598
] = &ixgbe_82598_info
,
68 [board_82599
] = &ixgbe_82599_info
,
69 [board_X540
] = &ixgbe_X540_info
,
72 /* ixgbe_pci_tbl - PCI Device ID Table
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl
) = {
81 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598
),
83 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_DUAL_PORT
),
85 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AF_SINGLE_PORT
),
87 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT
),
89 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598AT2
),
91 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_CX4
),
93 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_CX4_DUAL_PORT
),
95 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_DA_DUAL_PORT
),
97 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM
),
99 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_XF_LR
),
101 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598EB_SFP_LOM
),
103 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82598_BX
),
105 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4
),
107 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_XAUI_LOM
),
109 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KR
),
111 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP
),
113 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_EM
),
115 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_KX4_MEZZ
),
117 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_CX4
),
119 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_BACKPLANE_FCOE
),
121 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_FCOE
),
123 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_T3_LOM
),
125 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_COMBO_BACKPLANE
),
127 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_X540T
),
129 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_SFP_SF2
),
131 {PCI_VDEVICE(INTEL
, IXGBE_DEV_ID_82599_LS
),
134 /* required last entry */
137 MODULE_DEVICE_TABLE(pci
, ixgbe_pci_tbl
);
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block
*, unsigned long event
,
142 static struct notifier_block dca_notifier
= {
143 .notifier_call
= ixgbe_notify_dca
,
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs
;
151 module_param(max_vfs
, uint
, 0);
152 MODULE_PARM_DESC(max_vfs
,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION
);
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter
*adapter
)
165 struct ixgbe_hw
*hw
= &adapter
->hw
;
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter
->pdev
);
175 /* turn off device IOV mode */
176 gcr
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
177 gcr
&= ~(IXGBE_GCR_EXT_SRIOV
);
178 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr
);
179 gpie
= IXGBE_READ_REG(hw
, IXGBE_GPIE
);
180 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
181 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
183 /* set default pool back to 0 */
184 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
185 vmdctl
&= ~IXGBE_VT_CTL_POOL_MASK
;
186 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
);
188 /* take a breather then clean up driver data */
191 kfree(adapter
->vfinfo
);
192 adapter
->vfinfo
= NULL
;
194 adapter
->num_vfs
= 0;
195 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter
*adapter
)
200 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
))
202 schedule_work(&adapter
->service_task
);
205 static void ixgbe_service_event_complete(struct ixgbe_adapter
*adapter
)
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
));
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
214 struct ixgbe_reg_info
{
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl
[] = {
221 /* General Registers */
222 {IXGBE_CTRL
, "CTRL"},
223 {IXGBE_STATUS
, "STATUS"},
224 {IXGBE_CTRL_EXT
, "CTRL_EXT"},
226 /* Interrupt Registers */
227 {IXGBE_EICR
, "EICR"},
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
247 /* List Terminator */
253 * ixgbe_regdump - register printout routine
255 static void ixgbe_regdump(struct ixgbe_hw
*hw
, struct ixgbe_reg_info
*reginfo
)
261 switch (reginfo
->ofs
) {
262 case IXGBE_SRRCTL(0):
263 for (i
= 0; i
< 64; i
++)
264 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_SRRCTL(i
));
266 case IXGBE_DCA_RXCTRL(0):
267 for (i
= 0; i
< 64; i
++)
268 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(i
));
271 for (i
= 0; i
< 64; i
++)
272 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDLEN(i
));
275 for (i
= 0; i
< 64; i
++)
276 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDH(i
));
279 for (i
= 0; i
< 64; i
++)
280 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDT(i
));
282 case IXGBE_RXDCTL(0):
283 for (i
= 0; i
< 64; i
++)
284 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RXDCTL(i
));
287 for (i
= 0; i
< 64; i
++)
288 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAL(i
));
291 for (i
= 0; i
< 64; i
++)
292 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_RDBAH(i
));
295 for (i
= 0; i
< 64; i
++)
296 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAL(i
));
299 for (i
= 0; i
< 64; i
++)
300 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDBAH(i
));
303 for (i
= 0; i
< 64; i
++)
304 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDLEN(i
));
307 for (i
= 0; i
< 64; i
++)
308 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDH(i
));
311 for (i
= 0; i
< 64; i
++)
312 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TDT(i
));
314 case IXGBE_TXDCTL(0):
315 for (i
= 0; i
< 64; i
++)
316 regs
[i
] = IXGBE_READ_REG(hw
, IXGBE_TXDCTL(i
));
319 pr_info("%-15s %08x\n", reginfo
->name
,
320 IXGBE_READ_REG(hw
, reginfo
->ofs
));
324 for (i
= 0; i
< 8; i
++) {
325 snprintf(rname
, 16, "%s[%d-%d]", reginfo
->name
, i
*8, i
*8+7);
326 pr_err("%-15s", rname
);
327 for (j
= 0; j
< 8; j
++)
328 pr_cont(" %08x", regs
[i
*8+j
]);
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
337 static void ixgbe_dump(struct ixgbe_adapter
*adapter
)
339 struct net_device
*netdev
= adapter
->netdev
;
340 struct ixgbe_hw
*hw
= &adapter
->hw
;
341 struct ixgbe_reg_info
*reginfo
;
343 struct ixgbe_ring
*tx_ring
;
344 struct ixgbe_tx_buffer
*tx_buffer_info
;
345 union ixgbe_adv_tx_desc
*tx_desc
;
346 struct my_u0
{ u64 a
; u64 b
; } *u0
;
347 struct ixgbe_ring
*rx_ring
;
348 union ixgbe_adv_rx_desc
*rx_desc
;
349 struct ixgbe_rx_buffer
*rx_buffer_info
;
353 if (!netif_msg_hw(adapter
))
356 /* Print netdevice Info */
358 dev_info(&adapter
->pdev
->dev
, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
368 /* Print Registers */
369 dev_info(&adapter
->pdev
->dev
, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo
= (struct ixgbe_reg_info
*)ixgbe_reg_info_tbl
;
372 reginfo
->name
; reginfo
++) {
373 ixgbe_regdump(hw
, reginfo
);
376 /* Print TX Ring Summary */
377 if (!netdev
|| !netif_running(netdev
))
380 dev_info(&adapter
->pdev
->dev
, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
383 tx_ring
= adapter
->tx_ring
[n
];
385 &tx_ring
->tx_buffer_info
[tx_ring
->next_to_clean
];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n
, tx_ring
->next_to_use
, tx_ring
->next_to_clean
,
388 (u64
)tx_buffer_info
->dma
,
389 tx_buffer_info
->length
,
390 tx_buffer_info
->next_to_watch
,
391 (u64
)tx_buffer_info
->time_stamp
);
395 if (!netif_msg_tx_done(adapter
))
396 goto rx_ring_summary
;
398 dev_info(&adapter
->pdev
->dev
, "TX Rings Dump\n");
400 /* Transmit Descriptor Formats
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
411 for (n
= 0; n
< adapter
->num_tx_queues
; n
++) {
412 tx_ring
= adapter
->tx_ring
[n
];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring
->queue_index
);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
420 for (i
= 0; tx_ring
->desc
&& (i
< tx_ring
->count
); i
++) {
421 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
422 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
423 u0
= (struct my_u0
*)tx_desc
;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i
,
428 (u64
)tx_buffer_info
->dma
,
429 tx_buffer_info
->length
,
430 tx_buffer_info
->next_to_watch
,
431 (u64
)tx_buffer_info
->time_stamp
,
432 tx_buffer_info
->skb
);
433 if (i
== tx_ring
->next_to_use
&&
434 i
== tx_ring
->next_to_clean
)
436 else if (i
== tx_ring
->next_to_use
)
438 else if (i
== tx_ring
->next_to_clean
)
443 if (netif_msg_pktdata(adapter
) &&
444 tx_buffer_info
->dma
!= 0)
445 print_hex_dump(KERN_INFO
, "",
446 DUMP_PREFIX_ADDRESS
, 16, 1,
447 phys_to_virt(tx_buffer_info
->dma
),
448 tx_buffer_info
->length
, true);
452 /* Print RX Rings Summary */
454 dev_info(&adapter
->pdev
->dev
, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
457 rx_ring
= adapter
->rx_ring
[n
];
458 pr_info("%5d %5X %5X\n",
459 n
, rx_ring
->next_to_use
, rx_ring
->next_to_clean
);
463 if (!netif_msg_rx_status(adapter
))
466 dev_info(&adapter
->pdev
->dev
, "RX Rings Dump\n");
468 /* Advanced Receive Descriptor (Read) Format
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
477 * Advanced Receive Descriptor (Write-Back) Format
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
488 for (n
= 0; n
< adapter
->num_rx_queues
; n
++) {
489 rx_ring
= adapter
->rx_ring
[n
];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring
->queue_index
);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
500 for (i
= 0; i
< rx_ring
->count
; i
++) {
501 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
502 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
503 u0
= (struct my_u0
*)rx_desc
;
504 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
505 if (staterr
& IXGBE_RXD_STAT_DD
) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i
,
511 rx_buffer_info
->skb
);
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i
,
517 (u64
)rx_buffer_info
->dma
,
518 rx_buffer_info
->skb
);
520 if (netif_msg_pktdata(adapter
)) {
521 print_hex_dump(KERN_INFO
, "",
522 DUMP_PREFIX_ADDRESS
, 16, 1,
523 phys_to_virt(rx_buffer_info
->dma
),
524 rx_ring
->rx_buf_len
, true);
526 if (rx_ring
->rx_buf_len
527 < IXGBE_RXBUFFER_2048
)
528 print_hex_dump(KERN_INFO
, "",
529 DUMP_PREFIX_ADDRESS
, 16, 1,
531 rx_buffer_info
->page_dma
+
532 rx_buffer_info
->page_offset
538 if (i
== rx_ring
->next_to_use
)
540 else if (i
== rx_ring
->next_to_clean
)
552 static void ixgbe_release_hw_control(struct ixgbe_adapter
*adapter
)
556 /* Let firmware take over control of h/w */
557 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
558 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
559 ctrl_ext
& ~IXGBE_CTRL_EXT_DRV_LOAD
);
562 static void ixgbe_get_hw_control(struct ixgbe_adapter
*adapter
)
566 /* Let firmware know the driver has taken over */
567 ctrl_ext
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_CTRL_EXT
);
568 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_CTRL_EXT
,
569 ctrl_ext
| IXGBE_CTRL_EXT_DRV_LOAD
);
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
580 static void ixgbe_set_ivar(struct ixgbe_adapter
*adapter
, s8 direction
,
581 u8 queue
, u8 msix_vector
)
584 struct ixgbe_hw
*hw
= &adapter
->hw
;
585 switch (hw
->mac
.type
) {
586 case ixgbe_mac_82598EB
:
587 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
590 index
= (((direction
* 64) + queue
) >> 2) & 0x1F;
591 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(index
));
592 ivar
&= ~(0xFF << (8 * (queue
& 0x3)));
593 ivar
|= (msix_vector
<< (8 * (queue
& 0x3)));
594 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(index
), ivar
);
596 case ixgbe_mac_82599EB
:
598 if (direction
== -1) {
600 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
601 index
= ((queue
& 1) * 8);
602 ivar
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_IVAR_MISC
);
603 ivar
&= ~(0xFF << index
);
604 ivar
|= (msix_vector
<< index
);
605 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_IVAR_MISC
, ivar
);
608 /* tx or rx causes */
609 msix_vector
|= IXGBE_IVAR_ALLOC_VAL
;
610 index
= ((16 * (queue
& 1)) + (8 * direction
));
611 ivar
= IXGBE_READ_REG(hw
, IXGBE_IVAR(queue
>> 1));
612 ivar
&= ~(0xFF << index
);
613 ivar
|= (msix_vector
<< index
);
614 IXGBE_WRITE_REG(hw
, IXGBE_IVAR(queue
>> 1), ivar
);
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter
*adapter
,
627 switch (adapter
->hw
.mac
.type
) {
628 case ixgbe_mac_82598EB
:
629 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
630 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS
, mask
);
632 case ixgbe_mac_82599EB
:
634 mask
= (qmask
& 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(0), mask
);
636 mask
= (qmask
>> 32);
637 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EICS_EX(1), mask
);
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring
*tx_ring
,
645 struct ixgbe_tx_buffer
*tx_buffer_info
)
647 if (tx_buffer_info
->dma
) {
648 if (tx_buffer_info
->mapped_as_page
)
649 dma_unmap_page(tx_ring
->dev
,
651 tx_buffer_info
->length
,
654 dma_unmap_single(tx_ring
->dev
,
656 tx_buffer_info
->length
,
658 tx_buffer_info
->dma
= 0;
660 if (tx_buffer_info
->skb
) {
661 dev_kfree_skb_any(tx_buffer_info
->skb
);
662 tx_buffer_info
->skb
= NULL
;
664 tx_buffer_info
->time_stamp
= 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
669 * ixgbe_dcb_txq_to_tc - convert a reg index to a traffic class
670 * @adapter: driver private struct
671 * @index: reg idx of queue to query (0-127)
673 * Helper function to determine the traffic index for a particular
676 * Returns : a tc index for use in range 0-7, or 0-3
678 static u8
ixgbe_dcb_txq_to_tc(struct ixgbe_adapter
*adapter
, u8 reg_idx
)
681 int dcb_i
= netdev_get_num_tc(adapter
->netdev
);
683 /* if DCB is not enabled the queues have no TC */
684 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
687 /* check valid range */
688 if (reg_idx
>= adapter
->hw
.mac
.max_tx_queues
)
691 switch (adapter
->hw
.mac
.type
) {
692 case ixgbe_mac_82598EB
:
696 if (dcb_i
!= 4 && dcb_i
!= 8)
699 /* if VMDq is enabled the lowest order bits determine TC */
700 if (adapter
->flags
& (IXGBE_FLAG_SRIOV_ENABLED
|
701 IXGBE_FLAG_VMDQ_ENABLED
)) {
702 tc
= reg_idx
& (dcb_i
- 1);
707 * Convert the reg_idx into the correct TC. This bitmask
708 * targets the last full 32 ring traffic class and assigns
709 * it a value of 1. From there the rest of the rings are
710 * based on shifting the mask further up to include the
711 * reg_idx / 16 and then reg_idx / 8. It assumes dcB_i
712 * will only ever be 8 or 4 and that reg_idx will never
713 * be greater then 128. The code without the power of 2
714 * optimizations would be:
715 * (((reg_idx % 32) + 32) * dcb_i) >> (9 - reg_idx / 32)
717 tc
= ((reg_idx
& 0X1F) + 0x20) * dcb_i
;
718 tc
>>= 9 - (reg_idx
>> 5);
724 static void ixgbe_update_xoff_received(struct ixgbe_adapter
*adapter
)
726 struct ixgbe_hw
*hw
= &adapter
->hw
;
727 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
732 if ((hw
->fc
.current_mode
== ixgbe_fc_full
) ||
733 (hw
->fc
.current_mode
== ixgbe_fc_rx_pause
)) {
734 switch (hw
->mac
.type
) {
735 case ixgbe_mac_82598EB
:
736 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXC
);
739 data
= IXGBE_READ_REG(hw
, IXGBE_LXOFFRXCNT
);
741 hwstats
->lxoffrxc
+= data
;
743 /* refill credits (no tx hang) if we received xoff */
747 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
748 clear_bit(__IXGBE_HANG_CHECK_ARMED
,
749 &adapter
->tx_ring
[i
]->state
);
751 } else if (!(adapter
->dcb_cfg
.pfc_mode_enable
))
754 /* update stats for each tc, only valid with PFC enabled */
755 for (i
= 0; i
< MAX_TX_PACKET_BUFFERS
; i
++) {
756 switch (hw
->mac
.type
) {
757 case ixgbe_mac_82598EB
:
758 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXC(i
));
761 xoff
[i
] = IXGBE_READ_REG(hw
, IXGBE_PXOFFRXCNT(i
));
763 hwstats
->pxoffrxc
[i
] += xoff
[i
];
766 /* disarm tx queues that have received xoff frames */
767 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
768 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
769 u32 tc
= ixgbe_dcb_txq_to_tc(adapter
, tx_ring
->reg_idx
);
772 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
776 static u64
ixgbe_get_tx_completed(struct ixgbe_ring
*ring
)
778 return ring
->tx_stats
.completed
;
781 static u64
ixgbe_get_tx_pending(struct ixgbe_ring
*ring
)
783 struct ixgbe_adapter
*adapter
= netdev_priv(ring
->netdev
);
784 struct ixgbe_hw
*hw
= &adapter
->hw
;
786 u32 head
= IXGBE_READ_REG(hw
, IXGBE_TDH(ring
->reg_idx
));
787 u32 tail
= IXGBE_READ_REG(hw
, IXGBE_TDT(ring
->reg_idx
));
790 return (head
< tail
) ?
791 tail
- head
: (tail
+ ring
->count
- head
);
796 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring
*tx_ring
)
798 u32 tx_done
= ixgbe_get_tx_completed(tx_ring
);
799 u32 tx_done_old
= tx_ring
->tx_stats
.tx_done_old
;
800 u32 tx_pending
= ixgbe_get_tx_pending(tx_ring
);
803 clear_check_for_tx_hang(tx_ring
);
806 * Check for a hung queue, but be thorough. This verifies
807 * that a transmit has been completed since the previous
808 * check AND there is at least one packet pending. The
809 * ARMED bit is set to indicate a potential hang. The
810 * bit is cleared if a pause frame is received to remove
811 * false hang detection due to PFC or 802.3x frames. By
812 * requiring this to fail twice we avoid races with
813 * pfc clearing the ARMED bit and conditions where we
814 * run the check_tx_hang logic with a transmit completion
815 * pending but without time to complete it yet.
817 if ((tx_done_old
== tx_done
) && tx_pending
) {
818 /* make sure it is true for two checks in a row */
819 ret
= test_and_set_bit(__IXGBE_HANG_CHECK_ARMED
,
822 /* update completed stats and continue */
823 tx_ring
->tx_stats
.tx_done_old
= tx_done
;
824 /* reset the countdown */
825 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &tx_ring
->state
);
831 #define IXGBE_MAX_TXD_PWR 14
832 #define IXGBE_MAX_DATA_PER_TXD (1 << IXGBE_MAX_TXD_PWR)
834 /* Tx Descriptors needed, worst case */
835 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
836 (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
837 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
838 MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
841 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
842 * @adapter: driver private struct
844 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter
*adapter
)
847 /* Do the reset outside of interrupt context */
848 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
849 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
850 ixgbe_service_event_schedule(adapter
);
855 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
856 * @q_vector: structure containing interrupt and ring information
857 * @tx_ring: tx ring to clean
859 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector
*q_vector
,
860 struct ixgbe_ring
*tx_ring
)
862 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
863 union ixgbe_adv_tx_desc
*tx_desc
, *eop_desc
;
864 struct ixgbe_tx_buffer
*tx_buffer_info
;
865 unsigned int total_bytes
= 0, total_packets
= 0;
866 u16 i
, eop
, count
= 0;
868 i
= tx_ring
->next_to_clean
;
869 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
870 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
872 while ((eop_desc
->wb
.status
& cpu_to_le32(IXGBE_TXD_STAT_DD
)) &&
873 (count
< tx_ring
->work_limit
)) {
874 bool cleaned
= false;
875 rmb(); /* read buffer_info after eop_desc */
876 for ( ; !cleaned
; count
++) {
877 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
878 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
880 tx_desc
->wb
.status
= 0;
881 cleaned
= (i
== eop
);
884 if (i
== tx_ring
->count
)
887 if (cleaned
&& tx_buffer_info
->skb
) {
888 total_bytes
+= tx_buffer_info
->bytecount
;
889 total_packets
+= tx_buffer_info
->gso_segs
;
892 ixgbe_unmap_and_free_tx_resource(tx_ring
,
896 tx_ring
->tx_stats
.completed
++;
897 eop
= tx_ring
->tx_buffer_info
[i
].next_to_watch
;
898 eop_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
901 tx_ring
->next_to_clean
= i
;
902 tx_ring
->total_bytes
+= total_bytes
;
903 tx_ring
->total_packets
+= total_packets
;
904 u64_stats_update_begin(&tx_ring
->syncp
);
905 tx_ring
->stats
.packets
+= total_packets
;
906 tx_ring
->stats
.bytes
+= total_bytes
;
907 u64_stats_update_end(&tx_ring
->syncp
);
909 if (check_for_tx_hang(tx_ring
) && ixgbe_check_tx_hang(tx_ring
)) {
910 /* schedule immediate reset if we believe we hung */
911 struct ixgbe_hw
*hw
= &adapter
->hw
;
912 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, eop
);
913 e_err(drv
, "Detected Tx Unit Hang\n"
915 " TDH, TDT <%x>, <%x>\n"
916 " next_to_use <%x>\n"
917 " next_to_clean <%x>\n"
918 "tx_buffer_info[next_to_clean]\n"
919 " time_stamp <%lx>\n"
921 tx_ring
->queue_index
,
922 IXGBE_READ_REG(hw
, IXGBE_TDH(tx_ring
->reg_idx
)),
923 IXGBE_READ_REG(hw
, IXGBE_TDT(tx_ring
->reg_idx
)),
924 tx_ring
->next_to_use
, eop
,
925 tx_ring
->tx_buffer_info
[eop
].time_stamp
, jiffies
);
927 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
930 "tx hang %d detected on queue %d, resetting adapter\n",
931 adapter
->tx_timeout_count
+ 1, tx_ring
->queue_index
);
933 /* schedule immediate reset if we believe we hung */
934 ixgbe_tx_timeout_reset(adapter
);
936 /* the adapter is about to reset, no point in enabling stuff */
940 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
941 if (unlikely(count
&& netif_carrier_ok(tx_ring
->netdev
) &&
942 (IXGBE_DESC_UNUSED(tx_ring
) >= TX_WAKE_THRESHOLD
))) {
943 /* Make sure that anybody stopping the queue after this
944 * sees the new next_to_clean.
947 if (__netif_subqueue_stopped(tx_ring
->netdev
, tx_ring
->queue_index
) &&
948 !test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
949 netif_wake_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
950 ++tx_ring
->tx_stats
.restart_queue
;
954 return count
< tx_ring
->work_limit
;
957 #ifdef CONFIG_IXGBE_DCA
958 static void ixgbe_update_rx_dca(struct ixgbe_adapter
*adapter
,
959 struct ixgbe_ring
*rx_ring
,
962 struct ixgbe_hw
*hw
= &adapter
->hw
;
964 u8 reg_idx
= rx_ring
->reg_idx
;
966 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
));
967 switch (hw
->mac
.type
) {
968 case ixgbe_mac_82598EB
:
969 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK
;
970 rxctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
972 case ixgbe_mac_82599EB
:
974 rxctrl
&= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599
;
975 rxctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
976 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599
);
981 rxctrl
|= IXGBE_DCA_RXCTRL_DESC_DCA_EN
;
982 rxctrl
|= IXGBE_DCA_RXCTRL_HEAD_DCA_EN
;
983 rxctrl
&= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN
);
984 IXGBE_WRITE_REG(hw
, IXGBE_DCA_RXCTRL(reg_idx
), rxctrl
);
987 static void ixgbe_update_tx_dca(struct ixgbe_adapter
*adapter
,
988 struct ixgbe_ring
*tx_ring
,
991 struct ixgbe_hw
*hw
= &adapter
->hw
;
993 u8 reg_idx
= tx_ring
->reg_idx
;
995 switch (hw
->mac
.type
) {
996 case ixgbe_mac_82598EB
:
997 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
));
998 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK
;
999 txctrl
|= dca3_get_tag(&adapter
->pdev
->dev
, cpu
);
1000 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
1001 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL(reg_idx
), txctrl
);
1003 case ixgbe_mac_82599EB
:
1004 case ixgbe_mac_X540
:
1005 txctrl
= IXGBE_READ_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
));
1006 txctrl
&= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599
;
1007 txctrl
|= (dca3_get_tag(&adapter
->pdev
->dev
, cpu
) <<
1008 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599
);
1009 txctrl
|= IXGBE_DCA_TXCTRL_DESC_DCA_EN
;
1010 IXGBE_WRITE_REG(hw
, IXGBE_DCA_TXCTRL_82599(reg_idx
), txctrl
);
1017 static void ixgbe_update_dca(struct ixgbe_q_vector
*q_vector
)
1019 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1020 int cpu
= get_cpu();
1024 if (q_vector
->cpu
== cpu
)
1027 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1028 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1029 ixgbe_update_tx_dca(adapter
, adapter
->tx_ring
[r_idx
], cpu
);
1030 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1034 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1035 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1036 ixgbe_update_rx_dca(adapter
, adapter
->rx_ring
[r_idx
], cpu
);
1037 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1041 q_vector
->cpu
= cpu
;
1046 static void ixgbe_setup_dca(struct ixgbe_adapter
*adapter
)
1051 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1054 /* always use CB2 mode, difference is masked in the CB driver */
1055 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 2);
1057 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
1058 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1062 for (i
= 0; i
< num_q_vectors
; i
++) {
1063 adapter
->q_vector
[i
]->cpu
= -1;
1064 ixgbe_update_dca(adapter
->q_vector
[i
]);
1068 static int __ixgbe_notify_dca(struct device
*dev
, void *data
)
1070 struct ixgbe_adapter
*adapter
= dev_get_drvdata(dev
);
1071 unsigned long event
= *(unsigned long *)data
;
1073 if (!(adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
))
1077 case DCA_PROVIDER_ADD
:
1078 /* if we're already enabled, don't do it again */
1079 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
1081 if (dca_add_requester(dev
) == 0) {
1082 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
1083 ixgbe_setup_dca(adapter
);
1086 /* Fall Through since DCA is disabled. */
1087 case DCA_PROVIDER_REMOVE
:
1088 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
1089 dca_remove_requester(dev
);
1090 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
1091 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
1098 #endif /* CONFIG_IXGBE_DCA */
1100 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc
*rx_desc
,
1101 struct sk_buff
*skb
)
1103 skb
->rxhash
= le32_to_cpu(rx_desc
->wb
.lower
.hi_dword
.rss
);
1107 * ixgbe_receive_skb - Send a completed packet up the stack
1108 * @adapter: board private structure
1109 * @skb: packet to send up
1110 * @status: hardware indication of status of receive
1111 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1112 * @rx_desc: rx descriptor
1114 static void ixgbe_receive_skb(struct ixgbe_q_vector
*q_vector
,
1115 struct sk_buff
*skb
, u8 status
,
1116 struct ixgbe_ring
*ring
,
1117 union ixgbe_adv_rx_desc
*rx_desc
)
1119 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1120 struct napi_struct
*napi
= &q_vector
->napi
;
1121 bool is_vlan
= (status
& IXGBE_RXD_STAT_VP
);
1122 u16 tag
= le16_to_cpu(rx_desc
->wb
.upper
.vlan
);
1124 if (is_vlan
&& (tag
& VLAN_VID_MASK
))
1125 __vlan_hwaccel_put_tag(skb
, tag
);
1127 if (!(adapter
->flags
& IXGBE_FLAG_IN_NETPOLL
))
1128 napi_gro_receive(napi
, skb
);
1134 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1135 * @adapter: address of board private structure
1136 * @status_err: hardware indication of status of receive
1137 * @skb: skb currently being received and modified
1139 static inline void ixgbe_rx_checksum(struct ixgbe_adapter
*adapter
,
1140 union ixgbe_adv_rx_desc
*rx_desc
,
1141 struct sk_buff
*skb
)
1143 u32 status_err
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1145 skb_checksum_none_assert(skb
);
1147 /* Rx csum disabled */
1148 if (!(adapter
->flags
& IXGBE_FLAG_RX_CSUM_ENABLED
))
1151 /* if IP and error */
1152 if ((status_err
& IXGBE_RXD_STAT_IPCS
) &&
1153 (status_err
& IXGBE_RXDADV_ERR_IPE
)) {
1154 adapter
->hw_csum_rx_error
++;
1158 if (!(status_err
& IXGBE_RXD_STAT_L4CS
))
1161 if (status_err
& IXGBE_RXDADV_ERR_TCPE
) {
1162 u16 pkt_info
= rx_desc
->wb
.lower
.lo_dword
.hs_rss
.pkt_info
;
1165 * 82599 errata, UDP frames with a 0 checksum can be marked as
1168 if ((pkt_info
& IXGBE_RXDADV_PKTTYPE_UDP
) &&
1169 (adapter
->hw
.mac
.type
== ixgbe_mac_82599EB
))
1172 adapter
->hw_csum_rx_error
++;
1176 /* It must be a TCP or UDP packet with a valid checksum */
1177 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1180 static inline void ixgbe_release_rx_desc(struct ixgbe_ring
*rx_ring
, u32 val
)
1183 * Force memory writes to complete before letting h/w
1184 * know there are new descriptors to fetch. (Only
1185 * applicable for weak-ordered memory model archs,
1189 writel(val
, rx_ring
->tail
);
1193 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1194 * @rx_ring: ring to place buffers on
1195 * @cleaned_count: number of buffers to replace
1197 void ixgbe_alloc_rx_buffers(struct ixgbe_ring
*rx_ring
, u16 cleaned_count
)
1199 union ixgbe_adv_rx_desc
*rx_desc
;
1200 struct ixgbe_rx_buffer
*bi
;
1201 struct sk_buff
*skb
;
1202 u16 i
= rx_ring
->next_to_use
;
1204 /* do nothing if no valid netdev defined */
1205 if (!rx_ring
->netdev
)
1208 while (cleaned_count
--) {
1209 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1210 bi
= &rx_ring
->rx_buffer_info
[i
];
1214 skb
= netdev_alloc_skb_ip_align(rx_ring
->netdev
,
1215 rx_ring
->rx_buf_len
);
1217 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1220 /* initialize queue mapping */
1221 skb_record_rx_queue(skb
, rx_ring
->queue_index
);
1226 bi
->dma
= dma_map_single(rx_ring
->dev
,
1228 rx_ring
->rx_buf_len
,
1230 if (dma_mapping_error(rx_ring
->dev
, bi
->dma
)) {
1231 rx_ring
->rx_stats
.alloc_rx_buff_failed
++;
1237 if (ring_is_ps_enabled(rx_ring
)) {
1239 bi
->page
= netdev_alloc_page(rx_ring
->netdev
);
1241 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1246 if (!bi
->page_dma
) {
1247 /* use a half page if we're re-using */
1248 bi
->page_offset
^= PAGE_SIZE
/ 2;
1249 bi
->page_dma
= dma_map_page(rx_ring
->dev
,
1254 if (dma_mapping_error(rx_ring
->dev
,
1256 rx_ring
->rx_stats
.alloc_rx_page_failed
++;
1262 /* Refresh the desc even if buffer_addrs didn't change
1263 * because each write-back erases this info. */
1264 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->page_dma
);
1265 rx_desc
->read
.hdr_addr
= cpu_to_le64(bi
->dma
);
1267 rx_desc
->read
.pkt_addr
= cpu_to_le64(bi
->dma
);
1268 rx_desc
->read
.hdr_addr
= 0;
1272 if (i
== rx_ring
->count
)
1277 if (rx_ring
->next_to_use
!= i
) {
1278 rx_ring
->next_to_use
= i
;
1279 ixgbe_release_rx_desc(rx_ring
, i
);
1283 static inline u16
ixgbe_get_hlen(union ixgbe_adv_rx_desc
*rx_desc
)
1285 /* HW will not DMA in data larger than the given buffer, even if it
1286 * parses the (NFS, of course) header to be larger. In that case, it
1287 * fills the header buffer and spills the rest into the page.
1289 u16 hdr_info
= le16_to_cpu(rx_desc
->wb
.lower
.lo_dword
.hs_rss
.hdr_info
);
1290 u16 hlen
= (hdr_info
& IXGBE_RXDADV_HDRBUFLEN_MASK
) >>
1291 IXGBE_RXDADV_HDRBUFLEN_SHIFT
;
1292 if (hlen
> IXGBE_RX_HDR_SIZE
)
1293 hlen
= IXGBE_RX_HDR_SIZE
;
1298 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1299 * @skb: pointer to the last skb in the rsc queue
1301 * This function changes a queue full of hw rsc buffers into a completed
1302 * packet. It uses the ->prev pointers to find the first packet and then
1303 * turns it into the frag list owner.
1305 static inline struct sk_buff
*ixgbe_transform_rsc_queue(struct sk_buff
*skb
)
1307 unsigned int frag_list_size
= 0;
1308 unsigned int skb_cnt
= 1;
1311 struct sk_buff
*prev
= skb
->prev
;
1312 frag_list_size
+= skb
->len
;
1318 skb_shinfo(skb
)->frag_list
= skb
->next
;
1320 skb
->len
+= frag_list_size
;
1321 skb
->data_len
+= frag_list_size
;
1322 skb
->truesize
+= frag_list_size
;
1323 IXGBE_RSC_CB(skb
)->skb_cnt
= skb_cnt
;
1328 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc
*rx_desc
)
1330 return !!(le32_to_cpu(rx_desc
->wb
.lower
.lo_dword
.data
) &
1331 IXGBE_RXDADV_RSCCNT_MASK
);
1334 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector
*q_vector
,
1335 struct ixgbe_ring
*rx_ring
,
1336 int *work_done
, int work_to_do
)
1338 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1339 union ixgbe_adv_rx_desc
*rx_desc
, *next_rxd
;
1340 struct ixgbe_rx_buffer
*rx_buffer_info
, *next_buffer
;
1341 struct sk_buff
*skb
;
1342 unsigned int total_rx_bytes
= 0, total_rx_packets
= 0;
1343 const int current_node
= numa_node_id();
1346 #endif /* IXGBE_FCOE */
1349 u16 cleaned_count
= 0;
1350 bool pkt_is_rsc
= false;
1352 i
= rx_ring
->next_to_clean
;
1353 rx_desc
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1354 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1356 while (staterr
& IXGBE_RXD_STAT_DD
) {
1359 rmb(); /* read descriptor and rx_buffer_info after status DD */
1361 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
1363 skb
= rx_buffer_info
->skb
;
1364 rx_buffer_info
->skb
= NULL
;
1365 prefetch(skb
->data
);
1367 if (ring_is_rsc_enabled(rx_ring
))
1368 pkt_is_rsc
= ixgbe_get_rsc_state(rx_desc
);
1370 /* if this is a skb from previous receive DMA will be 0 */
1371 if (rx_buffer_info
->dma
) {
1374 !(staterr
& IXGBE_RXD_STAT_EOP
) &&
1377 * When HWRSC is enabled, delay unmapping
1378 * of the first packet. It carries the
1379 * header information, HW may still
1380 * access the header after the writeback.
1381 * Only unmap it when EOP is reached
1383 IXGBE_RSC_CB(skb
)->delay_unmap
= true;
1384 IXGBE_RSC_CB(skb
)->dma
= rx_buffer_info
->dma
;
1386 dma_unmap_single(rx_ring
->dev
,
1387 rx_buffer_info
->dma
,
1388 rx_ring
->rx_buf_len
,
1391 rx_buffer_info
->dma
= 0;
1393 if (ring_is_ps_enabled(rx_ring
)) {
1394 hlen
= ixgbe_get_hlen(rx_desc
);
1395 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1397 hlen
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1402 /* assume packet split since header is unmapped */
1403 upper_len
= le16_to_cpu(rx_desc
->wb
.upper
.length
);
1407 dma_unmap_page(rx_ring
->dev
,
1408 rx_buffer_info
->page_dma
,
1411 rx_buffer_info
->page_dma
= 0;
1412 skb_fill_page_desc(skb
, skb_shinfo(skb
)->nr_frags
,
1413 rx_buffer_info
->page
,
1414 rx_buffer_info
->page_offset
,
1417 if ((page_count(rx_buffer_info
->page
) == 1) &&
1418 (page_to_nid(rx_buffer_info
->page
) == current_node
))
1419 get_page(rx_buffer_info
->page
);
1421 rx_buffer_info
->page
= NULL
;
1423 skb
->len
+= upper_len
;
1424 skb
->data_len
+= upper_len
;
1425 skb
->truesize
+= upper_len
;
1429 if (i
== rx_ring
->count
)
1432 next_rxd
= IXGBE_RX_DESC_ADV(rx_ring
, i
);
1437 u32 nextp
= (staterr
& IXGBE_RXDADV_NEXTP_MASK
) >>
1438 IXGBE_RXDADV_NEXTP_SHIFT
;
1439 next_buffer
= &rx_ring
->rx_buffer_info
[nextp
];
1441 next_buffer
= &rx_ring
->rx_buffer_info
[i
];
1444 if (!(staterr
& IXGBE_RXD_STAT_EOP
)) {
1445 if (ring_is_ps_enabled(rx_ring
)) {
1446 rx_buffer_info
->skb
= next_buffer
->skb
;
1447 rx_buffer_info
->dma
= next_buffer
->dma
;
1448 next_buffer
->skb
= skb
;
1449 next_buffer
->dma
= 0;
1451 skb
->next
= next_buffer
->skb
;
1452 skb
->next
->prev
= skb
;
1454 rx_ring
->rx_stats
.non_eop_descs
++;
1459 skb
= ixgbe_transform_rsc_queue(skb
);
1460 /* if we got here without RSC the packet is invalid */
1462 __pskb_trim(skb
, 0);
1463 rx_buffer_info
->skb
= skb
;
1468 if (ring_is_rsc_enabled(rx_ring
)) {
1469 if (IXGBE_RSC_CB(skb
)->delay_unmap
) {
1470 dma_unmap_single(rx_ring
->dev
,
1471 IXGBE_RSC_CB(skb
)->dma
,
1472 rx_ring
->rx_buf_len
,
1474 IXGBE_RSC_CB(skb
)->dma
= 0;
1475 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
1479 if (ring_is_ps_enabled(rx_ring
))
1480 rx_ring
->rx_stats
.rsc_count
+=
1481 skb_shinfo(skb
)->nr_frags
;
1483 rx_ring
->rx_stats
.rsc_count
+=
1484 IXGBE_RSC_CB(skb
)->skb_cnt
;
1485 rx_ring
->rx_stats
.rsc_flush
++;
1488 /* ERR_MASK will only have valid bits if EOP set */
1489 if (staterr
& IXGBE_RXDADV_ERR_FRAME_ERR_MASK
) {
1490 /* trim packet back to size 0 and recycle it */
1491 __pskb_trim(skb
, 0);
1492 rx_buffer_info
->skb
= skb
;
1496 ixgbe_rx_checksum(adapter
, rx_desc
, skb
);
1497 if (adapter
->netdev
->features
& NETIF_F_RXHASH
)
1498 ixgbe_rx_hash(rx_desc
, skb
);
1500 /* probably a little skewed due to removing CRC */
1501 total_rx_bytes
+= skb
->len
;
1504 skb
->protocol
= eth_type_trans(skb
, rx_ring
->netdev
);
1506 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1507 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
1508 ddp_bytes
= ixgbe_fcoe_ddp(adapter
, rx_desc
, skb
);
1512 #endif /* IXGBE_FCOE */
1513 ixgbe_receive_skb(q_vector
, skb
, staterr
, rx_ring
, rx_desc
);
1516 rx_desc
->wb
.upper
.status_error
= 0;
1519 if (*work_done
>= work_to_do
)
1522 /* return some buffers to hardware, one at a time is too slow */
1523 if (cleaned_count
>= IXGBE_RX_BUFFER_WRITE
) {
1524 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1528 /* use prefetched values */
1530 staterr
= le32_to_cpu(rx_desc
->wb
.upper
.status_error
);
1533 rx_ring
->next_to_clean
= i
;
1534 cleaned_count
= IXGBE_DESC_UNUSED(rx_ring
);
1537 ixgbe_alloc_rx_buffers(rx_ring
, cleaned_count
);
1540 /* include DDPed FCoE data */
1541 if (ddp_bytes
> 0) {
1544 mss
= rx_ring
->netdev
->mtu
- sizeof(struct fcoe_hdr
) -
1545 sizeof(struct fc_frame_header
) -
1546 sizeof(struct fcoe_crc_eof
);
1549 total_rx_bytes
+= ddp_bytes
;
1550 total_rx_packets
+= DIV_ROUND_UP(ddp_bytes
, mss
);
1552 #endif /* IXGBE_FCOE */
1554 rx_ring
->total_packets
+= total_rx_packets
;
1555 rx_ring
->total_bytes
+= total_rx_bytes
;
1556 u64_stats_update_begin(&rx_ring
->syncp
);
1557 rx_ring
->stats
.packets
+= total_rx_packets
;
1558 rx_ring
->stats
.bytes
+= total_rx_bytes
;
1559 u64_stats_update_end(&rx_ring
->syncp
);
1562 static int ixgbe_clean_rxonly(struct napi_struct
*, int);
1564 * ixgbe_configure_msix - Configure MSI-X hardware
1565 * @adapter: board private structure
1567 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1570 static void ixgbe_configure_msix(struct ixgbe_adapter
*adapter
)
1572 struct ixgbe_q_vector
*q_vector
;
1573 int i
, q_vectors
, v_idx
, r_idx
;
1576 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
1579 * Populate the IVAR table and set the ITR values to the
1580 * corresponding register.
1582 for (v_idx
= 0; v_idx
< q_vectors
; v_idx
++) {
1583 q_vector
= adapter
->q_vector
[v_idx
];
1584 /* XXX for_each_set_bit(...) */
1585 r_idx
= find_first_bit(q_vector
->rxr_idx
,
1586 adapter
->num_rx_queues
);
1588 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1589 u8 reg_idx
= adapter
->rx_ring
[r_idx
]->reg_idx
;
1590 ixgbe_set_ivar(adapter
, 0, reg_idx
, v_idx
);
1591 r_idx
= find_next_bit(q_vector
->rxr_idx
,
1592 adapter
->num_rx_queues
,
1595 r_idx
= find_first_bit(q_vector
->txr_idx
,
1596 adapter
->num_tx_queues
);
1598 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1599 u8 reg_idx
= adapter
->tx_ring
[r_idx
]->reg_idx
;
1600 ixgbe_set_ivar(adapter
, 1, reg_idx
, v_idx
);
1601 r_idx
= find_next_bit(q_vector
->txr_idx
,
1602 adapter
->num_tx_queues
,
1606 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
1608 q_vector
->eitr
= adapter
->tx_eitr_param
;
1609 else if (q_vector
->rxr_count
)
1611 q_vector
->eitr
= adapter
->rx_eitr_param
;
1613 ixgbe_write_eitr(q_vector
);
1614 /* If Flow Director is enabled, set interrupt affinity */
1615 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
1616 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
1618 * Allocate the affinity_hint cpumask, assign the mask
1619 * for this vector, and set our affinity_hint for
1622 if (!alloc_cpumask_var(&q_vector
->affinity_mask
,
1625 cpumask_set_cpu(v_idx
, q_vector
->affinity_mask
);
1626 irq_set_affinity_hint(adapter
->msix_entries
[v_idx
].vector
,
1627 q_vector
->affinity_mask
);
1631 switch (adapter
->hw
.mac
.type
) {
1632 case ixgbe_mac_82598EB
:
1633 ixgbe_set_ivar(adapter
, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX
,
1636 case ixgbe_mac_82599EB
:
1637 case ixgbe_mac_X540
:
1638 ixgbe_set_ivar(adapter
, -1, 1, v_idx
);
1644 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITR(v_idx
), 1950);
1646 /* set up to autoclear timer, and the vectors */
1647 mask
= IXGBE_EIMS_ENABLE_MASK
;
1648 if (adapter
->num_vfs
)
1649 mask
&= ~(IXGBE_EIMS_OTHER
|
1650 IXGBE_EIMS_MAILBOX
|
1653 mask
&= ~(IXGBE_EIMS_OTHER
| IXGBE_EIMS_LSC
);
1654 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIAC
, mask
);
1657 enum latency_range
{
1661 latency_invalid
= 255
1665 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1666 * @adapter: pointer to adapter
1667 * @eitr: eitr setting (ints per sec) to give last timeslice
1668 * @itr_setting: current throttle rate in ints/second
1669 * @packets: the number of packets during this measurement interval
1670 * @bytes: the number of bytes during this measurement interval
1672 * Stores a new ITR value based on packets and byte
1673 * counts during the last interrupt. The advantage of per interrupt
1674 * computation is faster updates and more accurate ITR for the current
1675 * traffic pattern. Constants in this function were computed
1676 * based on theoretical maximum wire speed and thresholds were set based
1677 * on testing data as well as attempting to minimize response time
1678 * while increasing bulk throughput.
1679 * this functionality is controlled by the InterruptThrottleRate module
1680 * parameter (see ixgbe_param.c)
1682 static u8
ixgbe_update_itr(struct ixgbe_adapter
*adapter
,
1683 u32 eitr
, u8 itr_setting
,
1684 int packets
, int bytes
)
1686 unsigned int retval
= itr_setting
;
1691 goto update_itr_done
;
1694 /* simple throttlerate management
1695 * 0-20MB/s lowest (100000 ints/s)
1696 * 20-100MB/s low (20000 ints/s)
1697 * 100-1249MB/s bulk (8000 ints/s)
1699 /* what was last interrupt timeslice? */
1700 timepassed_us
= 1000000/eitr
;
1701 bytes_perint
= bytes
/ timepassed_us
; /* bytes/usec */
1703 switch (itr_setting
) {
1704 case lowest_latency
:
1705 if (bytes_perint
> adapter
->eitr_low
)
1706 retval
= low_latency
;
1709 if (bytes_perint
> adapter
->eitr_high
)
1710 retval
= bulk_latency
;
1711 else if (bytes_perint
<= adapter
->eitr_low
)
1712 retval
= lowest_latency
;
1715 if (bytes_perint
<= adapter
->eitr_high
)
1716 retval
= low_latency
;
1725 * ixgbe_write_eitr - write EITR register in hardware specific way
1726 * @q_vector: structure containing interrupt and ring information
1728 * This function is made to be called by ethtool and by the driver
1729 * when it needs to update EITR registers at runtime. Hardware
1730 * specific quirks/differences are taken care of here.
1732 void ixgbe_write_eitr(struct ixgbe_q_vector
*q_vector
)
1734 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1735 struct ixgbe_hw
*hw
= &adapter
->hw
;
1736 int v_idx
= q_vector
->v_idx
;
1737 u32 itr_reg
= EITR_INTS_PER_SEC_TO_REG(q_vector
->eitr
);
1739 switch (adapter
->hw
.mac
.type
) {
1740 case ixgbe_mac_82598EB
:
1741 /* must write high and low 16 bits to reset counter */
1742 itr_reg
|= (itr_reg
<< 16);
1744 case ixgbe_mac_82599EB
:
1745 case ixgbe_mac_X540
:
1747 * 82599 and X540 can support a value of zero, so allow it for
1748 * max interrupt rate, but there is an errata where it can
1749 * not be zero with RSC
1752 !(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
))
1756 * set the WDIS bit to not clear the timer bits and cause an
1757 * immediate assertion of the interrupt
1759 itr_reg
|= IXGBE_EITR_CNT_WDIS
;
1764 IXGBE_WRITE_REG(hw
, IXGBE_EITR(v_idx
), itr_reg
);
1767 static void ixgbe_set_itr_msix(struct ixgbe_q_vector
*q_vector
)
1769 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
1772 u8 current_itr
, ret_itr
;
1774 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
1775 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
1776 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[r_idx
];
1777 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1779 tx_ring
->total_packets
,
1780 tx_ring
->total_bytes
);
1781 /* if the result for this queue would decrease interrupt
1782 * rate for this vector then use that result */
1783 q_vector
->tx_itr
= ((q_vector
->tx_itr
> ret_itr
) ?
1784 q_vector
->tx_itr
- 1 : ret_itr
);
1785 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
1789 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
1790 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
1791 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[r_idx
];
1792 ret_itr
= ixgbe_update_itr(adapter
, q_vector
->eitr
,
1794 rx_ring
->total_packets
,
1795 rx_ring
->total_bytes
);
1796 /* if the result for this queue would decrease interrupt
1797 * rate for this vector then use that result */
1798 q_vector
->rx_itr
= ((q_vector
->rx_itr
> ret_itr
) ?
1799 q_vector
->rx_itr
- 1 : ret_itr
);
1800 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
1804 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
1806 switch (current_itr
) {
1807 /* counts and packets in update_itr are dependent on these numbers */
1808 case lowest_latency
:
1812 new_itr
= 20000; /* aka hwitr = ~200 */
1820 if (new_itr
!= q_vector
->eitr
) {
1821 /* do an exponential smoothing */
1822 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
1824 /* save the algorithm value here, not the smoothed one */
1825 q_vector
->eitr
= new_itr
;
1827 ixgbe_write_eitr(q_vector
);
1832 * ixgbe_check_overtemp_subtask - check for over tempurature
1833 * @adapter: pointer to adapter
1835 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter
*adapter
)
1837 struct ixgbe_hw
*hw
= &adapter
->hw
;
1838 u32 eicr
= adapter
->interrupt_event
;
1840 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
1843 if (!(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1844 !(adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_EVENT
))
1847 adapter
->flags2
&= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1849 switch (hw
->device_id
) {
1850 case IXGBE_DEV_ID_82599_T3_LOM
:
1852 * Since the warning interrupt is for both ports
1853 * we don't have to check if:
1854 * - This interrupt wasn't for our port.
1855 * - We may have missed the interrupt so always have to
1856 * check if we got a LSC
1858 if (!(eicr
& IXGBE_EICR_GPI_SDP0
) &&
1859 !(eicr
& IXGBE_EICR_LSC
))
1862 if (!(eicr
& IXGBE_EICR_LSC
) && hw
->mac
.ops
.check_link
) {
1864 bool link_up
= false;
1866 hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
1872 /* Check if this is not due to overtemp */
1873 if (hw
->phy
.ops
.check_overtemp(hw
) != IXGBE_ERR_OVERTEMP
)
1878 if (!(eicr
& IXGBE_EICR_GPI_SDP0
))
1883 "Network adapter has been stopped because it has over heated. "
1884 "Restart the computer. If the problem persists, "
1885 "power off the system and replace the adapter\n");
1887 adapter
->interrupt_event
= 0;
1890 static void ixgbe_check_fan_failure(struct ixgbe_adapter
*adapter
, u32 eicr
)
1892 struct ixgbe_hw
*hw
= &adapter
->hw
;
1894 if ((adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) &&
1895 (eicr
& IXGBE_EICR_GPI_SDP1
)) {
1896 e_crit(probe
, "Fan has stopped, replace the adapter\n");
1897 /* write to clear the interrupt */
1898 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1902 static void ixgbe_check_sfp_event(struct ixgbe_adapter
*adapter
, u32 eicr
)
1904 struct ixgbe_hw
*hw
= &adapter
->hw
;
1906 if (eicr
& IXGBE_EICR_GPI_SDP2
) {
1907 /* Clear the interrupt */
1908 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP2
);
1909 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1910 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
1911 ixgbe_service_event_schedule(adapter
);
1915 if (eicr
& IXGBE_EICR_GPI_SDP1
) {
1916 /* Clear the interrupt */
1917 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, IXGBE_EICR_GPI_SDP1
);
1918 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1919 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
1920 ixgbe_service_event_schedule(adapter
);
1925 static void ixgbe_check_lsc(struct ixgbe_adapter
*adapter
)
1927 struct ixgbe_hw
*hw
= &adapter
->hw
;
1930 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
1931 adapter
->link_check_timeout
= jiffies
;
1932 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1933 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_LSC
);
1934 IXGBE_WRITE_FLUSH(hw
);
1935 ixgbe_service_event_schedule(adapter
);
1939 static irqreturn_t
ixgbe_msix_lsc(int irq
, void *data
)
1941 struct net_device
*netdev
= data
;
1942 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
1943 struct ixgbe_hw
*hw
= &adapter
->hw
;
1947 * Workaround for Silicon errata. Use clear-by-write instead
1948 * of clear-by-read. Reading with EICS will return the
1949 * interrupt causes without clearing, which later be done
1950 * with the write to EICR.
1952 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICS
);
1953 IXGBE_WRITE_REG(hw
, IXGBE_EICR
, eicr
);
1955 if (eicr
& IXGBE_EICR_LSC
)
1956 ixgbe_check_lsc(adapter
);
1958 if (eicr
& IXGBE_EICR_MAILBOX
)
1959 ixgbe_msg_task(adapter
);
1961 switch (hw
->mac
.type
) {
1962 case ixgbe_mac_82599EB
:
1963 case ixgbe_mac_X540
:
1964 /* Handle Flow Director Full threshold interrupt */
1965 if (eicr
& IXGBE_EICR_FLOW_DIR
) {
1966 int reinit_count
= 0;
1968 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
1969 struct ixgbe_ring
*ring
= adapter
->tx_ring
[i
];
1970 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE
,
1975 /* no more flow director interrupts until after init */
1976 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_EIMC_FLOW_DIR
);
1977 eicr
&= ~IXGBE_EICR_FLOW_DIR
;
1978 adapter
->flags2
|= IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
1979 ixgbe_service_event_schedule(adapter
);
1982 ixgbe_check_sfp_event(adapter
, eicr
);
1983 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
1984 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
1985 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
1986 adapter
->interrupt_event
= eicr
;
1987 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
1988 ixgbe_service_event_schedule(adapter
);
1996 ixgbe_check_fan_failure(adapter
, eicr
);
1998 /* re-enable the original interrupt state, no lsc, no queues */
1999 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2000 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, eicr
&
2001 ~(IXGBE_EIMS_LSC
| IXGBE_EIMS_RTX_QUEUE
));
2006 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter
*adapter
,
2010 struct ixgbe_hw
*hw
= &adapter
->hw
;
2012 switch (hw
->mac
.type
) {
2013 case ixgbe_mac_82598EB
:
2014 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
2015 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, mask
);
2017 case ixgbe_mac_82599EB
:
2018 case ixgbe_mac_X540
:
2019 mask
= (qmask
& 0xFFFFFFFF);
2021 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(0), mask
);
2022 mask
= (qmask
>> 32);
2024 IXGBE_WRITE_REG(hw
, IXGBE_EIMS_EX(1), mask
);
2029 /* skip the flush */
2032 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter
*adapter
,
2036 struct ixgbe_hw
*hw
= &adapter
->hw
;
2038 switch (hw
->mac
.type
) {
2039 case ixgbe_mac_82598EB
:
2040 mask
= (IXGBE_EIMS_RTX_QUEUE
& qmask
);
2041 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, mask
);
2043 case ixgbe_mac_82599EB
:
2044 case ixgbe_mac_X540
:
2045 mask
= (qmask
& 0xFFFFFFFF);
2047 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(0), mask
);
2048 mask
= (qmask
>> 32);
2050 IXGBE_WRITE_REG(hw
, IXGBE_EIMC_EX(1), mask
);
2055 /* skip the flush */
2058 static irqreturn_t
ixgbe_msix_clean_tx(int irq
, void *data
)
2060 struct ixgbe_q_vector
*q_vector
= data
;
2061 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2062 struct ixgbe_ring
*tx_ring
;
2065 if (!q_vector
->txr_count
)
2068 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2069 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2070 tx_ring
= adapter
->tx_ring
[r_idx
];
2071 tx_ring
->total_bytes
= 0;
2072 tx_ring
->total_packets
= 0;
2073 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2077 /* EIAM disabled interrupts (on this vector) for us */
2078 napi_schedule(&q_vector
->napi
);
2084 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2086 * @data: pointer to our q_vector struct for this interrupt vector
2088 static irqreturn_t
ixgbe_msix_clean_rx(int irq
, void *data
)
2090 struct ixgbe_q_vector
*q_vector
= data
;
2091 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2092 struct ixgbe_ring
*rx_ring
;
2096 #ifdef CONFIG_IXGBE_DCA
2097 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2098 ixgbe_update_dca(q_vector
);
2101 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2102 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2103 rx_ring
= adapter
->rx_ring
[r_idx
];
2104 rx_ring
->total_bytes
= 0;
2105 rx_ring
->total_packets
= 0;
2106 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2110 if (!q_vector
->rxr_count
)
2113 /* EIAM disabled interrupts (on this vector) for us */
2114 napi_schedule(&q_vector
->napi
);
2119 static irqreturn_t
ixgbe_msix_clean_many(int irq
, void *data
)
2121 struct ixgbe_q_vector
*q_vector
= data
;
2122 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2123 struct ixgbe_ring
*ring
;
2127 if (!q_vector
->txr_count
&& !q_vector
->rxr_count
)
2130 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2131 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2132 ring
= adapter
->tx_ring
[r_idx
];
2133 ring
->total_bytes
= 0;
2134 ring
->total_packets
= 0;
2135 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2139 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2140 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2141 ring
= adapter
->rx_ring
[r_idx
];
2142 ring
->total_bytes
= 0;
2143 ring
->total_packets
= 0;
2144 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2148 /* EIAM disabled interrupts (on this vector) for us */
2149 napi_schedule(&q_vector
->napi
);
2155 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2156 * @napi: napi struct with our devices info in it
2157 * @budget: amount of work driver is allowed to do this pass, in packets
2159 * This function is optimized for cleaning one queue only on a single
2162 static int ixgbe_clean_rxonly(struct napi_struct
*napi
, int budget
)
2164 struct ixgbe_q_vector
*q_vector
=
2165 container_of(napi
, struct ixgbe_q_vector
, napi
);
2166 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2167 struct ixgbe_ring
*rx_ring
= NULL
;
2171 #ifdef CONFIG_IXGBE_DCA
2172 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2173 ixgbe_update_dca(q_vector
);
2176 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2177 rx_ring
= adapter
->rx_ring
[r_idx
];
2179 ixgbe_clean_rx_irq(q_vector
, rx_ring
, &work_done
, budget
);
2181 /* If all Rx work done, exit the polling mode */
2182 if (work_done
< budget
) {
2183 napi_complete(napi
);
2184 if (adapter
->rx_itr_setting
& 1)
2185 ixgbe_set_itr_msix(q_vector
);
2186 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2187 ixgbe_irq_enable_queues(adapter
,
2188 ((u64
)1 << q_vector
->v_idx
));
2195 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2196 * @napi: napi struct with our devices info in it
2197 * @budget: amount of work driver is allowed to do this pass, in packets
2199 * This function will clean more than one rx queue associated with a
2202 static int ixgbe_clean_rxtx_many(struct napi_struct
*napi
, int budget
)
2204 struct ixgbe_q_vector
*q_vector
=
2205 container_of(napi
, struct ixgbe_q_vector
, napi
);
2206 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2207 struct ixgbe_ring
*ring
= NULL
;
2208 int work_done
= 0, i
;
2210 bool tx_clean_complete
= true;
2212 #ifdef CONFIG_IXGBE_DCA
2213 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2214 ixgbe_update_dca(q_vector
);
2217 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2218 for (i
= 0; i
< q_vector
->txr_count
; i
++) {
2219 ring
= adapter
->tx_ring
[r_idx
];
2220 tx_clean_complete
&= ixgbe_clean_tx_irq(q_vector
, ring
);
2221 r_idx
= find_next_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
,
2225 /* attempt to distribute budget to each queue fairly, but don't allow
2226 * the budget to go below 1 because we'll exit polling */
2227 budget
/= (q_vector
->rxr_count
?: 1);
2228 budget
= max(budget
, 1);
2229 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2230 for (i
= 0; i
< q_vector
->rxr_count
; i
++) {
2231 ring
= adapter
->rx_ring
[r_idx
];
2232 ixgbe_clean_rx_irq(q_vector
, ring
, &work_done
, budget
);
2233 r_idx
= find_next_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
,
2237 r_idx
= find_first_bit(q_vector
->rxr_idx
, adapter
->num_rx_queues
);
2238 ring
= adapter
->rx_ring
[r_idx
];
2239 /* If all Rx work done, exit the polling mode */
2240 if (work_done
< budget
) {
2241 napi_complete(napi
);
2242 if (adapter
->rx_itr_setting
& 1)
2243 ixgbe_set_itr_msix(q_vector
);
2244 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2245 ixgbe_irq_enable_queues(adapter
,
2246 ((u64
)1 << q_vector
->v_idx
));
2254 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2255 * @napi: napi struct with our devices info in it
2256 * @budget: amount of work driver is allowed to do this pass, in packets
2258 * This function is optimized for cleaning one queue only on a single
2261 static int ixgbe_clean_txonly(struct napi_struct
*napi
, int budget
)
2263 struct ixgbe_q_vector
*q_vector
=
2264 container_of(napi
, struct ixgbe_q_vector
, napi
);
2265 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
2266 struct ixgbe_ring
*tx_ring
= NULL
;
2270 #ifdef CONFIG_IXGBE_DCA
2271 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
2272 ixgbe_update_dca(q_vector
);
2275 r_idx
= find_first_bit(q_vector
->txr_idx
, adapter
->num_tx_queues
);
2276 tx_ring
= adapter
->tx_ring
[r_idx
];
2278 if (!ixgbe_clean_tx_irq(q_vector
, tx_ring
))
2281 /* If all Tx work done, exit the polling mode */
2282 if (work_done
< budget
) {
2283 napi_complete(napi
);
2284 if (adapter
->tx_itr_setting
& 1)
2285 ixgbe_set_itr_msix(q_vector
);
2286 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2287 ixgbe_irq_enable_queues(adapter
,
2288 ((u64
)1 << q_vector
->v_idx
));
2294 static inline void map_vector_to_rxq(struct ixgbe_adapter
*a
, int v_idx
,
2297 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2298 struct ixgbe_ring
*rx_ring
= a
->rx_ring
[r_idx
];
2300 set_bit(r_idx
, q_vector
->rxr_idx
);
2301 q_vector
->rxr_count
++;
2302 rx_ring
->q_vector
= q_vector
;
2305 static inline void map_vector_to_txq(struct ixgbe_adapter
*a
, int v_idx
,
2308 struct ixgbe_q_vector
*q_vector
= a
->q_vector
[v_idx
];
2309 struct ixgbe_ring
*tx_ring
= a
->tx_ring
[t_idx
];
2311 set_bit(t_idx
, q_vector
->txr_idx
);
2312 q_vector
->txr_count
++;
2313 tx_ring
->q_vector
= q_vector
;
2317 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2318 * @adapter: board private structure to initialize
2320 * This function maps descriptor rings to the queue-specific vectors
2321 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2322 * one vector per ring/queue, but on a constrained vector budget, we
2323 * group the rings as "efficiently" as possible. You would add new
2324 * mapping configurations in here.
2326 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter
*adapter
)
2330 int rxr_idx
= 0, txr_idx
= 0;
2331 int rxr_remaining
= adapter
->num_rx_queues
;
2332 int txr_remaining
= adapter
->num_tx_queues
;
2337 /* No mapping required if MSI-X is disabled. */
2338 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
2341 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2344 * The ideal configuration...
2345 * We have enough vectors to map one per queue.
2347 if (q_vectors
== adapter
->num_rx_queues
+ adapter
->num_tx_queues
) {
2348 for (; rxr_idx
< rxr_remaining
; v_start
++, rxr_idx
++)
2349 map_vector_to_rxq(adapter
, v_start
, rxr_idx
);
2351 for (; txr_idx
< txr_remaining
; v_start
++, txr_idx
++)
2352 map_vector_to_txq(adapter
, v_start
, txr_idx
);
2358 * If we don't have enough vectors for a 1-to-1
2359 * mapping, we'll have to group them so there are
2360 * multiple queues per vector.
2362 /* Re-adjusting *qpv takes care of the remainder. */
2363 for (i
= v_start
; i
< q_vectors
; i
++) {
2364 rqpv
= DIV_ROUND_UP(rxr_remaining
, q_vectors
- i
);
2365 for (j
= 0; j
< rqpv
; j
++) {
2366 map_vector_to_rxq(adapter
, i
, rxr_idx
);
2370 tqpv
= DIV_ROUND_UP(txr_remaining
, q_vectors
- i
);
2371 for (j
= 0; j
< tqpv
; j
++) {
2372 map_vector_to_txq(adapter
, i
, txr_idx
);
2382 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2383 * @adapter: board private structure
2385 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2386 * interrupts from the kernel.
2388 static int ixgbe_request_msix_irqs(struct ixgbe_adapter
*adapter
)
2390 struct net_device
*netdev
= adapter
->netdev
;
2391 irqreturn_t (*handler
)(int, void *);
2392 int i
, vector
, q_vectors
, err
;
2395 /* Decrement for Other and TCP Timer vectors */
2396 q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2398 err
= ixgbe_map_rings_to_vectors(adapter
);
2402 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count) \
2403 ? &ixgbe_msix_clean_many : \
2404 (_v)->rxr_count ? &ixgbe_msix_clean_rx : \
2405 (_v)->txr_count ? &ixgbe_msix_clean_tx : \
2407 for (vector
= 0; vector
< q_vectors
; vector
++) {
2408 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[vector
];
2409 handler
= SET_HANDLER(q_vector
);
2411 if (handler
== &ixgbe_msix_clean_rx
) {
2412 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2413 "%s-%s-%d", netdev
->name
, "rx", ri
++);
2414 } else if (handler
== &ixgbe_msix_clean_tx
) {
2415 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2416 "%s-%s-%d", netdev
->name
, "tx", ti
++);
2417 } else if (handler
== &ixgbe_msix_clean_many
) {
2418 snprintf(q_vector
->name
, sizeof(q_vector
->name
) - 1,
2419 "%s-%s-%d", netdev
->name
, "TxRx", ri
++);
2422 /* skip this unused q_vector */
2425 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2426 handler
, 0, q_vector
->name
,
2429 e_err(probe
, "request_irq failed for MSIX interrupt "
2430 "Error: %d\n", err
);
2431 goto free_queue_irqs
;
2435 sprintf(adapter
->lsc_int_name
, "%s:lsc", netdev
->name
);
2436 err
= request_irq(adapter
->msix_entries
[vector
].vector
,
2437 ixgbe_msix_lsc
, 0, adapter
->lsc_int_name
, netdev
);
2439 e_err(probe
, "request_irq for msix_lsc failed: %d\n", err
);
2440 goto free_queue_irqs
;
2446 for (i
= vector
- 1; i
>= 0; i
--)
2447 free_irq(adapter
->msix_entries
[--vector
].vector
,
2448 adapter
->q_vector
[i
]);
2449 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
2450 pci_disable_msix(adapter
->pdev
);
2451 kfree(adapter
->msix_entries
);
2452 adapter
->msix_entries
= NULL
;
2456 static void ixgbe_set_itr(struct ixgbe_adapter
*adapter
)
2458 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2459 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[0];
2460 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[0];
2461 u32 new_itr
= q_vector
->eitr
;
2464 q_vector
->tx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2466 tx_ring
->total_packets
,
2467 tx_ring
->total_bytes
);
2468 q_vector
->rx_itr
= ixgbe_update_itr(adapter
, new_itr
,
2470 rx_ring
->total_packets
,
2471 rx_ring
->total_bytes
);
2473 current_itr
= max(q_vector
->rx_itr
, q_vector
->tx_itr
);
2475 switch (current_itr
) {
2476 /* counts and packets in update_itr are dependent on these numbers */
2477 case lowest_latency
:
2481 new_itr
= 20000; /* aka hwitr = ~200 */
2490 if (new_itr
!= q_vector
->eitr
) {
2491 /* do an exponential smoothing */
2492 new_itr
= ((q_vector
->eitr
* 9) + new_itr
)/10;
2494 /* save the algorithm value here */
2495 q_vector
->eitr
= new_itr
;
2497 ixgbe_write_eitr(q_vector
);
2502 * ixgbe_irq_enable - Enable default interrupt generation settings
2503 * @adapter: board private structure
2505 static inline void ixgbe_irq_enable(struct ixgbe_adapter
*adapter
, bool queues
,
2510 mask
= (IXGBE_EIMS_ENABLE_MASK
& ~IXGBE_EIMS_RTX_QUEUE
);
2511 if (adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
)
2512 mask
|= IXGBE_EIMS_GPI_SDP0
;
2513 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
2514 mask
|= IXGBE_EIMS_GPI_SDP1
;
2515 switch (adapter
->hw
.mac
.type
) {
2516 case ixgbe_mac_82599EB
:
2517 case ixgbe_mac_X540
:
2518 mask
|= IXGBE_EIMS_ECC
;
2519 mask
|= IXGBE_EIMS_GPI_SDP1
;
2520 mask
|= IXGBE_EIMS_GPI_SDP2
;
2521 if (adapter
->num_vfs
)
2522 mask
|= IXGBE_EIMS_MAILBOX
;
2527 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
2528 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
2529 mask
|= IXGBE_EIMS_FLOW_DIR
;
2531 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMS
, mask
);
2533 ixgbe_irq_enable_queues(adapter
, ~0);
2535 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2537 if (adapter
->num_vfs
> 32) {
2538 u32 eitrsel
= (1 << (adapter
->num_vfs
- 32)) - 1;
2539 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, eitrsel
);
2544 * ixgbe_intr - legacy mode Interrupt Handler
2545 * @irq: interrupt number
2546 * @data: pointer to a network interface device structure
2548 static irqreturn_t
ixgbe_intr(int irq
, void *data
)
2550 struct net_device
*netdev
= data
;
2551 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
2552 struct ixgbe_hw
*hw
= &adapter
->hw
;
2553 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[0];
2557 * Workaround for silicon errata on 82598. Mask the interrupts
2558 * before the read of EICR.
2560 IXGBE_WRITE_REG(hw
, IXGBE_EIMC
, IXGBE_IRQ_CLEAR_MASK
);
2562 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2563 * therefore no explict interrupt disable is necessary */
2564 eicr
= IXGBE_READ_REG(hw
, IXGBE_EICR
);
2567 * shared interrupt alert!
2568 * make sure interrupts are enabled because the read will
2569 * have disabled interrupts due to EIAM
2570 * finish the workaround of silicon errata on 82598. Unmask
2571 * the interrupt that we masked before the EICR read.
2573 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2574 ixgbe_irq_enable(adapter
, true, true);
2575 return IRQ_NONE
; /* Not our interrupt */
2578 if (eicr
& IXGBE_EICR_LSC
)
2579 ixgbe_check_lsc(adapter
);
2581 switch (hw
->mac
.type
) {
2582 case ixgbe_mac_82599EB
:
2583 ixgbe_check_sfp_event(adapter
, eicr
);
2584 if ((adapter
->flags2
& IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
) &&
2585 ((eicr
& IXGBE_EICR_GPI_SDP0
) || (eicr
& IXGBE_EICR_LSC
))) {
2586 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
)) {
2587 adapter
->interrupt_event
= eicr
;
2588 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_EVENT
;
2589 ixgbe_service_event_schedule(adapter
);
2597 ixgbe_check_fan_failure(adapter
, eicr
);
2599 if (napi_schedule_prep(&(q_vector
->napi
))) {
2600 adapter
->tx_ring
[0]->total_packets
= 0;
2601 adapter
->tx_ring
[0]->total_bytes
= 0;
2602 adapter
->rx_ring
[0]->total_packets
= 0;
2603 adapter
->rx_ring
[0]->total_bytes
= 0;
2604 /* would disable interrupts here but EIAM disabled it */
2605 __napi_schedule(&(q_vector
->napi
));
2609 * re-enable link(maybe) and non-queue interrupts, no flush.
2610 * ixgbe_poll will re-enable the queue interrupts
2613 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
2614 ixgbe_irq_enable(adapter
, false, false);
2619 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter
*adapter
)
2621 int i
, q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
2623 for (i
= 0; i
< q_vectors
; i
++) {
2624 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
2625 bitmap_zero(q_vector
->rxr_idx
, MAX_RX_QUEUES
);
2626 bitmap_zero(q_vector
->txr_idx
, MAX_TX_QUEUES
);
2627 q_vector
->rxr_count
= 0;
2628 q_vector
->txr_count
= 0;
2633 * ixgbe_request_irq - initialize interrupts
2634 * @adapter: board private structure
2636 * Attempts to configure interrupts using the best available
2637 * capabilities of the hardware and kernel.
2639 static int ixgbe_request_irq(struct ixgbe_adapter
*adapter
)
2641 struct net_device
*netdev
= adapter
->netdev
;
2644 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2645 err
= ixgbe_request_msix_irqs(adapter
);
2646 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
2647 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, 0,
2648 netdev
->name
, netdev
);
2650 err
= request_irq(adapter
->pdev
->irq
, ixgbe_intr
, IRQF_SHARED
,
2651 netdev
->name
, netdev
);
2655 e_err(probe
, "request_irq failed, Error %d\n", err
);
2660 static void ixgbe_free_irq(struct ixgbe_adapter
*adapter
)
2662 struct net_device
*netdev
= adapter
->netdev
;
2664 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2667 q_vectors
= adapter
->num_msix_vectors
;
2670 free_irq(adapter
->msix_entries
[i
].vector
, netdev
);
2673 for (; i
>= 0; i
--) {
2674 /* free only the irqs that were actually requested */
2675 if (!adapter
->q_vector
[i
]->rxr_count
&&
2676 !adapter
->q_vector
[i
]->txr_count
)
2679 free_irq(adapter
->msix_entries
[i
].vector
,
2680 adapter
->q_vector
[i
]);
2683 ixgbe_reset_q_vectors(adapter
);
2685 free_irq(adapter
->pdev
->irq
, netdev
);
2690 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2691 * @adapter: board private structure
2693 static inline void ixgbe_irq_disable(struct ixgbe_adapter
*adapter
)
2695 switch (adapter
->hw
.mac
.type
) {
2696 case ixgbe_mac_82598EB
:
2697 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, ~0);
2699 case ixgbe_mac_82599EB
:
2700 case ixgbe_mac_X540
:
2701 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC
, 0xFFFF0000);
2702 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(0), ~0);
2703 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EIMC_EX(1), ~0);
2704 if (adapter
->num_vfs
> 32)
2705 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_EITRSEL
, 0);
2710 IXGBE_WRITE_FLUSH(&adapter
->hw
);
2711 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
2713 for (i
= 0; i
< adapter
->num_msix_vectors
; i
++)
2714 synchronize_irq(adapter
->msix_entries
[i
].vector
);
2716 synchronize_irq(adapter
->pdev
->irq
);
2721 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2724 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter
*adapter
)
2726 struct ixgbe_hw
*hw
= &adapter
->hw
;
2728 IXGBE_WRITE_REG(hw
, IXGBE_EITR(0),
2729 EITR_INTS_PER_SEC_TO_REG(adapter
->rx_eitr_param
));
2731 ixgbe_set_ivar(adapter
, 0, 0, 0);
2732 ixgbe_set_ivar(adapter
, 1, 0, 0);
2734 map_vector_to_rxq(adapter
, 0, 0);
2735 map_vector_to_txq(adapter
, 0, 0);
2737 e_info(hw
, "Legacy interrupt IVAR setup done\n");
2741 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2742 * @adapter: board private structure
2743 * @ring: structure containing ring specific data
2745 * Configure the Tx descriptor ring after a reset.
2747 void ixgbe_configure_tx_ring(struct ixgbe_adapter
*adapter
,
2748 struct ixgbe_ring
*ring
)
2750 struct ixgbe_hw
*hw
= &adapter
->hw
;
2751 u64 tdba
= ring
->dma
;
2754 u8 reg_idx
= ring
->reg_idx
;
2756 /* disable queue to avoid issues while updating state */
2757 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2758 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
),
2759 txdctl
& ~IXGBE_TXDCTL_ENABLE
);
2760 IXGBE_WRITE_FLUSH(hw
);
2762 IXGBE_WRITE_REG(hw
, IXGBE_TDBAL(reg_idx
),
2763 (tdba
& DMA_BIT_MASK(32)));
2764 IXGBE_WRITE_REG(hw
, IXGBE_TDBAH(reg_idx
), (tdba
>> 32));
2765 IXGBE_WRITE_REG(hw
, IXGBE_TDLEN(reg_idx
),
2766 ring
->count
* sizeof(union ixgbe_adv_tx_desc
));
2767 IXGBE_WRITE_REG(hw
, IXGBE_TDH(reg_idx
), 0);
2768 IXGBE_WRITE_REG(hw
, IXGBE_TDT(reg_idx
), 0);
2769 ring
->tail
= hw
->hw_addr
+ IXGBE_TDT(reg_idx
);
2771 /* configure fetching thresholds */
2772 if (adapter
->rx_itr_setting
== 0) {
2773 /* cannot set wthresh when itr==0 */
2774 txdctl
&= ~0x007F0000;
2776 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2777 txdctl
|= (8 << 16);
2779 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
2780 /* PThresh workaround for Tx hang with DFP enabled. */
2784 /* reinitialize flowdirector state */
2785 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) &&
2786 adapter
->atr_sample_rate
) {
2787 ring
->atr_sample_rate
= adapter
->atr_sample_rate
;
2788 ring
->atr_count
= 0;
2789 set_bit(__IXGBE_TX_FDIR_INIT_DONE
, &ring
->state
);
2791 ring
->atr_sample_rate
= 0;
2794 clear_bit(__IXGBE_HANG_CHECK_ARMED
, &ring
->state
);
2797 txdctl
|= IXGBE_TXDCTL_ENABLE
;
2798 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), txdctl
);
2800 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2801 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
2802 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
2805 /* poll to verify queue is enabled */
2807 usleep_range(1000, 2000);
2808 txdctl
= IXGBE_READ_REG(hw
, IXGBE_TXDCTL(reg_idx
));
2809 } while (--wait_loop
&& !(txdctl
& IXGBE_TXDCTL_ENABLE
));
2811 e_err(drv
, "Could not enable Tx Queue %d\n", reg_idx
);
2814 static void ixgbe_setup_mtqc(struct ixgbe_adapter
*adapter
)
2816 struct ixgbe_hw
*hw
= &adapter
->hw
;
2819 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2821 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
2824 /* disable the arbiter while setting MTQC */
2825 rttdcs
= IXGBE_READ_REG(hw
, IXGBE_RTTDCS
);
2826 rttdcs
|= IXGBE_RTTDCS_ARBDIS
;
2827 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2829 /* set transmit pool layout */
2830 switch (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
2831 case (IXGBE_FLAG_SRIOV_ENABLED
):
2832 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
,
2833 (IXGBE_MTQC_VT_ENA
| IXGBE_MTQC_64VF
));
2837 reg
= IXGBE_MTQC_64Q_1PB
;
2839 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_4TC_4TQ
;
2841 reg
= IXGBE_MTQC_RT_ENA
| IXGBE_MTQC_8TC_8TQ
;
2843 IXGBE_WRITE_REG(hw
, IXGBE_MTQC
, reg
);
2845 /* Enable Security TX Buffer IFG for multiple pb */
2847 reg
= IXGBE_READ_REG(hw
, IXGBE_SECTXMINIFG
);
2848 reg
|= IXGBE_SECTX_DCB
;
2849 IXGBE_WRITE_REG(hw
, IXGBE_SECTXMINIFG
, reg
);
2854 /* re-enable the arbiter */
2855 rttdcs
&= ~IXGBE_RTTDCS_ARBDIS
;
2856 IXGBE_WRITE_REG(hw
, IXGBE_RTTDCS
, rttdcs
);
2860 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2861 * @adapter: board private structure
2863 * Configure the Tx unit of the MAC after a reset.
2865 static void ixgbe_configure_tx(struct ixgbe_adapter
*adapter
)
2867 struct ixgbe_hw
*hw
= &adapter
->hw
;
2871 ixgbe_setup_mtqc(adapter
);
2873 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
2874 /* DMATXCTL.EN must be before Tx queues are enabled */
2875 dmatxctl
= IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
);
2876 dmatxctl
|= IXGBE_DMATXCTL_TE
;
2877 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
, dmatxctl
);
2880 /* Setup the HW Tx Head and Tail descriptor pointers */
2881 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
2882 ixgbe_configure_tx_ring(adapter
, adapter
->tx_ring
[i
]);
2885 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2887 static void ixgbe_configure_srrctl(struct ixgbe_adapter
*adapter
,
2888 struct ixgbe_ring
*rx_ring
)
2891 u8 reg_idx
= rx_ring
->reg_idx
;
2893 switch (adapter
->hw
.mac
.type
) {
2894 case ixgbe_mac_82598EB
: {
2895 struct ixgbe_ring_feature
*feature
= adapter
->ring_feature
;
2896 const int mask
= feature
[RING_F_RSS
].mask
;
2897 reg_idx
= reg_idx
& mask
;
2900 case ixgbe_mac_82599EB
:
2901 case ixgbe_mac_X540
:
2906 srrctl
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
));
2908 srrctl
&= ~IXGBE_SRRCTL_BSIZEHDR_MASK
;
2909 srrctl
&= ~IXGBE_SRRCTL_BSIZEPKT_MASK
;
2910 if (adapter
->num_vfs
)
2911 srrctl
|= IXGBE_SRRCTL_DROP_EN
;
2913 srrctl
|= (IXGBE_RX_HDR_SIZE
<< IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT
) &
2914 IXGBE_SRRCTL_BSIZEHDR_MASK
;
2916 if (ring_is_ps_enabled(rx_ring
)) {
2917 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2918 srrctl
|= IXGBE_MAX_RXBUFFER
>> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2920 srrctl
|= (PAGE_SIZE
/ 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2922 srrctl
|= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS
;
2924 srrctl
|= ALIGN(rx_ring
->rx_buf_len
, 1024) >>
2925 IXGBE_SRRCTL_BSIZEPKT_SHIFT
;
2926 srrctl
|= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF
;
2929 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_SRRCTL(reg_idx
), srrctl
);
2932 static void ixgbe_setup_mrqc(struct ixgbe_adapter
*adapter
)
2934 struct ixgbe_hw
*hw
= &adapter
->hw
;
2935 static const u32 seed
[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2936 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2937 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2938 u32 mrqc
= 0, reta
= 0;
2941 u8 tcs
= netdev_get_num_tc(adapter
->netdev
);
2943 /* Fill out hash function seeds */
2944 for (i
= 0; i
< 10; i
++)
2945 IXGBE_WRITE_REG(hw
, IXGBE_RSSRK(i
), seed
[i
]);
2947 /* Fill out redirection table */
2948 for (i
= 0, j
= 0; i
< 128; i
++, j
++) {
2949 if (j
== adapter
->ring_feature
[RING_F_RSS
].indices
)
2951 /* reta = 4-byte sliding window of
2952 * 0x00..(indices-1)(indices-1)00..etc. */
2953 reta
= (reta
<< 8) | (j
* 0x11);
2955 IXGBE_WRITE_REG(hw
, IXGBE_RETA(i
>> 2), reta
);
2958 /* Disable indicating checksum in descriptor, enables RSS hash */
2959 rxcsum
= IXGBE_READ_REG(hw
, IXGBE_RXCSUM
);
2960 rxcsum
|= IXGBE_RXCSUM_PCSD
;
2961 IXGBE_WRITE_REG(hw
, IXGBE_RXCSUM
, rxcsum
);
2963 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
&&
2964 (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)) {
2965 mrqc
= IXGBE_MRQC_RSSEN
;
2967 int mask
= adapter
->flags
& (IXGBE_FLAG_RSS_ENABLED
2968 | IXGBE_FLAG_SRIOV_ENABLED
);
2971 case (IXGBE_FLAG_RSS_ENABLED
):
2973 mrqc
= IXGBE_MRQC_RSSEN
;
2975 mrqc
= IXGBE_MRQC_RTRSS4TCEN
;
2977 mrqc
= IXGBE_MRQC_RTRSS8TCEN
;
2979 case (IXGBE_FLAG_SRIOV_ENABLED
):
2980 mrqc
= IXGBE_MRQC_VMDQEN
;
2987 /* Perform hash on these packet types */
2988 mrqc
|= IXGBE_MRQC_RSS_FIELD_IPV4
2989 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2990 | IXGBE_MRQC_RSS_FIELD_IPV6
2991 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
;
2993 IXGBE_WRITE_REG(hw
, IXGBE_MRQC
, mrqc
);
2997 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2998 * @adapter: address of board private structure
2999 * @ring: structure containing ring specific data
3001 void ixgbe_clear_rscctl(struct ixgbe_adapter
*adapter
,
3002 struct ixgbe_ring
*ring
)
3004 struct ixgbe_hw
*hw
= &adapter
->hw
;
3006 u8 reg_idx
= ring
->reg_idx
;
3008 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
3009 rscctrl
&= ~IXGBE_RSCCTL_RSCEN
;
3010 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
3014 * ixgbe_configure_rscctl - enable RSC for the indicated ring
3015 * @adapter: address of board private structure
3016 * @index: index of ring to set
3018 void ixgbe_configure_rscctl(struct ixgbe_adapter
*adapter
,
3019 struct ixgbe_ring
*ring
)
3021 struct ixgbe_hw
*hw
= &adapter
->hw
;
3024 u8 reg_idx
= ring
->reg_idx
;
3026 if (!ring_is_rsc_enabled(ring
))
3029 rx_buf_len
= ring
->rx_buf_len
;
3030 rscctrl
= IXGBE_READ_REG(hw
, IXGBE_RSCCTL(reg_idx
));
3031 rscctrl
|= IXGBE_RSCCTL_RSCEN
;
3033 * we must limit the number of descriptors so that the
3034 * total size of max desc * buf_len is not greater
3037 if (ring_is_ps_enabled(ring
)) {
3038 #if (MAX_SKB_FRAGS > 16)
3039 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
3040 #elif (MAX_SKB_FRAGS > 8)
3041 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
3042 #elif (MAX_SKB_FRAGS > 4)
3043 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
3045 rscctrl
|= IXGBE_RSCCTL_MAXDESC_1
;
3048 if (rx_buf_len
< IXGBE_RXBUFFER_4096
)
3049 rscctrl
|= IXGBE_RSCCTL_MAXDESC_16
;
3050 else if (rx_buf_len
< IXGBE_RXBUFFER_8192
)
3051 rscctrl
|= IXGBE_RSCCTL_MAXDESC_8
;
3053 rscctrl
|= IXGBE_RSCCTL_MAXDESC_4
;
3055 IXGBE_WRITE_REG(hw
, IXGBE_RSCCTL(reg_idx
), rscctrl
);
3059 * ixgbe_set_uta - Set unicast filter table address
3060 * @adapter: board private structure
3062 * The unicast table address is a register array of 32-bit registers.
3063 * The table is meant to be used in a way similar to how the MTA is used
3064 * however due to certain limitations in the hardware it is necessary to
3065 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3066 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3068 static void ixgbe_set_uta(struct ixgbe_adapter
*adapter
)
3070 struct ixgbe_hw
*hw
= &adapter
->hw
;
3073 /* The UTA table only exists on 82599 hardware and newer */
3074 if (hw
->mac
.type
< ixgbe_mac_82599EB
)
3077 /* we only need to do this if VMDq is enabled */
3078 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3081 for (i
= 0; i
< 128; i
++)
3082 IXGBE_WRITE_REG(hw
, IXGBE_UTA(i
), ~0);
3085 #define IXGBE_MAX_RX_DESC_POLL 10
3086 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter
*adapter
,
3087 struct ixgbe_ring
*ring
)
3089 struct ixgbe_hw
*hw
= &adapter
->hw
;
3090 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3092 u8 reg_idx
= ring
->reg_idx
;
3094 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3095 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3096 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3100 usleep_range(1000, 2000);
3101 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3102 } while (--wait_loop
&& !(rxdctl
& IXGBE_RXDCTL_ENABLE
));
3105 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not set within "
3106 "the polling period\n", reg_idx
);
3110 void ixgbe_disable_rx_queue(struct ixgbe_adapter
*adapter
,
3111 struct ixgbe_ring
*ring
)
3113 struct ixgbe_hw
*hw
= &adapter
->hw
;
3114 int wait_loop
= IXGBE_MAX_RX_DESC_POLL
;
3116 u8 reg_idx
= ring
->reg_idx
;
3118 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3119 rxdctl
&= ~IXGBE_RXDCTL_ENABLE
;
3121 /* write value back with RXDCTL.ENABLE bit cleared */
3122 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3124 if (hw
->mac
.type
== ixgbe_mac_82598EB
&&
3125 !(IXGBE_READ_REG(hw
, IXGBE_LINKS
) & IXGBE_LINKS_UP
))
3128 /* the hardware may take up to 100us to really disable the rx queue */
3131 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3132 } while (--wait_loop
&& (rxdctl
& IXGBE_RXDCTL_ENABLE
));
3135 e_err(drv
, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3136 "the polling period\n", reg_idx
);
3140 void ixgbe_configure_rx_ring(struct ixgbe_adapter
*adapter
,
3141 struct ixgbe_ring
*ring
)
3143 struct ixgbe_hw
*hw
= &adapter
->hw
;
3144 u64 rdba
= ring
->dma
;
3146 u8 reg_idx
= ring
->reg_idx
;
3148 /* disable queue to avoid issues while updating state */
3149 rxdctl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(reg_idx
));
3150 ixgbe_disable_rx_queue(adapter
, ring
);
3152 IXGBE_WRITE_REG(hw
, IXGBE_RDBAL(reg_idx
), (rdba
& DMA_BIT_MASK(32)));
3153 IXGBE_WRITE_REG(hw
, IXGBE_RDBAH(reg_idx
), (rdba
>> 32));
3154 IXGBE_WRITE_REG(hw
, IXGBE_RDLEN(reg_idx
),
3155 ring
->count
* sizeof(union ixgbe_adv_rx_desc
));
3156 IXGBE_WRITE_REG(hw
, IXGBE_RDH(reg_idx
), 0);
3157 IXGBE_WRITE_REG(hw
, IXGBE_RDT(reg_idx
), 0);
3158 ring
->tail
= hw
->hw_addr
+ IXGBE_RDT(reg_idx
);
3160 ixgbe_configure_srrctl(adapter
, ring
);
3161 ixgbe_configure_rscctl(adapter
, ring
);
3163 /* If operating in IOV mode set RLPML for X540 */
3164 if ((adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) &&
3165 hw
->mac
.type
== ixgbe_mac_X540
) {
3166 rxdctl
&= ~IXGBE_RXDCTL_RLPMLMASK
;
3167 rxdctl
|= ((ring
->netdev
->mtu
+ ETH_HLEN
+
3168 ETH_FCS_LEN
+ VLAN_HLEN
) | IXGBE_RXDCTL_RLPML_EN
);
3171 if (hw
->mac
.type
== ixgbe_mac_82598EB
) {
3173 * enable cache line friendly hardware writes:
3174 * PTHRESH=32 descriptors (half the internal cache),
3175 * this also removes ugly rx_no_buffer_count increment
3176 * HTHRESH=4 descriptors (to minimize latency on fetch)
3177 * WTHRESH=8 burst writeback up to two cache lines
3179 rxdctl
&= ~0x3FFFFF;
3183 /* enable receive descriptor ring */
3184 rxdctl
|= IXGBE_RXDCTL_ENABLE
;
3185 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(reg_idx
), rxdctl
);
3187 ixgbe_rx_desc_queue_enable(adapter
, ring
);
3188 ixgbe_alloc_rx_buffers(ring
, IXGBE_DESC_UNUSED(ring
));
3191 static void ixgbe_setup_psrtype(struct ixgbe_adapter
*adapter
)
3193 struct ixgbe_hw
*hw
= &adapter
->hw
;
3196 /* PSRTYPE must be initialized in non 82598 adapters */
3197 u32 psrtype
= IXGBE_PSRTYPE_TCPHDR
|
3198 IXGBE_PSRTYPE_UDPHDR
|
3199 IXGBE_PSRTYPE_IPV4HDR
|
3200 IXGBE_PSRTYPE_L2HDR
|
3201 IXGBE_PSRTYPE_IPV6HDR
;
3203 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3206 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
)
3207 psrtype
|= (adapter
->num_rx_queues_per_pool
<< 29);
3209 for (p
= 0; p
< adapter
->num_rx_pools
; p
++)
3210 IXGBE_WRITE_REG(hw
, IXGBE_PSRTYPE(adapter
->num_vfs
+ p
),
3214 static void ixgbe_configure_virtualization(struct ixgbe_adapter
*adapter
)
3216 struct ixgbe_hw
*hw
= &adapter
->hw
;
3219 u32 reg_offset
, vf_shift
;
3222 if (!(adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
))
3225 vmdctl
= IXGBE_READ_REG(hw
, IXGBE_VT_CTL
);
3226 vt_reg_bits
= IXGBE_VMD_CTL_VMDQ_EN
| IXGBE_VT_CTL_REPLEN
;
3227 vt_reg_bits
|= (adapter
->num_vfs
<< IXGBE_VT_CTL_POOL_SHIFT
);
3228 IXGBE_WRITE_REG(hw
, IXGBE_VT_CTL
, vmdctl
| vt_reg_bits
);
3230 vf_shift
= adapter
->num_vfs
% 32;
3231 reg_offset
= (adapter
->num_vfs
> 32) ? 1 : 0;
3233 /* Enable only the PF's pool for Tx/Rx */
3234 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
), (1 << vf_shift
));
3235 IXGBE_WRITE_REG(hw
, IXGBE_VFRE(reg_offset
^ 1), 0);
3236 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
), (1 << vf_shift
));
3237 IXGBE_WRITE_REG(hw
, IXGBE_VFTE(reg_offset
^ 1), 0);
3238 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3240 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3241 hw
->mac
.ops
.set_vmdq(hw
, 0, adapter
->num_vfs
);
3244 * Set up VF register offsets for selected VT Mode,
3245 * i.e. 32 or 64 VFs for SR-IOV
3247 gcr_ext
= IXGBE_READ_REG(hw
, IXGBE_GCR_EXT
);
3248 gcr_ext
|= IXGBE_GCR_EXT_MSIX_EN
;
3249 gcr_ext
|= IXGBE_GCR_EXT_VT_MODE_64
;
3250 IXGBE_WRITE_REG(hw
, IXGBE_GCR_EXT
, gcr_ext
);
3252 /* enable Tx loopback for VF/PF communication */
3253 IXGBE_WRITE_REG(hw
, IXGBE_PFDTXGSWC
, IXGBE_PFDTXGSWC_VT_LBEN
);
3254 /* Enable MAC Anti-Spoofing */
3255 hw
->mac
.ops
.set_mac_anti_spoofing(hw
,
3256 (adapter
->antispoofing_enabled
=
3257 (adapter
->num_vfs
!= 0)),
3261 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter
*adapter
)
3263 struct ixgbe_hw
*hw
= &adapter
->hw
;
3264 struct net_device
*netdev
= adapter
->netdev
;
3265 int max_frame
= netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3267 struct ixgbe_ring
*rx_ring
;
3271 /* Decide whether to use packet split mode or not */
3273 adapter
->flags
|= IXGBE_FLAG_RX_PS_ENABLED
;
3275 /* Do not use packet split if we're in SR-IOV Mode */
3276 if (adapter
->num_vfs
)
3277 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3279 /* Disable packet split due to 82599 erratum #45 */
3280 if (hw
->mac
.type
== ixgbe_mac_82599EB
)
3281 adapter
->flags
&= ~IXGBE_FLAG_RX_PS_ENABLED
;
3283 /* Set the RX buffer length according to the mode */
3284 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
) {
3285 rx_buf_len
= IXGBE_RX_HDR_SIZE
;
3287 if (!(adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) &&
3288 (netdev
->mtu
<= ETH_DATA_LEN
))
3289 rx_buf_len
= MAXIMUM_ETHERNET_VLAN_SIZE
;
3291 rx_buf_len
= ALIGN(max_frame
+ VLAN_HLEN
, 1024);
3295 /* adjust max frame to be able to do baby jumbo for FCoE */
3296 if ((adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) &&
3297 (max_frame
< IXGBE_FCOE_JUMBO_FRAME_SIZE
))
3298 max_frame
= IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3300 #endif /* IXGBE_FCOE */
3301 mhadd
= IXGBE_READ_REG(hw
, IXGBE_MHADD
);
3302 if (max_frame
!= (mhadd
>> IXGBE_MHADD_MFS_SHIFT
)) {
3303 mhadd
&= ~IXGBE_MHADD_MFS_MASK
;
3304 mhadd
|= max_frame
<< IXGBE_MHADD_MFS_SHIFT
;
3306 IXGBE_WRITE_REG(hw
, IXGBE_MHADD
, mhadd
);
3309 hlreg0
= IXGBE_READ_REG(hw
, IXGBE_HLREG0
);
3310 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3311 hlreg0
|= IXGBE_HLREG0_JUMBOEN
;
3312 IXGBE_WRITE_REG(hw
, IXGBE_HLREG0
, hlreg0
);
3315 * Setup the HW Rx Head and Tail Descriptor Pointers and
3316 * the Base and Length of the Rx Descriptor Ring
3318 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3319 rx_ring
= adapter
->rx_ring
[i
];
3320 rx_ring
->rx_buf_len
= rx_buf_len
;
3322 if (adapter
->flags
& IXGBE_FLAG_RX_PS_ENABLED
)
3323 set_ring_ps_enabled(rx_ring
);
3325 clear_ring_ps_enabled(rx_ring
);
3327 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
3328 set_ring_rsc_enabled(rx_ring
);
3330 clear_ring_rsc_enabled(rx_ring
);
3333 if (netdev
->features
& NETIF_F_FCOE_MTU
) {
3334 struct ixgbe_ring_feature
*f
;
3335 f
= &adapter
->ring_feature
[RING_F_FCOE
];
3336 if ((i
>= f
->mask
) && (i
< f
->mask
+ f
->indices
)) {
3337 clear_ring_ps_enabled(rx_ring
);
3338 if (rx_buf_len
< IXGBE_FCOE_JUMBO_FRAME_SIZE
)
3339 rx_ring
->rx_buf_len
=
3340 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3341 } else if (!ring_is_rsc_enabled(rx_ring
) &&
3342 !ring_is_ps_enabled(rx_ring
)) {
3343 rx_ring
->rx_buf_len
=
3344 IXGBE_FCOE_JUMBO_FRAME_SIZE
;
3347 #endif /* IXGBE_FCOE */
3351 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter
*adapter
)
3353 struct ixgbe_hw
*hw
= &adapter
->hw
;
3354 u32 rdrxctl
= IXGBE_READ_REG(hw
, IXGBE_RDRXCTL
);
3356 switch (hw
->mac
.type
) {
3357 case ixgbe_mac_82598EB
:
3359 * For VMDq support of different descriptor types or
3360 * buffer sizes through the use of multiple SRRCTL
3361 * registers, RDRXCTL.MVMEN must be set to 1
3363 * also, the manual doesn't mention it clearly but DCA hints
3364 * will only use queue 0's tags unless this bit is set. Side
3365 * effects of setting this bit are only that SRRCTL must be
3366 * fully programmed [0..15]
3368 rdrxctl
|= IXGBE_RDRXCTL_MVMEN
;
3370 case ixgbe_mac_82599EB
:
3371 case ixgbe_mac_X540
:
3372 /* Disable RSC for ACK packets */
3373 IXGBE_WRITE_REG(hw
, IXGBE_RSCDBU
,
3374 (IXGBE_RSCDBU_RSCACKDIS
| IXGBE_READ_REG(hw
, IXGBE_RSCDBU
)));
3375 rdrxctl
&= ~IXGBE_RDRXCTL_RSCFRSTSIZE
;
3376 /* hardware requires some bits to be set by default */
3377 rdrxctl
|= (IXGBE_RDRXCTL_RSCACKC
| IXGBE_RDRXCTL_FCOE_WRFIX
);
3378 rdrxctl
|= IXGBE_RDRXCTL_CRCSTRIP
;
3381 /* We should do nothing since we don't know this hardware */
3385 IXGBE_WRITE_REG(hw
, IXGBE_RDRXCTL
, rdrxctl
);
3389 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3390 * @adapter: board private structure
3392 * Configure the Rx unit of the MAC after a reset.
3394 static void ixgbe_configure_rx(struct ixgbe_adapter
*adapter
)
3396 struct ixgbe_hw
*hw
= &adapter
->hw
;
3400 /* disable receives while setting up the descriptors */
3401 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
3402 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
3404 ixgbe_setup_psrtype(adapter
);
3405 ixgbe_setup_rdrxctl(adapter
);
3407 /* Program registers for the distribution of queues */
3408 ixgbe_setup_mrqc(adapter
);
3410 ixgbe_set_uta(adapter
);
3412 /* set_rx_buffer_len must be called before ring initialization */
3413 ixgbe_set_rx_buffer_len(adapter
);
3416 * Setup the HW Rx Head and Tail Descriptor Pointers and
3417 * the Base and Length of the Rx Descriptor Ring
3419 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
3420 ixgbe_configure_rx_ring(adapter
, adapter
->rx_ring
[i
]);
3422 /* disable drop enable for 82598 parts */
3423 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3424 rxctrl
|= IXGBE_RXCTRL_DMBYPS
;
3426 /* enable all receives */
3427 rxctrl
|= IXGBE_RXCTRL_RXEN
;
3428 hw
->mac
.ops
.enable_rx_dma(hw
, rxctrl
);
3431 static void ixgbe_vlan_rx_add_vid(struct net_device
*netdev
, u16 vid
)
3433 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3434 struct ixgbe_hw
*hw
= &adapter
->hw
;
3435 int pool_ndx
= adapter
->num_vfs
;
3437 /* add VID to filter table */
3438 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, true);
3439 set_bit(vid
, adapter
->active_vlans
);
3442 static void ixgbe_vlan_rx_kill_vid(struct net_device
*netdev
, u16 vid
)
3444 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3445 struct ixgbe_hw
*hw
= &adapter
->hw
;
3446 int pool_ndx
= adapter
->num_vfs
;
3448 /* remove VID from filter table */
3449 hw
->mac
.ops
.set_vfta(&adapter
->hw
, vid
, pool_ndx
, false);
3450 clear_bit(vid
, adapter
->active_vlans
);
3454 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3455 * @adapter: driver data
3457 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter
*adapter
)
3459 struct ixgbe_hw
*hw
= &adapter
->hw
;
3462 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3463 vlnctrl
&= ~(IXGBE_VLNCTRL_VFE
| IXGBE_VLNCTRL_CFIEN
);
3464 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3468 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3469 * @adapter: driver data
3471 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter
*adapter
)
3473 struct ixgbe_hw
*hw
= &adapter
->hw
;
3476 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3477 vlnctrl
|= IXGBE_VLNCTRL_VFE
;
3478 vlnctrl
&= ~IXGBE_VLNCTRL_CFIEN
;
3479 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3483 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3484 * @adapter: driver data
3486 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter
*adapter
)
3488 struct ixgbe_hw
*hw
= &adapter
->hw
;
3492 switch (hw
->mac
.type
) {
3493 case ixgbe_mac_82598EB
:
3494 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3495 vlnctrl
&= ~IXGBE_VLNCTRL_VME
;
3496 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3498 case ixgbe_mac_82599EB
:
3499 case ixgbe_mac_X540
:
3500 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3501 j
= adapter
->rx_ring
[i
]->reg_idx
;
3502 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3503 vlnctrl
&= ~IXGBE_RXDCTL_VME
;
3504 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3513 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3514 * @adapter: driver data
3516 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter
*adapter
)
3518 struct ixgbe_hw
*hw
= &adapter
->hw
;
3522 switch (hw
->mac
.type
) {
3523 case ixgbe_mac_82598EB
:
3524 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_VLNCTRL
);
3525 vlnctrl
|= IXGBE_VLNCTRL_VME
;
3526 IXGBE_WRITE_REG(hw
, IXGBE_VLNCTRL
, vlnctrl
);
3528 case ixgbe_mac_82599EB
:
3529 case ixgbe_mac_X540
:
3530 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
3531 j
= adapter
->rx_ring
[i
]->reg_idx
;
3532 vlnctrl
= IXGBE_READ_REG(hw
, IXGBE_RXDCTL(j
));
3533 vlnctrl
|= IXGBE_RXDCTL_VME
;
3534 IXGBE_WRITE_REG(hw
, IXGBE_RXDCTL(j
), vlnctrl
);
3542 static void ixgbe_restore_vlan(struct ixgbe_adapter
*adapter
)
3546 ixgbe_vlan_rx_add_vid(adapter
->netdev
, 0);
3548 for_each_set_bit(vid
, adapter
->active_vlans
, VLAN_N_VID
)
3549 ixgbe_vlan_rx_add_vid(adapter
->netdev
, vid
);
3553 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3554 * @netdev: network interface device structure
3556 * Writes unicast address list to the RAR table.
3557 * Returns: -ENOMEM on failure/insufficient address space
3558 * 0 on no addresses written
3559 * X on writing X addresses to the RAR table
3561 static int ixgbe_write_uc_addr_list(struct net_device
*netdev
)
3563 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3564 struct ixgbe_hw
*hw
= &adapter
->hw
;
3565 unsigned int vfn
= adapter
->num_vfs
;
3566 unsigned int rar_entries
= IXGBE_MAX_PF_MACVLANS
;
3569 /* return ENOMEM indicating insufficient memory for addresses */
3570 if (netdev_uc_count(netdev
) > rar_entries
)
3573 if (!netdev_uc_empty(netdev
) && rar_entries
) {
3574 struct netdev_hw_addr
*ha
;
3575 /* return error if we do not support writing to RAR table */
3576 if (!hw
->mac
.ops
.set_rar
)
3579 netdev_for_each_uc_addr(ha
, netdev
) {
3582 hw
->mac
.ops
.set_rar(hw
, rar_entries
--, ha
->addr
,
3587 /* write the addresses in reverse order to avoid write combining */
3588 for (; rar_entries
> 0 ; rar_entries
--)
3589 hw
->mac
.ops
.clear_rar(hw
, rar_entries
);
3595 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3596 * @netdev: network interface device structure
3598 * The set_rx_method entry point is called whenever the unicast/multicast
3599 * address list or the network interface flags are updated. This routine is
3600 * responsible for configuring the hardware for proper unicast, multicast and
3603 void ixgbe_set_rx_mode(struct net_device
*netdev
)
3605 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
3606 struct ixgbe_hw
*hw
= &adapter
->hw
;
3607 u32 fctrl
, vmolr
= IXGBE_VMOLR_BAM
| IXGBE_VMOLR_AUPE
;
3610 /* Check for Promiscuous and All Multicast modes */
3612 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
3614 /* set all bits that we expect to always be set */
3615 fctrl
|= IXGBE_FCTRL_BAM
;
3616 fctrl
|= IXGBE_FCTRL_DPF
; /* discard pause frames when FC enabled */
3617 fctrl
|= IXGBE_FCTRL_PMCF
;
3619 /* clear the bits we are changing the status of */
3620 fctrl
&= ~(IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3622 if (netdev
->flags
& IFF_PROMISC
) {
3623 hw
->addr_ctrl
.user_set_promisc
= true;
3624 fctrl
|= (IXGBE_FCTRL_UPE
| IXGBE_FCTRL_MPE
);
3625 vmolr
|= (IXGBE_VMOLR_ROPE
| IXGBE_VMOLR_MPE
);
3626 /* don't hardware filter vlans in promisc mode */
3627 ixgbe_vlan_filter_disable(adapter
);
3629 if (netdev
->flags
& IFF_ALLMULTI
) {
3630 fctrl
|= IXGBE_FCTRL_MPE
;
3631 vmolr
|= IXGBE_VMOLR_MPE
;
3634 * Write addresses to the MTA, if the attempt fails
3635 * then we should just turn on promiscuous mode so
3636 * that we can at least receive multicast traffic
3638 hw
->mac
.ops
.update_mc_addr_list(hw
, netdev
);
3639 vmolr
|= IXGBE_VMOLR_ROMPE
;
3641 ixgbe_vlan_filter_enable(adapter
);
3642 hw
->addr_ctrl
.user_set_promisc
= false;
3644 * Write addresses to available RAR registers, if there is not
3645 * sufficient space to store all the addresses then enable
3646 * unicast promiscuous mode
3648 count
= ixgbe_write_uc_addr_list(netdev
);
3650 fctrl
|= IXGBE_FCTRL_UPE
;
3651 vmolr
|= IXGBE_VMOLR_ROPE
;
3655 if (adapter
->num_vfs
) {
3656 ixgbe_restore_vf_multicasts(adapter
);
3657 vmolr
|= IXGBE_READ_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
)) &
3658 ~(IXGBE_VMOLR_MPE
| IXGBE_VMOLR_ROMPE
|
3660 IXGBE_WRITE_REG(hw
, IXGBE_VMOLR(adapter
->num_vfs
), vmolr
);
3663 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
3665 if (netdev
->features
& NETIF_F_HW_VLAN_RX
)
3666 ixgbe_vlan_strip_enable(adapter
);
3668 ixgbe_vlan_strip_disable(adapter
);
3671 static void ixgbe_napi_enable_all(struct ixgbe_adapter
*adapter
)
3674 struct ixgbe_q_vector
*q_vector
;
3675 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3677 /* legacy and MSI only use one vector */
3678 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3681 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3682 struct napi_struct
*napi
;
3683 q_vector
= adapter
->q_vector
[q_idx
];
3684 napi
= &q_vector
->napi
;
3685 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3686 if (!q_vector
->rxr_count
|| !q_vector
->txr_count
) {
3687 if (q_vector
->txr_count
== 1)
3688 napi
->poll
= &ixgbe_clean_txonly
;
3689 else if (q_vector
->rxr_count
== 1)
3690 napi
->poll
= &ixgbe_clean_rxonly
;
3698 static void ixgbe_napi_disable_all(struct ixgbe_adapter
*adapter
)
3701 struct ixgbe_q_vector
*q_vector
;
3702 int q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
3704 /* legacy and MSI only use one vector */
3705 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
))
3708 for (q_idx
= 0; q_idx
< q_vectors
; q_idx
++) {
3709 q_vector
= adapter
->q_vector
[q_idx
];
3710 napi_disable(&q_vector
->napi
);
3714 #ifdef CONFIG_IXGBE_DCB
3716 * ixgbe_configure_dcb - Configure DCB hardware
3717 * @adapter: ixgbe adapter struct
3719 * This is called by the driver on open to configure the DCB hardware.
3720 * This is also called by the gennetlink interface when reconfiguring
3723 static void ixgbe_configure_dcb(struct ixgbe_adapter
*adapter
)
3725 struct ixgbe_hw
*hw
= &adapter
->hw
;
3726 int max_frame
= adapter
->netdev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
3728 if (!(adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
)) {
3729 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3730 netif_set_gso_max_size(adapter
->netdev
, 65536);
3734 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
3735 netif_set_gso_max_size(adapter
->netdev
, 32768);
3738 /* Enable VLAN tag insert/strip */
3739 adapter
->netdev
->features
|= NETIF_F_HW_VLAN_RX
;
3741 hw
->mac
.ops
.set_vfta(&adapter
->hw
, 0, 0, true);
3743 /* reconfigure the hardware */
3744 if (adapter
->dcbx_cap
& (DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
)) {
3746 if (adapter
->netdev
->features
& NETIF_F_FCOE_MTU
)
3747 max_frame
= max(max_frame
, IXGBE_FCOE_JUMBO_FRAME_SIZE
);
3749 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3751 ixgbe_dcb_calculate_tc_credits(hw
, &adapter
->dcb_cfg
, max_frame
,
3753 ixgbe_dcb_hw_config(hw
, &adapter
->dcb_cfg
);
3755 struct net_device
*dev
= adapter
->netdev
;
3757 if (adapter
->ixgbe_ieee_ets
)
3758 dev
->dcbnl_ops
->ieee_setets(dev
,
3759 adapter
->ixgbe_ieee_ets
);
3760 if (adapter
->ixgbe_ieee_pfc
)
3761 dev
->dcbnl_ops
->ieee_setpfc(dev
,
3762 adapter
->ixgbe_ieee_pfc
);
3765 /* Enable RSS Hash per TC */
3766 if (hw
->mac
.type
!= ixgbe_mac_82598EB
) {
3770 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
3772 u8 cnt
= adapter
->netdev
->tc_to_txq
[i
].count
;
3777 reg
|= msb
<< IXGBE_RQTC_SHIFT_TC(i
);
3779 IXGBE_WRITE_REG(hw
, IXGBE_RQTC
, reg
);
3785 static void ixgbe_configure_pb(struct ixgbe_adapter
*adapter
)
3788 int num_tc
= netdev_get_num_tc(adapter
->netdev
);
3789 struct ixgbe_hw
*hw
= &adapter
->hw
;
3791 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
3792 adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)
3793 hdrm
= 64 << adapter
->fdir_pballoc
;
3795 hw
->mac
.ops
.set_rxpba(&adapter
->hw
, num_tc
, hdrm
, PBA_STRATEGY_EQUAL
);
3798 static void ixgbe_configure(struct ixgbe_adapter
*adapter
)
3800 struct net_device
*netdev
= adapter
->netdev
;
3801 struct ixgbe_hw
*hw
= &adapter
->hw
;
3804 ixgbe_configure_pb(adapter
);
3805 #ifdef CONFIG_IXGBE_DCB
3806 ixgbe_configure_dcb(adapter
);
3809 ixgbe_set_rx_mode(netdev
);
3810 ixgbe_restore_vlan(adapter
);
3813 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
3814 ixgbe_configure_fcoe(adapter
);
3816 #endif /* IXGBE_FCOE */
3817 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
3818 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
3819 adapter
->tx_ring
[i
]->atr_sample_rate
=
3820 adapter
->atr_sample_rate
;
3821 ixgbe_init_fdir_signature_82599(hw
, adapter
->fdir_pballoc
);
3822 } else if (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
) {
3823 ixgbe_init_fdir_perfect_82599(hw
, adapter
->fdir_pballoc
);
3825 ixgbe_configure_virtualization(adapter
);
3827 ixgbe_configure_tx(adapter
);
3828 ixgbe_configure_rx(adapter
);
3831 static inline bool ixgbe_is_sfp(struct ixgbe_hw
*hw
)
3833 switch (hw
->phy
.type
) {
3834 case ixgbe_phy_sfp_avago
:
3835 case ixgbe_phy_sfp_ftl
:
3836 case ixgbe_phy_sfp_intel
:
3837 case ixgbe_phy_sfp_unknown
:
3838 case ixgbe_phy_sfp_passive_tyco
:
3839 case ixgbe_phy_sfp_passive_unknown
:
3840 case ixgbe_phy_sfp_active_unknown
:
3841 case ixgbe_phy_sfp_ftl_active
:
3849 * ixgbe_sfp_link_config - set up SFP+ link
3850 * @adapter: pointer to private adapter struct
3852 static void ixgbe_sfp_link_config(struct ixgbe_adapter
*adapter
)
3855 * We are assuming the worst case scenerio here, and that
3856 * is that an SFP was inserted/removed after the reset
3857 * but before SFP detection was enabled. As such the best
3858 * solution is to just start searching as soon as we start
3860 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
3861 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
3863 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
3867 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3868 * @hw: pointer to private hardware struct
3870 * Returns 0 on success, negative on failure
3872 static int ixgbe_non_sfp_link_config(struct ixgbe_hw
*hw
)
3875 bool negotiation
, link_up
= false;
3876 u32 ret
= IXGBE_ERR_LINK_SETUP
;
3878 if (hw
->mac
.ops
.check_link
)
3879 ret
= hw
->mac
.ops
.check_link(hw
, &autoneg
, &link_up
, false);
3884 autoneg
= hw
->phy
.autoneg_advertised
;
3885 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
3886 ret
= hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
,
3891 if (hw
->mac
.ops
.setup_link
)
3892 ret
= hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, link_up
);
3897 static void ixgbe_setup_gpie(struct ixgbe_adapter
*adapter
)
3899 struct ixgbe_hw
*hw
= &adapter
->hw
;
3902 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
3903 gpie
= IXGBE_GPIE_MSIX_MODE
| IXGBE_GPIE_PBA_SUPPORT
|
3905 gpie
|= IXGBE_GPIE_EIAME
;
3907 * use EIAM to auto-mask when MSI-X interrupt is asserted
3908 * this saves a register write for every interrupt
3910 switch (hw
->mac
.type
) {
3911 case ixgbe_mac_82598EB
:
3912 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3914 case ixgbe_mac_82599EB
:
3915 case ixgbe_mac_X540
:
3917 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3918 IXGBE_WRITE_REG(hw
, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3922 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3923 * specifically only auto mask tx and rx interrupts */
3924 IXGBE_WRITE_REG(hw
, IXGBE_EIAM
, IXGBE_EICS_RTX_QUEUE
);
3927 /* XXX: to interrupt immediately for EICS writes, enable this */
3928 /* gpie |= IXGBE_GPIE_EIMEN; */
3930 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
3931 gpie
&= ~IXGBE_GPIE_VTMODE_MASK
;
3932 gpie
|= IXGBE_GPIE_VTMODE_64
;
3935 /* Enable fan failure interrupt */
3936 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
)
3937 gpie
|= IXGBE_SDP1_GPIEN
;
3939 if (hw
->mac
.type
== ixgbe_mac_82599EB
) {
3940 gpie
|= IXGBE_SDP1_GPIEN
;
3941 gpie
|= IXGBE_SDP2_GPIEN
;
3944 IXGBE_WRITE_REG(hw
, IXGBE_GPIE
, gpie
);
3947 static int ixgbe_up_complete(struct ixgbe_adapter
*adapter
)
3949 struct ixgbe_hw
*hw
= &adapter
->hw
;
3953 ixgbe_get_hw_control(adapter
);
3954 ixgbe_setup_gpie(adapter
);
3956 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
3957 ixgbe_configure_msix(adapter
);
3959 ixgbe_configure_msi_and_legacy(adapter
);
3961 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3962 if (hw
->mac
.ops
.enable_tx_laser
&&
3963 ((hw
->phy
.multispeed_fiber
) ||
3964 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
3965 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
3966 hw
->mac
.ops
.enable_tx_laser(hw
);
3968 clear_bit(__IXGBE_DOWN
, &adapter
->state
);
3969 ixgbe_napi_enable_all(adapter
);
3971 if (ixgbe_is_sfp(hw
)) {
3972 ixgbe_sfp_link_config(adapter
);
3974 err
= ixgbe_non_sfp_link_config(hw
);
3976 e_err(probe
, "link_config FAILED %d\n", err
);
3979 /* clear any pending interrupts, may auto mask */
3980 IXGBE_READ_REG(hw
, IXGBE_EICR
);
3981 ixgbe_irq_enable(adapter
, true, true);
3984 * If this adapter has a fan, check to see if we had a failure
3985 * before we enabled the interrupt.
3987 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
3988 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
3989 if (esdp
& IXGBE_ESDP_SDP1
)
3990 e_crit(drv
, "Fan has stopped, replace the adapter\n");
3993 /* enable transmits */
3994 netif_tx_start_all_queues(adapter
->netdev
);
3996 /* bring the link up in the watchdog, this could race with our first
3997 * link up interrupt but shouldn't be a problem */
3998 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
3999 adapter
->link_check_timeout
= jiffies
;
4000 mod_timer(&adapter
->service_timer
, jiffies
);
4002 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
4003 ctrl_ext
= IXGBE_READ_REG(hw
, IXGBE_CTRL_EXT
);
4004 ctrl_ext
|= IXGBE_CTRL_EXT_PFRSTD
;
4005 IXGBE_WRITE_REG(hw
, IXGBE_CTRL_EXT
, ctrl_ext
);
4010 void ixgbe_reinit_locked(struct ixgbe_adapter
*adapter
)
4012 WARN_ON(in_interrupt());
4013 /* put off any impending NetWatchDogTimeout */
4014 adapter
->netdev
->trans_start
= jiffies
;
4016 while (test_and_set_bit(__IXGBE_RESETTING
, &adapter
->state
))
4017 usleep_range(1000, 2000);
4018 ixgbe_down(adapter
);
4020 * If SR-IOV enabled then wait a bit before bringing the adapter
4021 * back up to give the VFs time to respond to the reset. The
4022 * two second wait is based upon the watchdog timer cycle in
4025 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4028 clear_bit(__IXGBE_RESETTING
, &adapter
->state
);
4031 int ixgbe_up(struct ixgbe_adapter
*adapter
)
4033 /* hardware has been reset, we need to reload some things */
4034 ixgbe_configure(adapter
);
4036 return ixgbe_up_complete(adapter
);
4039 void ixgbe_reset(struct ixgbe_adapter
*adapter
)
4041 struct ixgbe_hw
*hw
= &adapter
->hw
;
4044 /* lock SFP init bit to prevent race conditions with the watchdog */
4045 while (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
4046 usleep_range(1000, 2000);
4048 /* clear all SFP and link config related flags while holding SFP_INIT */
4049 adapter
->flags2
&= ~(IXGBE_FLAG2_SEARCH_FOR_SFP
|
4050 IXGBE_FLAG2_SFP_NEEDS_RESET
);
4051 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
4053 err
= hw
->mac
.ops
.init_hw(hw
);
4056 case IXGBE_ERR_SFP_NOT_PRESENT
:
4057 case IXGBE_ERR_SFP_NOT_SUPPORTED
:
4059 case IXGBE_ERR_MASTER_REQUESTS_PENDING
:
4060 e_dev_err("master disable timed out\n");
4062 case IXGBE_ERR_EEPROM_VERSION
:
4063 /* We are running on a pre-production device, log a warning */
4064 e_dev_warn("This device is a pre-production adapter/LOM. "
4065 "Please be aware there may be issuesassociated with "
4066 "your hardware. If you are experiencing problems "
4067 "please contact your Intel or hardware "
4068 "representative who provided you with this "
4072 e_dev_err("Hardware Error: %d\n", err
);
4075 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
4077 /* reprogram the RAR[0] in case user changed it. */
4078 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
4083 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4084 * @rx_ring: ring to free buffers from
4086 static void ixgbe_clean_rx_ring(struct ixgbe_ring
*rx_ring
)
4088 struct device
*dev
= rx_ring
->dev
;
4092 /* ring already cleared, nothing to do */
4093 if (!rx_ring
->rx_buffer_info
)
4096 /* Free all the Rx ring sk_buffs */
4097 for (i
= 0; i
< rx_ring
->count
; i
++) {
4098 struct ixgbe_rx_buffer
*rx_buffer_info
;
4100 rx_buffer_info
= &rx_ring
->rx_buffer_info
[i
];
4101 if (rx_buffer_info
->dma
) {
4102 dma_unmap_single(rx_ring
->dev
, rx_buffer_info
->dma
,
4103 rx_ring
->rx_buf_len
,
4105 rx_buffer_info
->dma
= 0;
4107 if (rx_buffer_info
->skb
) {
4108 struct sk_buff
*skb
= rx_buffer_info
->skb
;
4109 rx_buffer_info
->skb
= NULL
;
4111 struct sk_buff
*this = skb
;
4112 if (IXGBE_RSC_CB(this)->delay_unmap
) {
4113 dma_unmap_single(dev
,
4114 IXGBE_RSC_CB(this)->dma
,
4115 rx_ring
->rx_buf_len
,
4117 IXGBE_RSC_CB(this)->dma
= 0;
4118 IXGBE_RSC_CB(skb
)->delay_unmap
= false;
4121 dev_kfree_skb(this);
4124 if (!rx_buffer_info
->page
)
4126 if (rx_buffer_info
->page_dma
) {
4127 dma_unmap_page(dev
, rx_buffer_info
->page_dma
,
4128 PAGE_SIZE
/ 2, DMA_FROM_DEVICE
);
4129 rx_buffer_info
->page_dma
= 0;
4131 put_page(rx_buffer_info
->page
);
4132 rx_buffer_info
->page
= NULL
;
4133 rx_buffer_info
->page_offset
= 0;
4136 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
4137 memset(rx_ring
->rx_buffer_info
, 0, size
);
4139 /* Zero out the descriptor ring */
4140 memset(rx_ring
->desc
, 0, rx_ring
->size
);
4142 rx_ring
->next_to_clean
= 0;
4143 rx_ring
->next_to_use
= 0;
4147 * ixgbe_clean_tx_ring - Free Tx Buffers
4148 * @tx_ring: ring to be cleaned
4150 static void ixgbe_clean_tx_ring(struct ixgbe_ring
*tx_ring
)
4152 struct ixgbe_tx_buffer
*tx_buffer_info
;
4156 /* ring already cleared, nothing to do */
4157 if (!tx_ring
->tx_buffer_info
)
4160 /* Free all the Tx ring sk_buffs */
4161 for (i
= 0; i
< tx_ring
->count
; i
++) {
4162 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
4163 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
4166 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
4167 memset(tx_ring
->tx_buffer_info
, 0, size
);
4169 /* Zero out the descriptor ring */
4170 memset(tx_ring
->desc
, 0, tx_ring
->size
);
4172 tx_ring
->next_to_use
= 0;
4173 tx_ring
->next_to_clean
= 0;
4177 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4178 * @adapter: board private structure
4180 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter
*adapter
)
4184 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4185 ixgbe_clean_rx_ring(adapter
->rx_ring
[i
]);
4189 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4190 * @adapter: board private structure
4192 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter
*adapter
)
4196 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4197 ixgbe_clean_tx_ring(adapter
->tx_ring
[i
]);
4200 void ixgbe_down(struct ixgbe_adapter
*adapter
)
4202 struct net_device
*netdev
= adapter
->netdev
;
4203 struct ixgbe_hw
*hw
= &adapter
->hw
;
4206 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4208 /* signal that we are down to the interrupt handler */
4209 set_bit(__IXGBE_DOWN
, &adapter
->state
);
4211 /* disable receives */
4212 rxctrl
= IXGBE_READ_REG(hw
, IXGBE_RXCTRL
);
4213 IXGBE_WRITE_REG(hw
, IXGBE_RXCTRL
, rxctrl
& ~IXGBE_RXCTRL_RXEN
);
4215 /* disable all enabled rx queues */
4216 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4217 /* this call also flushes the previous write */
4218 ixgbe_disable_rx_queue(adapter
, adapter
->rx_ring
[i
]);
4220 usleep_range(10000, 20000);
4222 netif_tx_stop_all_queues(netdev
);
4224 /* call carrier off first to avoid false dev_watchdog timeouts */
4225 netif_carrier_off(netdev
);
4226 netif_tx_disable(netdev
);
4228 ixgbe_irq_disable(adapter
);
4230 ixgbe_napi_disable_all(adapter
);
4232 adapter
->flags2
&= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT
|
4233 IXGBE_FLAG2_RESET_REQUESTED
);
4234 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
4236 del_timer_sync(&adapter
->service_timer
);
4238 /* disable receive for all VFs and wait one second */
4239 if (adapter
->num_vfs
) {
4240 /* ping all the active vfs to let them know we are going down */
4241 ixgbe_ping_all_vfs(adapter
);
4243 /* Disable all VFTE/VFRE TX/RX */
4244 ixgbe_disable_tx_rx(adapter
);
4246 /* Mark all the VFs as inactive */
4247 for (i
= 0 ; i
< adapter
->num_vfs
; i
++)
4248 adapter
->vfinfo
[i
].clear_to_send
= 0;
4251 /* Cleanup the affinity_hint CPU mask memory and callback */
4252 for (i
= 0; i
< num_q_vectors
; i
++) {
4253 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
4254 /* clear the affinity_mask in the IRQ descriptor */
4255 irq_set_affinity_hint(adapter
->msix_entries
[i
]. vector
, NULL
);
4256 /* release the CPU mask memory */
4257 free_cpumask_var(q_vector
->affinity_mask
);
4260 /* disable transmits in the hardware now that interrupts are off */
4261 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
4262 u8 reg_idx
= adapter
->tx_ring
[i
]->reg_idx
;
4263 IXGBE_WRITE_REG(hw
, IXGBE_TXDCTL(reg_idx
), IXGBE_TXDCTL_SWFLSH
);
4266 /* Disable the Tx DMA engine on 82599 and X540 */
4267 switch (hw
->mac
.type
) {
4268 case ixgbe_mac_82599EB
:
4269 case ixgbe_mac_X540
:
4270 IXGBE_WRITE_REG(hw
, IXGBE_DMATXCTL
,
4271 (IXGBE_READ_REG(hw
, IXGBE_DMATXCTL
) &
4272 ~IXGBE_DMATXCTL_TE
));
4278 if (!pci_channel_offline(adapter
->pdev
))
4279 ixgbe_reset(adapter
);
4281 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4282 if (hw
->mac
.ops
.disable_tx_laser
&&
4283 ((hw
->phy
.multispeed_fiber
) ||
4284 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
4285 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
4286 hw
->mac
.ops
.disable_tx_laser(hw
);
4288 ixgbe_clean_all_tx_rings(adapter
);
4289 ixgbe_clean_all_rx_rings(adapter
);
4291 #ifdef CONFIG_IXGBE_DCA
4292 /* since we reset the hardware DCA settings were cleared */
4293 ixgbe_setup_dca(adapter
);
4298 * ixgbe_poll - NAPI Rx polling callback
4299 * @napi: structure for representing this polling device
4300 * @budget: how many packets driver is allowed to clean
4302 * This function is used for legacy and MSI, NAPI mode
4304 static int ixgbe_poll(struct napi_struct
*napi
, int budget
)
4306 struct ixgbe_q_vector
*q_vector
=
4307 container_of(napi
, struct ixgbe_q_vector
, napi
);
4308 struct ixgbe_adapter
*adapter
= q_vector
->adapter
;
4309 int tx_clean_complete
, work_done
= 0;
4311 #ifdef CONFIG_IXGBE_DCA
4312 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
)
4313 ixgbe_update_dca(q_vector
);
4316 tx_clean_complete
= ixgbe_clean_tx_irq(q_vector
, adapter
->tx_ring
[0]);
4317 ixgbe_clean_rx_irq(q_vector
, adapter
->rx_ring
[0], &work_done
, budget
);
4319 if (!tx_clean_complete
)
4322 /* If budget not fully consumed, exit the polling mode */
4323 if (work_done
< budget
) {
4324 napi_complete(napi
);
4325 if (adapter
->rx_itr_setting
& 1)
4326 ixgbe_set_itr(adapter
);
4327 if (!test_bit(__IXGBE_DOWN
, &adapter
->state
))
4328 ixgbe_irq_enable_queues(adapter
, IXGBE_EIMS_RTX_QUEUE
);
4334 * ixgbe_tx_timeout - Respond to a Tx Hang
4335 * @netdev: network interface device structure
4337 static void ixgbe_tx_timeout(struct net_device
*netdev
)
4339 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
4341 /* Do the reset outside of interrupt context */
4342 ixgbe_tx_timeout_reset(adapter
);
4346 * ixgbe_set_rss_queues: Allocate queues for RSS
4347 * @adapter: board private structure to initialize
4349 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4350 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4353 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter
*adapter
)
4356 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_RSS
];
4358 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4360 adapter
->num_rx_queues
= f
->indices
;
4361 adapter
->num_tx_queues
= f
->indices
;
4371 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4372 * @adapter: board private structure to initialize
4374 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4375 * to the original CPU that initiated the Tx session. This runs in addition
4376 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4377 * Rx load across CPUs using RSS.
4380 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter
*adapter
)
4383 struct ixgbe_ring_feature
*f_fdir
= &adapter
->ring_feature
[RING_F_FDIR
];
4385 f_fdir
->indices
= min((int)num_online_cpus(), f_fdir
->indices
);
4388 /* Flow Director must have RSS enabled */
4389 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4390 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
||
4391 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)))) {
4392 adapter
->num_tx_queues
= f_fdir
->indices
;
4393 adapter
->num_rx_queues
= f_fdir
->indices
;
4396 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4397 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4404 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4405 * @adapter: board private structure to initialize
4407 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4408 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4409 * rx queues out of the max number of rx queues, instead, it is used as the
4410 * index of the first rx queue used by FCoE.
4413 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter
*adapter
)
4415 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4417 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4420 f
->indices
= min((int)num_online_cpus(), f
->indices
);
4422 adapter
->num_rx_queues
= 1;
4423 adapter
->num_tx_queues
= 1;
4425 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4426 e_info(probe
, "FCoE enabled with RSS\n");
4427 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4428 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4429 ixgbe_set_fdir_queues(adapter
);
4431 ixgbe_set_rss_queues(adapter
);
4433 /* adding FCoE rx rings to the end */
4434 f
->mask
= adapter
->num_rx_queues
;
4435 adapter
->num_rx_queues
+= f
->indices
;
4436 adapter
->num_tx_queues
+= f
->indices
;
4440 #endif /* IXGBE_FCOE */
4442 /* Artificial max queue cap per traffic class in DCB mode */
4443 #define DCB_QUEUE_CAP 8
4445 #ifdef CONFIG_IXGBE_DCB
4446 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter
*adapter
)
4448 int per_tc_q
, q
, i
, offset
= 0;
4449 struct net_device
*dev
= adapter
->netdev
;
4450 int tcs
= netdev_get_num_tc(dev
);
4455 /* Map queue offset and counts onto allocated tx queues */
4456 per_tc_q
= min(dev
->num_tx_queues
/ tcs
, (unsigned int)DCB_QUEUE_CAP
);
4457 q
= min((int)num_online_cpus(), per_tc_q
);
4459 for (i
= 0; i
< tcs
; i
++) {
4460 netdev_set_prio_tc_map(dev
, i
, i
);
4461 netdev_set_tc_queue(dev
, i
, q
, offset
);
4465 adapter
->num_tx_queues
= q
* tcs
;
4466 adapter
->num_rx_queues
= q
* tcs
;
4469 /* FCoE enabled queues require special configuration indexed
4470 * by feature specific indices and mask. Here we map FCoE
4471 * indices onto the DCB queue pairs allowing FCoE to own
4472 * configuration later.
4474 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
) {
4476 struct ixgbe_ring_feature
*f
=
4477 &adapter
->ring_feature
[RING_F_FCOE
];
4479 tc
= netdev_get_prio_tc_map(dev
, adapter
->fcoe
.up
);
4480 f
->indices
= dev
->tc_to_txq
[tc
].count
;
4481 f
->mask
= dev
->tc_to_txq
[tc
].offset
;
4490 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4491 * @adapter: board private structure to initialize
4493 * IOV doesn't actually use anything, so just NAK the
4494 * request for now and let the other queue routines
4495 * figure out what to do.
4497 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter
*adapter
)
4503 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4504 * @adapter: board private structure to initialize
4506 * This is the top level queue allocation routine. The order here is very
4507 * important, starting with the "most" number of features turned on at once,
4508 * and ending with the smallest set of features. This way large combinations
4509 * can be allocated if they're turned on, and smaller combinations are the
4510 * fallthrough conditions.
4513 static int ixgbe_set_num_queues(struct ixgbe_adapter
*adapter
)
4515 /* Start with base case */
4516 adapter
->num_rx_queues
= 1;
4517 adapter
->num_tx_queues
= 1;
4518 adapter
->num_rx_pools
= adapter
->num_rx_queues
;
4519 adapter
->num_rx_queues_per_pool
= 1;
4521 if (ixgbe_set_sriov_queues(adapter
))
4524 #ifdef CONFIG_IXGBE_DCB
4525 if (ixgbe_set_dcb_queues(adapter
))
4530 if (ixgbe_set_fcoe_queues(adapter
))
4533 #endif /* IXGBE_FCOE */
4534 if (ixgbe_set_fdir_queues(adapter
))
4537 if (ixgbe_set_rss_queues(adapter
))
4540 /* fallback to base case */
4541 adapter
->num_rx_queues
= 1;
4542 adapter
->num_tx_queues
= 1;
4545 /* Notify the stack of the (possibly) reduced queue counts. */
4546 netif_set_real_num_tx_queues(adapter
->netdev
, adapter
->num_tx_queues
);
4547 return netif_set_real_num_rx_queues(adapter
->netdev
,
4548 adapter
->num_rx_queues
);
4551 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter
*adapter
,
4554 int err
, vector_threshold
;
4556 /* We'll want at least 3 (vector_threshold):
4559 * 3) Other (Link Status Change, etc.)
4560 * 4) TCP Timer (optional)
4562 vector_threshold
= MIN_MSIX_COUNT
;
4564 /* The more we get, the more we will assign to Tx/Rx Cleanup
4565 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4566 * Right now, we simply care about how many we'll get; we'll
4567 * set them up later while requesting irq's.
4569 while (vectors
>= vector_threshold
) {
4570 err
= pci_enable_msix(adapter
->pdev
, adapter
->msix_entries
,
4572 if (!err
) /* Success in acquiring all requested vectors. */
4575 vectors
= 0; /* Nasty failure, quit now */
4576 else /* err == number of vectors we should try again with */
4580 if (vectors
< vector_threshold
) {
4581 /* Can't allocate enough MSI-X interrupts? Oh well.
4582 * This just means we'll go with either a single MSI
4583 * vector or fall back to legacy interrupts.
4585 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4586 "Unable to allocate MSI-X interrupts\n");
4587 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
4588 kfree(adapter
->msix_entries
);
4589 adapter
->msix_entries
= NULL
;
4591 adapter
->flags
|= IXGBE_FLAG_MSIX_ENABLED
; /* Woot! */
4593 * Adjust for only the vectors we'll use, which is minimum
4594 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4595 * vectors we were allocated.
4597 adapter
->num_msix_vectors
= min(vectors
,
4598 adapter
->max_msix_q_vectors
+ NON_Q_VECTORS
);
4603 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4604 * @adapter: board private structure to initialize
4606 * Cache the descriptor ring offsets for RSS to the assigned rings.
4609 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter
*adapter
)
4613 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
4616 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4617 adapter
->rx_ring
[i
]->reg_idx
= i
;
4618 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4619 adapter
->tx_ring
[i
]->reg_idx
= i
;
4624 #ifdef CONFIG_IXGBE_DCB
4626 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4627 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter
*adapter
, u8 tc
,
4628 unsigned int *tx
, unsigned int *rx
)
4630 struct net_device
*dev
= adapter
->netdev
;
4631 struct ixgbe_hw
*hw
= &adapter
->hw
;
4632 u8 num_tcs
= netdev_get_num_tc(dev
);
4637 switch (hw
->mac
.type
) {
4638 case ixgbe_mac_82598EB
:
4642 case ixgbe_mac_82599EB
:
4643 case ixgbe_mac_X540
:
4648 } else if (tc
< 5) {
4649 *tx
= ((tc
+ 2) << 4);
4651 } else if (tc
< num_tcs
) {
4652 *tx
= ((tc
+ 8) << 3);
4655 } else if (num_tcs
== 4) {
4681 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4682 * @adapter: board private structure to initialize
4684 * Cache the descriptor ring offsets for DCB to the assigned rings.
4687 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter
*adapter
)
4689 struct net_device
*dev
= adapter
->netdev
;
4691 u8 num_tcs
= netdev_get_num_tc(dev
);
4696 for (i
= 0, k
= 0; i
< num_tcs
; i
++) {
4697 unsigned int tx_s
, rx_s
;
4698 u16 count
= dev
->tc_to_txq
[i
].count
;
4700 ixgbe_get_first_reg_idx(adapter
, i
, &tx_s
, &rx_s
);
4701 for (j
= 0; j
< count
; j
++, k
++) {
4702 adapter
->tx_ring
[k
]->reg_idx
= tx_s
+ j
;
4703 adapter
->rx_ring
[k
]->reg_idx
= rx_s
+ j
;
4704 adapter
->tx_ring
[k
]->dcb_tc
= i
;
4705 adapter
->rx_ring
[k
]->dcb_tc
= i
;
4714 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4715 * @adapter: board private structure to initialize
4717 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4720 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter
*adapter
)
4725 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
&&
4726 ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4727 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))) {
4728 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
4729 adapter
->rx_ring
[i
]->reg_idx
= i
;
4730 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
4731 adapter
->tx_ring
[i
]->reg_idx
= i
;
4740 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4741 * @adapter: board private structure to initialize
4743 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4746 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter
*adapter
)
4748 struct ixgbe_ring_feature
*f
= &adapter
->ring_feature
[RING_F_FCOE
];
4750 u8 fcoe_rx_i
= 0, fcoe_tx_i
= 0;
4752 if (!(adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
))
4755 if (adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
) {
4756 if ((adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) ||
4757 (adapter
->flags
& IXGBE_FLAG_FDIR_PERFECT_CAPABLE
))
4758 ixgbe_cache_ring_fdir(adapter
);
4760 ixgbe_cache_ring_rss(adapter
);
4762 fcoe_rx_i
= f
->mask
;
4763 fcoe_tx_i
= f
->mask
;
4765 for (i
= 0; i
< f
->indices
; i
++, fcoe_rx_i
++, fcoe_tx_i
++) {
4766 adapter
->rx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_rx_i
;
4767 adapter
->tx_ring
[f
->mask
+ i
]->reg_idx
= fcoe_tx_i
;
4772 #endif /* IXGBE_FCOE */
4774 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4775 * @adapter: board private structure to initialize
4777 * SR-IOV doesn't use any descriptor rings but changes the default if
4778 * no other mapping is used.
4781 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter
*adapter
)
4783 adapter
->rx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4784 adapter
->tx_ring
[0]->reg_idx
= adapter
->num_vfs
* 2;
4785 if (adapter
->num_vfs
)
4792 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4793 * @adapter: board private structure to initialize
4795 * Once we know the feature-set enabled for the device, we'll cache
4796 * the register offset the descriptor ring is assigned to.
4798 * Note, the order the various feature calls is important. It must start with
4799 * the "most" features enabled at the same time, then trickle down to the
4800 * least amount of features turned on at once.
4802 static void ixgbe_cache_ring_register(struct ixgbe_adapter
*adapter
)
4804 /* start with default case */
4805 adapter
->rx_ring
[0]->reg_idx
= 0;
4806 adapter
->tx_ring
[0]->reg_idx
= 0;
4808 if (ixgbe_cache_ring_sriov(adapter
))
4811 #ifdef CONFIG_IXGBE_DCB
4812 if (ixgbe_cache_ring_dcb(adapter
))
4817 if (ixgbe_cache_ring_fcoe(adapter
))
4819 #endif /* IXGBE_FCOE */
4821 if (ixgbe_cache_ring_fdir(adapter
))
4824 if (ixgbe_cache_ring_rss(adapter
))
4829 * ixgbe_alloc_queues - Allocate memory for all rings
4830 * @adapter: board private structure to initialize
4832 * We allocate one ring per queue at run-time since we don't know the
4833 * number of queues at compile-time. The polling_netdev array is
4834 * intended for Multiqueue, but should work fine with a single queue.
4836 static int ixgbe_alloc_queues(struct ixgbe_adapter
*adapter
)
4838 int rx
= 0, tx
= 0, nid
= adapter
->node
;
4840 if (nid
< 0 || !node_online(nid
))
4841 nid
= first_online_node
;
4843 for (; tx
< adapter
->num_tx_queues
; tx
++) {
4844 struct ixgbe_ring
*ring
;
4846 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4848 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4850 goto err_allocation
;
4851 ring
->count
= adapter
->tx_ring_count
;
4852 ring
->queue_index
= tx
;
4853 ring
->numa_node
= nid
;
4854 ring
->dev
= &adapter
->pdev
->dev
;
4855 ring
->netdev
= adapter
->netdev
;
4857 adapter
->tx_ring
[tx
] = ring
;
4860 for (; rx
< adapter
->num_rx_queues
; rx
++) {
4861 struct ixgbe_ring
*ring
;
4863 ring
= kzalloc_node(sizeof(*ring
), GFP_KERNEL
, nid
);
4865 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
4867 goto err_allocation
;
4868 ring
->count
= adapter
->rx_ring_count
;
4869 ring
->queue_index
= rx
;
4870 ring
->numa_node
= nid
;
4871 ring
->dev
= &adapter
->pdev
->dev
;
4872 ring
->netdev
= adapter
->netdev
;
4874 adapter
->rx_ring
[rx
] = ring
;
4877 ixgbe_cache_ring_register(adapter
);
4883 kfree(adapter
->tx_ring
[--tx
]);
4886 kfree(adapter
->rx_ring
[--rx
]);
4891 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4892 * @adapter: board private structure to initialize
4894 * Attempt to configure the interrupts using the best available
4895 * capabilities of the hardware and the kernel.
4897 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter
*adapter
)
4899 struct ixgbe_hw
*hw
= &adapter
->hw
;
4901 int vector
, v_budget
;
4904 * It's easy to be greedy for MSI-X vectors, but it really
4905 * doesn't do us much good if we have a lot more vectors
4906 * than CPU's. So let's be conservative and only ask for
4907 * (roughly) the same number of vectors as there are CPU's.
4909 v_budget
= min(adapter
->num_rx_queues
+ adapter
->num_tx_queues
,
4910 (int)num_online_cpus()) + NON_Q_VECTORS
;
4913 * At the same time, hardware can only support a maximum of
4914 * hw.mac->max_msix_vectors vectors. With features
4915 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4916 * descriptor queues supported by our device. Thus, we cap it off in
4917 * those rare cases where the cpu count also exceeds our vector limit.
4919 v_budget
= min(v_budget
, (int)hw
->mac
.max_msix_vectors
);
4921 /* A failure in MSI-X entry allocation isn't fatal, but it does
4922 * mean we disable MSI-X capabilities of the adapter. */
4923 adapter
->msix_entries
= kcalloc(v_budget
,
4924 sizeof(struct msix_entry
), GFP_KERNEL
);
4925 if (adapter
->msix_entries
) {
4926 for (vector
= 0; vector
< v_budget
; vector
++)
4927 adapter
->msix_entries
[vector
].entry
= vector
;
4929 ixgbe_acquire_msix_vectors(adapter
, v_budget
);
4931 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
4935 adapter
->flags
&= ~IXGBE_FLAG_DCB_ENABLED
;
4936 adapter
->flags
&= ~IXGBE_FLAG_RSS_ENABLED
;
4937 if (adapter
->flags
& (IXGBE_FLAG_FDIR_HASH_CAPABLE
|
4938 IXGBE_FLAG_FDIR_PERFECT_CAPABLE
)) {
4940 "Flow Director is not supported while multiple "
4941 "queues are disabled. Disabling Flow Director\n");
4943 adapter
->flags
&= ~IXGBE_FLAG_FDIR_HASH_CAPABLE
;
4944 adapter
->flags
&= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE
;
4945 adapter
->atr_sample_rate
= 0;
4946 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
4947 ixgbe_disable_sriov(adapter
);
4949 err
= ixgbe_set_num_queues(adapter
);
4953 err
= pci_enable_msi(adapter
->pdev
);
4955 adapter
->flags
|= IXGBE_FLAG_MSI_ENABLED
;
4957 netif_printk(adapter
, hw
, KERN_DEBUG
, adapter
->netdev
,
4958 "Unable to allocate MSI interrupt, "
4959 "falling back to legacy. Error: %d\n", err
);
4969 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4970 * @adapter: board private structure to initialize
4972 * We allocate one q_vector per queue interrupt. If allocation fails we
4975 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter
*adapter
)
4977 int q_idx
, num_q_vectors
;
4978 struct ixgbe_q_vector
*q_vector
;
4979 int (*poll
)(struct napi_struct
*, int);
4981 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
4982 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
4983 poll
= &ixgbe_clean_rxtx_many
;
4989 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
4990 q_vector
= kzalloc_node(sizeof(struct ixgbe_q_vector
),
4991 GFP_KERNEL
, adapter
->node
);
4993 q_vector
= kzalloc(sizeof(struct ixgbe_q_vector
),
4997 q_vector
->adapter
= adapter
;
4998 if (q_vector
->txr_count
&& !q_vector
->rxr_count
)
4999 q_vector
->eitr
= adapter
->tx_eitr_param
;
5001 q_vector
->eitr
= adapter
->rx_eitr_param
;
5002 q_vector
->v_idx
= q_idx
;
5003 netif_napi_add(adapter
->netdev
, &q_vector
->napi
, (*poll
), 64);
5004 adapter
->q_vector
[q_idx
] = q_vector
;
5012 q_vector
= adapter
->q_vector
[q_idx
];
5013 netif_napi_del(&q_vector
->napi
);
5015 adapter
->q_vector
[q_idx
] = NULL
;
5021 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
5022 * @adapter: board private structure to initialize
5024 * This function frees the memory allocated to the q_vectors. In addition if
5025 * NAPI is enabled it will delete any references to the NAPI struct prior
5026 * to freeing the q_vector.
5028 static void ixgbe_free_q_vectors(struct ixgbe_adapter
*adapter
)
5030 int q_idx
, num_q_vectors
;
5032 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)
5033 num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
5037 for (q_idx
= 0; q_idx
< num_q_vectors
; q_idx
++) {
5038 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[q_idx
];
5039 adapter
->q_vector
[q_idx
] = NULL
;
5040 netif_napi_del(&q_vector
->napi
);
5045 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter
*adapter
)
5047 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
5048 adapter
->flags
&= ~IXGBE_FLAG_MSIX_ENABLED
;
5049 pci_disable_msix(adapter
->pdev
);
5050 kfree(adapter
->msix_entries
);
5051 adapter
->msix_entries
= NULL
;
5052 } else if (adapter
->flags
& IXGBE_FLAG_MSI_ENABLED
) {
5053 adapter
->flags
&= ~IXGBE_FLAG_MSI_ENABLED
;
5054 pci_disable_msi(adapter
->pdev
);
5059 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5060 * @adapter: board private structure to initialize
5062 * We determine which interrupt scheme to use based on...
5063 * - Kernel support (MSI, MSI-X)
5064 * - which can be user-defined (via MODULE_PARAM)
5065 * - Hardware queue count (num_*_queues)
5066 * - defined by miscellaneous hardware support/features (RSS, etc.)
5068 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5072 /* Number of supported queues */
5073 err
= ixgbe_set_num_queues(adapter
);
5077 err
= ixgbe_set_interrupt_capability(adapter
);
5079 e_dev_err("Unable to setup interrupt capabilities\n");
5080 goto err_set_interrupt
;
5083 err
= ixgbe_alloc_q_vectors(adapter
);
5085 e_dev_err("Unable to allocate memory for queue vectors\n");
5086 goto err_alloc_q_vectors
;
5089 err
= ixgbe_alloc_queues(adapter
);
5091 e_dev_err("Unable to allocate memory for queues\n");
5092 goto err_alloc_queues
;
5095 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5096 (adapter
->num_rx_queues
> 1) ? "Enabled" : "Disabled",
5097 adapter
->num_rx_queues
, adapter
->num_tx_queues
);
5099 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5104 ixgbe_free_q_vectors(adapter
);
5105 err_alloc_q_vectors
:
5106 ixgbe_reset_interrupt_capability(adapter
);
5112 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5113 * @adapter: board private structure to clear interrupt scheme on
5115 * We go through and clear interrupt specific resources and reset the structure
5116 * to pre-load conditions
5118 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter
*adapter
)
5122 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5123 kfree(adapter
->tx_ring
[i
]);
5124 adapter
->tx_ring
[i
] = NULL
;
5126 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5127 struct ixgbe_ring
*ring
= adapter
->rx_ring
[i
];
5129 /* ixgbe_get_stats64() might access this ring, we must wait
5130 * a grace period before freeing it.
5132 kfree_rcu(ring
, rcu
);
5133 adapter
->rx_ring
[i
] = NULL
;
5136 adapter
->num_tx_queues
= 0;
5137 adapter
->num_rx_queues
= 0;
5139 ixgbe_free_q_vectors(adapter
);
5140 ixgbe_reset_interrupt_capability(adapter
);
5144 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5145 * @adapter: board private structure to initialize
5147 * ixgbe_sw_init initializes the Adapter private data structure.
5148 * Fields are initialized based on PCI device information and
5149 * OS network device settings (MTU size).
5151 static int __devinit
ixgbe_sw_init(struct ixgbe_adapter
*adapter
)
5153 struct ixgbe_hw
*hw
= &adapter
->hw
;
5154 struct pci_dev
*pdev
= adapter
->pdev
;
5155 struct net_device
*dev
= adapter
->netdev
;
5157 #ifdef CONFIG_IXGBE_DCB
5159 struct tc_configuration
*tc
;
5161 int max_frame
= dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5163 /* PCI config space info */
5165 hw
->vendor_id
= pdev
->vendor
;
5166 hw
->device_id
= pdev
->device
;
5167 hw
->revision_id
= pdev
->revision
;
5168 hw
->subsystem_vendor_id
= pdev
->subsystem_vendor
;
5169 hw
->subsystem_device_id
= pdev
->subsystem_device
;
5171 /* Set capability flags */
5172 rss
= min(IXGBE_MAX_RSS_INDICES
, (int)num_online_cpus());
5173 adapter
->ring_feature
[RING_F_RSS
].indices
= rss
;
5174 adapter
->flags
|= IXGBE_FLAG_RSS_ENABLED
;
5175 switch (hw
->mac
.type
) {
5176 case ixgbe_mac_82598EB
:
5177 if (hw
->device_id
== IXGBE_DEV_ID_82598AT
)
5178 adapter
->flags
|= IXGBE_FLAG_FAN_FAIL_CAPABLE
;
5179 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82598
;
5181 case ixgbe_mac_82599EB
:
5182 case ixgbe_mac_X540
:
5183 adapter
->max_msix_q_vectors
= MAX_MSIX_Q_VECTORS_82599
;
5184 adapter
->flags2
|= IXGBE_FLAG2_RSC_CAPABLE
;
5185 adapter
->flags2
|= IXGBE_FLAG2_RSC_ENABLED
;
5186 if (hw
->device_id
== IXGBE_DEV_ID_82599_T3_LOM
)
5187 adapter
->flags2
|= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE
;
5188 /* n-tuple support exists, always init our spinlock */
5189 spin_lock_init(&adapter
->fdir_perfect_lock
);
5190 /* Flow Director hash filters enabled */
5191 adapter
->flags
|= IXGBE_FLAG_FDIR_HASH_CAPABLE
;
5192 adapter
->atr_sample_rate
= 20;
5193 adapter
->ring_feature
[RING_F_FDIR
].indices
=
5194 IXGBE_MAX_FDIR_INDICES
;
5195 adapter
->fdir_pballoc
= 0;
5197 adapter
->flags
|= IXGBE_FLAG_FCOE_CAPABLE
;
5198 adapter
->flags
&= ~IXGBE_FLAG_FCOE_ENABLED
;
5199 adapter
->ring_feature
[RING_F_FCOE
].indices
= 0;
5200 #ifdef CONFIG_IXGBE_DCB
5201 /* Default traffic class to use for FCoE */
5202 adapter
->fcoe
.tc
= IXGBE_FCOE_DEFTC
;
5203 adapter
->fcoe
.up
= IXGBE_FCOE_DEFTC
;
5205 #endif /* IXGBE_FCOE */
5211 #ifdef CONFIG_IXGBE_DCB
5212 /* Configure DCB traffic classes */
5213 for (j
= 0; j
< MAX_TRAFFIC_CLASS
; j
++) {
5214 tc
= &adapter
->dcb_cfg
.tc_config
[j
];
5215 tc
->path
[DCB_TX_CONFIG
].bwg_id
= 0;
5216 tc
->path
[DCB_TX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5217 tc
->path
[DCB_RX_CONFIG
].bwg_id
= 0;
5218 tc
->path
[DCB_RX_CONFIG
].bwg_percent
= 12 + (j
& 1);
5219 tc
->dcb_pfc
= pfc_disabled
;
5221 adapter
->dcb_cfg
.bw_percentage
[DCB_TX_CONFIG
][0] = 100;
5222 adapter
->dcb_cfg
.bw_percentage
[DCB_RX_CONFIG
][0] = 100;
5223 adapter
->dcb_cfg
.pfc_mode_enable
= false;
5224 adapter
->dcb_set_bitmap
= 0x00;
5225 adapter
->dcbx_cap
= DCB_CAP_DCBX_HOST
| DCB_CAP_DCBX_VER_CEE
;
5226 ixgbe_copy_dcb_cfg(&adapter
->dcb_cfg
, &adapter
->temp_dcb_cfg
,
5231 /* default flow control settings */
5232 hw
->fc
.requested_mode
= ixgbe_fc_full
;
5233 hw
->fc
.current_mode
= ixgbe_fc_full
; /* init for ethtool output */
5235 adapter
->last_lfc_mode
= hw
->fc
.current_mode
;
5237 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5238 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5239 hw
->fc
.pause_time
= IXGBE_DEFAULT_FCPAUSE
;
5240 hw
->fc
.send_xon
= true;
5241 hw
->fc
.disable_fc_autoneg
= false;
5243 /* enable itr by default in dynamic mode */
5244 adapter
->rx_itr_setting
= 1;
5245 adapter
->rx_eitr_param
= 20000;
5246 adapter
->tx_itr_setting
= 1;
5247 adapter
->tx_eitr_param
= 10000;
5249 /* set defaults for eitr in MegaBytes */
5250 adapter
->eitr_low
= 10;
5251 adapter
->eitr_high
= 20;
5253 /* set default ring sizes */
5254 adapter
->tx_ring_count
= IXGBE_DEFAULT_TXD
;
5255 adapter
->rx_ring_count
= IXGBE_DEFAULT_RXD
;
5257 /* initialize eeprom parameters */
5258 if (ixgbe_init_eeprom_params_generic(hw
)) {
5259 e_dev_err("EEPROM initialization failed\n");
5263 /* enable rx csum by default */
5264 adapter
->flags
|= IXGBE_FLAG_RX_CSUM_ENABLED
;
5266 /* get assigned NUMA node */
5267 adapter
->node
= dev_to_node(&pdev
->dev
);
5269 set_bit(__IXGBE_DOWN
, &adapter
->state
);
5275 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5276 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5278 * Return 0 on success, negative on failure
5280 int ixgbe_setup_tx_resources(struct ixgbe_ring
*tx_ring
)
5282 struct device
*dev
= tx_ring
->dev
;
5285 size
= sizeof(struct ixgbe_tx_buffer
) * tx_ring
->count
;
5286 tx_ring
->tx_buffer_info
= vzalloc_node(size
, tx_ring
->numa_node
);
5287 if (!tx_ring
->tx_buffer_info
)
5288 tx_ring
->tx_buffer_info
= vzalloc(size
);
5289 if (!tx_ring
->tx_buffer_info
)
5292 /* round up to nearest 4K */
5293 tx_ring
->size
= tx_ring
->count
* sizeof(union ixgbe_adv_tx_desc
);
5294 tx_ring
->size
= ALIGN(tx_ring
->size
, 4096);
5296 tx_ring
->desc
= dma_alloc_coherent(dev
, tx_ring
->size
,
5297 &tx_ring
->dma
, GFP_KERNEL
);
5301 tx_ring
->next_to_use
= 0;
5302 tx_ring
->next_to_clean
= 0;
5303 tx_ring
->work_limit
= tx_ring
->count
;
5307 vfree(tx_ring
->tx_buffer_info
);
5308 tx_ring
->tx_buffer_info
= NULL
;
5309 dev_err(dev
, "Unable to allocate memory for the Tx descriptor ring\n");
5314 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5315 * @adapter: board private structure
5317 * If this function returns with an error, then it's possible one or
5318 * more of the rings is populated (while the rest are not). It is the
5319 * callers duty to clean those orphaned rings.
5321 * Return 0 on success, negative on failure
5323 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter
*adapter
)
5327 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5328 err
= ixgbe_setup_tx_resources(adapter
->tx_ring
[i
]);
5331 e_err(probe
, "Allocation for Tx Queue %u failed\n", i
);
5339 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5340 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5342 * Returns 0 on success, negative on failure
5344 int ixgbe_setup_rx_resources(struct ixgbe_ring
*rx_ring
)
5346 struct device
*dev
= rx_ring
->dev
;
5349 size
= sizeof(struct ixgbe_rx_buffer
) * rx_ring
->count
;
5350 rx_ring
->rx_buffer_info
= vzalloc_node(size
, rx_ring
->numa_node
);
5351 if (!rx_ring
->rx_buffer_info
)
5352 rx_ring
->rx_buffer_info
= vzalloc(size
);
5353 if (!rx_ring
->rx_buffer_info
)
5356 /* Round up to nearest 4K */
5357 rx_ring
->size
= rx_ring
->count
* sizeof(union ixgbe_adv_rx_desc
);
5358 rx_ring
->size
= ALIGN(rx_ring
->size
, 4096);
5360 rx_ring
->desc
= dma_alloc_coherent(dev
, rx_ring
->size
,
5361 &rx_ring
->dma
, GFP_KERNEL
);
5366 rx_ring
->next_to_clean
= 0;
5367 rx_ring
->next_to_use
= 0;
5371 vfree(rx_ring
->rx_buffer_info
);
5372 rx_ring
->rx_buffer_info
= NULL
;
5373 dev_err(dev
, "Unable to allocate memory for the Rx descriptor ring\n");
5378 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5379 * @adapter: board private structure
5381 * If this function returns with an error, then it's possible one or
5382 * more of the rings is populated (while the rest are not). It is the
5383 * callers duty to clean those orphaned rings.
5385 * Return 0 on success, negative on failure
5387 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter
*adapter
)
5391 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5392 err
= ixgbe_setup_rx_resources(adapter
->rx_ring
[i
]);
5395 e_err(probe
, "Allocation for Rx Queue %u failed\n", i
);
5403 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5404 * @tx_ring: Tx descriptor ring for a specific queue
5406 * Free all transmit software resources
5408 void ixgbe_free_tx_resources(struct ixgbe_ring
*tx_ring
)
5410 ixgbe_clean_tx_ring(tx_ring
);
5412 vfree(tx_ring
->tx_buffer_info
);
5413 tx_ring
->tx_buffer_info
= NULL
;
5415 /* if not set, then don't free */
5419 dma_free_coherent(tx_ring
->dev
, tx_ring
->size
,
5420 tx_ring
->desc
, tx_ring
->dma
);
5422 tx_ring
->desc
= NULL
;
5426 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5427 * @adapter: board private structure
5429 * Free all transmit software resources
5431 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter
*adapter
)
5435 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5436 if (adapter
->tx_ring
[i
]->desc
)
5437 ixgbe_free_tx_resources(adapter
->tx_ring
[i
]);
5441 * ixgbe_free_rx_resources - Free Rx Resources
5442 * @rx_ring: ring to clean the resources from
5444 * Free all receive software resources
5446 void ixgbe_free_rx_resources(struct ixgbe_ring
*rx_ring
)
5448 ixgbe_clean_rx_ring(rx_ring
);
5450 vfree(rx_ring
->rx_buffer_info
);
5451 rx_ring
->rx_buffer_info
= NULL
;
5453 /* if not set, then don't free */
5457 dma_free_coherent(rx_ring
->dev
, rx_ring
->size
,
5458 rx_ring
->desc
, rx_ring
->dma
);
5460 rx_ring
->desc
= NULL
;
5464 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5465 * @adapter: board private structure
5467 * Free all receive software resources
5469 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter
*adapter
)
5473 for (i
= 0; i
< adapter
->num_rx_queues
; i
++)
5474 if (adapter
->rx_ring
[i
]->desc
)
5475 ixgbe_free_rx_resources(adapter
->rx_ring
[i
]);
5479 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5480 * @netdev: network interface device structure
5481 * @new_mtu: new value for maximum frame size
5483 * Returns 0 on success, negative on failure
5485 static int ixgbe_change_mtu(struct net_device
*netdev
, int new_mtu
)
5487 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5488 struct ixgbe_hw
*hw
= &adapter
->hw
;
5489 int max_frame
= new_mtu
+ ETH_HLEN
+ ETH_FCS_LEN
;
5491 /* MTU < 68 is an error and causes problems on some kernels */
5492 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
&&
5493 hw
->mac
.type
!= ixgbe_mac_X540
) {
5494 if ((new_mtu
< 68) || (max_frame
> MAXIMUM_ETHERNET_VLAN_SIZE
))
5497 if ((new_mtu
< 68) || (max_frame
> IXGBE_MAX_JUMBO_FRAME_SIZE
))
5501 e_info(probe
, "changing MTU from %d to %d\n", netdev
->mtu
, new_mtu
);
5502 /* must set new MTU before calling down or up */
5503 netdev
->mtu
= new_mtu
;
5505 hw
->fc
.high_water
= FC_HIGH_WATER(max_frame
);
5506 hw
->fc
.low_water
= FC_LOW_WATER(max_frame
);
5508 if (netif_running(netdev
))
5509 ixgbe_reinit_locked(adapter
);
5515 * ixgbe_open - Called when a network interface is made active
5516 * @netdev: network interface device structure
5518 * Returns 0 on success, negative value on failure
5520 * The open entry point is called when a network interface is made
5521 * active by the system (IFF_UP). At this point all resources needed
5522 * for transmit and receive operations are allocated, the interrupt
5523 * handler is registered with the OS, the watchdog timer is started,
5524 * and the stack is notified that the interface is ready.
5526 static int ixgbe_open(struct net_device
*netdev
)
5528 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5531 /* disallow open during test */
5532 if (test_bit(__IXGBE_TESTING
, &adapter
->state
))
5535 netif_carrier_off(netdev
);
5537 /* allocate transmit descriptors */
5538 err
= ixgbe_setup_all_tx_resources(adapter
);
5542 /* allocate receive descriptors */
5543 err
= ixgbe_setup_all_rx_resources(adapter
);
5547 ixgbe_configure(adapter
);
5549 err
= ixgbe_request_irq(adapter
);
5553 err
= ixgbe_up_complete(adapter
);
5557 netif_tx_start_all_queues(netdev
);
5562 ixgbe_release_hw_control(adapter
);
5563 ixgbe_free_irq(adapter
);
5566 ixgbe_free_all_rx_resources(adapter
);
5568 ixgbe_free_all_tx_resources(adapter
);
5569 ixgbe_reset(adapter
);
5575 * ixgbe_close - Disables a network interface
5576 * @netdev: network interface device structure
5578 * Returns 0, this is not allowed to fail
5580 * The close entry point is called when an interface is de-activated
5581 * by the OS. The hardware is still under the drivers control, but
5582 * needs to be disabled. A global MAC reset is issued to stop the
5583 * hardware, and all transmit and receive resources are freed.
5585 static int ixgbe_close(struct net_device
*netdev
)
5587 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
5589 ixgbe_down(adapter
);
5590 ixgbe_free_irq(adapter
);
5592 ixgbe_free_all_tx_resources(adapter
);
5593 ixgbe_free_all_rx_resources(adapter
);
5595 ixgbe_release_hw_control(adapter
);
5601 static int ixgbe_resume(struct pci_dev
*pdev
)
5603 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5604 struct net_device
*netdev
= adapter
->netdev
;
5607 pci_set_power_state(pdev
, PCI_D0
);
5608 pci_restore_state(pdev
);
5610 * pci_restore_state clears dev->state_saved so call
5611 * pci_save_state to restore it.
5613 pci_save_state(pdev
);
5615 err
= pci_enable_device_mem(pdev
);
5617 e_dev_err("Cannot enable PCI device from suspend\n");
5620 pci_set_master(pdev
);
5622 pci_wake_from_d3(pdev
, false);
5624 err
= ixgbe_init_interrupt_scheme(adapter
);
5626 e_dev_err("Cannot initialize interrupts for device\n");
5630 ixgbe_reset(adapter
);
5632 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
5634 if (netif_running(netdev
)) {
5635 err
= ixgbe_open(netdev
);
5640 netif_device_attach(netdev
);
5644 #endif /* CONFIG_PM */
5646 static int __ixgbe_shutdown(struct pci_dev
*pdev
, bool *enable_wake
)
5648 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
5649 struct net_device
*netdev
= adapter
->netdev
;
5650 struct ixgbe_hw
*hw
= &adapter
->hw
;
5652 u32 wufc
= adapter
->wol
;
5657 netif_device_detach(netdev
);
5659 if (netif_running(netdev
)) {
5660 ixgbe_down(adapter
);
5661 ixgbe_free_irq(adapter
);
5662 ixgbe_free_all_tx_resources(adapter
);
5663 ixgbe_free_all_rx_resources(adapter
);
5666 ixgbe_clear_interrupt_scheme(adapter
);
5668 kfree(adapter
->ixgbe_ieee_pfc
);
5669 kfree(adapter
->ixgbe_ieee_ets
);
5673 retval
= pci_save_state(pdev
);
5679 ixgbe_set_rx_mode(netdev
);
5681 /* turn on all-multi mode if wake on multicast is enabled */
5682 if (wufc
& IXGBE_WUFC_MC
) {
5683 fctrl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
5684 fctrl
|= IXGBE_FCTRL_MPE
;
5685 IXGBE_WRITE_REG(hw
, IXGBE_FCTRL
, fctrl
);
5688 ctrl
= IXGBE_READ_REG(hw
, IXGBE_CTRL
);
5689 ctrl
|= IXGBE_CTRL_GIO_DIS
;
5690 IXGBE_WRITE_REG(hw
, IXGBE_CTRL
, ctrl
);
5692 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, wufc
);
5694 IXGBE_WRITE_REG(hw
, IXGBE_WUC
, 0);
5695 IXGBE_WRITE_REG(hw
, IXGBE_WUFC
, 0);
5698 switch (hw
->mac
.type
) {
5699 case ixgbe_mac_82598EB
:
5700 pci_wake_from_d3(pdev
, false);
5702 case ixgbe_mac_82599EB
:
5703 case ixgbe_mac_X540
:
5704 pci_wake_from_d3(pdev
, !!wufc
);
5710 *enable_wake
= !!wufc
;
5712 ixgbe_release_hw_control(adapter
);
5714 pci_disable_device(pdev
);
5720 static int ixgbe_suspend(struct pci_dev
*pdev
, pm_message_t state
)
5725 retval
= __ixgbe_shutdown(pdev
, &wake
);
5730 pci_prepare_to_sleep(pdev
);
5732 pci_wake_from_d3(pdev
, false);
5733 pci_set_power_state(pdev
, PCI_D3hot
);
5738 #endif /* CONFIG_PM */
5740 static void ixgbe_shutdown(struct pci_dev
*pdev
)
5744 __ixgbe_shutdown(pdev
, &wake
);
5746 if (system_state
== SYSTEM_POWER_OFF
) {
5747 pci_wake_from_d3(pdev
, wake
);
5748 pci_set_power_state(pdev
, PCI_D3hot
);
5753 * ixgbe_update_stats - Update the board statistics counters.
5754 * @adapter: board private structure
5756 void ixgbe_update_stats(struct ixgbe_adapter
*adapter
)
5758 struct net_device
*netdev
= adapter
->netdev
;
5759 struct ixgbe_hw
*hw
= &adapter
->hw
;
5760 struct ixgbe_hw_stats
*hwstats
= &adapter
->stats
;
5762 u32 i
, missed_rx
= 0, mpc
, bprc
, lxon
, lxoff
, xon_off_tot
;
5763 u64 non_eop_descs
= 0, restart_queue
= 0, tx_busy
= 0;
5764 u64 alloc_rx_page_failed
= 0, alloc_rx_buff_failed
= 0;
5765 u64 bytes
= 0, packets
= 0;
5767 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5768 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5771 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
) {
5774 for (i
= 0; i
< 16; i
++)
5775 adapter
->hw_rx_no_dma_resources
+=
5776 IXGBE_READ_REG(hw
, IXGBE_QPRDC(i
));
5777 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5778 rsc_count
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_count
;
5779 rsc_flush
+= adapter
->rx_ring
[i
]->rx_stats
.rsc_flush
;
5781 adapter
->rsc_total_count
= rsc_count
;
5782 adapter
->rsc_total_flush
= rsc_flush
;
5785 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
5786 struct ixgbe_ring
*rx_ring
= adapter
->rx_ring
[i
];
5787 non_eop_descs
+= rx_ring
->rx_stats
.non_eop_descs
;
5788 alloc_rx_page_failed
+= rx_ring
->rx_stats
.alloc_rx_page_failed
;
5789 alloc_rx_buff_failed
+= rx_ring
->rx_stats
.alloc_rx_buff_failed
;
5790 bytes
+= rx_ring
->stats
.bytes
;
5791 packets
+= rx_ring
->stats
.packets
;
5793 adapter
->non_eop_descs
= non_eop_descs
;
5794 adapter
->alloc_rx_page_failed
= alloc_rx_page_failed
;
5795 adapter
->alloc_rx_buff_failed
= alloc_rx_buff_failed
;
5796 netdev
->stats
.rx_bytes
= bytes
;
5797 netdev
->stats
.rx_packets
= packets
;
5801 /* gather some stats to the adapter struct that are per queue */
5802 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
5803 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
5804 restart_queue
+= tx_ring
->tx_stats
.restart_queue
;
5805 tx_busy
+= tx_ring
->tx_stats
.tx_busy
;
5806 bytes
+= tx_ring
->stats
.bytes
;
5807 packets
+= tx_ring
->stats
.packets
;
5809 adapter
->restart_queue
= restart_queue
;
5810 adapter
->tx_busy
= tx_busy
;
5811 netdev
->stats
.tx_bytes
= bytes
;
5812 netdev
->stats
.tx_packets
= packets
;
5814 hwstats
->crcerrs
+= IXGBE_READ_REG(hw
, IXGBE_CRCERRS
);
5815 for (i
= 0; i
< 8; i
++) {
5816 /* for packet buffers not used, the register should read 0 */
5817 mpc
= IXGBE_READ_REG(hw
, IXGBE_MPC(i
));
5819 hwstats
->mpc
[i
] += mpc
;
5820 total_mpc
+= hwstats
->mpc
[i
];
5821 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5822 hwstats
->rnbc
[i
] += IXGBE_READ_REG(hw
, IXGBE_RNBC(i
));
5823 hwstats
->qptc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPTC(i
));
5824 hwstats
->qbtc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBTC(i
));
5825 hwstats
->qprc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QPRC(i
));
5826 hwstats
->qbrc
[i
] += IXGBE_READ_REG(hw
, IXGBE_QBRC(i
));
5827 switch (hw
->mac
.type
) {
5828 case ixgbe_mac_82598EB
:
5829 hwstats
->pxonrxc
[i
] +=
5830 IXGBE_READ_REG(hw
, IXGBE_PXONRXC(i
));
5832 case ixgbe_mac_82599EB
:
5833 case ixgbe_mac_X540
:
5834 hwstats
->pxonrxc
[i
] +=
5835 IXGBE_READ_REG(hw
, IXGBE_PXONRXCNT(i
));
5840 hwstats
->pxontxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXONTXC(i
));
5841 hwstats
->pxofftxc
[i
] += IXGBE_READ_REG(hw
, IXGBE_PXOFFTXC(i
));
5843 hwstats
->gprc
+= IXGBE_READ_REG(hw
, IXGBE_GPRC
);
5844 /* work around hardware counting issue */
5845 hwstats
->gprc
-= missed_rx
;
5847 ixgbe_update_xoff_received(adapter
);
5849 /* 82598 hardware only has a 32 bit counter in the high register */
5850 switch (hw
->mac
.type
) {
5851 case ixgbe_mac_82598EB
:
5852 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXC
);
5853 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCH
);
5854 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCH
);
5855 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORH
);
5857 case ixgbe_mac_X540
:
5858 /* OS2BMC stats are X540 only*/
5859 hwstats
->o2bgptc
+= IXGBE_READ_REG(hw
, IXGBE_O2BGPTC
);
5860 hwstats
->o2bspc
+= IXGBE_READ_REG(hw
, IXGBE_O2BSPC
);
5861 hwstats
->b2ospc
+= IXGBE_READ_REG(hw
, IXGBE_B2OSPC
);
5862 hwstats
->b2ogprc
+= IXGBE_READ_REG(hw
, IXGBE_B2OGPRC
);
5863 case ixgbe_mac_82599EB
:
5864 hwstats
->gorc
+= IXGBE_READ_REG(hw
, IXGBE_GORCL
);
5865 IXGBE_READ_REG(hw
, IXGBE_GORCH
); /* to clear */
5866 hwstats
->gotc
+= IXGBE_READ_REG(hw
, IXGBE_GOTCL
);
5867 IXGBE_READ_REG(hw
, IXGBE_GOTCH
); /* to clear */
5868 hwstats
->tor
+= IXGBE_READ_REG(hw
, IXGBE_TORL
);
5869 IXGBE_READ_REG(hw
, IXGBE_TORH
); /* to clear */
5870 hwstats
->lxonrxc
+= IXGBE_READ_REG(hw
, IXGBE_LXONRXCNT
);
5871 hwstats
->fdirmatch
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMATCH
);
5872 hwstats
->fdirmiss
+= IXGBE_READ_REG(hw
, IXGBE_FDIRMISS
);
5874 hwstats
->fccrc
+= IXGBE_READ_REG(hw
, IXGBE_FCCRC
);
5875 hwstats
->fcoerpdc
+= IXGBE_READ_REG(hw
, IXGBE_FCOERPDC
);
5876 hwstats
->fcoeprc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPRC
);
5877 hwstats
->fcoeptc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEPTC
);
5878 hwstats
->fcoedwrc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWRC
);
5879 hwstats
->fcoedwtc
+= IXGBE_READ_REG(hw
, IXGBE_FCOEDWTC
);
5880 #endif /* IXGBE_FCOE */
5885 bprc
= IXGBE_READ_REG(hw
, IXGBE_BPRC
);
5886 hwstats
->bprc
+= bprc
;
5887 hwstats
->mprc
+= IXGBE_READ_REG(hw
, IXGBE_MPRC
);
5888 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
5889 hwstats
->mprc
-= bprc
;
5890 hwstats
->roc
+= IXGBE_READ_REG(hw
, IXGBE_ROC
);
5891 hwstats
->prc64
+= IXGBE_READ_REG(hw
, IXGBE_PRC64
);
5892 hwstats
->prc127
+= IXGBE_READ_REG(hw
, IXGBE_PRC127
);
5893 hwstats
->prc255
+= IXGBE_READ_REG(hw
, IXGBE_PRC255
);
5894 hwstats
->prc511
+= IXGBE_READ_REG(hw
, IXGBE_PRC511
);
5895 hwstats
->prc1023
+= IXGBE_READ_REG(hw
, IXGBE_PRC1023
);
5896 hwstats
->prc1522
+= IXGBE_READ_REG(hw
, IXGBE_PRC1522
);
5897 hwstats
->rlec
+= IXGBE_READ_REG(hw
, IXGBE_RLEC
);
5898 lxon
= IXGBE_READ_REG(hw
, IXGBE_LXONTXC
);
5899 hwstats
->lxontxc
+= lxon
;
5900 lxoff
= IXGBE_READ_REG(hw
, IXGBE_LXOFFTXC
);
5901 hwstats
->lxofftxc
+= lxoff
;
5902 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5903 hwstats
->gptc
+= IXGBE_READ_REG(hw
, IXGBE_GPTC
);
5904 hwstats
->mptc
+= IXGBE_READ_REG(hw
, IXGBE_MPTC
);
5906 * 82598 errata - tx of flow control packets is included in tx counters
5908 xon_off_tot
= lxon
+ lxoff
;
5909 hwstats
->gptc
-= xon_off_tot
;
5910 hwstats
->mptc
-= xon_off_tot
;
5911 hwstats
->gotc
-= (xon_off_tot
* (ETH_ZLEN
+ ETH_FCS_LEN
));
5912 hwstats
->ruc
+= IXGBE_READ_REG(hw
, IXGBE_RUC
);
5913 hwstats
->rfc
+= IXGBE_READ_REG(hw
, IXGBE_RFC
);
5914 hwstats
->rjc
+= IXGBE_READ_REG(hw
, IXGBE_RJC
);
5915 hwstats
->tpr
+= IXGBE_READ_REG(hw
, IXGBE_TPR
);
5916 hwstats
->ptc64
+= IXGBE_READ_REG(hw
, IXGBE_PTC64
);
5917 hwstats
->ptc64
-= xon_off_tot
;
5918 hwstats
->ptc127
+= IXGBE_READ_REG(hw
, IXGBE_PTC127
);
5919 hwstats
->ptc255
+= IXGBE_READ_REG(hw
, IXGBE_PTC255
);
5920 hwstats
->ptc511
+= IXGBE_READ_REG(hw
, IXGBE_PTC511
);
5921 hwstats
->ptc1023
+= IXGBE_READ_REG(hw
, IXGBE_PTC1023
);
5922 hwstats
->ptc1522
+= IXGBE_READ_REG(hw
, IXGBE_PTC1522
);
5923 hwstats
->bptc
+= IXGBE_READ_REG(hw
, IXGBE_BPTC
);
5925 /* Fill out the OS statistics structure */
5926 netdev
->stats
.multicast
= hwstats
->mprc
;
5929 netdev
->stats
.rx_errors
= hwstats
->crcerrs
+ hwstats
->rlec
;
5930 netdev
->stats
.rx_dropped
= 0;
5931 netdev
->stats
.rx_length_errors
= hwstats
->rlec
;
5932 netdev
->stats
.rx_crc_errors
= hwstats
->crcerrs
;
5933 netdev
->stats
.rx_missed_errors
= total_mpc
;
5937 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5938 * @adapter - pointer to the device adapter structure
5940 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter
*adapter
)
5942 struct ixgbe_hw
*hw
= &adapter
->hw
;
5945 if (!(adapter
->flags2
& IXGBE_FLAG2_FDIR_REQUIRES_REINIT
))
5948 adapter
->flags2
&= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT
;
5950 /* if interface is down do nothing */
5951 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
5954 /* do nothing if we are not using signature filters */
5955 if (!(adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
))
5958 adapter
->fdir_overflow
++;
5960 if (ixgbe_reinit_fdir_tables_82599(hw
) == 0) {
5961 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5962 set_bit(__IXGBE_TX_FDIR_INIT_DONE
,
5963 &(adapter
->tx_ring
[i
]->state
));
5964 /* re-enable flow director interrupts */
5965 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMS_FLOW_DIR
);
5967 e_err(probe
, "failed to finish FDIR re-initialization, "
5968 "ignored adding FDIR ATR filters\n");
5973 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5974 * @adapter - pointer to the device adapter structure
5976 * This function serves two purposes. First it strobes the interrupt lines
5977 * in order to make certain interrupts are occuring. Secondly it sets the
5978 * bits needed to check for TX hangs. As a result we should immediately
5979 * determine if a hang has occured.
5981 static void ixgbe_check_hang_subtask(struct ixgbe_adapter
*adapter
)
5983 struct ixgbe_hw
*hw
= &adapter
->hw
;
5987 /* If we're down or resetting, just bail */
5988 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
5989 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
5992 /* Force detection of hung controller */
5993 if (netif_carrier_ok(adapter
->netdev
)) {
5994 for (i
= 0; i
< adapter
->num_tx_queues
; i
++)
5995 set_check_for_tx_hang(adapter
->tx_ring
[i
]);
5998 if (!(adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
)) {
6000 * for legacy and MSI interrupts don't set any bits
6001 * that are enabled for EIAM, because this operation
6002 * would set *both* EIMS and EICS for any bit in EIAM
6004 IXGBE_WRITE_REG(hw
, IXGBE_EICS
,
6005 (IXGBE_EICS_TCP_TIMER
| IXGBE_EICS_OTHER
));
6007 /* get one bit for every active tx/rx interrupt vector */
6008 for (i
= 0; i
< adapter
->num_msix_vectors
- NON_Q_VECTORS
; i
++) {
6009 struct ixgbe_q_vector
*qv
= adapter
->q_vector
[i
];
6010 if (qv
->rxr_count
|| qv
->txr_count
)
6011 eics
|= ((u64
)1 << i
);
6015 /* Cause software interrupt to ensure rings are cleaned */
6016 ixgbe_irq_rearm_queues(adapter
, eics
);
6021 * ixgbe_watchdog_update_link - update the link status
6022 * @adapter - pointer to the device adapter structure
6023 * @link_speed - pointer to a u32 to store the link_speed
6025 static void ixgbe_watchdog_update_link(struct ixgbe_adapter
*adapter
)
6027 struct ixgbe_hw
*hw
= &adapter
->hw
;
6028 u32 link_speed
= adapter
->link_speed
;
6029 bool link_up
= adapter
->link_up
;
6032 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
))
6035 if (hw
->mac
.ops
.check_link
) {
6036 hw
->mac
.ops
.check_link(hw
, &link_speed
, &link_up
, false);
6038 /* always assume link is up, if no check link function */
6039 link_speed
= IXGBE_LINK_SPEED_10GB_FULL
;
6043 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6044 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++)
6045 hw
->mac
.ops
.fc_enable(hw
, i
);
6047 hw
->mac
.ops
.fc_enable(hw
, 0);
6052 time_after(jiffies
, (adapter
->link_check_timeout
+
6053 IXGBE_TRY_LINK_TIMEOUT
))) {
6054 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_UPDATE
;
6055 IXGBE_WRITE_REG(hw
, IXGBE_EIMS
, IXGBE_EIMC_LSC
);
6056 IXGBE_WRITE_FLUSH(hw
);
6059 adapter
->link_up
= link_up
;
6060 adapter
->link_speed
= link_speed
;
6064 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6065 * print link up message
6066 * @adapter - pointer to the device adapter structure
6068 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter
*adapter
)
6070 struct net_device
*netdev
= adapter
->netdev
;
6071 struct ixgbe_hw
*hw
= &adapter
->hw
;
6072 u32 link_speed
= adapter
->link_speed
;
6073 bool flow_rx
, flow_tx
;
6075 /* only continue if link was previously down */
6076 if (netif_carrier_ok(netdev
))
6079 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
6081 switch (hw
->mac
.type
) {
6082 case ixgbe_mac_82598EB
: {
6083 u32 frctl
= IXGBE_READ_REG(hw
, IXGBE_FCTRL
);
6084 u32 rmcs
= IXGBE_READ_REG(hw
, IXGBE_RMCS
);
6085 flow_rx
= !!(frctl
& IXGBE_FCTRL_RFCE
);
6086 flow_tx
= !!(rmcs
& IXGBE_RMCS_TFCE_802_3X
);
6089 case ixgbe_mac_X540
:
6090 case ixgbe_mac_82599EB
: {
6091 u32 mflcn
= IXGBE_READ_REG(hw
, IXGBE_MFLCN
);
6092 u32 fccfg
= IXGBE_READ_REG(hw
, IXGBE_FCCFG
);
6093 flow_rx
= !!(mflcn
& IXGBE_MFLCN_RFCE
);
6094 flow_tx
= !!(fccfg
& IXGBE_FCCFG_TFCE_802_3X
);
6102 e_info(drv
, "NIC Link is Up %s, Flow Control: %s\n",
6103 (link_speed
== IXGBE_LINK_SPEED_10GB_FULL
?
6105 (link_speed
== IXGBE_LINK_SPEED_1GB_FULL
?
6107 (link_speed
== IXGBE_LINK_SPEED_100_FULL
?
6110 ((flow_rx
&& flow_tx
) ? "RX/TX" :
6112 (flow_tx
? "TX" : "None"))));
6114 netif_carrier_on(netdev
);
6115 #ifdef HAVE_IPLINK_VF_CONFIG
6116 ixgbe_check_vf_rate_limit(adapter
);
6117 #endif /* HAVE_IPLINK_VF_CONFIG */
6121 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6122 * print link down message
6123 * @adapter - pointer to the adapter structure
6125 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter
* adapter
)
6127 struct net_device
*netdev
= adapter
->netdev
;
6128 struct ixgbe_hw
*hw
= &adapter
->hw
;
6130 adapter
->link_up
= false;
6131 adapter
->link_speed
= 0;
6133 /* only continue if link was up previously */
6134 if (!netif_carrier_ok(netdev
))
6137 /* poll for SFP+ cable when link is down */
6138 if (ixgbe_is_sfp(hw
) && hw
->mac
.type
== ixgbe_mac_82598EB
)
6139 adapter
->flags2
|= IXGBE_FLAG2_SEARCH_FOR_SFP
;
6141 e_info(drv
, "NIC Link is Down\n");
6142 netif_carrier_off(netdev
);
6146 * ixgbe_watchdog_flush_tx - flush queues on link down
6147 * @adapter - pointer to the device adapter structure
6149 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter
*adapter
)
6152 int some_tx_pending
= 0;
6154 if (!netif_carrier_ok(adapter
->netdev
)) {
6155 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
6156 struct ixgbe_ring
*tx_ring
= adapter
->tx_ring
[i
];
6157 if (tx_ring
->next_to_use
!= tx_ring
->next_to_clean
) {
6158 some_tx_pending
= 1;
6163 if (some_tx_pending
) {
6164 /* We've lost link, so the controller stops DMA,
6165 * but we've got queued Tx work that's never going
6166 * to get done, so reset controller to flush Tx.
6167 * (Do the reset outside of interrupt context).
6169 adapter
->flags2
|= IXGBE_FLAG2_RESET_REQUESTED
;
6174 static void ixgbe_spoof_check(struct ixgbe_adapter
*adapter
)
6178 /* Do not perform spoof check for 82598 */
6179 if (adapter
->hw
.mac
.type
== ixgbe_mac_82598EB
)
6182 ssvpc
= IXGBE_READ_REG(&adapter
->hw
, IXGBE_SSVPC
);
6185 * ssvpc register is cleared on read, if zero then no
6186 * spoofed packets in the last interval.
6191 e_warn(drv
, "%d Spoofed packets detected\n", ssvpc
);
6195 * ixgbe_watchdog_subtask - check and bring link up
6196 * @adapter - pointer to the device adapter structure
6198 static void ixgbe_watchdog_subtask(struct ixgbe_adapter
*adapter
)
6200 /* if interface is down do nothing */
6201 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
6204 ixgbe_watchdog_update_link(adapter
);
6206 if (adapter
->link_up
)
6207 ixgbe_watchdog_link_is_up(adapter
);
6209 ixgbe_watchdog_link_is_down(adapter
);
6211 ixgbe_spoof_check(adapter
);
6212 ixgbe_update_stats(adapter
);
6214 ixgbe_watchdog_flush_tx(adapter
);
6218 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6219 * @adapter - the ixgbe adapter structure
6221 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter
*adapter
)
6223 struct ixgbe_hw
*hw
= &adapter
->hw
;
6226 /* not searching for SFP so there is nothing to do here */
6227 if (!(adapter
->flags2
& IXGBE_FLAG2_SEARCH_FOR_SFP
) &&
6228 !(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6231 /* someone else is in init, wait until next service event */
6232 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6235 err
= hw
->phy
.ops
.identify_sfp(hw
);
6236 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6239 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
) {
6240 /* If no cable is present, then we need to reset
6241 * the next time we find a good cable. */
6242 adapter
->flags2
|= IXGBE_FLAG2_SFP_NEEDS_RESET
;
6249 /* exit if reset not needed */
6250 if (!(adapter
->flags2
& IXGBE_FLAG2_SFP_NEEDS_RESET
))
6253 adapter
->flags2
&= ~IXGBE_FLAG2_SFP_NEEDS_RESET
;
6256 * A module may be identified correctly, but the EEPROM may not have
6257 * support for that module. setup_sfp() will fail in that case, so
6258 * we should not allow that module to load.
6260 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
6261 err
= hw
->phy
.ops
.reset(hw
);
6263 err
= hw
->mac
.ops
.setup_sfp(hw
);
6265 if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
)
6268 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_CONFIG
;
6269 e_info(probe
, "detected SFP+: %d\n", hw
->phy
.sfp_type
);
6272 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6274 if ((err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) &&
6275 (adapter
->netdev
->reg_state
== NETREG_REGISTERED
)) {
6276 e_dev_err("failed to initialize because an unsupported "
6277 "SFP+ module type was detected.\n");
6278 e_dev_err("Reload the driver after installing a "
6279 "supported module.\n");
6280 unregister_netdev(adapter
->netdev
);
6285 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6286 * @adapter - the ixgbe adapter structure
6288 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter
*adapter
)
6290 struct ixgbe_hw
*hw
= &adapter
->hw
;
6294 if (!(adapter
->flags
& IXGBE_FLAG_NEED_LINK_CONFIG
))
6297 /* someone else is in init, wait until next service event */
6298 if (test_and_set_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
))
6301 adapter
->flags
&= ~IXGBE_FLAG_NEED_LINK_CONFIG
;
6303 autoneg
= hw
->phy
.autoneg_advertised
;
6304 if ((!autoneg
) && (hw
->mac
.ops
.get_link_capabilities
))
6305 hw
->mac
.ops
.get_link_capabilities(hw
, &autoneg
, &negotiation
);
6306 hw
->mac
.autotry_restart
= false;
6307 if (hw
->mac
.ops
.setup_link
)
6308 hw
->mac
.ops
.setup_link(hw
, autoneg
, negotiation
, true);
6310 adapter
->flags
|= IXGBE_FLAG_NEED_LINK_UPDATE
;
6311 adapter
->link_check_timeout
= jiffies
;
6312 clear_bit(__IXGBE_IN_SFP_INIT
, &adapter
->state
);
6316 * ixgbe_service_timer - Timer Call-back
6317 * @data: pointer to adapter cast into an unsigned long
6319 static void ixgbe_service_timer(unsigned long data
)
6321 struct ixgbe_adapter
*adapter
= (struct ixgbe_adapter
*)data
;
6322 unsigned long next_event_offset
;
6324 /* poll faster when waiting for link */
6325 if (adapter
->flags
& IXGBE_FLAG_NEED_LINK_UPDATE
)
6326 next_event_offset
= HZ
/ 10;
6328 next_event_offset
= HZ
* 2;
6330 /* Reset the timer */
6331 mod_timer(&adapter
->service_timer
, next_event_offset
+ jiffies
);
6333 ixgbe_service_event_schedule(adapter
);
6336 static void ixgbe_reset_subtask(struct ixgbe_adapter
*adapter
)
6338 if (!(adapter
->flags2
& IXGBE_FLAG2_RESET_REQUESTED
))
6341 adapter
->flags2
&= ~IXGBE_FLAG2_RESET_REQUESTED
;
6343 /* If we're already down or resetting, just bail */
6344 if (test_bit(__IXGBE_DOWN
, &adapter
->state
) ||
6345 test_bit(__IXGBE_RESETTING
, &adapter
->state
))
6348 ixgbe_dump(adapter
);
6349 netdev_err(adapter
->netdev
, "Reset adapter\n");
6350 adapter
->tx_timeout_count
++;
6352 ixgbe_reinit_locked(adapter
);
6356 * ixgbe_service_task - manages and runs subtasks
6357 * @work: pointer to work_struct containing our data
6359 static void ixgbe_service_task(struct work_struct
*work
)
6361 struct ixgbe_adapter
*adapter
= container_of(work
,
6362 struct ixgbe_adapter
,
6365 ixgbe_reset_subtask(adapter
);
6366 ixgbe_sfp_detection_subtask(adapter
);
6367 ixgbe_sfp_link_config_subtask(adapter
);
6368 ixgbe_check_overtemp_subtask(adapter
);
6369 ixgbe_watchdog_subtask(adapter
);
6370 ixgbe_fdir_reinit_subtask(adapter
);
6371 ixgbe_check_hang_subtask(adapter
);
6373 ixgbe_service_event_complete(adapter
);
6376 static int ixgbe_tso(struct ixgbe_adapter
*adapter
,
6377 struct ixgbe_ring
*tx_ring
, struct sk_buff
*skb
,
6378 u32 tx_flags
, u8
*hdr_len
, __be16 protocol
)
6380 struct ixgbe_adv_tx_context_desc
*context_desc
;
6383 struct ixgbe_tx_buffer
*tx_buffer_info
;
6384 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
;
6385 u32 mss_l4len_idx
, l4len
;
6387 if (skb_is_gso(skb
)) {
6388 if (skb_header_cloned(skb
)) {
6389 err
= pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
);
6393 l4len
= tcp_hdrlen(skb
);
6396 if (protocol
== htons(ETH_P_IP
)) {
6397 struct iphdr
*iph
= ip_hdr(skb
);
6400 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
6404 } else if (skb_is_gso_v6(skb
)) {
6405 ipv6_hdr(skb
)->payload_len
= 0;
6406 tcp_hdr(skb
)->check
=
6407 ~csum_ipv6_magic(&ipv6_hdr(skb
)->saddr
,
6408 &ipv6_hdr(skb
)->daddr
,
6412 i
= tx_ring
->next_to_use
;
6414 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6415 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6417 /* VLAN MACLEN IPLEN */
6418 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6420 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6421 vlan_macip_lens
|= ((skb_network_offset(skb
)) <<
6422 IXGBE_ADVTXD_MACLEN_SHIFT
);
6423 *hdr_len
+= skb_network_offset(skb
);
6425 (skb_transport_header(skb
) - skb_network_header(skb
));
6427 (skb_transport_header(skb
) - skb_network_header(skb
));
6428 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6429 context_desc
->seqnum_seed
= 0;
6431 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6432 type_tucmd_mlhl
= (IXGBE_TXD_CMD_DEXT
|
6433 IXGBE_ADVTXD_DTYP_CTXT
);
6435 if (protocol
== htons(ETH_P_IP
))
6436 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6437 type_tucmd_mlhl
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6438 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6442 (skb_shinfo(skb
)->gso_size
<< IXGBE_ADVTXD_MSS_SHIFT
);
6443 mss_l4len_idx
|= (l4len
<< IXGBE_ADVTXD_L4LEN_SHIFT
);
6444 /* use index 1 for TSO */
6445 mss_l4len_idx
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6446 context_desc
->mss_l4len_idx
= cpu_to_le32(mss_l4len_idx
);
6448 tx_buffer_info
->time_stamp
= jiffies
;
6449 tx_buffer_info
->next_to_watch
= i
;
6452 if (i
== tx_ring
->count
)
6454 tx_ring
->next_to_use
= i
;
6461 static u32
ixgbe_psum(struct ixgbe_adapter
*adapter
, struct sk_buff
*skb
,
6467 case cpu_to_be16(ETH_P_IP
):
6468 rtn
|= IXGBE_ADVTXD_TUCMD_IPV4
;
6469 switch (ip_hdr(skb
)->protocol
) {
6471 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6474 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6478 case cpu_to_be16(ETH_P_IPV6
):
6479 /* XXX what about other V6 headers?? */
6480 switch (ipv6_hdr(skb
)->nexthdr
) {
6482 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_TCP
;
6485 rtn
|= IXGBE_ADVTXD_TUCMD_L4T_SCTP
;
6490 if (unlikely(net_ratelimit()))
6491 e_warn(probe
, "partial checksum but proto=%x!\n",
6499 static bool ixgbe_tx_csum(struct ixgbe_adapter
*adapter
,
6500 struct ixgbe_ring
*tx_ring
,
6501 struct sk_buff
*skb
, u32 tx_flags
,
6504 struct ixgbe_adv_tx_context_desc
*context_desc
;
6506 struct ixgbe_tx_buffer
*tx_buffer_info
;
6507 u32 vlan_macip_lens
= 0, type_tucmd_mlhl
= 0;
6509 if (skb
->ip_summed
== CHECKSUM_PARTIAL
||
6510 (tx_flags
& IXGBE_TX_FLAGS_VLAN
)) {
6511 i
= tx_ring
->next_to_use
;
6512 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6513 context_desc
= IXGBE_TX_CTXTDESC_ADV(tx_ring
, i
);
6515 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6517 (tx_flags
& IXGBE_TX_FLAGS_VLAN_MASK
);
6518 vlan_macip_lens
|= (skb_network_offset(skb
) <<
6519 IXGBE_ADVTXD_MACLEN_SHIFT
);
6520 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6521 vlan_macip_lens
|= (skb_transport_header(skb
) -
6522 skb_network_header(skb
));
6524 context_desc
->vlan_macip_lens
= cpu_to_le32(vlan_macip_lens
);
6525 context_desc
->seqnum_seed
= 0;
6527 type_tucmd_mlhl
|= (IXGBE_TXD_CMD_DEXT
|
6528 IXGBE_ADVTXD_DTYP_CTXT
);
6530 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
6531 type_tucmd_mlhl
|= ixgbe_psum(adapter
, skb
, protocol
);
6533 context_desc
->type_tucmd_mlhl
= cpu_to_le32(type_tucmd_mlhl
);
6534 /* use index zero for tx checksum offload */
6535 context_desc
->mss_l4len_idx
= 0;
6537 tx_buffer_info
->time_stamp
= jiffies
;
6538 tx_buffer_info
->next_to_watch
= i
;
6541 if (i
== tx_ring
->count
)
6543 tx_ring
->next_to_use
= i
;
6551 static int ixgbe_tx_map(struct ixgbe_adapter
*adapter
,
6552 struct ixgbe_ring
*tx_ring
,
6553 struct sk_buff
*skb
, u32 tx_flags
,
6554 unsigned int first
, const u8 hdr_len
)
6556 struct device
*dev
= tx_ring
->dev
;
6557 struct ixgbe_tx_buffer
*tx_buffer_info
;
6559 unsigned int total
= skb
->len
;
6560 unsigned int offset
= 0, size
, count
= 0, i
;
6561 unsigned int nr_frags
= skb_shinfo(skb
)->nr_frags
;
6563 unsigned int bytecount
= skb
->len
;
6566 i
= tx_ring
->next_to_use
;
6568 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
)
6569 /* excluding fcoe_crc_eof for FCoE */
6570 total
-= sizeof(struct fcoe_crc_eof
);
6572 len
= min(skb_headlen(skb
), total
);
6574 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6575 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6577 tx_buffer_info
->length
= size
;
6578 tx_buffer_info
->mapped_as_page
= false;
6579 tx_buffer_info
->dma
= dma_map_single(dev
,
6581 size
, DMA_TO_DEVICE
);
6582 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6584 tx_buffer_info
->time_stamp
= jiffies
;
6585 tx_buffer_info
->next_to_watch
= i
;
6594 if (i
== tx_ring
->count
)
6599 for (f
= 0; f
< nr_frags
; f
++) {
6600 struct skb_frag_struct
*frag
;
6602 frag
= &skb_shinfo(skb
)->frags
[f
];
6603 len
= min((unsigned int)frag
->size
, total
);
6604 offset
= frag
->page_offset
;
6608 if (i
== tx_ring
->count
)
6611 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6612 size
= min(len
, (uint
)IXGBE_MAX_DATA_PER_TXD
);
6614 tx_buffer_info
->length
= size
;
6615 tx_buffer_info
->dma
= dma_map_page(dev
,
6619 tx_buffer_info
->mapped_as_page
= true;
6620 if (dma_mapping_error(dev
, tx_buffer_info
->dma
))
6622 tx_buffer_info
->time_stamp
= jiffies
;
6623 tx_buffer_info
->next_to_watch
= i
;
6634 if (tx_flags
& IXGBE_TX_FLAGS_TSO
)
6635 gso_segs
= skb_shinfo(skb
)->gso_segs
;
6637 /* adjust for FCoE Sequence Offload */
6638 else if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6639 gso_segs
= DIV_ROUND_UP(skb
->len
- hdr_len
,
6640 skb_shinfo(skb
)->gso_size
);
6641 #endif /* IXGBE_FCOE */
6642 bytecount
+= (gso_segs
- 1) * hdr_len
;
6644 /* multiply data chunks by size of headers */
6645 tx_ring
->tx_buffer_info
[i
].bytecount
= bytecount
;
6646 tx_ring
->tx_buffer_info
[i
].gso_segs
= gso_segs
;
6647 tx_ring
->tx_buffer_info
[i
].skb
= skb
;
6648 tx_ring
->tx_buffer_info
[first
].next_to_watch
= i
;
6653 e_dev_err("TX DMA map failed\n");
6655 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6656 tx_buffer_info
->dma
= 0;
6657 tx_buffer_info
->time_stamp
= 0;
6658 tx_buffer_info
->next_to_watch
= 0;
6662 /* clear timestamp and dma mappings for remaining portion of packet */
6665 i
+= tx_ring
->count
;
6667 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6668 ixgbe_unmap_and_free_tx_resource(tx_ring
, tx_buffer_info
);
6674 static void ixgbe_tx_queue(struct ixgbe_ring
*tx_ring
,
6675 int tx_flags
, int count
, u32 paylen
, u8 hdr_len
)
6677 union ixgbe_adv_tx_desc
*tx_desc
= NULL
;
6678 struct ixgbe_tx_buffer
*tx_buffer_info
;
6679 u32 olinfo_status
= 0, cmd_type_len
= 0;
6681 u32 txd_cmd
= IXGBE_TXD_CMD_EOP
| IXGBE_TXD_CMD_RS
| IXGBE_TXD_CMD_IFCS
;
6683 cmd_type_len
|= IXGBE_ADVTXD_DTYP_DATA
;
6685 cmd_type_len
|= IXGBE_ADVTXD_DCMD_IFCS
| IXGBE_ADVTXD_DCMD_DEXT
;
6687 if (tx_flags
& IXGBE_TX_FLAGS_VLAN
)
6688 cmd_type_len
|= IXGBE_ADVTXD_DCMD_VLE
;
6690 if (tx_flags
& IXGBE_TX_FLAGS_TSO
) {
6691 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6693 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6694 IXGBE_ADVTXD_POPTS_SHIFT
;
6696 /* use index 1 context for tso */
6697 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6698 if (tx_flags
& IXGBE_TX_FLAGS_IPV4
)
6699 olinfo_status
|= IXGBE_TXD_POPTS_IXSM
<<
6700 IXGBE_ADVTXD_POPTS_SHIFT
;
6702 } else if (tx_flags
& IXGBE_TX_FLAGS_CSUM
)
6703 olinfo_status
|= IXGBE_TXD_POPTS_TXSM
<<
6704 IXGBE_ADVTXD_POPTS_SHIFT
;
6706 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6707 olinfo_status
|= IXGBE_ADVTXD_CC
;
6708 olinfo_status
|= (1 << IXGBE_ADVTXD_IDX_SHIFT
);
6709 if (tx_flags
& IXGBE_TX_FLAGS_FSO
)
6710 cmd_type_len
|= IXGBE_ADVTXD_DCMD_TSE
;
6713 olinfo_status
|= ((paylen
- hdr_len
) << IXGBE_ADVTXD_PAYLEN_SHIFT
);
6715 i
= tx_ring
->next_to_use
;
6717 tx_buffer_info
= &tx_ring
->tx_buffer_info
[i
];
6718 tx_desc
= IXGBE_TX_DESC_ADV(tx_ring
, i
);
6719 tx_desc
->read
.buffer_addr
= cpu_to_le64(tx_buffer_info
->dma
);
6720 tx_desc
->read
.cmd_type_len
=
6721 cpu_to_le32(cmd_type_len
| tx_buffer_info
->length
);
6722 tx_desc
->read
.olinfo_status
= cpu_to_le32(olinfo_status
);
6724 if (i
== tx_ring
->count
)
6728 tx_desc
->read
.cmd_type_len
|= cpu_to_le32(txd_cmd
);
6731 * Force memory writes to complete before letting h/w
6732 * know there are new descriptors to fetch. (Only
6733 * applicable for weak-ordered memory model archs,
6738 tx_ring
->next_to_use
= i
;
6739 writel(i
, tx_ring
->tail
);
6742 static void ixgbe_atr(struct ixgbe_ring
*ring
, struct sk_buff
*skb
,
6743 u32 tx_flags
, __be16 protocol
)
6745 struct ixgbe_q_vector
*q_vector
= ring
->q_vector
;
6746 union ixgbe_atr_hash_dword input
= { .dword
= 0 };
6747 union ixgbe_atr_hash_dword common
= { .dword
= 0 };
6749 unsigned char *network
;
6751 struct ipv6hdr
*ipv6
;
6756 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6760 /* do nothing if sampling is disabled */
6761 if (!ring
->atr_sample_rate
)
6766 /* snag network header to get L4 type and address */
6767 hdr
.network
= skb_network_header(skb
);
6769 /* Currently only IPv4/IPv6 with TCP is supported */
6770 if ((protocol
!= __constant_htons(ETH_P_IPV6
) ||
6771 hdr
.ipv6
->nexthdr
!= IPPROTO_TCP
) &&
6772 (protocol
!= __constant_htons(ETH_P_IP
) ||
6773 hdr
.ipv4
->protocol
!= IPPROTO_TCP
))
6778 /* skip this packet since the socket is closing */
6782 /* sample on all syn packets or once every atr sample count */
6783 if (!th
->syn
&& (ring
->atr_count
< ring
->atr_sample_rate
))
6786 /* reset sample count */
6787 ring
->atr_count
= 0;
6789 vlan_id
= htons(tx_flags
>> IXGBE_TX_FLAGS_VLAN_SHIFT
);
6792 * src and dst are inverted, think how the receiver sees them
6794 * The input is broken into two sections, a non-compressed section
6795 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6796 * is XORed together and stored in the compressed dword.
6798 input
.formatted
.vlan_id
= vlan_id
;
6801 * since src port and flex bytes occupy the same word XOR them together
6802 * and write the value to source port portion of compressed dword
6805 common
.port
.src
^= th
->dest
^ __constant_htons(ETH_P_8021Q
);
6807 common
.port
.src
^= th
->dest
^ protocol
;
6808 common
.port
.dst
^= th
->source
;
6810 if (protocol
== __constant_htons(ETH_P_IP
)) {
6811 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV4
;
6812 common
.ip
^= hdr
.ipv4
->saddr
^ hdr
.ipv4
->daddr
;
6814 input
.formatted
.flow_type
= IXGBE_ATR_FLOW_TYPE_TCPV6
;
6815 common
.ip
^= hdr
.ipv6
->saddr
.s6_addr32
[0] ^
6816 hdr
.ipv6
->saddr
.s6_addr32
[1] ^
6817 hdr
.ipv6
->saddr
.s6_addr32
[2] ^
6818 hdr
.ipv6
->saddr
.s6_addr32
[3] ^
6819 hdr
.ipv6
->daddr
.s6_addr32
[0] ^
6820 hdr
.ipv6
->daddr
.s6_addr32
[1] ^
6821 hdr
.ipv6
->daddr
.s6_addr32
[2] ^
6822 hdr
.ipv6
->daddr
.s6_addr32
[3];
6825 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6826 ixgbe_fdir_add_signature_filter_82599(&q_vector
->adapter
->hw
,
6827 input
, common
, ring
->queue_index
);
6830 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6832 netif_stop_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6833 /* Herbert's original patch had:
6834 * smp_mb__after_netif_stop_queue();
6835 * but since that doesn't exist yet, just open code it. */
6838 /* We need to check again in a case another CPU has just
6839 * made room available. */
6840 if (likely(IXGBE_DESC_UNUSED(tx_ring
) < size
))
6843 /* A reprieve! - use start_queue because it doesn't call schedule */
6844 netif_start_subqueue(tx_ring
->netdev
, tx_ring
->queue_index
);
6845 ++tx_ring
->tx_stats
.restart_queue
;
6849 static int ixgbe_maybe_stop_tx(struct ixgbe_ring
*tx_ring
, int size
)
6851 if (likely(IXGBE_DESC_UNUSED(tx_ring
) >= size
))
6853 return __ixgbe_maybe_stop_tx(tx_ring
, size
);
6856 static u16
ixgbe_select_queue(struct net_device
*dev
, struct sk_buff
*skb
)
6858 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
6859 int txq
= smp_processor_id();
6863 protocol
= vlan_get_protocol(skb
);
6865 if (((protocol
== htons(ETH_P_FCOE
)) ||
6866 (protocol
== htons(ETH_P_FIP
))) &&
6867 (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)) {
6868 txq
&= (adapter
->ring_feature
[RING_F_FCOE
].indices
- 1);
6869 txq
+= adapter
->ring_feature
[RING_F_FCOE
].mask
;
6874 if (adapter
->flags
& IXGBE_FLAG_FDIR_HASH_CAPABLE
) {
6875 while (unlikely(txq
>= dev
->real_num_tx_queues
))
6876 txq
-= dev
->real_num_tx_queues
;
6880 return skb_tx_hash(dev
, skb
);
6883 netdev_tx_t
ixgbe_xmit_frame_ring(struct sk_buff
*skb
,
6884 struct ixgbe_adapter
*adapter
,
6885 struct ixgbe_ring
*tx_ring
)
6888 unsigned int tx_flags
= 0;
6895 protocol
= vlan_get_protocol(skb
);
6897 if (vlan_tx_tag_present(skb
)) {
6898 tx_flags
|= vlan_tx_tag_get(skb
);
6899 if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
) {
6900 tx_flags
&= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK
;
6901 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6903 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6904 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6905 } else if (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
&&
6906 skb
->priority
!= TC_PRIO_CONTROL
) {
6907 tx_flags
|= tx_ring
->dcb_tc
<< 13;
6908 tx_flags
<<= IXGBE_TX_FLAGS_VLAN_SHIFT
;
6909 tx_flags
|= IXGBE_TX_FLAGS_VLAN
;
6913 /* for FCoE with DCB, we force the priority to what
6914 * was specified by the switch */
6915 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
&&
6916 (protocol
== htons(ETH_P_FCOE
)))
6917 tx_flags
|= IXGBE_TX_FLAGS_FCOE
;
6920 /* four things can cause us to need a context descriptor */
6921 if (skb_is_gso(skb
) ||
6922 (skb
->ip_summed
== CHECKSUM_PARTIAL
) ||
6923 (tx_flags
& IXGBE_TX_FLAGS_VLAN
) ||
6924 (tx_flags
& IXGBE_TX_FLAGS_FCOE
))
6927 count
+= TXD_USE_COUNT(skb_headlen(skb
));
6928 for (f
= 0; f
< skb_shinfo(skb
)->nr_frags
; f
++)
6929 count
+= TXD_USE_COUNT(skb_shinfo(skb
)->frags
[f
].size
);
6931 if (ixgbe_maybe_stop_tx(tx_ring
, count
)) {
6932 tx_ring
->tx_stats
.tx_busy
++;
6933 return NETDEV_TX_BUSY
;
6936 first
= tx_ring
->next_to_use
;
6937 if (tx_flags
& IXGBE_TX_FLAGS_FCOE
) {
6939 /* setup tx offload for FCoE */
6940 tso
= ixgbe_fso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
);
6942 dev_kfree_skb_any(skb
);
6943 return NETDEV_TX_OK
;
6946 tx_flags
|= IXGBE_TX_FLAGS_FSO
;
6947 #endif /* IXGBE_FCOE */
6949 if (protocol
== htons(ETH_P_IP
))
6950 tx_flags
|= IXGBE_TX_FLAGS_IPV4
;
6951 tso
= ixgbe_tso(adapter
, tx_ring
, skb
, tx_flags
, &hdr_len
,
6954 dev_kfree_skb_any(skb
);
6955 return NETDEV_TX_OK
;
6959 tx_flags
|= IXGBE_TX_FLAGS_TSO
;
6960 else if (ixgbe_tx_csum(adapter
, tx_ring
, skb
, tx_flags
,
6962 (skb
->ip_summed
== CHECKSUM_PARTIAL
))
6963 tx_flags
|= IXGBE_TX_FLAGS_CSUM
;
6966 count
= ixgbe_tx_map(adapter
, tx_ring
, skb
, tx_flags
, first
, hdr_len
);
6968 /* add the ATR filter if ATR is on */
6969 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE
, &tx_ring
->state
))
6970 ixgbe_atr(tx_ring
, skb
, tx_flags
, protocol
);
6971 ixgbe_tx_queue(tx_ring
, tx_flags
, count
, skb
->len
, hdr_len
);
6972 ixgbe_maybe_stop_tx(tx_ring
, DESC_NEEDED
);
6975 dev_kfree_skb_any(skb
);
6976 tx_ring
->tx_buffer_info
[first
].time_stamp
= 0;
6977 tx_ring
->next_to_use
= first
;
6980 return NETDEV_TX_OK
;
6983 static netdev_tx_t
ixgbe_xmit_frame(struct sk_buff
*skb
, struct net_device
*netdev
)
6985 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
6986 struct ixgbe_ring
*tx_ring
;
6988 tx_ring
= adapter
->tx_ring
[skb
->queue_mapping
];
6989 return ixgbe_xmit_frame_ring(skb
, adapter
, tx_ring
);
6993 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6994 * @netdev: network interface device structure
6995 * @p: pointer to an address structure
6997 * Returns 0 on success, negative on failure
6999 static int ixgbe_set_mac(struct net_device
*netdev
, void *p
)
7001 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7002 struct ixgbe_hw
*hw
= &adapter
->hw
;
7003 struct sockaddr
*addr
= p
;
7005 if (!is_valid_ether_addr(addr
->sa_data
))
7006 return -EADDRNOTAVAIL
;
7008 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
7009 memcpy(hw
->mac
.addr
, addr
->sa_data
, netdev
->addr_len
);
7011 hw
->mac
.ops
.set_rar(hw
, 0, hw
->mac
.addr
, adapter
->num_vfs
,
7018 ixgbe_mdio_read(struct net_device
*netdev
, int prtad
, int devad
, u16 addr
)
7020 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7021 struct ixgbe_hw
*hw
= &adapter
->hw
;
7025 if (prtad
!= hw
->phy
.mdio
.prtad
)
7027 rc
= hw
->phy
.ops
.read_reg(hw
, addr
, devad
, &value
);
7033 static int ixgbe_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
7034 u16 addr
, u16 value
)
7036 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7037 struct ixgbe_hw
*hw
= &adapter
->hw
;
7039 if (prtad
!= hw
->phy
.mdio
.prtad
)
7041 return hw
->phy
.ops
.write_reg(hw
, addr
, devad
, value
);
7044 static int ixgbe_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
7046 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7048 return mdio_mii_ioctl(&adapter
->hw
.phy
.mdio
, if_mii(req
), cmd
);
7052 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
7054 * @netdev: network interface device structure
7056 * Returns non-zero on failure
7058 static int ixgbe_add_sanmac_netdev(struct net_device
*dev
)
7061 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7062 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
7064 if (is_valid_ether_addr(mac
->san_addr
)) {
7066 err
= dev_addr_add(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
7073 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7075 * @netdev: network interface device structure
7077 * Returns non-zero on failure
7079 static int ixgbe_del_sanmac_netdev(struct net_device
*dev
)
7082 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7083 struct ixgbe_mac_info
*mac
= &adapter
->hw
.mac
;
7085 if (is_valid_ether_addr(mac
->san_addr
)) {
7087 err
= dev_addr_del(dev
, mac
->san_addr
, NETDEV_HW_ADDR_T_SAN
);
7093 #ifdef CONFIG_NET_POLL_CONTROLLER
7095 * Polling 'interrupt' - used by things like netconsole to send skbs
7096 * without having to re-enable interrupts. It's not called while
7097 * the interrupt routine is executing.
7099 static void ixgbe_netpoll(struct net_device
*netdev
)
7101 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7104 /* if interface is down do nothing */
7105 if (test_bit(__IXGBE_DOWN
, &adapter
->state
))
7108 adapter
->flags
|= IXGBE_FLAG_IN_NETPOLL
;
7109 if (adapter
->flags
& IXGBE_FLAG_MSIX_ENABLED
) {
7110 int num_q_vectors
= adapter
->num_msix_vectors
- NON_Q_VECTORS
;
7111 for (i
= 0; i
< num_q_vectors
; i
++) {
7112 struct ixgbe_q_vector
*q_vector
= adapter
->q_vector
[i
];
7113 ixgbe_msix_clean_many(0, q_vector
);
7116 ixgbe_intr(adapter
->pdev
->irq
, netdev
);
7118 adapter
->flags
&= ~IXGBE_FLAG_IN_NETPOLL
;
7122 static struct rtnl_link_stats64
*ixgbe_get_stats64(struct net_device
*netdev
,
7123 struct rtnl_link_stats64
*stats
)
7125 struct ixgbe_adapter
*adapter
= netdev_priv(netdev
);
7129 for (i
= 0; i
< adapter
->num_rx_queues
; i
++) {
7130 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->rx_ring
[i
]);
7136 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7137 packets
= ring
->stats
.packets
;
7138 bytes
= ring
->stats
.bytes
;
7139 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7140 stats
->rx_packets
+= packets
;
7141 stats
->rx_bytes
+= bytes
;
7145 for (i
= 0; i
< adapter
->num_tx_queues
; i
++) {
7146 struct ixgbe_ring
*ring
= ACCESS_ONCE(adapter
->tx_ring
[i
]);
7152 start
= u64_stats_fetch_begin_bh(&ring
->syncp
);
7153 packets
= ring
->stats
.packets
;
7154 bytes
= ring
->stats
.bytes
;
7155 } while (u64_stats_fetch_retry_bh(&ring
->syncp
, start
));
7156 stats
->tx_packets
+= packets
;
7157 stats
->tx_bytes
+= bytes
;
7161 /* following stats updated by ixgbe_watchdog_task() */
7162 stats
->multicast
= netdev
->stats
.multicast
;
7163 stats
->rx_errors
= netdev
->stats
.rx_errors
;
7164 stats
->rx_length_errors
= netdev
->stats
.rx_length_errors
;
7165 stats
->rx_crc_errors
= netdev
->stats
.rx_crc_errors
;
7166 stats
->rx_missed_errors
= netdev
->stats
.rx_missed_errors
;
7170 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7171 * #adapter: pointer to ixgbe_adapter
7172 * @tc: number of traffic classes currently enabled
7174 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7175 * 802.1Q priority maps to a packet buffer that exists.
7177 static void ixgbe_validate_rtr(struct ixgbe_adapter
*adapter
, u8 tc
)
7179 struct ixgbe_hw
*hw
= &adapter
->hw
;
7183 /* 82598 have a static priority to TC mapping that can not
7184 * be changed so no validation is needed.
7186 if (hw
->mac
.type
== ixgbe_mac_82598EB
)
7189 reg
= IXGBE_READ_REG(hw
, IXGBE_RTRUP2TC
);
7192 for (i
= 0; i
< MAX_TRAFFIC_CLASS
; i
++) {
7193 u8 up2tc
= reg
>> (i
* IXGBE_RTRUP2TC_UP_SHIFT
);
7195 /* If up2tc is out of bounds default to zero */
7197 reg
&= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT
);
7201 IXGBE_WRITE_REG(hw
, IXGBE_RTRUP2TC
, reg
);
7207 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7210 * @netdev: net device to configure
7211 * @tc: number of traffic classes to enable
7213 int ixgbe_setup_tc(struct net_device
*dev
, u8 tc
)
7215 struct ixgbe_adapter
*adapter
= netdev_priv(dev
);
7216 struct ixgbe_hw
*hw
= &adapter
->hw
;
7218 /* If DCB is anabled do not remove traffic classes, multiple
7219 * traffic classes are required to implement DCB
7221 if (!tc
&& (adapter
->flags
& IXGBE_FLAG_DCB_ENABLED
))
7224 /* Hardware supports up to 8 traffic classes */
7225 if (tc
> MAX_TRAFFIC_CLASS
||
7226 (hw
->mac
.type
== ixgbe_mac_82598EB
&& tc
< MAX_TRAFFIC_CLASS
))
7229 /* Hardware has to reinitialize queues and interrupts to
7230 * match packet buffer alignment. Unfortunantly, the
7231 * hardware is not flexible enough to do this dynamically.
7233 if (netif_running(dev
))
7235 ixgbe_clear_interrupt_scheme(adapter
);
7238 netdev_set_num_tc(dev
, tc
);
7240 netdev_reset_tc(dev
);
7242 ixgbe_init_interrupt_scheme(adapter
);
7243 ixgbe_validate_rtr(adapter
, tc
);
7244 if (netif_running(dev
))
7250 static const struct net_device_ops ixgbe_netdev_ops
= {
7251 .ndo_open
= ixgbe_open
,
7252 .ndo_stop
= ixgbe_close
,
7253 .ndo_start_xmit
= ixgbe_xmit_frame
,
7254 .ndo_select_queue
= ixgbe_select_queue
,
7255 .ndo_set_rx_mode
= ixgbe_set_rx_mode
,
7256 .ndo_set_multicast_list
= ixgbe_set_rx_mode
,
7257 .ndo_validate_addr
= eth_validate_addr
,
7258 .ndo_set_mac_address
= ixgbe_set_mac
,
7259 .ndo_change_mtu
= ixgbe_change_mtu
,
7260 .ndo_tx_timeout
= ixgbe_tx_timeout
,
7261 .ndo_vlan_rx_add_vid
= ixgbe_vlan_rx_add_vid
,
7262 .ndo_vlan_rx_kill_vid
= ixgbe_vlan_rx_kill_vid
,
7263 .ndo_do_ioctl
= ixgbe_ioctl
,
7264 .ndo_set_vf_mac
= ixgbe_ndo_set_vf_mac
,
7265 .ndo_set_vf_vlan
= ixgbe_ndo_set_vf_vlan
,
7266 .ndo_set_vf_tx_rate
= ixgbe_ndo_set_vf_bw
,
7267 .ndo_get_vf_config
= ixgbe_ndo_get_vf_config
,
7268 .ndo_get_stats64
= ixgbe_get_stats64
,
7269 .ndo_setup_tc
= ixgbe_setup_tc
,
7270 #ifdef CONFIG_NET_POLL_CONTROLLER
7271 .ndo_poll_controller
= ixgbe_netpoll
,
7274 .ndo_fcoe_ddp_setup
= ixgbe_fcoe_ddp_get
,
7275 .ndo_fcoe_ddp_target
= ixgbe_fcoe_ddp_target
,
7276 .ndo_fcoe_ddp_done
= ixgbe_fcoe_ddp_put
,
7277 .ndo_fcoe_enable
= ixgbe_fcoe_enable
,
7278 .ndo_fcoe_disable
= ixgbe_fcoe_disable
,
7279 .ndo_fcoe_get_wwn
= ixgbe_fcoe_get_wwn
,
7280 #endif /* IXGBE_FCOE */
7283 static void __devinit
ixgbe_probe_vf(struct ixgbe_adapter
*adapter
,
7284 const struct ixgbe_info
*ii
)
7286 #ifdef CONFIG_PCI_IOV
7287 struct ixgbe_hw
*hw
= &adapter
->hw
;
7289 int num_vf_macvlans
, i
;
7290 struct vf_macvlans
*mv_list
;
7292 if (hw
->mac
.type
== ixgbe_mac_82598EB
|| !max_vfs
)
7295 /* The 82599 supports up to 64 VFs per physical function
7296 * but this implementation limits allocation to 63 so that
7297 * basic networking resources are still available to the
7300 adapter
->num_vfs
= (max_vfs
> 63) ? 63 : max_vfs
;
7301 adapter
->flags
|= IXGBE_FLAG_SRIOV_ENABLED
;
7302 err
= pci_enable_sriov(adapter
->pdev
, adapter
->num_vfs
);
7304 e_err(probe
, "Failed to enable PCI sriov: %d\n", err
);
7308 num_vf_macvlans
= hw
->mac
.num_rar_entries
-
7309 (IXGBE_MAX_PF_MACVLANS
+ 1 + adapter
->num_vfs
);
7311 adapter
->mv_list
= mv_list
= kcalloc(num_vf_macvlans
,
7312 sizeof(struct vf_macvlans
),
7315 /* Initialize list of VF macvlans */
7316 INIT_LIST_HEAD(&adapter
->vf_mvs
.l
);
7317 for (i
= 0; i
< num_vf_macvlans
; i
++) {
7319 mv_list
->free
= true;
7320 mv_list
->rar_entry
= hw
->mac
.num_rar_entries
-
7321 (i
+ adapter
->num_vfs
+ 1);
7322 list_add(&mv_list
->l
, &adapter
->vf_mvs
.l
);
7327 /* If call to enable VFs succeeded then allocate memory
7328 * for per VF control structures.
7331 kcalloc(adapter
->num_vfs
,
7332 sizeof(struct vf_data_storage
), GFP_KERNEL
);
7333 if (adapter
->vfinfo
) {
7334 /* Now that we're sure SR-IOV is enabled
7335 * and memory allocated set up the mailbox parameters
7337 ixgbe_init_mbx_params_pf(hw
);
7338 memcpy(&hw
->mbx
.ops
, ii
->mbx_ops
,
7339 sizeof(hw
->mbx
.ops
));
7341 /* Disable RSC when in SR-IOV mode */
7342 adapter
->flags2
&= ~(IXGBE_FLAG2_RSC_CAPABLE
|
7343 IXGBE_FLAG2_RSC_ENABLED
);
7348 e_err(probe
, "Unable to allocate memory for VF Data Storage - "
7349 "SRIOV disabled\n");
7350 pci_disable_sriov(adapter
->pdev
);
7353 adapter
->flags
&= ~IXGBE_FLAG_SRIOV_ENABLED
;
7354 adapter
->num_vfs
= 0;
7355 #endif /* CONFIG_PCI_IOV */
7359 * ixgbe_probe - Device Initialization Routine
7360 * @pdev: PCI device information struct
7361 * @ent: entry in ixgbe_pci_tbl
7363 * Returns 0 on success, negative on failure
7365 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7366 * The OS initialization, configuring of the adapter private structure,
7367 * and a hardware reset occur.
7369 static int __devinit
ixgbe_probe(struct pci_dev
*pdev
,
7370 const struct pci_device_id
*ent
)
7372 struct net_device
*netdev
;
7373 struct ixgbe_adapter
*adapter
= NULL
;
7374 struct ixgbe_hw
*hw
;
7375 const struct ixgbe_info
*ii
= ixgbe_info_tbl
[ent
->driver_data
];
7376 static int cards_found
;
7377 int i
, err
, pci_using_dac
;
7378 u8 part_str
[IXGBE_PBANUM_LENGTH
];
7379 unsigned int indices
= num_possible_cpus();
7385 /* Catch broken hardware that put the wrong VF device ID in
7386 * the PCIe SR-IOV capability.
7388 if (pdev
->is_virtfn
) {
7389 WARN(1, KERN_ERR
"%s (%hx:%hx) should not be a VF!\n",
7390 pci_name(pdev
), pdev
->vendor
, pdev
->device
);
7394 err
= pci_enable_device_mem(pdev
);
7398 if (!dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(64)) &&
7399 !dma_set_coherent_mask(&pdev
->dev
, DMA_BIT_MASK(64))) {
7402 err
= dma_set_mask(&pdev
->dev
, DMA_BIT_MASK(32));
7404 err
= dma_set_coherent_mask(&pdev
->dev
,
7408 "No usable DMA configuration, aborting\n");
7415 err
= pci_request_selected_regions(pdev
, pci_select_bars(pdev
,
7416 IORESOURCE_MEM
), ixgbe_driver_name
);
7419 "pci_request_selected_regions failed 0x%x\n", err
);
7423 pci_enable_pcie_error_reporting(pdev
);
7425 pci_set_master(pdev
);
7426 pci_save_state(pdev
);
7428 #ifdef CONFIG_IXGBE_DCB
7429 indices
*= MAX_TRAFFIC_CLASS
;
7432 if (ii
->mac
== ixgbe_mac_82598EB
)
7433 indices
= min_t(unsigned int, indices
, IXGBE_MAX_RSS_INDICES
);
7435 indices
= min_t(unsigned int, indices
, IXGBE_MAX_FDIR_INDICES
);
7438 indices
+= min_t(unsigned int, num_possible_cpus(),
7439 IXGBE_MAX_FCOE_INDICES
);
7441 netdev
= alloc_etherdev_mq(sizeof(struct ixgbe_adapter
), indices
);
7444 goto err_alloc_etherdev
;
7447 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
7449 adapter
= netdev_priv(netdev
);
7450 pci_set_drvdata(pdev
, adapter
);
7452 adapter
->netdev
= netdev
;
7453 adapter
->pdev
= pdev
;
7456 adapter
->msg_enable
= (1 << DEFAULT_DEBUG_LEVEL_SHIFT
) - 1;
7458 hw
->hw_addr
= ioremap(pci_resource_start(pdev
, 0),
7459 pci_resource_len(pdev
, 0));
7465 for (i
= 1; i
<= 5; i
++) {
7466 if (pci_resource_len(pdev
, i
) == 0)
7470 netdev
->netdev_ops
= &ixgbe_netdev_ops
;
7471 ixgbe_set_ethtool_ops(netdev
);
7472 netdev
->watchdog_timeo
= 5 * HZ
;
7473 strncpy(netdev
->name
, pci_name(pdev
), sizeof(netdev
->name
) - 1);
7475 adapter
->bd_number
= cards_found
;
7478 memcpy(&hw
->mac
.ops
, ii
->mac_ops
, sizeof(hw
->mac
.ops
));
7479 hw
->mac
.type
= ii
->mac
;
7482 memcpy(&hw
->eeprom
.ops
, ii
->eeprom_ops
, sizeof(hw
->eeprom
.ops
));
7483 eec
= IXGBE_READ_REG(hw
, IXGBE_EEC
);
7484 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7485 if (!(eec
& (1 << 8)))
7486 hw
->eeprom
.ops
.read
= &ixgbe_read_eeprom_bit_bang_generic
;
7489 memcpy(&hw
->phy
.ops
, ii
->phy_ops
, sizeof(hw
->phy
.ops
));
7490 hw
->phy
.sfp_type
= ixgbe_sfp_type_unknown
;
7491 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7492 hw
->phy
.mdio
.prtad
= MDIO_PRTAD_NONE
;
7493 hw
->phy
.mdio
.mmds
= 0;
7494 hw
->phy
.mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
7495 hw
->phy
.mdio
.dev
= netdev
;
7496 hw
->phy
.mdio
.mdio_read
= ixgbe_mdio_read
;
7497 hw
->phy
.mdio
.mdio_write
= ixgbe_mdio_write
;
7499 ii
->get_invariants(hw
);
7501 /* setup the private structure */
7502 err
= ixgbe_sw_init(adapter
);
7506 /* Make it possible the adapter to be woken up via WOL */
7507 switch (adapter
->hw
.mac
.type
) {
7508 case ixgbe_mac_82599EB
:
7509 case ixgbe_mac_X540
:
7510 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7517 * If there is a fan on this device and it has failed log the
7520 if (adapter
->flags
& IXGBE_FLAG_FAN_FAIL_CAPABLE
) {
7521 u32 esdp
= IXGBE_READ_REG(hw
, IXGBE_ESDP
);
7522 if (esdp
& IXGBE_ESDP_SDP1
)
7523 e_crit(probe
, "Fan has stopped, replace the adapter\n");
7526 /* reset_hw fills in the perm_addr as well */
7527 hw
->phy
.reset_if_overtemp
= true;
7528 err
= hw
->mac
.ops
.reset_hw(hw
);
7529 hw
->phy
.reset_if_overtemp
= false;
7530 if (err
== IXGBE_ERR_SFP_NOT_PRESENT
&&
7531 hw
->mac
.type
== ixgbe_mac_82598EB
) {
7533 } else if (err
== IXGBE_ERR_SFP_NOT_SUPPORTED
) {
7534 e_dev_err("failed to load because an unsupported SFP+ "
7535 "module type was detected.\n");
7536 e_dev_err("Reload the driver after installing a supported "
7540 e_dev_err("HW Init failed: %d\n", err
);
7544 ixgbe_probe_vf(adapter
, ii
);
7546 netdev
->features
= NETIF_F_SG
|
7548 NETIF_F_HW_VLAN_TX
|
7549 NETIF_F_HW_VLAN_RX
|
7550 NETIF_F_HW_VLAN_FILTER
;
7552 netdev
->features
|= NETIF_F_IPV6_CSUM
;
7553 netdev
->features
|= NETIF_F_TSO
;
7554 netdev
->features
|= NETIF_F_TSO6
;
7555 netdev
->features
|= NETIF_F_GRO
;
7556 netdev
->features
|= NETIF_F_RXHASH
;
7558 switch (adapter
->hw
.mac
.type
) {
7559 case ixgbe_mac_82599EB
:
7560 case ixgbe_mac_X540
:
7561 netdev
->features
|= NETIF_F_SCTP_CSUM
;
7567 netdev
->vlan_features
|= NETIF_F_TSO
;
7568 netdev
->vlan_features
|= NETIF_F_TSO6
;
7569 netdev
->vlan_features
|= NETIF_F_IP_CSUM
;
7570 netdev
->vlan_features
|= NETIF_F_IPV6_CSUM
;
7571 netdev
->vlan_features
|= NETIF_F_SG
;
7573 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7574 adapter
->flags
&= ~(IXGBE_FLAG_RSS_ENABLED
|
7575 IXGBE_FLAG_DCB_ENABLED
);
7577 #ifdef CONFIG_IXGBE_DCB
7578 netdev
->dcbnl_ops
= &dcbnl_ops
;
7582 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7583 if (hw
->mac
.ops
.get_device_caps
) {
7584 hw
->mac
.ops
.get_device_caps(hw
, &device_caps
);
7585 if (device_caps
& IXGBE_DEVICE_CAPS_FCOE_OFFLOADS
)
7586 adapter
->flags
&= ~IXGBE_FLAG_FCOE_CAPABLE
;
7589 if (adapter
->flags
& IXGBE_FLAG_FCOE_CAPABLE
) {
7590 netdev
->vlan_features
|= NETIF_F_FCOE_CRC
;
7591 netdev
->vlan_features
|= NETIF_F_FSO
;
7592 netdev
->vlan_features
|= NETIF_F_FCOE_MTU
;
7594 #endif /* IXGBE_FCOE */
7595 if (pci_using_dac
) {
7596 netdev
->features
|= NETIF_F_HIGHDMA
;
7597 netdev
->vlan_features
|= NETIF_F_HIGHDMA
;
7600 if (adapter
->flags2
& IXGBE_FLAG2_RSC_ENABLED
)
7601 netdev
->features
|= NETIF_F_LRO
;
7603 /* make sure the EEPROM is good */
7604 if (hw
->eeprom
.ops
.validate_checksum(hw
, NULL
) < 0) {
7605 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7610 memcpy(netdev
->dev_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7611 memcpy(netdev
->perm_addr
, hw
->mac
.perm_addr
, netdev
->addr_len
);
7613 if (ixgbe_validate_mac_addr(netdev
->perm_addr
)) {
7614 e_dev_err("invalid MAC address\n");
7619 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7620 if (hw
->mac
.ops
.disable_tx_laser
&&
7621 ((hw
->phy
.multispeed_fiber
) ||
7622 ((hw
->mac
.ops
.get_media_type(hw
) == ixgbe_media_type_fiber
) &&
7623 (hw
->mac
.type
== ixgbe_mac_82599EB
))))
7624 hw
->mac
.ops
.disable_tx_laser(hw
);
7626 setup_timer(&adapter
->service_timer
, &ixgbe_service_timer
,
7627 (unsigned long) adapter
);
7629 INIT_WORK(&adapter
->service_task
, ixgbe_service_task
);
7630 clear_bit(__IXGBE_SERVICE_SCHED
, &adapter
->state
);
7632 err
= ixgbe_init_interrupt_scheme(adapter
);
7636 if (!(adapter
->flags
& IXGBE_FLAG_RSS_ENABLED
))
7637 netdev
->features
&= ~NETIF_F_RXHASH
;
7639 switch (pdev
->device
) {
7640 case IXGBE_DEV_ID_82599_SFP
:
7641 /* Only this subdevice supports WOL */
7642 if (pdev
->subsystem_device
== IXGBE_SUBDEV_ID_82599_SFP
)
7643 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7644 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7646 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE
:
7647 /* All except this subdevice support WOL */
7648 if (pdev
->subsystem_device
!= IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ
)
7649 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7650 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7652 case IXGBE_DEV_ID_82599_KX4
:
7653 adapter
->wol
= (IXGBE_WUFC_MAG
| IXGBE_WUFC_EX
|
7654 IXGBE_WUFC_MC
| IXGBE_WUFC_BC
);
7660 device_set_wakeup_enable(&adapter
->pdev
->dev
, adapter
->wol
);
7662 /* pick up the PCI bus settings for reporting later */
7663 hw
->mac
.ops
.get_bus_info(hw
);
7665 /* print bus type/speed/width info */
7666 e_dev_info("(PCI Express:%s:%s) %pM\n",
7667 (hw
->bus
.speed
== ixgbe_bus_speed_5000
? "5.0GT/s" :
7668 hw
->bus
.speed
== ixgbe_bus_speed_2500
? "2.5GT/s" :
7670 (hw
->bus
.width
== ixgbe_bus_width_pcie_x8
? "Width x8" :
7671 hw
->bus
.width
== ixgbe_bus_width_pcie_x4
? "Width x4" :
7672 hw
->bus
.width
== ixgbe_bus_width_pcie_x1
? "Width x1" :
7676 err
= ixgbe_read_pba_string_generic(hw
, part_str
, IXGBE_PBANUM_LENGTH
);
7678 strncpy(part_str
, "Unknown", IXGBE_PBANUM_LENGTH
);
7679 if (ixgbe_is_sfp(hw
) && hw
->phy
.sfp_type
!= ixgbe_sfp_type_not_present
)
7680 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7681 hw
->mac
.type
, hw
->phy
.type
, hw
->phy
.sfp_type
,
7684 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7685 hw
->mac
.type
, hw
->phy
.type
, part_str
);
7687 if (hw
->bus
.width
<= ixgbe_bus_width_pcie_x4
) {
7688 e_dev_warn("PCI-Express bandwidth available for this card is "
7689 "not sufficient for optimal performance.\n");
7690 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7694 /* save off EEPROM version number */
7695 hw
->eeprom
.ops
.read(hw
, 0x29, &adapter
->eeprom_version
);
7697 /* reset the hardware with the new settings */
7698 err
= hw
->mac
.ops
.start_hw(hw
);
7700 if (err
== IXGBE_ERR_EEPROM_VERSION
) {
7701 /* We are running on a pre-production device, log a warning */
7702 e_dev_warn("This device is a pre-production adapter/LOM. "
7703 "Please be aware there may be issues associated "
7704 "with your hardware. If you are experiencing "
7705 "problems please contact your Intel or hardware "
7706 "representative who provided you with this "
7709 strcpy(netdev
->name
, "eth%d");
7710 err
= register_netdev(netdev
);
7714 /* carrier off reporting is important to ethtool even BEFORE open */
7715 netif_carrier_off(netdev
);
7717 #ifdef CONFIG_IXGBE_DCA
7718 if (dca_add_requester(&pdev
->dev
) == 0) {
7719 adapter
->flags
|= IXGBE_FLAG_DCA_ENABLED
;
7720 ixgbe_setup_dca(adapter
);
7723 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
) {
7724 e_info(probe
, "IOV is enabled with %d VFs\n", adapter
->num_vfs
);
7725 for (i
= 0; i
< adapter
->num_vfs
; i
++)
7726 ixgbe_vf_configuration(pdev
, (i
| 0x10000000));
7729 /* add san mac addr to netdev */
7730 ixgbe_add_sanmac_netdev(netdev
);
7732 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7737 ixgbe_release_hw_control(adapter
);
7738 ixgbe_clear_interrupt_scheme(adapter
);
7741 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7742 ixgbe_disable_sriov(adapter
);
7743 adapter
->flags2
&= ~IXGBE_FLAG2_SEARCH_FOR_SFP
;
7744 iounmap(hw
->hw_addr
);
7746 free_netdev(netdev
);
7748 pci_release_selected_regions(pdev
,
7749 pci_select_bars(pdev
, IORESOURCE_MEM
));
7752 pci_disable_device(pdev
);
7757 * ixgbe_remove - Device Removal Routine
7758 * @pdev: PCI device information struct
7760 * ixgbe_remove is called by the PCI subsystem to alert the driver
7761 * that it should release a PCI device. The could be caused by a
7762 * Hot-Plug event, or because the driver is going to be removed from
7765 static void __devexit
ixgbe_remove(struct pci_dev
*pdev
)
7767 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7768 struct net_device
*netdev
= adapter
->netdev
;
7770 set_bit(__IXGBE_DOWN
, &adapter
->state
);
7771 cancel_work_sync(&adapter
->service_task
);
7773 #ifdef CONFIG_IXGBE_DCA
7774 if (adapter
->flags
& IXGBE_FLAG_DCA_ENABLED
) {
7775 adapter
->flags
&= ~IXGBE_FLAG_DCA_ENABLED
;
7776 dca_remove_requester(&pdev
->dev
);
7777 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_DCA_CTRL
, 1);
7782 if (adapter
->flags
& IXGBE_FLAG_FCOE_ENABLED
)
7783 ixgbe_cleanup_fcoe(adapter
);
7785 #endif /* IXGBE_FCOE */
7787 /* remove the added san mac */
7788 ixgbe_del_sanmac_netdev(netdev
);
7790 if (netdev
->reg_state
== NETREG_REGISTERED
)
7791 unregister_netdev(netdev
);
7793 if (adapter
->flags
& IXGBE_FLAG_SRIOV_ENABLED
)
7794 ixgbe_disable_sriov(adapter
);
7796 ixgbe_clear_interrupt_scheme(adapter
);
7798 ixgbe_release_hw_control(adapter
);
7800 iounmap(adapter
->hw
.hw_addr
);
7801 pci_release_selected_regions(pdev
, pci_select_bars(pdev
,
7804 e_dev_info("complete\n");
7806 free_netdev(netdev
);
7808 pci_disable_pcie_error_reporting(pdev
);
7810 pci_disable_device(pdev
);
7814 * ixgbe_io_error_detected - called when PCI error is detected
7815 * @pdev: Pointer to PCI device
7816 * @state: The current pci connection state
7818 * This function is called after a PCI bus error affecting
7819 * this device has been detected.
7821 static pci_ers_result_t
ixgbe_io_error_detected(struct pci_dev
*pdev
,
7822 pci_channel_state_t state
)
7824 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7825 struct net_device
*netdev
= adapter
->netdev
;
7827 netif_device_detach(netdev
);
7829 if (state
== pci_channel_io_perm_failure
)
7830 return PCI_ERS_RESULT_DISCONNECT
;
7832 if (netif_running(netdev
))
7833 ixgbe_down(adapter
);
7834 pci_disable_device(pdev
);
7836 /* Request a slot reset. */
7837 return PCI_ERS_RESULT_NEED_RESET
;
7841 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7842 * @pdev: Pointer to PCI device
7844 * Restart the card from scratch, as if from a cold-boot.
7846 static pci_ers_result_t
ixgbe_io_slot_reset(struct pci_dev
*pdev
)
7848 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7849 pci_ers_result_t result
;
7852 if (pci_enable_device_mem(pdev
)) {
7853 e_err(probe
, "Cannot re-enable PCI device after reset.\n");
7854 result
= PCI_ERS_RESULT_DISCONNECT
;
7856 pci_set_master(pdev
);
7857 pci_restore_state(pdev
);
7858 pci_save_state(pdev
);
7860 pci_wake_from_d3(pdev
, false);
7862 ixgbe_reset(adapter
);
7863 IXGBE_WRITE_REG(&adapter
->hw
, IXGBE_WUS
, ~0);
7864 result
= PCI_ERS_RESULT_RECOVERED
;
7867 err
= pci_cleanup_aer_uncorrect_error_status(pdev
);
7869 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7870 "failed 0x%0x\n", err
);
7871 /* non-fatal, continue */
7878 * ixgbe_io_resume - called when traffic can start flowing again.
7879 * @pdev: Pointer to PCI device
7881 * This callback is called when the error recovery driver tells us that
7882 * its OK to resume normal operation.
7884 static void ixgbe_io_resume(struct pci_dev
*pdev
)
7886 struct ixgbe_adapter
*adapter
= pci_get_drvdata(pdev
);
7887 struct net_device
*netdev
= adapter
->netdev
;
7889 if (netif_running(netdev
)) {
7890 if (ixgbe_up(adapter
)) {
7891 e_info(probe
, "ixgbe_up failed after reset\n");
7896 netif_device_attach(netdev
);
7899 static struct pci_error_handlers ixgbe_err_handler
= {
7900 .error_detected
= ixgbe_io_error_detected
,
7901 .slot_reset
= ixgbe_io_slot_reset
,
7902 .resume
= ixgbe_io_resume
,
7905 static struct pci_driver ixgbe_driver
= {
7906 .name
= ixgbe_driver_name
,
7907 .id_table
= ixgbe_pci_tbl
,
7908 .probe
= ixgbe_probe
,
7909 .remove
= __devexit_p(ixgbe_remove
),
7911 .suspend
= ixgbe_suspend
,
7912 .resume
= ixgbe_resume
,
7914 .shutdown
= ixgbe_shutdown
,
7915 .err_handler
= &ixgbe_err_handler
7919 * ixgbe_init_module - Driver Registration Routine
7921 * ixgbe_init_module is the first routine called when the driver is
7922 * loaded. All it does is register with the PCI subsystem.
7924 static int __init
ixgbe_init_module(void)
7927 pr_info("%s - version %s\n", ixgbe_driver_string
, ixgbe_driver_version
);
7928 pr_info("%s\n", ixgbe_copyright
);
7930 #ifdef CONFIG_IXGBE_DCA
7931 dca_register_notify(&dca_notifier
);
7934 ret
= pci_register_driver(&ixgbe_driver
);
7938 module_init(ixgbe_init_module
);
7941 * ixgbe_exit_module - Driver Exit Cleanup Routine
7943 * ixgbe_exit_module is called just before the driver is removed
7946 static void __exit
ixgbe_exit_module(void)
7948 #ifdef CONFIG_IXGBE_DCA
7949 dca_unregister_notify(&dca_notifier
);
7951 pci_unregister_driver(&ixgbe_driver
);
7952 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7955 #ifdef CONFIG_IXGBE_DCA
7956 static int ixgbe_notify_dca(struct notifier_block
*nb
, unsigned long event
,
7961 ret_val
= driver_for_each_device(&ixgbe_driver
.driver
, NULL
, &event
,
7962 __ixgbe_notify_dca
);
7964 return ret_val
? NOTIFY_BAD
: NOTIFY_DONE
;
7967 #endif /* CONFIG_IXGBE_DCA */
7969 module_exit(ixgbe_exit_module
);