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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/roland...
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_phy.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe_common.h"
33 #include "ixgbe_phy.h"
34
35 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
36 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
37 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
38 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
39 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
40 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
41 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
42 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
43 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
44 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
45 static bool ixgbe_get_i2c_data(u32 *i2cctl);
46 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
47 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
48 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
49
50 /**
51 * ixgbe_identify_phy_generic - Get physical layer module
52 * @hw: pointer to hardware structure
53 *
54 * Determines the physical layer module found on the current adapter.
55 **/
56 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
57 {
58 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
59 u32 phy_addr;
60
61 if (hw->phy.type == ixgbe_phy_unknown) {
62 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
63 hw->phy.mdio.prtad = phy_addr;
64 if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) {
65 ixgbe_get_phy_id(hw);
66 hw->phy.type =
67 ixgbe_get_phy_type_from_id(hw->phy.id);
68 status = 0;
69 break;
70 }
71 }
72 /* clear value if nothing found */
73 hw->phy.mdio.prtad = 0;
74 } else {
75 status = 0;
76 }
77
78 return status;
79 }
80
81 /**
82 * ixgbe_get_phy_id - Get the phy type
83 * @hw: pointer to hardware structure
84 *
85 **/
86 static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
87 {
88 u32 status;
89 u16 phy_id_high = 0;
90 u16 phy_id_low = 0;
91
92 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
93 &phy_id_high);
94
95 if (status == 0) {
96 hw->phy.id = (u32)(phy_id_high << 16);
97 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
98 &phy_id_low);
99 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
100 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
101 }
102 return status;
103 }
104
105 /**
106 * ixgbe_get_phy_type_from_id - Get the phy type
107 * @hw: pointer to hardware structure
108 *
109 **/
110 static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
111 {
112 enum ixgbe_phy_type phy_type;
113
114 switch (phy_id) {
115 case TN1010_PHY_ID:
116 phy_type = ixgbe_phy_tn;
117 break;
118 case QT2022_PHY_ID:
119 phy_type = ixgbe_phy_qt;
120 break;
121 case ATH_PHY_ID:
122 phy_type = ixgbe_phy_nl;
123 break;
124 default:
125 phy_type = ixgbe_phy_unknown;
126 break;
127 }
128
129 return phy_type;
130 }
131
132 /**
133 * ixgbe_reset_phy_generic - Performs a PHY reset
134 * @hw: pointer to hardware structure
135 **/
136 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
137 {
138 /*
139 * Perform soft PHY reset to the PHY_XS.
140 * This will cause a soft reset to the PHY
141 */
142 return hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
143 MDIO_CTRL1_RESET);
144 }
145
146 /**
147 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
148 * @hw: pointer to hardware structure
149 * @reg_addr: 32 bit address of PHY register to read
150 * @phy_data: Pointer to read data from PHY register
151 **/
152 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
153 u32 device_type, u16 *phy_data)
154 {
155 u32 command;
156 u32 i;
157 u32 data;
158 s32 status = 0;
159 u16 gssr;
160
161 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
162 gssr = IXGBE_GSSR_PHY1_SM;
163 else
164 gssr = IXGBE_GSSR_PHY0_SM;
165
166 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
167 status = IXGBE_ERR_SWFW_SYNC;
168
169 if (status == 0) {
170 /* Setup and write the address cycle command */
171 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
172 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
173 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
174 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
175
176 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
177
178 /*
179 * Check every 10 usec to see if the address cycle completed.
180 * The MDI Command bit will clear when the operation is
181 * complete
182 */
183 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
184 udelay(10);
185
186 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
187
188 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
189 break;
190 }
191
192 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
193 hw_dbg(hw, "PHY address command did not complete.\n");
194 status = IXGBE_ERR_PHY;
195 }
196
197 if (status == 0) {
198 /*
199 * Address cycle complete, setup and write the read
200 * command
201 */
202 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
203 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
204 (hw->phy.mdio.prtad <<
205 IXGBE_MSCA_PHY_ADDR_SHIFT) |
206 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
207
208 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
209
210 /*
211 * Check every 10 usec to see if the address cycle
212 * completed. The MDI Command bit will clear when the
213 * operation is complete
214 */
215 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
216 udelay(10);
217
218 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
219
220 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
221 break;
222 }
223
224 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
225 hw_dbg(hw, "PHY read command didn't complete\n");
226 status = IXGBE_ERR_PHY;
227 } else {
228 /*
229 * Read operation is complete. Get the data
230 * from MSRWD
231 */
232 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
233 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
234 *phy_data = (u16)(data);
235 }
236 }
237
238 ixgbe_release_swfw_sync(hw, gssr);
239 }
240
241 return status;
242 }
243
244 /**
245 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
246 * @hw: pointer to hardware structure
247 * @reg_addr: 32 bit PHY register to write
248 * @device_type: 5 bit device type
249 * @phy_data: Data to write to the PHY register
250 **/
251 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
252 u32 device_type, u16 phy_data)
253 {
254 u32 command;
255 u32 i;
256 s32 status = 0;
257 u16 gssr;
258
259 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
260 gssr = IXGBE_GSSR_PHY1_SM;
261 else
262 gssr = IXGBE_GSSR_PHY0_SM;
263
264 if (ixgbe_acquire_swfw_sync(hw, gssr) != 0)
265 status = IXGBE_ERR_SWFW_SYNC;
266
267 if (status == 0) {
268 /* Put the data in the MDI single read and write data register*/
269 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
270
271 /* Setup and write the address cycle command */
272 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
273 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
274 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
275 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
276
277 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
278
279 /*
280 * Check every 10 usec to see if the address cycle completed.
281 * The MDI Command bit will clear when the operation is
282 * complete
283 */
284 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
285 udelay(10);
286
287 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
288
289 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
290 break;
291 }
292
293 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
294 hw_dbg(hw, "PHY address cmd didn't complete\n");
295 status = IXGBE_ERR_PHY;
296 }
297
298 if (status == 0) {
299 /*
300 * Address cycle complete, setup and write the write
301 * command
302 */
303 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
304 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
305 (hw->phy.mdio.prtad <<
306 IXGBE_MSCA_PHY_ADDR_SHIFT) |
307 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
308
309 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
310
311 /*
312 * Check every 10 usec to see if the address cycle
313 * completed. The MDI Command bit will clear when the
314 * operation is complete
315 */
316 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
317 udelay(10);
318
319 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
320
321 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
322 break;
323 }
324
325 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
326 hw_dbg(hw, "PHY address cmd didn't complete\n");
327 status = IXGBE_ERR_PHY;
328 }
329 }
330
331 ixgbe_release_swfw_sync(hw, gssr);
332 }
333
334 return status;
335 }
336
337 /**
338 * ixgbe_setup_phy_link_generic - Set and restart autoneg
339 * @hw: pointer to hardware structure
340 *
341 * Restart autonegotiation and PHY and waits for completion.
342 **/
343 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
344 {
345 s32 status = IXGBE_NOT_IMPLEMENTED;
346 u32 time_out;
347 u32 max_time_out = 10;
348 u16 autoneg_reg;
349
350 /*
351 * Set advertisement settings in PHY based on autoneg_advertised
352 * settings. If autoneg_advertised = 0, then advertise default values
353 * tnx devices cannot be "forced" to a autoneg 10G and fail. But can
354 * for a 1G.
355 */
356 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
357
358 if (hw->phy.autoneg_advertised == IXGBE_LINK_SPEED_1GB_FULL)
359 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
360 else
361 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
362
363 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
364
365 /* Restart PHY autonegotiation and wait for completion */
366 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, &autoneg_reg);
367
368 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
369
370 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_AN, autoneg_reg);
371
372 /* Wait for autonegotiation to finish */
373 for (time_out = 0; time_out < max_time_out; time_out++) {
374 udelay(10);
375 /* Restart PHY autonegotiation and wait for completion */
376 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
377 &autoneg_reg);
378
379 autoneg_reg &= MDIO_AN_STAT1_COMPLETE;
380 if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) {
381 status = 0;
382 break;
383 }
384 }
385
386 if (time_out == max_time_out)
387 status = IXGBE_ERR_LINK_SETUP;
388
389 return status;
390 }
391
392 /**
393 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
394 * @hw: pointer to hardware structure
395 * @speed: new link speed
396 * @autoneg: true if autonegotiation enabled
397 **/
398 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
399 ixgbe_link_speed speed,
400 bool autoneg,
401 bool autoneg_wait_to_complete)
402 {
403
404 /*
405 * Clear autoneg_advertised and set new values based on input link
406 * speed.
407 */
408 hw->phy.autoneg_advertised = 0;
409
410 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
411 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
412
413 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
414 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
415
416 /* Setup link based on the new speed settings */
417 hw->phy.ops.setup_link(hw);
418
419 return 0;
420 }
421
422 /**
423 * ixgbe_reset_phy_nl - Performs a PHY reset
424 * @hw: pointer to hardware structure
425 **/
426 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
427 {
428 u16 phy_offset, control, eword, edata, block_crc;
429 bool end_data = false;
430 u16 list_offset, data_offset;
431 u16 phy_data = 0;
432 s32 ret_val = 0;
433 u32 i;
434
435 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
436
437 /* reset the PHY and poll for completion */
438 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
439 (phy_data | MDIO_CTRL1_RESET));
440
441 for (i = 0; i < 100; i++) {
442 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
443 &phy_data);
444 if ((phy_data & MDIO_CTRL1_RESET) == 0)
445 break;
446 msleep(10);
447 }
448
449 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
450 hw_dbg(hw, "PHY reset did not complete.\n");
451 ret_val = IXGBE_ERR_PHY;
452 goto out;
453 }
454
455 /* Get init offsets */
456 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
457 &data_offset);
458 if (ret_val != 0)
459 goto out;
460
461 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
462 data_offset++;
463 while (!end_data) {
464 /*
465 * Read control word from PHY init contents offset
466 */
467 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
468 control = (eword & IXGBE_CONTROL_MASK_NL) >>
469 IXGBE_CONTROL_SHIFT_NL;
470 edata = eword & IXGBE_DATA_MASK_NL;
471 switch (control) {
472 case IXGBE_DELAY_NL:
473 data_offset++;
474 hw_dbg(hw, "DELAY: %d MS\n", edata);
475 msleep(edata);
476 break;
477 case IXGBE_DATA_NL:
478 hw_dbg(hw, "DATA:\n");
479 data_offset++;
480 hw->eeprom.ops.read(hw, data_offset++,
481 &phy_offset);
482 for (i = 0; i < edata; i++) {
483 hw->eeprom.ops.read(hw, data_offset, &eword);
484 hw->phy.ops.write_reg(hw, phy_offset,
485 MDIO_MMD_PMAPMD, eword);
486 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
487 phy_offset);
488 data_offset++;
489 phy_offset++;
490 }
491 break;
492 case IXGBE_CONTROL_NL:
493 data_offset++;
494 hw_dbg(hw, "CONTROL:\n");
495 if (edata == IXGBE_CONTROL_EOL_NL) {
496 hw_dbg(hw, "EOL\n");
497 end_data = true;
498 } else if (edata == IXGBE_CONTROL_SOL_NL) {
499 hw_dbg(hw, "SOL\n");
500 } else {
501 hw_dbg(hw, "Bad control value\n");
502 ret_val = IXGBE_ERR_PHY;
503 goto out;
504 }
505 break;
506 default:
507 hw_dbg(hw, "Bad control type\n");
508 ret_val = IXGBE_ERR_PHY;
509 goto out;
510 }
511 }
512
513 out:
514 return ret_val;
515 }
516
517 /**
518 * ixgbe_identify_sfp_module_generic - Identifies SFP module and assigns
519 * the PHY type.
520 * @hw: pointer to hardware structure
521 *
522 * Searches for and indentifies the SFP module. Assings appropriate PHY type.
523 **/
524 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
525 {
526 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
527 u32 vendor_oui = 0;
528 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
529 u8 identifier = 0;
530 u8 comp_codes_1g = 0;
531 u8 comp_codes_10g = 0;
532 u8 oui_bytes[3] = {0, 0, 0};
533 u8 cable_tech = 0;
534 u8 cable_spec = 0;
535 u16 enforce_sfp = 0;
536
537 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
538 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
539 status = IXGBE_ERR_SFP_NOT_PRESENT;
540 goto out;
541 }
542
543 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
544 &identifier);
545
546 if (status == IXGBE_ERR_SFP_NOT_PRESENT || status == IXGBE_ERR_I2C) {
547 status = IXGBE_ERR_SFP_NOT_PRESENT;
548 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
549 if (hw->phy.type != ixgbe_phy_nl) {
550 hw->phy.id = 0;
551 hw->phy.type = ixgbe_phy_unknown;
552 }
553 goto out;
554 }
555
556 if (identifier == IXGBE_SFF_IDENTIFIER_SFP) {
557 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_1GBE_COMP_CODES,
558 &comp_codes_1g);
559 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_10GBE_COMP_CODES,
560 &comp_codes_10g);
561 hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_CABLE_TECHNOLOGY,
562 &cable_tech);
563
564 /* ID Module
565 * =========
566 * 0 SFP_DA_CU
567 * 1 SFP_SR
568 * 2 SFP_LR
569 * 3 SFP_DA_CORE0 - 82599-specific
570 * 4 SFP_DA_CORE1 - 82599-specific
571 * 5 SFP_SR/LR_CORE0 - 82599-specific
572 * 6 SFP_SR/LR_CORE1 - 82599-specific
573 */
574 if (hw->mac.type == ixgbe_mac_82598EB) {
575 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
576 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
577 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
578 hw->phy.sfp_type = ixgbe_sfp_type_sr;
579 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
580 hw->phy.sfp_type = ixgbe_sfp_type_lr;
581 else
582 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
583 } else if (hw->mac.type == ixgbe_mac_82599EB) {
584 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
585 if (hw->bus.lan_id == 0)
586 hw->phy.sfp_type =
587 ixgbe_sfp_type_da_cu_core0;
588 else
589 hw->phy.sfp_type =
590 ixgbe_sfp_type_da_cu_core1;
591 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
592 hw->phy.ops.read_i2c_eeprom(
593 hw, IXGBE_SFF_CABLE_SPEC_COMP,
594 &cable_spec);
595 if (cable_spec &
596 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
597 if (hw->bus.lan_id == 0)
598 hw->phy.sfp_type =
599 ixgbe_sfp_type_da_act_lmt_core0;
600 else
601 hw->phy.sfp_type =
602 ixgbe_sfp_type_da_act_lmt_core1;
603 } else {
604 hw->phy.sfp_type =
605 ixgbe_sfp_type_unknown;
606 }
607 } else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
608 if (hw->bus.lan_id == 0)
609 hw->phy.sfp_type =
610 ixgbe_sfp_type_srlr_core0;
611 else
612 hw->phy.sfp_type =
613 ixgbe_sfp_type_srlr_core1;
614 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
615 if (hw->bus.lan_id == 0)
616 hw->phy.sfp_type =
617 ixgbe_sfp_type_srlr_core0;
618 else
619 hw->phy.sfp_type =
620 ixgbe_sfp_type_srlr_core1;
621 else
622 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
623 }
624
625 if (hw->phy.sfp_type != stored_sfp_type)
626 hw->phy.sfp_setup_needed = true;
627
628 /* Determine if the SFP+ PHY is dual speed or not. */
629 hw->phy.multispeed_fiber = false;
630 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
631 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
632 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
633 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
634 hw->phy.multispeed_fiber = true;
635
636 /* Determine PHY vendor */
637 if (hw->phy.type != ixgbe_phy_nl) {
638 hw->phy.id = identifier;
639 hw->phy.ops.read_i2c_eeprom(hw,
640 IXGBE_SFF_VENDOR_OUI_BYTE0,
641 &oui_bytes[0]);
642 hw->phy.ops.read_i2c_eeprom(hw,
643 IXGBE_SFF_VENDOR_OUI_BYTE1,
644 &oui_bytes[1]);
645 hw->phy.ops.read_i2c_eeprom(hw,
646 IXGBE_SFF_VENDOR_OUI_BYTE2,
647 &oui_bytes[2]);
648
649 vendor_oui =
650 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
651 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
652 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
653
654 switch (vendor_oui) {
655 case IXGBE_SFF_VENDOR_OUI_TYCO:
656 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
657 hw->phy.type =
658 ixgbe_phy_sfp_passive_tyco;
659 break;
660 case IXGBE_SFF_VENDOR_OUI_FTL:
661 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
662 hw->phy.type = ixgbe_phy_sfp_ftl_active;
663 else
664 hw->phy.type = ixgbe_phy_sfp_ftl;
665 break;
666 case IXGBE_SFF_VENDOR_OUI_AVAGO:
667 hw->phy.type = ixgbe_phy_sfp_avago;
668 break;
669 case IXGBE_SFF_VENDOR_OUI_INTEL:
670 hw->phy.type = ixgbe_phy_sfp_intel;
671 break;
672 default:
673 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
674 hw->phy.type =
675 ixgbe_phy_sfp_passive_unknown;
676 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
677 hw->phy.type =
678 ixgbe_phy_sfp_active_unknown;
679 else
680 hw->phy.type = ixgbe_phy_sfp_unknown;
681 break;
682 }
683 }
684
685 /* All passive DA cables are supported */
686 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
687 IXGBE_SFF_DA_ACTIVE_CABLE)) {
688 status = 0;
689 goto out;
690 }
691
692 /* 1G SFP modules are not supported */
693 if (comp_codes_10g == 0) {
694 hw->phy.type = ixgbe_phy_sfp_unsupported;
695 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
696 goto out;
697 }
698
699 /* Anything else 82598-based is supported */
700 if (hw->mac.type == ixgbe_mac_82598EB) {
701 status = 0;
702 goto out;
703 }
704
705 /* This is guaranteed to be 82599, no need to check for NULL */
706 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
707 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
708 /* Make sure we're a supported PHY type */
709 if (hw->phy.type == ixgbe_phy_sfp_intel) {
710 status = 0;
711 } else {
712 hw_dbg(hw, "SFP+ module not supported\n");
713 hw->phy.type = ixgbe_phy_sfp_unsupported;
714 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
715 }
716 } else {
717 status = 0;
718 }
719 }
720
721 out:
722 return status;
723 }
724
725 /**
726 * ixgbe_get_sfp_init_sequence_offsets - Checks the MAC's EEPROM to see
727 * if it supports a given SFP+ module type, if so it returns the offsets to the
728 * phy init sequence block.
729 * @hw: pointer to hardware structure
730 * @list_offset: offset to the SFP ID list
731 * @data_offset: offset to the SFP data block
732 **/
733 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
734 u16 *list_offset,
735 u16 *data_offset)
736 {
737 u16 sfp_id;
738
739 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
740 return IXGBE_ERR_SFP_NOT_SUPPORTED;
741
742 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
743 return IXGBE_ERR_SFP_NOT_PRESENT;
744
745 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
746 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
747 return IXGBE_ERR_SFP_NOT_SUPPORTED;
748
749 /* Read offset to PHY init contents */
750 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
751
752 if ((!*list_offset) || (*list_offset == 0xFFFF))
753 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
754
755 /* Shift offset to first ID word */
756 (*list_offset)++;
757
758 /*
759 * Find the matching SFP ID in the EEPROM
760 * and program the init sequence
761 */
762 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
763
764 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
765 if (sfp_id == hw->phy.sfp_type) {
766 (*list_offset)++;
767 hw->eeprom.ops.read(hw, *list_offset, data_offset);
768 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
769 hw_dbg(hw, "SFP+ module not supported\n");
770 return IXGBE_ERR_SFP_NOT_SUPPORTED;
771 } else {
772 break;
773 }
774 } else {
775 (*list_offset) += 2;
776 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
777 return IXGBE_ERR_PHY;
778 }
779 }
780
781 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
782 hw_dbg(hw, "No matching SFP+ module found\n");
783 return IXGBE_ERR_SFP_NOT_SUPPORTED;
784 }
785
786 return 0;
787 }
788
789 /**
790 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
791 * @hw: pointer to hardware structure
792 * @byte_offset: EEPROM byte offset to read
793 * @eeprom_data: value read
794 *
795 * Performs byte read operation to SFP module's EEPROM over I2C interface.
796 **/
797 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
798 u8 *eeprom_data)
799 {
800 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
801 IXGBE_I2C_EEPROM_DEV_ADDR,
802 eeprom_data);
803 }
804
805 /**
806 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
807 * @hw: pointer to hardware structure
808 * @byte_offset: EEPROM byte offset to write
809 * @eeprom_data: value to write
810 *
811 * Performs byte write operation to SFP module's EEPROM over I2C interface.
812 **/
813 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
814 u8 eeprom_data)
815 {
816 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
817 IXGBE_I2C_EEPROM_DEV_ADDR,
818 eeprom_data);
819 }
820
821 /**
822 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
823 * @hw: pointer to hardware structure
824 * @byte_offset: byte offset to read
825 * @data: value read
826 *
827 * Performs byte read operation to SFP module's EEPROM over I2C interface at
828 * a specified deivce address.
829 **/
830 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
831 u8 dev_addr, u8 *data)
832 {
833 s32 status = 0;
834 u32 max_retry = 1;
835 u32 retry = 0;
836 bool nack = 1;
837
838 do {
839 ixgbe_i2c_start(hw);
840
841 /* Device Address and write indication */
842 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
843 if (status != 0)
844 goto fail;
845
846 status = ixgbe_get_i2c_ack(hw);
847 if (status != 0)
848 goto fail;
849
850 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
851 if (status != 0)
852 goto fail;
853
854 status = ixgbe_get_i2c_ack(hw);
855 if (status != 0)
856 goto fail;
857
858 ixgbe_i2c_start(hw);
859
860 /* Device Address and read indication */
861 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
862 if (status != 0)
863 goto fail;
864
865 status = ixgbe_get_i2c_ack(hw);
866 if (status != 0)
867 goto fail;
868
869 status = ixgbe_clock_in_i2c_byte(hw, data);
870 if (status != 0)
871 goto fail;
872
873 status = ixgbe_clock_out_i2c_bit(hw, nack);
874 if (status != 0)
875 goto fail;
876
877 ixgbe_i2c_stop(hw);
878 break;
879
880 fail:
881 ixgbe_i2c_bus_clear(hw);
882 retry++;
883 if (retry < max_retry)
884 hw_dbg(hw, "I2C byte read error - Retrying.\n");
885 else
886 hw_dbg(hw, "I2C byte read error.\n");
887
888 } while (retry < max_retry);
889
890 return status;
891 }
892
893 /**
894 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
895 * @hw: pointer to hardware structure
896 * @byte_offset: byte offset to write
897 * @data: value to write
898 *
899 * Performs byte write operation to SFP module's EEPROM over I2C interface at
900 * a specified device address.
901 **/
902 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
903 u8 dev_addr, u8 data)
904 {
905 s32 status = 0;
906 u32 max_retry = 1;
907 u32 retry = 0;
908
909 do {
910 ixgbe_i2c_start(hw);
911
912 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
913 if (status != 0)
914 goto fail;
915
916 status = ixgbe_get_i2c_ack(hw);
917 if (status != 0)
918 goto fail;
919
920 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
921 if (status != 0)
922 goto fail;
923
924 status = ixgbe_get_i2c_ack(hw);
925 if (status != 0)
926 goto fail;
927
928 status = ixgbe_clock_out_i2c_byte(hw, data);
929 if (status != 0)
930 goto fail;
931
932 status = ixgbe_get_i2c_ack(hw);
933 if (status != 0)
934 goto fail;
935
936 ixgbe_i2c_stop(hw);
937 break;
938
939 fail:
940 ixgbe_i2c_bus_clear(hw);
941 retry++;
942 if (retry < max_retry)
943 hw_dbg(hw, "I2C byte write error - Retrying.\n");
944 else
945 hw_dbg(hw, "I2C byte write error.\n");
946 } while (retry < max_retry);
947
948 return status;
949 }
950
951 /**
952 * ixgbe_i2c_start - Sets I2C start condition
953 * @hw: pointer to hardware structure
954 *
955 * Sets I2C start condition (High -> Low on SDA while SCL is High)
956 **/
957 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
958 {
959 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
960
961 /* Start condition must begin with data and clock high */
962 ixgbe_set_i2c_data(hw, &i2cctl, 1);
963 ixgbe_raise_i2c_clk(hw, &i2cctl);
964
965 /* Setup time for start condition (4.7us) */
966 udelay(IXGBE_I2C_T_SU_STA);
967
968 ixgbe_set_i2c_data(hw, &i2cctl, 0);
969
970 /* Hold time for start condition (4us) */
971 udelay(IXGBE_I2C_T_HD_STA);
972
973 ixgbe_lower_i2c_clk(hw, &i2cctl);
974
975 /* Minimum low period of clock is 4.7 us */
976 udelay(IXGBE_I2C_T_LOW);
977
978 }
979
980 /**
981 * ixgbe_i2c_stop - Sets I2C stop condition
982 * @hw: pointer to hardware structure
983 *
984 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
985 **/
986 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
987 {
988 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
989
990 /* Stop condition must begin with data low and clock high */
991 ixgbe_set_i2c_data(hw, &i2cctl, 0);
992 ixgbe_raise_i2c_clk(hw, &i2cctl);
993
994 /* Setup time for stop condition (4us) */
995 udelay(IXGBE_I2C_T_SU_STO);
996
997 ixgbe_set_i2c_data(hw, &i2cctl, 1);
998
999 /* bus free time between stop and start (4.7us)*/
1000 udelay(IXGBE_I2C_T_BUF);
1001 }
1002
1003 /**
1004 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1005 * @hw: pointer to hardware structure
1006 * @data: data byte to clock in
1007 *
1008 * Clocks in one byte data via I2C data/clock
1009 **/
1010 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1011 {
1012 s32 status = 0;
1013 s32 i;
1014 bool bit = 0;
1015
1016 for (i = 7; i >= 0; i--) {
1017 status = ixgbe_clock_in_i2c_bit(hw, &bit);
1018 *data |= bit << i;
1019
1020 if (status != 0)
1021 break;
1022 }
1023
1024 return status;
1025 }
1026
1027 /**
1028 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1029 * @hw: pointer to hardware structure
1030 * @data: data byte clocked out
1031 *
1032 * Clocks out one byte data via I2C data/clock
1033 **/
1034 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1035 {
1036 s32 status = 0;
1037 s32 i;
1038 u32 i2cctl;
1039 bool bit = 0;
1040
1041 for (i = 7; i >= 0; i--) {
1042 bit = (data >> i) & 0x1;
1043 status = ixgbe_clock_out_i2c_bit(hw, bit);
1044
1045 if (status != 0)
1046 break;
1047 }
1048
1049 /* Release SDA line (set high) */
1050 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1051 i2cctl |= IXGBE_I2C_DATA_OUT;
1052 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1053
1054 return status;
1055 }
1056
1057 /**
1058 * ixgbe_get_i2c_ack - Polls for I2C ACK
1059 * @hw: pointer to hardware structure
1060 *
1061 * Clocks in/out one bit via I2C data/clock
1062 **/
1063 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1064 {
1065 s32 status;
1066 u32 i = 0;
1067 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1068 u32 timeout = 10;
1069 bool ack = 1;
1070
1071 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1072
1073 if (status != 0)
1074 goto out;
1075
1076 /* Minimum high period of clock is 4us */
1077 udelay(IXGBE_I2C_T_HIGH);
1078
1079 /* Poll for ACK. Note that ACK in I2C spec is
1080 * transition from 1 to 0 */
1081 for (i = 0; i < timeout; i++) {
1082 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1083 ack = ixgbe_get_i2c_data(&i2cctl);
1084
1085 udelay(1);
1086 if (ack == 0)
1087 break;
1088 }
1089
1090 if (ack == 1) {
1091 hw_dbg(hw, "I2C ack was not received.\n");
1092 status = IXGBE_ERR_I2C;
1093 }
1094
1095 ixgbe_lower_i2c_clk(hw, &i2cctl);
1096
1097 /* Minimum low period of clock is 4.7 us */
1098 udelay(IXGBE_I2C_T_LOW);
1099
1100 out:
1101 return status;
1102 }
1103
1104 /**
1105 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1106 * @hw: pointer to hardware structure
1107 * @data: read data value
1108 *
1109 * Clocks in one bit via I2C data/clock
1110 **/
1111 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1112 {
1113 s32 status;
1114 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1115
1116 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1117
1118 /* Minimum high period of clock is 4us */
1119 udelay(IXGBE_I2C_T_HIGH);
1120
1121 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1122 *data = ixgbe_get_i2c_data(&i2cctl);
1123
1124 ixgbe_lower_i2c_clk(hw, &i2cctl);
1125
1126 /* Minimum low period of clock is 4.7 us */
1127 udelay(IXGBE_I2C_T_LOW);
1128
1129 return status;
1130 }
1131
1132 /**
1133 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1134 * @hw: pointer to hardware structure
1135 * @data: data value to write
1136 *
1137 * Clocks out one bit via I2C data/clock
1138 **/
1139 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1140 {
1141 s32 status;
1142 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1143
1144 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1145 if (status == 0) {
1146 status = ixgbe_raise_i2c_clk(hw, &i2cctl);
1147
1148 /* Minimum high period of clock is 4us */
1149 udelay(IXGBE_I2C_T_HIGH);
1150
1151 ixgbe_lower_i2c_clk(hw, &i2cctl);
1152
1153 /* Minimum low period of clock is 4.7 us.
1154 * This also takes care of the data hold time.
1155 */
1156 udelay(IXGBE_I2C_T_LOW);
1157 } else {
1158 status = IXGBE_ERR_I2C;
1159 hw_dbg(hw, "I2C data was not set to %X\n", data);
1160 }
1161
1162 return status;
1163 }
1164 /**
1165 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1166 * @hw: pointer to hardware structure
1167 * @i2cctl: Current value of I2CCTL register
1168 *
1169 * Raises the I2C clock line '0'->'1'
1170 **/
1171 static s32 ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1172 {
1173 s32 status = 0;
1174
1175 *i2cctl |= IXGBE_I2C_CLK_OUT;
1176
1177 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1178
1179 /* SCL rise time (1000ns) */
1180 udelay(IXGBE_I2C_T_RISE);
1181
1182 return status;
1183 }
1184
1185 /**
1186 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1187 * @hw: pointer to hardware structure
1188 * @i2cctl: Current value of I2CCTL register
1189 *
1190 * Lowers the I2C clock line '1'->'0'
1191 **/
1192 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1193 {
1194
1195 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1196
1197 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1198
1199 /* SCL fall time (300ns) */
1200 udelay(IXGBE_I2C_T_FALL);
1201 }
1202
1203 /**
1204 * ixgbe_set_i2c_data - Sets the I2C data bit
1205 * @hw: pointer to hardware structure
1206 * @i2cctl: Current value of I2CCTL register
1207 * @data: I2C data value (0 or 1) to set
1208 *
1209 * Sets the I2C data bit
1210 **/
1211 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1212 {
1213 s32 status = 0;
1214
1215 if (data)
1216 *i2cctl |= IXGBE_I2C_DATA_OUT;
1217 else
1218 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1219
1220 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1221
1222 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1223 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1224
1225 /* Verify data was set correctly */
1226 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1227 if (data != ixgbe_get_i2c_data(i2cctl)) {
1228 status = IXGBE_ERR_I2C;
1229 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
1230 }
1231
1232 return status;
1233 }
1234
1235 /**
1236 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1237 * @hw: pointer to hardware structure
1238 * @i2cctl: Current value of I2CCTL register
1239 *
1240 * Returns the I2C data bit value
1241 **/
1242 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1243 {
1244 bool data;
1245
1246 if (*i2cctl & IXGBE_I2C_DATA_IN)
1247 data = 1;
1248 else
1249 data = 0;
1250
1251 return data;
1252 }
1253
1254 /**
1255 * ixgbe_i2c_bus_clear - Clears the I2C bus
1256 * @hw: pointer to hardware structure
1257 *
1258 * Clears the I2C bus by sending nine clock pulses.
1259 * Used when data line is stuck low.
1260 **/
1261 static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1262 {
1263 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1264 u32 i;
1265
1266 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1267
1268 for (i = 0; i < 9; i++) {
1269 ixgbe_raise_i2c_clk(hw, &i2cctl);
1270
1271 /* Min high period of clock is 4us */
1272 udelay(IXGBE_I2C_T_HIGH);
1273
1274 ixgbe_lower_i2c_clk(hw, &i2cctl);
1275
1276 /* Min low period of clock is 4.7us*/
1277 udelay(IXGBE_I2C_T_LOW);
1278 }
1279
1280 /* Put the i2c bus back to default state */
1281 ixgbe_i2c_stop(hw);
1282 }
1283
1284 /**
1285 * ixgbe_check_phy_link_tnx - Determine link and speed status
1286 * @hw: pointer to hardware structure
1287 *
1288 * Reads the VS1 register to determine if link is up and the current speed for
1289 * the PHY.
1290 **/
1291 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1292 bool *link_up)
1293 {
1294 s32 status = 0;
1295 u32 time_out;
1296 u32 max_time_out = 10;
1297 u16 phy_link = 0;
1298 u16 phy_speed = 0;
1299 u16 phy_data = 0;
1300
1301 /* Initialize speed and link to default case */
1302 *link_up = false;
1303 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1304
1305 /*
1306 * Check current speed and link status of the PHY register.
1307 * This is a vendor specific register and may have to
1308 * be changed for other copper PHYs.
1309 */
1310 for (time_out = 0; time_out < max_time_out; time_out++) {
1311 udelay(10);
1312 status = hw->phy.ops.read_reg(hw,
1313 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1314 MDIO_MMD_VEND1,
1315 &phy_data);
1316 phy_link = phy_data &
1317 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1318 phy_speed = phy_data &
1319 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1320 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1321 *link_up = true;
1322 if (phy_speed ==
1323 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1324 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1325 break;
1326 }
1327 }
1328
1329 return status;
1330 }
1331
1332 /**
1333 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1334 * @hw: pointer to hardware structure
1335 * @firmware_version: pointer to the PHY Firmware Version
1336 **/
1337 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1338 u16 *firmware_version)
1339 {
1340 s32 status = 0;
1341
1342 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, MDIO_MMD_VEND1,
1343 firmware_version);
1344
1345 return status;
1346 }
1347
Linux kernel - Deliverables
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