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intel drivers: repair missing flush operations
[deliverable/linux.git] / drivers / net / ixgbe / ixgbe_x540.c
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_X540_MAX_TX_QUEUES 128
36 #define IXGBE_X540_MAX_RX_QUEUES 128
37 #define IXGBE_X540_RAR_ENTRIES 128
38 #define IXGBE_X540_MC_TBL_SIZE 128
39 #define IXGBE_X540_VFT_TBL_SIZE 128
40 #define IXGBE_X540_RX_PB_SIZE 384
41
42 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
43 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
44 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
45 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
46 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
47 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
48
49 static enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
50 {
51 return ixgbe_media_type_copper;
52 }
53
54 static s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
55 {
56 struct ixgbe_mac_info *mac = &hw->mac;
57
58 /* Call PHY identify routine to get the phy type */
59 ixgbe_identify_phy_generic(hw);
60
61 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
62 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
63 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
64 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
65 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
66 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
67
68 return 0;
69 }
70
71 /**
72 * ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
73 * @hw: pointer to hardware structure
74 * @speed: new link speed
75 * @autoneg: true if autonegotiation enabled
76 * @autoneg_wait_to_complete: true when waiting for completion is needed
77 **/
78 static s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw,
79 ixgbe_link_speed speed, bool autoneg,
80 bool autoneg_wait_to_complete)
81 {
82 return hw->phy.ops.setup_link_speed(hw, speed, autoneg,
83 autoneg_wait_to_complete);
84 }
85
86 /**
87 * ixgbe_reset_hw_X540 - Perform hardware reset
88 * @hw: pointer to hardware structure
89 *
90 * Resets the hardware by resetting the transmit and receive units, masks
91 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
92 * reset.
93 **/
94 static s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
95 {
96 ixgbe_link_speed link_speed;
97 s32 status = 0;
98 u32 ctrl;
99 u32 ctrl_ext;
100 u32 reset_bit;
101 u32 i;
102 u32 autoc;
103 u32 autoc2;
104 bool link_up = false;
105
106 /* Call adapter stop to disable tx/rx and clear interrupts */
107 hw->mac.ops.stop_adapter(hw);
108
109 /*
110 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
111 * access and verify no pending requests before reset
112 */
113 ixgbe_disable_pcie_master(hw);
114
115 mac_reset_top:
116 /*
117 * Issue global reset to the MAC. Needs to be SW reset if link is up.
118 * If link reset is used when link is up, it might reset the PHY when
119 * mng is using it. If link is down or the flag to force full link
120 * reset is set, then perform link reset.
121 */
122 if (hw->force_full_reset) {
123 reset_bit = IXGBE_CTRL_LNK_RST;
124 } else {
125 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
126 if (!link_up)
127 reset_bit = IXGBE_CTRL_LNK_RST;
128 else
129 reset_bit = IXGBE_CTRL_RST;
130 }
131
132 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
133 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | reset_bit));
134 IXGBE_WRITE_FLUSH(hw);
135
136 /* Poll for reset bit to self-clear indicating reset is complete */
137 for (i = 0; i < 10; i++) {
138 udelay(1);
139 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
140 if (!(ctrl & reset_bit))
141 break;
142 }
143 if (ctrl & reset_bit) {
144 status = IXGBE_ERR_RESET_FAILED;
145 hw_dbg(hw, "Reset polling failed to complete.\n");
146 }
147
148 /*
149 * Double resets are required for recovery from certain error
150 * conditions. Between resets, it is necessary to stall to allow time
151 * for any pending HW events to complete. We use 1usec since that is
152 * what is needed for ixgbe_disable_pcie_master(). The second reset
153 * then clears out any effects of those events.
154 */
155 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
156 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
157 udelay(1);
158 goto mac_reset_top;
159 }
160
161 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
162 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
163 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
164 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
165 IXGBE_WRITE_FLUSH(hw);
166
167 msleep(50);
168
169 /* Set the Rx packet buffer size. */
170 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
171
172 /* Store the permanent mac address */
173 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
174
175 /*
176 * Store the original AUTOC/AUTOC2 values if they have not been
177 * stored off yet. Otherwise restore the stored original
178 * values since the reset operation sets back to defaults.
179 */
180 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
181 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
182 if (hw->mac.orig_link_settings_stored == false) {
183 hw->mac.orig_autoc = autoc;
184 hw->mac.orig_autoc2 = autoc2;
185 hw->mac.orig_link_settings_stored = true;
186 } else {
187 if (autoc != hw->mac.orig_autoc)
188 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
189 IXGBE_AUTOC_AN_RESTART));
190
191 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
192 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
193 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
194 autoc2 |= (hw->mac.orig_autoc2 &
195 IXGBE_AUTOC2_UPPER_MASK);
196 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
197 }
198 }
199
200 /*
201 * Store MAC address from RAR0, clear receive address registers, and
202 * clear the multicast table. Also reset num_rar_entries to 128,
203 * since we modify this value when programming the SAN MAC address.
204 */
205 hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
206 hw->mac.ops.init_rx_addrs(hw);
207
208 /* Store the permanent mac address */
209 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
210
211 /* Store the permanent SAN mac address */
212 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
213
214 /* Add the SAN MAC address to the RAR only if it's a valid address */
215 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
216 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
217 hw->mac.san_addr, 0, IXGBE_RAH_AV);
218
219 /* Reserve the last RAR for the SAN MAC address */
220 hw->mac.num_rar_entries--;
221 }
222
223 /* Store the alternative WWNN/WWPN prefix */
224 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
225 &hw->mac.wwpn_prefix);
226
227 return status;
228 }
229
230 /**
231 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
232 * @hw: pointer to hardware structure
233 *
234 * Starts the hardware using the generic start_hw function
235 * and the generation start_hw function.
236 * Then performs revision-specific operations, if any.
237 **/
238 static s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
239 {
240 s32 ret_val = 0;
241
242 ret_val = ixgbe_start_hw_generic(hw);
243 if (ret_val != 0)
244 goto out;
245
246 ret_val = ixgbe_start_hw_gen2(hw);
247 hw->mac.rx_pb_size = IXGBE_X540_RX_PB_SIZE;
248 out:
249 return ret_val;
250 }
251
252 /**
253 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type
254 * @hw: pointer to hardware structure
255 *
256 * Determines physical layer capabilities of the current configuration.
257 **/
258 static u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw)
259 {
260 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
261 u16 ext_ability = 0;
262
263 hw->phy.ops.identify(hw);
264
265 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
266 &ext_ability);
267 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
268 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
269 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
270 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
271 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
272 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
273
274 return physical_layer;
275 }
276
277 /**
278 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
279 * @hw: pointer to hardware structure
280 *
281 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
282 * ixgbe_hw struct in order to set up EEPROM access.
283 **/
284 static s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
285 {
286 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
287 u32 eec;
288 u16 eeprom_size;
289
290 if (eeprom->type == ixgbe_eeprom_uninitialized) {
291 eeprom->semaphore_delay = 10;
292 eeprom->type = ixgbe_flash;
293
294 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
295 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
296 IXGBE_EEC_SIZE_SHIFT);
297 eeprom->word_size = 1 << (eeprom_size +
298 IXGBE_EEPROM_WORD_SIZE_SHIFT);
299
300 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
301 eeprom->type, eeprom->word_size);
302 }
303
304 return 0;
305 }
306
307 /**
308 * ixgbe_read_eerd_X540- Read EEPROM word using EERD
309 * @hw: pointer to hardware structure
310 * @offset: offset of word in the EEPROM to read
311 * @data: word read from the EEPROM
312 *
313 * Reads a 16 bit word from the EEPROM using the EERD register.
314 **/
315 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
316 {
317 s32 status = 0;
318
319 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
320 0)
321 status = ixgbe_read_eerd_generic(hw, offset, data);
322 else
323 status = IXGBE_ERR_SWFW_SYNC;
324
325 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
326 return status;
327 }
328
329 /**
330 * ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
331 * @hw: pointer to hardware structure
332 * @offset: offset of word in the EEPROM to read
333 * @words: number of words
334 * @data: word(s) read from the EEPROM
335 *
336 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
337 **/
338 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
339 u16 offset, u16 words, u16 *data)
340 {
341 s32 status = 0;
342
343 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
344 0)
345 status = ixgbe_read_eerd_buffer_generic(hw, offset,
346 words, data);
347 else
348 status = IXGBE_ERR_SWFW_SYNC;
349
350 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
351 return status;
352 }
353
354 /**
355 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
356 * @hw: pointer to hardware structure
357 * @offset: offset of word in the EEPROM to write
358 * @data: word write to the EEPROM
359 *
360 * Write a 16 bit word to the EEPROM using the EEWR register.
361 **/
362 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
363 {
364 s32 status = 0;
365
366 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0)
367 status = ixgbe_write_eewr_generic(hw, offset, data);
368 else
369 status = IXGBE_ERR_SWFW_SYNC;
370
371 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
372 return status;
373 }
374
375 /**
376 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
377 * @hw: pointer to hardware structure
378 * @offset: offset of word in the EEPROM to write
379 * @words: number of words
380 * @data: word(s) write to the EEPROM
381 *
382 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
383 **/
384 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
385 u16 offset, u16 words, u16 *data)
386 {
387 s32 status = 0;
388
389 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) ==
390 0)
391 status = ixgbe_write_eewr_buffer_generic(hw, offset,
392 words, data);
393 else
394 status = IXGBE_ERR_SWFW_SYNC;
395
396 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
397 return status;
398 }
399
400 /**
401 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
402 *
403 * This function does not use synchronization for EERD and EEWR. It can
404 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
405 *
406 * @hw: pointer to hardware structure
407 **/
408 static u16 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
409 {
410 u16 i;
411 u16 j;
412 u16 checksum = 0;
413 u16 length = 0;
414 u16 pointer = 0;
415 u16 word = 0;
416
417 /*
418 * Do not use hw->eeprom.ops.read because we do not want to take
419 * the synchronization semaphores here. Instead use
420 * ixgbe_read_eerd_generic
421 */
422
423 /* Include 0x0-0x3F in the checksum */
424 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
425 if (ixgbe_read_eerd_generic(hw, i, &word) != 0) {
426 hw_dbg(hw, "EEPROM read failed\n");
427 break;
428 }
429 checksum += word;
430 }
431
432 /*
433 * Include all data from pointers 0x3, 0x6-0xE. This excludes the
434 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
435 */
436 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
437 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
438 continue;
439
440 if (ixgbe_read_eerd_generic(hw, i, &pointer) != 0) {
441 hw_dbg(hw, "EEPROM read failed\n");
442 break;
443 }
444
445 /* Skip pointer section if the pointer is invalid. */
446 if (pointer == 0xFFFF || pointer == 0 ||
447 pointer >= hw->eeprom.word_size)
448 continue;
449
450 if (ixgbe_read_eerd_generic(hw, pointer, &length) != 0) {
451 hw_dbg(hw, "EEPROM read failed\n");
452 break;
453 }
454
455 /* Skip pointer section if length is invalid. */
456 if (length == 0xFFFF || length == 0 ||
457 (pointer + length) >= hw->eeprom.word_size)
458 continue;
459
460 for (j = pointer+1; j <= pointer+length; j++) {
461 if (ixgbe_read_eerd_generic(hw, j, &word) != 0) {
462 hw_dbg(hw, "EEPROM read failed\n");
463 break;
464 }
465 checksum += word;
466 }
467 }
468
469 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
470
471 return checksum;
472 }
473
474 /**
475 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
476 * @hw: pointer to hardware structure
477 * @checksum_val: calculated checksum
478 *
479 * Performs checksum calculation and validates the EEPROM checksum. If the
480 * caller does not need checksum_val, the value can be NULL.
481 **/
482 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
483 u16 *checksum_val)
484 {
485 s32 status;
486 u16 checksum;
487 u16 read_checksum = 0;
488
489 /*
490 * Read the first word from the EEPROM. If this times out or fails, do
491 * not continue or we could be in for a very long wait while every
492 * EEPROM read fails
493 */
494 status = hw->eeprom.ops.read(hw, 0, &checksum);
495
496 if (status != 0) {
497 hw_dbg(hw, "EEPROM read failed\n");
498 goto out;
499 }
500
501 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
502 checksum = hw->eeprom.ops.calc_checksum(hw);
503
504 /*
505 * Do not use hw->eeprom.ops.read because we do not want to take
506 * the synchronization semaphores twice here.
507 */
508 ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
509 &read_checksum);
510
511 /*
512 * Verify read checksum from EEPROM is the same as
513 * calculated checksum
514 */
515 if (read_checksum != checksum)
516 status = IXGBE_ERR_EEPROM_CHECKSUM;
517
518 /* If the user cares, return the calculated checksum */
519 if (checksum_val)
520 *checksum_val = checksum;
521 } else {
522 status = IXGBE_ERR_SWFW_SYNC;
523 }
524
525 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
526 out:
527 return status;
528 }
529
530 /**
531 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
532 * @hw: pointer to hardware structure
533 *
534 * After writing EEPROM to shadow RAM using EEWR register, software calculates
535 * checksum and updates the EEPROM and instructs the hardware to update
536 * the flash.
537 **/
538 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
539 {
540 s32 status;
541 u16 checksum;
542
543 /*
544 * Read the first word from the EEPROM. If this times out or fails, do
545 * not continue or we could be in for a very long wait while every
546 * EEPROM read fails
547 */
548 status = hw->eeprom.ops.read(hw, 0, &checksum);
549
550 if (status != 0)
551 hw_dbg(hw, "EEPROM read failed\n");
552
553 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
554 checksum = hw->eeprom.ops.calc_checksum(hw);
555
556 /*
557 * Do not use hw->eeprom.ops.write because we do not want to
558 * take the synchronization semaphores twice here.
559 */
560 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM,
561 checksum);
562
563 if (status == 0)
564 status = ixgbe_update_flash_X540(hw);
565 else
566 status = IXGBE_ERR_SWFW_SYNC;
567 }
568
569 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
570
571 return status;
572 }
573
574 /**
575 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
576 * @hw: pointer to hardware structure
577 *
578 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
579 * EEPROM from shadow RAM to the flash device.
580 **/
581 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
582 {
583 u32 flup;
584 s32 status = IXGBE_ERR_EEPROM;
585
586 status = ixgbe_poll_flash_update_done_X540(hw);
587 if (status == IXGBE_ERR_EEPROM) {
588 hw_dbg(hw, "Flash update time out\n");
589 goto out;
590 }
591
592 flup = IXGBE_READ_REG(hw, IXGBE_EEC) | IXGBE_EEC_FLUP;
593 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
594
595 status = ixgbe_poll_flash_update_done_X540(hw);
596 if (status == 0)
597 hw_dbg(hw, "Flash update complete\n");
598 else
599 hw_dbg(hw, "Flash update time out\n");
600
601 if (hw->revision_id == 0) {
602 flup = IXGBE_READ_REG(hw, IXGBE_EEC);
603
604 if (flup & IXGBE_EEC_SEC1VAL) {
605 flup |= IXGBE_EEC_FLUP;
606 IXGBE_WRITE_REG(hw, IXGBE_EEC, flup);
607 }
608
609 status = ixgbe_poll_flash_update_done_X540(hw);
610 if (status == 0)
611 hw_dbg(hw, "Flash update complete\n");
612 else
613 hw_dbg(hw, "Flash update time out\n");
614 }
615 out:
616 return status;
617 }
618
619 /**
620 * ixgbe_poll_flash_update_done_X540 - Poll flash update status
621 * @hw: pointer to hardware structure
622 *
623 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
624 * flash update is done.
625 **/
626 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
627 {
628 u32 i;
629 u32 reg;
630 s32 status = IXGBE_ERR_EEPROM;
631
632 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
633 reg = IXGBE_READ_REG(hw, IXGBE_EEC);
634 if (reg & IXGBE_EEC_FLUDONE) {
635 status = 0;
636 break;
637 }
638 udelay(5);
639 }
640 return status;
641 }
642
643 /**
644 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
645 * @hw: pointer to hardware structure
646 * @mask: Mask to specify which semaphore to acquire
647 *
648 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
649 * the specified function (CSR, PHY0, PHY1, NVM, Flash)
650 **/
651 static s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
652 {
653 u32 swfw_sync;
654 u32 swmask = mask;
655 u32 fwmask = mask << 5;
656 u32 hwmask = 0;
657 u32 timeout = 200;
658 u32 i;
659
660 if (swmask == IXGBE_GSSR_EEP_SM)
661 hwmask = IXGBE_GSSR_FLASH_SM;
662
663 for (i = 0; i < timeout; i++) {
664 /*
665 * SW NVM semaphore bit is used for access to all
666 * SW_FW_SYNC bits (not just NVM)
667 */
668 if (ixgbe_get_swfw_sync_semaphore(hw))
669 return IXGBE_ERR_SWFW_SYNC;
670
671 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
672 if (!(swfw_sync & (fwmask | swmask | hwmask))) {
673 swfw_sync |= swmask;
674 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
675 ixgbe_release_swfw_sync_semaphore(hw);
676 break;
677 } else {
678 /*
679 * Firmware currently using resource (fwmask),
680 * hardware currently using resource (hwmask),
681 * or other software thread currently using
682 * resource (swmask)
683 */
684 ixgbe_release_swfw_sync_semaphore(hw);
685 usleep_range(5000, 10000);
686 }
687 }
688
689 /*
690 * If the resource is not released by the FW/HW the SW can assume that
691 * the FW/HW malfunctions. In that case the SW should sets the
692 * SW bit(s) of the requested resource(s) while ignoring the
693 * corresponding FW/HW bits in the SW_FW_SYNC register.
694 */
695 if (i >= timeout) {
696 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
697 if (swfw_sync & (fwmask | hwmask)) {
698 if (ixgbe_get_swfw_sync_semaphore(hw))
699 return IXGBE_ERR_SWFW_SYNC;
700
701 swfw_sync |= swmask;
702 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
703 ixgbe_release_swfw_sync_semaphore(hw);
704 }
705 }
706
707 usleep_range(5000, 10000);
708 return 0;
709 }
710
711 /**
712 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
713 * @hw: pointer to hardware structure
714 * @mask: Mask to specify which semaphore to release
715 *
716 * Releases the SWFW semaphore through the SW_FW_SYNC register
717 * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
718 **/
719 static void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
720 {
721 u32 swfw_sync;
722 u32 swmask = mask;
723
724 ixgbe_get_swfw_sync_semaphore(hw);
725
726 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
727 swfw_sync &= ~swmask;
728 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swfw_sync);
729
730 ixgbe_release_swfw_sync_semaphore(hw);
731 usleep_range(5000, 10000);
732 }
733
734 /**
735 * ixgbe_get_nvm_semaphore - Get hardware semaphore
736 * @hw: pointer to hardware structure
737 *
738 * Sets the hardware semaphores so SW/FW can gain control of shared resources
739 **/
740 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
741 {
742 s32 status = IXGBE_ERR_EEPROM;
743 u32 timeout = 2000;
744 u32 i;
745 u32 swsm;
746
747 /* Get SMBI software semaphore between device drivers first */
748 for (i = 0; i < timeout; i++) {
749 /*
750 * If the SMBI bit is 0 when we read it, then the bit will be
751 * set and we have the semaphore
752 */
753 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
754 if (!(swsm & IXGBE_SWSM_SMBI)) {
755 status = 0;
756 break;
757 }
758 udelay(50);
759 }
760
761 /* Now get the semaphore between SW/FW through the REGSMP bit */
762 if (status) {
763 for (i = 0; i < timeout; i++) {
764 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
765 if (!(swsm & IXGBE_SWFW_REGSMP))
766 break;
767
768 udelay(50);
769 }
770 } else {
771 hw_dbg(hw, "Software semaphore SMBI between device drivers "
772 "not granted.\n");
773 }
774
775 return status;
776 }
777
778 /**
779 * ixgbe_release_nvm_semaphore - Release hardware semaphore
780 * @hw: pointer to hardware structure
781 *
782 * This function clears hardware semaphore bits.
783 **/
784 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
785 {
786 u32 swsm;
787
788 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
789
790 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
791 swsm &= ~IXGBE_SWSM_SMBI;
792 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
793
794 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC);
795 swsm &= ~IXGBE_SWFW_REGSMP;
796 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC, swsm);
797
798 IXGBE_WRITE_FLUSH(hw);
799 }
800
801 /**
802 * ixgbe_blink_led_start_X540 - Blink LED based on index.
803 * @hw: pointer to hardware structure
804 * @index: led number to blink
805 *
806 * Devices that implement the version 2 interface:
807 * X540
808 **/
809 static s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
810 {
811 u32 macc_reg;
812 u32 ledctl_reg;
813
814 /*
815 * In order for the blink bit in the LED control register
816 * to work, link and speed must be forced in the MAC. We
817 * will reverse this when we stop the blinking.
818 */
819 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
820 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
821 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
822
823 /* Set the LED to LINK_UP + BLINK. */
824 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
825 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
826 ledctl_reg |= IXGBE_LED_BLINK(index);
827 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
828 IXGBE_WRITE_FLUSH(hw);
829
830 return 0;
831 }
832
833 /**
834 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
835 * @hw: pointer to hardware structure
836 * @index: led number to stop blinking
837 *
838 * Devices that implement the version 2 interface:
839 * X540
840 **/
841 static s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
842 {
843 u32 macc_reg;
844 u32 ledctl_reg;
845
846 /* Restore the LED to its default value. */
847 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
848 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
849 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
850 ledctl_reg &= ~IXGBE_LED_BLINK(index);
851 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
852
853 /* Unforce link and speed in the MAC. */
854 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
855 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
856 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
857 IXGBE_WRITE_FLUSH(hw);
858
859 return 0;
860 }
861 static struct ixgbe_mac_operations mac_ops_X540 = {
862 .init_hw = &ixgbe_init_hw_generic,
863 .reset_hw = &ixgbe_reset_hw_X540,
864 .start_hw = &ixgbe_start_hw_X540,
865 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
866 .get_media_type = &ixgbe_get_media_type_X540,
867 .get_supported_physical_layer =
868 &ixgbe_get_supported_physical_layer_X540,
869 .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
870 .get_mac_addr = &ixgbe_get_mac_addr_generic,
871 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
872 .get_device_caps = &ixgbe_get_device_caps_generic,
873 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
874 .stop_adapter = &ixgbe_stop_adapter_generic,
875 .get_bus_info = &ixgbe_get_bus_info_generic,
876 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
877 .read_analog_reg8 = NULL,
878 .write_analog_reg8 = NULL,
879 .setup_link = &ixgbe_setup_mac_link_X540,
880 .set_rxpba = &ixgbe_set_rxpba_generic,
881 .check_link = &ixgbe_check_mac_link_generic,
882 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
883 .led_on = &ixgbe_led_on_generic,
884 .led_off = &ixgbe_led_off_generic,
885 .blink_led_start = &ixgbe_blink_led_start_X540,
886 .blink_led_stop = &ixgbe_blink_led_stop_X540,
887 .set_rar = &ixgbe_set_rar_generic,
888 .clear_rar = &ixgbe_clear_rar_generic,
889 .set_vmdq = &ixgbe_set_vmdq_generic,
890 .clear_vmdq = &ixgbe_clear_vmdq_generic,
891 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
892 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
893 .enable_mc = &ixgbe_enable_mc_generic,
894 .disable_mc = &ixgbe_disable_mc_generic,
895 .clear_vfta = &ixgbe_clear_vfta_generic,
896 .set_vfta = &ixgbe_set_vfta_generic,
897 .fc_enable = &ixgbe_fc_enable_generic,
898 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic,
899 .init_uta_tables = &ixgbe_init_uta_tables_generic,
900 .setup_sfp = NULL,
901 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
902 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
903 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
904 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
905 };
906
907 static struct ixgbe_eeprom_operations eeprom_ops_X540 = {
908 .init_params = &ixgbe_init_eeprom_params_X540,
909 .read = &ixgbe_read_eerd_X540,
910 .read_buffer = &ixgbe_read_eerd_buffer_X540,
911 .write = &ixgbe_write_eewr_X540,
912 .write_buffer = &ixgbe_write_eewr_buffer_X540,
913 .calc_checksum = &ixgbe_calc_eeprom_checksum_X540,
914 .validate_checksum = &ixgbe_validate_eeprom_checksum_X540,
915 .update_checksum = &ixgbe_update_eeprom_checksum_X540,
916 };
917
918 static struct ixgbe_phy_operations phy_ops_X540 = {
919 .identify = &ixgbe_identify_phy_generic,
920 .identify_sfp = &ixgbe_identify_sfp_module_generic,
921 .init = NULL,
922 .reset = NULL,
923 .read_reg = &ixgbe_read_phy_reg_generic,
924 .write_reg = &ixgbe_write_phy_reg_generic,
925 .setup_link = &ixgbe_setup_phy_link_generic,
926 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
927 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
928 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
929 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
930 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
931 .check_overtemp = &ixgbe_tn_check_overtemp,
932 };
933
934 struct ixgbe_info ixgbe_X540_info = {
935 .mac = ixgbe_mac_X540,
936 .get_invariants = &ixgbe_get_invariants_X540,
937 .mac_ops = &mac_ops_X540,
938 .eeprom_ops = &eeprom_ops_X540,
939 .phy_ops = &phy_ops_X540,
940 .mbx_ops = &mbx_ops_generic,
941 };
Linux kernel - Deliverables
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