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[deliverable/linux.git] / drivers / net / jme.c
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 *
7 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 */
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/mii.h>
31 #include <linux/crc32.h>
32 #include <linux/delay.h>
33 #include <linux/spinlock.h>
34 #include <linux/in.h>
35 #include <linux/ip.h>
36 #include <linux/ipv6.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/if_vlan.h>
40 #include <net/ip6_checksum.h>
41 #include "jme.h"
42
43 static int force_pseudohp = -1;
44 static int no_pseudohp = -1;
45 static int no_extplug = -1;
46 module_param(force_pseudohp, int, 0);
47 MODULE_PARM_DESC(force_pseudohp,
48 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
49 module_param(no_pseudohp, int, 0);
50 MODULE_PARM_DESC(no_pseudohp, "Disable pseudo hot-plug feature.");
51 module_param(no_extplug, int, 0);
52 MODULE_PARM_DESC(no_extplug,
53 "Do not use external plug signal for pseudo hot-plug.");
54
55 static int
56 jme_mdio_read(struct net_device *netdev, int phy, int reg)
57 {
58 struct jme_adapter *jme = netdev_priv(netdev);
59 int i, val, again = (reg == MII_BMSR) ? 1 : 0;
60
61 read_again:
62 jwrite32(jme, JME_SMI, SMI_OP_REQ |
63 smi_phy_addr(phy) |
64 smi_reg_addr(reg));
65
66 wmb();
67 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
68 udelay(20);
69 val = jread32(jme, JME_SMI);
70 if ((val & SMI_OP_REQ) == 0)
71 break;
72 }
73
74 if (i == 0) {
75 jeprintk(jme->pdev, "phy(%d) read timeout : %d\n", phy, reg);
76 return 0;
77 }
78
79 if (again--)
80 goto read_again;
81
82 return (val & SMI_DATA_MASK) >> SMI_DATA_SHIFT;
83 }
84
85 static void
86 jme_mdio_write(struct net_device *netdev,
87 int phy, int reg, int val)
88 {
89 struct jme_adapter *jme = netdev_priv(netdev);
90 int i;
91
92 jwrite32(jme, JME_SMI, SMI_OP_WRITE | SMI_OP_REQ |
93 ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
94 smi_phy_addr(phy) | smi_reg_addr(reg));
95
96 wmb();
97 for (i = JME_PHY_TIMEOUT * 50 ; i > 0 ; --i) {
98 udelay(20);
99 if ((jread32(jme, JME_SMI) & SMI_OP_REQ) == 0)
100 break;
101 }
102
103 if (i == 0)
104 jeprintk(jme->pdev, "phy(%d) write timeout : %d\n", phy, reg);
105
106 return;
107 }
108
109 static inline void
110 jme_reset_phy_processor(struct jme_adapter *jme)
111 {
112 u32 val;
113
114 jme_mdio_write(jme->dev,
115 jme->mii_if.phy_id,
116 MII_ADVERTISE, ADVERTISE_ALL |
117 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
118
119 if (jme->pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
120 jme_mdio_write(jme->dev,
121 jme->mii_if.phy_id,
122 MII_CTRL1000,
123 ADVERTISE_1000FULL | ADVERTISE_1000HALF);
124
125 val = jme_mdio_read(jme->dev,
126 jme->mii_if.phy_id,
127 MII_BMCR);
128
129 jme_mdio_write(jme->dev,
130 jme->mii_if.phy_id,
131 MII_BMCR, val | BMCR_RESET);
132
133 return;
134 }
135
136 static void
137 jme_setup_wakeup_frame(struct jme_adapter *jme,
138 u32 *mask, u32 crc, int fnr)
139 {
140 int i;
141
142 /*
143 * Setup CRC pattern
144 */
145 jwrite32(jme, JME_WFOI, WFOI_CRC_SEL | (fnr & WFOI_FRAME_SEL));
146 wmb();
147 jwrite32(jme, JME_WFODP, crc);
148 wmb();
149
150 /*
151 * Setup Mask
152 */
153 for (i = 0 ; i < WAKEUP_FRAME_MASK_DWNR ; ++i) {
154 jwrite32(jme, JME_WFOI,
155 ((i << WFOI_MASK_SHIFT) & WFOI_MASK_SEL) |
156 (fnr & WFOI_FRAME_SEL));
157 wmb();
158 jwrite32(jme, JME_WFODP, mask[i]);
159 wmb();
160 }
161 }
162
163 static inline void
164 jme_reset_mac_processor(struct jme_adapter *jme)
165 {
166 u32 mask[WAKEUP_FRAME_MASK_DWNR] = {0, 0, 0, 0};
167 u32 crc = 0xCDCDCDCD;
168 u32 gpreg0;
169 int i;
170
171 jwrite32(jme, JME_GHC, jme->reg_ghc | GHC_SWRST);
172 udelay(2);
173 jwrite32(jme, JME_GHC, jme->reg_ghc);
174
175 jwrite32(jme, JME_RXDBA_LO, 0x00000000);
176 jwrite32(jme, JME_RXDBA_HI, 0x00000000);
177 jwrite32(jme, JME_RXQDC, 0x00000000);
178 jwrite32(jme, JME_RXNDA, 0x00000000);
179 jwrite32(jme, JME_TXDBA_LO, 0x00000000);
180 jwrite32(jme, JME_TXDBA_HI, 0x00000000);
181 jwrite32(jme, JME_TXQDC, 0x00000000);
182 jwrite32(jme, JME_TXNDA, 0x00000000);
183
184 jwrite32(jme, JME_RXMCHT_LO, 0x00000000);
185 jwrite32(jme, JME_RXMCHT_HI, 0x00000000);
186 for (i = 0 ; i < WAKEUP_FRAME_NR ; ++i)
187 jme_setup_wakeup_frame(jme, mask, crc, i);
188 if (jme->fpgaver)
189 gpreg0 = GPREG0_DEFAULT | GPREG0_LNKINTPOLL;
190 else
191 gpreg0 = GPREG0_DEFAULT;
192 jwrite32(jme, JME_GPREG0, gpreg0);
193 jwrite32(jme, JME_GPREG1, GPREG1_DEFAULT);
194 }
195
196 static inline void
197 jme_reset_ghc_speed(struct jme_adapter *jme)
198 {
199 jme->reg_ghc &= ~(GHC_SPEED_1000M | GHC_DPX);
200 jwrite32(jme, JME_GHC, jme->reg_ghc);
201 }
202
203 static inline void
204 jme_clear_pm(struct jme_adapter *jme)
205 {
206 jwrite32(jme, JME_PMCS, 0xFFFF0000 | jme->reg_pmcs);
207 pci_set_power_state(jme->pdev, PCI_D0);
208 pci_enable_wake(jme->pdev, PCI_D0, false);
209 }
210
211 static int
212 jme_reload_eeprom(struct jme_adapter *jme)
213 {
214 u32 val;
215 int i;
216
217 val = jread32(jme, JME_SMBCSR);
218
219 if (val & SMBCSR_EEPROMD) {
220 val |= SMBCSR_CNACK;
221 jwrite32(jme, JME_SMBCSR, val);
222 val |= SMBCSR_RELOAD;
223 jwrite32(jme, JME_SMBCSR, val);
224 mdelay(12);
225
226 for (i = JME_EEPROM_RELOAD_TIMEOUT; i > 0; --i) {
227 mdelay(1);
228 if ((jread32(jme, JME_SMBCSR) & SMBCSR_RELOAD) == 0)
229 break;
230 }
231
232 if (i == 0) {
233 jeprintk(jme->pdev, "eeprom reload timeout\n");
234 return -EIO;
235 }
236 }
237
238 return 0;
239 }
240
241 static void
242 jme_load_macaddr(struct net_device *netdev)
243 {
244 struct jme_adapter *jme = netdev_priv(netdev);
245 unsigned char macaddr[6];
246 u32 val;
247
248 spin_lock_bh(&jme->macaddr_lock);
249 val = jread32(jme, JME_RXUMA_LO);
250 macaddr[0] = (val >> 0) & 0xFF;
251 macaddr[1] = (val >> 8) & 0xFF;
252 macaddr[2] = (val >> 16) & 0xFF;
253 macaddr[3] = (val >> 24) & 0xFF;
254 val = jread32(jme, JME_RXUMA_HI);
255 macaddr[4] = (val >> 0) & 0xFF;
256 macaddr[5] = (val >> 8) & 0xFF;
257 memcpy(netdev->dev_addr, macaddr, 6);
258 spin_unlock_bh(&jme->macaddr_lock);
259 }
260
261 static inline void
262 jme_set_rx_pcc(struct jme_adapter *jme, int p)
263 {
264 switch (p) {
265 case PCC_OFF:
266 jwrite32(jme, JME_PCCRX0,
267 ((PCC_OFF_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
268 ((PCC_OFF_CNT << PCCRX_SHIFT) & PCCRX_MASK));
269 break;
270 case PCC_P1:
271 jwrite32(jme, JME_PCCRX0,
272 ((PCC_P1_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
273 ((PCC_P1_CNT << PCCRX_SHIFT) & PCCRX_MASK));
274 break;
275 case PCC_P2:
276 jwrite32(jme, JME_PCCRX0,
277 ((PCC_P2_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
278 ((PCC_P2_CNT << PCCRX_SHIFT) & PCCRX_MASK));
279 break;
280 case PCC_P3:
281 jwrite32(jme, JME_PCCRX0,
282 ((PCC_P3_TO << PCCRXTO_SHIFT) & PCCRXTO_MASK) |
283 ((PCC_P3_CNT << PCCRX_SHIFT) & PCCRX_MASK));
284 break;
285 default:
286 break;
287 }
288 wmb();
289
290 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
291 msg_rx_status(jme, "Switched to PCC_P%d\n", p);
292 }
293
294 static void
295 jme_start_irq(struct jme_adapter *jme)
296 {
297 register struct dynpcc_info *dpi = &(jme->dpi);
298
299 jme_set_rx_pcc(jme, PCC_P1);
300 dpi->cur = PCC_P1;
301 dpi->attempt = PCC_P1;
302 dpi->cnt = 0;
303
304 jwrite32(jme, JME_PCCTX,
305 ((PCC_TX_TO << PCCTXTO_SHIFT) & PCCTXTO_MASK) |
306 ((PCC_TX_CNT << PCCTX_SHIFT) & PCCTX_MASK) |
307 PCCTXQ0_EN
308 );
309
310 /*
311 * Enable Interrupts
312 */
313 jwrite32(jme, JME_IENS, INTR_ENABLE);
314 }
315
316 static inline void
317 jme_stop_irq(struct jme_adapter *jme)
318 {
319 /*
320 * Disable Interrupts
321 */
322 jwrite32f(jme, JME_IENC, INTR_ENABLE);
323 }
324
325 static inline void
326 jme_enable_shadow(struct jme_adapter *jme)
327 {
328 jwrite32(jme,
329 JME_SHBA_LO,
330 ((u32)jme->shadow_dma & ~((u32)0x1F)) | SHBA_POSTEN);
331 }
332
333 static inline void
334 jme_disable_shadow(struct jme_adapter *jme)
335 {
336 jwrite32(jme, JME_SHBA_LO, 0x0);
337 }
338
339 static u32
340 jme_linkstat_from_phy(struct jme_adapter *jme)
341 {
342 u32 phylink, bmsr;
343
344 phylink = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 17);
345 bmsr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMSR);
346 if (bmsr & BMSR_ANCOMP)
347 phylink |= PHY_LINK_AUTONEG_COMPLETE;
348
349 return phylink;
350 }
351
352 static inline void
353 jme_set_phyfifoa(struct jme_adapter *jme)
354 {
355 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0004);
356 }
357
358 static inline void
359 jme_set_phyfifob(struct jme_adapter *jme)
360 {
361 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 27, 0x0000);
362 }
363
364 static int
365 jme_check_link(struct net_device *netdev, int testonly)
366 {
367 struct jme_adapter *jme = netdev_priv(netdev);
368 u32 phylink, ghc, cnt = JME_SPDRSV_TIMEOUT, bmcr, gpreg1;
369 char linkmsg[64];
370 int rc = 0;
371
372 linkmsg[0] = '\0';
373
374 if (jme->fpgaver)
375 phylink = jme_linkstat_from_phy(jme);
376 else
377 phylink = jread32(jme, JME_PHY_LINK);
378
379 if (phylink & PHY_LINK_UP) {
380 if (!(phylink & PHY_LINK_AUTONEG_COMPLETE)) {
381 /*
382 * If we did not enable AN
383 * Speed/Duplex Info should be obtained from SMI
384 */
385 phylink = PHY_LINK_UP;
386
387 bmcr = jme_mdio_read(jme->dev,
388 jme->mii_if.phy_id,
389 MII_BMCR);
390
391 phylink |= ((bmcr & BMCR_SPEED1000) &&
392 (bmcr & BMCR_SPEED100) == 0) ?
393 PHY_LINK_SPEED_1000M :
394 (bmcr & BMCR_SPEED100) ?
395 PHY_LINK_SPEED_100M :
396 PHY_LINK_SPEED_10M;
397
398 phylink |= (bmcr & BMCR_FULLDPLX) ?
399 PHY_LINK_DUPLEX : 0;
400
401 strcat(linkmsg, "Forced: ");
402 } else {
403 /*
404 * Keep polling for speed/duplex resolve complete
405 */
406 while (!(phylink & PHY_LINK_SPEEDDPU_RESOLVED) &&
407 --cnt) {
408
409 udelay(1);
410
411 if (jme->fpgaver)
412 phylink = jme_linkstat_from_phy(jme);
413 else
414 phylink = jread32(jme, JME_PHY_LINK);
415 }
416 if (!cnt)
417 jeprintk(jme->pdev,
418 "Waiting speed resolve timeout.\n");
419
420 strcat(linkmsg, "ANed: ");
421 }
422
423 if (jme->phylink == phylink) {
424 rc = 1;
425 goto out;
426 }
427 if (testonly)
428 goto out;
429
430 jme->phylink = phylink;
431
432 ghc = jme->reg_ghc & ~(GHC_SPEED_10M |
433 GHC_SPEED_100M |
434 GHC_SPEED_1000M |
435 GHC_DPX);
436 switch (phylink & PHY_LINK_SPEED_MASK) {
437 case PHY_LINK_SPEED_10M:
438 ghc |= GHC_SPEED_10M |
439 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
440 strcat(linkmsg, "10 Mbps, ");
441 break;
442 case PHY_LINK_SPEED_100M:
443 ghc |= GHC_SPEED_100M |
444 GHC_TO_CLK_PCIE | GHC_TXMAC_CLK_PCIE;
445 strcat(linkmsg, "100 Mbps, ");
446 break;
447 case PHY_LINK_SPEED_1000M:
448 ghc |= GHC_SPEED_1000M |
449 GHC_TO_CLK_GPHY | GHC_TXMAC_CLK_GPHY;
450 strcat(linkmsg, "1000 Mbps, ");
451 break;
452 default:
453 break;
454 }
455
456 if (phylink & PHY_LINK_DUPLEX) {
457 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT);
458 ghc |= GHC_DPX;
459 } else {
460 jwrite32(jme, JME_TXMCS, TXMCS_DEFAULT |
461 TXMCS_BACKOFF |
462 TXMCS_CARRIERSENSE |
463 TXMCS_COLLISION);
464 jwrite32(jme, JME_TXTRHD, TXTRHD_TXPEN |
465 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
466 TXTRHD_TXREN |
467 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL));
468 }
469
470 gpreg1 = GPREG1_DEFAULT;
471 if (is_buggy250(jme->pdev->device, jme->chiprev)) {
472 if (!(phylink & PHY_LINK_DUPLEX))
473 gpreg1 |= GPREG1_HALFMODEPATCH;
474 switch (phylink & PHY_LINK_SPEED_MASK) {
475 case PHY_LINK_SPEED_10M:
476 jme_set_phyfifoa(jme);
477 gpreg1 |= GPREG1_RSSPATCH;
478 break;
479 case PHY_LINK_SPEED_100M:
480 jme_set_phyfifob(jme);
481 gpreg1 |= GPREG1_RSSPATCH;
482 break;
483 case PHY_LINK_SPEED_1000M:
484 jme_set_phyfifoa(jme);
485 break;
486 default:
487 break;
488 }
489 }
490
491 jwrite32(jme, JME_GPREG1, gpreg1);
492 jwrite32(jme, JME_GHC, ghc);
493 jme->reg_ghc = ghc;
494
495 strcat(linkmsg, (phylink & PHY_LINK_DUPLEX) ?
496 "Full-Duplex, " :
497 "Half-Duplex, ");
498 strcat(linkmsg, (phylink & PHY_LINK_MDI_STAT) ?
499 "MDI-X" :
500 "MDI");
501 msg_link(jme, "Link is up at %s.\n", linkmsg);
502 netif_carrier_on(netdev);
503 } else {
504 if (testonly)
505 goto out;
506
507 msg_link(jme, "Link is down.\n");
508 jme->phylink = 0;
509 netif_carrier_off(netdev);
510 }
511
512 out:
513 return rc;
514 }
515
516 static int
517 jme_setup_tx_resources(struct jme_adapter *jme)
518 {
519 struct jme_ring *txring = &(jme->txring[0]);
520
521 txring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
522 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
523 &(txring->dmaalloc),
524 GFP_ATOMIC);
525
526 if (!txring->alloc) {
527 txring->desc = NULL;
528 txring->dmaalloc = 0;
529 txring->dma = 0;
530 return -ENOMEM;
531 }
532
533 /*
534 * 16 Bytes align
535 */
536 txring->desc = (void *)ALIGN((unsigned long)(txring->alloc),
537 RING_DESC_ALIGN);
538 txring->dma = ALIGN(txring->dmaalloc, RING_DESC_ALIGN);
539 txring->next_to_use = 0;
540 atomic_set(&txring->next_to_clean, 0);
541 atomic_set(&txring->nr_free, jme->tx_ring_size);
542
543 /*
544 * Initialize Transmit Descriptors
545 */
546 memset(txring->alloc, 0, TX_RING_ALLOC_SIZE(jme->tx_ring_size));
547 memset(txring->bufinf, 0,
548 sizeof(struct jme_buffer_info) * jme->tx_ring_size);
549
550 return 0;
551 }
552
553 static void
554 jme_free_tx_resources(struct jme_adapter *jme)
555 {
556 int i;
557 struct jme_ring *txring = &(jme->txring[0]);
558 struct jme_buffer_info *txbi = txring->bufinf;
559
560 if (txring->alloc) {
561 for (i = 0 ; i < jme->tx_ring_size ; ++i) {
562 txbi = txring->bufinf + i;
563 if (txbi->skb) {
564 dev_kfree_skb(txbi->skb);
565 txbi->skb = NULL;
566 }
567 txbi->mapping = 0;
568 txbi->len = 0;
569 txbi->nr_desc = 0;
570 txbi->start_xmit = 0;
571 }
572
573 dma_free_coherent(&(jme->pdev->dev),
574 TX_RING_ALLOC_SIZE(jme->tx_ring_size),
575 txring->alloc,
576 txring->dmaalloc);
577
578 txring->alloc = NULL;
579 txring->desc = NULL;
580 txring->dmaalloc = 0;
581 txring->dma = 0;
582 }
583 txring->next_to_use = 0;
584 atomic_set(&txring->next_to_clean, 0);
585 atomic_set(&txring->nr_free, 0);
586
587 }
588
589 static inline void
590 jme_enable_tx_engine(struct jme_adapter *jme)
591 {
592 /*
593 * Select Queue 0
594 */
595 jwrite32(jme, JME_TXCS, TXCS_DEFAULT | TXCS_SELECT_QUEUE0);
596 wmb();
597
598 /*
599 * Setup TX Queue 0 DMA Bass Address
600 */
601 jwrite32(jme, JME_TXDBA_LO, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
602 jwrite32(jme, JME_TXDBA_HI, (__u64)(jme->txring[0].dma) >> 32);
603 jwrite32(jme, JME_TXNDA, (__u64)jme->txring[0].dma & 0xFFFFFFFFUL);
604
605 /*
606 * Setup TX Descptor Count
607 */
608 jwrite32(jme, JME_TXQDC, jme->tx_ring_size);
609
610 /*
611 * Enable TX Engine
612 */
613 wmb();
614 jwrite32(jme, JME_TXCS, jme->reg_txcs |
615 TXCS_SELECT_QUEUE0 |
616 TXCS_ENABLE);
617
618 }
619
620 static inline void
621 jme_restart_tx_engine(struct jme_adapter *jme)
622 {
623 /*
624 * Restart TX Engine
625 */
626 jwrite32(jme, JME_TXCS, jme->reg_txcs |
627 TXCS_SELECT_QUEUE0 |
628 TXCS_ENABLE);
629 }
630
631 static inline void
632 jme_disable_tx_engine(struct jme_adapter *jme)
633 {
634 int i;
635 u32 val;
636
637 /*
638 * Disable TX Engine
639 */
640 jwrite32(jme, JME_TXCS, jme->reg_txcs | TXCS_SELECT_QUEUE0);
641 wmb();
642
643 val = jread32(jme, JME_TXCS);
644 for (i = JME_TX_DISABLE_TIMEOUT ; (val & TXCS_ENABLE) && i > 0 ; --i) {
645 mdelay(1);
646 val = jread32(jme, JME_TXCS);
647 rmb();
648 }
649
650 if (!i)
651 jeprintk(jme->pdev, "Disable TX engine timeout.\n");
652 }
653
654 static void
655 jme_set_clean_rxdesc(struct jme_adapter *jme, int i)
656 {
657 struct jme_ring *rxring = jme->rxring;
658 register struct rxdesc *rxdesc = rxring->desc;
659 struct jme_buffer_info *rxbi = rxring->bufinf;
660 rxdesc += i;
661 rxbi += i;
662
663 rxdesc->dw[0] = 0;
664 rxdesc->dw[1] = 0;
665 rxdesc->desc1.bufaddrh = cpu_to_le32((__u64)rxbi->mapping >> 32);
666 rxdesc->desc1.bufaddrl = cpu_to_le32(
667 (__u64)rxbi->mapping & 0xFFFFFFFFUL);
668 rxdesc->desc1.datalen = cpu_to_le16(rxbi->len);
669 if (jme->dev->features & NETIF_F_HIGHDMA)
670 rxdesc->desc1.flags = RXFLAG_64BIT;
671 wmb();
672 rxdesc->desc1.flags |= RXFLAG_OWN | RXFLAG_INT;
673 }
674
675 static int
676 jme_make_new_rx_buf(struct jme_adapter *jme, int i)
677 {
678 struct jme_ring *rxring = &(jme->rxring[0]);
679 struct jme_buffer_info *rxbi = rxring->bufinf + i;
680 struct sk_buff *skb;
681
682 skb = netdev_alloc_skb(jme->dev,
683 jme->dev->mtu + RX_EXTRA_LEN);
684 if (unlikely(!skb))
685 return -ENOMEM;
686
687 rxbi->skb = skb;
688 rxbi->len = skb_tailroom(skb);
689 rxbi->mapping = pci_map_page(jme->pdev,
690 virt_to_page(skb->data),
691 offset_in_page(skb->data),
692 rxbi->len,
693 PCI_DMA_FROMDEVICE);
694
695 return 0;
696 }
697
698 static void
699 jme_free_rx_buf(struct jme_adapter *jme, int i)
700 {
701 struct jme_ring *rxring = &(jme->rxring[0]);
702 struct jme_buffer_info *rxbi = rxring->bufinf;
703 rxbi += i;
704
705 if (rxbi->skb) {
706 pci_unmap_page(jme->pdev,
707 rxbi->mapping,
708 rxbi->len,
709 PCI_DMA_FROMDEVICE);
710 dev_kfree_skb(rxbi->skb);
711 rxbi->skb = NULL;
712 rxbi->mapping = 0;
713 rxbi->len = 0;
714 }
715 }
716
717 static void
718 jme_free_rx_resources(struct jme_adapter *jme)
719 {
720 int i;
721 struct jme_ring *rxring = &(jme->rxring[0]);
722
723 if (rxring->alloc) {
724 for (i = 0 ; i < jme->rx_ring_size ; ++i)
725 jme_free_rx_buf(jme, i);
726
727 dma_free_coherent(&(jme->pdev->dev),
728 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
729 rxring->alloc,
730 rxring->dmaalloc);
731 rxring->alloc = NULL;
732 rxring->desc = NULL;
733 rxring->dmaalloc = 0;
734 rxring->dma = 0;
735 }
736 rxring->next_to_use = 0;
737 atomic_set(&rxring->next_to_clean, 0);
738 }
739
740 static int
741 jme_setup_rx_resources(struct jme_adapter *jme)
742 {
743 int i;
744 struct jme_ring *rxring = &(jme->rxring[0]);
745
746 rxring->alloc = dma_alloc_coherent(&(jme->pdev->dev),
747 RX_RING_ALLOC_SIZE(jme->rx_ring_size),
748 &(rxring->dmaalloc),
749 GFP_ATOMIC);
750 if (!rxring->alloc) {
751 rxring->desc = NULL;
752 rxring->dmaalloc = 0;
753 rxring->dma = 0;
754 return -ENOMEM;
755 }
756
757 /*
758 * 16 Bytes align
759 */
760 rxring->desc = (void *)ALIGN((unsigned long)(rxring->alloc),
761 RING_DESC_ALIGN);
762 rxring->dma = ALIGN(rxring->dmaalloc, RING_DESC_ALIGN);
763 rxring->next_to_use = 0;
764 atomic_set(&rxring->next_to_clean, 0);
765
766 /*
767 * Initiallize Receive Descriptors
768 */
769 for (i = 0 ; i < jme->rx_ring_size ; ++i) {
770 if (unlikely(jme_make_new_rx_buf(jme, i))) {
771 jme_free_rx_resources(jme);
772 return -ENOMEM;
773 }
774
775 jme_set_clean_rxdesc(jme, i);
776 }
777
778 return 0;
779 }
780
781 static inline void
782 jme_enable_rx_engine(struct jme_adapter *jme)
783 {
784 /*
785 * Select Queue 0
786 */
787 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
788 RXCS_QUEUESEL_Q0);
789 wmb();
790
791 /*
792 * Setup RX DMA Bass Address
793 */
794 jwrite32(jme, JME_RXDBA_LO, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
795 jwrite32(jme, JME_RXDBA_HI, (__u64)(jme->rxring[0].dma) >> 32);
796 jwrite32(jme, JME_RXNDA, (__u64)jme->rxring[0].dma & 0xFFFFFFFFUL);
797
798 /*
799 * Setup RX Descriptor Count
800 */
801 jwrite32(jme, JME_RXQDC, jme->rx_ring_size);
802
803 /*
804 * Setup Unicast Filter
805 */
806 jme_set_multi(jme->dev);
807
808 /*
809 * Enable RX Engine
810 */
811 wmb();
812 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
813 RXCS_QUEUESEL_Q0 |
814 RXCS_ENABLE |
815 RXCS_QST);
816 }
817
818 static inline void
819 jme_restart_rx_engine(struct jme_adapter *jme)
820 {
821 /*
822 * Start RX Engine
823 */
824 jwrite32(jme, JME_RXCS, jme->reg_rxcs |
825 RXCS_QUEUESEL_Q0 |
826 RXCS_ENABLE |
827 RXCS_QST);
828 }
829
830 static inline void
831 jme_disable_rx_engine(struct jme_adapter *jme)
832 {
833 int i;
834 u32 val;
835
836 /*
837 * Disable RX Engine
838 */
839 jwrite32(jme, JME_RXCS, jme->reg_rxcs);
840 wmb();
841
842 val = jread32(jme, JME_RXCS);
843 for (i = JME_RX_DISABLE_TIMEOUT ; (val & RXCS_ENABLE) && i > 0 ; --i) {
844 mdelay(1);
845 val = jread32(jme, JME_RXCS);
846 rmb();
847 }
848
849 if (!i)
850 jeprintk(jme->pdev, "Disable RX engine timeout.\n");
851
852 }
853
854 static int
855 jme_rxsum_ok(struct jme_adapter *jme, u16 flags)
856 {
857 if (!(flags & (RXWBFLAG_TCPON | RXWBFLAG_UDPON | RXWBFLAG_IPV4)))
858 return false;
859
860 if (unlikely(!(flags & RXWBFLAG_MF) &&
861 (flags & RXWBFLAG_TCPON) && !(flags & RXWBFLAG_TCPCS))) {
862 msg_rx_err(jme, "TCP Checksum error.\n");
863 goto out_sumerr;
864 }
865
866 if (unlikely(!(flags & RXWBFLAG_MF) &&
867 (flags & RXWBFLAG_UDPON) && !(flags & RXWBFLAG_UDPCS))) {
868 msg_rx_err(jme, "UDP Checksum error.\n");
869 goto out_sumerr;
870 }
871
872 if (unlikely((flags & RXWBFLAG_IPV4) && !(flags & RXWBFLAG_IPCS))) {
873 msg_rx_err(jme, "IPv4 Checksum error.\n");
874 goto out_sumerr;
875 }
876
877 return true;
878
879 out_sumerr:
880 return false;
881 }
882
883 static void
884 jme_alloc_and_feed_skb(struct jme_adapter *jme, int idx)
885 {
886 struct jme_ring *rxring = &(jme->rxring[0]);
887 struct rxdesc *rxdesc = rxring->desc;
888 struct jme_buffer_info *rxbi = rxring->bufinf;
889 struct sk_buff *skb;
890 int framesize;
891
892 rxdesc += idx;
893 rxbi += idx;
894
895 skb = rxbi->skb;
896 pci_dma_sync_single_for_cpu(jme->pdev,
897 rxbi->mapping,
898 rxbi->len,
899 PCI_DMA_FROMDEVICE);
900
901 if (unlikely(jme_make_new_rx_buf(jme, idx))) {
902 pci_dma_sync_single_for_device(jme->pdev,
903 rxbi->mapping,
904 rxbi->len,
905 PCI_DMA_FROMDEVICE);
906
907 ++(NET_STAT(jme).rx_dropped);
908 } else {
909 framesize = le16_to_cpu(rxdesc->descwb.framesize)
910 - RX_PREPAD_SIZE;
911
912 skb_reserve(skb, RX_PREPAD_SIZE);
913 skb_put(skb, framesize);
914 skb->protocol = eth_type_trans(skb, jme->dev);
915
916 if (jme_rxsum_ok(jme, le16_to_cpu(rxdesc->descwb.flags)))
917 skb->ip_summed = CHECKSUM_UNNECESSARY;
918 else
919 skb->ip_summed = CHECKSUM_NONE;
920
921 if (rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_TAGON)) {
922 if (jme->vlgrp) {
923 jme->jme_vlan_rx(skb, jme->vlgrp,
924 le16_to_cpu(rxdesc->descwb.vlan));
925 NET_STAT(jme).rx_bytes += 4;
926 }
927 } else {
928 jme->jme_rx(skb);
929 }
930
931 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_DEST)) ==
932 cpu_to_le16(RXWBFLAG_DEST_MUL))
933 ++(NET_STAT(jme).multicast);
934
935 NET_STAT(jme).rx_bytes += framesize;
936 ++(NET_STAT(jme).rx_packets);
937 }
938
939 jme_set_clean_rxdesc(jme, idx);
940
941 }
942
943 static int
944 jme_process_receive(struct jme_adapter *jme, int limit)
945 {
946 struct jme_ring *rxring = &(jme->rxring[0]);
947 struct rxdesc *rxdesc = rxring->desc;
948 int i, j, ccnt, desccnt, mask = jme->rx_ring_mask;
949
950 if (unlikely(!atomic_dec_and_test(&jme->rx_cleaning)))
951 goto out_inc;
952
953 if (unlikely(atomic_read(&jme->link_changing) != 1))
954 goto out_inc;
955
956 if (unlikely(!netif_carrier_ok(jme->dev)))
957 goto out_inc;
958
959 i = atomic_read(&rxring->next_to_clean);
960 while (limit > 0) {
961 rxdesc = rxring->desc;
962 rxdesc += i;
963
964 if ((rxdesc->descwb.flags & cpu_to_le16(RXWBFLAG_OWN)) ||
965 !(rxdesc->descwb.desccnt & RXWBDCNT_WBCPL))
966 goto out;
967 --limit;
968
969 desccnt = rxdesc->descwb.desccnt & RXWBDCNT_DCNT;
970
971 if (unlikely(desccnt > 1 ||
972 rxdesc->descwb.errstat & RXWBERR_ALLERR)) {
973
974 if (rxdesc->descwb.errstat & RXWBERR_CRCERR)
975 ++(NET_STAT(jme).rx_crc_errors);
976 else if (rxdesc->descwb.errstat & RXWBERR_OVERUN)
977 ++(NET_STAT(jme).rx_fifo_errors);
978 else
979 ++(NET_STAT(jme).rx_errors);
980
981 if (desccnt > 1)
982 limit -= desccnt - 1;
983
984 for (j = i, ccnt = desccnt ; ccnt-- ; ) {
985 jme_set_clean_rxdesc(jme, j);
986 j = (j + 1) & (mask);
987 }
988
989 } else {
990 jme_alloc_and_feed_skb(jme, i);
991 }
992
993 i = (i + desccnt) & (mask);
994 }
995
996 out:
997 atomic_set(&rxring->next_to_clean, i);
998
999 out_inc:
1000 atomic_inc(&jme->rx_cleaning);
1001
1002 return limit > 0 ? limit : 0;
1003
1004 }
1005
1006 static void
1007 jme_attempt_pcc(struct dynpcc_info *dpi, int atmp)
1008 {
1009 if (likely(atmp == dpi->cur)) {
1010 dpi->cnt = 0;
1011 return;
1012 }
1013
1014 if (dpi->attempt == atmp) {
1015 ++(dpi->cnt);
1016 } else {
1017 dpi->attempt = atmp;
1018 dpi->cnt = 0;
1019 }
1020
1021 }
1022
1023 static void
1024 jme_dynamic_pcc(struct jme_adapter *jme)
1025 {
1026 register struct dynpcc_info *dpi = &(jme->dpi);
1027
1028 if ((NET_STAT(jme).rx_bytes - dpi->last_bytes) > PCC_P3_THRESHOLD)
1029 jme_attempt_pcc(dpi, PCC_P3);
1030 else if ((NET_STAT(jme).rx_packets - dpi->last_pkts) > PCC_P2_THRESHOLD
1031 || dpi->intr_cnt > PCC_INTR_THRESHOLD)
1032 jme_attempt_pcc(dpi, PCC_P2);
1033 else
1034 jme_attempt_pcc(dpi, PCC_P1);
1035
1036 if (unlikely(dpi->attempt != dpi->cur && dpi->cnt > 5)) {
1037 if (dpi->attempt < dpi->cur)
1038 tasklet_schedule(&jme->rxclean_task);
1039 jme_set_rx_pcc(jme, dpi->attempt);
1040 dpi->cur = dpi->attempt;
1041 dpi->cnt = 0;
1042 }
1043 }
1044
1045 static void
1046 jme_start_pcc_timer(struct jme_adapter *jme)
1047 {
1048 struct dynpcc_info *dpi = &(jme->dpi);
1049 dpi->last_bytes = NET_STAT(jme).rx_bytes;
1050 dpi->last_pkts = NET_STAT(jme).rx_packets;
1051 dpi->intr_cnt = 0;
1052 jwrite32(jme, JME_TMCSR,
1053 TMCSR_EN | ((0xFFFFFF - PCC_INTERVAL_US) & TMCSR_CNT));
1054 }
1055
1056 static inline void
1057 jme_stop_pcc_timer(struct jme_adapter *jme)
1058 {
1059 jwrite32(jme, JME_TMCSR, 0);
1060 }
1061
1062 static void
1063 jme_shutdown_nic(struct jme_adapter *jme)
1064 {
1065 u32 phylink;
1066
1067 phylink = jme_linkstat_from_phy(jme);
1068
1069 if (!(phylink & PHY_LINK_UP)) {
1070 /*
1071 * Disable all interrupt before issue timer
1072 */
1073 jme_stop_irq(jme);
1074 jwrite32(jme, JME_TIMER2, TMCSR_EN | 0xFFFFFE);
1075 }
1076 }
1077
1078 static void
1079 jme_pcc_tasklet(unsigned long arg)
1080 {
1081 struct jme_adapter *jme = (struct jme_adapter *)arg;
1082 struct net_device *netdev = jme->dev;
1083
1084 if (unlikely(test_bit(JME_FLAG_SHUTDOWN, &jme->flags))) {
1085 jme_shutdown_nic(jme);
1086 return;
1087 }
1088
1089 if (unlikely(!netif_carrier_ok(netdev) ||
1090 (atomic_read(&jme->link_changing) != 1)
1091 )) {
1092 jme_stop_pcc_timer(jme);
1093 return;
1094 }
1095
1096 if (!(test_bit(JME_FLAG_POLL, &jme->flags)))
1097 jme_dynamic_pcc(jme);
1098
1099 jme_start_pcc_timer(jme);
1100 }
1101
1102 static inline void
1103 jme_polling_mode(struct jme_adapter *jme)
1104 {
1105 jme_set_rx_pcc(jme, PCC_OFF);
1106 }
1107
1108 static inline void
1109 jme_interrupt_mode(struct jme_adapter *jme)
1110 {
1111 jme_set_rx_pcc(jme, PCC_P1);
1112 }
1113
1114 static inline int
1115 jme_pseudo_hotplug_enabled(struct jme_adapter *jme)
1116 {
1117 u32 apmc;
1118 apmc = jread32(jme, JME_APMC);
1119 return apmc & JME_APMC_PSEUDO_HP_EN;
1120 }
1121
1122 static void
1123 jme_start_shutdown_timer(struct jme_adapter *jme)
1124 {
1125 u32 apmc;
1126
1127 apmc = jread32(jme, JME_APMC) | JME_APMC_PCIE_SD_EN;
1128 apmc &= ~JME_APMC_EPIEN_CTRL;
1129 if (!no_extplug) {
1130 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_EN);
1131 wmb();
1132 }
1133 jwrite32f(jme, JME_APMC, apmc);
1134
1135 jwrite32f(jme, JME_TIMER2, 0);
1136 set_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1137 jwrite32(jme, JME_TMCSR,
1138 TMCSR_EN | ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY) & TMCSR_CNT));
1139 }
1140
1141 static void
1142 jme_stop_shutdown_timer(struct jme_adapter *jme)
1143 {
1144 u32 apmc;
1145
1146 jwrite32f(jme, JME_TMCSR, 0);
1147 jwrite32f(jme, JME_TIMER2, 0);
1148 clear_bit(JME_FLAG_SHUTDOWN, &jme->flags);
1149
1150 apmc = jread32(jme, JME_APMC);
1151 apmc &= ~(JME_APMC_PCIE_SD_EN | JME_APMC_EPIEN_CTRL);
1152 jwrite32f(jme, JME_APMC, apmc | JME_APMC_EPIEN_CTRL_DIS);
1153 wmb();
1154 jwrite32f(jme, JME_APMC, apmc);
1155 }
1156
1157 static void
1158 jme_link_change_tasklet(unsigned long arg)
1159 {
1160 struct jme_adapter *jme = (struct jme_adapter *)arg;
1161 struct net_device *netdev = jme->dev;
1162 int rc;
1163
1164 while (!atomic_dec_and_test(&jme->link_changing)) {
1165 atomic_inc(&jme->link_changing);
1166 msg_intr(jme, "Get link change lock failed.\n");
1167 while (atomic_read(&jme->link_changing) != 1)
1168 msg_intr(jme, "Waiting link change lock.\n");
1169 }
1170
1171 if (jme_check_link(netdev, 1) && jme->old_mtu == netdev->mtu)
1172 goto out;
1173
1174 jme->old_mtu = netdev->mtu;
1175 netif_stop_queue(netdev);
1176 if (jme_pseudo_hotplug_enabled(jme))
1177 jme_stop_shutdown_timer(jme);
1178
1179 jme_stop_pcc_timer(jme);
1180 tasklet_disable(&jme->txclean_task);
1181 tasklet_disable(&jme->rxclean_task);
1182 tasklet_disable(&jme->rxempty_task);
1183
1184 if (netif_carrier_ok(netdev)) {
1185 jme_reset_ghc_speed(jme);
1186 jme_disable_rx_engine(jme);
1187 jme_disable_tx_engine(jme);
1188 jme_reset_mac_processor(jme);
1189 jme_free_rx_resources(jme);
1190 jme_free_tx_resources(jme);
1191
1192 if (test_bit(JME_FLAG_POLL, &jme->flags))
1193 jme_polling_mode(jme);
1194
1195 netif_carrier_off(netdev);
1196 }
1197
1198 jme_check_link(netdev, 0);
1199 if (netif_carrier_ok(netdev)) {
1200 rc = jme_setup_rx_resources(jme);
1201 if (rc) {
1202 jeprintk(jme->pdev, "Allocating resources for RX error"
1203 ", Device STOPPED!\n");
1204 goto out_enable_tasklet;
1205 }
1206
1207 rc = jme_setup_tx_resources(jme);
1208 if (rc) {
1209 jeprintk(jme->pdev, "Allocating resources for TX error"
1210 ", Device STOPPED!\n");
1211 goto err_out_free_rx_resources;
1212 }
1213
1214 jme_enable_rx_engine(jme);
1215 jme_enable_tx_engine(jme);
1216
1217 netif_start_queue(netdev);
1218
1219 if (test_bit(JME_FLAG_POLL, &jme->flags))
1220 jme_interrupt_mode(jme);
1221
1222 jme_start_pcc_timer(jme);
1223 } else if (jme_pseudo_hotplug_enabled(jme)) {
1224 jme_start_shutdown_timer(jme);
1225 }
1226
1227 goto out_enable_tasklet;
1228
1229 err_out_free_rx_resources:
1230 jme_free_rx_resources(jme);
1231 out_enable_tasklet:
1232 tasklet_enable(&jme->txclean_task);
1233 tasklet_hi_enable(&jme->rxclean_task);
1234 tasklet_hi_enable(&jme->rxempty_task);
1235 out:
1236 atomic_inc(&jme->link_changing);
1237 }
1238
1239 static void
1240 jme_rx_clean_tasklet(unsigned long arg)
1241 {
1242 struct jme_adapter *jme = (struct jme_adapter *)arg;
1243 struct dynpcc_info *dpi = &(jme->dpi);
1244
1245 jme_process_receive(jme, jme->rx_ring_size);
1246 ++(dpi->intr_cnt);
1247
1248 }
1249
1250 static int
1251 jme_poll(JME_NAPI_HOLDER(holder), JME_NAPI_WEIGHT(budget))
1252 {
1253 struct jme_adapter *jme = jme_napi_priv(holder);
1254 int rest;
1255
1256 rest = jme_process_receive(jme, JME_NAPI_WEIGHT_VAL(budget));
1257
1258 while (atomic_read(&jme->rx_empty) > 0) {
1259 atomic_dec(&jme->rx_empty);
1260 ++(NET_STAT(jme).rx_dropped);
1261 jme_restart_rx_engine(jme);
1262 }
1263 atomic_inc(&jme->rx_empty);
1264
1265 if (rest) {
1266 JME_RX_COMPLETE(netdev, holder);
1267 jme_interrupt_mode(jme);
1268 }
1269
1270 JME_NAPI_WEIGHT_SET(budget, rest);
1271 return JME_NAPI_WEIGHT_VAL(budget) - rest;
1272 }
1273
1274 static void
1275 jme_rx_empty_tasklet(unsigned long arg)
1276 {
1277 struct jme_adapter *jme = (struct jme_adapter *)arg;
1278
1279 if (unlikely(atomic_read(&jme->link_changing) != 1))
1280 return;
1281
1282 if (unlikely(!netif_carrier_ok(jme->dev)))
1283 return;
1284
1285 msg_rx_status(jme, "RX Queue Full!\n");
1286
1287 jme_rx_clean_tasklet(arg);
1288
1289 while (atomic_read(&jme->rx_empty) > 0) {
1290 atomic_dec(&jme->rx_empty);
1291 ++(NET_STAT(jme).rx_dropped);
1292 jme_restart_rx_engine(jme);
1293 }
1294 atomic_inc(&jme->rx_empty);
1295 }
1296
1297 static void
1298 jme_wake_queue_if_stopped(struct jme_adapter *jme)
1299 {
1300 struct jme_ring *txring = jme->txring;
1301
1302 smp_wmb();
1303 if (unlikely(netif_queue_stopped(jme->dev) &&
1304 atomic_read(&txring->nr_free) >= (jme->tx_wake_threshold))) {
1305 msg_tx_done(jme, "TX Queue Waked.\n");
1306 netif_wake_queue(jme->dev);
1307 }
1308
1309 }
1310
1311 static void
1312 jme_tx_clean_tasklet(unsigned long arg)
1313 {
1314 struct jme_adapter *jme = (struct jme_adapter *)arg;
1315 struct jme_ring *txring = &(jme->txring[0]);
1316 struct txdesc *txdesc = txring->desc;
1317 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi, *ttxbi;
1318 int i, j, cnt = 0, max, err, mask;
1319
1320 tx_dbg(jme, "Into txclean.\n");
1321
1322 if (unlikely(!atomic_dec_and_test(&jme->tx_cleaning)))
1323 goto out;
1324
1325 if (unlikely(atomic_read(&jme->link_changing) != 1))
1326 goto out;
1327
1328 if (unlikely(!netif_carrier_ok(jme->dev)))
1329 goto out;
1330
1331 max = jme->tx_ring_size - atomic_read(&txring->nr_free);
1332 mask = jme->tx_ring_mask;
1333
1334 for (i = atomic_read(&txring->next_to_clean) ; cnt < max ; ) {
1335
1336 ctxbi = txbi + i;
1337
1338 if (likely(ctxbi->skb &&
1339 !(txdesc[i].descwb.flags & TXWBFLAG_OWN))) {
1340
1341 tx_dbg(jme, "txclean: %d+%d@%lu\n",
1342 i, ctxbi->nr_desc, jiffies);
1343
1344 err = txdesc[i].descwb.flags & TXWBFLAG_ALLERR;
1345
1346 for (j = 1 ; j < ctxbi->nr_desc ; ++j) {
1347 ttxbi = txbi + ((i + j) & (mask));
1348 txdesc[(i + j) & (mask)].dw[0] = 0;
1349
1350 pci_unmap_page(jme->pdev,
1351 ttxbi->mapping,
1352 ttxbi->len,
1353 PCI_DMA_TODEVICE);
1354
1355 ttxbi->mapping = 0;
1356 ttxbi->len = 0;
1357 }
1358
1359 dev_kfree_skb(ctxbi->skb);
1360
1361 cnt += ctxbi->nr_desc;
1362
1363 if (unlikely(err)) {
1364 ++(NET_STAT(jme).tx_carrier_errors);
1365 } else {
1366 ++(NET_STAT(jme).tx_packets);
1367 NET_STAT(jme).tx_bytes += ctxbi->len;
1368 }
1369
1370 ctxbi->skb = NULL;
1371 ctxbi->len = 0;
1372 ctxbi->start_xmit = 0;
1373
1374 } else {
1375 break;
1376 }
1377
1378 i = (i + ctxbi->nr_desc) & mask;
1379
1380 ctxbi->nr_desc = 0;
1381 }
1382
1383 tx_dbg(jme, "txclean: done %d@%lu.\n", i, jiffies);
1384 atomic_set(&txring->next_to_clean, i);
1385 atomic_add(cnt, &txring->nr_free);
1386
1387 jme_wake_queue_if_stopped(jme);
1388
1389 out:
1390 atomic_inc(&jme->tx_cleaning);
1391 }
1392
1393 static void
1394 jme_intr_msi(struct jme_adapter *jme, u32 intrstat)
1395 {
1396 /*
1397 * Disable interrupt
1398 */
1399 jwrite32f(jme, JME_IENC, INTR_ENABLE);
1400
1401 if (intrstat & (INTR_LINKCH | INTR_SWINTR)) {
1402 /*
1403 * Link change event is critical
1404 * all other events are ignored
1405 */
1406 jwrite32(jme, JME_IEVE, intrstat);
1407 tasklet_schedule(&jme->linkch_task);
1408 goto out_reenable;
1409 }
1410
1411 if (intrstat & INTR_TMINTR) {
1412 jwrite32(jme, JME_IEVE, INTR_TMINTR);
1413 tasklet_schedule(&jme->pcc_task);
1414 }
1415
1416 if (intrstat & (INTR_PCCTXTO | INTR_PCCTX)) {
1417 jwrite32(jme, JME_IEVE, INTR_PCCTXTO | INTR_PCCTX | INTR_TX0);
1418 tasklet_schedule(&jme->txclean_task);
1419 }
1420
1421 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1422 jwrite32(jme, JME_IEVE, (intrstat & (INTR_PCCRX0TO |
1423 INTR_PCCRX0 |
1424 INTR_RX0EMP)) |
1425 INTR_RX0);
1426 }
1427
1428 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
1429 if (intrstat & INTR_RX0EMP)
1430 atomic_inc(&jme->rx_empty);
1431
1432 if ((intrstat & (INTR_PCCRX0TO | INTR_PCCRX0 | INTR_RX0EMP))) {
1433 if (likely(JME_RX_SCHEDULE_PREP(jme))) {
1434 jme_polling_mode(jme);
1435 JME_RX_SCHEDULE(jme);
1436 }
1437 }
1438 } else {
1439 if (intrstat & INTR_RX0EMP) {
1440 atomic_inc(&jme->rx_empty);
1441 tasklet_hi_schedule(&jme->rxempty_task);
1442 } else if (intrstat & (INTR_PCCRX0TO | INTR_PCCRX0)) {
1443 tasklet_hi_schedule(&jme->rxclean_task);
1444 }
1445 }
1446
1447 out_reenable:
1448 /*
1449 * Re-enable interrupt
1450 */
1451 jwrite32f(jme, JME_IENS, INTR_ENABLE);
1452 }
1453
1454 static irqreturn_t
1455 jme_intr(int irq, void *dev_id)
1456 {
1457 struct net_device *netdev = dev_id;
1458 struct jme_adapter *jme = netdev_priv(netdev);
1459 u32 intrstat;
1460
1461 intrstat = jread32(jme, JME_IEVE);
1462
1463 /*
1464 * Check if it's really an interrupt for us
1465 */
1466 if (unlikely((intrstat & INTR_ENABLE) == 0))
1467 return IRQ_NONE;
1468
1469 /*
1470 * Check if the device still exist
1471 */
1472 if (unlikely(intrstat == ~((typeof(intrstat))0)))
1473 return IRQ_NONE;
1474
1475 jme_intr_msi(jme, intrstat);
1476
1477 return IRQ_HANDLED;
1478 }
1479
1480 static irqreturn_t
1481 jme_msi(int irq, void *dev_id)
1482 {
1483 struct net_device *netdev = dev_id;
1484 struct jme_adapter *jme = netdev_priv(netdev);
1485 u32 intrstat;
1486
1487 pci_dma_sync_single_for_cpu(jme->pdev,
1488 jme->shadow_dma,
1489 sizeof(u32) * SHADOW_REG_NR,
1490 PCI_DMA_FROMDEVICE);
1491 intrstat = jme->shadow_regs[SHADOW_IEVE];
1492 jme->shadow_regs[SHADOW_IEVE] = 0;
1493
1494 jme_intr_msi(jme, intrstat);
1495
1496 return IRQ_HANDLED;
1497 }
1498
1499 static void
1500 jme_reset_link(struct jme_adapter *jme)
1501 {
1502 jwrite32(jme, JME_TMCSR, TMCSR_SWIT);
1503 }
1504
1505 static void
1506 jme_restart_an(struct jme_adapter *jme)
1507 {
1508 u32 bmcr;
1509
1510 spin_lock_bh(&jme->phy_lock);
1511 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1512 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
1513 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, bmcr);
1514 spin_unlock_bh(&jme->phy_lock);
1515 }
1516
1517 static int
1518 jme_request_irq(struct jme_adapter *jme)
1519 {
1520 int rc;
1521 struct net_device *netdev = jme->dev;
1522 irq_handler_t handler = jme_intr;
1523 int irq_flags = IRQF_SHARED;
1524
1525 if (!pci_enable_msi(jme->pdev)) {
1526 set_bit(JME_FLAG_MSI, &jme->flags);
1527 handler = jme_msi;
1528 irq_flags = 0;
1529 }
1530
1531 rc = request_irq(jme->pdev->irq, handler, irq_flags, netdev->name,
1532 netdev);
1533 if (rc) {
1534 jeprintk(jme->pdev,
1535 "Unable to request %s interrupt (return: %d)\n",
1536 test_bit(JME_FLAG_MSI, &jme->flags) ? "MSI" : "INTx",
1537 rc);
1538
1539 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1540 pci_disable_msi(jme->pdev);
1541 clear_bit(JME_FLAG_MSI, &jme->flags);
1542 }
1543 } else {
1544 netdev->irq = jme->pdev->irq;
1545 }
1546
1547 return rc;
1548 }
1549
1550 static void
1551 jme_free_irq(struct jme_adapter *jme)
1552 {
1553 free_irq(jme->pdev->irq, jme->dev);
1554 if (test_bit(JME_FLAG_MSI, &jme->flags)) {
1555 pci_disable_msi(jme->pdev);
1556 clear_bit(JME_FLAG_MSI, &jme->flags);
1557 jme->dev->irq = jme->pdev->irq;
1558 }
1559 }
1560
1561 static int
1562 jme_open(struct net_device *netdev)
1563 {
1564 struct jme_adapter *jme = netdev_priv(netdev);
1565 int rc;
1566
1567 jme_clear_pm(jme);
1568 JME_NAPI_ENABLE(jme);
1569
1570 tasklet_enable(&jme->txclean_task);
1571 tasklet_hi_enable(&jme->rxclean_task);
1572 tasklet_hi_enable(&jme->rxempty_task);
1573
1574 rc = jme_request_irq(jme);
1575 if (rc)
1576 goto err_out;
1577
1578 jme_enable_shadow(jme);
1579 jme_start_irq(jme);
1580
1581 if (test_bit(JME_FLAG_SSET, &jme->flags))
1582 jme_set_settings(netdev, &jme->old_ecmd);
1583 else
1584 jme_reset_phy_processor(jme);
1585
1586 jme_reset_link(jme);
1587
1588 return 0;
1589
1590 err_out:
1591 netif_stop_queue(netdev);
1592 netif_carrier_off(netdev);
1593 return rc;
1594 }
1595
1596 #ifdef CONFIG_PM
1597 static void
1598 jme_set_100m_half(struct jme_adapter *jme)
1599 {
1600 u32 bmcr, tmp;
1601
1602 bmcr = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_BMCR);
1603 tmp = bmcr & ~(BMCR_ANENABLE | BMCR_SPEED100 |
1604 BMCR_SPEED1000 | BMCR_FULLDPLX);
1605 tmp |= BMCR_SPEED100;
1606
1607 if (bmcr != tmp)
1608 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, tmp);
1609
1610 if (jme->fpgaver)
1611 jwrite32(jme, JME_GHC, GHC_SPEED_100M | GHC_LINK_POLL);
1612 else
1613 jwrite32(jme, JME_GHC, GHC_SPEED_100M);
1614 }
1615
1616 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1617 static void
1618 jme_wait_link(struct jme_adapter *jme)
1619 {
1620 u32 phylink, to = JME_WAIT_LINK_TIME;
1621
1622 mdelay(1000);
1623 phylink = jme_linkstat_from_phy(jme);
1624 while (!(phylink & PHY_LINK_UP) && (to -= 10) > 0) {
1625 mdelay(10);
1626 phylink = jme_linkstat_from_phy(jme);
1627 }
1628 }
1629 #endif
1630
1631 static inline void
1632 jme_phy_off(struct jme_adapter *jme)
1633 {
1634 jme_mdio_write(jme->dev, jme->mii_if.phy_id, MII_BMCR, BMCR_PDOWN);
1635 }
1636
1637 static int
1638 jme_close(struct net_device *netdev)
1639 {
1640 struct jme_adapter *jme = netdev_priv(netdev);
1641
1642 netif_stop_queue(netdev);
1643 netif_carrier_off(netdev);
1644
1645 jme_stop_irq(jme);
1646 jme_disable_shadow(jme);
1647 jme_free_irq(jme);
1648
1649 JME_NAPI_DISABLE(jme);
1650
1651 tasklet_kill(&jme->linkch_task);
1652 tasklet_kill(&jme->txclean_task);
1653 tasklet_kill(&jme->rxclean_task);
1654 tasklet_kill(&jme->rxempty_task);
1655
1656 jme_reset_ghc_speed(jme);
1657 jme_disable_rx_engine(jme);
1658 jme_disable_tx_engine(jme);
1659 jme_reset_mac_processor(jme);
1660 jme_free_rx_resources(jme);
1661 jme_free_tx_resources(jme);
1662 jme->phylink = 0;
1663 jme_phy_off(jme);
1664
1665 return 0;
1666 }
1667
1668 static int
1669 jme_alloc_txdesc(struct jme_adapter *jme,
1670 struct sk_buff *skb)
1671 {
1672 struct jme_ring *txring = jme->txring;
1673 int idx, nr_alloc, mask = jme->tx_ring_mask;
1674
1675 idx = txring->next_to_use;
1676 nr_alloc = skb_shinfo(skb)->nr_frags + 2;
1677
1678 if (unlikely(atomic_read(&txring->nr_free) < nr_alloc))
1679 return -1;
1680
1681 atomic_sub(nr_alloc, &txring->nr_free);
1682
1683 txring->next_to_use = (txring->next_to_use + nr_alloc) & mask;
1684
1685 return idx;
1686 }
1687
1688 static void
1689 jme_fill_tx_map(struct pci_dev *pdev,
1690 struct txdesc *txdesc,
1691 struct jme_buffer_info *txbi,
1692 struct page *page,
1693 u32 page_offset,
1694 u32 len,
1695 u8 hidma)
1696 {
1697 dma_addr_t dmaaddr;
1698
1699 dmaaddr = pci_map_page(pdev,
1700 page,
1701 page_offset,
1702 len,
1703 PCI_DMA_TODEVICE);
1704
1705 pci_dma_sync_single_for_device(pdev,
1706 dmaaddr,
1707 len,
1708 PCI_DMA_TODEVICE);
1709
1710 txdesc->dw[0] = 0;
1711 txdesc->dw[1] = 0;
1712 txdesc->desc2.flags = TXFLAG_OWN;
1713 txdesc->desc2.flags |= (hidma) ? TXFLAG_64BIT : 0;
1714 txdesc->desc2.datalen = cpu_to_le16(len);
1715 txdesc->desc2.bufaddrh = cpu_to_le32((__u64)dmaaddr >> 32);
1716 txdesc->desc2.bufaddrl = cpu_to_le32(
1717 (__u64)dmaaddr & 0xFFFFFFFFUL);
1718
1719 txbi->mapping = dmaaddr;
1720 txbi->len = len;
1721 }
1722
1723 static void
1724 jme_map_tx_skb(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1725 {
1726 struct jme_ring *txring = jme->txring;
1727 struct txdesc *txdesc = txring->desc, *ctxdesc;
1728 struct jme_buffer_info *txbi = txring->bufinf, *ctxbi;
1729 u8 hidma = jme->dev->features & NETIF_F_HIGHDMA;
1730 int i, nr_frags = skb_shinfo(skb)->nr_frags;
1731 int mask = jme->tx_ring_mask;
1732 struct skb_frag_struct *frag;
1733 u32 len;
1734
1735 for (i = 0 ; i < nr_frags ; ++i) {
1736 frag = &skb_shinfo(skb)->frags[i];
1737 ctxdesc = txdesc + ((idx + i + 2) & (mask));
1738 ctxbi = txbi + ((idx + i + 2) & (mask));
1739
1740 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, frag->page,
1741 frag->page_offset, frag->size, hidma);
1742 }
1743
1744 len = skb_is_nonlinear(skb) ? skb_headlen(skb) : skb->len;
1745 ctxdesc = txdesc + ((idx + 1) & (mask));
1746 ctxbi = txbi + ((idx + 1) & (mask));
1747 jme_fill_tx_map(jme->pdev, ctxdesc, ctxbi, virt_to_page(skb->data),
1748 offset_in_page(skb->data), len, hidma);
1749
1750 }
1751
1752 static int
1753 jme_expand_header(struct jme_adapter *jme, struct sk_buff *skb)
1754 {
1755 if (unlikely(skb_shinfo(skb)->gso_size &&
1756 skb_header_cloned(skb) &&
1757 pskb_expand_head(skb, 0, 0, GFP_ATOMIC))) {
1758 dev_kfree_skb(skb);
1759 return -1;
1760 }
1761
1762 return 0;
1763 }
1764
1765 static int
1766 jme_tx_tso(struct sk_buff *skb, __le16 *mss, u8 *flags)
1767 {
1768 *mss = cpu_to_le16(skb_shinfo(skb)->gso_size << TXDESC_MSS_SHIFT);
1769 if (*mss) {
1770 *flags |= TXFLAG_LSEN;
1771
1772 if (skb->protocol == htons(ETH_P_IP)) {
1773 struct iphdr *iph = ip_hdr(skb);
1774
1775 iph->check = 0;
1776 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1777 iph->daddr, 0,
1778 IPPROTO_TCP,
1779 0);
1780 } else {
1781 struct ipv6hdr *ip6h = ipv6_hdr(skb);
1782
1783 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ip6h->saddr,
1784 &ip6h->daddr, 0,
1785 IPPROTO_TCP,
1786 0);
1787 }
1788
1789 return 0;
1790 }
1791
1792 return 1;
1793 }
1794
1795 static void
1796 jme_tx_csum(struct jme_adapter *jme, struct sk_buff *skb, u8 *flags)
1797 {
1798 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1799 u8 ip_proto;
1800
1801 switch (skb->protocol) {
1802 case htons(ETH_P_IP):
1803 ip_proto = ip_hdr(skb)->protocol;
1804 break;
1805 case htons(ETH_P_IPV6):
1806 ip_proto = ipv6_hdr(skb)->nexthdr;
1807 break;
1808 default:
1809 ip_proto = 0;
1810 break;
1811 }
1812
1813 switch (ip_proto) {
1814 case IPPROTO_TCP:
1815 *flags |= TXFLAG_TCPCS;
1816 break;
1817 case IPPROTO_UDP:
1818 *flags |= TXFLAG_UDPCS;
1819 break;
1820 default:
1821 msg_tx_err(jme, "Error upper layer protocol.\n");
1822 break;
1823 }
1824 }
1825 }
1826
1827 static inline void
1828 jme_tx_vlan(struct sk_buff *skb, __le16 *vlan, u8 *flags)
1829 {
1830 if (vlan_tx_tag_present(skb)) {
1831 *flags |= TXFLAG_TAGON;
1832 *vlan = cpu_to_le16(vlan_tx_tag_get(skb));
1833 }
1834 }
1835
1836 static int
1837 jme_fill_first_tx_desc(struct jme_adapter *jme, struct sk_buff *skb, int idx)
1838 {
1839 struct jme_ring *txring = jme->txring;
1840 struct txdesc *txdesc;
1841 struct jme_buffer_info *txbi;
1842 u8 flags;
1843
1844 txdesc = (struct txdesc *)txring->desc + idx;
1845 txbi = txring->bufinf + idx;
1846
1847 txdesc->dw[0] = 0;
1848 txdesc->dw[1] = 0;
1849 txdesc->dw[2] = 0;
1850 txdesc->dw[3] = 0;
1851 txdesc->desc1.pktsize = cpu_to_le16(skb->len);
1852 /*
1853 * Set OWN bit at final.
1854 * When kernel transmit faster than NIC.
1855 * And NIC trying to send this descriptor before we tell
1856 * it to start sending this TX queue.
1857 * Other fields are already filled correctly.
1858 */
1859 wmb();
1860 flags = TXFLAG_OWN | TXFLAG_INT;
1861 /*
1862 * Set checksum flags while not tso
1863 */
1864 if (jme_tx_tso(skb, &txdesc->desc1.mss, &flags))
1865 jme_tx_csum(jme, skb, &flags);
1866 jme_tx_vlan(skb, &txdesc->desc1.vlan, &flags);
1867 txdesc->desc1.flags = flags;
1868 /*
1869 * Set tx buffer info after telling NIC to send
1870 * For better tx_clean timing
1871 */
1872 wmb();
1873 txbi->nr_desc = skb_shinfo(skb)->nr_frags + 2;
1874 txbi->skb = skb;
1875 txbi->len = skb->len;
1876 txbi->start_xmit = jiffies;
1877 if (!txbi->start_xmit)
1878 txbi->start_xmit = (0UL-1);
1879
1880 return 0;
1881 }
1882
1883 static void
1884 jme_stop_queue_if_full(struct jme_adapter *jme)
1885 {
1886 struct jme_ring *txring = jme->txring;
1887 struct jme_buffer_info *txbi = txring->bufinf;
1888 int idx = atomic_read(&txring->next_to_clean);
1889
1890 txbi += idx;
1891
1892 smp_wmb();
1893 if (unlikely(atomic_read(&txring->nr_free) < (MAX_SKB_FRAGS+2))) {
1894 netif_stop_queue(jme->dev);
1895 msg_tx_queued(jme, "TX Queue Paused.\n");
1896 smp_wmb();
1897 if (atomic_read(&txring->nr_free)
1898 >= (jme->tx_wake_threshold)) {
1899 netif_wake_queue(jme->dev);
1900 msg_tx_queued(jme, "TX Queue Fast Waked.\n");
1901 }
1902 }
1903
1904 if (unlikely(txbi->start_xmit &&
1905 (jiffies - txbi->start_xmit) >= TX_TIMEOUT &&
1906 txbi->skb)) {
1907 netif_stop_queue(jme->dev);
1908 msg_tx_queued(jme, "TX Queue Stopped %d@%lu.\n", idx, jiffies);
1909 }
1910 }
1911
1912 /*
1913 * This function is already protected by netif_tx_lock()
1914 */
1915
1916 static int
1917 jme_start_xmit(struct sk_buff *skb, struct net_device *netdev)
1918 {
1919 struct jme_adapter *jme = netdev_priv(netdev);
1920 int idx;
1921
1922 if (unlikely(jme_expand_header(jme, skb))) {
1923 ++(NET_STAT(jme).tx_dropped);
1924 return NETDEV_TX_OK;
1925 }
1926
1927 idx = jme_alloc_txdesc(jme, skb);
1928
1929 if (unlikely(idx < 0)) {
1930 netif_stop_queue(netdev);
1931 msg_tx_err(jme, "BUG! Tx ring full when queue awake!\n");
1932
1933 return NETDEV_TX_BUSY;
1934 }
1935
1936 jme_map_tx_skb(jme, skb, idx);
1937 jme_fill_first_tx_desc(jme, skb, idx);
1938
1939 jwrite32(jme, JME_TXCS, jme->reg_txcs |
1940 TXCS_SELECT_QUEUE0 |
1941 TXCS_QUEUE0S |
1942 TXCS_ENABLE);
1943 netdev->trans_start = jiffies;
1944
1945 tx_dbg(jme, "xmit: %d+%d@%lu\n", idx,
1946 skb_shinfo(skb)->nr_frags + 2,
1947 jiffies);
1948 jme_stop_queue_if_full(jme);
1949
1950 return NETDEV_TX_OK;
1951 }
1952
1953 static int
1954 jme_set_macaddr(struct net_device *netdev, void *p)
1955 {
1956 struct jme_adapter *jme = netdev_priv(netdev);
1957 struct sockaddr *addr = p;
1958 u32 val;
1959
1960 if (netif_running(netdev))
1961 return -EBUSY;
1962
1963 spin_lock_bh(&jme->macaddr_lock);
1964 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1965
1966 val = (addr->sa_data[3] & 0xff) << 24 |
1967 (addr->sa_data[2] & 0xff) << 16 |
1968 (addr->sa_data[1] & 0xff) << 8 |
1969 (addr->sa_data[0] & 0xff);
1970 jwrite32(jme, JME_RXUMA_LO, val);
1971 val = (addr->sa_data[5] & 0xff) << 8 |
1972 (addr->sa_data[4] & 0xff);
1973 jwrite32(jme, JME_RXUMA_HI, val);
1974 spin_unlock_bh(&jme->macaddr_lock);
1975
1976 return 0;
1977 }
1978
1979 static void
1980 jme_set_multi(struct net_device *netdev)
1981 {
1982 struct jme_adapter *jme = netdev_priv(netdev);
1983 u32 mc_hash[2] = {};
1984 int i;
1985
1986 spin_lock_bh(&jme->rxmcs_lock);
1987
1988 jme->reg_rxmcs |= RXMCS_BRDFRAME | RXMCS_UNIFRAME;
1989
1990 if (netdev->flags & IFF_PROMISC) {
1991 jme->reg_rxmcs |= RXMCS_ALLFRAME;
1992 } else if (netdev->flags & IFF_ALLMULTI) {
1993 jme->reg_rxmcs |= RXMCS_ALLMULFRAME;
1994 } else if (netdev->flags & IFF_MULTICAST) {
1995 struct dev_mc_list *mclist;
1996 int bit_nr;
1997
1998 jme->reg_rxmcs |= RXMCS_MULFRAME | RXMCS_MULFILTERED;
1999 for (i = 0, mclist = netdev->mc_list;
2000 mclist && i < netdev->mc_count;
2001 ++i, mclist = mclist->next) {
2002
2003 bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3F;
2004 mc_hash[bit_nr >> 5] |= 1 << (bit_nr & 0x1F);
2005 }
2006
2007 jwrite32(jme, JME_RXMCHT_LO, mc_hash[0]);
2008 jwrite32(jme, JME_RXMCHT_HI, mc_hash[1]);
2009 }
2010
2011 wmb();
2012 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2013
2014 spin_unlock_bh(&jme->rxmcs_lock);
2015 }
2016
2017 static int
2018 jme_change_mtu(struct net_device *netdev, int new_mtu)
2019 {
2020 struct jme_adapter *jme = netdev_priv(netdev);
2021
2022 if (new_mtu == jme->old_mtu)
2023 return 0;
2024
2025 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
2026 ((new_mtu) < IPV6_MIN_MTU))
2027 return -EINVAL;
2028
2029 if (new_mtu > 4000) {
2030 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2031 jme->reg_rxcs |= RXCS_FIFOTHNP_64QW;
2032 jme_restart_rx_engine(jme);
2033 } else {
2034 jme->reg_rxcs &= ~RXCS_FIFOTHNP;
2035 jme->reg_rxcs |= RXCS_FIFOTHNP_128QW;
2036 jme_restart_rx_engine(jme);
2037 }
2038
2039 if (new_mtu > 1900) {
2040 netdev->features &= ~(NETIF_F_HW_CSUM |
2041 NETIF_F_TSO |
2042 NETIF_F_TSO6);
2043 } else {
2044 if (test_bit(JME_FLAG_TXCSUM, &jme->flags))
2045 netdev->features |= NETIF_F_HW_CSUM;
2046 if (test_bit(JME_FLAG_TSO, &jme->flags))
2047 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2048 }
2049
2050 netdev->mtu = new_mtu;
2051 jme_reset_link(jme);
2052
2053 return 0;
2054 }
2055
2056 static void
2057 jme_tx_timeout(struct net_device *netdev)
2058 {
2059 struct jme_adapter *jme = netdev_priv(netdev);
2060
2061 jme->phylink = 0;
2062 jme_reset_phy_processor(jme);
2063 if (test_bit(JME_FLAG_SSET, &jme->flags))
2064 jme_set_settings(netdev, &jme->old_ecmd);
2065
2066 /*
2067 * Force to Reset the link again
2068 */
2069 jme_reset_link(jme);
2070 }
2071
2072 static void
2073 jme_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
2074 {
2075 struct jme_adapter *jme = netdev_priv(netdev);
2076
2077 jme->vlgrp = grp;
2078 }
2079
2080 static void
2081 jme_get_drvinfo(struct net_device *netdev,
2082 struct ethtool_drvinfo *info)
2083 {
2084 struct jme_adapter *jme = netdev_priv(netdev);
2085
2086 strcpy(info->driver, DRV_NAME);
2087 strcpy(info->version, DRV_VERSION);
2088 strcpy(info->bus_info, pci_name(jme->pdev));
2089 }
2090
2091 static int
2092 jme_get_regs_len(struct net_device *netdev)
2093 {
2094 return JME_REG_LEN;
2095 }
2096
2097 static void
2098 mmapio_memcpy(struct jme_adapter *jme, u32 *p, u32 reg, int len)
2099 {
2100 int i;
2101
2102 for (i = 0 ; i < len ; i += 4)
2103 p[i >> 2] = jread32(jme, reg + i);
2104 }
2105
2106 static void
2107 mdio_memcpy(struct jme_adapter *jme, u32 *p, int reg_nr)
2108 {
2109 int i;
2110 u16 *p16 = (u16 *)p;
2111
2112 for (i = 0 ; i < reg_nr ; ++i)
2113 p16[i] = jme_mdio_read(jme->dev, jme->mii_if.phy_id, i);
2114 }
2115
2116 static void
2117 jme_get_regs(struct net_device *netdev, struct ethtool_regs *regs, void *p)
2118 {
2119 struct jme_adapter *jme = netdev_priv(netdev);
2120 u32 *p32 = (u32 *)p;
2121
2122 memset(p, 0xFF, JME_REG_LEN);
2123
2124 regs->version = 1;
2125 mmapio_memcpy(jme, p32, JME_MAC, JME_MAC_LEN);
2126
2127 p32 += 0x100 >> 2;
2128 mmapio_memcpy(jme, p32, JME_PHY, JME_PHY_LEN);
2129
2130 p32 += 0x100 >> 2;
2131 mmapio_memcpy(jme, p32, JME_MISC, JME_MISC_LEN);
2132
2133 p32 += 0x100 >> 2;
2134 mmapio_memcpy(jme, p32, JME_RSS, JME_RSS_LEN);
2135
2136 p32 += 0x100 >> 2;
2137 mdio_memcpy(jme, p32, JME_PHY_REG_NR);
2138 }
2139
2140 static int
2141 jme_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2142 {
2143 struct jme_adapter *jme = netdev_priv(netdev);
2144
2145 ecmd->tx_coalesce_usecs = PCC_TX_TO;
2146 ecmd->tx_max_coalesced_frames = PCC_TX_CNT;
2147
2148 if (test_bit(JME_FLAG_POLL, &jme->flags)) {
2149 ecmd->use_adaptive_rx_coalesce = false;
2150 ecmd->rx_coalesce_usecs = 0;
2151 ecmd->rx_max_coalesced_frames = 0;
2152 return 0;
2153 }
2154
2155 ecmd->use_adaptive_rx_coalesce = true;
2156
2157 switch (jme->dpi.cur) {
2158 case PCC_P1:
2159 ecmd->rx_coalesce_usecs = PCC_P1_TO;
2160 ecmd->rx_max_coalesced_frames = PCC_P1_CNT;
2161 break;
2162 case PCC_P2:
2163 ecmd->rx_coalesce_usecs = PCC_P2_TO;
2164 ecmd->rx_max_coalesced_frames = PCC_P2_CNT;
2165 break;
2166 case PCC_P3:
2167 ecmd->rx_coalesce_usecs = PCC_P3_TO;
2168 ecmd->rx_max_coalesced_frames = PCC_P3_CNT;
2169 break;
2170 default:
2171 break;
2172 }
2173
2174 return 0;
2175 }
2176
2177 static int
2178 jme_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *ecmd)
2179 {
2180 struct jme_adapter *jme = netdev_priv(netdev);
2181 struct dynpcc_info *dpi = &(jme->dpi);
2182
2183 if (netif_running(netdev))
2184 return -EBUSY;
2185
2186 if (ecmd->use_adaptive_rx_coalesce
2187 && test_bit(JME_FLAG_POLL, &jme->flags)) {
2188 clear_bit(JME_FLAG_POLL, &jme->flags);
2189 jme->jme_rx = netif_rx;
2190 jme->jme_vlan_rx = vlan_hwaccel_rx;
2191 dpi->cur = PCC_P1;
2192 dpi->attempt = PCC_P1;
2193 dpi->cnt = 0;
2194 jme_set_rx_pcc(jme, PCC_P1);
2195 jme_interrupt_mode(jme);
2196 } else if (!(ecmd->use_adaptive_rx_coalesce)
2197 && !(test_bit(JME_FLAG_POLL, &jme->flags))) {
2198 set_bit(JME_FLAG_POLL, &jme->flags);
2199 jme->jme_rx = netif_receive_skb;
2200 jme->jme_vlan_rx = vlan_hwaccel_receive_skb;
2201 jme_interrupt_mode(jme);
2202 }
2203
2204 return 0;
2205 }
2206
2207 static void
2208 jme_get_pauseparam(struct net_device *netdev,
2209 struct ethtool_pauseparam *ecmd)
2210 {
2211 struct jme_adapter *jme = netdev_priv(netdev);
2212 u32 val;
2213
2214 ecmd->tx_pause = (jme->reg_txpfc & TXPFC_PF_EN) != 0;
2215 ecmd->rx_pause = (jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0;
2216
2217 spin_lock_bh(&jme->phy_lock);
2218 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2219 spin_unlock_bh(&jme->phy_lock);
2220
2221 ecmd->autoneg =
2222 (val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0;
2223 }
2224
2225 static int
2226 jme_set_pauseparam(struct net_device *netdev,
2227 struct ethtool_pauseparam *ecmd)
2228 {
2229 struct jme_adapter *jme = netdev_priv(netdev);
2230 u32 val;
2231
2232 if (((jme->reg_txpfc & TXPFC_PF_EN) != 0) ^
2233 (ecmd->tx_pause != 0)) {
2234
2235 if (ecmd->tx_pause)
2236 jme->reg_txpfc |= TXPFC_PF_EN;
2237 else
2238 jme->reg_txpfc &= ~TXPFC_PF_EN;
2239
2240 jwrite32(jme, JME_TXPFC, jme->reg_txpfc);
2241 }
2242
2243 spin_lock_bh(&jme->rxmcs_lock);
2244 if (((jme->reg_rxmcs & RXMCS_FLOWCTRL) != 0) ^
2245 (ecmd->rx_pause != 0)) {
2246
2247 if (ecmd->rx_pause)
2248 jme->reg_rxmcs |= RXMCS_FLOWCTRL;
2249 else
2250 jme->reg_rxmcs &= ~RXMCS_FLOWCTRL;
2251
2252 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2253 }
2254 spin_unlock_bh(&jme->rxmcs_lock);
2255
2256 spin_lock_bh(&jme->phy_lock);
2257 val = jme_mdio_read(jme->dev, jme->mii_if.phy_id, MII_ADVERTISE);
2258 if (((val & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) != 0) ^
2259 (ecmd->autoneg != 0)) {
2260
2261 if (ecmd->autoneg)
2262 val |= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2263 else
2264 val &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2265
2266 jme_mdio_write(jme->dev, jme->mii_if.phy_id,
2267 MII_ADVERTISE, val);
2268 }
2269 spin_unlock_bh(&jme->phy_lock);
2270
2271 return 0;
2272 }
2273
2274 static void
2275 jme_get_wol(struct net_device *netdev,
2276 struct ethtool_wolinfo *wol)
2277 {
2278 struct jme_adapter *jme = netdev_priv(netdev);
2279
2280 wol->supported = WAKE_MAGIC | WAKE_PHY;
2281
2282 wol->wolopts = 0;
2283
2284 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2285 wol->wolopts |= WAKE_PHY;
2286
2287 if (jme->reg_pmcs & PMCS_MFEN)
2288 wol->wolopts |= WAKE_MAGIC;
2289
2290 }
2291
2292 static int
2293 jme_set_wol(struct net_device *netdev,
2294 struct ethtool_wolinfo *wol)
2295 {
2296 struct jme_adapter *jme = netdev_priv(netdev);
2297
2298 if (wol->wolopts & (WAKE_MAGICSECURE |
2299 WAKE_UCAST |
2300 WAKE_MCAST |
2301 WAKE_BCAST |
2302 WAKE_ARP))
2303 return -EOPNOTSUPP;
2304
2305 jme->reg_pmcs = 0;
2306
2307 if (wol->wolopts & WAKE_PHY)
2308 jme->reg_pmcs |= PMCS_LFEN | PMCS_LREN;
2309
2310 if (wol->wolopts & WAKE_MAGIC)
2311 jme->reg_pmcs |= PMCS_MFEN;
2312
2313 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2314
2315 return 0;
2316 }
2317
2318 static int
2319 jme_get_settings(struct net_device *netdev,
2320 struct ethtool_cmd *ecmd)
2321 {
2322 struct jme_adapter *jme = netdev_priv(netdev);
2323 int rc;
2324
2325 spin_lock_bh(&jme->phy_lock);
2326 rc = mii_ethtool_gset(&(jme->mii_if), ecmd);
2327 spin_unlock_bh(&jme->phy_lock);
2328 return rc;
2329 }
2330
2331 static int
2332 jme_set_settings(struct net_device *netdev,
2333 struct ethtool_cmd *ecmd)
2334 {
2335 struct jme_adapter *jme = netdev_priv(netdev);
2336 int rc, fdc = 0;
2337
2338 if (ecmd->speed == SPEED_1000 && ecmd->autoneg != AUTONEG_ENABLE)
2339 return -EINVAL;
2340
2341 if (jme->mii_if.force_media &&
2342 ecmd->autoneg != AUTONEG_ENABLE &&
2343 (jme->mii_if.full_duplex != ecmd->duplex))
2344 fdc = 1;
2345
2346 spin_lock_bh(&jme->phy_lock);
2347 rc = mii_ethtool_sset(&(jme->mii_if), ecmd);
2348 spin_unlock_bh(&jme->phy_lock);
2349
2350 if (!rc && fdc)
2351 jme_reset_link(jme);
2352
2353 if (!rc) {
2354 set_bit(JME_FLAG_SSET, &jme->flags);
2355 jme->old_ecmd = *ecmd;
2356 }
2357
2358 return rc;
2359 }
2360
2361 static u32
2362 jme_get_link(struct net_device *netdev)
2363 {
2364 struct jme_adapter *jme = netdev_priv(netdev);
2365 return jread32(jme, JME_PHY_LINK) & PHY_LINK_UP;
2366 }
2367
2368 static u32
2369 jme_get_msglevel(struct net_device *netdev)
2370 {
2371 struct jme_adapter *jme = netdev_priv(netdev);
2372 return jme->msg_enable;
2373 }
2374
2375 static void
2376 jme_set_msglevel(struct net_device *netdev, u32 value)
2377 {
2378 struct jme_adapter *jme = netdev_priv(netdev);
2379 jme->msg_enable = value;
2380 }
2381
2382 static u32
2383 jme_get_rx_csum(struct net_device *netdev)
2384 {
2385 struct jme_adapter *jme = netdev_priv(netdev);
2386 return jme->reg_rxmcs & RXMCS_CHECKSUM;
2387 }
2388
2389 static int
2390 jme_set_rx_csum(struct net_device *netdev, u32 on)
2391 {
2392 struct jme_adapter *jme = netdev_priv(netdev);
2393
2394 spin_lock_bh(&jme->rxmcs_lock);
2395 if (on)
2396 jme->reg_rxmcs |= RXMCS_CHECKSUM;
2397 else
2398 jme->reg_rxmcs &= ~RXMCS_CHECKSUM;
2399 jwrite32(jme, JME_RXMCS, jme->reg_rxmcs);
2400 spin_unlock_bh(&jme->rxmcs_lock);
2401
2402 return 0;
2403 }
2404
2405 static int
2406 jme_set_tx_csum(struct net_device *netdev, u32 on)
2407 {
2408 struct jme_adapter *jme = netdev_priv(netdev);
2409
2410 if (on) {
2411 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2412 if (netdev->mtu <= 1900)
2413 netdev->features |= NETIF_F_HW_CSUM;
2414 } else {
2415 clear_bit(JME_FLAG_TXCSUM, &jme->flags);
2416 netdev->features &= ~NETIF_F_HW_CSUM;
2417 }
2418
2419 return 0;
2420 }
2421
2422 static int
2423 jme_set_tso(struct net_device *netdev, u32 on)
2424 {
2425 struct jme_adapter *jme = netdev_priv(netdev);
2426
2427 if (on) {
2428 set_bit(JME_FLAG_TSO, &jme->flags);
2429 if (netdev->mtu <= 1900)
2430 netdev->features |= NETIF_F_TSO | NETIF_F_TSO6;
2431 } else {
2432 clear_bit(JME_FLAG_TSO, &jme->flags);
2433 netdev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
2434 }
2435
2436 return 0;
2437 }
2438
2439 static int
2440 jme_nway_reset(struct net_device *netdev)
2441 {
2442 struct jme_adapter *jme = netdev_priv(netdev);
2443 jme_restart_an(jme);
2444 return 0;
2445 }
2446
2447 static u8
2448 jme_smb_read(struct jme_adapter *jme, unsigned int addr)
2449 {
2450 u32 val;
2451 int to;
2452
2453 val = jread32(jme, JME_SMBCSR);
2454 to = JME_SMB_BUSY_TIMEOUT;
2455 while ((val & SMBCSR_BUSY) && --to) {
2456 msleep(1);
2457 val = jread32(jme, JME_SMBCSR);
2458 }
2459 if (!to) {
2460 msg_hw(jme, "SMB Bus Busy.\n");
2461 return 0xFF;
2462 }
2463
2464 jwrite32(jme, JME_SMBINTF,
2465 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2466 SMBINTF_HWRWN_READ |
2467 SMBINTF_HWCMD);
2468
2469 val = jread32(jme, JME_SMBINTF);
2470 to = JME_SMB_BUSY_TIMEOUT;
2471 while ((val & SMBINTF_HWCMD) && --to) {
2472 msleep(1);
2473 val = jread32(jme, JME_SMBINTF);
2474 }
2475 if (!to) {
2476 msg_hw(jme, "SMB Bus Busy.\n");
2477 return 0xFF;
2478 }
2479
2480 return (val & SMBINTF_HWDATR) >> SMBINTF_HWDATR_SHIFT;
2481 }
2482
2483 static void
2484 jme_smb_write(struct jme_adapter *jme, unsigned int addr, u8 data)
2485 {
2486 u32 val;
2487 int to;
2488
2489 val = jread32(jme, JME_SMBCSR);
2490 to = JME_SMB_BUSY_TIMEOUT;
2491 while ((val & SMBCSR_BUSY) && --to) {
2492 msleep(1);
2493 val = jread32(jme, JME_SMBCSR);
2494 }
2495 if (!to) {
2496 msg_hw(jme, "SMB Bus Busy.\n");
2497 return;
2498 }
2499
2500 jwrite32(jme, JME_SMBINTF,
2501 ((data << SMBINTF_HWDATW_SHIFT) & SMBINTF_HWDATW) |
2502 ((addr << SMBINTF_HWADDR_SHIFT) & SMBINTF_HWADDR) |
2503 SMBINTF_HWRWN_WRITE |
2504 SMBINTF_HWCMD);
2505
2506 val = jread32(jme, JME_SMBINTF);
2507 to = JME_SMB_BUSY_TIMEOUT;
2508 while ((val & SMBINTF_HWCMD) && --to) {
2509 msleep(1);
2510 val = jread32(jme, JME_SMBINTF);
2511 }
2512 if (!to) {
2513 msg_hw(jme, "SMB Bus Busy.\n");
2514 return;
2515 }
2516
2517 mdelay(2);
2518 }
2519
2520 static int
2521 jme_get_eeprom_len(struct net_device *netdev)
2522 {
2523 struct jme_adapter *jme = netdev_priv(netdev);
2524 u32 val;
2525 val = jread32(jme, JME_SMBCSR);
2526 return (val & SMBCSR_EEPROMD) ? JME_SMB_LEN : 0;
2527 }
2528
2529 static int
2530 jme_get_eeprom(struct net_device *netdev,
2531 struct ethtool_eeprom *eeprom, u8 *data)
2532 {
2533 struct jme_adapter *jme = netdev_priv(netdev);
2534 int i, offset = eeprom->offset, len = eeprom->len;
2535
2536 /*
2537 * ethtool will check the boundary for us
2538 */
2539 eeprom->magic = JME_EEPROM_MAGIC;
2540 for (i = 0 ; i < len ; ++i)
2541 data[i] = jme_smb_read(jme, i + offset);
2542
2543 return 0;
2544 }
2545
2546 static int
2547 jme_set_eeprom(struct net_device *netdev,
2548 struct ethtool_eeprom *eeprom, u8 *data)
2549 {
2550 struct jme_adapter *jme = netdev_priv(netdev);
2551 int i, offset = eeprom->offset, len = eeprom->len;
2552
2553 if (eeprom->magic != JME_EEPROM_MAGIC)
2554 return -EINVAL;
2555
2556 /*
2557 * ethtool will check the boundary for us
2558 */
2559 for (i = 0 ; i < len ; ++i)
2560 jme_smb_write(jme, i + offset, data[i]);
2561
2562 return 0;
2563 }
2564
2565 static const struct ethtool_ops jme_ethtool_ops = {
2566 .get_drvinfo = jme_get_drvinfo,
2567 .get_regs_len = jme_get_regs_len,
2568 .get_regs = jme_get_regs,
2569 .get_coalesce = jme_get_coalesce,
2570 .set_coalesce = jme_set_coalesce,
2571 .get_pauseparam = jme_get_pauseparam,
2572 .set_pauseparam = jme_set_pauseparam,
2573 .get_wol = jme_get_wol,
2574 .set_wol = jme_set_wol,
2575 .get_settings = jme_get_settings,
2576 .set_settings = jme_set_settings,
2577 .get_link = jme_get_link,
2578 .get_msglevel = jme_get_msglevel,
2579 .set_msglevel = jme_set_msglevel,
2580 .get_rx_csum = jme_get_rx_csum,
2581 .set_rx_csum = jme_set_rx_csum,
2582 .set_tx_csum = jme_set_tx_csum,
2583 .set_tso = jme_set_tso,
2584 .set_sg = ethtool_op_set_sg,
2585 .nway_reset = jme_nway_reset,
2586 .get_eeprom_len = jme_get_eeprom_len,
2587 .get_eeprom = jme_get_eeprom,
2588 .set_eeprom = jme_set_eeprom,
2589 };
2590
2591 static int
2592 jme_pci_dma64(struct pci_dev *pdev)
2593 {
2594 if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK))
2595 if (!pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK))
2596 return 0;
2597
2598 return -1;
2599 }
2600
2601 static inline void
2602 jme_phy_init(struct jme_adapter *jme)
2603 {
2604 u16 reg26;
2605
2606 reg26 = jme_mdio_read(jme->dev, jme->mii_if.phy_id, 26);
2607 jme_mdio_write(jme->dev, jme->mii_if.phy_id, 26, reg26 | 0x1000);
2608 }
2609
2610 static inline void
2611 jme_check_hw_ver(struct jme_adapter *jme)
2612 {
2613 u32 chipmode;
2614
2615 chipmode = jread32(jme, JME_CHIPMODE);
2616
2617 jme->fpgaver = (chipmode & CM_FPGAVER_MASK) >> CM_FPGAVER_SHIFT;
2618 jme->chiprev = (chipmode & CM_CHIPREV_MASK) >> CM_CHIPREV_SHIFT;
2619 }
2620
2621 static const struct net_device_ops jme_netdev_ops = {
2622 .ndo_open = jme_open,
2623 .ndo_stop = jme_close,
2624 .ndo_validate_addr = eth_validate_addr,
2625 .ndo_start_xmit = jme_start_xmit,
2626 .ndo_set_mac_address = jme_set_macaddr,
2627 .ndo_set_multicast_list = jme_set_multi,
2628 .ndo_change_mtu = jme_change_mtu,
2629 .ndo_tx_timeout = jme_tx_timeout,
2630 .ndo_vlan_rx_register = jme_vlan_rx_register,
2631 };
2632
2633 static int __devinit
2634 jme_init_one(struct pci_dev *pdev,
2635 const struct pci_device_id *ent)
2636 {
2637 int rc = 0, using_dac, i;
2638 struct net_device *netdev;
2639 struct jme_adapter *jme;
2640 u16 bmcr, bmsr;
2641 u32 apmc;
2642
2643 /*
2644 * set up PCI device basics
2645 */
2646 rc = pci_enable_device(pdev);
2647 if (rc) {
2648 jeprintk(pdev, "Cannot enable PCI device.\n");
2649 goto err_out;
2650 }
2651
2652 using_dac = jme_pci_dma64(pdev);
2653 if (using_dac < 0) {
2654 jeprintk(pdev, "Cannot set PCI DMA Mask.\n");
2655 rc = -EIO;
2656 goto err_out_disable_pdev;
2657 }
2658
2659 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
2660 jeprintk(pdev, "No PCI resource region found.\n");
2661 rc = -ENOMEM;
2662 goto err_out_disable_pdev;
2663 }
2664
2665 rc = pci_request_regions(pdev, DRV_NAME);
2666 if (rc) {
2667 jeprintk(pdev, "Cannot obtain PCI resource region.\n");
2668 goto err_out_disable_pdev;
2669 }
2670
2671 pci_set_master(pdev);
2672
2673 /*
2674 * alloc and init net device
2675 */
2676 netdev = alloc_etherdev(sizeof(*jme));
2677 if (!netdev) {
2678 jeprintk(pdev, "Cannot allocate netdev structure.\n");
2679 rc = -ENOMEM;
2680 goto err_out_release_regions;
2681 }
2682 netdev->netdev_ops = &jme_netdev_ops;
2683 netdev->ethtool_ops = &jme_ethtool_ops;
2684 netdev->watchdog_timeo = TX_TIMEOUT;
2685 netdev->features = NETIF_F_HW_CSUM |
2686 NETIF_F_SG |
2687 NETIF_F_TSO |
2688 NETIF_F_TSO6 |
2689 NETIF_F_HW_VLAN_TX |
2690 NETIF_F_HW_VLAN_RX;
2691 if (using_dac)
2692 netdev->features |= NETIF_F_HIGHDMA;
2693
2694 SET_NETDEV_DEV(netdev, &pdev->dev);
2695 pci_set_drvdata(pdev, netdev);
2696
2697 /*
2698 * init adapter info
2699 */
2700 jme = netdev_priv(netdev);
2701 jme->pdev = pdev;
2702 jme->dev = netdev;
2703 jme->jme_rx = netif_rx;
2704 jme->jme_vlan_rx = vlan_hwaccel_rx;
2705 jme->old_mtu = netdev->mtu = 1500;
2706 jme->phylink = 0;
2707 jme->tx_ring_size = 1 << 10;
2708 jme->tx_ring_mask = jme->tx_ring_size - 1;
2709 jme->tx_wake_threshold = 1 << 9;
2710 jme->rx_ring_size = 1 << 9;
2711 jme->rx_ring_mask = jme->rx_ring_size - 1;
2712 jme->msg_enable = JME_DEF_MSG_ENABLE;
2713 jme->regs = ioremap(pci_resource_start(pdev, 0),
2714 pci_resource_len(pdev, 0));
2715 if (!(jme->regs)) {
2716 jeprintk(pdev, "Mapping PCI resource region error.\n");
2717 rc = -ENOMEM;
2718 goto err_out_free_netdev;
2719 }
2720 jme->shadow_regs = pci_alloc_consistent(pdev,
2721 sizeof(u32) * SHADOW_REG_NR,
2722 &(jme->shadow_dma));
2723 if (!(jme->shadow_regs)) {
2724 jeprintk(pdev, "Allocating shadow register mapping error.\n");
2725 rc = -ENOMEM;
2726 goto err_out_unmap;
2727 }
2728
2729 if (no_pseudohp) {
2730 apmc = jread32(jme, JME_APMC) & ~JME_APMC_PSEUDO_HP_EN;
2731 jwrite32(jme, JME_APMC, apmc);
2732 } else if (force_pseudohp) {
2733 apmc = jread32(jme, JME_APMC) | JME_APMC_PSEUDO_HP_EN;
2734 jwrite32(jme, JME_APMC, apmc);
2735 }
2736
2737 NETIF_NAPI_SET(netdev, &jme->napi, jme_poll, jme->rx_ring_size >> 2)
2738
2739 spin_lock_init(&jme->phy_lock);
2740 spin_lock_init(&jme->macaddr_lock);
2741 spin_lock_init(&jme->rxmcs_lock);
2742
2743 atomic_set(&jme->link_changing, 1);
2744 atomic_set(&jme->rx_cleaning, 1);
2745 atomic_set(&jme->tx_cleaning, 1);
2746 atomic_set(&jme->rx_empty, 1);
2747
2748 tasklet_init(&jme->pcc_task,
2749 &jme_pcc_tasklet,
2750 (unsigned long) jme);
2751 tasklet_init(&jme->linkch_task,
2752 &jme_link_change_tasklet,
2753 (unsigned long) jme);
2754 tasklet_init(&jme->txclean_task,
2755 &jme_tx_clean_tasklet,
2756 (unsigned long) jme);
2757 tasklet_init(&jme->rxclean_task,
2758 &jme_rx_clean_tasklet,
2759 (unsigned long) jme);
2760 tasklet_init(&jme->rxempty_task,
2761 &jme_rx_empty_tasklet,
2762 (unsigned long) jme);
2763 tasklet_disable_nosync(&jme->txclean_task);
2764 tasklet_disable_nosync(&jme->rxclean_task);
2765 tasklet_disable_nosync(&jme->rxempty_task);
2766 jme->dpi.cur = PCC_P1;
2767
2768 jme->reg_ghc = 0;
2769 jme->reg_rxcs = RXCS_DEFAULT;
2770 jme->reg_rxmcs = RXMCS_DEFAULT;
2771 jme->reg_txpfc = 0;
2772 jme->reg_pmcs = PMCS_MFEN;
2773 set_bit(JME_FLAG_TXCSUM, &jme->flags);
2774 set_bit(JME_FLAG_TSO, &jme->flags);
2775
2776 /*
2777 * Get Max Read Req Size from PCI Config Space
2778 */
2779 pci_read_config_byte(pdev, PCI_DCSR_MRRS, &jme->mrrs);
2780 jme->mrrs &= PCI_DCSR_MRRS_MASK;
2781 switch (jme->mrrs) {
2782 case MRRS_128B:
2783 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_128B;
2784 break;
2785 case MRRS_256B:
2786 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_256B;
2787 break;
2788 default:
2789 jme->reg_txcs = TXCS_DEFAULT | TXCS_DMASIZE_512B;
2790 break;
2791 };
2792
2793 /*
2794 * Must check before reset_mac_processor
2795 */
2796 jme_check_hw_ver(jme);
2797 jme->mii_if.dev = netdev;
2798 if (jme->fpgaver) {
2799 jme->mii_if.phy_id = 0;
2800 for (i = 1 ; i < 32 ; ++i) {
2801 bmcr = jme_mdio_read(netdev, i, MII_BMCR);
2802 bmsr = jme_mdio_read(netdev, i, MII_BMSR);
2803 if (bmcr != 0xFFFFU && (bmcr != 0 || bmsr != 0)) {
2804 jme->mii_if.phy_id = i;
2805 break;
2806 }
2807 }
2808
2809 if (!jme->mii_if.phy_id) {
2810 rc = -EIO;
2811 jeprintk(pdev, "Can not find phy_id.\n");
2812 goto err_out_free_shadow;
2813 }
2814
2815 jme->reg_ghc |= GHC_LINK_POLL;
2816 } else {
2817 jme->mii_if.phy_id = 1;
2818 }
2819 if (pdev->device == PCI_DEVICE_ID_JMICRON_JMC250)
2820 jme->mii_if.supports_gmii = true;
2821 else
2822 jme->mii_if.supports_gmii = false;
2823 jme->mii_if.mdio_read = jme_mdio_read;
2824 jme->mii_if.mdio_write = jme_mdio_write;
2825
2826 jme_clear_pm(jme);
2827 jme_set_phyfifoa(jme);
2828 pci_read_config_byte(pdev, PCI_REVISION_ID, &jme->rev);
2829 if (!jme->fpgaver)
2830 jme_phy_init(jme);
2831 jme_phy_off(jme);
2832
2833 /*
2834 * Reset MAC processor and reload EEPROM for MAC Address
2835 */
2836 jme_reset_mac_processor(jme);
2837 rc = jme_reload_eeprom(jme);
2838 if (rc) {
2839 jeprintk(pdev,
2840 "Reload eeprom for reading MAC Address error.\n");
2841 goto err_out_free_shadow;
2842 }
2843 jme_load_macaddr(netdev);
2844
2845 /*
2846 * Tell stack that we are not ready to work until open()
2847 */
2848 netif_carrier_off(netdev);
2849 netif_stop_queue(netdev);
2850
2851 /*
2852 * Register netdev
2853 */
2854 rc = register_netdev(netdev);
2855 if (rc) {
2856 jeprintk(pdev, "Cannot register net device.\n");
2857 goto err_out_free_shadow;
2858 }
2859
2860 msg_probe(jme, "JMC250 gigabit%s ver:%x rev:%x macaddr:%pM\n",
2861 (jme->fpgaver != 0) ? " (FPGA)" : "",
2862 (jme->fpgaver != 0) ? jme->fpgaver : jme->chiprev,
2863 jme->rev, netdev->dev_addr);
2864
2865 return 0;
2866
2867 err_out_free_shadow:
2868 pci_free_consistent(pdev,
2869 sizeof(u32) * SHADOW_REG_NR,
2870 jme->shadow_regs,
2871 jme->shadow_dma);
2872 err_out_unmap:
2873 iounmap(jme->regs);
2874 err_out_free_netdev:
2875 pci_set_drvdata(pdev, NULL);
2876 free_netdev(netdev);
2877 err_out_release_regions:
2878 pci_release_regions(pdev);
2879 err_out_disable_pdev:
2880 pci_disable_device(pdev);
2881 err_out:
2882 return rc;
2883 }
2884
2885 static void __devexit
2886 jme_remove_one(struct pci_dev *pdev)
2887 {
2888 struct net_device *netdev = pci_get_drvdata(pdev);
2889 struct jme_adapter *jme = netdev_priv(netdev);
2890
2891 unregister_netdev(netdev);
2892 pci_free_consistent(pdev,
2893 sizeof(u32) * SHADOW_REG_NR,
2894 jme->shadow_regs,
2895 jme->shadow_dma);
2896 iounmap(jme->regs);
2897 pci_set_drvdata(pdev, NULL);
2898 free_netdev(netdev);
2899 pci_release_regions(pdev);
2900 pci_disable_device(pdev);
2901
2902 }
2903
2904 #ifdef CONFIG_PM
2905 static int
2906 jme_suspend(struct pci_dev *pdev, pm_message_t state)
2907 {
2908 struct net_device *netdev = pci_get_drvdata(pdev);
2909 struct jme_adapter *jme = netdev_priv(netdev);
2910
2911 atomic_dec(&jme->link_changing);
2912
2913 netif_device_detach(netdev);
2914 netif_stop_queue(netdev);
2915 jme_stop_irq(jme);
2916
2917 tasklet_disable(&jme->txclean_task);
2918 tasklet_disable(&jme->rxclean_task);
2919 tasklet_disable(&jme->rxempty_task);
2920
2921 jme_disable_shadow(jme);
2922
2923 if (netif_carrier_ok(netdev)) {
2924 if (test_bit(JME_FLAG_POLL, &jme->flags))
2925 jme_polling_mode(jme);
2926
2927 jme_stop_pcc_timer(jme);
2928 jme_reset_ghc_speed(jme);
2929 jme_disable_rx_engine(jme);
2930 jme_disable_tx_engine(jme);
2931 jme_reset_mac_processor(jme);
2932 jme_free_rx_resources(jme);
2933 jme_free_tx_resources(jme);
2934 netif_carrier_off(netdev);
2935 jme->phylink = 0;
2936 }
2937
2938 tasklet_enable(&jme->txclean_task);
2939 tasklet_hi_enable(&jme->rxclean_task);
2940 tasklet_hi_enable(&jme->rxempty_task);
2941
2942 pci_save_state(pdev);
2943 if (jme->reg_pmcs) {
2944 jme_set_100m_half(jme);
2945
2946 if (jme->reg_pmcs & (PMCS_LFEN | PMCS_LREN))
2947 jme_wait_link(jme);
2948
2949 jwrite32(jme, JME_PMCS, jme->reg_pmcs);
2950
2951 pci_enable_wake(pdev, PCI_D3cold, true);
2952 } else {
2953 jme_phy_off(jme);
2954 }
2955 pci_set_power_state(pdev, PCI_D3cold);
2956
2957 return 0;
2958 }
2959
2960 static int
2961 jme_resume(struct pci_dev *pdev)
2962 {
2963 struct net_device *netdev = pci_get_drvdata(pdev);
2964 struct jme_adapter *jme = netdev_priv(netdev);
2965
2966 jme_clear_pm(jme);
2967 pci_restore_state(pdev);
2968
2969 if (test_bit(JME_FLAG_SSET, &jme->flags))
2970 jme_set_settings(netdev, &jme->old_ecmd);
2971 else
2972 jme_reset_phy_processor(jme);
2973
2974 jme_enable_shadow(jme);
2975 jme_start_irq(jme);
2976 netif_device_attach(netdev);
2977
2978 atomic_inc(&jme->link_changing);
2979
2980 jme_reset_link(jme);
2981
2982 return 0;
2983 }
2984 #endif
2985
2986 static struct pci_device_id jme_pci_tbl[] = {
2987 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC250) },
2988 { PCI_VDEVICE(JMICRON, PCI_DEVICE_ID_JMICRON_JMC260) },
2989 { }
2990 };
2991
2992 static struct pci_driver jme_driver = {
2993 .name = DRV_NAME,
2994 .id_table = jme_pci_tbl,
2995 .probe = jme_init_one,
2996 .remove = __devexit_p(jme_remove_one),
2997 #ifdef CONFIG_PM
2998 .suspend = jme_suspend,
2999 .resume = jme_resume,
3000 #endif /* CONFIG_PM */
3001 };
3002
3003 static int __init
3004 jme_init_module(void)
3005 {
3006 printk(KERN_INFO PFX "JMicron JMC250 gigabit ethernet "
3007 "driver version %s\n", DRV_VERSION);
3008 return pci_register_driver(&jme_driver);
3009 }
3010
3011 static void __exit
3012 jme_cleanup_module(void)
3013 {
3014 pci_unregister_driver(&jme_driver);
3015 }
3016
3017 module_init(jme_init_module);
3018 module_exit(jme_cleanup_module);
3019
3020 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3021 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3022 MODULE_LICENSE("GPL");
3023 MODULE_VERSION(DRV_VERSION);
3024 MODULE_DEVICE_TABLE(pci, jme_pci_tbl);
3025
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