2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/mii.h>
34 #include <linux/crc32.h>
35 #include <linux/delay.h>
36 #include <linux/spinlock.h>
39 #include <linux/ipv6.h>
40 #include <linux/tcp.h>
41 #include <linux/udp.h>
42 #include <linux/if_vlan.h>
43 #include <linux/slab.h>
44 #include <net/ip6_checksum.h>
47 static int force_pseudohp
= -1;
48 static int no_pseudohp
= -1;
49 static int no_extplug
= -1;
50 module_param(force_pseudohp
, int, 0);
51 MODULE_PARM_DESC(force_pseudohp
,
52 "Enable pseudo hot-plug feature manually by driver instead of BIOS.");
53 module_param(no_pseudohp
, int, 0);
54 MODULE_PARM_DESC(no_pseudohp
, "Disable pseudo hot-plug feature.");
55 module_param(no_extplug
, int, 0);
56 MODULE_PARM_DESC(no_extplug
,
57 "Do not use external plug signal for pseudo hot-plug.");
60 jme_mdio_read(struct net_device
*netdev
, int phy
, int reg
)
62 struct jme_adapter
*jme
= netdev_priv(netdev
);
63 int i
, val
, again
= (reg
== MII_BMSR
) ? 1 : 0;
66 jwrite32(jme
, JME_SMI
, SMI_OP_REQ
|
71 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
73 val
= jread32(jme
, JME_SMI
);
74 if ((val
& SMI_OP_REQ
) == 0)
79 pr_err("phy(%d) read timeout : %d\n", phy
, reg
);
86 return (val
& SMI_DATA_MASK
) >> SMI_DATA_SHIFT
;
90 jme_mdio_write(struct net_device
*netdev
,
91 int phy
, int reg
, int val
)
93 struct jme_adapter
*jme
= netdev_priv(netdev
);
96 jwrite32(jme
, JME_SMI
, SMI_OP_WRITE
| SMI_OP_REQ
|
97 ((val
<< SMI_DATA_SHIFT
) & SMI_DATA_MASK
) |
98 smi_phy_addr(phy
) | smi_reg_addr(reg
));
101 for (i
= JME_PHY_TIMEOUT
* 50 ; i
> 0 ; --i
) {
103 if ((jread32(jme
, JME_SMI
) & SMI_OP_REQ
) == 0)
108 pr_err("phy(%d) write timeout : %d\n", phy
, reg
);
112 jme_reset_phy_processor(struct jme_adapter
*jme
)
116 jme_mdio_write(jme
->dev
,
118 MII_ADVERTISE
, ADVERTISE_ALL
|
119 ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
121 if (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
122 jme_mdio_write(jme
->dev
,
125 ADVERTISE_1000FULL
| ADVERTISE_1000HALF
);
127 val
= jme_mdio_read(jme
->dev
,
131 jme_mdio_write(jme
->dev
,
133 MII_BMCR
, val
| BMCR_RESET
);
137 jme_setup_wakeup_frame(struct jme_adapter
*jme
,
138 const u32
*mask
, u32 crc
, int fnr
)
145 jwrite32(jme
, JME_WFOI
, WFOI_CRC_SEL
| (fnr
& WFOI_FRAME_SEL
));
147 jwrite32(jme
, JME_WFODP
, crc
);
153 for (i
= 0 ; i
< WAKEUP_FRAME_MASK_DWNR
; ++i
) {
154 jwrite32(jme
, JME_WFOI
,
155 ((i
<< WFOI_MASK_SHIFT
) & WFOI_MASK_SEL
) |
156 (fnr
& WFOI_FRAME_SEL
));
158 jwrite32(jme
, JME_WFODP
, mask
[i
]);
164 jme_reset_mac_processor(struct jme_adapter
*jme
)
166 static const u32 mask
[WAKEUP_FRAME_MASK_DWNR
] = {0, 0, 0, 0};
167 u32 crc
= 0xCDCDCDCD;
171 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
| GHC_SWRST
);
173 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
175 jwrite32(jme
, JME_RXDBA_LO
, 0x00000000);
176 jwrite32(jme
, JME_RXDBA_HI
, 0x00000000);
177 jwrite32(jme
, JME_RXQDC
, 0x00000000);
178 jwrite32(jme
, JME_RXNDA
, 0x00000000);
179 jwrite32(jme
, JME_TXDBA_LO
, 0x00000000);
180 jwrite32(jme
, JME_TXDBA_HI
, 0x00000000);
181 jwrite32(jme
, JME_TXQDC
, 0x00000000);
182 jwrite32(jme
, JME_TXNDA
, 0x00000000);
184 jwrite32(jme
, JME_RXMCHT_LO
, 0x00000000);
185 jwrite32(jme
, JME_RXMCHT_HI
, 0x00000000);
186 for (i
= 0 ; i
< WAKEUP_FRAME_NR
; ++i
)
187 jme_setup_wakeup_frame(jme
, mask
, crc
, i
);
189 gpreg0
= GPREG0_DEFAULT
| GPREG0_LNKINTPOLL
;
191 gpreg0
= GPREG0_DEFAULT
;
192 jwrite32(jme
, JME_GPREG0
, gpreg0
);
193 jwrite32(jme
, JME_GPREG1
, GPREG1_DEFAULT
);
197 jme_reset_ghc_speed(struct jme_adapter
*jme
)
199 jme
->reg_ghc
&= ~(GHC_SPEED_1000M
| GHC_DPX
);
200 jwrite32(jme
, JME_GHC
, jme
->reg_ghc
);
204 jme_clear_pm(struct jme_adapter
*jme
)
206 jwrite32(jme
, JME_PMCS
, 0xFFFF0000 | jme
->reg_pmcs
);
207 pci_set_power_state(jme
->pdev
, PCI_D0
);
208 pci_enable_wake(jme
->pdev
, PCI_D0
, false);
212 jme_reload_eeprom(struct jme_adapter
*jme
)
217 val
= jread32(jme
, JME_SMBCSR
);
219 if (val
& SMBCSR_EEPROMD
) {
221 jwrite32(jme
, JME_SMBCSR
, val
);
222 val
|= SMBCSR_RELOAD
;
223 jwrite32(jme
, JME_SMBCSR
, val
);
226 for (i
= JME_EEPROM_RELOAD_TIMEOUT
; i
> 0; --i
) {
228 if ((jread32(jme
, JME_SMBCSR
) & SMBCSR_RELOAD
) == 0)
233 pr_err("eeprom reload timeout\n");
242 jme_load_macaddr(struct net_device
*netdev
)
244 struct jme_adapter
*jme
= netdev_priv(netdev
);
245 unsigned char macaddr
[6];
248 spin_lock_bh(&jme
->macaddr_lock
);
249 val
= jread32(jme
, JME_RXUMA_LO
);
250 macaddr
[0] = (val
>> 0) & 0xFF;
251 macaddr
[1] = (val
>> 8) & 0xFF;
252 macaddr
[2] = (val
>> 16) & 0xFF;
253 macaddr
[3] = (val
>> 24) & 0xFF;
254 val
= jread32(jme
, JME_RXUMA_HI
);
255 macaddr
[4] = (val
>> 0) & 0xFF;
256 macaddr
[5] = (val
>> 8) & 0xFF;
257 memcpy(netdev
->dev_addr
, macaddr
, 6);
258 spin_unlock_bh(&jme
->macaddr_lock
);
262 jme_set_rx_pcc(struct jme_adapter
*jme
, int p
)
266 jwrite32(jme
, JME_PCCRX0
,
267 ((PCC_OFF_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
268 ((PCC_OFF_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
271 jwrite32(jme
, JME_PCCRX0
,
272 ((PCC_P1_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
273 ((PCC_P1_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
276 jwrite32(jme
, JME_PCCRX0
,
277 ((PCC_P2_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
278 ((PCC_P2_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
281 jwrite32(jme
, JME_PCCRX0
,
282 ((PCC_P3_TO
<< PCCRXTO_SHIFT
) & PCCRXTO_MASK
) |
283 ((PCC_P3_CNT
<< PCCRX_SHIFT
) & PCCRX_MASK
));
290 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
291 netif_info(jme
, rx_status
, jme
->dev
, "Switched to PCC_P%d\n", p
);
295 jme_start_irq(struct jme_adapter
*jme
)
297 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
299 jme_set_rx_pcc(jme
, PCC_P1
);
301 dpi
->attempt
= PCC_P1
;
304 jwrite32(jme
, JME_PCCTX
,
305 ((PCC_TX_TO
<< PCCTXTO_SHIFT
) & PCCTXTO_MASK
) |
306 ((PCC_TX_CNT
<< PCCTX_SHIFT
) & PCCTX_MASK
) |
313 jwrite32(jme
, JME_IENS
, INTR_ENABLE
);
317 jme_stop_irq(struct jme_adapter
*jme
)
322 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
326 jme_linkstat_from_phy(struct jme_adapter
*jme
)
330 phylink
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 17);
331 bmsr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMSR
);
332 if (bmsr
& BMSR_ANCOMP
)
333 phylink
|= PHY_LINK_AUTONEG_COMPLETE
;
339 jme_set_phyfifo_5level(struct jme_adapter
*jme
)
341 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0004);
345 jme_set_phyfifo_8level(struct jme_adapter
*jme
)
347 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 27, 0x0000);
351 jme_check_link(struct net_device
*netdev
, int testonly
)
353 struct jme_adapter
*jme
= netdev_priv(netdev
);
354 u32 phylink
, ghc
, cnt
= JME_SPDRSV_TIMEOUT
, bmcr
, gpreg1
;
361 phylink
= jme_linkstat_from_phy(jme
);
363 phylink
= jread32(jme
, JME_PHY_LINK
);
365 if (phylink
& PHY_LINK_UP
) {
366 if (!(phylink
& PHY_LINK_AUTONEG_COMPLETE
)) {
368 * If we did not enable AN
369 * Speed/Duplex Info should be obtained from SMI
371 phylink
= PHY_LINK_UP
;
373 bmcr
= jme_mdio_read(jme
->dev
,
377 phylink
|= ((bmcr
& BMCR_SPEED1000
) &&
378 (bmcr
& BMCR_SPEED100
) == 0) ?
379 PHY_LINK_SPEED_1000M
:
380 (bmcr
& BMCR_SPEED100
) ?
381 PHY_LINK_SPEED_100M
:
384 phylink
|= (bmcr
& BMCR_FULLDPLX
) ?
387 strcat(linkmsg
, "Forced: ");
390 * Keep polling for speed/duplex resolve complete
392 while (!(phylink
& PHY_LINK_SPEEDDPU_RESOLVED
) &&
398 phylink
= jme_linkstat_from_phy(jme
);
400 phylink
= jread32(jme
, JME_PHY_LINK
);
403 pr_err("Waiting speed resolve timeout\n");
405 strcat(linkmsg
, "ANed: ");
408 if (jme
->phylink
== phylink
) {
415 jme
->phylink
= phylink
;
417 ghc
= jme
->reg_ghc
& ~(GHC_SPEED
| GHC_DPX
|
418 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
|
419 GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
);
420 switch (phylink
& PHY_LINK_SPEED_MASK
) {
421 case PHY_LINK_SPEED_10M
:
422 ghc
|= GHC_SPEED_10M
|
423 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
424 strcat(linkmsg
, "10 Mbps, ");
426 case PHY_LINK_SPEED_100M
:
427 ghc
|= GHC_SPEED_100M
|
428 GHC_TO_CLK_PCIE
| GHC_TXMAC_CLK_PCIE
;
429 strcat(linkmsg
, "100 Mbps, ");
431 case PHY_LINK_SPEED_1000M
:
432 ghc
|= GHC_SPEED_1000M
|
433 GHC_TO_CLK_GPHY
| GHC_TXMAC_CLK_GPHY
;
434 strcat(linkmsg
, "1000 Mbps, ");
440 if (phylink
& PHY_LINK_DUPLEX
) {
441 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
);
442 jwrite32(jme
, JME_TXTRHD
, TXTRHD_FULLDUPLEX
);
445 jwrite32(jme
, JME_TXMCS
, TXMCS_DEFAULT
|
449 jwrite32(jme
, JME_TXTRHD
, TXTRHD_HALFDUPLEX
);
452 gpreg1
= GPREG1_DEFAULT
;
453 if (is_buggy250(jme
->pdev
->device
, jme
->chiprev
)) {
454 if (!(phylink
& PHY_LINK_DUPLEX
))
455 gpreg1
|= GPREG1_HALFMODEPATCH
;
456 switch (phylink
& PHY_LINK_SPEED_MASK
) {
457 case PHY_LINK_SPEED_10M
:
458 jme_set_phyfifo_8level(jme
);
459 gpreg1
|= GPREG1_RSSPATCH
;
461 case PHY_LINK_SPEED_100M
:
462 jme_set_phyfifo_5level(jme
);
463 gpreg1
|= GPREG1_RSSPATCH
;
465 case PHY_LINK_SPEED_1000M
:
466 jme_set_phyfifo_8level(jme
);
473 jwrite32(jme
, JME_GPREG1
, gpreg1
);
474 jwrite32(jme
, JME_GHC
, ghc
);
477 strcat(linkmsg
, (phylink
& PHY_LINK_DUPLEX
) ?
480 strcat(linkmsg
, (phylink
& PHY_LINK_MDI_STAT
) ?
483 netif_info(jme
, link
, jme
->dev
, "Link is up at %s\n", linkmsg
);
484 netif_carrier_on(netdev
);
489 netif_info(jme
, link
, jme
->dev
, "Link is down\n");
491 netif_carrier_off(netdev
);
499 jme_setup_tx_resources(struct jme_adapter
*jme
)
501 struct jme_ring
*txring
= &(jme
->txring
[0]);
503 txring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
504 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
514 txring
->desc
= (void *)ALIGN((unsigned long)(txring
->alloc
),
516 txring
->dma
= ALIGN(txring
->dmaalloc
, RING_DESC_ALIGN
);
517 txring
->next_to_use
= 0;
518 atomic_set(&txring
->next_to_clean
, 0);
519 atomic_set(&txring
->nr_free
, jme
->tx_ring_size
);
521 txring
->bufinf
= kmalloc(sizeof(struct jme_buffer_info
) *
522 jme
->tx_ring_size
, GFP_ATOMIC
);
523 if (unlikely(!(txring
->bufinf
)))
524 goto err_free_txring
;
527 * Initialize Transmit Descriptors
529 memset(txring
->alloc
, 0, TX_RING_ALLOC_SIZE(jme
->tx_ring_size
));
530 memset(txring
->bufinf
, 0,
531 sizeof(struct jme_buffer_info
) * jme
->tx_ring_size
);
536 dma_free_coherent(&(jme
->pdev
->dev
),
537 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
543 txring
->dmaalloc
= 0;
545 txring
->bufinf
= NULL
;
551 jme_free_tx_resources(struct jme_adapter
*jme
)
554 struct jme_ring
*txring
= &(jme
->txring
[0]);
555 struct jme_buffer_info
*txbi
;
558 if (txring
->bufinf
) {
559 for (i
= 0 ; i
< jme
->tx_ring_size
; ++i
) {
560 txbi
= txring
->bufinf
+ i
;
562 dev_kfree_skb(txbi
->skb
);
568 txbi
->start_xmit
= 0;
570 kfree(txring
->bufinf
);
573 dma_free_coherent(&(jme
->pdev
->dev
),
574 TX_RING_ALLOC_SIZE(jme
->tx_ring_size
),
578 txring
->alloc
= NULL
;
580 txring
->dmaalloc
= 0;
582 txring
->bufinf
= NULL
;
584 txring
->next_to_use
= 0;
585 atomic_set(&txring
->next_to_clean
, 0);
586 atomic_set(&txring
->nr_free
, 0);
590 jme_enable_tx_engine(struct jme_adapter
*jme
)
595 jwrite32(jme
, JME_TXCS
, TXCS_DEFAULT
| TXCS_SELECT_QUEUE0
);
599 * Setup TX Queue 0 DMA Bass Address
601 jwrite32(jme
, JME_TXDBA_LO
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
602 jwrite32(jme
, JME_TXDBA_HI
, (__u64
)(jme
->txring
[0].dma
) >> 32);
603 jwrite32(jme
, JME_TXNDA
, (__u64
)jme
->txring
[0].dma
& 0xFFFFFFFFUL
);
606 * Setup TX Descptor Count
608 jwrite32(jme
, JME_TXQDC
, jme
->tx_ring_size
);
614 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
621 jme_restart_tx_engine(struct jme_adapter
*jme
)
626 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
632 jme_disable_tx_engine(struct jme_adapter
*jme
)
640 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
| TXCS_SELECT_QUEUE0
);
643 val
= jread32(jme
, JME_TXCS
);
644 for (i
= JME_TX_DISABLE_TIMEOUT
; (val
& TXCS_ENABLE
) && i
> 0 ; --i
) {
646 val
= jread32(jme
, JME_TXCS
);
651 pr_err("Disable TX engine timeout\n");
655 jme_set_clean_rxdesc(struct jme_adapter
*jme
, int i
)
657 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
658 register struct rxdesc
*rxdesc
= rxring
->desc
;
659 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
665 rxdesc
->desc1
.bufaddrh
= cpu_to_le32((__u64
)rxbi
->mapping
>> 32);
666 rxdesc
->desc1
.bufaddrl
= cpu_to_le32(
667 (__u64
)rxbi
->mapping
& 0xFFFFFFFFUL
);
668 rxdesc
->desc1
.datalen
= cpu_to_le16(rxbi
->len
);
669 if (jme
->dev
->features
& NETIF_F_HIGHDMA
)
670 rxdesc
->desc1
.flags
= RXFLAG_64BIT
;
672 rxdesc
->desc1
.flags
|= RXFLAG_OWN
| RXFLAG_INT
;
676 jme_make_new_rx_buf(struct jme_adapter
*jme
, int i
)
678 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
679 struct jme_buffer_info
*rxbi
= rxring
->bufinf
+ i
;
682 skb
= netdev_alloc_skb(jme
->dev
,
683 jme
->dev
->mtu
+ RX_EXTRA_LEN
);
688 rxbi
->len
= skb_tailroom(skb
);
689 rxbi
->mapping
= pci_map_page(jme
->pdev
,
690 virt_to_page(skb
->data
),
691 offset_in_page(skb
->data
),
699 jme_free_rx_buf(struct jme_adapter
*jme
, int i
)
701 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
702 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
706 pci_unmap_page(jme
->pdev
,
710 dev_kfree_skb(rxbi
->skb
);
718 jme_free_rx_resources(struct jme_adapter
*jme
)
721 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
724 if (rxring
->bufinf
) {
725 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
)
726 jme_free_rx_buf(jme
, i
);
727 kfree(rxring
->bufinf
);
730 dma_free_coherent(&(jme
->pdev
->dev
),
731 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
734 rxring
->alloc
= NULL
;
736 rxring
->dmaalloc
= 0;
738 rxring
->bufinf
= NULL
;
740 rxring
->next_to_use
= 0;
741 atomic_set(&rxring
->next_to_clean
, 0);
745 jme_setup_rx_resources(struct jme_adapter
*jme
)
748 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
750 rxring
->alloc
= dma_alloc_coherent(&(jme
->pdev
->dev
),
751 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
760 rxring
->desc
= (void *)ALIGN((unsigned long)(rxring
->alloc
),
762 rxring
->dma
= ALIGN(rxring
->dmaalloc
, RING_DESC_ALIGN
);
763 rxring
->next_to_use
= 0;
764 atomic_set(&rxring
->next_to_clean
, 0);
766 rxring
->bufinf
= kmalloc(sizeof(struct jme_buffer_info
) *
767 jme
->rx_ring_size
, GFP_ATOMIC
);
768 if (unlikely(!(rxring
->bufinf
)))
769 goto err_free_rxring
;
772 * Initiallize Receive Descriptors
774 memset(rxring
->bufinf
, 0,
775 sizeof(struct jme_buffer_info
) * jme
->rx_ring_size
);
776 for (i
= 0 ; i
< jme
->rx_ring_size
; ++i
) {
777 if (unlikely(jme_make_new_rx_buf(jme
, i
))) {
778 jme_free_rx_resources(jme
);
782 jme_set_clean_rxdesc(jme
, i
);
788 dma_free_coherent(&(jme
->pdev
->dev
),
789 RX_RING_ALLOC_SIZE(jme
->rx_ring_size
),
794 rxring
->dmaalloc
= 0;
796 rxring
->bufinf
= NULL
;
802 jme_enable_rx_engine(struct jme_adapter
*jme
)
807 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
812 * Setup RX DMA Bass Address
814 jwrite32(jme
, JME_RXDBA_LO
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
815 jwrite32(jme
, JME_RXDBA_HI
, (__u64
)(jme
->rxring
[0].dma
) >> 32);
816 jwrite32(jme
, JME_RXNDA
, (__u64
)(jme
->rxring
[0].dma
) & 0xFFFFFFFFUL
);
819 * Setup RX Descriptor Count
821 jwrite32(jme
, JME_RXQDC
, jme
->rx_ring_size
);
824 * Setup Unicast Filter
826 jme_set_multi(jme
->dev
);
832 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
839 jme_restart_rx_engine(struct jme_adapter
*jme
)
844 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
|
851 jme_disable_rx_engine(struct jme_adapter
*jme
)
859 jwrite32(jme
, JME_RXCS
, jme
->reg_rxcs
);
862 val
= jread32(jme
, JME_RXCS
);
863 for (i
= JME_RX_DISABLE_TIMEOUT
; (val
& RXCS_ENABLE
) && i
> 0 ; --i
) {
865 val
= jread32(jme
, JME_RXCS
);
870 pr_err("Disable RX engine timeout\n");
875 jme_rxsum_ok(struct jme_adapter
*jme
, u16 flags
)
877 if (!(flags
& (RXWBFLAG_TCPON
| RXWBFLAG_UDPON
| RXWBFLAG_IPV4
)))
880 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_TCPON
| RXWBFLAG_TCPCS
))
881 == RXWBFLAG_TCPON
)) {
882 if (flags
& RXWBFLAG_IPV4
)
883 netif_err(jme
, rx_err
, jme
->dev
, "TCP Checksum error\n");
887 if (unlikely((flags
& (RXWBFLAG_MF
| RXWBFLAG_UDPON
| RXWBFLAG_UDPCS
))
888 == RXWBFLAG_UDPON
)) {
889 if (flags
& RXWBFLAG_IPV4
)
890 netif_err(jme
, rx_err
, jme
->dev
, "UDP Checksum error\n");
894 if (unlikely((flags
& (RXWBFLAG_IPV4
| RXWBFLAG_IPCS
))
896 netif_err(jme
, rx_err
, jme
->dev
, "IPv4 Checksum error\n");
904 jme_alloc_and_feed_skb(struct jme_adapter
*jme
, int idx
)
906 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
907 struct rxdesc
*rxdesc
= rxring
->desc
;
908 struct jme_buffer_info
*rxbi
= rxring
->bufinf
;
916 pci_dma_sync_single_for_cpu(jme
->pdev
,
921 if (unlikely(jme_make_new_rx_buf(jme
, idx
))) {
922 pci_dma_sync_single_for_device(jme
->pdev
,
927 ++(NET_STAT(jme
).rx_dropped
);
929 framesize
= le16_to_cpu(rxdesc
->descwb
.framesize
)
932 skb_reserve(skb
, RX_PREPAD_SIZE
);
933 skb_put(skb
, framesize
);
934 skb
->protocol
= eth_type_trans(skb
, jme
->dev
);
936 if (jme_rxsum_ok(jme
, le16_to_cpu(rxdesc
->descwb
.flags
)))
937 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
939 skb_checksum_none_assert(skb
);
941 if (rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_TAGON
)) {
943 jme
->jme_vlan_rx(skb
, jme
->vlgrp
,
944 le16_to_cpu(rxdesc
->descwb
.vlan
));
945 NET_STAT(jme
).rx_bytes
+= 4;
953 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_DEST
)) ==
954 cpu_to_le16(RXWBFLAG_DEST_MUL
))
955 ++(NET_STAT(jme
).multicast
);
957 NET_STAT(jme
).rx_bytes
+= framesize
;
958 ++(NET_STAT(jme
).rx_packets
);
961 jme_set_clean_rxdesc(jme
, idx
);
966 jme_process_receive(struct jme_adapter
*jme
, int limit
)
968 struct jme_ring
*rxring
= &(jme
->rxring
[0]);
969 struct rxdesc
*rxdesc
= rxring
->desc
;
970 int i
, j
, ccnt
, desccnt
, mask
= jme
->rx_ring_mask
;
972 if (unlikely(!atomic_dec_and_test(&jme
->rx_cleaning
)))
975 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
978 if (unlikely(!netif_carrier_ok(jme
->dev
)))
981 i
= atomic_read(&rxring
->next_to_clean
);
983 rxdesc
= rxring
->desc
;
986 if ((rxdesc
->descwb
.flags
& cpu_to_le16(RXWBFLAG_OWN
)) ||
987 !(rxdesc
->descwb
.desccnt
& RXWBDCNT_WBCPL
))
992 desccnt
= rxdesc
->descwb
.desccnt
& RXWBDCNT_DCNT
;
994 if (unlikely(desccnt
> 1 ||
995 rxdesc
->descwb
.errstat
& RXWBERR_ALLERR
)) {
997 if (rxdesc
->descwb
.errstat
& RXWBERR_CRCERR
)
998 ++(NET_STAT(jme
).rx_crc_errors
);
999 else if (rxdesc
->descwb
.errstat
& RXWBERR_OVERUN
)
1000 ++(NET_STAT(jme
).rx_fifo_errors
);
1002 ++(NET_STAT(jme
).rx_errors
);
1005 limit
-= desccnt
- 1;
1007 for (j
= i
, ccnt
= desccnt
; ccnt
-- ; ) {
1008 jme_set_clean_rxdesc(jme
, j
);
1009 j
= (j
+ 1) & (mask
);
1013 jme_alloc_and_feed_skb(jme
, i
);
1016 i
= (i
+ desccnt
) & (mask
);
1020 atomic_set(&rxring
->next_to_clean
, i
);
1023 atomic_inc(&jme
->rx_cleaning
);
1025 return limit
> 0 ? limit
: 0;
1030 jme_attempt_pcc(struct dynpcc_info
*dpi
, int atmp
)
1032 if (likely(atmp
== dpi
->cur
)) {
1037 if (dpi
->attempt
== atmp
) {
1040 dpi
->attempt
= atmp
;
1047 jme_dynamic_pcc(struct jme_adapter
*jme
)
1049 register struct dynpcc_info
*dpi
= &(jme
->dpi
);
1051 if ((NET_STAT(jme
).rx_bytes
- dpi
->last_bytes
) > PCC_P3_THRESHOLD
)
1052 jme_attempt_pcc(dpi
, PCC_P3
);
1053 else if ((NET_STAT(jme
).rx_packets
- dpi
->last_pkts
) > PCC_P2_THRESHOLD
||
1054 dpi
->intr_cnt
> PCC_INTR_THRESHOLD
)
1055 jme_attempt_pcc(dpi
, PCC_P2
);
1057 jme_attempt_pcc(dpi
, PCC_P1
);
1059 if (unlikely(dpi
->attempt
!= dpi
->cur
&& dpi
->cnt
> 5)) {
1060 if (dpi
->attempt
< dpi
->cur
)
1061 tasklet_schedule(&jme
->rxclean_task
);
1062 jme_set_rx_pcc(jme
, dpi
->attempt
);
1063 dpi
->cur
= dpi
->attempt
;
1069 jme_start_pcc_timer(struct jme_adapter
*jme
)
1071 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1072 dpi
->last_bytes
= NET_STAT(jme
).rx_bytes
;
1073 dpi
->last_pkts
= NET_STAT(jme
).rx_packets
;
1075 jwrite32(jme
, JME_TMCSR
,
1076 TMCSR_EN
| ((0xFFFFFF - PCC_INTERVAL_US
) & TMCSR_CNT
));
1080 jme_stop_pcc_timer(struct jme_adapter
*jme
)
1082 jwrite32(jme
, JME_TMCSR
, 0);
1086 jme_shutdown_nic(struct jme_adapter
*jme
)
1090 phylink
= jme_linkstat_from_phy(jme
);
1092 if (!(phylink
& PHY_LINK_UP
)) {
1094 * Disable all interrupt before issue timer
1097 jwrite32(jme
, JME_TIMER2
, TMCSR_EN
| 0xFFFFFE);
1102 jme_pcc_tasklet(unsigned long arg
)
1104 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1105 struct net_device
*netdev
= jme
->dev
;
1107 if (unlikely(test_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
))) {
1108 jme_shutdown_nic(jme
);
1112 if (unlikely(!netif_carrier_ok(netdev
) ||
1113 (atomic_read(&jme
->link_changing
) != 1)
1115 jme_stop_pcc_timer(jme
);
1119 if (!(test_bit(JME_FLAG_POLL
, &jme
->flags
)))
1120 jme_dynamic_pcc(jme
);
1122 jme_start_pcc_timer(jme
);
1126 jme_polling_mode(struct jme_adapter
*jme
)
1128 jme_set_rx_pcc(jme
, PCC_OFF
);
1132 jme_interrupt_mode(struct jme_adapter
*jme
)
1134 jme_set_rx_pcc(jme
, PCC_P1
);
1138 jme_pseudo_hotplug_enabled(struct jme_adapter
*jme
)
1141 apmc
= jread32(jme
, JME_APMC
);
1142 return apmc
& JME_APMC_PSEUDO_HP_EN
;
1146 jme_start_shutdown_timer(struct jme_adapter
*jme
)
1150 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PCIE_SD_EN
;
1151 apmc
&= ~JME_APMC_EPIEN_CTRL
;
1153 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_EN
);
1156 jwrite32f(jme
, JME_APMC
, apmc
);
1158 jwrite32f(jme
, JME_TIMER2
, 0);
1159 set_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1160 jwrite32(jme
, JME_TMCSR
,
1161 TMCSR_EN
| ((0xFFFFFF - APMC_PHP_SHUTDOWN_DELAY
) & TMCSR_CNT
));
1165 jme_stop_shutdown_timer(struct jme_adapter
*jme
)
1169 jwrite32f(jme
, JME_TMCSR
, 0);
1170 jwrite32f(jme
, JME_TIMER2
, 0);
1171 clear_bit(JME_FLAG_SHUTDOWN
, &jme
->flags
);
1173 apmc
= jread32(jme
, JME_APMC
);
1174 apmc
&= ~(JME_APMC_PCIE_SD_EN
| JME_APMC_EPIEN_CTRL
);
1175 jwrite32f(jme
, JME_APMC
, apmc
| JME_APMC_EPIEN_CTRL_DIS
);
1177 jwrite32f(jme
, JME_APMC
, apmc
);
1181 jme_link_change_tasklet(unsigned long arg
)
1183 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1184 struct net_device
*netdev
= jme
->dev
;
1187 while (!atomic_dec_and_test(&jme
->link_changing
)) {
1188 atomic_inc(&jme
->link_changing
);
1189 netif_info(jme
, intr
, jme
->dev
, "Get link change lock failed\n");
1190 while (atomic_read(&jme
->link_changing
) != 1)
1191 netif_info(jme
, intr
, jme
->dev
, "Waiting link change lock\n");
1194 if (jme_check_link(netdev
, 1) && jme
->old_mtu
== netdev
->mtu
)
1197 jme
->old_mtu
= netdev
->mtu
;
1198 netif_stop_queue(netdev
);
1199 if (jme_pseudo_hotplug_enabled(jme
))
1200 jme_stop_shutdown_timer(jme
);
1202 jme_stop_pcc_timer(jme
);
1203 tasklet_disable(&jme
->txclean_task
);
1204 tasklet_disable(&jme
->rxclean_task
);
1205 tasklet_disable(&jme
->rxempty_task
);
1207 if (netif_carrier_ok(netdev
)) {
1208 jme_reset_ghc_speed(jme
);
1209 jme_disable_rx_engine(jme
);
1210 jme_disable_tx_engine(jme
);
1211 jme_reset_mac_processor(jme
);
1212 jme_free_rx_resources(jme
);
1213 jme_free_tx_resources(jme
);
1215 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1216 jme_polling_mode(jme
);
1218 netif_carrier_off(netdev
);
1221 jme_check_link(netdev
, 0);
1222 if (netif_carrier_ok(netdev
)) {
1223 rc
= jme_setup_rx_resources(jme
);
1225 pr_err("Allocating resources for RX error, Device STOPPED!\n");
1226 goto out_enable_tasklet
;
1229 rc
= jme_setup_tx_resources(jme
);
1231 pr_err("Allocating resources for TX error, Device STOPPED!\n");
1232 goto err_out_free_rx_resources
;
1235 jme_enable_rx_engine(jme
);
1236 jme_enable_tx_engine(jme
);
1238 netif_start_queue(netdev
);
1240 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
1241 jme_interrupt_mode(jme
);
1243 jme_start_pcc_timer(jme
);
1244 } else if (jme_pseudo_hotplug_enabled(jme
)) {
1245 jme_start_shutdown_timer(jme
);
1248 goto out_enable_tasklet
;
1250 err_out_free_rx_resources
:
1251 jme_free_rx_resources(jme
);
1253 tasklet_enable(&jme
->txclean_task
);
1254 tasklet_hi_enable(&jme
->rxclean_task
);
1255 tasklet_hi_enable(&jme
->rxempty_task
);
1257 atomic_inc(&jme
->link_changing
);
1261 jme_rx_clean_tasklet(unsigned long arg
)
1263 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1264 struct dynpcc_info
*dpi
= &(jme
->dpi
);
1266 jme_process_receive(jme
, jme
->rx_ring_size
);
1272 jme_poll(JME_NAPI_HOLDER(holder
), JME_NAPI_WEIGHT(budget
))
1274 struct jme_adapter
*jme
= jme_napi_priv(holder
);
1277 rest
= jme_process_receive(jme
, JME_NAPI_WEIGHT_VAL(budget
));
1279 while (atomic_read(&jme
->rx_empty
) > 0) {
1280 atomic_dec(&jme
->rx_empty
);
1281 ++(NET_STAT(jme
).rx_dropped
);
1282 jme_restart_rx_engine(jme
);
1284 atomic_inc(&jme
->rx_empty
);
1287 JME_RX_COMPLETE(netdev
, holder
);
1288 jme_interrupt_mode(jme
);
1291 JME_NAPI_WEIGHT_SET(budget
, rest
);
1292 return JME_NAPI_WEIGHT_VAL(budget
) - rest
;
1296 jme_rx_empty_tasklet(unsigned long arg
)
1298 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1300 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1303 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1306 netif_info(jme
, rx_status
, jme
->dev
, "RX Queue Full!\n");
1308 jme_rx_clean_tasklet(arg
);
1310 while (atomic_read(&jme
->rx_empty
) > 0) {
1311 atomic_dec(&jme
->rx_empty
);
1312 ++(NET_STAT(jme
).rx_dropped
);
1313 jme_restart_rx_engine(jme
);
1315 atomic_inc(&jme
->rx_empty
);
1319 jme_wake_queue_if_stopped(struct jme_adapter
*jme
)
1321 struct jme_ring
*txring
= &(jme
->txring
[0]);
1324 if (unlikely(netif_queue_stopped(jme
->dev
) &&
1325 atomic_read(&txring
->nr_free
) >= (jme
->tx_wake_threshold
))) {
1326 netif_info(jme
, tx_done
, jme
->dev
, "TX Queue Waked\n");
1327 netif_wake_queue(jme
->dev
);
1333 jme_tx_clean_tasklet(unsigned long arg
)
1335 struct jme_adapter
*jme
= (struct jme_adapter
*)arg
;
1336 struct jme_ring
*txring
= &(jme
->txring
[0]);
1337 struct txdesc
*txdesc
= txring
->desc
;
1338 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
, *ttxbi
;
1339 int i
, j
, cnt
= 0, max
, err
, mask
;
1341 tx_dbg(jme
, "Into txclean\n");
1343 if (unlikely(!atomic_dec_and_test(&jme
->tx_cleaning
)))
1346 if (unlikely(atomic_read(&jme
->link_changing
) != 1))
1349 if (unlikely(!netif_carrier_ok(jme
->dev
)))
1352 max
= jme
->tx_ring_size
- atomic_read(&txring
->nr_free
);
1353 mask
= jme
->tx_ring_mask
;
1355 for (i
= atomic_read(&txring
->next_to_clean
) ; cnt
< max
; ) {
1359 if (likely(ctxbi
->skb
&&
1360 !(txdesc
[i
].descwb
.flags
& TXWBFLAG_OWN
))) {
1362 tx_dbg(jme
, "txclean: %d+%d@%lu\n",
1363 i
, ctxbi
->nr_desc
, jiffies
);
1365 err
= txdesc
[i
].descwb
.flags
& TXWBFLAG_ALLERR
;
1367 for (j
= 1 ; j
< ctxbi
->nr_desc
; ++j
) {
1368 ttxbi
= txbi
+ ((i
+ j
) & (mask
));
1369 txdesc
[(i
+ j
) & (mask
)].dw
[0] = 0;
1371 pci_unmap_page(jme
->pdev
,
1380 dev_kfree_skb(ctxbi
->skb
);
1382 cnt
+= ctxbi
->nr_desc
;
1384 if (unlikely(err
)) {
1385 ++(NET_STAT(jme
).tx_carrier_errors
);
1387 ++(NET_STAT(jme
).tx_packets
);
1388 NET_STAT(jme
).tx_bytes
+= ctxbi
->len
;
1393 ctxbi
->start_xmit
= 0;
1399 i
= (i
+ ctxbi
->nr_desc
) & mask
;
1404 tx_dbg(jme
, "txclean: done %d@%lu\n", i
, jiffies
);
1405 atomic_set(&txring
->next_to_clean
, i
);
1406 atomic_add(cnt
, &txring
->nr_free
);
1408 jme_wake_queue_if_stopped(jme
);
1411 atomic_inc(&jme
->tx_cleaning
);
1415 jme_intr_msi(struct jme_adapter
*jme
, u32 intrstat
)
1420 jwrite32f(jme
, JME_IENC
, INTR_ENABLE
);
1422 if (intrstat
& (INTR_LINKCH
| INTR_SWINTR
)) {
1424 * Link change event is critical
1425 * all other events are ignored
1427 jwrite32(jme
, JME_IEVE
, intrstat
);
1428 tasklet_schedule(&jme
->linkch_task
);
1432 if (intrstat
& INTR_TMINTR
) {
1433 jwrite32(jme
, JME_IEVE
, INTR_TMINTR
);
1434 tasklet_schedule(&jme
->pcc_task
);
1437 if (intrstat
& (INTR_PCCTXTO
| INTR_PCCTX
)) {
1438 jwrite32(jme
, JME_IEVE
, INTR_PCCTXTO
| INTR_PCCTX
| INTR_TX0
);
1439 tasklet_schedule(&jme
->txclean_task
);
1442 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1443 jwrite32(jme
, JME_IEVE
, (intrstat
& (INTR_PCCRX0TO
|
1449 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
1450 if (intrstat
& INTR_RX0EMP
)
1451 atomic_inc(&jme
->rx_empty
);
1453 if ((intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
| INTR_RX0EMP
))) {
1454 if (likely(JME_RX_SCHEDULE_PREP(jme
))) {
1455 jme_polling_mode(jme
);
1456 JME_RX_SCHEDULE(jme
);
1460 if (intrstat
& INTR_RX0EMP
) {
1461 atomic_inc(&jme
->rx_empty
);
1462 tasklet_hi_schedule(&jme
->rxempty_task
);
1463 } else if (intrstat
& (INTR_PCCRX0TO
| INTR_PCCRX0
)) {
1464 tasklet_hi_schedule(&jme
->rxclean_task
);
1470 * Re-enable interrupt
1472 jwrite32f(jme
, JME_IENS
, INTR_ENABLE
);
1476 jme_intr(int irq
, void *dev_id
)
1478 struct net_device
*netdev
= dev_id
;
1479 struct jme_adapter
*jme
= netdev_priv(netdev
);
1482 intrstat
= jread32(jme
, JME_IEVE
);
1485 * Check if it's really an interrupt for us
1487 if (unlikely((intrstat
& INTR_ENABLE
) == 0))
1491 * Check if the device still exist
1493 if (unlikely(intrstat
== ~((typeof(intrstat
))0)))
1496 jme_intr_msi(jme
, intrstat
);
1502 jme_msi(int irq
, void *dev_id
)
1504 struct net_device
*netdev
= dev_id
;
1505 struct jme_adapter
*jme
= netdev_priv(netdev
);
1508 intrstat
= jread32(jme
, JME_IEVE
);
1510 jme_intr_msi(jme
, intrstat
);
1516 jme_reset_link(struct jme_adapter
*jme
)
1518 jwrite32(jme
, JME_TMCSR
, TMCSR_SWIT
);
1522 jme_restart_an(struct jme_adapter
*jme
)
1526 spin_lock_bh(&jme
->phy_lock
);
1527 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1528 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1529 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1530 spin_unlock_bh(&jme
->phy_lock
);
1534 jme_request_irq(struct jme_adapter
*jme
)
1537 struct net_device
*netdev
= jme
->dev
;
1538 irq_handler_t handler
= jme_intr
;
1539 int irq_flags
= IRQF_SHARED
;
1541 if (!pci_enable_msi(jme
->pdev
)) {
1542 set_bit(JME_FLAG_MSI
, &jme
->flags
);
1547 rc
= request_irq(jme
->pdev
->irq
, handler
, irq_flags
, netdev
->name
,
1551 "Unable to request %s interrupt (return: %d)\n",
1552 test_bit(JME_FLAG_MSI
, &jme
->flags
) ? "MSI" : "INTx",
1555 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1556 pci_disable_msi(jme
->pdev
);
1557 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1560 netdev
->irq
= jme
->pdev
->irq
;
1567 jme_free_irq(struct jme_adapter
*jme
)
1569 free_irq(jme
->pdev
->irq
, jme
->dev
);
1570 if (test_bit(JME_FLAG_MSI
, &jme
->flags
)) {
1571 pci_disable_msi(jme
->pdev
);
1572 clear_bit(JME_FLAG_MSI
, &jme
->flags
);
1573 jme
->dev
->irq
= jme
->pdev
->irq
;
1578 jme_new_phy_on(struct jme_adapter
*jme
)
1582 reg
= jread32(jme
, JME_PHY_PWR
);
1583 reg
&= ~(PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1584 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
);
1585 jwrite32(jme
, JME_PHY_PWR
, reg
);
1587 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1588 reg
&= ~PE1_GPREG0_PBG
;
1589 reg
|= PE1_GPREG0_ENBG
;
1590 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1594 jme_new_phy_off(struct jme_adapter
*jme
)
1598 reg
= jread32(jme
, JME_PHY_PWR
);
1599 reg
|= PHY_PWR_DWN1SEL
| PHY_PWR_DWN1SW
|
1600 PHY_PWR_DWN2
| PHY_PWR_CLKSEL
;
1601 jwrite32(jme
, JME_PHY_PWR
, reg
);
1603 pci_read_config_dword(jme
->pdev
, PCI_PRIV_PE1
, ®
);
1604 reg
&= ~PE1_GPREG0_PBG
;
1605 reg
|= PE1_GPREG0_PDD3COLD
;
1606 pci_write_config_dword(jme
->pdev
, PCI_PRIV_PE1
, reg
);
1610 jme_phy_on(struct jme_adapter
*jme
)
1614 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1615 bmcr
&= ~BMCR_PDOWN
;
1616 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1618 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1619 jme_new_phy_on(jme
);
1623 jme_phy_off(struct jme_adapter
*jme
)
1627 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1629 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, bmcr
);
1631 if (new_phy_power_ctrl(jme
->chip_main_rev
))
1632 jme_new_phy_off(jme
);
1636 jme_open(struct net_device
*netdev
)
1638 struct jme_adapter
*jme
= netdev_priv(netdev
);
1642 JME_NAPI_ENABLE(jme
);
1644 tasklet_enable(&jme
->linkch_task
);
1645 tasklet_enable(&jme
->txclean_task
);
1646 tasklet_hi_enable(&jme
->rxclean_task
);
1647 tasklet_hi_enable(&jme
->rxempty_task
);
1649 rc
= jme_request_irq(jme
);
1656 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
1657 jme_set_settings(netdev
, &jme
->old_ecmd
);
1659 jme_reset_phy_processor(jme
);
1661 jme_reset_link(jme
);
1666 netif_stop_queue(netdev
);
1667 netif_carrier_off(netdev
);
1672 jme_set_100m_half(struct jme_adapter
*jme
)
1677 bmcr
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
);
1678 tmp
= bmcr
& ~(BMCR_ANENABLE
| BMCR_SPEED100
|
1679 BMCR_SPEED1000
| BMCR_FULLDPLX
);
1680 tmp
|= BMCR_SPEED100
;
1683 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, MII_BMCR
, tmp
);
1686 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
| GHC_LINK_POLL
);
1688 jwrite32(jme
, JME_GHC
, GHC_SPEED_100M
);
1691 #define JME_WAIT_LINK_TIME 2000 /* 2000ms */
1693 jme_wait_link(struct jme_adapter
*jme
)
1695 u32 phylink
, to
= JME_WAIT_LINK_TIME
;
1698 phylink
= jme_linkstat_from_phy(jme
);
1699 while (!(phylink
& PHY_LINK_UP
) && (to
-= 10) > 0) {
1701 phylink
= jme_linkstat_from_phy(jme
);
1706 jme_powersave_phy(struct jme_adapter
*jme
)
1708 if (jme
->reg_pmcs
) {
1709 jme_set_100m_half(jme
);
1711 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
1714 jwrite32(jme
, JME_PMCS
, jme
->reg_pmcs
);
1721 jme_close(struct net_device
*netdev
)
1723 struct jme_adapter
*jme
= netdev_priv(netdev
);
1725 netif_stop_queue(netdev
);
1726 netif_carrier_off(netdev
);
1731 JME_NAPI_DISABLE(jme
);
1733 tasklet_disable(&jme
->linkch_task
);
1734 tasklet_disable(&jme
->txclean_task
);
1735 tasklet_disable(&jme
->rxclean_task
);
1736 tasklet_disable(&jme
->rxempty_task
);
1738 jme_reset_ghc_speed(jme
);
1739 jme_disable_rx_engine(jme
);
1740 jme_disable_tx_engine(jme
);
1741 jme_reset_mac_processor(jme
);
1742 jme_free_rx_resources(jme
);
1743 jme_free_tx_resources(jme
);
1751 jme_alloc_txdesc(struct jme_adapter
*jme
,
1752 struct sk_buff
*skb
)
1754 struct jme_ring
*txring
= &(jme
->txring
[0]);
1755 int idx
, nr_alloc
, mask
= jme
->tx_ring_mask
;
1757 idx
= txring
->next_to_use
;
1758 nr_alloc
= skb_shinfo(skb
)->nr_frags
+ 2;
1760 if (unlikely(atomic_read(&txring
->nr_free
) < nr_alloc
))
1763 atomic_sub(nr_alloc
, &txring
->nr_free
);
1765 txring
->next_to_use
= (txring
->next_to_use
+ nr_alloc
) & mask
;
1771 jme_fill_tx_map(struct pci_dev
*pdev
,
1772 struct txdesc
*txdesc
,
1773 struct jme_buffer_info
*txbi
,
1781 dmaaddr
= pci_map_page(pdev
,
1787 pci_dma_sync_single_for_device(pdev
,
1794 txdesc
->desc2
.flags
= TXFLAG_OWN
;
1795 txdesc
->desc2
.flags
|= (hidma
) ? TXFLAG_64BIT
: 0;
1796 txdesc
->desc2
.datalen
= cpu_to_le16(len
);
1797 txdesc
->desc2
.bufaddrh
= cpu_to_le32((__u64
)dmaaddr
>> 32);
1798 txdesc
->desc2
.bufaddrl
= cpu_to_le32(
1799 (__u64
)dmaaddr
& 0xFFFFFFFFUL
);
1801 txbi
->mapping
= dmaaddr
;
1806 jme_map_tx_skb(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
1808 struct jme_ring
*txring
= &(jme
->txring
[0]);
1809 struct txdesc
*txdesc
= txring
->desc
, *ctxdesc
;
1810 struct jme_buffer_info
*txbi
= txring
->bufinf
, *ctxbi
;
1811 u8 hidma
= jme
->dev
->features
& NETIF_F_HIGHDMA
;
1812 int i
, nr_frags
= skb_shinfo(skb
)->nr_frags
;
1813 int mask
= jme
->tx_ring_mask
;
1814 struct skb_frag_struct
*frag
;
1817 for (i
= 0 ; i
< nr_frags
; ++i
) {
1818 frag
= &skb_shinfo(skb
)->frags
[i
];
1819 ctxdesc
= txdesc
+ ((idx
+ i
+ 2) & (mask
));
1820 ctxbi
= txbi
+ ((idx
+ i
+ 2) & (mask
));
1822 jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, frag
->page
,
1823 frag
->page_offset
, frag
->size
, hidma
);
1826 len
= skb_is_nonlinear(skb
) ? skb_headlen(skb
) : skb
->len
;
1827 ctxdesc
= txdesc
+ ((idx
+ 1) & (mask
));
1828 ctxbi
= txbi
+ ((idx
+ 1) & (mask
));
1829 jme_fill_tx_map(jme
->pdev
, ctxdesc
, ctxbi
, virt_to_page(skb
->data
),
1830 offset_in_page(skb
->data
), len
, hidma
);
1835 jme_expand_header(struct jme_adapter
*jme
, struct sk_buff
*skb
)
1837 if (unlikely(skb_shinfo(skb
)->gso_size
&&
1838 skb_header_cloned(skb
) &&
1839 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
))) {
1848 jme_tx_tso(struct sk_buff
*skb
, __le16
*mss
, u8
*flags
)
1850 *mss
= cpu_to_le16(skb_shinfo(skb
)->gso_size
<< TXDESC_MSS_SHIFT
);
1852 *flags
|= TXFLAG_LSEN
;
1854 if (skb
->protocol
== htons(ETH_P_IP
)) {
1855 struct iphdr
*iph
= ip_hdr(skb
);
1858 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
1863 struct ipv6hdr
*ip6h
= ipv6_hdr(skb
);
1865 tcp_hdr(skb
)->check
= ~csum_ipv6_magic(&ip6h
->saddr
,
1878 jme_tx_csum(struct jme_adapter
*jme
, struct sk_buff
*skb
, u8
*flags
)
1880 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1883 switch (skb
->protocol
) {
1884 case htons(ETH_P_IP
):
1885 ip_proto
= ip_hdr(skb
)->protocol
;
1887 case htons(ETH_P_IPV6
):
1888 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1897 *flags
|= TXFLAG_TCPCS
;
1900 *flags
|= TXFLAG_UDPCS
;
1903 netif_err(jme
, tx_err
, jme
->dev
, "Error upper layer protocol\n");
1910 jme_tx_vlan(struct sk_buff
*skb
, __le16
*vlan
, u8
*flags
)
1912 if (vlan_tx_tag_present(skb
)) {
1913 *flags
|= TXFLAG_TAGON
;
1914 *vlan
= cpu_to_le16(vlan_tx_tag_get(skb
));
1919 jme_fill_tx_desc(struct jme_adapter
*jme
, struct sk_buff
*skb
, int idx
)
1921 struct jme_ring
*txring
= &(jme
->txring
[0]);
1922 struct txdesc
*txdesc
;
1923 struct jme_buffer_info
*txbi
;
1926 txdesc
= (struct txdesc
*)txring
->desc
+ idx
;
1927 txbi
= txring
->bufinf
+ idx
;
1933 txdesc
->desc1
.pktsize
= cpu_to_le16(skb
->len
);
1935 * Set OWN bit at final.
1936 * When kernel transmit faster than NIC.
1937 * And NIC trying to send this descriptor before we tell
1938 * it to start sending this TX queue.
1939 * Other fields are already filled correctly.
1942 flags
= TXFLAG_OWN
| TXFLAG_INT
;
1944 * Set checksum flags while not tso
1946 if (jme_tx_tso(skb
, &txdesc
->desc1
.mss
, &flags
))
1947 jme_tx_csum(jme
, skb
, &flags
);
1948 jme_tx_vlan(skb
, &txdesc
->desc1
.vlan
, &flags
);
1949 jme_map_tx_skb(jme
, skb
, idx
);
1950 txdesc
->desc1
.flags
= flags
;
1952 * Set tx buffer info after telling NIC to send
1953 * For better tx_clean timing
1956 txbi
->nr_desc
= skb_shinfo(skb
)->nr_frags
+ 2;
1958 txbi
->len
= skb
->len
;
1959 txbi
->start_xmit
= jiffies
;
1960 if (!txbi
->start_xmit
)
1961 txbi
->start_xmit
= (0UL-1);
1967 jme_stop_queue_if_full(struct jme_adapter
*jme
)
1969 struct jme_ring
*txring
= &(jme
->txring
[0]);
1970 struct jme_buffer_info
*txbi
= txring
->bufinf
;
1971 int idx
= atomic_read(&txring
->next_to_clean
);
1976 if (unlikely(atomic_read(&txring
->nr_free
) < (MAX_SKB_FRAGS
+2))) {
1977 netif_stop_queue(jme
->dev
);
1978 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Paused\n");
1980 if (atomic_read(&txring
->nr_free
)
1981 >= (jme
->tx_wake_threshold
)) {
1982 netif_wake_queue(jme
->dev
);
1983 netif_info(jme
, tx_queued
, jme
->dev
, "TX Queue Fast Waked\n");
1987 if (unlikely(txbi
->start_xmit
&&
1988 (jiffies
- txbi
->start_xmit
) >= TX_TIMEOUT
&&
1990 netif_stop_queue(jme
->dev
);
1991 netif_info(jme
, tx_queued
, jme
->dev
,
1992 "TX Queue Stopped %d@%lu\n", idx
, jiffies
);
1997 * This function is already protected by netif_tx_lock()
2001 jme_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
2003 struct jme_adapter
*jme
= netdev_priv(netdev
);
2006 if (unlikely(jme_expand_header(jme
, skb
))) {
2007 ++(NET_STAT(jme
).tx_dropped
);
2008 return NETDEV_TX_OK
;
2011 idx
= jme_alloc_txdesc(jme
, skb
);
2013 if (unlikely(idx
< 0)) {
2014 netif_stop_queue(netdev
);
2015 netif_err(jme
, tx_err
, jme
->dev
,
2016 "BUG! Tx ring full when queue awake!\n");
2018 return NETDEV_TX_BUSY
;
2021 jme_fill_tx_desc(jme
, skb
, idx
);
2023 jwrite32(jme
, JME_TXCS
, jme
->reg_txcs
|
2024 TXCS_SELECT_QUEUE0
|
2028 tx_dbg(jme
, "xmit: %d+%d@%lu\n",
2029 idx
, skb_shinfo(skb
)->nr_frags
+ 2, jiffies
);
2030 jme_stop_queue_if_full(jme
);
2032 return NETDEV_TX_OK
;
2036 jme_set_macaddr(struct net_device
*netdev
, void *p
)
2038 struct jme_adapter
*jme
= netdev_priv(netdev
);
2039 struct sockaddr
*addr
= p
;
2042 if (netif_running(netdev
))
2045 spin_lock_bh(&jme
->macaddr_lock
);
2046 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
2048 val
= (addr
->sa_data
[3] & 0xff) << 24 |
2049 (addr
->sa_data
[2] & 0xff) << 16 |
2050 (addr
->sa_data
[1] & 0xff) << 8 |
2051 (addr
->sa_data
[0] & 0xff);
2052 jwrite32(jme
, JME_RXUMA_LO
, val
);
2053 val
= (addr
->sa_data
[5] & 0xff) << 8 |
2054 (addr
->sa_data
[4] & 0xff);
2055 jwrite32(jme
, JME_RXUMA_HI
, val
);
2056 spin_unlock_bh(&jme
->macaddr_lock
);
2062 jme_set_multi(struct net_device
*netdev
)
2064 struct jme_adapter
*jme
= netdev_priv(netdev
);
2065 u32 mc_hash
[2] = {};
2067 spin_lock_bh(&jme
->rxmcs_lock
);
2069 jme
->reg_rxmcs
|= RXMCS_BRDFRAME
| RXMCS_UNIFRAME
;
2071 if (netdev
->flags
& IFF_PROMISC
) {
2072 jme
->reg_rxmcs
|= RXMCS_ALLFRAME
;
2073 } else if (netdev
->flags
& IFF_ALLMULTI
) {
2074 jme
->reg_rxmcs
|= RXMCS_ALLMULFRAME
;
2075 } else if (netdev
->flags
& IFF_MULTICAST
) {
2076 struct netdev_hw_addr
*ha
;
2079 jme
->reg_rxmcs
|= RXMCS_MULFRAME
| RXMCS_MULFILTERED
;
2080 netdev_for_each_mc_addr(ha
, netdev
) {
2081 bit_nr
= ether_crc(ETH_ALEN
, ha
->addr
) & 0x3F;
2082 mc_hash
[bit_nr
>> 5] |= 1 << (bit_nr
& 0x1F);
2085 jwrite32(jme
, JME_RXMCHT_LO
, mc_hash
[0]);
2086 jwrite32(jme
, JME_RXMCHT_HI
, mc_hash
[1]);
2090 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2092 spin_unlock_bh(&jme
->rxmcs_lock
);
2096 jme_change_mtu(struct net_device
*netdev
, int new_mtu
)
2098 struct jme_adapter
*jme
= netdev_priv(netdev
);
2100 if (new_mtu
== jme
->old_mtu
)
2103 if (((new_mtu
+ ETH_HLEN
) > MAX_ETHERNET_JUMBO_PACKET_SIZE
) ||
2104 ((new_mtu
) < IPV6_MIN_MTU
))
2107 if (new_mtu
> 4000) {
2108 jme
->reg_rxcs
&= ~RXCS_FIFOTHNP
;
2109 jme
->reg_rxcs
|= RXCS_FIFOTHNP_64QW
;
2110 jme_restart_rx_engine(jme
);
2112 jme
->reg_rxcs
&= ~RXCS_FIFOTHNP
;
2113 jme
->reg_rxcs
|= RXCS_FIFOTHNP_128QW
;
2114 jme_restart_rx_engine(jme
);
2117 if (new_mtu
> 1900) {
2118 netdev
->features
&= ~(NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
2119 NETIF_F_TSO
| NETIF_F_TSO6
);
2121 if (test_bit(JME_FLAG_TXCSUM
, &jme
->flags
))
2122 netdev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
2123 if (test_bit(JME_FLAG_TSO
, &jme
->flags
))
2124 netdev
->features
|= NETIF_F_TSO
| NETIF_F_TSO6
;
2127 netdev
->mtu
= new_mtu
;
2128 jme_reset_link(jme
);
2134 jme_tx_timeout(struct net_device
*netdev
)
2136 struct jme_adapter
*jme
= netdev_priv(netdev
);
2139 jme_reset_phy_processor(jme
);
2140 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
2141 jme_set_settings(netdev
, &jme
->old_ecmd
);
2144 * Force to Reset the link again
2146 jme_reset_link(jme
);
2149 static inline void jme_pause_rx(struct jme_adapter
*jme
)
2151 atomic_dec(&jme
->link_changing
);
2153 jme_set_rx_pcc(jme
, PCC_OFF
);
2154 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2155 JME_NAPI_DISABLE(jme
);
2157 tasklet_disable(&jme
->rxclean_task
);
2158 tasklet_disable(&jme
->rxempty_task
);
2162 static inline void jme_resume_rx(struct jme_adapter
*jme
)
2164 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2166 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2167 JME_NAPI_ENABLE(jme
);
2169 tasklet_hi_enable(&jme
->rxclean_task
);
2170 tasklet_hi_enable(&jme
->rxempty_task
);
2173 dpi
->attempt
= PCC_P1
;
2175 jme_set_rx_pcc(jme
, PCC_P1
);
2177 atomic_inc(&jme
->link_changing
);
2181 jme_vlan_rx_register(struct net_device
*netdev
, struct vlan_group
*grp
)
2183 struct jme_adapter
*jme
= netdev_priv(netdev
);
2191 jme_get_drvinfo(struct net_device
*netdev
,
2192 struct ethtool_drvinfo
*info
)
2194 struct jme_adapter
*jme
= netdev_priv(netdev
);
2196 strcpy(info
->driver
, DRV_NAME
);
2197 strcpy(info
->version
, DRV_VERSION
);
2198 strcpy(info
->bus_info
, pci_name(jme
->pdev
));
2202 jme_get_regs_len(struct net_device
*netdev
)
2208 mmapio_memcpy(struct jme_adapter
*jme
, u32
*p
, u32 reg
, int len
)
2212 for (i
= 0 ; i
< len
; i
+= 4)
2213 p
[i
>> 2] = jread32(jme
, reg
+ i
);
2217 mdio_memcpy(struct jme_adapter
*jme
, u32
*p
, int reg_nr
)
2220 u16
*p16
= (u16
*)p
;
2222 for (i
= 0 ; i
< reg_nr
; ++i
)
2223 p16
[i
] = jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, i
);
2227 jme_get_regs(struct net_device
*netdev
, struct ethtool_regs
*regs
, void *p
)
2229 struct jme_adapter
*jme
= netdev_priv(netdev
);
2230 u32
*p32
= (u32
*)p
;
2232 memset(p
, 0xFF, JME_REG_LEN
);
2235 mmapio_memcpy(jme
, p32
, JME_MAC
, JME_MAC_LEN
);
2238 mmapio_memcpy(jme
, p32
, JME_PHY
, JME_PHY_LEN
);
2241 mmapio_memcpy(jme
, p32
, JME_MISC
, JME_MISC_LEN
);
2244 mmapio_memcpy(jme
, p32
, JME_RSS
, JME_RSS_LEN
);
2247 mdio_memcpy(jme
, p32
, JME_PHY_REG_NR
);
2251 jme_get_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2253 struct jme_adapter
*jme
= netdev_priv(netdev
);
2255 ecmd
->tx_coalesce_usecs
= PCC_TX_TO
;
2256 ecmd
->tx_max_coalesced_frames
= PCC_TX_CNT
;
2258 if (test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2259 ecmd
->use_adaptive_rx_coalesce
= false;
2260 ecmd
->rx_coalesce_usecs
= 0;
2261 ecmd
->rx_max_coalesced_frames
= 0;
2265 ecmd
->use_adaptive_rx_coalesce
= true;
2267 switch (jme
->dpi
.cur
) {
2269 ecmd
->rx_coalesce_usecs
= PCC_P1_TO
;
2270 ecmd
->rx_max_coalesced_frames
= PCC_P1_CNT
;
2273 ecmd
->rx_coalesce_usecs
= PCC_P2_TO
;
2274 ecmd
->rx_max_coalesced_frames
= PCC_P2_CNT
;
2277 ecmd
->rx_coalesce_usecs
= PCC_P3_TO
;
2278 ecmd
->rx_max_coalesced_frames
= PCC_P3_CNT
;
2288 jme_set_coalesce(struct net_device
*netdev
, struct ethtool_coalesce
*ecmd
)
2290 struct jme_adapter
*jme
= netdev_priv(netdev
);
2291 struct dynpcc_info
*dpi
= &(jme
->dpi
);
2293 if (netif_running(netdev
))
2296 if (ecmd
->use_adaptive_rx_coalesce
&&
2297 test_bit(JME_FLAG_POLL
, &jme
->flags
)) {
2298 clear_bit(JME_FLAG_POLL
, &jme
->flags
);
2299 jme
->jme_rx
= netif_rx
;
2300 jme
->jme_vlan_rx
= vlan_hwaccel_rx
;
2302 dpi
->attempt
= PCC_P1
;
2304 jme_set_rx_pcc(jme
, PCC_P1
);
2305 jme_interrupt_mode(jme
);
2306 } else if (!(ecmd
->use_adaptive_rx_coalesce
) &&
2307 !(test_bit(JME_FLAG_POLL
, &jme
->flags
))) {
2308 set_bit(JME_FLAG_POLL
, &jme
->flags
);
2309 jme
->jme_rx
= netif_receive_skb
;
2310 jme
->jme_vlan_rx
= vlan_hwaccel_receive_skb
;
2311 jme_interrupt_mode(jme
);
2318 jme_get_pauseparam(struct net_device
*netdev
,
2319 struct ethtool_pauseparam
*ecmd
)
2321 struct jme_adapter
*jme
= netdev_priv(netdev
);
2324 ecmd
->tx_pause
= (jme
->reg_txpfc
& TXPFC_PF_EN
) != 0;
2325 ecmd
->rx_pause
= (jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0;
2327 spin_lock_bh(&jme
->phy_lock
);
2328 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2329 spin_unlock_bh(&jme
->phy_lock
);
2332 (val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0;
2336 jme_set_pauseparam(struct net_device
*netdev
,
2337 struct ethtool_pauseparam
*ecmd
)
2339 struct jme_adapter
*jme
= netdev_priv(netdev
);
2342 if (((jme
->reg_txpfc
& TXPFC_PF_EN
) != 0) ^
2343 (ecmd
->tx_pause
!= 0)) {
2346 jme
->reg_txpfc
|= TXPFC_PF_EN
;
2348 jme
->reg_txpfc
&= ~TXPFC_PF_EN
;
2350 jwrite32(jme
, JME_TXPFC
, jme
->reg_txpfc
);
2353 spin_lock_bh(&jme
->rxmcs_lock
);
2354 if (((jme
->reg_rxmcs
& RXMCS_FLOWCTRL
) != 0) ^
2355 (ecmd
->rx_pause
!= 0)) {
2358 jme
->reg_rxmcs
|= RXMCS_FLOWCTRL
;
2360 jme
->reg_rxmcs
&= ~RXMCS_FLOWCTRL
;
2362 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2364 spin_unlock_bh(&jme
->rxmcs_lock
);
2366 spin_lock_bh(&jme
->phy_lock
);
2367 val
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, MII_ADVERTISE
);
2368 if (((val
& (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
)) != 0) ^
2369 (ecmd
->autoneg
!= 0)) {
2372 val
|= (ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2374 val
&= ~(ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
2376 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
,
2377 MII_ADVERTISE
, val
);
2379 spin_unlock_bh(&jme
->phy_lock
);
2385 jme_get_wol(struct net_device
*netdev
,
2386 struct ethtool_wolinfo
*wol
)
2388 struct jme_adapter
*jme
= netdev_priv(netdev
);
2390 wol
->supported
= WAKE_MAGIC
| WAKE_PHY
;
2394 if (jme
->reg_pmcs
& (PMCS_LFEN
| PMCS_LREN
))
2395 wol
->wolopts
|= WAKE_PHY
;
2397 if (jme
->reg_pmcs
& PMCS_MFEN
)
2398 wol
->wolopts
|= WAKE_MAGIC
;
2403 jme_set_wol(struct net_device
*netdev
,
2404 struct ethtool_wolinfo
*wol
)
2406 struct jme_adapter
*jme
= netdev_priv(netdev
);
2408 if (wol
->wolopts
& (WAKE_MAGICSECURE
|
2417 if (wol
->wolopts
& WAKE_PHY
)
2418 jme
->reg_pmcs
|= PMCS_LFEN
| PMCS_LREN
;
2420 if (wol
->wolopts
& WAKE_MAGIC
)
2421 jme
->reg_pmcs
|= PMCS_MFEN
;
2423 jwrite32(jme
, JME_PMCS
, jme
->reg_pmcs
);
2429 jme_get_settings(struct net_device
*netdev
,
2430 struct ethtool_cmd
*ecmd
)
2432 struct jme_adapter
*jme
= netdev_priv(netdev
);
2435 spin_lock_bh(&jme
->phy_lock
);
2436 rc
= mii_ethtool_gset(&(jme
->mii_if
), ecmd
);
2437 spin_unlock_bh(&jme
->phy_lock
);
2442 jme_set_settings(struct net_device
*netdev
,
2443 struct ethtool_cmd
*ecmd
)
2445 struct jme_adapter
*jme
= netdev_priv(netdev
);
2448 if (ecmd
->speed
== SPEED_1000
&& ecmd
->autoneg
!= AUTONEG_ENABLE
)
2452 * Check If user changed duplex only while force_media.
2453 * Hardware would not generate link change interrupt.
2455 if (jme
->mii_if
.force_media
&&
2456 ecmd
->autoneg
!= AUTONEG_ENABLE
&&
2457 (jme
->mii_if
.full_duplex
!= ecmd
->duplex
))
2460 spin_lock_bh(&jme
->phy_lock
);
2461 rc
= mii_ethtool_sset(&(jme
->mii_if
), ecmd
);
2462 spin_unlock_bh(&jme
->phy_lock
);
2466 jme_reset_link(jme
);
2467 jme
->old_ecmd
= *ecmd
;
2468 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2475 jme_ioctl(struct net_device
*netdev
, struct ifreq
*rq
, int cmd
)
2478 struct jme_adapter
*jme
= netdev_priv(netdev
);
2479 struct mii_ioctl_data
*mii_data
= if_mii(rq
);
2480 unsigned int duplex_chg
;
2482 if (cmd
== SIOCSMIIREG
) {
2483 u16 val
= mii_data
->val_in
;
2484 if (!(val
& (BMCR_RESET
|BMCR_ANENABLE
)) &&
2485 (val
& BMCR_SPEED1000
))
2489 spin_lock_bh(&jme
->phy_lock
);
2490 rc
= generic_mii_ioctl(&jme
->mii_if
, mii_data
, cmd
, &duplex_chg
);
2491 spin_unlock_bh(&jme
->phy_lock
);
2493 if (!rc
&& (cmd
== SIOCSMIIREG
)) {
2495 jme_reset_link(jme
);
2496 jme_get_settings(netdev
, &jme
->old_ecmd
);
2497 set_bit(JME_FLAG_SSET
, &jme
->flags
);
2504 jme_get_link(struct net_device
*netdev
)
2506 struct jme_adapter
*jme
= netdev_priv(netdev
);
2507 return jread32(jme
, JME_PHY_LINK
) & PHY_LINK_UP
;
2511 jme_get_msglevel(struct net_device
*netdev
)
2513 struct jme_adapter
*jme
= netdev_priv(netdev
);
2514 return jme
->msg_enable
;
2518 jme_set_msglevel(struct net_device
*netdev
, u32 value
)
2520 struct jme_adapter
*jme
= netdev_priv(netdev
);
2521 jme
->msg_enable
= value
;
2525 jme_get_rx_csum(struct net_device
*netdev
)
2527 struct jme_adapter
*jme
= netdev_priv(netdev
);
2528 return jme
->reg_rxmcs
& RXMCS_CHECKSUM
;
2532 jme_set_rx_csum(struct net_device
*netdev
, u32 on
)
2534 struct jme_adapter
*jme
= netdev_priv(netdev
);
2536 spin_lock_bh(&jme
->rxmcs_lock
);
2538 jme
->reg_rxmcs
|= RXMCS_CHECKSUM
;
2540 jme
->reg_rxmcs
&= ~RXMCS_CHECKSUM
;
2541 jwrite32(jme
, JME_RXMCS
, jme
->reg_rxmcs
);
2542 spin_unlock_bh(&jme
->rxmcs_lock
);
2548 jme_set_tx_csum(struct net_device
*netdev
, u32 on
)
2550 struct jme_adapter
*jme
= netdev_priv(netdev
);
2553 set_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2554 if (netdev
->mtu
<= 1900)
2556 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
2558 clear_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2560 ~(NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
);
2567 jme_set_tso(struct net_device
*netdev
, u32 on
)
2569 struct jme_adapter
*jme
= netdev_priv(netdev
);
2572 set_bit(JME_FLAG_TSO
, &jme
->flags
);
2573 if (netdev
->mtu
<= 1900)
2574 netdev
->features
|= NETIF_F_TSO
| NETIF_F_TSO6
;
2576 clear_bit(JME_FLAG_TSO
, &jme
->flags
);
2577 netdev
->features
&= ~(NETIF_F_TSO
| NETIF_F_TSO6
);
2584 jme_nway_reset(struct net_device
*netdev
)
2586 struct jme_adapter
*jme
= netdev_priv(netdev
);
2587 jme_restart_an(jme
);
2592 jme_smb_read(struct jme_adapter
*jme
, unsigned int addr
)
2597 val
= jread32(jme
, JME_SMBCSR
);
2598 to
= JME_SMB_BUSY_TIMEOUT
;
2599 while ((val
& SMBCSR_BUSY
) && --to
) {
2601 val
= jread32(jme
, JME_SMBCSR
);
2604 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2608 jwrite32(jme
, JME_SMBINTF
,
2609 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2610 SMBINTF_HWRWN_READ
|
2613 val
= jread32(jme
, JME_SMBINTF
);
2614 to
= JME_SMB_BUSY_TIMEOUT
;
2615 while ((val
& SMBINTF_HWCMD
) && --to
) {
2617 val
= jread32(jme
, JME_SMBINTF
);
2620 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2624 return (val
& SMBINTF_HWDATR
) >> SMBINTF_HWDATR_SHIFT
;
2628 jme_smb_write(struct jme_adapter
*jme
, unsigned int addr
, u8 data
)
2633 val
= jread32(jme
, JME_SMBCSR
);
2634 to
= JME_SMB_BUSY_TIMEOUT
;
2635 while ((val
& SMBCSR_BUSY
) && --to
) {
2637 val
= jread32(jme
, JME_SMBCSR
);
2640 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2644 jwrite32(jme
, JME_SMBINTF
,
2645 ((data
<< SMBINTF_HWDATW_SHIFT
) & SMBINTF_HWDATW
) |
2646 ((addr
<< SMBINTF_HWADDR_SHIFT
) & SMBINTF_HWADDR
) |
2647 SMBINTF_HWRWN_WRITE
|
2650 val
= jread32(jme
, JME_SMBINTF
);
2651 to
= JME_SMB_BUSY_TIMEOUT
;
2652 while ((val
& SMBINTF_HWCMD
) && --to
) {
2654 val
= jread32(jme
, JME_SMBINTF
);
2657 netif_err(jme
, hw
, jme
->dev
, "SMB Bus Busy\n");
2665 jme_get_eeprom_len(struct net_device
*netdev
)
2667 struct jme_adapter
*jme
= netdev_priv(netdev
);
2669 val
= jread32(jme
, JME_SMBCSR
);
2670 return (val
& SMBCSR_EEPROMD
) ? JME_SMB_LEN
: 0;
2674 jme_get_eeprom(struct net_device
*netdev
,
2675 struct ethtool_eeprom
*eeprom
, u8
*data
)
2677 struct jme_adapter
*jme
= netdev_priv(netdev
);
2678 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2681 * ethtool will check the boundary for us
2683 eeprom
->magic
= JME_EEPROM_MAGIC
;
2684 for (i
= 0 ; i
< len
; ++i
)
2685 data
[i
] = jme_smb_read(jme
, i
+ offset
);
2691 jme_set_eeprom(struct net_device
*netdev
,
2692 struct ethtool_eeprom
*eeprom
, u8
*data
)
2694 struct jme_adapter
*jme
= netdev_priv(netdev
);
2695 int i
, offset
= eeprom
->offset
, len
= eeprom
->len
;
2697 if (eeprom
->magic
!= JME_EEPROM_MAGIC
)
2701 * ethtool will check the boundary for us
2703 for (i
= 0 ; i
< len
; ++i
)
2704 jme_smb_write(jme
, i
+ offset
, data
[i
]);
2709 static const struct ethtool_ops jme_ethtool_ops
= {
2710 .get_drvinfo
= jme_get_drvinfo
,
2711 .get_regs_len
= jme_get_regs_len
,
2712 .get_regs
= jme_get_regs
,
2713 .get_coalesce
= jme_get_coalesce
,
2714 .set_coalesce
= jme_set_coalesce
,
2715 .get_pauseparam
= jme_get_pauseparam
,
2716 .set_pauseparam
= jme_set_pauseparam
,
2717 .get_wol
= jme_get_wol
,
2718 .set_wol
= jme_set_wol
,
2719 .get_settings
= jme_get_settings
,
2720 .set_settings
= jme_set_settings
,
2721 .get_link
= jme_get_link
,
2722 .get_msglevel
= jme_get_msglevel
,
2723 .set_msglevel
= jme_set_msglevel
,
2724 .get_rx_csum
= jme_get_rx_csum
,
2725 .set_rx_csum
= jme_set_rx_csum
,
2726 .set_tx_csum
= jme_set_tx_csum
,
2727 .set_tso
= jme_set_tso
,
2728 .set_sg
= ethtool_op_set_sg
,
2729 .nway_reset
= jme_nway_reset
,
2730 .get_eeprom_len
= jme_get_eeprom_len
,
2731 .get_eeprom
= jme_get_eeprom
,
2732 .set_eeprom
= jme_set_eeprom
,
2736 jme_pci_dma64(struct pci_dev
*pdev
)
2738 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2739 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(64)))
2740 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64)))
2743 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
&&
2744 !pci_set_dma_mask(pdev
, DMA_BIT_MASK(40)))
2745 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40)))
2748 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(32)))
2749 if (!pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32)))
2756 jme_phy_init(struct jme_adapter
*jme
)
2760 reg26
= jme_mdio_read(jme
->dev
, jme
->mii_if
.phy_id
, 26);
2761 jme_mdio_write(jme
->dev
, jme
->mii_if
.phy_id
, 26, reg26
| 0x1000);
2765 jme_check_hw_ver(struct jme_adapter
*jme
)
2769 chipmode
= jread32(jme
, JME_CHIPMODE
);
2771 jme
->fpgaver
= (chipmode
& CM_FPGAVER_MASK
) >> CM_FPGAVER_SHIFT
;
2772 jme
->chiprev
= (chipmode
& CM_CHIPREV_MASK
) >> CM_CHIPREV_SHIFT
;
2773 jme
->chip_main_rev
= jme
->chiprev
& 0xF;
2774 jme
->chip_sub_rev
= (jme
->chiprev
>> 4) & 0xF;
2777 static const struct net_device_ops jme_netdev_ops
= {
2778 .ndo_open
= jme_open
,
2779 .ndo_stop
= jme_close
,
2780 .ndo_validate_addr
= eth_validate_addr
,
2781 .ndo_do_ioctl
= jme_ioctl
,
2782 .ndo_start_xmit
= jme_start_xmit
,
2783 .ndo_set_mac_address
= jme_set_macaddr
,
2784 .ndo_set_multicast_list
= jme_set_multi
,
2785 .ndo_change_mtu
= jme_change_mtu
,
2786 .ndo_tx_timeout
= jme_tx_timeout
,
2787 .ndo_vlan_rx_register
= jme_vlan_rx_register
,
2790 static int __devinit
2791 jme_init_one(struct pci_dev
*pdev
,
2792 const struct pci_device_id
*ent
)
2794 int rc
= 0, using_dac
, i
;
2795 struct net_device
*netdev
;
2796 struct jme_adapter
*jme
;
2801 * set up PCI device basics
2803 rc
= pci_enable_device(pdev
);
2805 pr_err("Cannot enable PCI device\n");
2809 using_dac
= jme_pci_dma64(pdev
);
2810 if (using_dac
< 0) {
2811 pr_err("Cannot set PCI DMA Mask\n");
2813 goto err_out_disable_pdev
;
2816 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
2817 pr_err("No PCI resource region found\n");
2819 goto err_out_disable_pdev
;
2822 rc
= pci_request_regions(pdev
, DRV_NAME
);
2824 pr_err("Cannot obtain PCI resource region\n");
2825 goto err_out_disable_pdev
;
2828 pci_set_master(pdev
);
2831 * alloc and init net device
2833 netdev
= alloc_etherdev(sizeof(*jme
));
2835 pr_err("Cannot allocate netdev structure\n");
2837 goto err_out_release_regions
;
2839 netdev
->netdev_ops
= &jme_netdev_ops
;
2840 netdev
->ethtool_ops
= &jme_ethtool_ops
;
2841 netdev
->watchdog_timeo
= TX_TIMEOUT
;
2842 netdev
->features
= NETIF_F_IP_CSUM
|
2847 NETIF_F_HW_VLAN_TX
|
2850 netdev
->features
|= NETIF_F_HIGHDMA
;
2852 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
2853 pci_set_drvdata(pdev
, netdev
);
2858 jme
= netdev_priv(netdev
);
2861 jme
->jme_rx
= netif_rx
;
2862 jme
->jme_vlan_rx
= vlan_hwaccel_rx
;
2863 jme
->old_mtu
= netdev
->mtu
= 1500;
2865 jme
->tx_ring_size
= 1 << 10;
2866 jme
->tx_ring_mask
= jme
->tx_ring_size
- 1;
2867 jme
->tx_wake_threshold
= 1 << 9;
2868 jme
->rx_ring_size
= 1 << 9;
2869 jme
->rx_ring_mask
= jme
->rx_ring_size
- 1;
2870 jme
->msg_enable
= JME_DEF_MSG_ENABLE
;
2871 jme
->regs
= ioremap(pci_resource_start(pdev
, 0),
2872 pci_resource_len(pdev
, 0));
2874 pr_err("Mapping PCI resource region error\n");
2876 goto err_out_free_netdev
;
2880 apmc
= jread32(jme
, JME_APMC
) & ~JME_APMC_PSEUDO_HP_EN
;
2881 jwrite32(jme
, JME_APMC
, apmc
);
2882 } else if (force_pseudohp
) {
2883 apmc
= jread32(jme
, JME_APMC
) | JME_APMC_PSEUDO_HP_EN
;
2884 jwrite32(jme
, JME_APMC
, apmc
);
2887 NETIF_NAPI_SET(netdev
, &jme
->napi
, jme_poll
, jme
->rx_ring_size
>> 2)
2889 spin_lock_init(&jme
->phy_lock
);
2890 spin_lock_init(&jme
->macaddr_lock
);
2891 spin_lock_init(&jme
->rxmcs_lock
);
2893 atomic_set(&jme
->link_changing
, 1);
2894 atomic_set(&jme
->rx_cleaning
, 1);
2895 atomic_set(&jme
->tx_cleaning
, 1);
2896 atomic_set(&jme
->rx_empty
, 1);
2898 tasklet_init(&jme
->pcc_task
,
2900 (unsigned long) jme
);
2901 tasklet_init(&jme
->linkch_task
,
2902 jme_link_change_tasklet
,
2903 (unsigned long) jme
);
2904 tasklet_init(&jme
->txclean_task
,
2905 jme_tx_clean_tasklet
,
2906 (unsigned long) jme
);
2907 tasklet_init(&jme
->rxclean_task
,
2908 jme_rx_clean_tasklet
,
2909 (unsigned long) jme
);
2910 tasklet_init(&jme
->rxempty_task
,
2911 jme_rx_empty_tasklet
,
2912 (unsigned long) jme
);
2913 tasklet_disable_nosync(&jme
->linkch_task
);
2914 tasklet_disable_nosync(&jme
->txclean_task
);
2915 tasklet_disable_nosync(&jme
->rxclean_task
);
2916 tasklet_disable_nosync(&jme
->rxempty_task
);
2917 jme
->dpi
.cur
= PCC_P1
;
2920 jme
->reg_rxcs
= RXCS_DEFAULT
;
2921 jme
->reg_rxmcs
= RXMCS_DEFAULT
;
2923 jme
->reg_pmcs
= PMCS_MFEN
;
2924 set_bit(JME_FLAG_TXCSUM
, &jme
->flags
);
2925 set_bit(JME_FLAG_TSO
, &jme
->flags
);
2928 * Get Max Read Req Size from PCI Config Space
2930 pci_read_config_byte(pdev
, PCI_DCSR_MRRS
, &jme
->mrrs
);
2931 jme
->mrrs
&= PCI_DCSR_MRRS_MASK
;
2932 switch (jme
->mrrs
) {
2934 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_128B
;
2937 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_256B
;
2940 jme
->reg_txcs
= TXCS_DEFAULT
| TXCS_DMASIZE_512B
;
2945 * Must check before reset_mac_processor
2947 jme_check_hw_ver(jme
);
2948 jme
->mii_if
.dev
= netdev
;
2950 jme
->mii_if
.phy_id
= 0;
2951 for (i
= 1 ; i
< 32 ; ++i
) {
2952 bmcr
= jme_mdio_read(netdev
, i
, MII_BMCR
);
2953 bmsr
= jme_mdio_read(netdev
, i
, MII_BMSR
);
2954 if (bmcr
!= 0xFFFFU
&& (bmcr
!= 0 || bmsr
!= 0)) {
2955 jme
->mii_if
.phy_id
= i
;
2960 if (!jme
->mii_if
.phy_id
) {
2962 pr_err("Can not find phy_id\n");
2966 jme
->reg_ghc
|= GHC_LINK_POLL
;
2968 jme
->mii_if
.phy_id
= 1;
2970 if (pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
)
2971 jme
->mii_if
.supports_gmii
= true;
2973 jme
->mii_if
.supports_gmii
= false;
2974 jme
->mii_if
.phy_id_mask
= 0x1F;
2975 jme
->mii_if
.reg_num_mask
= 0x1F;
2976 jme
->mii_if
.mdio_read
= jme_mdio_read
;
2977 jme
->mii_if
.mdio_write
= jme_mdio_write
;
2980 jme_set_phyfifo_5level(jme
);
2981 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &jme
->pcirev
);
2987 * Reset MAC processor and reload EEPROM for MAC Address
2989 jme_reset_mac_processor(jme
);
2990 rc
= jme_reload_eeprom(jme
);
2992 pr_err("Reload eeprom for reading MAC Address error\n");
2995 jme_load_macaddr(netdev
);
2998 * Tell stack that we are not ready to work until open()
3000 netif_carrier_off(netdev
);
3002 rc
= register_netdev(netdev
);
3004 pr_err("Cannot register net device\n");
3008 netif_info(jme
, probe
, jme
->dev
, "%s%s chiprev:%x pcirev:%x macaddr:%pM\n",
3009 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC250
) ?
3010 "JMC250 Gigabit Ethernet" :
3011 (jme
->pdev
->device
== PCI_DEVICE_ID_JMICRON_JMC260
) ?
3012 "JMC260 Fast Ethernet" : "Unknown",
3013 (jme
->fpgaver
!= 0) ? " (FPGA)" : "",
3014 (jme
->fpgaver
!= 0) ? jme
->fpgaver
: jme
->chiprev
,
3015 jme
->pcirev
, netdev
->dev_addr
);
3021 err_out_free_netdev
:
3022 pci_set_drvdata(pdev
, NULL
);
3023 free_netdev(netdev
);
3024 err_out_release_regions
:
3025 pci_release_regions(pdev
);
3026 err_out_disable_pdev
:
3027 pci_disable_device(pdev
);
3032 static void __devexit
3033 jme_remove_one(struct pci_dev
*pdev
)
3035 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3036 struct jme_adapter
*jme
= netdev_priv(netdev
);
3038 unregister_netdev(netdev
);
3040 pci_set_drvdata(pdev
, NULL
);
3041 free_netdev(netdev
);
3042 pci_release_regions(pdev
);
3043 pci_disable_device(pdev
);
3048 jme_shutdown(struct pci_dev
*pdev
)
3050 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3051 struct jme_adapter
*jme
= netdev_priv(netdev
);
3053 jme_powersave_phy(jme
);
3054 pci_pme_active(pdev
, true);
3059 jme_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3061 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3062 struct jme_adapter
*jme
= netdev_priv(netdev
);
3064 atomic_dec(&jme
->link_changing
);
3066 netif_device_detach(netdev
);
3067 netif_stop_queue(netdev
);
3070 tasklet_disable(&jme
->txclean_task
);
3071 tasklet_disable(&jme
->rxclean_task
);
3072 tasklet_disable(&jme
->rxempty_task
);
3074 if (netif_carrier_ok(netdev
)) {
3075 if (test_bit(JME_FLAG_POLL
, &jme
->flags
))
3076 jme_polling_mode(jme
);
3078 jme_stop_pcc_timer(jme
);
3079 jme_reset_ghc_speed(jme
);
3080 jme_disable_rx_engine(jme
);
3081 jme_disable_tx_engine(jme
);
3082 jme_reset_mac_processor(jme
);
3083 jme_free_rx_resources(jme
);
3084 jme_free_tx_resources(jme
);
3085 netif_carrier_off(netdev
);
3089 tasklet_enable(&jme
->txclean_task
);
3090 tasklet_hi_enable(&jme
->rxclean_task
);
3091 tasklet_hi_enable(&jme
->rxempty_task
);
3093 pci_save_state(pdev
);
3094 jme_powersave_phy(jme
);
3095 pci_enable_wake(jme
->pdev
, PCI_D3hot
, true);
3096 pci_set_power_state(pdev
, PCI_D3hot
);
3102 jme_resume(struct pci_dev
*pdev
)
3104 struct net_device
*netdev
= pci_get_drvdata(pdev
);
3105 struct jme_adapter
*jme
= netdev_priv(netdev
);
3108 pci_restore_state(pdev
);
3111 if (test_bit(JME_FLAG_SSET
, &jme
->flags
))
3112 jme_set_settings(netdev
, &jme
->old_ecmd
);
3114 jme_reset_phy_processor(jme
);
3117 netif_device_attach(netdev
);
3119 atomic_inc(&jme
->link_changing
);
3121 jme_reset_link(jme
);
3127 static DEFINE_PCI_DEVICE_TABLE(jme_pci_tbl
) = {
3128 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC250
) },
3129 { PCI_VDEVICE(JMICRON
, PCI_DEVICE_ID_JMICRON_JMC260
) },
3133 static struct pci_driver jme_driver
= {
3135 .id_table
= jme_pci_tbl
,
3136 .probe
= jme_init_one
,
3137 .remove
= __devexit_p(jme_remove_one
),
3139 .suspend
= jme_suspend
,
3140 .resume
= jme_resume
,
3141 #endif /* CONFIG_PM */
3142 .shutdown
= jme_shutdown
,
3146 jme_init_module(void)
3148 pr_info("JMicron JMC2XX ethernet driver version %s\n", DRV_VERSION
);
3149 return pci_register_driver(&jme_driver
);
3153 jme_cleanup_module(void)
3155 pci_unregister_driver(&jme_driver
);
3158 module_init(jme_init_module
);
3159 module_exit(jme_cleanup_module
);
3161 MODULE_AUTHOR("Guo-Fu Tseng <cooldavid@cooldavid.org>");
3162 MODULE_DESCRIPTION("JMicron JMC2x0 PCI Express Ethernet driver");
3163 MODULE_LICENSE("GPL");
3164 MODULE_VERSION(DRV_VERSION
);
3165 MODULE_DEVICE_TABLE(pci
, jme_pci_tbl
);