2 * drivers/net/ks8851_mll.c
3 * Copyright (c) 2009 Micrel Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 * KS8851 16bit MLL chip from Micrel Inc.
24 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26 #include <linux/interrupt.h>
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/netdevice.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/cache.h>
33 #include <linux/crc32.h>
34 #include <linux/mii.h>
35 #include <linux/platform_device.h>
36 #include <linux/delay.h>
37 #include <linux/slab.h>
39 #define DRV_NAME "ks8851_mll"
41 static u8 KS_DEFAULT_MAC_ADDRESS
[] = { 0x00, 0x10, 0xA1, 0x86, 0x95, 0x11 };
42 #define MAX_RECV_FRAMES 32
43 #define MAX_BUF_SIZE 2048
44 #define TX_BUF_SIZE 2000
45 #define RX_BUF_SIZE 2000
48 #define CCR_EEPROM (1 << 9)
49 #define CCR_SPI (1 << 8)
50 #define CCR_8BIT (1 << 7)
51 #define CCR_16BIT (1 << 6)
52 #define CCR_32BIT (1 << 5)
53 #define CCR_SHARED (1 << 4)
54 #define CCR_32PIN (1 << 0)
56 /* MAC address registers */
62 #define OBCR_ODS_16MA (1 << 6)
65 #define EEPCR_EESA (1 << 4)
66 #define EEPCR_EESB (1 << 3)
67 #define EEPCR_EEDO (1 << 2)
68 #define EEPCR_EESCK (1 << 1)
69 #define EEPCR_EECS (1 << 0)
72 #define MBIR_TXMBF (1 << 12)
73 #define MBIR_TXMBFA (1 << 11)
74 #define MBIR_RXMBF (1 << 4)
75 #define MBIR_RXMBFA (1 << 3)
78 #define GRR_QMU (1 << 1)
79 #define GRR_GSR (1 << 0)
82 #define WFCR_MPRXE (1 << 7)
83 #define WFCR_WF3E (1 << 3)
84 #define WFCR_WF2E (1 << 2)
85 #define WFCR_WF1E (1 << 1)
86 #define WFCR_WF0E (1 << 0)
88 #define KS_WF0CRC0 0x30
89 #define KS_WF0CRC1 0x32
90 #define KS_WF0BM0 0x34
91 #define KS_WF0BM1 0x36
92 #define KS_WF0BM2 0x38
93 #define KS_WF0BM3 0x3A
95 #define KS_WF1CRC0 0x40
96 #define KS_WF1CRC1 0x42
97 #define KS_WF1BM0 0x44
98 #define KS_WF1BM1 0x46
99 #define KS_WF1BM2 0x48
100 #define KS_WF1BM3 0x4A
102 #define KS_WF2CRC0 0x50
103 #define KS_WF2CRC1 0x52
104 #define KS_WF2BM0 0x54
105 #define KS_WF2BM1 0x56
106 #define KS_WF2BM2 0x58
107 #define KS_WF2BM3 0x5A
109 #define KS_WF3CRC0 0x60
110 #define KS_WF3CRC1 0x62
111 #define KS_WF3BM0 0x64
112 #define KS_WF3BM1 0x66
113 #define KS_WF3BM2 0x68
114 #define KS_WF3BM3 0x6A
117 #define TXCR_TCGICMP (1 << 8)
118 #define TXCR_TCGUDP (1 << 7)
119 #define TXCR_TCGTCP (1 << 6)
120 #define TXCR_TCGIP (1 << 5)
121 #define TXCR_FTXQ (1 << 4)
122 #define TXCR_TXFCE (1 << 3)
123 #define TXCR_TXPE (1 << 2)
124 #define TXCR_TXCRC (1 << 1)
125 #define TXCR_TXE (1 << 0)
128 #define TXSR_TXLC (1 << 13)
129 #define TXSR_TXMC (1 << 12)
130 #define TXSR_TXFID_MASK (0x3f << 0)
131 #define TXSR_TXFID_SHIFT (0)
132 #define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
135 #define KS_RXCR1 0x74
136 #define RXCR1_FRXQ (1 << 15)
137 #define RXCR1_RXUDPFCC (1 << 14)
138 #define RXCR1_RXTCPFCC (1 << 13)
139 #define RXCR1_RXIPFCC (1 << 12)
140 #define RXCR1_RXPAFMA (1 << 11)
141 #define RXCR1_RXFCE (1 << 10)
142 #define RXCR1_RXEFE (1 << 9)
143 #define RXCR1_RXMAFMA (1 << 8)
144 #define RXCR1_RXBE (1 << 7)
145 #define RXCR1_RXME (1 << 6)
146 #define RXCR1_RXUE (1 << 5)
147 #define RXCR1_RXAE (1 << 4)
148 #define RXCR1_RXINVF (1 << 1)
149 #define RXCR1_RXE (1 << 0)
150 #define RXCR1_FILTER_MASK (RXCR1_RXINVF | RXCR1_RXAE | \
151 RXCR1_RXMAFMA | RXCR1_RXPAFMA)
153 #define KS_RXCR2 0x76
154 #define RXCR2_SRDBL_MASK (0x7 << 5)
155 #define RXCR2_SRDBL_SHIFT (5)
156 #define RXCR2_SRDBL_4B (0x0 << 5)
157 #define RXCR2_SRDBL_8B (0x1 << 5)
158 #define RXCR2_SRDBL_16B (0x2 << 5)
159 #define RXCR2_SRDBL_32B (0x3 << 5)
160 /* #define RXCR2_SRDBL_FRAME (0x4 << 5) */
161 #define RXCR2_IUFFP (1 << 4)
162 #define RXCR2_RXIUFCEZ (1 << 3)
163 #define RXCR2_UDPLFE (1 << 2)
164 #define RXCR2_RXICMPFCC (1 << 1)
165 #define RXCR2_RXSAF (1 << 0)
167 #define KS_TXMIR 0x78
169 #define KS_RXFHSR 0x7C
170 #define RXFSHR_RXFV (1 << 15)
171 #define RXFSHR_RXICMPFCS (1 << 13)
172 #define RXFSHR_RXIPFCS (1 << 12)
173 #define RXFSHR_RXTCPFCS (1 << 11)
174 #define RXFSHR_RXUDPFCS (1 << 10)
175 #define RXFSHR_RXBF (1 << 7)
176 #define RXFSHR_RXMF (1 << 6)
177 #define RXFSHR_RXUF (1 << 5)
178 #define RXFSHR_RXMR (1 << 4)
179 #define RXFSHR_RXFT (1 << 3)
180 #define RXFSHR_RXFTL (1 << 2)
181 #define RXFSHR_RXRF (1 << 1)
182 #define RXFSHR_RXCE (1 << 0)
183 #define RXFSHR_ERR (RXFSHR_RXCE | RXFSHR_RXRF |\
184 RXFSHR_RXFTL | RXFSHR_RXMR |\
185 RXFSHR_RXICMPFCS | RXFSHR_RXIPFCS |\
187 #define KS_RXFHBCR 0x7E
188 #define RXFHBCR_CNT_MASK 0x0FFF
190 #define KS_TXQCR 0x80
191 #define TXQCR_AETFE (1 << 2)
192 #define TXQCR_TXQMAM (1 << 1)
193 #define TXQCR_METFE (1 << 0)
195 #define KS_RXQCR 0x82
196 #define RXQCR_RXDTTS (1 << 12)
197 #define RXQCR_RXDBCTS (1 << 11)
198 #define RXQCR_RXFCTS (1 << 10)
199 #define RXQCR_RXIPHTOE (1 << 9)
200 #define RXQCR_RXDTTE (1 << 7)
201 #define RXQCR_RXDBCTE (1 << 6)
202 #define RXQCR_RXFCTE (1 << 5)
203 #define RXQCR_ADRFE (1 << 4)
204 #define RXQCR_SDA (1 << 3)
205 #define RXQCR_RRXEF (1 << 0)
206 #define RXQCR_CMD_CNTL (RXQCR_RXFCTE|RXQCR_ADRFE)
208 #define KS_TXFDPR 0x84
209 #define TXFDPR_TXFPAI (1 << 14)
210 #define TXFDPR_TXFP_MASK (0x7ff << 0)
211 #define TXFDPR_TXFP_SHIFT (0)
213 #define KS_RXFDPR 0x86
214 #define RXFDPR_RXFPAI (1 << 14)
216 #define KS_RXDTTR 0x8C
217 #define KS_RXDBCTR 0x8E
221 #define IRQ_LCI (1 << 15)
222 #define IRQ_TXI (1 << 14)
223 #define IRQ_RXI (1 << 13)
224 #define IRQ_RXOI (1 << 11)
225 #define IRQ_TXPSI (1 << 9)
226 #define IRQ_RXPSI (1 << 8)
227 #define IRQ_TXSAI (1 << 6)
228 #define IRQ_RXWFDI (1 << 5)
229 #define IRQ_RXMPDI (1 << 4)
230 #define IRQ_LDI (1 << 3)
231 #define IRQ_EDI (1 << 2)
232 #define IRQ_SPIBEI (1 << 1)
233 #define IRQ_DEDI (1 << 0)
235 #define KS_RXFCTR 0x9C
236 #define RXFCTR_THRESHOLD_MASK 0x00FF
239 #define RXFCTR_RXFC_MASK (0xff << 8)
240 #define RXFCTR_RXFC_SHIFT (8)
241 #define RXFCTR_RXFC_GET(_v) (((_v) >> 8) & 0xff)
242 #define RXFCTR_RXFCT_MASK (0xff << 0)
243 #define RXFCTR_RXFCT_SHIFT (0)
245 #define KS_TXNTFSR 0x9E
247 #define KS_MAHTR0 0xA0
248 #define KS_MAHTR1 0xA2
249 #define KS_MAHTR2 0xA4
250 #define KS_MAHTR3 0xA6
252 #define KS_FCLWR 0xB0
253 #define KS_FCHWR 0xB2
254 #define KS_FCOWR 0xB4
256 #define KS_CIDER 0xC0
257 #define CIDER_ID 0x8870
258 #define CIDER_REV_MASK (0x7 << 1)
259 #define CIDER_REV_SHIFT (1)
260 #define CIDER_REV_GET(_v) (((_v) >> 1) & 0x7)
264 #define IACR_RDEN (1 << 12)
265 #define IACR_TSEL_MASK (0x3 << 10)
266 #define IACR_TSEL_SHIFT (10)
267 #define IACR_TSEL_MIB (0x3 << 10)
268 #define IACR_ADDR_MASK (0x1f << 0)
269 #define IACR_ADDR_SHIFT (0)
271 #define KS_IADLR 0xD0
272 #define KS_IAHDR 0xD2
274 #define KS_PMECR 0xD4
275 #define PMECR_PME_DELAY (1 << 14)
276 #define PMECR_PME_POL (1 << 12)
277 #define PMECR_WOL_WAKEUP (1 << 11)
278 #define PMECR_WOL_MAGICPKT (1 << 10)
279 #define PMECR_WOL_LINKUP (1 << 9)
280 #define PMECR_WOL_ENERGY (1 << 8)
281 #define PMECR_AUTO_WAKE_EN (1 << 7)
282 #define PMECR_WAKEUP_NORMAL (1 << 6)
283 #define PMECR_WKEVT_MASK (0xf << 2)
284 #define PMECR_WKEVT_SHIFT (2)
285 #define PMECR_WKEVT_GET(_v) (((_v) >> 2) & 0xf)
286 #define PMECR_WKEVT_ENERGY (0x1 << 2)
287 #define PMECR_WKEVT_LINK (0x2 << 2)
288 #define PMECR_WKEVT_MAGICPKT (0x4 << 2)
289 #define PMECR_WKEVT_FRAME (0x8 << 2)
290 #define PMECR_PM_MASK (0x3 << 0)
291 #define PMECR_PM_SHIFT (0)
292 #define PMECR_PM_NORMAL (0x0 << 0)
293 #define PMECR_PM_ENERGY (0x1 << 0)
294 #define PMECR_PM_SOFTDOWN (0x2 << 0)
295 #define PMECR_PM_POWERSAVE (0x3 << 0)
297 /* Standard MII PHY data */
298 #define KS_P1MBCR 0xE4
299 #define P1MBCR_FORCE_FDX (1 << 8)
301 #define KS_P1MBSR 0xE6
302 #define P1MBSR_AN_COMPLETE (1 << 5)
303 #define P1MBSR_AN_CAPABLE (1 << 3)
304 #define P1MBSR_LINK_UP (1 << 2)
306 #define KS_PHY1ILR 0xE8
307 #define KS_PHY1IHR 0xEA
308 #define KS_P1ANAR 0xEC
309 #define KS_P1ANLPR 0xEE
311 #define KS_P1SCLMD 0xF4
312 #define P1SCLMD_LEDOFF (1 << 15)
313 #define P1SCLMD_TXIDS (1 << 14)
314 #define P1SCLMD_RESTARTAN (1 << 13)
315 #define P1SCLMD_DISAUTOMDIX (1 << 10)
316 #define P1SCLMD_FORCEMDIX (1 << 9)
317 #define P1SCLMD_AUTONEGEN (1 << 7)
318 #define P1SCLMD_FORCE100 (1 << 6)
319 #define P1SCLMD_FORCEFDX (1 << 5)
320 #define P1SCLMD_ADV_FLOW (1 << 4)
321 #define P1SCLMD_ADV_100BT_FDX (1 << 3)
322 #define P1SCLMD_ADV_100BT_HDX (1 << 2)
323 #define P1SCLMD_ADV_10BT_FDX (1 << 1)
324 #define P1SCLMD_ADV_10BT_HDX (1 << 0)
327 #define P1CR_HP_MDIX (1 << 15)
328 #define P1CR_REV_POL (1 << 13)
329 #define P1CR_OP_100M (1 << 10)
330 #define P1CR_OP_FDX (1 << 9)
331 #define P1CR_OP_MDI (1 << 7)
332 #define P1CR_AN_DONE (1 << 6)
333 #define P1CR_LINK_GOOD (1 << 5)
334 #define P1CR_PNTR_FLOW (1 << 4)
335 #define P1CR_PNTR_100BT_FDX (1 << 3)
336 #define P1CR_PNTR_100BT_HDX (1 << 2)
337 #define P1CR_PNTR_10BT_FDX (1 << 1)
338 #define P1CR_PNTR_10BT_HDX (1 << 0)
340 /* TX Frame control */
342 #define TXFR_TXIC (1 << 15)
343 #define TXFR_TXFID_MASK (0x3f << 0)
344 #define TXFR_TXFID_SHIFT (0)
347 #define P1SR_HP_MDIX (1 << 15)
348 #define P1SR_REV_POL (1 << 13)
349 #define P1SR_OP_100M (1 << 10)
350 #define P1SR_OP_FDX (1 << 9)
351 #define P1SR_OP_MDI (1 << 7)
352 #define P1SR_AN_DONE (1 << 6)
353 #define P1SR_LINK_GOOD (1 << 5)
354 #define P1SR_PNTR_FLOW (1 << 4)
355 #define P1SR_PNTR_100BT_FDX (1 << 3)
356 #define P1SR_PNTR_100BT_HDX (1 << 2)
357 #define P1SR_PNTR_10BT_FDX (1 << 1)
358 #define P1SR_PNTR_10BT_HDX (1 << 0)
360 #define ENUM_BUS_NONE 0
361 #define ENUM_BUS_8BIT 1
362 #define ENUM_BUS_16BIT 2
363 #define ENUM_BUS_32BIT 3
365 #define MAX_MCAST_LST 32
366 #define HW_MCAST_SIZE 8
369 * union ks_tx_hdr - tx header data
370 * @txb: The header as bytes
371 * @txw: The header as 16bit, little-endian words
373 * A dual representation of the tx header data to allow
374 * access to individual bytes, and to allow 16bit accesses
375 * with 16bit alignment.
383 * struct ks_net - KS8851 driver private data
384 * @net_device : The network device we're bound to
385 * @hw_addr : start address of data register.
386 * @hw_addr_cmd : start address of command register.
387 * @txh : temporaly buffer to save status/length.
388 * @lock : Lock to ensure that the device is not accessed when busy.
389 * @pdev : Pointer to platform device.
390 * @mii : The MII state information for the mii calls.
391 * @frame_head_info : frame header information for multi-pkt rx.
392 * @statelock : Lock on this structure for tx list.
393 * @msg_enable : The message flags controlling driver output (see ethtool).
394 * @frame_cnt : number of frames received.
395 * @bus_width : i/o bus width.
396 * @irq : irq number assigned to this device.
397 * @rc_rxqcr : Cached copy of KS_RXQCR.
398 * @rc_txcr : Cached copy of KS_TXCR.
399 * @rc_ier : Cached copy of KS_IER.
400 * @sharedbus : Multipex(addr and data bus) mode indicator.
401 * @cmd_reg_cache : command register cached.
402 * @cmd_reg_cache_int : command register cached. Used in the irq handler.
403 * @promiscuous : promiscuous mode indicator.
404 * @all_mcast : mutlicast indicator.
405 * @mcast_lst_size : size of multicast list.
406 * @mcast_lst : multicast list.
407 * @mcast_bits : multicast enabed.
408 * @mac_addr : MAC address assigned to this device.
410 * @extra_byte : number of extra byte prepended rx pkt.
411 * @enabled : indicator this device works.
413 * The @lock ensures that the chip is protected when certain operations are
414 * in progress. When the read or write packet transfer is in progress, most
415 * of the chip registers are not accessible until the transfer is finished and
416 * the DMA has been de-asserted.
418 * The @statelock is used to protect information in the structure which may
419 * need to be accessed via several sources, such as the network driver layer
420 * or one of the work queues.
424 /* Receive multiplex framer header info */
425 struct type_frame_head
{
426 u16 sts
; /* Frame status */
427 u16 len
; /* Byte count */
431 struct net_device
*netdev
;
432 void __iomem
*hw_addr
;
433 void __iomem
*hw_addr_cmd
;
434 union ks_tx_hdr txh ____cacheline_aligned
;
435 struct mutex lock
; /* spinlock to be interrupt safe */
436 struct platform_device
*pdev
;
437 struct mii_if_info mii
;
438 struct type_frame_head
*frame_head_info
;
439 spinlock_t statelock
;
450 u16 cmd_reg_cache_int
;
454 u8 mcast_lst
[MAX_MCAST_LST
][ETH_ALEN
];
455 u8 mcast_bits
[HW_MCAST_SIZE
];
462 static int msg_enable
;
464 #define BE3 0x8000 /* Byte Enable 3 */
465 #define BE2 0x4000 /* Byte Enable 2 */
466 #define BE1 0x2000 /* Byte Enable 1 */
467 #define BE0 0x1000 /* Byte Enable 0 */
470 * register read/write calls.
472 * All these calls issue transactions to access the chip's registers. They
473 * all require that the necessary lock is held to prevent accesses when the
474 * chip is busy transferring packet data (RX/TX FIFO accesses).
478 * ks_rdreg8 - read 8 bit register from device
479 * @ks : The chip information
480 * @offset: The register address
482 * Read a 8bit register from the chip, returning the result
484 static u8
ks_rdreg8(struct ks_net
*ks
, int offset
)
487 u8 shift_bit
= offset
& 0x03;
488 u8 shift_data
= (offset
& 1) << 3;
489 ks
->cmd_reg_cache
= (u16
) offset
| (u16
)(BE0
<< shift_bit
);
490 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
491 data
= ioread16(ks
->hw_addr
);
492 return (u8
)(data
>> shift_data
);
496 * ks_rdreg16 - read 16 bit register from device
497 * @ks : The chip information
498 * @offset: The register address
500 * Read a 16bit register from the chip, returning the result
503 static u16
ks_rdreg16(struct ks_net
*ks
, int offset
)
505 ks
->cmd_reg_cache
= (u16
)offset
| ((BE1
| BE0
) << (offset
& 0x02));
506 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
507 return ioread16(ks
->hw_addr
);
511 * ks_wrreg8 - write 8bit register value to chip
512 * @ks: The chip information
513 * @offset: The register address
514 * @value: The value to write
517 static void ks_wrreg8(struct ks_net
*ks
, int offset
, u8 value
)
519 u8 shift_bit
= (offset
& 0x03);
520 u16 value_write
= (u16
)(value
<< ((offset
& 1) << 3));
521 ks
->cmd_reg_cache
= (u16
)offset
| (BE0
<< shift_bit
);
522 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
523 iowrite16(value_write
, ks
->hw_addr
);
527 * ks_wrreg16 - write 16bit register value to chip
528 * @ks: The chip information
529 * @offset: The register address
530 * @value: The value to write
534 static void ks_wrreg16(struct ks_net
*ks
, int offset
, u16 value
)
536 ks
->cmd_reg_cache
= (u16
)offset
| ((BE1
| BE0
) << (offset
& 0x02));
537 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
538 iowrite16(value
, ks
->hw_addr
);
542 * ks_inblk - read a block of data from QMU. This is called after sudo DMA mode enabled.
543 * @ks: The chip state
544 * @wptr: buffer address to save data
545 * @len: length in byte to read
548 static inline void ks_inblk(struct ks_net
*ks
, u16
*wptr
, u32 len
)
552 *wptr
++ = (u16
)ioread16(ks
->hw_addr
);
556 * ks_outblk - write data to QMU. This is called after sudo DMA mode enabled.
557 * @ks: The chip information
558 * @wptr: buffer address
559 * @len: length in byte to write
562 static inline void ks_outblk(struct ks_net
*ks
, u16
*wptr
, u32 len
)
566 iowrite16(*wptr
++, ks
->hw_addr
);
569 static void ks_disable_int(struct ks_net
*ks
)
571 ks_wrreg16(ks
, KS_IER
, 0x0000);
572 } /* ks_disable_int */
574 static void ks_enable_int(struct ks_net
*ks
)
576 ks_wrreg16(ks
, KS_IER
, ks
->rc_ier
);
577 } /* ks_enable_int */
580 * ks_tx_fifo_space - return the available hardware buffer size.
581 * @ks: The chip information
584 static inline u16
ks_tx_fifo_space(struct ks_net
*ks
)
586 return ks_rdreg16(ks
, KS_TXMIR
) & 0x1fff;
590 * ks_save_cmd_reg - save the command register from the cache.
591 * @ks: The chip information
594 static inline void ks_save_cmd_reg(struct ks_net
*ks
)
596 /*ks8851 MLL has a bug to read back the command register.
597 * So rely on software to save the content of command register.
599 ks
->cmd_reg_cache_int
= ks
->cmd_reg_cache
;
603 * ks_restore_cmd_reg - restore the command register from the cache and
604 * write to hardware register.
605 * @ks: The chip information
608 static inline void ks_restore_cmd_reg(struct ks_net
*ks
)
610 ks
->cmd_reg_cache
= ks
->cmd_reg_cache_int
;
611 iowrite16(ks
->cmd_reg_cache
, ks
->hw_addr_cmd
);
615 * ks_set_powermode - set power mode of the device
616 * @ks: The chip information
617 * @pwrmode: The power mode value to write to KS_PMECR.
619 * Change the power mode of the chip.
621 static void ks_set_powermode(struct ks_net
*ks
, unsigned pwrmode
)
625 netif_dbg(ks
, hw
, ks
->netdev
, "setting power mode %d\n", pwrmode
);
627 ks_rdreg16(ks
, KS_GRR
);
628 pmecr
= ks_rdreg16(ks
, KS_PMECR
);
629 pmecr
&= ~PMECR_PM_MASK
;
632 ks_wrreg16(ks
, KS_PMECR
, pmecr
);
636 * ks_read_config - read chip configuration of bus width.
637 * @ks: The chip information
640 static void ks_read_config(struct ks_net
*ks
)
644 /* Regardless of bus width, 8 bit read should always work.*/
645 reg_data
= ks_rdreg8(ks
, KS_CCR
) & 0x00FF;
646 reg_data
|= ks_rdreg8(ks
, KS_CCR
+1) << 8;
648 /* addr/data bus are multiplexed */
649 ks
->sharedbus
= (reg_data
& CCR_SHARED
) == CCR_SHARED
;
651 /* There are garbage data when reading data from QMU,
652 depending on bus-width.
655 if (reg_data
& CCR_8BIT
) {
656 ks
->bus_width
= ENUM_BUS_8BIT
;
658 } else if (reg_data
& CCR_16BIT
) {
659 ks
->bus_width
= ENUM_BUS_16BIT
;
662 ks
->bus_width
= ENUM_BUS_32BIT
;
668 * ks_soft_reset - issue one of the soft reset to the device
669 * @ks: The device state.
670 * @op: The bit(s) to set in the GRR
672 * Issue the relevant soft-reset command to the device's GRR register
675 * Note, the delays are in there as a caution to ensure that the reset
676 * has time to take effect and then complete. Since the datasheet does
677 * not currently specify the exact sequence, we have chosen something
678 * that seems to work with our device.
680 static void ks_soft_reset(struct ks_net
*ks
, unsigned op
)
682 /* Disable interrupt first */
683 ks_wrreg16(ks
, KS_IER
, 0x0000);
684 ks_wrreg16(ks
, KS_GRR
, op
);
685 mdelay(10); /* wait a short time to effect reset */
686 ks_wrreg16(ks
, KS_GRR
, 0);
687 mdelay(1); /* wait for condition to clear */
691 void ks_enable_qmu(struct ks_net
*ks
)
695 w
= ks_rdreg16(ks
, KS_TXCR
);
696 /* Enables QMU Transmit (TXCR). */
697 ks_wrreg16(ks
, KS_TXCR
, w
| TXCR_TXE
);
700 * RX Frame Count Threshold Enable and Auto-Dequeue RXQ Frame
704 w
= ks_rdreg16(ks
, KS_RXQCR
);
705 ks_wrreg16(ks
, KS_RXQCR
, w
| RXQCR_RXFCTE
);
707 /* Enables QMU Receive (RXCR1). */
708 w
= ks_rdreg16(ks
, KS_RXCR1
);
709 ks_wrreg16(ks
, KS_RXCR1
, w
| RXCR1_RXE
);
711 } /* ks_enable_qmu */
713 static void ks_disable_qmu(struct ks_net
*ks
)
717 w
= ks_rdreg16(ks
, KS_TXCR
);
719 /* Disables QMU Transmit (TXCR). */
721 ks_wrreg16(ks
, KS_TXCR
, w
);
723 /* Disables QMU Receive (RXCR1). */
724 w
= ks_rdreg16(ks
, KS_RXCR1
);
726 ks_wrreg16(ks
, KS_RXCR1
, w
);
730 } /* ks_disable_qmu */
733 * ks_read_qmu - read 1 pkt data from the QMU.
734 * @ks: The chip information
735 * @buf: buffer address to save 1 pkt
737 * Here is the sequence to read 1 pkt:
738 * 1. set sudo DMA mode
739 * 2. read prepend data
741 * 4. reset sudo DMA Mode
743 static inline void ks_read_qmu(struct ks_net
*ks
, u16
*buf
, u32 len
)
745 u32 r
= ks
->extra_byte
& 0x1 ;
746 u32 w
= ks
->extra_byte
- r
;
748 /* 1. set sudo DMA mode */
749 ks_wrreg16(ks
, KS_RXFDPR
, RXFDPR_RXFPAI
);
750 ks_wrreg8(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_SDA
) & 0xff);
752 /* 2. read prepend data */
754 * read 4 + extra bytes and discard them.
755 * extra bytes for dummy, 2 for status, 2 for len
758 /* use likely(r) for 8 bit access for performance */
760 ioread8(ks
->hw_addr
);
761 ks_inblk(ks
, buf
, w
+ 2 + 2);
763 /* 3. read pkt data */
764 ks_inblk(ks
, buf
, ALIGN(len
, 4));
766 /* 4. reset sudo DMA Mode */
767 ks_wrreg8(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
771 * ks_rcv - read multiple pkts data from the QMU.
772 * @ks: The chip information
773 * @netdev: The network device being opened.
775 * Read all of header information before reading pkt content.
776 * It is not allowed only port of pkts in QMU after issuing
779 static void ks_rcv(struct ks_net
*ks
, struct net_device
*netdev
)
782 struct type_frame_head
*frame_hdr
= ks
->frame_head_info
;
785 ks
->frame_cnt
= ks_rdreg16(ks
, KS_RXFCTR
) >> 8;
787 /* read all header information */
788 for (i
= 0; i
< ks
->frame_cnt
; i
++) {
789 /* Checking Received packet status */
790 frame_hdr
->sts
= ks_rdreg16(ks
, KS_RXFHSR
);
791 /* Get packet len from hardware */
792 frame_hdr
->len
= ks_rdreg16(ks
, KS_RXFHBCR
);
796 frame_hdr
= ks
->frame_head_info
;
797 while (ks
->frame_cnt
--) {
798 skb
= dev_alloc_skb(frame_hdr
->len
+ 16);
799 if (likely(skb
&& (frame_hdr
->sts
& RXFSHR_RXFV
) &&
800 (frame_hdr
->len
< RX_BUF_SIZE
) && frame_hdr
->len
)) {
802 /* read data block including CRC 4 bytes */
803 ks_read_qmu(ks
, (u16
*)skb
->data
, frame_hdr
->len
);
804 skb_put(skb
, frame_hdr
->len
);
805 skb
->protocol
= eth_type_trans(skb
, netdev
);
808 pr_err("%s: err:skb alloc\n", __func__
);
809 ks_wrreg16(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_RRXEF
));
811 dev_kfree_skb_irq(skb
);
818 * ks_update_link_status - link status update.
819 * @netdev: The network device being opened.
820 * @ks: The chip information
824 static void ks_update_link_status(struct net_device
*netdev
, struct ks_net
*ks
)
826 /* check the status of the link */
828 if (ks_rdreg16(ks
, KS_P1SR
) & P1SR_LINK_GOOD
) {
829 netif_carrier_on(netdev
);
830 link_up_status
= true;
832 netif_carrier_off(netdev
);
833 link_up_status
= false;
835 netif_dbg(ks
, link
, ks
->netdev
,
836 "%s: %s\n", __func__
, link_up_status
? "UP" : "DOWN");
840 * ks_irq - device interrupt handler
841 * @irq: Interrupt number passed from the IRQ hnalder.
842 * @pw: The private word passed to register_irq(), our struct ks_net.
844 * This is the handler invoked to find out what happened
846 * Read the interrupt status, work out what needs to be done and then clear
847 * any of the interrupts that are not needed.
850 static irqreturn_t
ks_irq(int irq
, void *pw
)
852 struct net_device
*netdev
= pw
;
853 struct ks_net
*ks
= netdev_priv(netdev
);
856 /*this should be the first in IRQ handler */
859 status
= ks_rdreg16(ks
, KS_ISR
);
860 if (unlikely(!status
)) {
861 ks_restore_cmd_reg(ks
);
865 ks_wrreg16(ks
, KS_ISR
, status
);
867 if (likely(status
& IRQ_RXI
))
870 if (unlikely(status
& IRQ_LCI
))
871 ks_update_link_status(netdev
, ks
);
873 if (unlikely(status
& IRQ_TXI
))
874 netif_wake_queue(netdev
);
876 if (unlikely(status
& IRQ_LDI
)) {
878 u16 pmecr
= ks_rdreg16(ks
, KS_PMECR
);
879 pmecr
&= ~PMECR_WKEVT_MASK
;
880 ks_wrreg16(ks
, KS_PMECR
, pmecr
| PMECR_WKEVT_LINK
);
883 /* this should be the last in IRQ handler*/
884 ks_restore_cmd_reg(ks
);
890 * ks_net_open - open network device
891 * @netdev: The network device being opened.
893 * Called when the network device is marked active, such as a user executing
894 * 'ifconfig up' on the device.
896 static int ks_net_open(struct net_device
*netdev
)
898 struct ks_net
*ks
= netdev_priv(netdev
);
901 #define KS_INT_FLAGS (IRQF_DISABLED|IRQF_TRIGGER_LOW)
902 /* lock the card, even if we may not actually do anything
903 * else at the moment.
906 netif_dbg(ks
, ifup
, ks
->netdev
, "%s - entry\n", __func__
);
909 err
= request_irq(ks
->irq
, ks_irq
, KS_INT_FLAGS
, DRV_NAME
, netdev
);
912 pr_err("Failed to request IRQ: %d: %d\n", ks
->irq
, err
);
916 /* wake up powermode to normal mode */
917 ks_set_powermode(ks
, PMECR_PM_NORMAL
);
918 mdelay(1); /* wait for normal mode to take effect */
920 ks_wrreg16(ks
, KS_ISR
, 0xffff);
923 netif_start_queue(ks
->netdev
);
925 netif_dbg(ks
, ifup
, ks
->netdev
, "network device up\n");
931 * ks_net_stop - close network device
932 * @netdev: The device being closed.
934 * Called to close down a network device which has been active. Cancell any
935 * work, shutdown the RX and TX process and then place the chip into a low
936 * power state whilst it is not being used.
938 static int ks_net_stop(struct net_device
*netdev
)
940 struct ks_net
*ks
= netdev_priv(netdev
);
942 netif_info(ks
, ifdown
, netdev
, "shutting down\n");
944 netif_stop_queue(netdev
);
946 mutex_lock(&ks
->lock
);
948 /* turn off the IRQs and ack any outstanding */
949 ks_wrreg16(ks
, KS_IER
, 0x0000);
950 ks_wrreg16(ks
, KS_ISR
, 0xffff);
952 /* shutdown RX/TX QMU */
955 /* set powermode to soft power down to save power */
956 ks_set_powermode(ks
, PMECR_PM_SOFTDOWN
);
957 free_irq(ks
->irq
, netdev
);
958 mutex_unlock(&ks
->lock
);
964 * ks_write_qmu - write 1 pkt data to the QMU.
965 * @ks: The chip information
966 * @pdata: buffer address to save 1 pkt
967 * @len: Pkt length in byte
968 * Here is the sequence to write 1 pkt:
969 * 1. set sudo DMA mode
970 * 2. write status/length
972 * 4. reset sudo DMA Mode
973 * 5. reset sudo DMA mode
974 * 6. Wait until pkt is out
976 static void ks_write_qmu(struct ks_net
*ks
, u8
*pdata
, u16 len
)
978 /* start header at txb[0] to align txw entries */
980 ks
->txh
.txw
[1] = cpu_to_le16(len
);
982 /* 1. set sudo-DMA mode */
983 ks_wrreg8(ks
, KS_RXQCR
, (ks
->rc_rxqcr
| RXQCR_SDA
) & 0xff);
984 /* 2. write status/lenth info */
985 ks_outblk(ks
, ks
->txh
.txw
, 4);
986 /* 3. write pkt data */
987 ks_outblk(ks
, (u16
*)pdata
, ALIGN(len
, 4));
988 /* 4. reset sudo-DMA mode */
989 ks_wrreg8(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
990 /* 5. Enqueue Tx(move the pkt from TX buffer into TXQ) */
991 ks_wrreg16(ks
, KS_TXQCR
, TXQCR_METFE
);
992 /* 6. wait until TXQCR_METFE is auto-cleared */
993 while (ks_rdreg16(ks
, KS_TXQCR
) & TXQCR_METFE
)
998 * ks_start_xmit - transmit packet
999 * @skb : The buffer to transmit
1000 * @netdev : The device used to transmit the packet.
1002 * Called by the network layer to transmit the @skb.
1003 * spin_lock_irqsave is required because tx and rx should be mutual exclusive.
1004 * So while tx is in-progress, prevent IRQ interrupt from happenning.
1006 static int ks_start_xmit(struct sk_buff
*skb
, struct net_device
*netdev
)
1008 int retv
= NETDEV_TX_OK
;
1009 struct ks_net
*ks
= netdev_priv(netdev
);
1011 disable_irq(netdev
->irq
);
1013 spin_lock(&ks
->statelock
);
1015 /* Extra space are required:
1016 * 4 byte for alignment, 4 for status/length, 4 for CRC
1019 if (likely(ks_tx_fifo_space(ks
) >= skb
->len
+ 12)) {
1020 ks_write_qmu(ks
, skb
->data
, skb
->len
);
1023 retv
= NETDEV_TX_BUSY
;
1024 spin_unlock(&ks
->statelock
);
1026 enable_irq(netdev
->irq
);
1031 * ks_start_rx - ready to serve pkts
1032 * @ks : The chip information
1035 static void ks_start_rx(struct ks_net
*ks
)
1039 /* Enables QMU Receive (RXCR1). */
1040 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1042 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1046 * ks_stop_rx - stop to serve pkts
1047 * @ks : The chip information
1050 static void ks_stop_rx(struct ks_net
*ks
)
1054 /* Disables QMU Receive (RXCR1). */
1055 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1056 cntl
&= ~RXCR1_RXE
;
1057 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1061 static unsigned long const ethernet_polynomial
= 0x04c11db7U
;
1063 static unsigned long ether_gen_crc(int length
, u8
*data
)
1066 while (--length
>= 0) {
1067 u8 current_octet
= *data
++;
1070 for (bit
= 0; bit
< 8; bit
++, current_octet
>>= 1) {
1072 ((crc
< 0) ^ (current_octet
& 1) ?
1073 ethernet_polynomial
: 0);
1076 return (unsigned long)crc
;
1077 } /* ether_gen_crc */
1080 * ks_set_grpaddr - set multicast information
1081 * @ks : The chip information
1084 static void ks_set_grpaddr(struct ks_net
*ks
)
1087 u32 index
, position
, value
;
1089 memset(ks
->mcast_bits
, 0, sizeof(u8
) * HW_MCAST_SIZE
);
1091 for (i
= 0; i
< ks
->mcast_lst_size
; i
++) {
1092 position
= (ether_gen_crc(6, ks
->mcast_lst
[i
]) >> 26) & 0x3f;
1093 index
= position
>> 3;
1094 value
= 1 << (position
& 7);
1095 ks
->mcast_bits
[index
] |= (u8
)value
;
1098 for (i
= 0; i
< HW_MCAST_SIZE
; i
++) {
1100 ks_wrreg16(ks
, (u16
)((KS_MAHTR0
+ i
) & ~1),
1101 (ks
->mcast_bits
[i
] << 8) |
1102 ks
->mcast_bits
[i
- 1]);
1105 } /* ks_set_grpaddr */
1108 * ks_clear_mcast - clear multicast information
1110 * @ks : The chip information
1111 * This routine removes all mcast addresses set in the hardware.
1114 static void ks_clear_mcast(struct ks_net
*ks
)
1117 for (i
= 0; i
< HW_MCAST_SIZE
; i
++)
1118 ks
->mcast_bits
[i
] = 0;
1120 mcast_size
= HW_MCAST_SIZE
>> 2;
1121 for (i
= 0; i
< mcast_size
; i
++)
1122 ks_wrreg16(ks
, KS_MAHTR0
+ (2*i
), 0);
1125 static void ks_set_promis(struct ks_net
*ks
, u16 promiscuous_mode
)
1128 ks
->promiscuous
= promiscuous_mode
;
1129 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1130 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1132 cntl
&= ~RXCR1_FILTER_MASK
;
1133 if (promiscuous_mode
)
1134 /* Enable Promiscuous mode */
1135 cntl
|= RXCR1_RXAE
| RXCR1_RXINVF
;
1137 /* Disable Promiscuous mode (default normal mode) */
1138 cntl
|= RXCR1_RXPAFMA
;
1140 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1145 } /* ks_set_promis */
1147 static void ks_set_mcast(struct ks_net
*ks
, u16 mcast
)
1151 ks
->all_mcast
= mcast
;
1152 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1153 cntl
= ks_rdreg16(ks
, KS_RXCR1
);
1154 cntl
&= ~RXCR1_FILTER_MASK
;
1156 /* Enable "Perfect with Multicast address passed mode" */
1157 cntl
|= (RXCR1_RXAE
| RXCR1_RXMAFMA
| RXCR1_RXPAFMA
);
1160 * Disable "Perfect with Multicast address passed
1161 * mode" (normal mode).
1163 cntl
|= RXCR1_RXPAFMA
;
1165 ks_wrreg16(ks
, KS_RXCR1
, cntl
);
1169 } /* ks_set_mcast */
1171 static void ks_set_rx_mode(struct net_device
*netdev
)
1173 struct ks_net
*ks
= netdev_priv(netdev
);
1174 struct netdev_hw_addr
*ha
;
1176 /* Turn on/off promiscuous mode. */
1177 if ((netdev
->flags
& IFF_PROMISC
) == IFF_PROMISC
)
1179 (u16
)((netdev
->flags
& IFF_PROMISC
) == IFF_PROMISC
));
1180 /* Turn on/off all mcast mode. */
1181 else if ((netdev
->flags
& IFF_ALLMULTI
) == IFF_ALLMULTI
)
1183 (u16
)((netdev
->flags
& IFF_ALLMULTI
) == IFF_ALLMULTI
));
1185 ks_set_promis(ks
, false);
1187 if ((netdev
->flags
& IFF_MULTICAST
) && netdev_mc_count(netdev
)) {
1188 if (netdev_mc_count(netdev
) <= MAX_MCAST_LST
) {
1191 netdev_for_each_mc_addr(ha
, netdev
) {
1192 if (!(*ha
->addr
& 1))
1194 if (i
>= MAX_MCAST_LST
)
1196 memcpy(ks
->mcast_lst
[i
++], ha
->addr
, ETH_ALEN
);
1198 ks
->mcast_lst_size
= (u8
)i
;
1202 * List too big to support so
1203 * turn on all mcast mode.
1205 ks
->mcast_lst_size
= MAX_MCAST_LST
;
1206 ks_set_mcast(ks
, true);
1209 ks
->mcast_lst_size
= 0;
1212 } /* ks_set_rx_mode */
1214 static void ks_set_mac(struct ks_net
*ks
, u8
*data
)
1216 u16
*pw
= (u16
*)data
;
1219 ks_stop_rx(ks
); /* Stop receiving for reconfiguration */
1222 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1223 ks_wrreg16(ks
, KS_MARH
, w
);
1226 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1227 ks_wrreg16(ks
, KS_MARM
, w
);
1230 w
= ((u
& 0xFF) << 8) | ((u
>> 8) & 0xFF);
1231 ks_wrreg16(ks
, KS_MARL
, w
);
1233 memcpy(ks
->mac_addr
, data
, 6);
1239 static int ks_set_mac_address(struct net_device
*netdev
, void *paddr
)
1241 struct ks_net
*ks
= netdev_priv(netdev
);
1242 struct sockaddr
*addr
= paddr
;
1245 memcpy(netdev
->dev_addr
, addr
->sa_data
, netdev
->addr_len
);
1247 da
= (u8
*)netdev
->dev_addr
;
1253 static int ks_net_ioctl(struct net_device
*netdev
, struct ifreq
*req
, int cmd
)
1255 struct ks_net
*ks
= netdev_priv(netdev
);
1257 if (!netif_running(netdev
))
1260 return generic_mii_ioctl(&ks
->mii
, if_mii(req
), cmd
, NULL
);
1263 static const struct net_device_ops ks_netdev_ops
= {
1264 .ndo_open
= ks_net_open
,
1265 .ndo_stop
= ks_net_stop
,
1266 .ndo_do_ioctl
= ks_net_ioctl
,
1267 .ndo_start_xmit
= ks_start_xmit
,
1268 .ndo_set_mac_address
= ks_set_mac_address
,
1269 .ndo_set_rx_mode
= ks_set_rx_mode
,
1270 .ndo_change_mtu
= eth_change_mtu
,
1271 .ndo_validate_addr
= eth_validate_addr
,
1274 /* ethtool support */
1276 static void ks_get_drvinfo(struct net_device
*netdev
,
1277 struct ethtool_drvinfo
*di
)
1279 strlcpy(di
->driver
, DRV_NAME
, sizeof(di
->driver
));
1280 strlcpy(di
->version
, "1.00", sizeof(di
->version
));
1281 strlcpy(di
->bus_info
, dev_name(netdev
->dev
.parent
),
1282 sizeof(di
->bus_info
));
1285 static u32
ks_get_msglevel(struct net_device
*netdev
)
1287 struct ks_net
*ks
= netdev_priv(netdev
);
1288 return ks
->msg_enable
;
1291 static void ks_set_msglevel(struct net_device
*netdev
, u32 to
)
1293 struct ks_net
*ks
= netdev_priv(netdev
);
1294 ks
->msg_enable
= to
;
1297 static int ks_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*cmd
)
1299 struct ks_net
*ks
= netdev_priv(netdev
);
1300 return mii_ethtool_gset(&ks
->mii
, cmd
);
1303 static int ks_set_settings(struct net_device
*netdev
, struct ethtool_cmd
*cmd
)
1305 struct ks_net
*ks
= netdev_priv(netdev
);
1306 return mii_ethtool_sset(&ks
->mii
, cmd
);
1309 static u32
ks_get_link(struct net_device
*netdev
)
1311 struct ks_net
*ks
= netdev_priv(netdev
);
1312 return mii_link_ok(&ks
->mii
);
1315 static int ks_nway_reset(struct net_device
*netdev
)
1317 struct ks_net
*ks
= netdev_priv(netdev
);
1318 return mii_nway_restart(&ks
->mii
);
1321 static const struct ethtool_ops ks_ethtool_ops
= {
1322 .get_drvinfo
= ks_get_drvinfo
,
1323 .get_msglevel
= ks_get_msglevel
,
1324 .set_msglevel
= ks_set_msglevel
,
1325 .get_settings
= ks_get_settings
,
1326 .set_settings
= ks_set_settings
,
1327 .get_link
= ks_get_link
,
1328 .nway_reset
= ks_nway_reset
,
1331 /* MII interface controls */
1334 * ks_phy_reg - convert MII register into a KS8851 register
1335 * @reg: MII register number.
1337 * Return the KS8851 register number for the corresponding MII PHY register
1338 * if possible. Return zero if the MII register has no direct mapping to the
1339 * KS8851 register set.
1341 static int ks_phy_reg(int reg
)
1362 * ks_phy_read - MII interface PHY register read.
1363 * @netdev: The network device the PHY is on.
1364 * @phy_addr: Address of PHY (ignored as we only have one)
1365 * @reg: The register to read.
1367 * This call reads data from the PHY register specified in @reg. Since the
1368 * device does not support all the MII registers, the non-existent values
1369 * are always returned as zero.
1371 * We return zero for unsupported registers as the MII code does not check
1372 * the value returned for any error status, and simply returns it to the
1373 * caller. The mii-tool that the driver was tested with takes any -ve error
1374 * as real PHY capabilities, thus displaying incorrect data to the user.
1376 static int ks_phy_read(struct net_device
*netdev
, int phy_addr
, int reg
)
1378 struct ks_net
*ks
= netdev_priv(netdev
);
1382 ksreg
= ks_phy_reg(reg
);
1384 return 0x0; /* no error return allowed, so use zero */
1386 mutex_lock(&ks
->lock
);
1387 result
= ks_rdreg16(ks
, ksreg
);
1388 mutex_unlock(&ks
->lock
);
1393 static void ks_phy_write(struct net_device
*netdev
,
1394 int phy
, int reg
, int value
)
1396 struct ks_net
*ks
= netdev_priv(netdev
);
1399 ksreg
= ks_phy_reg(reg
);
1401 mutex_lock(&ks
->lock
);
1402 ks_wrreg16(ks
, ksreg
, value
);
1403 mutex_unlock(&ks
->lock
);
1408 * ks_read_selftest - read the selftest memory info.
1409 * @ks: The device state
1411 * Read and check the TX/RX memory selftest information.
1413 static int ks_read_selftest(struct ks_net
*ks
)
1415 unsigned both_done
= MBIR_TXMBF
| MBIR_RXMBF
;
1419 rd
= ks_rdreg16(ks
, KS_MBIR
);
1421 if ((rd
& both_done
) != both_done
) {
1422 netdev_warn(ks
->netdev
, "Memory selftest not finished\n");
1426 if (rd
& MBIR_TXMBFA
) {
1427 netdev_err(ks
->netdev
, "TX memory selftest fails\n");
1431 if (rd
& MBIR_RXMBFA
) {
1432 netdev_err(ks
->netdev
, "RX memory selftest fails\n");
1436 netdev_info(ks
->netdev
, "the selftest passes\n");
1440 static void ks_setup(struct ks_net
*ks
)
1445 * Configure QMU Transmit
1448 /* Setup Transmit Frame Data Pointer Auto-Increment (TXFDPR) */
1449 ks_wrreg16(ks
, KS_TXFDPR
, TXFDPR_TXFPAI
);
1451 /* Setup Receive Frame Data Pointer Auto-Increment */
1452 ks_wrreg16(ks
, KS_RXFDPR
, RXFDPR_RXFPAI
);
1454 /* Setup Receive Frame Threshold - 1 frame (RXFCTFC) */
1455 ks_wrreg16(ks
, KS_RXFCTR
, 1 & RXFCTR_THRESHOLD_MASK
);
1457 /* Setup RxQ Command Control (RXQCR) */
1458 ks
->rc_rxqcr
= RXQCR_CMD_CNTL
;
1459 ks_wrreg16(ks
, KS_RXQCR
, ks
->rc_rxqcr
);
1462 * set the force mode to half duplex, default is full duplex
1463 * because if the auto-negotiation fails, most switch uses
1467 w
= ks_rdreg16(ks
, KS_P1MBCR
);
1468 w
&= ~P1MBCR_FORCE_FDX
;
1469 ks_wrreg16(ks
, KS_P1MBCR
, w
);
1471 w
= TXCR_TXFCE
| TXCR_TXPE
| TXCR_TXCRC
| TXCR_TCGIP
;
1472 ks_wrreg16(ks
, KS_TXCR
, w
);
1474 w
= RXCR1_RXFCE
| RXCR1_RXBE
| RXCR1_RXUE
| RXCR1_RXME
| RXCR1_RXIPFCC
;
1476 if (ks
->promiscuous
) /* bPromiscuous */
1477 w
|= (RXCR1_RXAE
| RXCR1_RXINVF
);
1478 else if (ks
->all_mcast
) /* Multicast address passed mode */
1479 w
|= (RXCR1_RXAE
| RXCR1_RXMAFMA
| RXCR1_RXPAFMA
);
1480 else /* Normal mode */
1483 ks_wrreg16(ks
, KS_RXCR1
, w
);
1487 static void ks_setup_int(struct ks_net
*ks
)
1490 /* Clear the interrupts status of the hardware. */
1491 ks_wrreg16(ks
, KS_ISR
, 0xffff);
1493 /* Enables the interrupts of the hardware. */
1494 ks
->rc_ier
= (IRQ_LCI
| IRQ_TXI
| IRQ_RXI
);
1495 } /* ks_setup_int */
1497 static int ks_hw_init(struct ks_net
*ks
)
1499 #define MHEADER_SIZE (sizeof(struct type_frame_head) * MAX_RECV_FRAMES)
1500 ks
->promiscuous
= 0;
1502 ks
->mcast_lst_size
= 0;
1504 ks
->frame_head_info
= (struct type_frame_head
*) \
1505 kmalloc(MHEADER_SIZE
, GFP_KERNEL
);
1506 if (!ks
->frame_head_info
) {
1507 pr_err("Error: Fail to allocate frame memory\n");
1511 ks_set_mac(ks
, KS_DEFAULT_MAC_ADDRESS
);
1516 static int __devinit
ks8851_probe(struct platform_device
*pdev
)
1519 struct resource
*io_d
, *io_c
;
1520 struct net_device
*netdev
;
1524 io_d
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1525 io_c
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
1527 if (!request_mem_region(io_d
->start
, resource_size(io_d
), DRV_NAME
))
1528 goto err_mem_region
;
1530 if (!request_mem_region(io_c
->start
, resource_size(io_c
), DRV_NAME
))
1531 goto err_mem_region1
;
1533 netdev
= alloc_etherdev(sizeof(struct ks_net
));
1535 goto err_alloc_etherdev
;
1537 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1539 ks
= netdev_priv(netdev
);
1540 ks
->netdev
= netdev
;
1541 ks
->hw_addr
= ioremap(io_d
->start
, resource_size(io_d
));
1546 ks
->hw_addr_cmd
= ioremap(io_c
->start
, resource_size(io_c
));
1547 if (!ks
->hw_addr_cmd
)
1550 ks
->irq
= platform_get_irq(pdev
, 0);
1559 mutex_init(&ks
->lock
);
1560 spin_lock_init(&ks
->statelock
);
1562 netdev
->netdev_ops
= &ks_netdev_ops
;
1563 netdev
->ethtool_ops
= &ks_ethtool_ops
;
1565 /* setup mii state */
1566 ks
->mii
.dev
= netdev
;
1568 ks
->mii
.phy_id_mask
= 1;
1569 ks
->mii
.reg_num_mask
= 0xf;
1570 ks
->mii
.mdio_read
= ks_phy_read
;
1571 ks
->mii
.mdio_write
= ks_phy_write
;
1573 netdev_info(netdev
, "message enable is %d\n", msg_enable
);
1574 /* set the default message enable */
1575 ks
->msg_enable
= netif_msg_init(msg_enable
, (NETIF_MSG_DRV
|
1580 /* simple check for a valid chip being connected to the bus */
1581 if ((ks_rdreg16(ks
, KS_CIDER
) & ~CIDER_REV_MASK
) != CIDER_ID
) {
1582 netdev_err(netdev
, "failed to read device ID\n");
1587 if (ks_read_selftest(ks
)) {
1588 netdev_err(netdev
, "failed to read device ID\n");
1593 err
= register_netdev(netdev
);
1597 platform_set_drvdata(pdev
, netdev
);
1599 ks_soft_reset(ks
, GRR_GSR
);
1604 memcpy(netdev
->dev_addr
, ks
->mac_addr
, 6);
1606 data
= ks_rdreg16(ks
, KS_OBCR
);
1607 ks_wrreg16(ks
, KS_OBCR
, data
| OBCR_ODS_16MA
);
1610 * If you want to use the default MAC addr,
1611 * comment out the 2 functions below.
1614 random_ether_addr(netdev
->dev_addr
);
1615 ks_set_mac(ks
, netdev
->dev_addr
);
1617 id
= ks_rdreg16(ks
, KS_CIDER
);
1619 netdev_info(netdev
, "Found chip, family: 0x%x, id: 0x%x, rev: 0x%x\n",
1620 (id
>> 8) & 0xff, (id
>> 4) & 0xf, (id
>> 1) & 0x7);
1625 iounmap(ks
->hw_addr_cmd
);
1627 iounmap(ks
->hw_addr
);
1629 free_netdev(netdev
);
1631 release_mem_region(io_c
->start
, resource_size(io_c
));
1633 release_mem_region(io_d
->start
, resource_size(io_d
));
1638 static int __devexit
ks8851_remove(struct platform_device
*pdev
)
1640 struct net_device
*netdev
= platform_get_drvdata(pdev
);
1641 struct ks_net
*ks
= netdev_priv(netdev
);
1642 struct resource
*iomem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1644 kfree(ks
->frame_head_info
);
1645 unregister_netdev(netdev
);
1646 iounmap(ks
->hw_addr
);
1647 free_netdev(netdev
);
1648 release_mem_region(iomem
->start
, resource_size(iomem
));
1649 platform_set_drvdata(pdev
, NULL
);
1654 static struct platform_driver ks8851_platform_driver
= {
1657 .owner
= THIS_MODULE
,
1659 .probe
= ks8851_probe
,
1660 .remove
= __devexit_p(ks8851_remove
),
1663 static int __init
ks8851_init(void)
1665 return platform_driver_register(&ks8851_platform_driver
);
1668 static void __exit
ks8851_exit(void)
1670 platform_driver_unregister(&ks8851_platform_driver
);
1673 module_init(ks8851_init
);
1674 module_exit(ks8851_exit
);
1676 MODULE_DESCRIPTION("KS8851 MLL Network driver");
1677 MODULE_AUTHOR("David Choi <david.choi@micrel.com>");
1678 MODULE_LICENSE("GPL");
1679 module_param_named(message
, msg_enable
, int, 0);
1680 MODULE_PARM_DESC(message
, "Message verbosity level (0=none, 31=all)");