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ll_temac: add error checking to DMA init path
[deliverable/linux.git] / drivers / net / ll_temac_main.c
1 /*
2 * Driver for Xilinx TEMAC Ethernet device
3 *
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
7 *
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
10 *
11 * Notes:
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
21 *
22 * TODO:
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
27 *
28 */
29
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/skbuff.h>
42 #include <linux/spinlock.h>
43 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
44 #include <linux/udp.h> /* needed for sizeof(udphdr) */
45 #include <linux/phy.h>
46 #include <linux/in.h>
47 #include <linux/io.h>
48 #include <linux/ip.h>
49 #include <linux/slab.h>
50
51 #include "ll_temac.h"
52
53 #define TX_BD_NUM 64
54 #define RX_BD_NUM 128
55
56 /* ---------------------------------------------------------------------
57 * Low level register access functions
58 */
59
60 u32 temac_ior(struct temac_local *lp, int offset)
61 {
62 return in_be32((u32 *)(lp->regs + offset));
63 }
64
65 void temac_iow(struct temac_local *lp, int offset, u32 value)
66 {
67 out_be32((u32 *) (lp->regs + offset), value);
68 }
69
70 int temac_indirect_busywait(struct temac_local *lp)
71 {
72 long end = jiffies + 2;
73
74 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
75 if (end - jiffies <= 0) {
76 WARN_ON(1);
77 return -ETIMEDOUT;
78 }
79 msleep(1);
80 }
81 return 0;
82 }
83
84 /**
85 * temac_indirect_in32
86 *
87 * lp->indirect_mutex must be held when calling this function
88 */
89 u32 temac_indirect_in32(struct temac_local *lp, int reg)
90 {
91 u32 val;
92
93 if (temac_indirect_busywait(lp))
94 return -ETIMEDOUT;
95 temac_iow(lp, XTE_CTL0_OFFSET, reg);
96 if (temac_indirect_busywait(lp))
97 return -ETIMEDOUT;
98 val = temac_ior(lp, XTE_LSW0_OFFSET);
99
100 return val;
101 }
102
103 /**
104 * temac_indirect_out32
105 *
106 * lp->indirect_mutex must be held when calling this function
107 */
108 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
109 {
110 if (temac_indirect_busywait(lp))
111 return;
112 temac_iow(lp, XTE_LSW0_OFFSET, value);
113 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
114 }
115
116 /**
117 * temac_dma_in32 - Memory mapped DMA read, this function expects a
118 * register input that is based on DCR word addresses which
119 * are then converted to memory mapped byte addresses
120 */
121 static u32 temac_dma_in32(struct temac_local *lp, int reg)
122 {
123 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
124 }
125
126 /**
127 * temac_dma_out32 - Memory mapped DMA read, this function expects a
128 * register input that is based on DCR word addresses which
129 * are then converted to memory mapped byte addresses
130 */
131 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
132 {
133 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
134 }
135
136 /* DMA register access functions can be DCR based or memory mapped.
137 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
138 * memory mapped.
139 */
140 #ifdef CONFIG_PPC_DCR
141
142 /**
143 * temac_dma_dcr_in32 - DCR based DMA read
144 */
145 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
146 {
147 return dcr_read(lp->sdma_dcrs, reg);
148 }
149
150 /**
151 * temac_dma_dcr_out32 - DCR based DMA write
152 */
153 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
154 {
155 dcr_write(lp->sdma_dcrs, reg, value);
156 }
157
158 /**
159 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
160 * I/O functions
161 */
162 static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
163 struct device_node *np)
164 {
165 unsigned int dcrs;
166
167 /* setup the dcr address mapping if it's in the device tree */
168
169 dcrs = dcr_resource_start(np, 0);
170 if (dcrs != 0) {
171 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
172 lp->dma_in = temac_dma_dcr_in;
173 lp->dma_out = temac_dma_dcr_out;
174 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
175 return 0;
176 }
177 /* no DCR in the device tree, indicate a failure */
178 return -1;
179 }
180
181 #else
182
183 /*
184 * temac_dcr_setup - This is a stub for when DCR is not supported,
185 * such as with MicroBlaze
186 */
187 static int temac_dcr_setup(struct temac_local *lp, struct of_device *op,
188 struct device_node *np)
189 {
190 return -1;
191 }
192
193 #endif
194
195 /**
196 * temac_dma_bd_init - Setup buffer descriptor rings
197 */
198 static int temac_dma_bd_init(struct net_device *ndev)
199 {
200 struct temac_local *lp = netdev_priv(ndev);
201 struct sk_buff *skb;
202 int i;
203
204 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
205 if (!lp->rx_skb) {
206 dev_err(&ndev->dev,
207 "can't allocate memory for DMA RX buffer\n");
208 goto out;
209 }
210 /* allocate the tx and rx ring buffer descriptors. */
211 /* returns a virtual addres and a physical address. */
212 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
213 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
214 &lp->tx_bd_p, GFP_KERNEL);
215 if (!lp->tx_bd_v) {
216 dev_err(&ndev->dev,
217 "unable to allocate DMA TX buffer descriptors");
218 goto out;
219 }
220 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
221 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
222 &lp->rx_bd_p, GFP_KERNEL);
223 if (!lp->rx_bd_v) {
224 dev_err(&ndev->dev,
225 "unable to allocate DMA RX buffer descriptors");
226 goto out;
227 }
228
229 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
230 for (i = 0; i < TX_BD_NUM; i++) {
231 lp->tx_bd_v[i].next = lp->tx_bd_p +
232 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
233 }
234
235 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
236 for (i = 0; i < RX_BD_NUM; i++) {
237 lp->rx_bd_v[i].next = lp->rx_bd_p +
238 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
239
240 skb = netdev_alloc_skb_ip_align(ndev,
241 XTE_MAX_JUMBO_FRAME_SIZE);
242
243 if (skb == 0) {
244 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
245 goto out;
246 }
247 lp->rx_skb[i] = skb;
248 /* returns physical address of skb->data */
249 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
250 skb->data,
251 XTE_MAX_JUMBO_FRAME_SIZE,
252 DMA_FROM_DEVICE);
253 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
254 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
255 }
256
257 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
258 CHNL_CTRL_IRQ_EN |
259 CHNL_CTRL_IRQ_DLY_EN |
260 CHNL_CTRL_IRQ_COAL_EN);
261 /* 0x10220483 */
262 /* 0x00100483 */
263 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
264 CHNL_CTRL_IRQ_EN |
265 CHNL_CTRL_IRQ_DLY_EN |
266 CHNL_CTRL_IRQ_COAL_EN |
267 CHNL_CTRL_IRQ_IOE);
268 /* 0xff010283 */
269
270 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
271 lp->dma_out(lp, RX_TAILDESC_PTR,
272 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
273 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
274
275 return 0;
276
277 out:
278 return -ENOMEM;
279 }
280
281 /* ---------------------------------------------------------------------
282 * net_device_ops
283 */
284
285 static int temac_set_mac_address(struct net_device *ndev, void *address)
286 {
287 struct temac_local *lp = netdev_priv(ndev);
288
289 if (address)
290 memcpy(ndev->dev_addr, address, ETH_ALEN);
291
292 if (!is_valid_ether_addr(ndev->dev_addr))
293 random_ether_addr(ndev->dev_addr);
294
295 /* set up unicast MAC address filter set its mac address */
296 mutex_lock(&lp->indirect_mutex);
297 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
298 (ndev->dev_addr[0]) |
299 (ndev->dev_addr[1] << 8) |
300 (ndev->dev_addr[2] << 16) |
301 (ndev->dev_addr[3] << 24));
302 /* There are reserved bits in EUAW1
303 * so don't affect them Set MAC bits [47:32] in EUAW1 */
304 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
305 (ndev->dev_addr[4] & 0x000000ff) |
306 (ndev->dev_addr[5] << 8));
307 mutex_unlock(&lp->indirect_mutex);
308
309 return 0;
310 }
311
312 static int netdev_set_mac_address(struct net_device *ndev, void *p)
313 {
314 struct sockaddr *addr = p;
315
316 return temac_set_mac_address(ndev, addr->sa_data);
317 }
318
319 static void temac_set_multicast_list(struct net_device *ndev)
320 {
321 struct temac_local *lp = netdev_priv(ndev);
322 u32 multi_addr_msw, multi_addr_lsw, val;
323 int i;
324
325 mutex_lock(&lp->indirect_mutex);
326 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
327 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
328 /*
329 * We must make the kernel realise we had to move
330 * into promisc mode or we start all out war on
331 * the cable. If it was a promisc request the
332 * flag is already set. If not we assert it.
333 */
334 ndev->flags |= IFF_PROMISC;
335 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
336 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
337 } else if (!netdev_mc_empty(ndev)) {
338 struct netdev_hw_addr *ha;
339
340 i = 0;
341 netdev_for_each_mc_addr(ha, ndev) {
342 if (i >= MULTICAST_CAM_TABLE_NUM)
343 break;
344 multi_addr_msw = ((ha->addr[3] << 24) |
345 (ha->addr[2] << 16) |
346 (ha->addr[1] << 8) |
347 (ha->addr[0]));
348 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
349 multi_addr_msw);
350 multi_addr_lsw = ((ha->addr[5] << 8) |
351 (ha->addr[4]) | (i << 16));
352 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
353 multi_addr_lsw);
354 i++;
355 }
356 } else {
357 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
358 temac_indirect_out32(lp, XTE_AFM_OFFSET,
359 val & ~XTE_AFM_EPPRM_MASK);
360 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
361 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
362 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
363 }
364 mutex_unlock(&lp->indirect_mutex);
365 }
366
367 struct temac_option {
368 int flg;
369 u32 opt;
370 u32 reg;
371 u32 m_or;
372 u32 m_and;
373 } temac_options[] = {
374 /* Turn on jumbo packet support for both Rx and Tx */
375 {
376 .opt = XTE_OPTION_JUMBO,
377 .reg = XTE_TXC_OFFSET,
378 .m_or = XTE_TXC_TXJMBO_MASK,
379 },
380 {
381 .opt = XTE_OPTION_JUMBO,
382 .reg = XTE_RXC1_OFFSET,
383 .m_or =XTE_RXC1_RXJMBO_MASK,
384 },
385 /* Turn on VLAN packet support for both Rx and Tx */
386 {
387 .opt = XTE_OPTION_VLAN,
388 .reg = XTE_TXC_OFFSET,
389 .m_or =XTE_TXC_TXVLAN_MASK,
390 },
391 {
392 .opt = XTE_OPTION_VLAN,
393 .reg = XTE_RXC1_OFFSET,
394 .m_or =XTE_RXC1_RXVLAN_MASK,
395 },
396 /* Turn on FCS stripping on receive packets */
397 {
398 .opt = XTE_OPTION_FCS_STRIP,
399 .reg = XTE_RXC1_OFFSET,
400 .m_or =XTE_RXC1_RXFCS_MASK,
401 },
402 /* Turn on FCS insertion on transmit packets */
403 {
404 .opt = XTE_OPTION_FCS_INSERT,
405 .reg = XTE_TXC_OFFSET,
406 .m_or =XTE_TXC_TXFCS_MASK,
407 },
408 /* Turn on length/type field checking on receive packets */
409 {
410 .opt = XTE_OPTION_LENTYPE_ERR,
411 .reg = XTE_RXC1_OFFSET,
412 .m_or =XTE_RXC1_RXLT_MASK,
413 },
414 /* Turn on flow control */
415 {
416 .opt = XTE_OPTION_FLOW_CONTROL,
417 .reg = XTE_FCC_OFFSET,
418 .m_or =XTE_FCC_RXFLO_MASK,
419 },
420 /* Turn on flow control */
421 {
422 .opt = XTE_OPTION_FLOW_CONTROL,
423 .reg = XTE_FCC_OFFSET,
424 .m_or =XTE_FCC_TXFLO_MASK,
425 },
426 /* Turn on promiscuous frame filtering (all frames are received ) */
427 {
428 .opt = XTE_OPTION_PROMISC,
429 .reg = XTE_AFM_OFFSET,
430 .m_or =XTE_AFM_EPPRM_MASK,
431 },
432 /* Enable transmitter if not already enabled */
433 {
434 .opt = XTE_OPTION_TXEN,
435 .reg = XTE_TXC_OFFSET,
436 .m_or =XTE_TXC_TXEN_MASK,
437 },
438 /* Enable receiver? */
439 {
440 .opt = XTE_OPTION_RXEN,
441 .reg = XTE_RXC1_OFFSET,
442 .m_or =XTE_RXC1_RXEN_MASK,
443 },
444 {}
445 };
446
447 /**
448 * temac_setoptions
449 */
450 static u32 temac_setoptions(struct net_device *ndev, u32 options)
451 {
452 struct temac_local *lp = netdev_priv(ndev);
453 struct temac_option *tp = &temac_options[0];
454 int reg;
455
456 mutex_lock(&lp->indirect_mutex);
457 while (tp->opt) {
458 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
459 if (options & tp->opt)
460 reg |= tp->m_or;
461 temac_indirect_out32(lp, tp->reg, reg);
462 tp++;
463 }
464 lp->options |= options;
465 mutex_unlock(&lp->indirect_mutex);
466
467 return (0);
468 }
469
470 /* Initilize temac */
471 static void temac_device_reset(struct net_device *ndev)
472 {
473 struct temac_local *lp = netdev_priv(ndev);
474 u32 timeout;
475 u32 val;
476
477 /* Perform a software reset */
478
479 /* 0x300 host enable bit ? */
480 /* reset PHY through control register ?:1 */
481
482 dev_dbg(&ndev->dev, "%s()\n", __func__);
483
484 mutex_lock(&lp->indirect_mutex);
485 /* Reset the receiver and wait for it to finish reset */
486 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
487 timeout = 1000;
488 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
489 udelay(1);
490 if (--timeout == 0) {
491 dev_err(&ndev->dev,
492 "temac_device_reset RX reset timeout!!\n");
493 break;
494 }
495 }
496
497 /* Reset the transmitter and wait for it to finish reset */
498 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
499 timeout = 1000;
500 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
501 udelay(1);
502 if (--timeout == 0) {
503 dev_err(&ndev->dev,
504 "temac_device_reset TX reset timeout!!\n");
505 break;
506 }
507 }
508
509 /* Disable the receiver */
510 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
511 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
512
513 /* Reset Local Link (DMA) */
514 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
515 timeout = 1000;
516 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
517 udelay(1);
518 if (--timeout == 0) {
519 dev_err(&ndev->dev,
520 "temac_device_reset DMA reset timeout!!\n");
521 break;
522 }
523 }
524 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
525
526 if (temac_dma_bd_init(ndev)) {
527 dev_err(&ndev->dev,
528 "temac_device_reset descriptor allocation failed\n");
529 }
530
531 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
532 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
533 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
534 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
535
536 mutex_unlock(&lp->indirect_mutex);
537
538 /* Sync default options with HW
539 * but leave receiver and transmitter disabled. */
540 temac_setoptions(ndev,
541 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
542
543 temac_set_mac_address(ndev, NULL);
544
545 /* Set address filter table */
546 temac_set_multicast_list(ndev);
547 if (temac_setoptions(ndev, lp->options))
548 dev_err(&ndev->dev, "Error setting TEMAC options\n");
549
550 /* Init Driver variable */
551 ndev->trans_start = jiffies; /* prevent tx timeout */
552 }
553
554 void temac_adjust_link(struct net_device *ndev)
555 {
556 struct temac_local *lp = netdev_priv(ndev);
557 struct phy_device *phy = lp->phy_dev;
558 u32 mii_speed;
559 int link_state;
560
561 /* hash together the state values to decide if something has changed */
562 link_state = phy->speed | (phy->duplex << 1) | phy->link;
563
564 mutex_lock(&lp->indirect_mutex);
565 if (lp->last_link != link_state) {
566 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
567 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
568
569 switch (phy->speed) {
570 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
571 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
572 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
573 }
574
575 /* Write new speed setting out to TEMAC */
576 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
577 lp->last_link = link_state;
578 phy_print_status(phy);
579 }
580 mutex_unlock(&lp->indirect_mutex);
581 }
582
583 static void temac_start_xmit_done(struct net_device *ndev)
584 {
585 struct temac_local *lp = netdev_priv(ndev);
586 struct cdmac_bd *cur_p;
587 unsigned int stat = 0;
588
589 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
590 stat = cur_p->app0;
591
592 while (stat & STS_CTRL_APP0_CMPLT) {
593 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
594 DMA_TO_DEVICE);
595 if (cur_p->app4)
596 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
597 cur_p->app0 = 0;
598 cur_p->app1 = 0;
599 cur_p->app2 = 0;
600 cur_p->app3 = 0;
601 cur_p->app4 = 0;
602
603 ndev->stats.tx_packets++;
604 ndev->stats.tx_bytes += cur_p->len;
605
606 lp->tx_bd_ci++;
607 if (lp->tx_bd_ci >= TX_BD_NUM)
608 lp->tx_bd_ci = 0;
609
610 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
611 stat = cur_p->app0;
612 }
613
614 netif_wake_queue(ndev);
615 }
616
617 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
618 {
619 struct cdmac_bd *cur_p;
620 int tail;
621
622 tail = lp->tx_bd_tail;
623 cur_p = &lp->tx_bd_v[tail];
624
625 do {
626 if (cur_p->app0)
627 return NETDEV_TX_BUSY;
628
629 tail++;
630 if (tail >= TX_BD_NUM)
631 tail = 0;
632
633 cur_p = &lp->tx_bd_v[tail];
634 num_frag--;
635 } while (num_frag >= 0);
636
637 return 0;
638 }
639
640 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
641 {
642 struct temac_local *lp = netdev_priv(ndev);
643 struct cdmac_bd *cur_p;
644 dma_addr_t start_p, tail_p;
645 int ii;
646 unsigned long num_frag;
647 skb_frag_t *frag;
648
649 num_frag = skb_shinfo(skb)->nr_frags;
650 frag = &skb_shinfo(skb)->frags[0];
651 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
652 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
653
654 if (temac_check_tx_bd_space(lp, num_frag)) {
655 if (!netif_queue_stopped(ndev)) {
656 netif_stop_queue(ndev);
657 return NETDEV_TX_BUSY;
658 }
659 return NETDEV_TX_BUSY;
660 }
661
662 cur_p->app0 = 0;
663 if (skb->ip_summed == CHECKSUM_PARTIAL) {
664 unsigned int csum_start_off = skb_transport_offset(skb);
665 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
666
667 cur_p->app0 |= 1; /* TX Checksum Enabled */
668 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
669 cur_p->app2 = 0; /* initial checksum seed */
670 }
671
672 cur_p->app0 |= STS_CTRL_APP0_SOP;
673 cur_p->len = skb_headlen(skb);
674 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
675 DMA_TO_DEVICE);
676 cur_p->app4 = (unsigned long)skb;
677
678 for (ii = 0; ii < num_frag; ii++) {
679 lp->tx_bd_tail++;
680 if (lp->tx_bd_tail >= TX_BD_NUM)
681 lp->tx_bd_tail = 0;
682
683 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
684 cur_p->phys = dma_map_single(ndev->dev.parent,
685 (void *)page_address(frag->page) +
686 frag->page_offset,
687 frag->size, DMA_TO_DEVICE);
688 cur_p->len = frag->size;
689 cur_p->app0 = 0;
690 frag++;
691 }
692 cur_p->app0 |= STS_CTRL_APP0_EOP;
693
694 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
695 lp->tx_bd_tail++;
696 if (lp->tx_bd_tail >= TX_BD_NUM)
697 lp->tx_bd_tail = 0;
698
699 /* Kick off the transfer */
700 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
701
702 return NETDEV_TX_OK;
703 }
704
705
706 static void ll_temac_recv(struct net_device *ndev)
707 {
708 struct temac_local *lp = netdev_priv(ndev);
709 struct sk_buff *skb, *new_skb;
710 unsigned int bdstat;
711 struct cdmac_bd *cur_p;
712 dma_addr_t tail_p;
713 int length;
714 unsigned long flags;
715
716 spin_lock_irqsave(&lp->rx_lock, flags);
717
718 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
719 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
720
721 bdstat = cur_p->app0;
722 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
723
724 skb = lp->rx_skb[lp->rx_bd_ci];
725 length = cur_p->app4 & 0x3FFF;
726
727 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
728 DMA_FROM_DEVICE);
729
730 skb_put(skb, length);
731 skb->dev = ndev;
732 skb->protocol = eth_type_trans(skb, ndev);
733 skb->ip_summed = CHECKSUM_NONE;
734
735 /* if we're doing rx csum offload, set it up */
736 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
737 (skb->protocol == __constant_htons(ETH_P_IP)) &&
738 (skb->len > 64)) {
739
740 skb->csum = cur_p->app3 & 0xFFFF;
741 skb->ip_summed = CHECKSUM_COMPLETE;
742 }
743
744 netif_rx(skb);
745
746 ndev->stats.rx_packets++;
747 ndev->stats.rx_bytes += length;
748
749 new_skb = netdev_alloc_skb_ip_align(ndev,
750 XTE_MAX_JUMBO_FRAME_SIZE);
751
752 if (new_skb == 0) {
753 dev_err(&ndev->dev, "no memory for new sk_buff\n");
754 spin_unlock_irqrestore(&lp->rx_lock, flags);
755 return;
756 }
757
758 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
759 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
760 XTE_MAX_JUMBO_FRAME_SIZE,
761 DMA_FROM_DEVICE);
762 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
763 lp->rx_skb[lp->rx_bd_ci] = new_skb;
764
765 lp->rx_bd_ci++;
766 if (lp->rx_bd_ci >= RX_BD_NUM)
767 lp->rx_bd_ci = 0;
768
769 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
770 bdstat = cur_p->app0;
771 }
772 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
773
774 spin_unlock_irqrestore(&lp->rx_lock, flags);
775 }
776
777 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
778 {
779 struct net_device *ndev = _ndev;
780 struct temac_local *lp = netdev_priv(ndev);
781 unsigned int status;
782
783 status = lp->dma_in(lp, TX_IRQ_REG);
784 lp->dma_out(lp, TX_IRQ_REG, status);
785
786 if (status & (IRQ_COAL | IRQ_DLY))
787 temac_start_xmit_done(lp->ndev);
788 if (status & 0x080)
789 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
790
791 return IRQ_HANDLED;
792 }
793
794 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
795 {
796 struct net_device *ndev = _ndev;
797 struct temac_local *lp = netdev_priv(ndev);
798 unsigned int status;
799
800 /* Read and clear the status registers */
801 status = lp->dma_in(lp, RX_IRQ_REG);
802 lp->dma_out(lp, RX_IRQ_REG, status);
803
804 if (status & (IRQ_COAL | IRQ_DLY))
805 ll_temac_recv(lp->ndev);
806
807 return IRQ_HANDLED;
808 }
809
810 static int temac_open(struct net_device *ndev)
811 {
812 struct temac_local *lp = netdev_priv(ndev);
813 int rc;
814
815 dev_dbg(&ndev->dev, "temac_open()\n");
816
817 if (lp->phy_node) {
818 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
819 temac_adjust_link, 0, 0);
820 if (!lp->phy_dev) {
821 dev_err(lp->dev, "of_phy_connect() failed\n");
822 return -ENODEV;
823 }
824
825 phy_start(lp->phy_dev);
826 }
827
828 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
829 if (rc)
830 goto err_tx_irq;
831 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
832 if (rc)
833 goto err_rx_irq;
834
835 temac_device_reset(ndev);
836 return 0;
837
838 err_rx_irq:
839 free_irq(lp->tx_irq, ndev);
840 err_tx_irq:
841 if (lp->phy_dev)
842 phy_disconnect(lp->phy_dev);
843 lp->phy_dev = NULL;
844 dev_err(lp->dev, "request_irq() failed\n");
845 return rc;
846 }
847
848 static int temac_stop(struct net_device *ndev)
849 {
850 struct temac_local *lp = netdev_priv(ndev);
851
852 dev_dbg(&ndev->dev, "temac_close()\n");
853
854 free_irq(lp->tx_irq, ndev);
855 free_irq(lp->rx_irq, ndev);
856
857 if (lp->phy_dev)
858 phy_disconnect(lp->phy_dev);
859 lp->phy_dev = NULL;
860
861 return 0;
862 }
863
864 #ifdef CONFIG_NET_POLL_CONTROLLER
865 static void
866 temac_poll_controller(struct net_device *ndev)
867 {
868 struct temac_local *lp = netdev_priv(ndev);
869
870 disable_irq(lp->tx_irq);
871 disable_irq(lp->rx_irq);
872
873 ll_temac_rx_irq(lp->tx_irq, lp);
874 ll_temac_tx_irq(lp->rx_irq, lp);
875
876 enable_irq(lp->tx_irq);
877 enable_irq(lp->rx_irq);
878 }
879 #endif
880
881 static const struct net_device_ops temac_netdev_ops = {
882 .ndo_open = temac_open,
883 .ndo_stop = temac_stop,
884 .ndo_start_xmit = temac_start_xmit,
885 .ndo_set_mac_address = netdev_set_mac_address,
886 //.ndo_set_multicast_list = temac_set_multicast_list,
887 #ifdef CONFIG_NET_POLL_CONTROLLER
888 .ndo_poll_controller = temac_poll_controller,
889 #endif
890 };
891
892 /* ---------------------------------------------------------------------
893 * SYSFS device attributes
894 */
895 static ssize_t temac_show_llink_regs(struct device *dev,
896 struct device_attribute *attr, char *buf)
897 {
898 struct net_device *ndev = dev_get_drvdata(dev);
899 struct temac_local *lp = netdev_priv(ndev);
900 int i, len = 0;
901
902 for (i = 0; i < 0x11; i++)
903 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
904 (i % 8) == 7 ? "\n" : " ");
905 len += sprintf(buf + len, "\n");
906
907 return len;
908 }
909
910 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
911
912 static struct attribute *temac_device_attrs[] = {
913 &dev_attr_llink_regs.attr,
914 NULL,
915 };
916
917 static const struct attribute_group temac_attr_group = {
918 .attrs = temac_device_attrs,
919 };
920
921 static int __init
922 temac_of_probe(struct of_device *op, const struct of_device_id *match)
923 {
924 struct device_node *np;
925 struct temac_local *lp;
926 struct net_device *ndev;
927 const void *addr;
928 __be32 *p;
929 int size, rc = 0;
930
931 /* Init network device structure */
932 ndev = alloc_etherdev(sizeof(*lp));
933 if (!ndev) {
934 dev_err(&op->dev, "could not allocate device.\n");
935 return -ENOMEM;
936 }
937 ether_setup(ndev);
938 dev_set_drvdata(&op->dev, ndev);
939 SET_NETDEV_DEV(ndev, &op->dev);
940 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
941 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
942 ndev->netdev_ops = &temac_netdev_ops;
943 #if 0
944 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
945 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
946 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
947 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
948 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
949 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
950 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
951 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
952 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
953 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
954 ndev->features |= NETIF_F_LRO; /* large receive offload */
955 #endif
956
957 /* setup temac private info structure */
958 lp = netdev_priv(ndev);
959 lp->ndev = ndev;
960 lp->dev = &op->dev;
961 lp->options = XTE_OPTION_DEFAULTS;
962 spin_lock_init(&lp->rx_lock);
963 mutex_init(&lp->indirect_mutex);
964
965 /* map device registers */
966 lp->regs = of_iomap(op->dev.of_node, 0);
967 if (!lp->regs) {
968 dev_err(&op->dev, "could not map temac regs.\n");
969 goto nodev;
970 }
971
972 /* Setup checksum offload, but default to off if not specified */
973 lp->temac_features = 0;
974 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
975 if (p && be32_to_cpu(*p)) {
976 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
977 /* Can checksum TCP/UDP over IPv4. */
978 ndev->features |= NETIF_F_IP_CSUM;
979 }
980 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
981 if (p && be32_to_cpu(*p))
982 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
983
984 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
985 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
986 if (!np) {
987 dev_err(&op->dev, "could not find DMA node\n");
988 goto nodev;
989 }
990
991 /* Setup the DMA register accesses, could be DCR or memory mapped */
992 if (temac_dcr_setup(lp, op, np)) {
993
994 /* no DCR in the device tree, try non-DCR */
995 lp->sdma_regs = of_iomap(np, 0);
996 if (lp->sdma_regs) {
997 lp->dma_in = temac_dma_in32;
998 lp->dma_out = temac_dma_out32;
999 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1000 } else {
1001 dev_err(&op->dev, "unable to map DMA registers\n");
1002 goto nodev;
1003 }
1004 }
1005
1006 lp->rx_irq = irq_of_parse_and_map(np, 0);
1007 lp->tx_irq = irq_of_parse_and_map(np, 1);
1008 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
1009 dev_err(&op->dev, "could not determine irqs\n");
1010 rc = -ENOMEM;
1011 goto nodev;
1012 }
1013
1014 of_node_put(np); /* Finished with the DMA node; drop the reference */
1015
1016 /* Retrieve the MAC address */
1017 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1018 if ((!addr) || (size != 6)) {
1019 dev_err(&op->dev, "could not find MAC address\n");
1020 rc = -ENODEV;
1021 goto nodev;
1022 }
1023 temac_set_mac_address(ndev, (void *)addr);
1024
1025 rc = temac_mdio_setup(lp, op->dev.of_node);
1026 if (rc)
1027 dev_warn(&op->dev, "error registering MDIO bus\n");
1028
1029 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1030 if (lp->phy_node)
1031 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1032
1033 /* Add the device attributes */
1034 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1035 if (rc) {
1036 dev_err(lp->dev, "Error creating sysfs files\n");
1037 goto nodev;
1038 }
1039
1040 rc = register_netdev(lp->ndev);
1041 if (rc) {
1042 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1043 goto err_register_ndev;
1044 }
1045
1046 return 0;
1047
1048 err_register_ndev:
1049 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1050 nodev:
1051 free_netdev(ndev);
1052 ndev = NULL;
1053 return rc;
1054 }
1055
1056 static int __devexit temac_of_remove(struct of_device *op)
1057 {
1058 struct net_device *ndev = dev_get_drvdata(&op->dev);
1059 struct temac_local *lp = netdev_priv(ndev);
1060
1061 temac_mdio_teardown(lp);
1062 unregister_netdev(ndev);
1063 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1064 if (lp->phy_node)
1065 of_node_put(lp->phy_node);
1066 lp->phy_node = NULL;
1067 dev_set_drvdata(&op->dev, NULL);
1068 free_netdev(ndev);
1069 return 0;
1070 }
1071
1072 static struct of_device_id temac_of_match[] __devinitdata = {
1073 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1074 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1075 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1076 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1077 {},
1078 };
1079 MODULE_DEVICE_TABLE(of, temac_of_match);
1080
1081 static struct of_platform_driver temac_of_driver = {
1082 .probe = temac_of_probe,
1083 .remove = __devexit_p(temac_of_remove),
1084 .driver = {
1085 .owner = THIS_MODULE,
1086 .name = "xilinx_temac",
1087 .of_match_table = temac_of_match,
1088 },
1089 };
1090
1091 static int __init temac_init(void)
1092 {
1093 return of_register_platform_driver(&temac_of_driver);
1094 }
1095 module_init(temac_init);
1096
1097 static void __exit temac_exit(void)
1098 {
1099 of_unregister_platform_driver(&temac_of_driver);
1100 }
1101 module_exit(temac_exit);
1102
1103 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1104 MODULE_AUTHOR("Yoshio Kashiwagi");
1105 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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