2 * Network device driver for the MACE ethernet controller on
3 * Apple Powermacs. Assumes it's under a DBDMA controller.
5 * Copyright (C) 1996 Paul Mackerras.
8 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/netdevice.h>
11 #include <linux/etherdevice.h>
12 #include <linux/delay.h>
13 #include <linux/string.h>
14 #include <linux/timer.h>
15 #include <linux/init.h>
16 #include <linux/crc32.h>
17 #include <linux/spinlock.h>
18 #include <linux/bitrev.h>
20 #include <asm/dbdma.h>
22 #include <asm/pgtable.h>
23 #include <asm/macio.h>
27 static int port_aaui
= -1;
31 #define MAX_TX_ACTIVE 1
32 #define NCMDS_TX 1 /* dma commands per element in tx ring */
33 #define RX_BUFLEN (ETH_FRAME_LEN + 8)
34 #define TX_TIMEOUT HZ /* 1 second */
36 /* Chip rev needs workaround on HW & multicast addr change */
37 #define BROKEN_ADDRCHG_REV 0x0941
39 /* Bits in transmit DMA status */
40 #define TX_DMA_ERR 0x80
43 volatile struct mace __iomem
*mace
;
44 volatile struct dbdma_regs __iomem
*tx_dma
;
46 volatile struct dbdma_regs __iomem
*rx_dma
;
48 volatile struct dbdma_cmd
*tx_cmds
; /* xmit dma command list */
49 volatile struct dbdma_cmd
*rx_cmds
; /* recv dma command list */
50 struct sk_buff
*rx_bufs
[N_RX_RING
];
53 struct sk_buff
*tx_bufs
[N_TX_RING
];
57 unsigned char tx_fullup
;
58 unsigned char tx_active
;
59 unsigned char tx_bad_runt
;
60 struct timer_list tx_timeout
;
64 struct macio_dev
*mdev
;
69 * Number of bytes of private data per MACE: allow enough for
70 * the rx and tx dma commands plus a branch dma command each,
71 * and another 16 bytes to allow us to align the dma command
72 * buffers on a 16 byte boundary.
74 #define PRIV_BYTES (sizeof(struct mace_data) \
75 + (N_RX_RING + NCMDS_TX * N_TX_RING + 3) * sizeof(struct dbdma_cmd))
77 static int mace_open(struct net_device
*dev
);
78 static int mace_close(struct net_device
*dev
);
79 static int mace_xmit_start(struct sk_buff
*skb
, struct net_device
*dev
);
80 static void mace_set_multicast(struct net_device
*dev
);
81 static void mace_reset(struct net_device
*dev
);
82 static int mace_set_address(struct net_device
*dev
, void *addr
);
83 static irqreturn_t
mace_interrupt(int irq
, void *dev_id
);
84 static irqreturn_t
mace_txdma_intr(int irq
, void *dev_id
);
85 static irqreturn_t
mace_rxdma_intr(int irq
, void *dev_id
);
86 static void mace_set_timeout(struct net_device
*dev
);
87 static void mace_tx_timeout(unsigned long data
);
88 static inline void dbdma_reset(volatile struct dbdma_regs __iomem
*dma
);
89 static inline void mace_clean_rings(struct mace_data
*mp
);
90 static void __mace_set_address(struct net_device
*dev
, void *addr
);
93 * If we can't get a skbuff when we need it, we use this area for DMA.
95 static unsigned char *dummy_buf
;
97 static int __devinit
mace_probe(struct macio_dev
*mdev
, const struct of_device_id
*match
)
99 struct device_node
*mace
= macio_get_of_node(mdev
);
100 struct net_device
*dev
;
101 struct mace_data
*mp
;
102 const unsigned char *addr
;
103 int j
, rev
, rc
= -EBUSY
;
105 if (macio_resource_count(mdev
) != 3 || macio_irq_count(mdev
) != 3) {
106 printk(KERN_ERR
"can't use MACE %s: need 3 addrs and 3 irqs\n",
111 addr
= of_get_property(mace
, "mac-address", NULL
);
113 addr
= of_get_property(mace
, "local-mac-address", NULL
);
115 printk(KERN_ERR
"Can't get mac-address for MACE %s\n",
122 * lazy allocate the driver-wide dummy buffer. (Note that we
123 * never have more than one MACE in the system anyway)
125 if (dummy_buf
== NULL
) {
126 dummy_buf
= kmalloc(RX_BUFLEN
+2, GFP_KERNEL
);
127 if (dummy_buf
== NULL
) {
128 printk(KERN_ERR
"MACE: couldn't allocate dummy buffer\n");
133 if (macio_request_resources(mdev
, "mace")) {
134 printk(KERN_ERR
"MACE: can't request IO resources !\n");
138 dev
= alloc_etherdev(PRIV_BYTES
);
140 printk(KERN_ERR
"MACE: can't allocate ethernet device !\n");
144 SET_NETDEV_DEV(dev
, &mdev
->ofdev
.dev
);
148 macio_set_drvdata(mdev
, dev
);
150 dev
->base_addr
= macio_resource_start(mdev
, 0);
151 mp
->mace
= ioremap(dev
->base_addr
, 0x1000);
152 if (mp
->mace
== NULL
) {
153 printk(KERN_ERR
"MACE: can't map IO resources !\n");
157 dev
->irq
= macio_irq(mdev
, 0);
159 rev
= addr
[0] == 0 && addr
[1] == 0xA0;
160 for (j
= 0; j
< 6; ++j
) {
161 dev
->dev_addr
[j
] = rev
? bitrev8(addr
[j
]): addr
[j
];
163 mp
->chipid
= (in_8(&mp
->mace
->chipid_hi
) << 8) |
164 in_8(&mp
->mace
->chipid_lo
);
167 mp
= (struct mace_data
*) dev
->priv
;
168 mp
->maccc
= ENXMT
| ENRCV
;
170 mp
->tx_dma
= ioremap(macio_resource_start(mdev
, 1), 0x1000);
171 if (mp
->tx_dma
== NULL
) {
172 printk(KERN_ERR
"MACE: can't map TX DMA resources !\n");
176 mp
->tx_dma_intr
= macio_irq(mdev
, 1);
178 mp
->rx_dma
= ioremap(macio_resource_start(mdev
, 2), 0x1000);
179 if (mp
->rx_dma
== NULL
) {
180 printk(KERN_ERR
"MACE: can't map RX DMA resources !\n");
182 goto err_unmap_tx_dma
;
184 mp
->rx_dma_intr
= macio_irq(mdev
, 2);
186 mp
->tx_cmds
= (volatile struct dbdma_cmd
*) DBDMA_ALIGN(mp
+ 1);
187 mp
->rx_cmds
= mp
->tx_cmds
+ NCMDS_TX
* N_TX_RING
+ 1;
189 memset((char *) mp
->tx_cmds
, 0,
190 (NCMDS_TX
*N_TX_RING
+ N_RX_RING
+ 2) * sizeof(struct dbdma_cmd
));
191 init_timer(&mp
->tx_timeout
);
192 spin_lock_init(&mp
->lock
);
193 mp
->timeout_active
= 0;
196 mp
->port_aaui
= port_aaui
;
198 /* Apple Network Server uses the AAUI port */
199 if (machine_is_compatible("AAPL,ShinerESB"))
202 #ifdef CONFIG_MACE_AAUI_PORT
210 dev
->open
= mace_open
;
211 dev
->stop
= mace_close
;
212 dev
->hard_start_xmit
= mace_xmit_start
;
213 dev
->set_multicast_list
= mace_set_multicast
;
214 dev
->set_mac_address
= mace_set_address
;
217 * Most of what is below could be moved to mace_open()
221 rc
= request_irq(dev
->irq
, mace_interrupt
, 0, "MACE", dev
);
223 printk(KERN_ERR
"MACE: can't get irq %d\n", dev
->irq
);
224 goto err_unmap_rx_dma
;
226 rc
= request_irq(mp
->tx_dma_intr
, mace_txdma_intr
, 0, "MACE-txdma", dev
);
228 printk(KERN_ERR
"MACE: can't get irq %d\n", mp
->tx_dma_intr
);
231 rc
= request_irq(mp
->rx_dma_intr
, mace_rxdma_intr
, 0, "MACE-rxdma", dev
);
233 printk(KERN_ERR
"MACE: can't get irq %d\n", mp
->rx_dma_intr
);
234 goto err_free_tx_irq
;
237 rc
= register_netdev(dev
);
239 printk(KERN_ERR
"MACE: Cannot register net device, aborting.\n");
240 goto err_free_rx_irq
;
243 printk(KERN_INFO
"%s: MACE at", dev
->name
);
244 for (j
= 0; j
< 6; ++j
) {
245 printk("%c%.2x", (j
? ':': ' '), dev
->dev_addr
[j
]);
247 printk(", chip revision %d.%d\n", mp
->chipid
>> 8, mp
->chipid
& 0xff);
252 free_irq(macio_irq(mdev
, 2), dev
);
254 free_irq(macio_irq(mdev
, 1), dev
);
256 free_irq(macio_irq(mdev
, 0), dev
);
266 macio_release_resources(mdev
);
271 static int __devexit
mace_remove(struct macio_dev
*mdev
)
273 struct net_device
*dev
= macio_get_drvdata(mdev
);
274 struct mace_data
*mp
;
278 macio_set_drvdata(mdev
, NULL
);
282 unregister_netdev(dev
);
284 free_irq(dev
->irq
, dev
);
285 free_irq(mp
->tx_dma_intr
, dev
);
286 free_irq(mp
->rx_dma_intr
, dev
);
294 macio_release_resources(mdev
);
299 static void dbdma_reset(volatile struct dbdma_regs __iomem
*dma
)
303 out_le32(&dma
->control
, (WAKE
|FLUSH
|PAUSE
|RUN
) << 16);
306 * Yes this looks peculiar, but apparently it needs to be this
307 * way on some machines.
309 for (i
= 200; i
> 0; --i
)
310 if (ld_le32(&dma
->control
) & RUN
)
314 static void mace_reset(struct net_device
*dev
)
316 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
317 volatile struct mace __iomem
*mb
= mp
->mace
;
320 /* soft-reset the chip */
323 out_8(&mb
->biucc
, SWRST
);
324 if (in_8(&mb
->biucc
) & SWRST
) {
331 printk(KERN_ERR
"mace: cannot reset chip!\n");
335 out_8(&mb
->imr
, 0xff); /* disable all intrs for now */
337 out_8(&mb
->maccc
, 0); /* turn off tx, rx */
339 out_8(&mb
->biucc
, XMTSP_64
);
340 out_8(&mb
->utr
, RTRD
);
341 out_8(&mb
->fifocc
, RCVFW_32
| XMTFW_16
| XMTFWU
| RCVFWU
| XMTBRST
);
342 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
); /* auto-pad short frames */
343 out_8(&mb
->rcvfc
, 0);
345 /* load up the hardware address */
346 __mace_set_address(dev
, dev
->dev_addr
);
348 /* clear the multicast filter */
349 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
350 out_8(&mb
->iac
, LOGADDR
);
352 out_8(&mb
->iac
, ADDRCHG
| LOGADDR
);
353 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
356 for (i
= 0; i
< 8; ++i
)
357 out_8(&mb
->ladrf
, 0);
359 /* done changing address */
360 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
364 out_8(&mb
->plscc
, PORTSEL_AUI
+ ENPLSIO
);
366 out_8(&mb
->plscc
, PORTSEL_GPSI
+ ENPLSIO
);
369 static void __mace_set_address(struct net_device
*dev
, void *addr
)
371 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
372 volatile struct mace __iomem
*mb
= mp
->mace
;
373 unsigned char *p
= addr
;
376 /* load up the hardware address */
377 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
378 out_8(&mb
->iac
, PHYADDR
);
380 out_8(&mb
->iac
, ADDRCHG
| PHYADDR
);
381 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
384 for (i
= 0; i
< 6; ++i
)
385 out_8(&mb
->padr
, dev
->dev_addr
[i
] = p
[i
]);
386 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
390 static int mace_set_address(struct net_device
*dev
, void *addr
)
392 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
393 volatile struct mace __iomem
*mb
= mp
->mace
;
396 spin_lock_irqsave(&mp
->lock
, flags
);
398 __mace_set_address(dev
, addr
);
400 /* note: setting ADDRCHG clears ENRCV */
401 out_8(&mb
->maccc
, mp
->maccc
);
403 spin_unlock_irqrestore(&mp
->lock
, flags
);
407 static inline void mace_clean_rings(struct mace_data
*mp
)
411 /* free some skb's */
412 for (i
= 0; i
< N_RX_RING
; ++i
) {
413 if (mp
->rx_bufs
[i
] != 0) {
414 dev_kfree_skb(mp
->rx_bufs
[i
]);
415 mp
->rx_bufs
[i
] = NULL
;
418 for (i
= mp
->tx_empty
; i
!= mp
->tx_fill
; ) {
419 dev_kfree_skb(mp
->tx_bufs
[i
]);
420 if (++i
>= N_TX_RING
)
425 static int mace_open(struct net_device
*dev
)
427 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
428 volatile struct mace __iomem
*mb
= mp
->mace
;
429 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
430 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
431 volatile struct dbdma_cmd
*cp
;
439 /* initialize list of sk_buffs for receiving and set up recv dma */
440 mace_clean_rings(mp
);
441 memset((char *)mp
->rx_cmds
, 0, N_RX_RING
* sizeof(struct dbdma_cmd
));
443 for (i
= 0; i
< N_RX_RING
- 1; ++i
) {
444 skb
= dev_alloc_skb(RX_BUFLEN
+ 2);
448 skb_reserve(skb
, 2); /* so IP header lands on 4-byte bdry */
451 mp
->rx_bufs
[i
] = skb
;
452 st_le16(&cp
->req_count
, RX_BUFLEN
);
453 st_le16(&cp
->command
, INPUT_LAST
+ INTR_ALWAYS
);
454 st_le32(&cp
->phy_addr
, virt_to_bus(data
));
458 mp
->rx_bufs
[i
] = NULL
;
459 st_le16(&cp
->command
, DBDMA_STOP
);
463 /* Put a branch back to the beginning of the receive command list */
465 st_le16(&cp
->command
, DBDMA_NOP
+ BR_ALWAYS
);
466 st_le32(&cp
->cmd_dep
, virt_to_bus(mp
->rx_cmds
));
469 out_le32(&rd
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
470 out_le32(&rd
->cmdptr
, virt_to_bus(mp
->rx_cmds
));
471 out_le32(&rd
->control
, (RUN
<< 16) | RUN
);
473 /* put a branch at the end of the tx command list */
474 cp
= mp
->tx_cmds
+ NCMDS_TX
* N_TX_RING
;
475 st_le16(&cp
->command
, DBDMA_NOP
+ BR_ALWAYS
);
476 st_le32(&cp
->cmd_dep
, virt_to_bus(mp
->tx_cmds
));
479 out_le32(&td
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16);
480 out_le32(&td
->cmdptr
, virt_to_bus(mp
->tx_cmds
));
488 out_8(&mb
->maccc
, mp
->maccc
);
489 /* enable all interrupts except receive interrupts */
490 out_8(&mb
->imr
, RCVINT
);
495 static int mace_close(struct net_device
*dev
)
497 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
498 volatile struct mace __iomem
*mb
= mp
->mace
;
499 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
500 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
502 /* disable rx and tx */
503 out_8(&mb
->maccc
, 0);
504 out_8(&mb
->imr
, 0xff); /* disable all intrs */
506 /* disable rx and tx dma */
507 st_le32(&rd
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
508 st_le32(&td
->control
, (RUN
|PAUSE
|FLUSH
|WAKE
) << 16); /* clear run bit */
510 mace_clean_rings(mp
);
515 static inline void mace_set_timeout(struct net_device
*dev
)
517 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
519 if (mp
->timeout_active
)
520 del_timer(&mp
->tx_timeout
);
521 mp
->tx_timeout
.expires
= jiffies
+ TX_TIMEOUT
;
522 mp
->tx_timeout
.function
= mace_tx_timeout
;
523 mp
->tx_timeout
.data
= (unsigned long) dev
;
524 add_timer(&mp
->tx_timeout
);
525 mp
->timeout_active
= 1;
528 static int mace_xmit_start(struct sk_buff
*skb
, struct net_device
*dev
)
530 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
531 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
532 volatile struct dbdma_cmd
*cp
, *np
;
536 /* see if there's a free slot in the tx ring */
537 spin_lock_irqsave(&mp
->lock
, flags
);
540 if (next
>= N_TX_RING
)
542 if (next
== mp
->tx_empty
) {
543 netif_stop_queue(dev
);
545 spin_unlock_irqrestore(&mp
->lock
, flags
);
546 return 1; /* can't take it at the moment */
548 spin_unlock_irqrestore(&mp
->lock
, flags
);
550 /* partially fill in the dma command block */
552 if (len
> ETH_FRAME_LEN
) {
553 printk(KERN_DEBUG
"mace: xmit frame too long (%d)\n", len
);
556 mp
->tx_bufs
[fill
] = skb
;
557 cp
= mp
->tx_cmds
+ NCMDS_TX
* fill
;
558 st_le16(&cp
->req_count
, len
);
559 st_le32(&cp
->phy_addr
, virt_to_bus(skb
->data
));
561 np
= mp
->tx_cmds
+ NCMDS_TX
* next
;
562 out_le16(&np
->command
, DBDMA_STOP
);
564 /* poke the tx dma channel */
565 spin_lock_irqsave(&mp
->lock
, flags
);
567 if (!mp
->tx_bad_runt
&& mp
->tx_active
< MAX_TX_ACTIVE
) {
568 out_le16(&cp
->xfer_status
, 0);
569 out_le16(&cp
->command
, OUTPUT_LAST
);
570 out_le32(&td
->control
, ((RUN
|WAKE
) << 16) + (RUN
|WAKE
));
572 mace_set_timeout(dev
);
574 if (++next
>= N_TX_RING
)
576 if (next
== mp
->tx_empty
)
577 netif_stop_queue(dev
);
578 spin_unlock_irqrestore(&mp
->lock
, flags
);
583 static void mace_set_multicast(struct net_device
*dev
)
585 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
586 volatile struct mace __iomem
*mb
= mp
->mace
;
591 spin_lock_irqsave(&mp
->lock
, flags
);
593 if (dev
->flags
& IFF_PROMISC
) {
596 unsigned char multicast_filter
[8];
597 struct dev_mc_list
*dmi
= dev
->mc_list
;
599 if (dev
->flags
& IFF_ALLMULTI
) {
600 for (i
= 0; i
< 8; i
++)
601 multicast_filter
[i
] = 0xff;
603 for (i
= 0; i
< 8; i
++)
604 multicast_filter
[i
] = 0;
605 for (i
= 0; i
< dev
->mc_count
; i
++) {
606 crc
= ether_crc_le(6, dmi
->dmi_addr
);
607 j
= crc
>> 26; /* bit number in multicast_filter */
608 multicast_filter
[j
>> 3] |= 1 << (j
& 7);
613 printk("Multicast filter :");
614 for (i
= 0; i
< 8; i
++)
615 printk("%02x ", multicast_filter
[i
]);
619 if (mp
->chipid
== BROKEN_ADDRCHG_REV
)
620 out_8(&mb
->iac
, LOGADDR
);
622 out_8(&mb
->iac
, ADDRCHG
| LOGADDR
);
623 while ((in_8(&mb
->iac
) & ADDRCHG
) != 0)
626 for (i
= 0; i
< 8; ++i
)
627 out_8(&mb
->ladrf
, multicast_filter
[i
]);
628 if (mp
->chipid
!= BROKEN_ADDRCHG_REV
)
632 out_8(&mb
->maccc
, mp
->maccc
);
633 spin_unlock_irqrestore(&mp
->lock
, flags
);
636 static void mace_handle_misc_intrs(struct mace_data
*mp
, int intr
, struct net_device
*dev
)
638 volatile struct mace __iomem
*mb
= mp
->mace
;
639 static int mace_babbles
, mace_jabbers
;
642 dev
->stats
.rx_missed_errors
+= 256;
643 dev
->stats
.rx_missed_errors
+= in_8(&mb
->mpc
); /* reading clears it */
645 dev
->stats
.rx_length_errors
+= 256;
646 dev
->stats
.rx_length_errors
+= in_8(&mb
->rntpc
); /* reading clears it */
648 ++dev
->stats
.tx_heartbeat_errors
;
650 if (mace_babbles
++ < 4)
651 printk(KERN_DEBUG
"mace: babbling transmitter\n");
653 if (mace_jabbers
++ < 4)
654 printk(KERN_DEBUG
"mace: jabbering transceiver\n");
657 static irqreturn_t
mace_interrupt(int irq
, void *dev_id
)
659 struct net_device
*dev
= (struct net_device
*) dev_id
;
660 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
661 volatile struct mace __iomem
*mb
= mp
->mace
;
662 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
663 volatile struct dbdma_cmd
*cp
;
664 int intr
, fs
, i
, stat
, x
;
667 /* static int mace_last_fs, mace_last_xcount; */
669 spin_lock_irqsave(&mp
->lock
, flags
);
670 intr
= in_8(&mb
->ir
); /* read interrupt register */
671 in_8(&mb
->xmtrc
); /* get retries */
672 mace_handle_misc_intrs(mp
, intr
, dev
);
675 while (in_8(&mb
->pr
) & XMTSV
) {
676 del_timer(&mp
->tx_timeout
);
677 mp
->timeout_active
= 0;
679 * Clear any interrupt indication associated with this status
680 * word. This appears to unlatch any error indication from
681 * the DMA controller.
683 intr
= in_8(&mb
->ir
);
685 mace_handle_misc_intrs(mp
, intr
, dev
);
686 if (mp
->tx_bad_runt
) {
687 fs
= in_8(&mb
->xmtfs
);
689 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
);
692 dstat
= ld_le32(&td
->status
);
693 /* stop DMA controller */
694 out_le32(&td
->control
, RUN
<< 16);
696 * xcount is the number of complete frames which have been
697 * written to the fifo but for which status has not been read.
699 xcount
= (in_8(&mb
->fifofc
) >> XMTFC_SH
) & XMTFC_MASK
;
700 if (xcount
== 0 || (dstat
& DEAD
)) {
702 * If a packet was aborted before the DMA controller has
703 * finished transferring it, it seems that there are 2 bytes
704 * which are stuck in some buffer somewhere. These will get
705 * transmitted as soon as we read the frame status (which
706 * reenables the transmit data transfer request). Turning
707 * off the DMA controller and/or resetting the MACE doesn't
708 * help. So we disable auto-padding and FCS transmission
709 * so the two bytes will only be a runt packet which should
710 * be ignored by other stations.
712 out_8(&mb
->xmtfc
, DXMTFCS
);
714 fs
= in_8(&mb
->xmtfs
);
715 if ((fs
& XMTSV
) == 0) {
716 printk(KERN_ERR
"mace: xmtfs not valid! (fs=%x xc=%d ds=%x)\n",
720 * XXX mace likes to hang the machine after a xmtfs error.
721 * This is hard to reproduce, reseting *may* help
724 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
725 stat
= ld_le16(&cp
->xfer_status
);
726 if ((fs
& (UFLO
|LCOL
|LCAR
|RTRY
)) || (dstat
& DEAD
) || xcount
== 0) {
728 * Check whether there were in fact 2 bytes written to
732 x
= (in_8(&mb
->fifofc
) >> XMTFC_SH
) & XMTFC_MASK
;
734 /* there were two bytes with an end-of-packet indication */
736 mace_set_timeout(dev
);
739 * Either there weren't the two bytes buffered up, or they
740 * didn't have an end-of-packet indication.
741 * We flush the transmit FIFO just in case (by setting the
742 * XMTFWU bit with the transmitter disabled).
744 out_8(&mb
->maccc
, in_8(&mb
->maccc
) & ~ENXMT
);
745 out_8(&mb
->fifocc
, in_8(&mb
->fifocc
) | XMTFWU
);
747 out_8(&mb
->maccc
, in_8(&mb
->maccc
) | ENXMT
);
748 out_8(&mb
->xmtfc
, AUTO_PAD_XMIT
);
751 /* dma should have finished */
752 if (i
== mp
->tx_fill
) {
753 printk(KERN_DEBUG
"mace: tx ring ran out? (fs=%x xc=%d ds=%x)\n",
758 if (fs
& (UFLO
|LCOL
|LCAR
|RTRY
)) {
759 ++dev
->stats
.tx_errors
;
761 ++dev
->stats
.tx_carrier_errors
;
762 if (fs
& (UFLO
|LCOL
|RTRY
))
763 ++dev
->stats
.tx_aborted_errors
;
765 dev
->stats
.tx_bytes
+= mp
->tx_bufs
[i
]->len
;
766 ++dev
->stats
.tx_packets
;
768 dev_kfree_skb_irq(mp
->tx_bufs
[i
]);
770 if (++i
>= N_TX_RING
)
774 mace_last_xcount
= xcount
;
778 if (i
!= mp
->tx_empty
) {
780 netif_wake_queue(dev
);
786 if (!mp
->tx_bad_runt
&& i
!= mp
->tx_fill
&& mp
->tx_active
< MAX_TX_ACTIVE
) {
788 /* set up the next one */
789 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
790 out_le16(&cp
->xfer_status
, 0);
791 out_le16(&cp
->command
, OUTPUT_LAST
);
793 if (++i
>= N_TX_RING
)
795 } while (i
!= mp
->tx_fill
&& mp
->tx_active
< MAX_TX_ACTIVE
);
796 out_le32(&td
->control
, ((RUN
|WAKE
) << 16) + (RUN
|WAKE
));
797 mace_set_timeout(dev
);
799 spin_unlock_irqrestore(&mp
->lock
, flags
);
803 static void mace_tx_timeout(unsigned long data
)
805 struct net_device
*dev
= (struct net_device
*) data
;
806 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
807 volatile struct mace __iomem
*mb
= mp
->mace
;
808 volatile struct dbdma_regs __iomem
*td
= mp
->tx_dma
;
809 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
810 volatile struct dbdma_cmd
*cp
;
814 spin_lock_irqsave(&mp
->lock
, flags
);
815 mp
->timeout_active
= 0;
816 if (mp
->tx_active
== 0 && !mp
->tx_bad_runt
)
819 /* update various counters */
820 mace_handle_misc_intrs(mp
, in_8(&mb
->ir
), dev
);
822 cp
= mp
->tx_cmds
+ NCMDS_TX
* mp
->tx_empty
;
824 /* turn off both tx and rx and reset the chip */
825 out_8(&mb
->maccc
, 0);
826 printk(KERN_ERR
"mace: transmit timeout - resetting\n");
831 cp
= bus_to_virt(ld_le32(&rd
->cmdptr
));
833 out_le16(&cp
->xfer_status
, 0);
834 out_le32(&rd
->cmdptr
, virt_to_bus(cp
));
835 out_le32(&rd
->control
, (RUN
<< 16) | RUN
);
837 /* fix up the transmit side */
840 ++dev
->stats
.tx_errors
;
841 if (mp
->tx_bad_runt
) {
843 } else if (i
!= mp
->tx_fill
) {
844 dev_kfree_skb(mp
->tx_bufs
[i
]);
845 if (++i
>= N_TX_RING
)
850 netif_wake_queue(dev
);
851 if (i
!= mp
->tx_fill
) {
852 cp
= mp
->tx_cmds
+ NCMDS_TX
* i
;
853 out_le16(&cp
->xfer_status
, 0);
854 out_le16(&cp
->command
, OUTPUT_LAST
);
855 out_le32(&td
->cmdptr
, virt_to_bus(cp
));
856 out_le32(&td
->control
, (RUN
<< 16) | RUN
);
858 mace_set_timeout(dev
);
861 /* turn it back on */
862 out_8(&mb
->imr
, RCVINT
);
863 out_8(&mb
->maccc
, mp
->maccc
);
866 spin_unlock_irqrestore(&mp
->lock
, flags
);
869 static irqreturn_t
mace_txdma_intr(int irq
, void *dev_id
)
874 static irqreturn_t
mace_rxdma_intr(int irq
, void *dev_id
)
876 struct net_device
*dev
= (struct net_device
*) dev_id
;
877 struct mace_data
*mp
= (struct mace_data
*) dev
->priv
;
878 volatile struct dbdma_regs __iomem
*rd
= mp
->rx_dma
;
879 volatile struct dbdma_cmd
*cp
, *np
;
880 int i
, nb
, stat
, next
;
882 unsigned frame_status
;
883 static int mace_lost_status
;
887 spin_lock_irqsave(&mp
->lock
, flags
);
888 for (i
= mp
->rx_empty
; i
!= mp
->rx_fill
; ) {
889 cp
= mp
->rx_cmds
+ i
;
890 stat
= ld_le16(&cp
->xfer_status
);
891 if ((stat
& ACTIVE
) == 0) {
893 if (next
>= N_RX_RING
)
895 np
= mp
->rx_cmds
+ next
;
896 if (next
!= mp
->rx_fill
897 && (ld_le16(&np
->xfer_status
) & ACTIVE
) != 0) {
898 printk(KERN_DEBUG
"mace: lost a status word\n");
903 nb
= ld_le16(&cp
->req_count
) - ld_le16(&cp
->res_count
);
904 out_le16(&cp
->command
, DBDMA_STOP
);
905 /* got a packet, have a look at it */
906 skb
= mp
->rx_bufs
[i
];
908 ++dev
->stats
.rx_dropped
;
911 frame_status
= (data
[nb
-3] << 8) + data
[nb
-4];
912 if (frame_status
& (RS_OFLO
|RS_CLSN
|RS_FRAMERR
|RS_FCSERR
)) {
913 ++dev
->stats
.rx_errors
;
914 if (frame_status
& RS_OFLO
)
915 ++dev
->stats
.rx_over_errors
;
916 if (frame_status
& RS_FRAMERR
)
917 ++dev
->stats
.rx_frame_errors
;
918 if (frame_status
& RS_FCSERR
)
919 ++dev
->stats
.rx_crc_errors
;
921 /* Mace feature AUTO_STRIP_RCV is on by default, dropping the
922 * FCS on frames with 802.3 headers. This means that Ethernet
923 * frames have 8 extra octets at the end, while 802.3 frames
924 * have only 4. We need to correctly account for this. */
925 if (*(unsigned short *)(data
+12) < 1536) /* 802.3 header */
927 else /* Ethernet header; mace includes FCS */
930 skb
->protocol
= eth_type_trans(skb
, dev
);
931 dev
->stats
.rx_bytes
+= skb
->len
;
933 dev
->last_rx
= jiffies
;
934 mp
->rx_bufs
[i
] = NULL
;
935 ++dev
->stats
.rx_packets
;
938 ++dev
->stats
.rx_errors
;
939 ++dev
->stats
.rx_length_errors
;
942 /* advance to next */
943 if (++i
>= N_RX_RING
)
951 if (next
>= N_RX_RING
)
953 if (next
== mp
->rx_empty
)
955 cp
= mp
->rx_cmds
+ i
;
956 skb
= mp
->rx_bufs
[i
];
958 skb
= dev_alloc_skb(RX_BUFLEN
+ 2);
961 mp
->rx_bufs
[i
] = skb
;
964 st_le16(&cp
->req_count
, RX_BUFLEN
);
965 data
= skb
? skb
->data
: dummy_buf
;
966 st_le32(&cp
->phy_addr
, virt_to_bus(data
));
967 out_le16(&cp
->xfer_status
, 0);
968 out_le16(&cp
->command
, INPUT_LAST
+ INTR_ALWAYS
);
970 if ((ld_le32(&rd
->status
) & ACTIVE
) != 0) {
971 out_le32(&rd
->control
, (PAUSE
<< 16) | PAUSE
);
972 while ((in_le32(&rd
->status
) & ACTIVE
) != 0)
978 if (i
!= mp
->rx_fill
) {
979 out_le32(&rd
->control
, ((RUN
|WAKE
) << 16) | (RUN
|WAKE
));
982 spin_unlock_irqrestore(&mp
->lock
, flags
);
986 static struct of_device_id mace_match
[] =
993 MODULE_DEVICE_TABLE (of
, mace_match
);
995 static struct macio_driver mace_driver
=
998 .match_table
= mace_match
,
1000 .remove
= mace_remove
,
1004 static int __init
mace_init(void)
1006 return macio_register_driver(&mace_driver
);
1009 static void __exit
mace_cleanup(void)
1011 macio_unregister_driver(&mace_driver
);
1017 MODULE_AUTHOR("Paul Mackerras");
1018 MODULE_DESCRIPTION("PowerMac MACE driver.");
1019 module_param(port_aaui
, int, 0);
1020 MODULE_PARM_DESC(port_aaui
, "MACE uses AAUI port (0-1)");
1021 MODULE_LICENSE("GPL");
1023 module_init(mace_init
);
1024 module_exit(mace_cleanup
);
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