drivers/net/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/compiler.h>
  38 #include <linux/list.h>
  39 #include <linux/mutex.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/inet_lro.h>
  42
  43 #include <linux/mlx4/device.h>
  44 #include <linux/mlx4/qp.h>
  45 #include <linux/mlx4/cq.h>
  46 #include <linux/mlx4/srq.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "en_port.h"
  50
  51 #define DRV_NAME        "mlx4_en"
  52 #define DRV_VERSION     "1.4.1.1"
  53 #define DRV_RELDATE     "June 2009"
  54
  55
  56 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  57
  58 #define en_print(level, priv, format, arg...)                   \
  59         {                                                       \
  60         if ((priv)->registered)                                 \
  61                 printk(level "%s: %s: " format, DRV_NAME,       \
  62                         (priv->dev)->name, ## arg);             \
  63         else                                                    \
  64                 printk(level "%s: %s: Port %d: " format,        \
  65                         DRV_NAME, dev_name(&priv->mdev->pdev->dev), \
  66                         (priv)->port, ## arg);                  \
  67         }
  68
  69 #define en_dbg(mlevel, priv, format, arg...)                    \
  70         {                                                       \
  71         if (NETIF_MSG_##mlevel & priv->msg_enable)              \
  72                 en_print(KERN_DEBUG, priv, format, ## arg)      \
  73         }
  74 #define en_warn(priv, format, arg...)                           \
  75         en_print(KERN_WARNING, priv, format, ## arg)
  76 #define en_err(priv, format, arg...)                            \
  77         en_print(KERN_ERR, priv, format, ## arg)
  78
  79 #define mlx4_err(mdev, format, arg...) \
  80         printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
  81                 dev_name(&mdev->pdev->dev) , ## arg)
  82 #define mlx4_info(mdev, format, arg...) \
  83         printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
  84                 dev_name(&mdev->pdev->dev) , ## arg)
  85 #define mlx4_warn(mdev, format, arg...) \
  86         printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
  87                 dev_name(&mdev->pdev->dev) , ## arg)
  88
  89 /*
  90  * Device constants
  91  */
  92
  93
  94 #define MLX4_EN_PAGE_SHIFT      12
  95 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  96 #define MAX_TX_RINGS            16
  97 #define MAX_RX_RINGS            16
  98 #define MAX_RSS_MAP_SIZE        64
  99 #define RSS_FACTOR              2
 100 #define TXBB_SIZE               64
 101 #define HEADROOM                (2048 / TXBB_SIZE + 1)
 102 #define MAX_LSO_HDR_SIZE        92
 103 #define STAMP_STRIDE            64
 104 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
 105 #define STAMP_SHIFT             31
 106 #define STAMP_VAL               0x7fffffff
 107 #define STATS_DELAY             (HZ / 4)
 108
 109 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
 110 #define MAX_DESC_SIZE           512
 111 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
 112
 113 /*
 114  * OS related constants and tunables
 115  */
 116
 117 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 118
 119 #define MLX4_EN_ALLOC_ORDER     2
 120 #define MLX4_EN_ALLOC_SIZE      (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
 121
 122 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
 123
 124 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 125  * and 4K allocations) */
 126 enum {
 127         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 128         FRAG_SZ1 = 1024,
 129         FRAG_SZ2 = 4096,
 130         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 131 };
 132 #define MLX4_EN_MAX_RX_FRAGS    4
 133
 134 /* Maximum ring sizes */
 135 #define MLX4_EN_MAX_TX_SIZE     8192
 136 #define MLX4_EN_MAX_RX_SIZE     8192
 137
 138 /* Minimum ring size for our page-allocation sceme to work */
 139 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 140 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 141
 142 #define MLX4_EN_SMALL_PKT_SIZE          64
 143 #define MLX4_EN_NUM_TX_RINGS            8
 144 #define MLX4_EN_NUM_PPP_RINGS           8
 145 #define MLX4_EN_DEF_TX_RING_SIZE        512
 146 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 147
 148 /* Target number of packets to coalesce with interrupt moderation */
 149 #define MLX4_EN_RX_COAL_TARGET  44
 150 #define MLX4_EN_RX_COAL_TIME    0x10
 151
 152 #define MLX4_EN_TX_COAL_PKTS    5
 153 #define MLX4_EN_TX_COAL_TIME    0x80
 154
 155 #define MLX4_EN_RX_RATE_LOW             400000
 156 #define MLX4_EN_RX_COAL_TIME_LOW        0
 157 #define MLX4_EN_RX_RATE_HIGH            450000
 158 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 159 #define MLX4_EN_RX_SIZE_THRESH          1024
 160 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 161 #define MLX4_EN_SAMPLE_INTERVAL         0
 162
 163 #define MLX4_EN_AUTO_CONF       0xffff
 164
 165 #define MLX4_EN_DEF_RX_PAUSE    1
 166 #define MLX4_EN_DEF_TX_PAUSE    1
 167
 168 /* Interval between sucessive polls in the Tx routine when polling is used
 169    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 170 #define MLX4_EN_TX_POLL_MODER   16
 171 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 172
 173 #define ETH_LLC_SNAP_SIZE       8
 174
 175 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 176 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 177
 178 #define MLX4_EN_MIN_MTU         46
 179 #define ETH_BCAST               0xffffffffffffULL
 180
 181 #ifdef MLX4_EN_PERF_STAT
 182 /* Number of samples to 'average' */
 183 #define AVG_SIZE                        128
 184 #define AVG_FACTOR                      1024
 185 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 186
 187 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 188 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 189 #define AVG_PERF_COUNTER(cnt, sample) \
 190         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 191 #define GET_PERF_COUNTER(cnt)           (cnt)
 192 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 193
 194 #else
 195
 196 #define NUM_PERF_STATS                  0
 197 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 198 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 199 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 200 #define GET_PERF_COUNTER(cnt)           (0)
 201 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 202 #endif /* MLX4_EN_PERF_STAT */
 203
 204 /*
 205  * Configurables
 206  */
 207
 208 enum cq_type {
 209         RX = 0,
 210         TX = 1,
 211 };
 212
 213
 214 /*
 215  * Useful macros
 216  */
 217 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 218 #define XNOR(x, y)              (!(x) == !(y))
 219 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 220
 221
 222 struct mlx4_en_tx_info {
 223         struct sk_buff *skb;
 224         u32 nr_txbb;
 225         u8 linear;
 226         u8 data_offset;
 227         u8 inl;
 228 };
 229
 230
 231 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 232 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 233 #define MLX4_EN_MEMTYPE_PAD     0x100
 234 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 235
 236
 237 struct mlx4_en_tx_desc {
 238         struct mlx4_wqe_ctrl_seg ctrl;
 239         union {
 240                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 241                 struct mlx4_wqe_lso_seg lso;
 242                 struct mlx4_wqe_inline_seg inl;
 243         };
 244 };
 245
 246 #define MLX4_EN_USE_SRQ         0x01000000
 247
 248 struct mlx4_en_rx_alloc {
 249         struct page *page;
 250         u16 offset;
 251 };
 252
 253 struct mlx4_en_tx_ring {
 254         struct mlx4_hwq_resources wqres;
 255         u32 size ; /* number of TXBBs */
 256         u32 size_mask;
 257         u16 stride;
 258         u16 cqn;        /* index of port CQ associated with this ring */
 259         u32 prod;
 260         u32 cons;
 261         u32 buf_size;
 262         u32 doorbell_qpn;
 263         void *buf;
 264         u16 poll_cnt;
 265         int blocked;
 266         struct mlx4_en_tx_info *tx_info;
 267         u8 *bounce_buf;
 268         u32 last_nr_txbb;
 269         struct mlx4_qp qp;
 270         struct mlx4_qp_context context;
 271         int qpn;
 272         enum mlx4_qp_state qp_state;
 273         struct mlx4_srq dummy;
 274         unsigned long bytes;
 275         unsigned long packets;
 276         spinlock_t comp_lock;
 277 };
 278
 279 struct mlx4_en_rx_desc {
 280         struct mlx4_wqe_srq_next_seg next;
 281         /* actual number of entries depends on rx ring stride */
 282         struct mlx4_wqe_data_seg data[0];
 283 };
 284
 285 struct mlx4_en_rx_ring {
 286         struct mlx4_srq srq;
 287         struct mlx4_hwq_resources wqres;
 288         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 289         struct net_lro_mgr lro;
 290         u32 size ;      /* number of Rx descs*/
 291         u32 actual_size;
 292         u32 size_mask;
 293         u16 stride;
 294         u16 log_stride;
 295         u16 cqn;        /* index of port CQ associated with this ring */
 296         u32 prod;
 297         u32 cons;
 298         u32 buf_size;
 299         int need_refill;
 300         int full;
 301         void *buf;
 302         void *rx_info;
 303         unsigned long bytes;
 304         unsigned long packets;
 305 };
 306
 307
 308 static inline int mlx4_en_can_lro(__be16 status)
 309 {
 310         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 311                                      MLX4_CQE_STATUS_IPV4F      |
 312                                      MLX4_CQE_STATUS_IPV6       |
 313                                      MLX4_CQE_STATUS_IPV4OPT    |
 314                                      MLX4_CQE_STATUS_TCP        |
 315                                      MLX4_CQE_STATUS_UDP        |
 316                                      MLX4_CQE_STATUS_IPOK)) ==
 317                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 318                             MLX4_CQE_STATUS_IPOK |
 319                             MLX4_CQE_STATUS_TCP);
 320 }
 321
 322 struct mlx4_en_cq {
 323         struct mlx4_cq          mcq;
 324         struct mlx4_hwq_resources wqres;
 325         int                     ring;
 326         spinlock_t              lock;
 327         struct net_device      *dev;
 328         struct napi_struct      napi;
 329         /* Per-core Tx cq processing support */
 330         struct timer_list timer;
 331         int size;
 332         int buf_size;
 333         unsigned vector;
 334         enum cq_type is_tx;
 335         u16 moder_time;
 336         u16 moder_cnt;
 337         struct mlx4_cqe *buf;
 338 #define MLX4_EN_OPCODE_ERROR    0x1e
 339 };
 340
 341 struct mlx4_en_port_profile {
 342         u32 flags;
 343         u32 tx_ring_num;
 344         u32 rx_ring_num;
 345         u32 tx_ring_size;
 346         u32 rx_ring_size;
 347         u8 rx_pause;
 348         u8 rx_ppp;
 349         u8 tx_pause;
 350         u8 tx_ppp;
 351 };
 352
 353 struct mlx4_en_profile {
 354         int rss_xor;
 355         int num_lro;
 356         u8 rss_mask;
 357         u32 active_ports;
 358         u32 small_pkt_int;
 359         u8 no_reset;
 360         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 361 };
 362
 363 struct mlx4_en_dev {
 364         struct mlx4_dev         *dev;
 365         struct pci_dev          *pdev;
 366         struct mutex            state_lock;
 367         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 368         u32                     port_cnt;
 369         bool                    device_up;
 370         struct mlx4_en_profile  profile;
 371         u32                     LSO_support;
 372         struct workqueue_struct *workqueue;
 373         struct device           *dma_device;
 374         void __iomem            *uar_map;
 375         struct mlx4_uar         priv_uar;
 376         struct mlx4_mr          mr;
 377         u32                     priv_pdn;
 378         spinlock_t              uar_lock;
 379 };
 380
 381
 382 struct mlx4_en_rss_map {
 383         int size;
 384         int base_qpn;
 385         u16 map[MAX_RSS_MAP_SIZE];
 386         struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
 387         enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
 388         struct mlx4_qp indir_qp;
 389         enum mlx4_qp_state indir_state;
 390 };
 391
 392 struct mlx4_en_rss_context {
 393         __be32 base_qpn;
 394         __be32 default_qpn;
 395         u16 reserved;
 396         u8 hash_fn;
 397         u8 flags;
 398         __be32 rss_key[10];
 399 };
 400
 401 struct mlx4_en_pkt_stats {
 402         unsigned long broadcast;
 403         unsigned long rx_prio[8];
 404         unsigned long tx_prio[8];
 405 #define NUM_PKT_STATS           17
 406 };
 407
 408 struct mlx4_en_port_stats {
 409         unsigned long lro_aggregated;
 410         unsigned long lro_flushed;
 411         unsigned long lro_no_desc;
 412         unsigned long tso_packets;
 413         unsigned long queue_stopped;
 414         unsigned long wake_queue;
 415         unsigned long tx_timeout;
 416         unsigned long rx_alloc_failed;
 417         unsigned long rx_chksum_good;
 418         unsigned long rx_chksum_none;
 419         unsigned long tx_chksum_offload;
 420 #define NUM_PORT_STATS          11
 421 };
 422
 423 struct mlx4_en_perf_stats {
 424         u32 tx_poll;
 425         u64 tx_pktsz_avg;
 426         u32 inflight_avg;
 427         u16 tx_coal_avg;
 428         u16 rx_coal_avg;
 429         u32 napi_quota;
 430 #define NUM_PERF_COUNTERS               6
 431 };
 432
 433 struct mlx4_en_frag_info {
 434         u16 frag_size;
 435         u16 frag_prefix_size;
 436         u16 frag_stride;
 437         u16 frag_align;
 438         u16 last_offset;
 439
 440 };
 441
 442 struct mlx4_en_priv {
 443         struct mlx4_en_dev *mdev;
 444         struct mlx4_en_port_profile *prof;
 445         struct net_device *dev;
 446         struct vlan_group *vlgrp;
 447         struct net_device_stats stats;
 448         struct net_device_stats ret_stats;
 449         spinlock_t stats_lock;
 450
 451         unsigned long last_moder_packets;
 452         unsigned long last_moder_tx_packets;
 453         unsigned long last_moder_bytes;
 454         unsigned long last_moder_jiffies;
 455         int last_moder_time;
 456         u16 rx_usecs;
 457         u16 rx_frames;
 458         u16 tx_usecs;
 459         u16 tx_frames;
 460         u32 pkt_rate_low;
 461         u16 rx_usecs_low;
 462         u32 pkt_rate_high;
 463         u16 rx_usecs_high;
 464         u16 sample_interval;
 465         u16 adaptive_rx_coal;
 466         u32 msg_enable;
 467
 468         struct mlx4_hwq_resources res;
 469         int link_state;
 470         int last_link_state;
 471         bool port_up;
 472         int port;
 473         int registered;
 474         int allocated;
 475         int stride;
 476         int rx_csum;
 477         u64 mac;
 478         int mac_index;
 479         unsigned max_mtu;
 480         int base_qpn;
 481
 482         struct mlx4_en_rss_map rss_map;
 483         u32 flags;
 484 #define MLX4_EN_FLAG_PROMISC    0x1
 485         u32 tx_ring_num;
 486         u32 rx_ring_num;
 487         u32 rx_skb_size;
 488         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 489         u16 num_frags;
 490         u16 log_rx_info;
 491
 492         struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
 493         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 494         struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
 495         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 496         struct work_struct mcast_task;
 497         struct work_struct mac_task;
 498         struct delayed_work refill_task;
 499         struct work_struct watchdog_task;
 500         struct work_struct linkstate_task;
 501         struct delayed_work stats_task;
 502         struct mlx4_en_perf_stats pstats;
 503         struct mlx4_en_pkt_stats pkstats;
 504         struct mlx4_en_port_stats port_stats;
 505         struct dev_mc_list *mc_list;
 506         struct mlx4_en_stat_out_mbox hw_stats;
 507 };
 508
 509
 510 void mlx4_en_destroy_netdev(struct net_device *dev);
 511 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 512                         struct mlx4_en_port_profile *prof);
 513
 514 int mlx4_en_start_port(struct net_device *dev);
 515 void mlx4_en_stop_port(struct net_device *dev);
 516
 517 void mlx4_en_free_resources(struct mlx4_en_priv *priv);
 518 int mlx4_en_alloc_resources(struct mlx4_en_priv *priv);
 519
 520 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 521                       int entries, int ring, enum cq_type mode);
 522 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 523 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 524 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 525 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 526 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 527
 528 void mlx4_en_poll_tx_cq(unsigned long data);
 529 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 530 u16 mlx4_en_select_queue(struct net_device *dev, struct sk_buff *skb);
 531 int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 532
 533 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 534                            u32 size, u16 stride);
 535 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 536 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 537                              struct mlx4_en_tx_ring *ring,
 538                              int cq, int srqn);
 539 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 540                                 struct mlx4_en_tx_ring *ring);
 541
 542 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 543                            struct mlx4_en_rx_ring *ring,
 544                            u32 size, u16 stride);
 545 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 546                              struct mlx4_en_rx_ring *ring);
 547 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 548 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 549                                 struct mlx4_en_rx_ring *ring);
 550 int mlx4_en_process_rx_cq(struct net_device *dev,
 551                           struct mlx4_en_cq *cq,
 552                           int budget);
 553 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 554 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 555                              int is_tx, int rss, int qpn, int cqn, int srqn,
 556                              struct mlx4_qp_context *context);
 557 void mlx4_en_sqp_event(struct mlx4_qp *qp, enum mlx4_event event);
 558 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 559 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 560
 561 void mlx4_en_calc_rx_buf(struct net_device *dev);
 562 void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
 563                                  struct mlx4_en_rss_map *rss_map,
 564                                  int num_entries, int num_rings);
 565 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 566 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 567 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 568 void mlx4_en_rx_refill(struct work_struct *work);
 569 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 570
 571 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 572 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
 573 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
 574                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
 575 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 576                            u8 promisc);
 577
 578 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 579
 580 /*
 581  * Globals
 582  */
 583 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 584 #endif