drivers/net/mlx4/mlx4_en.h

   1 /*
   2  * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  */
  33
  34 #ifndef _MLX4_EN_H_
  35 #define _MLX4_EN_H_
  36
  37 #include <linux/compiler.h>
  38 #include <linux/list.h>
  39 #include <linux/mutex.h>
  40 #include <linux/netdevice.h>
  41 #include <linux/inet_lro.h>
  42
  43 #include <linux/mlx4/device.h>
  44 #include <linux/mlx4/qp.h>
  45 #include <linux/mlx4/cq.h>
  46 #include <linux/mlx4/srq.h>
  47 #include <linux/mlx4/doorbell.h>
  48
  49 #include "en_port.h"
  50
  51 #define DRV_NAME        "mlx4_en"
  52 #define DRV_VERSION     "1.4.0"
  53 #define DRV_RELDATE     "Sep 2008"
  54
  55
  56 #define MLX4_EN_MSG_LEVEL       (NETIF_MSG_LINK | NETIF_MSG_IFDOWN)
  57
  58 #define mlx4_dbg(mlevel, priv, format, arg...)  \
  59         if (NETIF_MSG_##mlevel & priv->msg_enable) \
  60         printk(KERN_DEBUG "%s %s: " format , DRV_NAME ,\
  61                 (dev_name(&priv->mdev->pdev->dev)) , ## arg)
  62
  63 #define mlx4_err(mdev, format, arg...) \
  64         printk(KERN_ERR "%s %s: " format , DRV_NAME ,\
  65                 (dev_name(&mdev->pdev->dev)) , ## arg)
  66 #define mlx4_info(mdev, format, arg...) \
  67         printk(KERN_INFO "%s %s: " format , DRV_NAME ,\
  68                 (dev_name(&mdev->pdev->dev)) , ## arg)
  69 #define mlx4_warn(mdev, format, arg...) \
  70         printk(KERN_WARNING "%s %s: " format , DRV_NAME ,\
  71                 (dev_name(&mdev->pdev->dev)) , ## arg)
  72
  73 /*
  74  * Device constants
  75  */
  76
  77
  78 #define MLX4_EN_PAGE_SHIFT      12
  79 #define MLX4_EN_PAGE_SIZE       (1 << MLX4_EN_PAGE_SHIFT)
  80 #define MAX_TX_RINGS            16
  81 #define MAX_RX_RINGS            16
  82 #define MAX_RSS_MAP_SIZE        64
  83 #define RSS_FACTOR              2
  84 #define TXBB_SIZE               64
  85 #define HEADROOM                (2048 / TXBB_SIZE + 1)
  86 #define MAX_LSO_HDR_SIZE        92
  87 #define STAMP_STRIDE            64
  88 #define STAMP_DWORDS            (STAMP_STRIDE / 4)
  89 #define STAMP_SHIFT             31
  90 #define STAMP_VAL               0x7fffffff
  91 #define STATS_DELAY             (HZ / 4)
  92
  93 /* Typical TSO descriptor with 16 gather entries is 352 bytes... */
  94 #define MAX_DESC_SIZE           512
  95 #define MAX_DESC_TXBBS          (MAX_DESC_SIZE / TXBB_SIZE)
  96
  97 /*
  98  * OS related constants and tunables
  99  */
 100
 101 #define MLX4_EN_WATCHDOG_TIMEOUT        (15 * HZ)
 102
 103 #define MLX4_EN_ALLOC_ORDER     2
 104 #define MLX4_EN_ALLOC_SIZE      (PAGE_SIZE << MLX4_EN_ALLOC_ORDER)
 105
 106 #define MLX4_EN_MAX_LRO_DESCRIPTORS     32
 107
 108 /* Receive fragment sizes; we use at most 4 fragments (for 9600 byte MTU
 109  * and 4K allocations) */
 110 enum {
 111         FRAG_SZ0 = 512 - NET_IP_ALIGN,
 112         FRAG_SZ1 = 1024,
 113         FRAG_SZ2 = 4096,
 114         FRAG_SZ3 = MLX4_EN_ALLOC_SIZE
 115 };
 116 #define MLX4_EN_MAX_RX_FRAGS    4
 117
 118 /* Minimum ring size for our page-allocation sceme to work */
 119 #define MLX4_EN_MIN_RX_SIZE     (MLX4_EN_ALLOC_SIZE / SMP_CACHE_BYTES)
 120 #define MLX4_EN_MIN_TX_SIZE     (4096 / TXBB_SIZE)
 121
 122 #define MLX4_EN_TX_RING_NUM             9
 123 #define MLX4_EN_DEF_TX_RING_SIZE        1024
 124 #define MLX4_EN_DEF_RX_RING_SIZE        1024
 125
 126 /* Target number of bytes to coalesce with interrupt moderation */
 127 #define MLX4_EN_RX_COAL_TARGET  0x20000
 128 #define MLX4_EN_RX_COAL_TIME    0x10
 129
 130 #define MLX4_EN_TX_COAL_PKTS    5
 131 #define MLX4_EN_TX_COAL_TIME    0x80
 132
 133 #define MLX4_EN_RX_RATE_LOW             400000
 134 #define MLX4_EN_RX_COAL_TIME_LOW        0
 135 #define MLX4_EN_RX_RATE_HIGH            450000
 136 #define MLX4_EN_RX_COAL_TIME_HIGH       128
 137 #define MLX4_EN_RX_SIZE_THRESH          1024
 138 #define MLX4_EN_RX_RATE_THRESH          (1000000 / MLX4_EN_RX_COAL_TIME_HIGH)
 139 #define MLX4_EN_SAMPLE_INTERVAL         0
 140
 141 #define MLX4_EN_AUTO_CONF       0xffff
 142
 143 #define MLX4_EN_DEF_RX_PAUSE    1
 144 #define MLX4_EN_DEF_TX_PAUSE    1
 145
 146 /* Interval between sucessive polls in the Tx routine when polling is used
 147    instead of interrupts (in per-core Tx rings) - should be power of 2 */
 148 #define MLX4_EN_TX_POLL_MODER   16
 149 #define MLX4_EN_TX_POLL_TIMEOUT (HZ / 4)
 150
 151 #define ETH_LLC_SNAP_SIZE       8
 152
 153 #define SMALL_PACKET_SIZE      (256 - NET_IP_ALIGN)
 154 #define HEADER_COPY_SIZE       (128 - NET_IP_ALIGN)
 155
 156 #define MLX4_EN_MIN_MTU         46
 157 #define ETH_BCAST               0xffffffffffffULL
 158
 159 #ifdef MLX4_EN_PERF_STAT
 160 /* Number of samples to 'average' */
 161 #define AVG_SIZE                        128
 162 #define AVG_FACTOR                      1024
 163 #define NUM_PERF_STATS                  NUM_PERF_COUNTERS
 164
 165 #define INC_PERF_COUNTER(cnt)           (++(cnt))
 166 #define ADD_PERF_COUNTER(cnt, add)      ((cnt) += (add))
 167 #define AVG_PERF_COUNTER(cnt, sample) \
 168         ((cnt) = ((cnt) * (AVG_SIZE - 1) + (sample) * AVG_FACTOR) / AVG_SIZE)
 169 #define GET_PERF_COUNTER(cnt)           (cnt)
 170 #define GET_AVG_PERF_COUNTER(cnt)       ((cnt) / AVG_FACTOR)
 171
 172 #else
 173
 174 #define NUM_PERF_STATS                  0
 175 #define INC_PERF_COUNTER(cnt)           do {} while (0)
 176 #define ADD_PERF_COUNTER(cnt, add)      do {} while (0)
 177 #define AVG_PERF_COUNTER(cnt, sample)   do {} while (0)
 178 #define GET_PERF_COUNTER(cnt)           (0)
 179 #define GET_AVG_PERF_COUNTER(cnt)       (0)
 180 #endif /* MLX4_EN_PERF_STAT */
 181
 182 /*
 183  * Configurables
 184  */
 185
 186 enum cq_type {
 187         RX = 0,
 188         TX = 1,
 189 };
 190
 191
 192 /*
 193  * Useful macros
 194  */
 195 #define ROUNDUP_LOG2(x)         ilog2(roundup_pow_of_two(x))
 196 #define XNOR(x, y)              (!(x) == !(y))
 197 #define ILLEGAL_MAC(addr)       (addr == 0xffffffffffffULL || addr == 0x0)
 198
 199
 200 struct mlx4_en_tx_info {
 201         struct sk_buff *skb;
 202         u32 nr_txbb;
 203         u8 linear;
 204         u8 data_offset;
 205 };
 206
 207
 208 #define MLX4_EN_BIT_DESC_OWN    0x80000000
 209 #define CTRL_SIZE       sizeof(struct mlx4_wqe_ctrl_seg)
 210 #define MLX4_EN_MEMTYPE_PAD     0x100
 211 #define DS_SIZE         sizeof(struct mlx4_wqe_data_seg)
 212
 213
 214 struct mlx4_en_tx_desc {
 215         struct mlx4_wqe_ctrl_seg ctrl;
 216         union {
 217                 struct mlx4_wqe_data_seg data; /* at least one data segment */
 218                 struct mlx4_wqe_lso_seg lso;
 219                 struct mlx4_wqe_inline_seg inl;
 220         };
 221 };
 222
 223 #define MLX4_EN_USE_SRQ         0x01000000
 224
 225 struct mlx4_en_rx_alloc {
 226         struct page *page;
 227         u16 offset;
 228 };
 229
 230 struct mlx4_en_tx_ring {
 231         struct mlx4_hwq_resources wqres;
 232         u32 size ; /* number of TXBBs */
 233         u32 size_mask;
 234         u16 stride;
 235         u16 cqn;        /* index of port CQ associated with this ring */
 236         u32 prod;
 237         u32 cons;
 238         u32 buf_size;
 239         u32 doorbell_qpn;
 240         void *buf;
 241         u16 poll_cnt;
 242         int blocked;
 243         struct mlx4_en_tx_info *tx_info;
 244         u8 *bounce_buf;
 245         u32 last_nr_txbb;
 246         struct mlx4_qp qp;
 247         struct mlx4_qp_context context;
 248         int qpn;
 249         enum mlx4_qp_state qp_state;
 250         struct mlx4_srq dummy;
 251         unsigned long bytes;
 252         unsigned long packets;
 253         spinlock_t comp_lock;
 254 };
 255
 256 struct mlx4_en_rx_desc {
 257         struct mlx4_wqe_srq_next_seg next;
 258         /* actual number of entries depends on rx ring stride */
 259         struct mlx4_wqe_data_seg data[0];
 260 };
 261
 262 struct mlx4_en_rx_ring {
 263         struct mlx4_srq srq;
 264         struct mlx4_hwq_resources wqres;
 265         struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
 266         struct net_lro_mgr lro;
 267         u32 size ;      /* number of Rx descs*/
 268         u32 actual_size;
 269         u32 size_mask;
 270         u16 stride;
 271         u16 log_stride;
 272         u16 cqn;        /* index of port CQ associated with this ring */
 273         u32 prod;
 274         u32 cons;
 275         u32 buf_size;
 276         int need_refill;
 277         int full;
 278         void *buf;
 279         void *rx_info;
 280         unsigned long bytes;
 281         unsigned long packets;
 282 };
 283
 284
 285 static inline int mlx4_en_can_lro(__be16 status)
 286 {
 287         return (status & cpu_to_be16(MLX4_CQE_STATUS_IPV4       |
 288                                      MLX4_CQE_STATUS_IPV4F      |
 289                                      MLX4_CQE_STATUS_IPV6       |
 290                                      MLX4_CQE_STATUS_IPV4OPT    |
 291                                      MLX4_CQE_STATUS_TCP        |
 292                                      MLX4_CQE_STATUS_UDP        |
 293                                      MLX4_CQE_STATUS_IPOK)) ==
 294                 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
 295                             MLX4_CQE_STATUS_IPOK |
 296                             MLX4_CQE_STATUS_TCP);
 297 }
 298
 299 struct mlx4_en_cq {
 300         struct mlx4_cq          mcq;
 301         struct mlx4_hwq_resources wqres;
 302         int                     ring;
 303         spinlock_t              lock;
 304         struct net_device      *dev;
 305         struct napi_struct      napi;
 306         /* Per-core Tx cq processing support */
 307         struct timer_list timer;
 308         int size;
 309         int buf_size;
 310         unsigned vector;
 311         enum cq_type is_tx;
 312         u16 moder_time;
 313         u16 moder_cnt;
 314         struct mlx4_cqe *buf;
 315 #define MLX4_EN_OPCODE_ERROR    0x1e
 316 };
 317
 318 struct mlx4_en_port_profile {
 319         u32 flags;
 320         u32 tx_ring_num;
 321         u32 rx_ring_num;
 322         u32 tx_ring_size;
 323         u32 rx_ring_size;
 324         u8 rx_pause;
 325         u8 rx_ppp;
 326         u8 tx_pause;
 327         u8 tx_ppp;
 328 };
 329
 330 struct mlx4_en_profile {
 331         int rss_xor;
 332         int num_lro;
 333         u8 rss_mask;
 334         u32 active_ports;
 335         u32 small_pkt_int;
 336         int rx_moder_cnt;
 337         int rx_moder_time;
 338         int auto_moder;
 339         u8 no_reset;
 340         struct mlx4_en_port_profile prof[MLX4_MAX_PORTS + 1];
 341 };
 342
 343 struct mlx4_en_dev {
 344         struct mlx4_dev         *dev;
 345         struct pci_dev          *pdev;
 346         struct mutex            state_lock;
 347         struct net_device       *pndev[MLX4_MAX_PORTS + 1];
 348         u32                     port_cnt;
 349         bool                    device_up;
 350         struct mlx4_en_profile  profile;
 351         u32                     LSO_support;
 352         struct workqueue_struct *workqueue;
 353         struct device           *dma_device;
 354         void __iomem            *uar_map;
 355         struct mlx4_uar         priv_uar;
 356         struct mlx4_mr          mr;
 357         u32                     priv_pdn;
 358         spinlock_t              uar_lock;
 359 };
 360
 361
 362 struct mlx4_en_rss_map {
 363         int size;
 364         int base_qpn;
 365         u16 map[MAX_RSS_MAP_SIZE];
 366         struct mlx4_qp qps[MAX_RSS_MAP_SIZE];
 367         enum mlx4_qp_state state[MAX_RSS_MAP_SIZE];
 368         struct mlx4_qp indir_qp;
 369         enum mlx4_qp_state indir_state;
 370 };
 371
 372 struct mlx4_en_rss_context {
 373         __be32 base_qpn;
 374         __be32 default_qpn;
 375         u16 reserved;
 376         u8 hash_fn;
 377         u8 flags;
 378         __be32 rss_key[10];
 379 };
 380
 381 struct mlx4_en_pkt_stats {
 382         unsigned long broadcast;
 383         unsigned long rx_prio[8];
 384         unsigned long tx_prio[8];
 385 #define NUM_PKT_STATS           17
 386 };
 387
 388 struct mlx4_en_port_stats {
 389         unsigned long lro_aggregated;
 390         unsigned long lro_flushed;
 391         unsigned long lro_no_desc;
 392         unsigned long tso_packets;
 393         unsigned long queue_stopped;
 394         unsigned long wake_queue;
 395         unsigned long tx_timeout;
 396         unsigned long rx_alloc_failed;
 397         unsigned long rx_chksum_good;
 398         unsigned long rx_chksum_none;
 399         unsigned long tx_chksum_offload;
 400 #define NUM_PORT_STATS          11
 401 };
 402
 403 struct mlx4_en_perf_stats {
 404         u32 tx_poll;
 405         u64 tx_pktsz_avg;
 406         u32 inflight_avg;
 407         u16 tx_coal_avg;
 408         u16 rx_coal_avg;
 409         u32 napi_quota;
 410 #define NUM_PERF_COUNTERS               6
 411 };
 412
 413 struct mlx4_en_frag_info {
 414         u16 frag_size;
 415         u16 frag_prefix_size;
 416         u16 frag_stride;
 417         u16 frag_align;
 418         u16 last_offset;
 419
 420 };
 421
 422 struct mlx4_en_priv {
 423         struct mlx4_en_dev *mdev;
 424         struct mlx4_en_port_profile *prof;
 425         struct net_device *dev;
 426         struct vlan_group *vlgrp;
 427         struct net_device_stats stats;
 428         struct net_device_stats ret_stats;
 429         spinlock_t stats_lock;
 430
 431         unsigned long last_moder_packets;
 432         unsigned long last_moder_tx_packets;
 433         unsigned long last_moder_bytes;
 434         unsigned long last_moder_jiffies;
 435         int last_moder_time;
 436         u16 rx_usecs;
 437         u16 rx_frames;
 438         u16 tx_usecs;
 439         u16 tx_frames;
 440         u32 pkt_rate_low;
 441         u16 rx_usecs_low;
 442         u32 pkt_rate_high;
 443         u16 rx_usecs_high;
 444         u16 sample_interval;
 445         u16 adaptive_rx_coal;
 446         u32 msg_enable;
 447
 448         struct mlx4_hwq_resources res;
 449         int link_state;
 450         int last_link_state;
 451         bool port_up;
 452         int port;
 453         int registered;
 454         int allocated;
 455         int stride;
 456         int rx_csum;
 457         u64 mac;
 458         int mac_index;
 459         unsigned max_mtu;
 460         int base_qpn;
 461
 462         struct mlx4_en_rss_map rss_map;
 463         u16 tx_prio_map[8];
 464         u32 flags;
 465 #define MLX4_EN_FLAG_PROMISC    0x1
 466         u32 tx_ring_num;
 467         u32 rx_ring_num;
 468         u32 rx_skb_size;
 469         struct mlx4_en_frag_info frag_info[MLX4_EN_MAX_RX_FRAGS];
 470         u16 num_frags;
 471         u16 log_rx_info;
 472
 473         struct mlx4_en_tx_ring tx_ring[MAX_TX_RINGS];
 474         struct mlx4_en_rx_ring rx_ring[MAX_RX_RINGS];
 475         struct mlx4_en_cq tx_cq[MAX_TX_RINGS];
 476         struct mlx4_en_cq rx_cq[MAX_RX_RINGS];
 477         struct work_struct mcast_task;
 478         struct work_struct mac_task;
 479         struct delayed_work refill_task;
 480         struct work_struct watchdog_task;
 481         struct work_struct linkstate_task;
 482         struct delayed_work stats_task;
 483         struct mlx4_en_perf_stats pstats;
 484         struct mlx4_en_pkt_stats pkstats;
 485         struct mlx4_en_port_stats port_stats;
 486         struct dev_mc_list *mc_list;
 487         struct mlx4_en_stat_out_mbox hw_stats;
 488 };
 489
 490
 491 void mlx4_en_destroy_netdev(struct net_device *dev);
 492 int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
 493                         struct mlx4_en_port_profile *prof);
 494
 495 int mlx4_en_get_profile(struct mlx4_en_dev *mdev);
 496
 497 int mlx4_en_create_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq,
 498                       int entries, int ring, enum cq_type mode);
 499 void mlx4_en_destroy_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 500 int mlx4_en_activate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 501 void mlx4_en_deactivate_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 502 int mlx4_en_set_cq_moder(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 503 int mlx4_en_arm_cq(struct mlx4_en_priv *priv, struct mlx4_en_cq *cq);
 504
 505 void mlx4_en_poll_tx_cq(unsigned long data);
 506 void mlx4_en_tx_irq(struct mlx4_cq *mcq);
 507 int mlx4_en_xmit(struct sk_buff *skb, struct net_device *dev);
 508
 509 int mlx4_en_create_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring,
 510                            u32 size, u16 stride);
 511 void mlx4_en_destroy_tx_ring(struct mlx4_en_priv *priv, struct mlx4_en_tx_ring *ring);
 512 int mlx4_en_activate_tx_ring(struct mlx4_en_priv *priv,
 513                              struct mlx4_en_tx_ring *ring,
 514                              int cq, int srqn);
 515 void mlx4_en_deactivate_tx_ring(struct mlx4_en_priv *priv,
 516                                 struct mlx4_en_tx_ring *ring);
 517
 518 int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
 519                            struct mlx4_en_rx_ring *ring,
 520                            u32 size, u16 stride);
 521 void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
 522                              struct mlx4_en_rx_ring *ring);
 523 int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv);
 524 void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
 525                                 struct mlx4_en_rx_ring *ring);
 526 int mlx4_en_process_rx_cq(struct net_device *dev,
 527                           struct mlx4_en_cq *cq,
 528                           int budget);
 529 int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget);
 530 void mlx4_en_fill_qp_context(struct mlx4_en_priv *priv, int size, int stride,
 531                              int is_tx, int rss, int qpn, int cqn, int srqn,
 532                              struct mlx4_qp_context *context);
 533 int mlx4_en_map_buffer(struct mlx4_buf *buf);
 534 void mlx4_en_unmap_buffer(struct mlx4_buf *buf);
 535
 536 void mlx4_en_calc_rx_buf(struct net_device *dev);
 537 void mlx4_en_set_default_rss_map(struct mlx4_en_priv *priv,
 538                                  struct mlx4_en_rss_map *rss_map,
 539                                  int num_entries, int num_rings);
 540 void mlx4_en_set_prio_map(struct mlx4_en_priv *priv, u16 *prio_map, u32 ring_num);
 541 int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv);
 542 void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv);
 543 int mlx4_en_free_tx_buf(struct net_device *dev, struct mlx4_en_tx_ring *ring);
 544 void mlx4_en_rx_refill(struct work_struct *work);
 545 void mlx4_en_rx_irq(struct mlx4_cq *mcq);
 546
 547 int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
 548 int mlx4_SET_VLAN_FLTR(struct mlx4_dev *dev, u8 port, struct vlan_group *grp);
 549 int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
 550                           u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
 551 int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
 552                            u8 promisc);
 553
 554 int mlx4_en_DUMP_ETH_STATS(struct mlx4_en_dev *mdev, u8 port, u8 reset);
 555
 556 /*
 557  * Globals
 558  */
 559 extern const struct ethtool_ops mlx4_en_ethtool_ops;
 560 #endif