2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
53 /* Static function declarations */
54 static void eth_port_uc_addr_get(unsigned int port_num
, unsigned char *p_addr
);
55 static void eth_port_uc_addr_set(unsigned int port_num
, unsigned char *p_addr
);
56 static void eth_port_set_multicast_list(struct net_device
*);
57 static void mv643xx_eth_port_enable_tx(unsigned int port_num
,
59 static void mv643xx_eth_port_enable_rx(unsigned int port_num
,
61 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num
);
62 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num
);
63 static int mv643xx_eth_open(struct net_device
*);
64 static int mv643xx_eth_stop(struct net_device
*);
65 static int mv643xx_eth_change_mtu(struct net_device
*, int);
66 static void eth_port_init_mac_tables(unsigned int eth_port_num
);
68 static int mv643xx_poll(struct napi_struct
*napi
, int budget
);
70 static int ethernet_phy_get(unsigned int eth_port_num
);
71 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
72 static int ethernet_phy_detect(unsigned int eth_port_num
);
73 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
);
74 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
);
75 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
);
76 static const struct ethtool_ops mv643xx_ethtool_ops
;
78 static char mv643xx_driver_name
[] = "mv643xx_eth";
79 static char mv643xx_driver_version
[] = "1.0";
81 static void __iomem
*mv643xx_eth_shared_base
;
83 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
84 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
86 static inline u32
mv_read(int offset
)
88 void __iomem
*reg_base
;
90 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
92 return readl(reg_base
+ offset
);
95 static inline void mv_write(int offset
, u32 data
)
97 void __iomem
*reg_base
;
99 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
100 writel(data
, reg_base
+ offset
);
104 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
106 * Input : pointer to ethernet interface network device structure
108 * Output : 0 upon success, -EINVAL upon failure
110 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
112 if ((new_mtu
> 9500) || (new_mtu
< 64))
117 * Stop then re-open the interface. This will allocate RX skb's with
119 * There is a possible danger that the open will not successed, due
120 * to memory is full, which might fail the open function.
122 if (netif_running(dev
)) {
123 mv643xx_eth_stop(dev
);
124 if (mv643xx_eth_open(dev
))
126 "%s: Fatal error on opening device\n",
134 * mv643xx_eth_rx_refill_descs
136 * Fills / refills RX queue on a certain gigabit ethernet port
138 * Input : pointer to ethernet interface network device structure
141 static void mv643xx_eth_rx_refill_descs(struct net_device
*dev
)
143 struct mv643xx_private
*mp
= netdev_priv(dev
);
144 struct pkt_info pkt_info
;
148 while (mp
->rx_desc_count
< mp
->rx_ring_size
) {
149 skb
= dev_alloc_skb(ETH_RX_SKB_SIZE
+ dma_get_cache_alignment());
153 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
155 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
156 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
157 pkt_info
.byte_cnt
= ETH_RX_SKB_SIZE
;
158 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
159 ETH_RX_SKB_SIZE
, DMA_FROM_DEVICE
);
160 pkt_info
.return_info
= skb
;
161 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
163 "%s: Error allocating RX Ring\n", dev
->name
);
166 skb_reserve(skb
, ETH_HW_IP_ALIGN
);
169 * If RX ring is empty of SKB, set a timer to try allocating
170 * again at a later time.
172 if (mp
->rx_desc_count
== 0) {
173 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
174 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10); /* 100 mSec */
175 add_timer(&mp
->timeout
);
180 * mv643xx_eth_rx_refill_descs_timer_wrapper
182 * Timer routine to wake up RX queue filling task. This function is
183 * used only in case the RX queue is empty, and all alloc_skb has
184 * failed (due to out of memory event).
186 * Input : pointer to ethernet interface network device structure
189 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data
)
191 mv643xx_eth_rx_refill_descs((struct net_device
*)data
);
195 * mv643xx_eth_update_mac_address
197 * Update the MAC address of the port in the address table
199 * Input : pointer to ethernet interface network device structure
202 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
204 struct mv643xx_private
*mp
= netdev_priv(dev
);
205 unsigned int port_num
= mp
->port_num
;
207 eth_port_init_mac_tables(port_num
);
208 eth_port_uc_addr_set(port_num
, dev
->dev_addr
);
212 * mv643xx_eth_set_rx_mode
214 * Change from promiscuos to regular rx mode
216 * Input : pointer to ethernet interface network device structure
219 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
221 struct mv643xx_private
*mp
= netdev_priv(dev
);
224 config_reg
= mv_read(MV643XX_ETH_PORT_CONFIG_REG(mp
->port_num
));
225 if (dev
->flags
& IFF_PROMISC
)
226 config_reg
|= (u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
228 config_reg
&= ~(u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
229 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp
->port_num
), config_reg
);
231 eth_port_set_multicast_list(dev
);
235 * mv643xx_eth_set_mac_address
237 * Change the interface's mac address.
238 * No special hardware thing should be done because interface is always
239 * put in promiscuous mode.
241 * Input : pointer to ethernet interface network device structure and
242 * a pointer to the designated entry to be added to the cache.
243 * Output : zero upon success, negative upon failure
245 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
249 for (i
= 0; i
< 6; i
++)
250 /* +2 is for the offset of the HW addr type */
251 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
252 mv643xx_eth_update_mac_address(dev
);
257 * mv643xx_eth_tx_timeout
259 * Called upon a timeout on transmitting a packet
261 * Input : pointer to ethernet interface network device structure.
264 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
266 struct mv643xx_private
*mp
= netdev_priv(dev
);
268 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
270 /* Do the reset outside of interrupt context */
271 schedule_work(&mp
->tx_timeout_task
);
275 * mv643xx_eth_tx_timeout_task
277 * Actual routine to reset the adapter when a timeout on Tx has occurred
279 static void mv643xx_eth_tx_timeout_task(struct work_struct
*ugly
)
281 struct mv643xx_private
*mp
= container_of(ugly
, struct mv643xx_private
,
283 struct net_device
*dev
= mp
->mii
.dev
; /* yuck */
285 if (!netif_running(dev
))
288 netif_stop_queue(dev
);
290 eth_port_reset(mp
->port_num
);
293 if (mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
294 netif_wake_queue(dev
);
298 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
300 * If force is non-zero, frees uncompleted descriptors as well
302 int mv643xx_eth_free_tx_descs(struct net_device
*dev
, int force
)
304 struct mv643xx_private
*mp
= netdev_priv(dev
);
305 struct eth_tx_desc
*desc
;
314 while (mp
->tx_desc_count
> 0) {
315 spin_lock_irqsave(&mp
->lock
, flags
);
317 /* tx_desc_count might have changed before acquiring the lock */
318 if (mp
->tx_desc_count
<= 0) {
319 spin_unlock_irqrestore(&mp
->lock
, flags
);
323 tx_index
= mp
->tx_used_desc_q
;
324 desc
= &mp
->p_tx_desc_area
[tx_index
];
325 cmd_sts
= desc
->cmd_sts
;
327 if (!force
&& (cmd_sts
& ETH_BUFFER_OWNED_BY_DMA
)) {
328 spin_unlock_irqrestore(&mp
->lock
, flags
);
332 mp
->tx_used_desc_q
= (tx_index
+ 1) % mp
->tx_ring_size
;
335 addr
= desc
->buf_ptr
;
336 count
= desc
->byte_cnt
;
337 skb
= mp
->tx_skb
[tx_index
];
339 mp
->tx_skb
[tx_index
] = NULL
;
341 if (cmd_sts
& ETH_ERROR_SUMMARY
) {
342 printk("%s: Error in TX\n", dev
->name
);
343 dev
->stats
.tx_errors
++;
346 spin_unlock_irqrestore(&mp
->lock
, flags
);
348 if (cmd_sts
& ETH_TX_FIRST_DESC
)
349 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
351 dma_unmap_page(NULL
, addr
, count
, DMA_TO_DEVICE
);
354 dev_kfree_skb_irq(skb
);
362 static void mv643xx_eth_free_completed_tx_descs(struct net_device
*dev
)
364 struct mv643xx_private
*mp
= netdev_priv(dev
);
366 if (mv643xx_eth_free_tx_descs(dev
, 0) &&
367 mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
368 netif_wake_queue(dev
);
371 static void mv643xx_eth_free_all_tx_descs(struct net_device
*dev
)
373 mv643xx_eth_free_tx_descs(dev
, 1);
377 * mv643xx_eth_receive
379 * This function is forward packets that are received from the port's
380 * queues toward kernel core or FastRoute them to another interface.
382 * Input : dev - a pointer to the required interface
383 * max - maximum number to receive (0 means unlimted)
385 * Output : number of served packets
387 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
389 struct mv643xx_private
*mp
= netdev_priv(dev
);
390 struct net_device_stats
*stats
= &dev
->stats
;
391 unsigned int received_packets
= 0;
393 struct pkt_info pkt_info
;
395 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
396 dma_unmap_single(NULL
, pkt_info
.buf_ptr
, ETH_RX_SKB_SIZE
,
403 * Note byte count includes 4 byte CRC count
406 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
407 skb
= pkt_info
.return_info
;
409 * In case received a packet without first / last bits on OR
410 * the error summary bit is on, the packets needs to be dropeed.
412 if (((pkt_info
.cmd_sts
413 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
414 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
415 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
417 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
418 ETH_RX_LAST_DESC
)) !=
419 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
422 "%s: Received packet spread "
423 "on multiple descriptors\n",
426 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
429 dev_kfree_skb_irq(skb
);
432 * The -4 is for the CRC in the trailer of the
435 skb_put(skb
, pkt_info
.byte_cnt
- 4);
437 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
438 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
440 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
442 skb
->protocol
= eth_type_trans(skb
, dev
);
444 netif_receive_skb(skb
);
449 dev
->last_rx
= jiffies
;
451 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
453 return received_packets
;
456 /* Set the mv643xx port configuration register for the speed/duplex mode. */
457 static void mv643xx_eth_update_pscr(struct net_device
*dev
,
458 struct ethtool_cmd
*ecmd
)
460 struct mv643xx_private
*mp
= netdev_priv(dev
);
461 int port_num
= mp
->port_num
;
465 o_pscr
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
468 /* clear speed, duplex and rx buffer size fields */
469 n_pscr
&= ~(MV643XX_ETH_SET_MII_SPEED_TO_100
|
470 MV643XX_ETH_SET_GMII_SPEED_TO_1000
|
471 MV643XX_ETH_SET_FULL_DUPLEX_MODE
|
472 MV643XX_ETH_MAX_RX_PACKET_MASK
);
474 if (ecmd
->duplex
== DUPLEX_FULL
)
475 n_pscr
|= MV643XX_ETH_SET_FULL_DUPLEX_MODE
;
477 if (ecmd
->speed
== SPEED_1000
)
478 n_pscr
|= MV643XX_ETH_SET_GMII_SPEED_TO_1000
|
479 MV643XX_ETH_MAX_RX_PACKET_9700BYTE
;
481 if (ecmd
->speed
== SPEED_100
)
482 n_pscr
|= MV643XX_ETH_SET_MII_SPEED_TO_100
;
483 n_pscr
|= MV643XX_ETH_MAX_RX_PACKET_1522BYTE
;
486 if (n_pscr
!= o_pscr
) {
487 if ((o_pscr
& MV643XX_ETH_SERIAL_PORT_ENABLE
) == 0)
488 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
491 queues
= mv643xx_eth_port_disable_tx(port_num
);
493 o_pscr
&= ~MV643XX_ETH_SERIAL_PORT_ENABLE
;
494 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
496 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
498 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
501 mv643xx_eth_port_enable_tx(port_num
, queues
);
507 * mv643xx_eth_int_handler
509 * Main interrupt handler for the gigbit ethernet ports
511 * Input : irq - irq number (not used)
512 * dev_id - a pointer to the required interface's data structure
517 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
)
519 struct net_device
*dev
= (struct net_device
*)dev_id
;
520 struct mv643xx_private
*mp
= netdev_priv(dev
);
521 u32 eth_int_cause
, eth_int_cause_ext
= 0;
522 unsigned int port_num
= mp
->port_num
;
524 /* Read interrupt cause registers */
525 eth_int_cause
= mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
)) &
527 if (eth_int_cause
& ETH_INT_CAUSE_EXT
) {
528 eth_int_cause_ext
= mv_read(
529 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
530 ETH_INT_UNMASK_ALL_EXT
;
531 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
),
535 /* PHY status changed */
536 if (eth_int_cause_ext
& (ETH_INT_CAUSE_PHY
| ETH_INT_CAUSE_STATE
)) {
537 struct ethtool_cmd cmd
;
539 if (mii_link_ok(&mp
->mii
)) {
540 mii_ethtool_gset(&mp
->mii
, &cmd
);
541 mv643xx_eth_update_pscr(dev
, &cmd
);
542 mv643xx_eth_port_enable_tx(port_num
,
543 ETH_TX_QUEUES_ENABLED
);
544 if (!netif_carrier_ok(dev
)) {
545 netif_carrier_on(dev
);
546 if (mp
->tx_ring_size
- mp
->tx_desc_count
>=
548 netif_wake_queue(dev
);
550 } else if (netif_carrier_ok(dev
)) {
551 netif_stop_queue(dev
);
552 netif_carrier_off(dev
);
557 if (eth_int_cause
& ETH_INT_CAUSE_RX
) {
558 /* schedule the NAPI poll routine to maintain port */
559 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
561 /* wait for previous write to complete */
562 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
564 netif_rx_schedule(dev
, &mp
->napi
);
567 if (eth_int_cause
& ETH_INT_CAUSE_RX
)
568 mv643xx_eth_receive_queue(dev
, INT_MAX
);
570 if (eth_int_cause_ext
& ETH_INT_CAUSE_TX
)
571 mv643xx_eth_free_completed_tx_descs(dev
);
574 * If no real interrupt occured, exit.
575 * This can happen when using gigE interrupt coalescing mechanism.
577 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
586 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
589 * This routine sets the RX coalescing interrupt mechanism parameter.
590 * This parameter is a timeout counter, that counts in 64 t_clk
591 * chunks ; that when timeout event occurs a maskable interrupt
593 * The parameter is calculated using the tClk of the MV-643xx chip
594 * , and the required delay of the interrupt in usec.
597 * unsigned int eth_port_num Ethernet port number
598 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
599 * unsigned int delay Delay in usec
602 * Interrupt coalescing mechanism value is set in MV-643xx chip.
605 * The interrupt coalescing value set in the gigE port.
608 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num
,
609 unsigned int t_clk
, unsigned int delay
)
611 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
613 /* Set RX Coalescing mechanism */
614 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
),
615 ((coal
& 0x3fff) << 8) |
616 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
))
624 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
627 * This routine sets the TX coalescing interrupt mechanism parameter.
628 * This parameter is a timeout counter, that counts in 64 t_clk
629 * chunks ; that when timeout event occurs a maskable interrupt
631 * The parameter is calculated using the t_cLK frequency of the
632 * MV-643xx chip and the required delay in the interrupt in uSec
635 * unsigned int eth_port_num Ethernet port number
636 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
637 * unsigned int delay Delay in uSeconds
640 * Interrupt coalescing mechanism value is set in MV-643xx chip.
643 * The interrupt coalescing value set in the gigE port.
646 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num
,
647 unsigned int t_clk
, unsigned int delay
)
650 coal
= ((t_clk
/ 1000000) * delay
) / 64;
651 /* Set TX Coalescing mechanism */
652 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num
),
658 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
661 * This function prepares a Rx chained list of descriptors and packet
662 * buffers in a form of a ring. The routine must be called after port
663 * initialization routine and before port start routine.
664 * The Ethernet SDMA engine uses CPU bus addresses to access the various
665 * devices in the system (i.e. DRAM). This function uses the ethernet
666 * struct 'virtual to physical' routine (set by the user) to set the ring
667 * with physical addresses.
670 * struct mv643xx_private *mp Ethernet Port Control srtuct.
673 * The routine updates the Ethernet port control struct with information
674 * regarding the Rx descriptors and buffers.
679 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
681 volatile struct eth_rx_desc
*p_rx_desc
;
682 int rx_desc_num
= mp
->rx_ring_size
;
685 /* initialize the next_desc_ptr links in the Rx descriptors ring */
686 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
687 for (i
= 0; i
< rx_desc_num
; i
++) {
688 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
689 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
692 /* Save Rx desc pointer to driver struct. */
693 mp
->rx_curr_desc_q
= 0;
694 mp
->rx_used_desc_q
= 0;
696 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
700 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
703 * This function prepares a Tx chained list of descriptors and packet
704 * buffers in a form of a ring. The routine must be called after port
705 * initialization routine and before port start routine.
706 * The Ethernet SDMA engine uses CPU bus addresses to access the various
707 * devices in the system (i.e. DRAM). This function uses the ethernet
708 * struct 'virtual to physical' routine (set by the user) to set the ring
709 * with physical addresses.
712 * struct mv643xx_private *mp Ethernet Port Control srtuct.
715 * The routine updates the Ethernet port control struct with information
716 * regarding the Tx descriptors and buffers.
721 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
723 int tx_desc_num
= mp
->tx_ring_size
;
724 struct eth_tx_desc
*p_tx_desc
;
727 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
728 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
729 for (i
= 0; i
< tx_desc_num
; i
++) {
730 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
731 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
734 mp
->tx_curr_desc_q
= 0;
735 mp
->tx_used_desc_q
= 0;
737 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
740 static int mv643xx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
742 struct mv643xx_private
*mp
= netdev_priv(dev
);
745 spin_lock_irq(&mp
->lock
);
746 err
= mii_ethtool_sset(&mp
->mii
, cmd
);
747 spin_unlock_irq(&mp
->lock
);
752 static int mv643xx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
754 struct mv643xx_private
*mp
= netdev_priv(dev
);
757 spin_lock_irq(&mp
->lock
);
758 err
= mii_ethtool_gset(&mp
->mii
, cmd
);
759 spin_unlock_irq(&mp
->lock
);
761 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
762 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
763 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
771 * This function is called when openning the network device. The function
772 * should initialize all the hardware, initialize cyclic Rx/Tx
773 * descriptors chain and buffers and allocate an IRQ to the network
776 * Input : a pointer to the network device structure
778 * Output : zero of success , nonzero if fails.
781 static int mv643xx_eth_open(struct net_device
*dev
)
783 struct mv643xx_private
*mp
= netdev_priv(dev
);
784 unsigned int port_num
= mp
->port_num
;
788 /* Clear any pending ethernet port interrupts */
789 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
790 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
791 /* wait for previous write to complete */
792 mv_read (MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
));
794 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
795 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
797 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
804 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
805 mp
->timeout
.function
= mv643xx_eth_rx_refill_descs_timer_wrapper
;
806 mp
->timeout
.data
= (unsigned long)dev
;
808 /* Allocate RX and TX skb rings */
809 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
812 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
816 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
819 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
821 goto out_free_rx_skb
;
824 /* Allocate TX ring */
825 mp
->tx_desc_count
= 0;
826 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
827 mp
->tx_desc_area_size
= size
;
829 if (mp
->tx_sram_size
) {
830 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
832 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
834 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
838 if (!mp
->p_tx_desc_area
) {
839 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
842 goto out_free_tx_skb
;
844 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
845 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
847 ether_init_tx_desc_ring(mp
);
849 /* Allocate RX ring */
850 mp
->rx_desc_count
= 0;
851 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
852 mp
->rx_desc_area_size
= size
;
854 if (mp
->rx_sram_size
) {
855 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
857 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
859 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
863 if (!mp
->p_rx_desc_area
) {
864 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
866 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
868 if (mp
->rx_sram_size
)
869 iounmap(mp
->p_tx_desc_area
);
871 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
872 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
874 goto out_free_tx_skb
;
876 memset((void *)mp
->p_rx_desc_area
, 0, size
);
878 ether_init_rx_desc_ring(mp
);
880 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
883 napi_enable(&mp
->napi
);
888 /* Interrupt Coalescing */
892 eth_port_set_rx_coal(port_num
, 133000000, MV643XX_RX_COAL
);
896 eth_port_set_tx_coal(port_num
, 133000000, MV643XX_TX_COAL
);
898 /* Unmask phy and link status changes interrupts */
899 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
900 ETH_INT_UNMASK_ALL_EXT
);
902 /* Unmask RX buffer and TX end interrupt */
903 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
912 free_irq(dev
->irq
, dev
);
917 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
919 struct mv643xx_private
*mp
= netdev_priv(dev
);
922 mv643xx_eth_port_disable_tx(mp
->port_num
);
924 /* Free outstanding skb's on TX ring */
925 mv643xx_eth_free_all_tx_descs(dev
);
927 BUG_ON(mp
->tx_used_desc_q
!= mp
->tx_curr_desc_q
);
930 if (mp
->tx_sram_size
)
931 iounmap(mp
->p_tx_desc_area
);
933 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
934 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
937 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
939 struct mv643xx_private
*mp
= netdev_priv(dev
);
940 unsigned int port_num
= mp
->port_num
;
944 mv643xx_eth_port_disable_rx(port_num
);
946 /* Free preallocated skb's on RX rings */
947 for (curr
= 0; mp
->rx_desc_count
&& curr
< mp
->rx_ring_size
; curr
++) {
948 if (mp
->rx_skb
[curr
]) {
949 dev_kfree_skb(mp
->rx_skb
[curr
]);
954 if (mp
->rx_desc_count
)
956 "%s: Error in freeing Rx Ring. %d skb's still"
957 " stuck in RX Ring - ignoring them\n", dev
->name
,
960 if (mp
->rx_sram_size
)
961 iounmap(mp
->p_rx_desc_area
);
963 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
964 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
970 * This function is used when closing the network device.
971 * It updates the hardware,
972 * release all memory that holds buffers and descriptors and release the IRQ.
973 * Input : a pointer to the device structure
974 * Output : zero if success , nonzero if fails
977 static int mv643xx_eth_stop(struct net_device
*dev
)
979 struct mv643xx_private
*mp
= netdev_priv(dev
);
980 unsigned int port_num
= mp
->port_num
;
982 /* Mask all interrupts on ethernet port */
983 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
984 /* wait for previous write to complete */
985 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
988 napi_disable(&mp
->napi
);
990 netif_carrier_off(dev
);
991 netif_stop_queue(dev
);
993 eth_port_reset(mp
->port_num
);
995 mv643xx_eth_free_tx_rings(dev
);
996 mv643xx_eth_free_rx_rings(dev
);
998 free_irq(dev
->irq
, dev
);
1007 * This function is used in case of NAPI
1009 static int mv643xx_poll(struct napi_struct
*napi
, int budget
)
1011 struct mv643xx_private
*mp
= container_of(napi
, struct mv643xx_private
, napi
);
1012 struct net_device
*dev
= mp
->dev
;
1013 unsigned int port_num
= mp
->port_num
;
1016 #ifdef MV643XX_TX_FAST_REFILL
1017 if (++mp
->tx_clean_threshold
> 5) {
1018 mv643xx_eth_free_completed_tx_descs(dev
);
1019 mp
->tx_clean_threshold
= 0;
1024 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1025 != (u32
) mp
->rx_used_desc_q
)
1026 work_done
= mv643xx_eth_receive_queue(dev
, budget
);
1028 if (work_done
< budget
) {
1029 netif_rx_complete(dev
, napi
);
1030 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
1031 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1032 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1033 ETH_INT_UNMASK_ALL
);
1041 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1043 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1044 * This helper function detects that case.
1047 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
1052 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1053 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1054 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7)
1061 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1063 static int eth_alloc_tx_desc_index(struct mv643xx_private
*mp
)
1067 BUG_ON(mp
->tx_desc_count
>= mp
->tx_ring_size
);
1069 tx_desc_curr
= mp
->tx_curr_desc_q
;
1070 mp
->tx_curr_desc_q
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
1072 BUG_ON(mp
->tx_curr_desc_q
== mp
->tx_used_desc_q
);
1074 return tx_desc_curr
;
1078 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1080 * Ensure the data for each fragment to be transmitted is mapped properly,
1081 * then fill in descriptors in the tx hw queue.
1083 static void eth_tx_fill_frag_descs(struct mv643xx_private
*mp
,
1084 struct sk_buff
*skb
)
1088 struct eth_tx_desc
*desc
;
1090 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1091 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1093 tx_index
= eth_alloc_tx_desc_index(mp
);
1094 desc
= &mp
->p_tx_desc_area
[tx_index
];
1096 desc
->cmd_sts
= ETH_BUFFER_OWNED_BY_DMA
;
1097 /* Last Frag enables interrupt and frees the skb */
1098 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1099 desc
->cmd_sts
|= ETH_ZERO_PADDING
|
1101 ETH_TX_ENABLE_INTERRUPT
;
1102 mp
->tx_skb
[tx_index
] = skb
;
1104 mp
->tx_skb
[tx_index
] = NULL
;
1106 desc
= &mp
->p_tx_desc_area
[tx_index
];
1108 desc
->byte_cnt
= this_frag
->size
;
1109 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1110 this_frag
->page_offset
,
1117 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1119 * Ensure the data for an skb to be transmitted is mapped properly,
1120 * then fill in descriptors in the tx hw queue and start the hardware.
1122 static void eth_tx_submit_descs_for_skb(struct mv643xx_private
*mp
,
1123 struct sk_buff
*skb
)
1126 struct eth_tx_desc
*desc
;
1129 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
1131 cmd_sts
= ETH_TX_FIRST_DESC
| ETH_GEN_CRC
| ETH_BUFFER_OWNED_BY_DMA
;
1133 tx_index
= eth_alloc_tx_desc_index(mp
);
1134 desc
= &mp
->p_tx_desc_area
[tx_index
];
1137 eth_tx_fill_frag_descs(mp
, skb
);
1139 length
= skb_headlen(skb
);
1140 mp
->tx_skb
[tx_index
] = NULL
;
1142 cmd_sts
|= ETH_ZERO_PADDING
|
1144 ETH_TX_ENABLE_INTERRUPT
;
1146 mp
->tx_skb
[tx_index
] = skb
;
1149 desc
->byte_cnt
= length
;
1150 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
1152 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1153 BUG_ON(skb
->protocol
!= ETH_P_IP
);
1155 cmd_sts
|= ETH_GEN_TCP_UDP_CHECKSUM
|
1156 ETH_GEN_IP_V_4_CHECKSUM
|
1157 ip_hdr(skb
)->ihl
<< ETH_TX_IHL_SHIFT
;
1159 switch (ip_hdr(skb
)->protocol
) {
1161 cmd_sts
|= ETH_UDP_FRAME
;
1162 desc
->l4i_chk
= udp_hdr(skb
)->check
;
1165 desc
->l4i_chk
= tcp_hdr(skb
)->check
;
1171 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1172 cmd_sts
|= 5 << ETH_TX_IHL_SHIFT
;
1176 /* ensure all other descriptors are written before first cmd_sts */
1178 desc
->cmd_sts
= cmd_sts
;
1180 /* ensure all descriptors are written before poking hardware */
1182 mv643xx_eth_port_enable_tx(mp
->port_num
, ETH_TX_QUEUES_ENABLED
);
1184 mp
->tx_desc_count
+= nr_frags
+ 1;
1188 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1191 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1193 struct mv643xx_private
*mp
= netdev_priv(dev
);
1194 struct net_device_stats
*stats
= &dev
->stats
;
1195 unsigned long flags
;
1197 BUG_ON(netif_queue_stopped(dev
));
1198 BUG_ON(skb
== NULL
);
1200 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
) {
1201 printk(KERN_ERR
"%s: transmit with queue full\n", dev
->name
);
1202 netif_stop_queue(dev
);
1206 if (has_tiny_unaligned_frags(skb
)) {
1207 if (__skb_linearize(skb
)) {
1208 stats
->tx_dropped
++;
1209 printk(KERN_DEBUG
"%s: failed to linearize tiny "
1210 "unaligned fragment\n", dev
->name
);
1215 spin_lock_irqsave(&mp
->lock
, flags
);
1217 eth_tx_submit_descs_for_skb(mp
, skb
);
1218 stats
->tx_bytes
+= skb
->len
;
1219 stats
->tx_packets
++;
1220 dev
->trans_start
= jiffies
;
1222 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
)
1223 netif_stop_queue(dev
);
1225 spin_unlock_irqrestore(&mp
->lock
, flags
);
1227 return 0; /* success */
1230 #ifdef CONFIG_NET_POLL_CONTROLLER
1231 static void mv643xx_netpoll(struct net_device
*netdev
)
1233 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1234 int port_num
= mp
->port_num
;
1236 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1237 /* wait for previous write to complete */
1238 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
1240 mv643xx_eth_int_handler(netdev
->irq
, netdev
);
1242 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1246 static void mv643xx_init_ethtool_cmd(struct net_device
*dev
, int phy_address
,
1247 int speed
, int duplex
,
1248 struct ethtool_cmd
*cmd
)
1250 struct mv643xx_private
*mp
= netdev_priv(dev
);
1252 memset(cmd
, 0, sizeof(*cmd
));
1254 cmd
->port
= PORT_MII
;
1255 cmd
->transceiver
= XCVR_INTERNAL
;
1256 cmd
->phy_address
= phy_address
;
1259 cmd
->autoneg
= AUTONEG_ENABLE
;
1260 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1261 cmd
->speed
= SPEED_100
;
1262 cmd
->advertising
= ADVERTISED_10baseT_Half
|
1263 ADVERTISED_10baseT_Full
|
1264 ADVERTISED_100baseT_Half
|
1265 ADVERTISED_100baseT_Full
;
1266 if (mp
->mii
.supports_gmii
)
1267 cmd
->advertising
|= ADVERTISED_1000baseT_Full
;
1269 cmd
->autoneg
= AUTONEG_DISABLE
;
1271 cmd
->duplex
= duplex
;
1278 * First function called after registering the network device.
1279 * It's purpose is to initialize the device as an ethernet device,
1280 * fill the ethernet device structure with pointers * to functions,
1281 * and set the MAC address of the interface
1283 * Input : struct device *
1284 * Output : -ENOMEM if failed , 0 if success
1286 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1288 struct mv643xx_eth_platform_data
*pd
;
1290 struct mv643xx_private
*mp
;
1291 struct net_device
*dev
;
1293 struct resource
*res
;
1295 struct ethtool_cmd cmd
;
1296 int duplex
= DUPLEX_HALF
;
1297 int speed
= 0; /* default to auto-negotiation */
1299 pd
= pdev
->dev
.platform_data
;
1301 printk(KERN_ERR
"No mv643xx_eth_platform_data\n");
1305 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1309 platform_set_drvdata(pdev
, dev
);
1311 mp
= netdev_priv(dev
);
1314 netif_napi_add(dev
, &mp
->napi
, mv643xx_poll
, 64);
1317 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1319 dev
->irq
= res
->start
;
1321 dev
->open
= mv643xx_eth_open
;
1322 dev
->stop
= mv643xx_eth_stop
;
1323 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1324 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1325 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1327 /* No need to Tx Timeout */
1328 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1330 #ifdef CONFIG_NET_POLL_CONTROLLER
1331 dev
->poll_controller
= mv643xx_netpoll
;
1334 dev
->watchdog_timeo
= 2 * HZ
;
1336 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1337 dev
->do_ioctl
= mv643xx_eth_do_ioctl
;
1338 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1340 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1341 #ifdef MAX_SKB_FRAGS
1343 * Zero copy can only work if we use Discovery II memory. Else, we will
1344 * have to map the buffers to ISA memory which is only 16 MB
1346 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
1350 /* Configure the timeout task */
1351 INIT_WORK(&mp
->tx_timeout_task
, mv643xx_eth_tx_timeout_task
);
1353 spin_lock_init(&mp
->lock
);
1355 port_num
= mp
->port_num
= pd
->port_number
;
1357 /* set default config values */
1358 eth_port_uc_addr_get(port_num
, dev
->dev_addr
);
1359 mp
->rx_ring_size
= MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1360 mp
->tx_ring_size
= MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1362 if (is_valid_ether_addr(pd
->mac_addr
))
1363 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1365 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1366 ethernet_phy_set(port_num
, pd
->phy_addr
);
1368 if (pd
->rx_queue_size
)
1369 mp
->rx_ring_size
= pd
->rx_queue_size
;
1371 if (pd
->tx_queue_size
)
1372 mp
->tx_ring_size
= pd
->tx_queue_size
;
1374 if (pd
->tx_sram_size
) {
1375 mp
->tx_sram_size
= pd
->tx_sram_size
;
1376 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1379 if (pd
->rx_sram_size
) {
1380 mp
->rx_sram_size
= pd
->rx_sram_size
;
1381 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1384 duplex
= pd
->duplex
;
1387 /* Hook up MII support for ethtool */
1389 mp
->mii
.mdio_read
= mv643xx_mdio_read
;
1390 mp
->mii
.mdio_write
= mv643xx_mdio_write
;
1391 mp
->mii
.phy_id
= ethernet_phy_get(port_num
);
1392 mp
->mii
.phy_id_mask
= 0x3f;
1393 mp
->mii
.reg_num_mask
= 0x1f;
1395 err
= ethernet_phy_detect(port_num
);
1397 pr_debug("MV643xx ethernet port %d: "
1398 "No PHY detected at addr %d\n",
1399 port_num
, ethernet_phy_get(port_num
));
1403 ethernet_phy_reset(port_num
);
1404 mp
->mii
.supports_gmii
= mii_check_gmii_support(&mp
->mii
);
1405 mv643xx_init_ethtool_cmd(dev
, mp
->mii
.phy_id
, speed
, duplex
, &cmd
);
1406 mv643xx_eth_update_pscr(dev
, &cmd
);
1407 mv643xx_set_settings(dev
, &cmd
);
1409 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1410 err
= register_netdev(dev
);
1416 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1417 dev
->name
, port_num
, p
[0], p
[1], p
[2], p
[3], p
[4], p
[5]);
1419 if (dev
->features
& NETIF_F_SG
)
1420 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1422 if (dev
->features
& NETIF_F_IP_CSUM
)
1423 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1426 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1427 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1431 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1436 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1439 if (mp
->tx_sram_size
> 0)
1440 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1450 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1452 struct net_device
*dev
= platform_get_drvdata(pdev
);
1454 unregister_netdev(dev
);
1455 flush_scheduled_work();
1458 platform_set_drvdata(pdev
, NULL
);
1462 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1464 struct resource
*res
;
1466 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1468 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1472 mv643xx_eth_shared_base
= ioremap(res
->start
,
1473 MV643XX_ETH_SHARED_REGS_SIZE
);
1474 if (mv643xx_eth_shared_base
== NULL
)
1481 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
1483 iounmap(mv643xx_eth_shared_base
);
1484 mv643xx_eth_shared_base
= NULL
;
1489 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
1491 struct net_device
*dev
= platform_get_drvdata(pdev
);
1492 struct mv643xx_private
*mp
= netdev_priv(dev
);
1493 unsigned int port_num
= mp
->port_num
;
1495 /* Mask all interrupts on ethernet port */
1496 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), 0);
1497 mv_read (MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
1499 eth_port_reset(port_num
);
1502 static struct platform_driver mv643xx_eth_driver
= {
1503 .probe
= mv643xx_eth_probe
,
1504 .remove
= mv643xx_eth_remove
,
1505 .shutdown
= mv643xx_eth_shutdown
,
1507 .name
= MV643XX_ETH_NAME
,
1511 static struct platform_driver mv643xx_eth_shared_driver
= {
1512 .probe
= mv643xx_eth_shared_probe
,
1513 .remove
= mv643xx_eth_shared_remove
,
1515 .name
= MV643XX_ETH_SHARED_NAME
,
1520 * mv643xx_init_module
1522 * Registers the network drivers into the Linux kernel
1528 static int __init
mv643xx_init_module(void)
1532 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
1534 rc
= platform_driver_register(&mv643xx_eth_driver
);
1536 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1542 * mv643xx_cleanup_module
1544 * Registers the network drivers into the Linux kernel
1550 static void __exit
mv643xx_cleanup_module(void)
1552 platform_driver_unregister(&mv643xx_eth_driver
);
1553 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1556 module_init(mv643xx_init_module
);
1557 module_exit(mv643xx_cleanup_module
);
1559 MODULE_LICENSE("GPL");
1560 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1561 " and Dale Farnsworth");
1562 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1565 * The second part is the low level driver of the gigE ethernet ports.
1569 * Marvell's Gigabit Ethernet controller low level driver
1572 * This file introduce low level API to Marvell's Gigabit Ethernet
1573 * controller. This Gigabit Ethernet Controller driver API controls
1574 * 1) Operations (i.e. port init, start, reset etc').
1575 * 2) Data flow (i.e. port send, receive etc').
1576 * Each Gigabit Ethernet port is controlled via
1577 * struct mv643xx_private.
1578 * This struct includes user configuration information as well as
1579 * driver internal data needed for its operations.
1581 * Supported Features:
1582 * - This low level driver is OS independent. Allocating memory for
1583 * the descriptor rings and buffers are not within the scope of
1585 * - The user is free from Rx/Tx queue managing.
1586 * - This low level driver introduce functionality API that enable
1587 * the to operate Marvell's Gigabit Ethernet Controller in a
1589 * - Simple Gigabit Ethernet port operation API.
1590 * - Simple Gigabit Ethernet port data flow API.
1591 * - Data flow and operation API support per queue functionality.
1592 * - Support cached descriptors for better performance.
1593 * - Enable access to all four DRAM banks and internal SRAM memory
1595 * - PHY access and control API.
1596 * - Port control register configuration API.
1597 * - Full control over Unicast and Multicast MAC configurations.
1601 * Initialization phase
1602 * This phase complete the initialization of the the
1603 * mv643xx_private struct.
1604 * User information regarding port configuration has to be set
1605 * prior to calling the port initialization routine.
1607 * In this phase any port Tx/Rx activity is halted, MIB counters
1608 * are cleared, PHY address is set according to user parameter and
1609 * access to DRAM and internal SRAM memory spaces.
1611 * Driver ring initialization
1612 * Allocating memory for the descriptor rings and buffers is not
1613 * within the scope of this driver. Thus, the user is required to
1614 * allocate memory for the descriptors ring and buffers. Those
1615 * memory parameters are used by the Rx and Tx ring initialization
1616 * routines in order to curve the descriptor linked list in a form
1618 * Note: Pay special attention to alignment issues when using
1619 * cached descriptors/buffers. In this phase the driver store
1620 * information in the mv643xx_private struct regarding each queue
1624 * This phase prepares the Ethernet port for Rx and Tx activity.
1625 * It uses the information stored in the mv643xx_private struct to
1626 * initialize the various port registers.
1629 * All packet references to/from the driver are done using
1631 * This struct is a unified struct used with Rx and Tx operations.
1632 * This way the user is not required to be familiar with neither
1633 * Tx nor Rx descriptors structures.
1634 * The driver's descriptors rings are management by indexes.
1635 * Those indexes controls the ring resources and used to indicate
1636 * a SW resource error:
1638 * This index points to the current available resource for use. For
1639 * example in Rx process this index will point to the descriptor
1640 * that will be passed to the user upon calling the receive
1641 * routine. In Tx process, this index will point to the descriptor
1642 * that will be assigned with the user packet info and transmitted.
1644 * This index points to the descriptor that need to restore its
1645 * resources. For example in Rx process, using the Rx buffer return
1646 * API will attach the buffer returned in packet info to the
1647 * descriptor pointed by 'used'. In Tx process, using the Tx
1648 * descriptor return will merely return the user packet info with
1649 * the command status of the transmitted buffer pointed by the
1650 * 'used' index. Nevertheless, it is essential to use this routine
1651 * to update the 'used' index.
1653 * This index supports Tx Scatter-Gather. It points to the first
1654 * descriptor of a packet assembled of multiple buffers. For
1655 * example when in middle of Such packet we have a Tx resource
1656 * error the 'curr' index get the value of 'first' to indicate
1657 * that the ring returned to its state before trying to transmit
1660 * Receive operation:
1661 * The eth_port_receive API set the packet information struct,
1662 * passed by the caller, with received information from the
1663 * 'current' SDMA descriptor.
1664 * It is the user responsibility to return this resource back
1665 * to the Rx descriptor ring to enable the reuse of this source.
1666 * Return Rx resource is done using the eth_rx_return_buff API.
1668 * Prior to calling the initialization routine eth_port_init() the user
1669 * must set the following fields under mv643xx_private struct:
1670 * port_num User Ethernet port number.
1671 * port_config User port configuration value.
1672 * port_config_extend User port config extend value.
1673 * port_sdma_config User port SDMA config value.
1674 * port_serial_control User port serial control value.
1676 * This driver data flow is done using the struct pkt_info which
1677 * is a unified struct for Rx and Tx operations:
1679 * byte_cnt Tx/Rx descriptor buffer byte count.
1680 * l4i_chk CPU provided TCP Checksum. For Tx operation
1682 * cmd_sts Tx/Rx descriptor command status.
1683 * buf_ptr Tx/Rx descriptor buffer pointer.
1684 * return_info Tx/Rx user resource return information.
1688 static int ethernet_phy_get(unsigned int eth_port_num
);
1689 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
1691 /* Ethernet Port routines */
1692 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
);
1695 * eth_port_init - Initialize the Ethernet port driver
1698 * This function prepares the ethernet port to start its activity:
1699 * 1) Completes the ethernet port driver struct initialization toward port
1701 * 2) Resets the device to a quiescent state in case of warm reboot.
1702 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1703 * 4) Clean MAC tables. The reset status of those tables is unknown.
1704 * 5) Set PHY address.
1705 * Note: Call this routine prior to eth_port_start routine and after
1706 * setting user values in the user fields of Ethernet port control
1710 * struct mv643xx_private *mp Ethernet port control struct
1718 static void eth_port_init(struct mv643xx_private
*mp
)
1720 mp
->rx_resource_err
= 0;
1722 eth_port_reset(mp
->port_num
);
1724 eth_port_init_mac_tables(mp
->port_num
);
1728 * eth_port_start - Start the Ethernet port activity.
1731 * This routine prepares the Ethernet port for Rx and Tx activity:
1732 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1733 * has been initialized a descriptor's ring (using
1734 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1735 * 2. Initialize and enable the Ethernet configuration port by writing to
1736 * the port's configuration and command registers.
1737 * 3. Initialize and enable the SDMA by writing to the SDMA's
1738 * configuration and command registers. After completing these steps,
1739 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1741 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1742 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1743 * and ether_init_rx_desc_ring for Rx queues).
1746 * dev - a pointer to the required interface
1749 * Ethernet port is ready to receive and transmit.
1754 static void eth_port_start(struct net_device
*dev
)
1756 struct mv643xx_private
*mp
= netdev_priv(dev
);
1757 unsigned int port_num
= mp
->port_num
;
1758 int tx_curr_desc
, rx_curr_desc
;
1760 struct ethtool_cmd ethtool_cmd
;
1762 /* Assignment of Tx CTRP of given queue */
1763 tx_curr_desc
= mp
->tx_curr_desc_q
;
1764 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1765 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
1767 /* Assignment of Rx CRDP of given queue */
1768 rx_curr_desc
= mp
->rx_curr_desc_q
;
1769 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1770 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
1772 /* Add the assigned Ethernet address to the port's address table */
1773 eth_port_uc_addr_set(port_num
, dev
->dev_addr
);
1775 /* Assign port configuration and command. */
1776 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num
),
1777 MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE
);
1779 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num
),
1780 MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE
);
1782 pscr
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
1784 pscr
&= ~(MV643XX_ETH_SERIAL_PORT_ENABLE
| MV643XX_ETH_FORCE_LINK_PASS
);
1785 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
1787 pscr
|= MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL
|
1788 MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII
|
1789 MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX
|
1790 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL
|
1791 MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED
;
1793 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
1795 pscr
|= MV643XX_ETH_SERIAL_PORT_ENABLE
;
1796 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
1798 /* Assign port SDMA configuration */
1799 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num
),
1800 MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE
);
1802 /* Enable port Rx. */
1803 mv643xx_eth_port_enable_rx(port_num
, ETH_RX_QUEUES_ENABLED
);
1805 /* Disable port bandwidth limits by clearing MTU register */
1806 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
1808 /* save phy settings across reset */
1809 mv643xx_get_settings(dev
, ðtool_cmd
);
1810 ethernet_phy_reset(mp
->port_num
);
1811 mv643xx_set_settings(dev
, ðtool_cmd
);
1815 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
1817 static void eth_port_uc_addr_set(unsigned int port_num
, unsigned char *p_addr
)
1823 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
1824 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
1827 mv_write(MV643XX_ETH_MAC_ADDR_LOW(port_num
), mac_l
);
1828 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(port_num
), mac_h
);
1830 /* Accept frames with this address */
1831 table
= MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port_num
);
1832 eth_port_set_filter_table_entry(table
, p_addr
[5] & 0x0f);
1836 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
1838 static void eth_port_uc_addr_get(unsigned int port_num
, unsigned char *p_addr
)
1843 mac_h
= mv_read(MV643XX_ETH_MAC_ADDR_HIGH(port_num
));
1844 mac_l
= mv_read(MV643XX_ETH_MAC_ADDR_LOW(port_num
));
1846 p_addr
[0] = (mac_h
>> 24) & 0xff;
1847 p_addr
[1] = (mac_h
>> 16) & 0xff;
1848 p_addr
[2] = (mac_h
>> 8) & 0xff;
1849 p_addr
[3] = mac_h
& 0xff;
1850 p_addr
[4] = (mac_l
>> 8) & 0xff;
1851 p_addr
[5] = mac_l
& 0xff;
1855 * The entries in each table are indexed by a hash of a packet's MAC
1856 * address. One bit in each entry determines whether the packet is
1857 * accepted. There are 4 entries (each 8 bits wide) in each register
1858 * of the table. The bits in each entry are defined as follows:
1859 * 0 Accept=1, Drop=0
1860 * 3-1 Queue (ETH_Q0=0)
1863 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
)
1865 unsigned int table_reg
;
1866 unsigned int tbl_offset
;
1867 unsigned int reg_offset
;
1869 tbl_offset
= (entry
/ 4) * 4; /* Register offset of DA table entry */
1870 reg_offset
= entry
% 4; /* Entry offset within the register */
1872 /* Set "accepts frame bit" at specified table entry */
1873 table_reg
= mv_read(table
+ tbl_offset
);
1874 table_reg
|= 0x01 << (8 * reg_offset
);
1875 mv_write(table
+ tbl_offset
, table_reg
);
1879 * eth_port_mc_addr - Multicast address settings.
1881 * The MV device supports multicast using two tables:
1882 * 1) Special Multicast Table for MAC addresses of the form
1883 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
1884 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
1885 * Table entries in the DA-Filter table.
1886 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
1887 * is used as an index to the Other Multicast Table entries in the
1888 * DA-Filter table. This function calculates the CRC-8bit value.
1889 * In either case, eth_port_set_filter_table_entry() is then called
1890 * to set to set the actual table entry.
1892 static void eth_port_mc_addr(unsigned int eth_port_num
, unsigned char *p_addr
)
1896 unsigned char crc_result
= 0;
1902 if ((p_addr
[0] == 0x01) && (p_addr
[1] == 0x00) &&
1903 (p_addr
[2] == 0x5E) && (p_addr
[3] == 0x00) && (p_addr
[4] == 0x00)) {
1904 table
= MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
1906 eth_port_set_filter_table_entry(table
, p_addr
[5]);
1910 /* Calculate CRC-8 out of the given address */
1911 mac_h
= (p_addr
[0] << 8) | (p_addr
[1]);
1912 mac_l
= (p_addr
[2] << 24) | (p_addr
[3] << 16) |
1913 (p_addr
[4] << 8) | (p_addr
[5] << 0);
1915 for (i
= 0; i
< 32; i
++)
1916 mac_array
[i
] = (mac_l
>> i
) & 0x1;
1917 for (i
= 32; i
< 48; i
++)
1918 mac_array
[i
] = (mac_h
>> (i
- 32)) & 0x1;
1920 crc
[0] = mac_array
[45] ^ mac_array
[43] ^ mac_array
[40] ^ mac_array
[39] ^
1921 mac_array
[35] ^ mac_array
[34] ^ mac_array
[31] ^ mac_array
[30] ^
1922 mac_array
[28] ^ mac_array
[23] ^ mac_array
[21] ^ mac_array
[19] ^
1923 mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^ mac_array
[12] ^
1924 mac_array
[8] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[0];
1926 crc
[1] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
1927 mac_array
[41] ^ mac_array
[39] ^ mac_array
[36] ^ mac_array
[34] ^
1928 mac_array
[32] ^ mac_array
[30] ^ mac_array
[29] ^ mac_array
[28] ^
1929 mac_array
[24] ^ mac_array
[23] ^ mac_array
[22] ^ mac_array
[21] ^
1930 mac_array
[20] ^ mac_array
[18] ^ mac_array
[17] ^ mac_array
[16] ^
1931 mac_array
[15] ^ mac_array
[14] ^ mac_array
[13] ^ mac_array
[12] ^
1932 mac_array
[9] ^ mac_array
[6] ^ mac_array
[1] ^ mac_array
[0];
1934 crc
[2] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[44] ^ mac_array
[43] ^
1935 mac_array
[42] ^ mac_array
[39] ^ mac_array
[37] ^ mac_array
[34] ^
1936 mac_array
[33] ^ mac_array
[29] ^ mac_array
[28] ^ mac_array
[25] ^
1937 mac_array
[24] ^ mac_array
[22] ^ mac_array
[17] ^ mac_array
[15] ^
1938 mac_array
[13] ^ mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^
1939 mac_array
[6] ^ mac_array
[2] ^ mac_array
[1] ^ mac_array
[0];
1941 crc
[3] = mac_array
[47] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
1942 mac_array
[40] ^ mac_array
[38] ^ mac_array
[35] ^ mac_array
[34] ^
1943 mac_array
[30] ^ mac_array
[29] ^ mac_array
[26] ^ mac_array
[25] ^
1944 mac_array
[23] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^
1945 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[7] ^
1946 mac_array
[3] ^ mac_array
[2] ^ mac_array
[1];
1948 crc
[4] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[41] ^
1949 mac_array
[39] ^ mac_array
[36] ^ mac_array
[35] ^ mac_array
[31] ^
1950 mac_array
[30] ^ mac_array
[27] ^ mac_array
[26] ^ mac_array
[24] ^
1951 mac_array
[19] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[14] ^
1952 mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^ mac_array
[4] ^
1953 mac_array
[3] ^ mac_array
[2];
1955 crc
[5] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[45] ^ mac_array
[42] ^
1956 mac_array
[40] ^ mac_array
[37] ^ mac_array
[36] ^ mac_array
[32] ^
1957 mac_array
[31] ^ mac_array
[28] ^ mac_array
[27] ^ mac_array
[25] ^
1958 mac_array
[20] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[15] ^
1959 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[5] ^
1960 mac_array
[4] ^ mac_array
[3];
1962 crc
[6] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[43] ^ mac_array
[41] ^
1963 mac_array
[38] ^ mac_array
[37] ^ mac_array
[33] ^ mac_array
[32] ^
1964 mac_array
[29] ^ mac_array
[28] ^ mac_array
[26] ^ mac_array
[21] ^
1965 mac_array
[19] ^ mac_array
[17] ^ mac_array
[16] ^ mac_array
[14] ^
1966 mac_array
[12] ^ mac_array
[10] ^ mac_array
[6] ^ mac_array
[5] ^
1969 crc
[7] = mac_array
[47] ^ mac_array
[44] ^ mac_array
[42] ^ mac_array
[39] ^
1970 mac_array
[38] ^ mac_array
[34] ^ mac_array
[33] ^ mac_array
[30] ^
1971 mac_array
[29] ^ mac_array
[27] ^ mac_array
[22] ^ mac_array
[20] ^
1972 mac_array
[18] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[13] ^
1973 mac_array
[11] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[5];
1975 for (i
= 0; i
< 8; i
++)
1976 crc_result
= crc_result
| (crc
[i
] << i
);
1978 table
= MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
);
1979 eth_port_set_filter_table_entry(table
, crc_result
);
1983 * Set the entire multicast list based on dev->mc_list.
1985 static void eth_port_set_multicast_list(struct net_device
*dev
)
1988 struct dev_mc_list
*mc_list
;
1991 struct mv643xx_private
*mp
= netdev_priv(dev
);
1992 unsigned int eth_port_num
= mp
->port_num
;
1994 /* If the device is in promiscuous mode or in all multicast mode,
1995 * we will fully populate both multicast tables with accept.
1996 * This is guaranteed to yield a match on all multicast addresses...
1998 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
)) {
1999 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2000 /* Set all entries in DA filter special multicast
2002 * Set for ETH_Q0 for now
2004 * 0 Accept=1, Drop=0
2005 * 3-1 Queue ETH_Q0=0
2008 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2010 /* Set all entries in DA filter other multicast
2012 * Set for ETH_Q0 for now
2014 * 0 Accept=1, Drop=0
2015 * 3-1 Queue ETH_Q0=0
2018 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2023 /* We will clear out multicast tables every time we get the list.
2024 * Then add the entire new list...
2026 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2027 /* Clear DA filter special multicast table (Ex_dFSMT) */
2028 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2029 (eth_port_num
) + table_index
, 0);
2031 /* Clear DA filter other multicast table (Ex_dFOMT) */
2032 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2033 (eth_port_num
) + table_index
, 0);
2036 /* Get pointer to net_device multicast list and add each one... */
2037 for (i
= 0, mc_list
= dev
->mc_list
;
2038 (i
< 256) && (mc_list
!= NULL
) && (i
< dev
->mc_count
);
2039 i
++, mc_list
= mc_list
->next
)
2040 if (mc_list
->dmi_addrlen
== 6)
2041 eth_port_mc_addr(eth_port_num
, mc_list
->dmi_addr
);
2045 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2048 * Go through all the DA filter tables (Unicast, Special Multicast &
2049 * Other Multicast) and set each entry to 0.
2052 * unsigned int eth_port_num Ethernet Port number.
2055 * Multicast and Unicast packets are rejected.
2060 static void eth_port_init_mac_tables(unsigned int eth_port_num
)
2064 /* Clear DA filter unicast table (Ex_dFUT) */
2065 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2066 mv_write(MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2067 (eth_port_num
) + table_index
, 0);
2069 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2070 /* Clear DA filter special multicast table (Ex_dFSMT) */
2071 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2072 (eth_port_num
) + table_index
, 0);
2073 /* Clear DA filter other multicast table (Ex_dFOMT) */
2074 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2075 (eth_port_num
) + table_index
, 0);
2080 * eth_clear_mib_counters - Clear all MIB counters
2083 * This function clears all MIB counters of a specific ethernet port.
2084 * A read from the MIB counter will reset the counter.
2087 * unsigned int eth_port_num Ethernet Port number.
2090 * After reading all MIB counters, the counters resets.
2093 * MIB counter value.
2096 static void eth_clear_mib_counters(unsigned int eth_port_num
)
2100 /* Perform dummy reads from MIB counters */
2101 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2103 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num
) + i
);
2106 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2108 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2111 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2113 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2116 p
->good_octets_received
+=
2117 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2118 p
->good_octets_received
+=
2119 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2121 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2122 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2124 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2126 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2127 p
->good_octets_sent
+=
2128 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2130 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2131 offset
<= ETH_MIB_LATE_COLLISION
;
2133 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2137 * ethernet_phy_detect - Detect whether a phy is present
2140 * This function tests whether there is a PHY present on
2141 * the specified port.
2144 * unsigned int eth_port_num Ethernet Port number.
2151 * -ENODEV on failure
2154 static int ethernet_phy_detect(unsigned int port_num
)
2156 unsigned int phy_reg_data0
;
2159 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2160 auto_neg
= phy_reg_data0
& 0x1000;
2161 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2162 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2164 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2165 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2166 return -ENODEV
; /* change didn't take */
2168 phy_reg_data0
^= 0x1000;
2169 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2174 * ethernet_phy_get - Get the ethernet port PHY address.
2177 * This routine returns the given ethernet port PHY address.
2180 * unsigned int eth_port_num Ethernet Port number.
2189 static int ethernet_phy_get(unsigned int eth_port_num
)
2191 unsigned int reg_data
;
2193 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2195 return ((reg_data
>> (5 * eth_port_num
)) & 0x1f);
2199 * ethernet_phy_set - Set the ethernet port PHY address.
2202 * This routine sets the given ethernet port PHY address.
2205 * unsigned int eth_port_num Ethernet Port number.
2206 * int phy_addr PHY address.
2215 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
)
2218 int addr_shift
= 5 * eth_port_num
;
2220 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2221 reg_data
&= ~(0x1f << addr_shift
);
2222 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2223 mv_write(MV643XX_ETH_PHY_ADDR_REG
, reg_data
);
2227 * ethernet_phy_reset - Reset Ethernet port PHY.
2230 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2233 * unsigned int eth_port_num Ethernet Port number.
2242 static void ethernet_phy_reset(unsigned int eth_port_num
)
2244 unsigned int phy_reg_data
;
2247 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2248 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2249 eth_port_write_smi_reg(eth_port_num
, 0, phy_reg_data
);
2251 /* wait for PHY to come out of reset */
2254 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2255 } while (phy_reg_data
& 0x8000);
2258 static void mv643xx_eth_port_enable_tx(unsigned int port_num
,
2259 unsigned int queues
)
2261 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
), queues
);
2264 static void mv643xx_eth_port_enable_rx(unsigned int port_num
,
2265 unsigned int queues
)
2267 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), queues
);
2270 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num
)
2274 /* Stop Tx port activity. Check port Tx activity. */
2275 queues
= mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
))
2278 /* Issue stop command for active queues only */
2279 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
),
2282 /* Wait for all Tx activity to terminate. */
2283 /* Check port cause register that all Tx queues are stopped */
2284 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
))
2286 udelay(PHY_WAIT_MICRO_SECONDS
);
2288 /* Wait for Tx FIFO to empty */
2289 while (mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num
)) &
2290 ETH_PORT_TX_FIFO_EMPTY
)
2291 udelay(PHY_WAIT_MICRO_SECONDS
);
2297 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num
)
2301 /* Stop Rx port activity. Check port Rx activity. */
2302 queues
= mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
))
2305 /* Issue stop command for active queues only */
2306 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
2309 /* Wait for all Rx activity to terminate. */
2310 /* Check port cause register that all Rx queues are stopped */
2311 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
))
2313 udelay(PHY_WAIT_MICRO_SECONDS
);
2320 * eth_port_reset - Reset Ethernet port
2323 * This routine resets the chip by aborting any SDMA engine activity and
2324 * clearing the MIB counters. The Receiver and the Transmit unit are in
2325 * idle state after this command is performed and the port is disabled.
2328 * unsigned int eth_port_num Ethernet Port number.
2331 * Channel activity is halted.
2337 static void eth_port_reset(unsigned int port_num
)
2339 unsigned int reg_data
;
2341 mv643xx_eth_port_disable_tx(port_num
);
2342 mv643xx_eth_port_disable_rx(port_num
);
2344 /* Clear all MIB counters */
2345 eth_clear_mib_counters(port_num
);
2347 /* Reset the Enable bit in the Configuration Register */
2348 reg_data
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
2349 reg_data
&= ~(MV643XX_ETH_SERIAL_PORT_ENABLE
|
2350 MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL
|
2351 MV643XX_ETH_FORCE_LINK_PASS
);
2352 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2357 * eth_port_read_smi_reg - Read PHY registers
2360 * This routine utilize the SMI interface to interact with the PHY in
2361 * order to perform PHY register read.
2364 * unsigned int port_num Ethernet Port number.
2365 * unsigned int phy_reg PHY register address offset.
2366 * unsigned int *value Register value buffer.
2369 * Write the value of a specified PHY register into given buffer.
2372 * false if the PHY is busy or read data is not in valid state.
2376 static void eth_port_read_smi_reg(unsigned int port_num
,
2377 unsigned int phy_reg
, unsigned int *value
)
2379 int phy_addr
= ethernet_phy_get(port_num
);
2380 unsigned long flags
;
2383 /* the SMI register is a shared resource */
2384 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2386 /* wait for the SMI register to become available */
2387 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2388 if (i
== PHY_WAIT_ITERATIONS
) {
2389 printk("mv643xx PHY busy timeout, port %d\n", port_num
);
2392 udelay(PHY_WAIT_MICRO_SECONDS
);
2395 mv_write(MV643XX_ETH_SMI_REG
,
2396 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2398 /* now wait for the data to be valid */
2399 for (i
= 0; !(mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2400 if (i
== PHY_WAIT_ITERATIONS
) {
2401 printk("mv643xx PHY read timeout, port %d\n", port_num
);
2404 udelay(PHY_WAIT_MICRO_SECONDS
);
2407 *value
= mv_read(MV643XX_ETH_SMI_REG
) & 0xffff;
2409 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2413 * eth_port_write_smi_reg - Write to PHY registers
2416 * This routine utilize the SMI interface to interact with the PHY in
2417 * order to perform writes to PHY registers.
2420 * unsigned int eth_port_num Ethernet Port number.
2421 * unsigned int phy_reg PHY register address offset.
2422 * unsigned int value Register value.
2425 * Write the given value to the specified PHY register.
2428 * false if the PHY is busy.
2432 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
2433 unsigned int phy_reg
, unsigned int value
)
2437 unsigned long flags
;
2439 phy_addr
= ethernet_phy_get(eth_port_num
);
2441 /* the SMI register is a shared resource */
2442 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2444 /* wait for the SMI register to become available */
2445 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2446 if (i
== PHY_WAIT_ITERATIONS
) {
2447 printk("mv643xx PHY busy timeout, port %d\n",
2451 udelay(PHY_WAIT_MICRO_SECONDS
);
2454 mv_write(MV643XX_ETH_SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2455 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2457 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2461 * Wrappers for MII support library.
2463 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
2466 struct mv643xx_private
*mp
= netdev_priv(dev
);
2468 eth_port_read_smi_reg(mp
->port_num
, location
, &val
);
2472 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
)
2474 struct mv643xx_private
*mp
= netdev_priv(dev
);
2475 eth_port_write_smi_reg(mp
->port_num
, location
, val
);
2479 * eth_port_receive - Get received information from Rx ring.
2482 * This routine returns the received data to the caller. There is no
2483 * data copying during routine operation. All information is returned
2484 * using pointer to packet information struct passed from the caller.
2485 * If the routine exhausts Rx ring resources then the resource error flag
2489 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2490 * struct pkt_info *p_pkt_info User packet buffer.
2493 * Rx ring current and used indexes are updated.
2496 * ETH_ERROR in case the routine can not access Rx desc ring.
2497 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2498 * ETH_END_OF_JOB if there is no received data.
2501 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
2502 struct pkt_info
*p_pkt_info
)
2504 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
2505 volatile struct eth_rx_desc
*p_rx_desc
;
2506 unsigned int command_status
;
2507 unsigned long flags
;
2509 /* Do not process Rx ring in case of Rx ring resource error */
2510 if (mp
->rx_resource_err
)
2511 return ETH_QUEUE_FULL
;
2513 spin_lock_irqsave(&mp
->lock
, flags
);
2515 /* Get the Rx Desc ring 'curr and 'used' indexes */
2516 rx_curr_desc
= mp
->rx_curr_desc_q
;
2517 rx_used_desc
= mp
->rx_used_desc_q
;
2519 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
2521 /* The following parameters are used to save readings from memory */
2522 command_status
= p_rx_desc
->cmd_sts
;
2525 /* Nothing to receive... */
2526 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
2527 spin_unlock_irqrestore(&mp
->lock
, flags
);
2528 return ETH_END_OF_JOB
;
2531 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
2532 p_pkt_info
->cmd_sts
= command_status
;
2533 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
2534 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
2535 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
2538 * Clean the return info field to indicate that the
2539 * packet has been moved to the upper layers
2541 mp
->rx_skb
[rx_curr_desc
] = NULL
;
2543 /* Update current index in data structure */
2544 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
2545 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
2547 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2548 if (rx_next_curr_desc
== rx_used_desc
)
2549 mp
->rx_resource_err
= 1;
2551 spin_unlock_irqrestore(&mp
->lock
, flags
);
2557 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2560 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2561 * next 'used' descriptor and attached the returned buffer to it.
2562 * In case the Rx ring was in "resource error" condition, where there are
2563 * no available Rx resources, the function resets the resource error flag.
2566 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2567 * struct pkt_info *p_pkt_info Information on returned buffer.
2570 * New available Rx resource in Rx descriptor ring.
2573 * ETH_ERROR in case the routine can not access Rx desc ring.
2576 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
2577 struct pkt_info
*p_pkt_info
)
2579 int used_rx_desc
; /* Where to return Rx resource */
2580 volatile struct eth_rx_desc
*p_used_rx_desc
;
2581 unsigned long flags
;
2583 spin_lock_irqsave(&mp
->lock
, flags
);
2585 /* Get 'used' Rx descriptor */
2586 used_rx_desc
= mp
->rx_used_desc_q
;
2587 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
2589 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
2590 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
2591 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
2593 /* Flush the write pipe */
2595 /* Return the descriptor to DMA ownership */
2597 p_used_rx_desc
->cmd_sts
=
2598 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
2601 /* Move the used descriptor pointer to the next descriptor */
2602 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
2604 /* Any Rx return cancels the Rx resource error status */
2605 mp
->rx_resource_err
= 0;
2607 spin_unlock_irqrestore(&mp
->lock
, flags
);
2612 /************* Begin ethtool support *************************/
2614 struct mv643xx_stats
{
2615 char stat_string
[ETH_GSTRING_LEN
];
2620 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2621 offsetof(struct mv643xx_private, m)
2623 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
2624 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
2625 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
2626 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
2627 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
2628 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
2629 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
2630 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
2631 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
2632 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
2633 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
2634 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
2635 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
2636 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
2637 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
2638 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
2639 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
2640 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
2641 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
2642 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
2643 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
2644 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
2645 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
2646 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
2647 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
2648 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
2649 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
2650 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
2651 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
2652 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
2653 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
2654 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
2655 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
2656 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
2657 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
2658 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
2659 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
2660 { "collision", MV643XX_STAT(mib_counters
.collision
) },
2661 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
2664 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
2666 static void mv643xx_get_drvinfo(struct net_device
*netdev
,
2667 struct ethtool_drvinfo
*drvinfo
)
2669 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
2670 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
2671 strncpy(drvinfo
->fw_version
, "N/A", 32);
2672 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
2673 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
2676 static int mv643xx_get_stats_count(struct net_device
*netdev
)
2678 return MV643XX_STATS_LEN
;
2681 static void mv643xx_get_ethtool_stats(struct net_device
*netdev
,
2682 struct ethtool_stats
*stats
, uint64_t *data
)
2684 struct mv643xx_private
*mp
= netdev
->priv
;
2687 eth_update_mib_counters(mp
);
2689 for (i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
2690 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
2691 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
2692 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
2696 static void mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
,
2703 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
2704 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2705 mv643xx_gstrings_stats
[i
].stat_string
,
2712 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
2714 struct mv643xx_private
*mp
= netdev_priv(dev
);
2716 return mii_link_ok(&mp
->mii
);
2719 static int mv643xx_eth_nway_restart(struct net_device
*dev
)
2721 struct mv643xx_private
*mp
= netdev_priv(dev
);
2723 return mii_nway_restart(&mp
->mii
);
2726 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
2728 struct mv643xx_private
*mp
= netdev_priv(dev
);
2730 return generic_mii_ioctl(&mp
->mii
, if_mii(ifr
), cmd
, NULL
);
2733 static const struct ethtool_ops mv643xx_ethtool_ops
= {
2734 .get_settings
= mv643xx_get_settings
,
2735 .set_settings
= mv643xx_set_settings
,
2736 .get_drvinfo
= mv643xx_get_drvinfo
,
2737 .get_link
= mv643xx_eth_get_link
,
2738 .get_sg
= ethtool_op_get_sg
,
2739 .set_sg
= ethtool_op_set_sg
,
2740 .get_stats_count
= mv643xx_get_stats_count
,
2741 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
2742 .get_strings
= mv643xx_get_strings
,
2743 .nway_reset
= mv643xx_eth_nway_restart
,
2746 /************* End ethtool support *************************/