2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define WRAP NET_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
61 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
63 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
64 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
65 #define INT_CAUSE_MASK_ALL 0x00000000
66 #define INT_CAUSE_MASK_ALL_EXT 0x00000000
67 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
68 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
70 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
77 #define PHY_WAIT_MICRO_SECONDS 10
79 /* Static function declarations */
80 static int eth_port_link_is_up(unsigned int eth_port_num
);
81 static void eth_port_uc_addr_get(struct net_device
*dev
,
82 unsigned char *MacAddr
);
83 static int mv643xx_eth_real_open(struct net_device
*);
84 static int mv643xx_eth_real_stop(struct net_device
*);
85 static int mv643xx_eth_change_mtu(struct net_device
*, int);
86 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*);
87 static void eth_port_init_mac_tables(unsigned int eth_port_num
);
89 static int mv643xx_poll(struct net_device
*dev
, int *budget
);
91 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
92 static int ethernet_phy_detect(unsigned int eth_port_num
);
93 static struct ethtool_ops mv643xx_ethtool_ops
;
95 static char mv643xx_driver_name
[] = "mv643xx_eth";
96 static char mv643xx_driver_version
[] = "1.0";
98 static void __iomem
*mv643xx_eth_shared_base
;
100 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
101 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
103 static inline u32
mv_read(int offset
)
105 void __iomem
*reg_base
;
107 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
109 return readl(reg_base
+ offset
);
112 static inline void mv_write(int offset
, u32 data
)
114 void __iomem
*reg_base
;
116 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
117 writel(data
, reg_base
+ offset
);
121 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
123 * Input : pointer to ethernet interface network device structure
125 * Output : 0 upon success, -EINVAL upon failure
127 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
129 struct mv643xx_private
*mp
= netdev_priv(dev
);
132 spin_lock_irqsave(&mp
->lock
, flags
);
134 if ((new_mtu
> 9500) || (new_mtu
< 64)) {
135 spin_unlock_irqrestore(&mp
->lock
, flags
);
141 * Stop then re-open the interface. This will allocate RX skb's with
143 * There is a possible danger that the open will not successed, due
144 * to memory is full, which might fail the open function.
146 if (netif_running(dev
)) {
147 if (mv643xx_eth_real_stop(dev
))
149 "%s: Fatal error on stopping device\n",
151 if (mv643xx_eth_real_open(dev
))
153 "%s: Fatal error on opening device\n",
157 spin_unlock_irqrestore(&mp
->lock
, flags
);
162 * mv643xx_eth_rx_task
164 * Fills / refills RX queue on a certain gigabit ethernet port
166 * Input : pointer to ethernet interface network device structure
169 static void mv643xx_eth_rx_task(void *data
)
171 struct net_device
*dev
= (struct net_device
*)data
;
172 struct mv643xx_private
*mp
= netdev_priv(dev
);
173 struct pkt_info pkt_info
;
176 if (test_and_set_bit(0, &mp
->rx_task_busy
))
177 panic("%s: Error in test_set_bit / clear_bit", dev
->name
);
179 while (mp
->rx_ring_skbs
< (mp
->rx_ring_size
- 5)) {
180 skb
= dev_alloc_skb(RX_SKB_SIZE
);
184 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
185 pkt_info
.byte_cnt
= RX_SKB_SIZE
;
186 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, RX_SKB_SIZE
,
188 pkt_info
.return_info
= skb
;
189 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
191 "%s: Error allocating RX Ring\n", dev
->name
);
196 clear_bit(0, &mp
->rx_task_busy
);
198 * If RX ring is empty of SKB, set a timer to try allocating
199 * again in a later time .
201 if ((mp
->rx_ring_skbs
== 0) && (mp
->rx_timer_flag
== 0)) {
202 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
204 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10);
205 add_timer(&mp
->timeout
);
206 mp
->rx_timer_flag
= 1;
208 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
210 /* Return interrupts */
211 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp
->port_num
),
212 INT_CAUSE_UNMASK_ALL
);
218 * mv643xx_eth_rx_task_timer_wrapper
220 * Timer routine to wake up RX queue filling task. This function is
221 * used only in case the RX queue is empty, and all alloc_skb has
222 * failed (due to out of memory event).
224 * Input : pointer to ethernet interface network device structure
227 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data
)
229 struct net_device
*dev
= (struct net_device
*)data
;
230 struct mv643xx_private
*mp
= netdev_priv(dev
);
232 mp
->rx_timer_flag
= 0;
233 mv643xx_eth_rx_task((void *)data
);
237 * mv643xx_eth_update_mac_address
239 * Update the MAC address of the port in the address table
241 * Input : pointer to ethernet interface network device structure
244 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
246 struct mv643xx_private
*mp
= netdev_priv(dev
);
247 unsigned int port_num
= mp
->port_num
;
249 eth_port_init_mac_tables(port_num
);
250 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
251 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
255 * mv643xx_eth_set_rx_mode
257 * Change from promiscuos to regular rx mode
259 * Input : pointer to ethernet interface network device structure
262 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
264 struct mv643xx_private
*mp
= netdev_priv(dev
);
266 if (dev
->flags
& IFF_PROMISC
)
267 mp
->port_config
|= (u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
269 mp
->port_config
&= ~(u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
271 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp
->port_num
), mp
->port_config
);
275 * mv643xx_eth_set_mac_address
277 * Change the interface's mac address.
278 * No special hardware thing should be done because interface is always
279 * put in promiscuous mode.
281 * Input : pointer to ethernet interface network device structure and
282 * a pointer to the designated entry to be added to the cache.
283 * Output : zero upon success, negative upon failure
285 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
289 for (i
= 0; i
< 6; i
++)
290 /* +2 is for the offset of the HW addr type */
291 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
292 mv643xx_eth_update_mac_address(dev
);
297 * mv643xx_eth_tx_timeout
299 * Called upon a timeout on transmitting a packet
301 * Input : pointer to ethernet interface network device structure.
304 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
306 struct mv643xx_private
*mp
= netdev_priv(dev
);
308 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
310 /* Do the reset outside of interrupt context */
311 schedule_work(&mp
->tx_timeout_task
);
315 * mv643xx_eth_tx_timeout_task
317 * Actual routine to reset the adapter when a timeout on Tx has occurred
319 static void mv643xx_eth_tx_timeout_task(struct net_device
*dev
)
321 struct mv643xx_private
*mp
= netdev_priv(dev
);
323 netif_device_detach(dev
);
324 eth_port_reset(mp
->port_num
);
326 netif_device_attach(dev
);
330 * mv643xx_eth_free_tx_queue
332 * Input : dev - a pointer to the required interface
334 * Output : 0 if was able to release skb , nonzero otherwise
336 static int mv643xx_eth_free_tx_queue(struct net_device
*dev
,
337 unsigned int eth_int_cause_ext
)
339 struct mv643xx_private
*mp
= netdev_priv(dev
);
340 struct net_device_stats
*stats
= &mp
->stats
;
341 struct pkt_info pkt_info
;
344 if (!(eth_int_cause_ext
& (BIT0
| BIT8
)))
347 spin_lock(&mp
->lock
);
349 /* Check only queue 0 */
350 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
351 if (pkt_info
.cmd_sts
& BIT0
) {
352 printk("%s: Error in TX\n", dev
->name
);
356 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
357 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
361 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
365 if (pkt_info
.return_info
) {
366 dev_kfree_skb_irq(pkt_info
.return_info
);
371 spin_unlock(&mp
->lock
);
377 * mv643xx_eth_receive
379 * This function is forward packets that are received from the port's
380 * queues toward kernel core or FastRoute them to another interface.
382 * Input : dev - a pointer to the required interface
383 * max - maximum number to receive (0 means unlimted)
385 * Output : number of served packets
388 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
390 static int mv643xx_eth_receive_queue(struct net_device
*dev
)
393 struct mv643xx_private
*mp
= netdev_priv(dev
);
394 struct net_device_stats
*stats
= &mp
->stats
;
395 unsigned int received_packets
= 0;
397 struct pkt_info pkt_info
;
400 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
402 while (eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
407 /* Update statistics. Note byte count includes 4 byte CRC count */
409 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
410 skb
= pkt_info
.return_info
;
412 * In case received a packet without first / last bits on OR
413 * the error summary bit is on, the packets needs to be dropeed.
415 if (((pkt_info
.cmd_sts
416 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
417 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
418 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
420 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
421 ETH_RX_LAST_DESC
)) !=
422 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
425 "%s: Received packet spread "
426 "on multiple descriptors\n",
429 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
432 dev_kfree_skb_irq(skb
);
435 * The -4 is for the CRC in the trailer of the
438 skb_put(skb
, pkt_info
.byte_cnt
- 4);
441 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
442 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
444 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
446 skb
->protocol
= eth_type_trans(skb
, dev
);
448 netif_receive_skb(skb
);
455 return received_packets
;
459 * mv643xx_eth_int_handler
461 * Main interrupt handler for the gigbit ethernet ports
463 * Input : irq - irq number (not used)
464 * dev_id - a pointer to the required interface's data structure
469 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
,
470 struct pt_regs
*regs
)
472 struct net_device
*dev
= (struct net_device
*)dev_id
;
473 struct mv643xx_private
*mp
= netdev_priv(dev
);
474 u32 eth_int_cause
, eth_int_cause_ext
= 0;
475 unsigned int port_num
= mp
->port_num
;
477 /* Read interrupt cause registers */
478 eth_int_cause
= mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
)) &
479 INT_CAUSE_UNMASK_ALL
;
481 if (eth_int_cause
& BIT1
)
482 eth_int_cause_ext
= mv_read(
483 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
484 INT_CAUSE_UNMASK_ALL_EXT
;
487 if (!(eth_int_cause
& 0x0007fffd)) {
488 /* Dont ack the Rx interrupt */
491 * Clear specific ethernet port intrerrupt registers by
492 * acknowleding relevant bits.
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
),
496 if (eth_int_cause_ext
!= 0x0)
497 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
498 (port_num
), ~eth_int_cause_ext
);
500 /* UDP change : We may need this */
501 if ((eth_int_cause_ext
& 0x0000ffff) &&
502 (mv643xx_eth_free_tx_queue(dev
, eth_int_cause_ext
) == 0) &&
503 (mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
504 netif_wake_queue(dev
);
507 if (netif_rx_schedule_prep(dev
)) {
508 /* Mask all the interrupts */
509 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), 0);
510 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
512 __netif_rx_schedule(dev
);
515 if (eth_int_cause
& (BIT2
| BIT11
))
516 mv643xx_eth_receive_queue(dev
, 0);
519 * After forwarded received packets to upper layer, add a task
520 * in an interrupts enabled context that refills the RX ring
523 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
524 /* Unmask all interrupts on ethernet port */
525 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
527 queue_task(&mp
->rx_task
, &tq_immediate
);
528 mark_bh(IMMEDIATE_BH
);
530 mp
->rx_task
.func(dev
);
534 /* PHY status changed */
535 if (eth_int_cause_ext
& (BIT16
| BIT20
)) {
536 if (eth_port_link_is_up(port_num
)) {
537 netif_carrier_on(dev
);
538 netif_wake_queue(dev
);
540 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
543 netif_carrier_off(dev
);
544 netif_stop_queue(dev
);
549 * If no real interrupt occured, exit.
550 * This can happen when using gigE interrupt coalescing mechanism.
552 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
561 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
564 * This routine sets the RX coalescing interrupt mechanism parameter.
565 * This parameter is a timeout counter, that counts in 64 t_clk
566 * chunks ; that when timeout event occurs a maskable interrupt
568 * The parameter is calculated using the tClk of the MV-643xx chip
569 * , and the required delay of the interrupt in usec.
572 * unsigned int eth_port_num Ethernet port number
573 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
574 * unsigned int delay Delay in usec
577 * Interrupt coalescing mechanism value is set in MV-643xx chip.
580 * The interrupt coalescing value set in the gigE port.
583 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num
,
584 unsigned int t_clk
, unsigned int delay
)
586 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
588 /* Set RX Coalescing mechanism */
589 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
),
590 ((coal
& 0x3fff) << 8) |
591 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
))
599 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
602 * This routine sets the TX coalescing interrupt mechanism parameter.
603 * This parameter is a timeout counter, that counts in 64 t_clk
604 * chunks ; that when timeout event occurs a maskable interrupt
606 * The parameter is calculated using the t_cLK frequency of the
607 * MV-643xx chip and the required delay in the interrupt in uSec
610 * unsigned int eth_port_num Ethernet port number
611 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
612 * unsigned int delay Delay in uSeconds
615 * Interrupt coalescing mechanism value is set in MV-643xx chip.
618 * The interrupt coalescing value set in the gigE port.
621 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num
,
622 unsigned int t_clk
, unsigned int delay
)
625 coal
= ((t_clk
/ 1000000) * delay
) / 64;
626 /* Set TX Coalescing mechanism */
627 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num
),
635 * This function is called when openning the network device. The function
636 * should initialize all the hardware, initialize cyclic Rx/Tx
637 * descriptors chain and buffers and allocate an IRQ to the network
640 * Input : a pointer to the network device structure
642 * Output : zero of success , nonzero if fails.
645 static int mv643xx_eth_open(struct net_device
*dev
)
647 struct mv643xx_private
*mp
= netdev_priv(dev
);
648 unsigned int port_num
= mp
->port_num
;
651 spin_lock_irq(&mp
->lock
);
653 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
654 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
657 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
663 if (mv643xx_eth_real_open(dev
)) {
664 printk("%s: Error opening interface\n", dev
->name
);
669 spin_unlock_irq(&mp
->lock
);
674 free_irq(dev
->irq
, dev
);
677 spin_unlock_irq(&mp
->lock
);
683 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
686 * This function prepares a Rx chained list of descriptors and packet
687 * buffers in a form of a ring. The routine must be called after port
688 * initialization routine and before port start routine.
689 * The Ethernet SDMA engine uses CPU bus addresses to access the various
690 * devices in the system (i.e. DRAM). This function uses the ethernet
691 * struct 'virtual to physical' routine (set by the user) to set the ring
692 * with physical addresses.
695 * struct mv643xx_private *mp Ethernet Port Control srtuct.
698 * The routine updates the Ethernet port control struct with information
699 * regarding the Rx descriptors and buffers.
704 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
706 volatile struct eth_rx_desc
*p_rx_desc
;
707 int rx_desc_num
= mp
->rx_ring_size
;
710 /* initialize the next_desc_ptr links in the Rx descriptors ring */
711 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
712 for (i
= 0; i
< rx_desc_num
; i
++) {
713 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
714 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
717 /* Save Rx desc pointer to driver struct. */
718 mp
->rx_curr_desc_q
= 0;
719 mp
->rx_used_desc_q
= 0;
721 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
723 /* Add the queue to the list of RX queues of this port */
724 mp
->port_rx_queue_command
|= 1;
728 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
731 * This function prepares a Tx chained list of descriptors and packet
732 * buffers in a form of a ring. The routine must be called after port
733 * initialization routine and before port start routine.
734 * The Ethernet SDMA engine uses CPU bus addresses to access the various
735 * devices in the system (i.e. DRAM). This function uses the ethernet
736 * struct 'virtual to physical' routine (set by the user) to set the ring
737 * with physical addresses.
740 * struct mv643xx_private *mp Ethernet Port Control srtuct.
743 * The routine updates the Ethernet port control struct with information
744 * regarding the Tx descriptors and buffers.
749 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
751 int tx_desc_num
= mp
->tx_ring_size
;
752 struct eth_tx_desc
*p_tx_desc
;
755 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
756 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
757 for (i
= 0; i
< tx_desc_num
; i
++) {
758 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
759 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
762 mp
->tx_curr_desc_q
= 0;
763 mp
->tx_used_desc_q
= 0;
764 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
765 mp
->tx_first_desc_q
= 0;
768 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
770 /* Add the queue to the list of Tx queues of this port */
771 mp
->port_tx_queue_command
|= 1;
774 /* Helper function for mv643xx_eth_open */
775 static int mv643xx_eth_real_open(struct net_device
*dev
)
777 struct mv643xx_private
*mp
= netdev_priv(dev
);
778 unsigned int port_num
= mp
->port_num
;
782 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
784 /* Clear the ethernet port interrupts */
785 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
786 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
788 /* Unmask RX buffer and TX end interrupt */
789 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
790 INT_CAUSE_UNMASK_ALL
);
792 /* Unmask phy and link status changes interrupts */
793 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
794 INT_CAUSE_UNMASK_ALL_EXT
);
796 /* Set the MAC Address */
797 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
801 INIT_WORK(&mp
->rx_task
, (void (*)(void *))mv643xx_eth_rx_task
, dev
);
803 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
804 mp
->timeout
.function
= mv643xx_eth_rx_task_timer_wrapper
;
805 mp
->timeout
.data
= (unsigned long)dev
;
807 mp
->rx_task_busy
= 0;
808 mp
->rx_timer_flag
= 0;
810 /* Allocate RX and TX skb rings */
811 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
814 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
817 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
820 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
825 /* Allocate TX ring */
826 mp
->tx_ring_skbs
= 0;
827 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
828 mp
->tx_desc_area_size
= size
;
830 if (mp
->tx_sram_size
) {
831 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
833 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
835 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
839 if (!mp
->p_tx_desc_area
) {
840 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
846 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
847 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
849 ether_init_tx_desc_ring(mp
);
851 /* Allocate RX ring */
852 mp
->rx_ring_skbs
= 0;
853 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
854 mp
->rx_desc_area_size
= size
;
856 if (mp
->rx_sram_size
) {
857 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
859 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
861 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
865 if (!mp
->p_rx_desc_area
) {
866 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
868 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
870 if (mp
->rx_sram_size
)
871 iounmap(mp
->p_rx_desc_area
);
873 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
874 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
879 memset((void *)mp
->p_rx_desc_area
, 0, size
);
881 ether_init_rx_desc_ring(mp
);
883 mv643xx_eth_rx_task(dev
); /* Fill RX ring with skb's */
887 /* Interrupt Coalescing */
891 eth_port_set_rx_coal(port_num
, 133000000, MV643XX_RX_COAL
);
895 eth_port_set_tx_coal(port_num
, 133000000, MV643XX_TX_COAL
);
897 netif_start_queue(dev
);
902 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
904 struct mv643xx_private
*mp
= netdev_priv(dev
);
905 unsigned int port_num
= mp
->port_num
;
909 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
911 /* Free outstanding skb's on TX rings */
912 for (curr
= 0; mp
->tx_ring_skbs
&& curr
< mp
->tx_ring_size
; curr
++) {
913 if (mp
->tx_skb
[curr
]) {
914 dev_kfree_skb(mp
->tx_skb
[curr
]);
918 if (mp
->tx_ring_skbs
)
919 printk("%s: Error on Tx descriptor free - could not free %d"
920 " descriptors\n", dev
->name
, mp
->tx_ring_skbs
);
923 if (mp
->tx_sram_size
)
924 iounmap(mp
->p_tx_desc_area
);
926 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
927 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
930 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
932 struct mv643xx_private
*mp
= netdev_priv(dev
);
933 unsigned int port_num
= mp
->port_num
;
937 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
939 /* Free preallocated skb's on RX rings */
940 for (curr
= 0; mp
->rx_ring_skbs
&& curr
< mp
->rx_ring_size
; curr
++) {
941 if (mp
->rx_skb
[curr
]) {
942 dev_kfree_skb(mp
->rx_skb
[curr
]);
947 if (mp
->rx_ring_skbs
)
949 "%s: Error in freeing Rx Ring. %d skb's still"
950 " stuck in RX Ring - ignoring them\n", dev
->name
,
953 if (mp
->rx_sram_size
)
954 iounmap(mp
->p_rx_desc_area
);
956 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
957 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
963 * This function is used when closing the network device.
964 * It updates the hardware,
965 * release all memory that holds buffers and descriptors and release the IRQ.
966 * Input : a pointer to the device structure
967 * Output : zero if success , nonzero if fails
970 /* Helper function for mv643xx_eth_stop */
972 static int mv643xx_eth_real_stop(struct net_device
*dev
)
974 struct mv643xx_private
*mp
= netdev_priv(dev
);
975 unsigned int port_num
= mp
->port_num
;
977 netif_carrier_off(dev
);
978 netif_stop_queue(dev
);
980 mv643xx_eth_free_tx_rings(dev
);
981 mv643xx_eth_free_rx_rings(dev
);
983 eth_port_reset(mp
->port_num
);
985 /* Disable ethernet port interrupts */
986 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
987 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
989 /* Mask RX buffer and TX end interrupt */
990 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), 0);
992 /* Mask phy and link status changes interrupts */
993 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
), 0);
998 static int mv643xx_eth_stop(struct net_device
*dev
)
1000 struct mv643xx_private
*mp
= netdev_priv(dev
);
1002 spin_lock_irq(&mp
->lock
);
1004 mv643xx_eth_real_stop(dev
);
1006 free_irq(dev
->irq
, dev
);
1007 spin_unlock_irq(&mp
->lock
);
1013 static void mv643xx_tx(struct net_device
*dev
)
1015 struct mv643xx_private
*mp
= netdev_priv(dev
);
1016 struct pkt_info pkt_info
;
1018 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
1019 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
1020 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
1024 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
1028 if (pkt_info
.return_info
)
1029 dev_kfree_skb_irq(pkt_info
.return_info
);
1032 if (netif_queue_stopped(dev
) &&
1033 mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
)
1034 netif_wake_queue(dev
);
1040 * This function is used in case of NAPI
1042 static int mv643xx_poll(struct net_device
*dev
, int *budget
)
1044 struct mv643xx_private
*mp
= netdev_priv(dev
);
1045 int done
= 1, orig_budget
, work_done
;
1046 unsigned int port_num
= mp
->port_num
;
1047 unsigned long flags
;
1049 #ifdef MV643XX_TX_FAST_REFILL
1050 if (++mp
->tx_clean_threshold
> 5) {
1051 spin_lock_irqsave(&mp
->lock
, flags
);
1053 mp
->tx_clean_threshold
= 0;
1054 spin_unlock_irqrestore(&mp
->lock
, flags
);
1058 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1059 != (u32
) mp
->rx_used_desc_q
) {
1060 orig_budget
= *budget
;
1061 if (orig_budget
> dev
->quota
)
1062 orig_budget
= dev
->quota
;
1063 work_done
= mv643xx_eth_receive_queue(dev
, orig_budget
);
1064 mp
->rx_task
.func(dev
);
1065 *budget
-= work_done
;
1066 dev
->quota
-= work_done
;
1067 if (work_done
>= orig_budget
)
1072 spin_lock_irqsave(&mp
->lock
, flags
);
1073 __netif_rx_complete(dev
);
1074 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
1075 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1076 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1077 INT_CAUSE_UNMASK_ALL
);
1078 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1079 INT_CAUSE_UNMASK_ALL_EXT
);
1080 spin_unlock_irqrestore(&mp
->lock
, flags
);
1083 return done
? 0 : 1;
1088 * mv643xx_eth_start_xmit
1090 * This function is queues a packet in the Tx descriptor for
1093 * Input : skb - a pointer to socket buffer
1094 * dev - a pointer to the required port
1096 * Output : zero upon success
1098 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1100 struct mv643xx_private
*mp
= netdev_priv(dev
);
1101 struct net_device_stats
*stats
= &mp
->stats
;
1102 ETH_FUNC_RET_STATUS status
;
1103 unsigned long flags
;
1104 struct pkt_info pkt_info
;
1106 if (netif_queue_stopped(dev
)) {
1108 "%s: Tried sending packet when interface is stopped\n",
1113 /* This is a hard error, log it. */
1114 if ((mp
->tx_ring_size
- mp
->tx_ring_skbs
) <=
1115 (skb_shinfo(skb
)->nr_frags
+ 1)) {
1116 netif_stop_queue(dev
);
1118 "%s: Bug in mv643xx_eth - Trying to transmit when"
1119 " queue full !\n", dev
->name
);
1123 /* Paranoid check - this shouldn't happen */
1125 stats
->tx_dropped
++;
1126 printk(KERN_ERR
"mv64320_eth paranoid check failed\n");
1130 spin_lock_irqsave(&mp
->lock
, flags
);
1132 /* Update packet info data structure -- DMA owned, first last */
1133 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1134 if (!skb_shinfo(skb
)->nr_frags
) {
1136 if (skb
->ip_summed
!= CHECKSUM_HW
) {
1137 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1138 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1141 5 << ETH_TX_IHL_SHIFT
;
1142 pkt_info
.l4i_chk
= 0;
1145 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1148 ETH_GEN_TCP_UDP_CHECKSUM
|
1149 ETH_GEN_IP_V_4_CHECKSUM
|
1150 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1151 /* CPU already calculated pseudo header checksum. */
1152 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) {
1153 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1154 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1155 } else if (skb
->nh
.iph
->protocol
== IPPROTO_TCP
)
1156 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1159 "%s: chksum proto != TCP or UDP\n",
1161 spin_unlock_irqrestore(&mp
->lock
, flags
);
1165 pkt_info
.byte_cnt
= skb
->len
;
1166 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1168 pkt_info
.return_info
= skb
;
1169 status
= eth_port_send(mp
, &pkt_info
);
1170 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1171 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1173 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1177 /* Since hardware can't handle unaligned fragments smaller
1178 * than 9 bytes, if we find any, we linearize the skb
1179 * and start again. When I've seen it, it's always been
1180 * the first frag (probably near the end of the page),
1181 * but we check all frags to be safe.
1183 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1186 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1187 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7) {
1188 skb_linearize(skb
, GFP_ATOMIC
);
1189 printk(KERN_DEBUG
"%s: unaligned tiny fragment"
1190 "%d of %d, fixed\n",
1192 skb_shinfo(skb
)->nr_frags
);
1197 /* first frag which is skb header */
1198 pkt_info
.byte_cnt
= skb_headlen(skb
);
1199 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
1202 pkt_info
.l4i_chk
= 0;
1203 pkt_info
.return_info
= 0;
1205 if (skb
->ip_summed
!= CHECKSUM_HW
)
1206 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1207 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1208 5 << ETH_TX_IHL_SHIFT
;
1210 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1211 ETH_GEN_TCP_UDP_CHECKSUM
|
1212 ETH_GEN_IP_V_4_CHECKSUM
|
1213 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1214 /* CPU already calculated pseudo header checksum. */
1215 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) {
1216 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1217 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1218 } else if (skb
->nh
.iph
->protocol
== IPPROTO_TCP
)
1219 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1222 "%s: chksum proto != TCP or UDP\n",
1224 spin_unlock_irqrestore(&mp
->lock
, flags
);
1229 status
= eth_port_send(mp
, &pkt_info
);
1230 if (status
!= ETH_OK
) {
1231 if ((status
== ETH_ERROR
))
1233 "%s: Error on transmitting packet\n",
1235 if (status
== ETH_QUEUE_FULL
)
1236 printk("Error on Queue Full \n");
1237 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1238 printk("Tx resource error \n");
1240 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1242 /* Check for the remaining frags */
1243 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1244 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1245 pkt_info
.l4i_chk
= 0x0000;
1246 pkt_info
.cmd_sts
= 0x00000000;
1248 /* Last Frag enables interrupt and frees the skb */
1249 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1250 pkt_info
.cmd_sts
|= ETH_TX_ENABLE_INTERRUPT
|
1252 pkt_info
.return_info
= skb
;
1254 pkt_info
.return_info
= 0;
1256 pkt_info
.l4i_chk
= 0;
1257 pkt_info
.byte_cnt
= this_frag
->size
;
1259 pkt_info
.buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1260 this_frag
->page_offset
,
1264 status
= eth_port_send(mp
, &pkt_info
);
1266 if (status
!= ETH_OK
) {
1267 if ((status
== ETH_ERROR
))
1268 printk(KERN_ERR
"%s: Error on "
1269 "transmitting packet\n",
1272 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1273 printk("Tx resource error \n");
1275 if (status
== ETH_QUEUE_FULL
)
1276 printk("Queue is full \n");
1278 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1282 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
| ETH_TX_FIRST_DESC
|
1284 pkt_info
.l4i_chk
= 0;
1285 pkt_info
.byte_cnt
= skb
->len
;
1286 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1288 pkt_info
.return_info
= skb
;
1289 status
= eth_port_send(mp
, &pkt_info
);
1290 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1291 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1293 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1296 /* Check if TX queue can handle another skb. If not, then
1297 * signal higher layers to stop requesting TX
1299 if (mp
->tx_ring_size
<= (mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
1301 * Stop getting skb's from upper layers.
1302 * Getting skb's from upper layers will be enabled again after
1303 * packets are released.
1305 netif_stop_queue(dev
);
1307 /* Update statistics and start of transmittion time */
1308 stats
->tx_packets
++;
1309 dev
->trans_start
= jiffies
;
1311 spin_unlock_irqrestore(&mp
->lock
, flags
);
1313 return 0; /* success */
1317 * mv643xx_eth_get_stats
1319 * Returns a pointer to the interface statistics.
1321 * Input : dev - a pointer to the required interface
1323 * Output : a pointer to the interface's statistics
1326 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1328 struct mv643xx_private
*mp
= netdev_priv(dev
);
1333 #ifdef CONFIG_NET_POLL_CONTROLLER
1334 static inline void mv643xx_enable_irq(struct mv643xx_private
*mp
)
1336 int port_num
= mp
->port_num
;
1337 unsigned long flags
;
1339 spin_lock_irqsave(&mp
->lock
, flags
);
1340 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1341 INT_CAUSE_UNMASK_ALL
);
1342 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1343 INT_CAUSE_UNMASK_ALL_EXT
);
1344 spin_unlock_irqrestore(&mp
->lock
, flags
);
1347 static inline void mv643xx_disable_irq(struct mv643xx_private
*mp
)
1349 int port_num
= mp
->port_num
;
1350 unsigned long flags
;
1352 spin_lock_irqsave(&mp
->lock
, flags
);
1353 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1354 INT_CAUSE_MASK_ALL
);
1355 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1356 INT_CAUSE_MASK_ALL_EXT
);
1357 spin_unlock_irqrestore(&mp
->lock
, flags
);
1360 static void mv643xx_netpoll(struct net_device
*netdev
)
1362 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1364 mv643xx_disable_irq(mp
);
1365 mv643xx_eth_int_handler(netdev
->irq
, netdev
, NULL
);
1366 mv643xx_enable_irq(mp
);
1373 * First function called after registering the network device.
1374 * It's purpose is to initialize the device as an ethernet device,
1375 * fill the ethernet device structure with pointers * to functions,
1376 * and set the MAC address of the interface
1378 * Input : struct device *
1379 * Output : -ENOMEM if failed , 0 if success
1381 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1383 struct mv643xx_eth_platform_data
*pd
;
1384 int port_num
= pdev
->id
;
1385 struct mv643xx_private
*mp
;
1386 struct net_device
*dev
;
1388 struct resource
*res
;
1391 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1395 platform_set_drvdata(pdev
, dev
);
1397 mp
= netdev_priv(dev
);
1399 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1401 dev
->irq
= res
->start
;
1403 mp
->port_num
= port_num
;
1405 dev
->open
= mv643xx_eth_open
;
1406 dev
->stop
= mv643xx_eth_stop
;
1407 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1408 dev
->get_stats
= mv643xx_eth_get_stats
;
1409 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1410 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1412 /* No need to Tx Timeout */
1413 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1415 dev
->poll
= mv643xx_poll
;
1419 #ifdef CONFIG_NET_POLL_CONTROLLER
1420 dev
->poll_controller
= mv643xx_netpoll
;
1423 dev
->watchdog_timeo
= 2 * HZ
;
1424 dev
->tx_queue_len
= mp
->tx_ring_size
;
1426 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1427 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1429 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1430 #ifdef MAX_SKB_FRAGS
1432 * Zero copy can only work if we use Discovery II memory. Else, we will
1433 * have to map the buffers to ISA memory which is only 16 MB
1435 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_HW_CSUM
;
1439 /* Configure the timeout task */
1440 INIT_WORK(&mp
->tx_timeout_task
,
1441 (void (*)(void *))mv643xx_eth_tx_timeout_task
, dev
);
1443 spin_lock_init(&mp
->lock
);
1445 /* set default config values */
1446 eth_port_uc_addr_get(dev
, dev
->dev_addr
);
1447 mp
->port_config
= MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE
;
1448 mp
->port_config_extend
= MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE
;
1449 mp
->port_sdma_config
= MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE
;
1450 mp
->port_serial_control
= MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE
;
1451 mp
->rx_ring_size
= MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1452 mp
->tx_ring_size
= MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1454 pd
= pdev
->dev
.platform_data
;
1456 if (pd
->mac_addr
!= NULL
)
1457 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1459 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1460 ethernet_phy_set(port_num
, pd
->phy_addr
);
1462 if (pd
->port_config
|| pd
->force_port_config
)
1463 mp
->port_config
= pd
->port_config
;
1465 if (pd
->port_config_extend
|| pd
->force_port_config_extend
)
1466 mp
->port_config_extend
= pd
->port_config_extend
;
1468 if (pd
->port_sdma_config
|| pd
->force_port_sdma_config
)
1469 mp
->port_sdma_config
= pd
->port_sdma_config
;
1471 if (pd
->port_serial_control
|| pd
->force_port_serial_control
)
1472 mp
->port_serial_control
= pd
->port_serial_control
;
1474 if (pd
->rx_queue_size
)
1475 mp
->rx_ring_size
= pd
->rx_queue_size
;
1477 if (pd
->tx_queue_size
)
1478 mp
->tx_ring_size
= pd
->tx_queue_size
;
1480 if (pd
->tx_sram_size
) {
1481 mp
->tx_sram_size
= pd
->tx_sram_size
;
1482 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1485 if (pd
->rx_sram_size
) {
1486 mp
->rx_sram_size
= pd
->rx_sram_size
;
1487 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1491 err
= ethernet_phy_detect(port_num
);
1493 pr_debug("MV643xx ethernet port %d: "
1494 "No PHY detected at addr %d\n",
1495 port_num
, ethernet_phy_get(port_num
));
1499 err
= register_netdev(dev
);
1505 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1506 dev
->name
, port_num
, p
[0], p
[1], p
[2], p
[3], p
[4], p
[5]);
1508 if (dev
->features
& NETIF_F_SG
)
1509 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1511 if (dev
->features
& NETIF_F_IP_CSUM
)
1512 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1515 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1516 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1520 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1525 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1528 if (mp
->tx_sram_size
> 0)
1529 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1539 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1541 struct net_device
*dev
= platform_get_drvdata(pdev
);
1543 unregister_netdev(dev
);
1544 flush_scheduled_work();
1547 platform_set_drvdata(pdev
, NULL
);
1551 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1553 struct resource
*res
;
1555 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1557 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1561 mv643xx_eth_shared_base
= ioremap(res
->start
,
1562 MV643XX_ETH_SHARED_REGS_SIZE
);
1563 if (mv643xx_eth_shared_base
== NULL
)
1570 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
1572 iounmap(mv643xx_eth_shared_base
);
1573 mv643xx_eth_shared_base
= NULL
;
1578 static struct platform_driver mv643xx_eth_driver
= {
1579 .probe
= mv643xx_eth_probe
,
1580 .remove
= mv643xx_eth_remove
,
1582 .name
= MV643XX_ETH_NAME
,
1586 static struct platform_driver mv643xx_eth_shared_driver
= {
1587 .probe
= mv643xx_eth_shared_probe
,
1588 .remove
= mv643xx_eth_shared_remove
,
1590 .name
= MV643XX_ETH_SHARED_NAME
,
1595 * mv643xx_init_module
1597 * Registers the network drivers into the Linux kernel
1603 static int __init
mv643xx_init_module(void)
1607 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
1609 rc
= platform_driver_register(&mv643xx_eth_driver
);
1611 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1617 * mv643xx_cleanup_module
1619 * Registers the network drivers into the Linux kernel
1625 static void __exit
mv643xx_cleanup_module(void)
1627 platform_driver_unregister(&mv643xx_eth_driver
);
1628 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1631 module_init(mv643xx_init_module
);
1632 module_exit(mv643xx_cleanup_module
);
1634 MODULE_LICENSE("GPL");
1635 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1636 " and Dale Farnsworth");
1637 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1640 * The second part is the low level driver of the gigE ethernet ports.
1644 * Marvell's Gigabit Ethernet controller low level driver
1647 * This file introduce low level API to Marvell's Gigabit Ethernet
1648 * controller. This Gigabit Ethernet Controller driver API controls
1649 * 1) Operations (i.e. port init, start, reset etc').
1650 * 2) Data flow (i.e. port send, receive etc').
1651 * Each Gigabit Ethernet port is controlled via
1652 * struct mv643xx_private.
1653 * This struct includes user configuration information as well as
1654 * driver internal data needed for its operations.
1656 * Supported Features:
1657 * - This low level driver is OS independent. Allocating memory for
1658 * the descriptor rings and buffers are not within the scope of
1660 * - The user is free from Rx/Tx queue managing.
1661 * - This low level driver introduce functionality API that enable
1662 * the to operate Marvell's Gigabit Ethernet Controller in a
1664 * - Simple Gigabit Ethernet port operation API.
1665 * - Simple Gigabit Ethernet port data flow API.
1666 * - Data flow and operation API support per queue functionality.
1667 * - Support cached descriptors for better performance.
1668 * - Enable access to all four DRAM banks and internal SRAM memory
1670 * - PHY access and control API.
1671 * - Port control register configuration API.
1672 * - Full control over Unicast and Multicast MAC configurations.
1676 * Initialization phase
1677 * This phase complete the initialization of the the
1678 * mv643xx_private struct.
1679 * User information regarding port configuration has to be set
1680 * prior to calling the port initialization routine.
1682 * In this phase any port Tx/Rx activity is halted, MIB counters
1683 * are cleared, PHY address is set according to user parameter and
1684 * access to DRAM and internal SRAM memory spaces.
1686 * Driver ring initialization
1687 * Allocating memory for the descriptor rings and buffers is not
1688 * within the scope of this driver. Thus, the user is required to
1689 * allocate memory for the descriptors ring and buffers. Those
1690 * memory parameters are used by the Rx and Tx ring initialization
1691 * routines in order to curve the descriptor linked list in a form
1693 * Note: Pay special attention to alignment issues when using
1694 * cached descriptors/buffers. In this phase the driver store
1695 * information in the mv643xx_private struct regarding each queue
1699 * This phase prepares the Ethernet port for Rx and Tx activity.
1700 * It uses the information stored in the mv643xx_private struct to
1701 * initialize the various port registers.
1704 * All packet references to/from the driver are done using
1706 * This struct is a unified struct used with Rx and Tx operations.
1707 * This way the user is not required to be familiar with neither
1708 * Tx nor Rx descriptors structures.
1709 * The driver's descriptors rings are management by indexes.
1710 * Those indexes controls the ring resources and used to indicate
1711 * a SW resource error:
1713 * This index points to the current available resource for use. For
1714 * example in Rx process this index will point to the descriptor
1715 * that will be passed to the user upon calling the receive
1716 * routine. In Tx process, this index will point to the descriptor
1717 * that will be assigned with the user packet info and transmitted.
1719 * This index points to the descriptor that need to restore its
1720 * resources. For example in Rx process, using the Rx buffer return
1721 * API will attach the buffer returned in packet info to the
1722 * descriptor pointed by 'used'. In Tx process, using the Tx
1723 * descriptor return will merely return the user packet info with
1724 * the command status of the transmitted buffer pointed by the
1725 * 'used' index. Nevertheless, it is essential to use this routine
1726 * to update the 'used' index.
1728 * This index supports Tx Scatter-Gather. It points to the first
1729 * descriptor of a packet assembled of multiple buffers. For
1730 * example when in middle of Such packet we have a Tx resource
1731 * error the 'curr' index get the value of 'first' to indicate
1732 * that the ring returned to its state before trying to transmit
1735 * Receive operation:
1736 * The eth_port_receive API set the packet information struct,
1737 * passed by the caller, with received information from the
1738 * 'current' SDMA descriptor.
1739 * It is the user responsibility to return this resource back
1740 * to the Rx descriptor ring to enable the reuse of this source.
1741 * Return Rx resource is done using the eth_rx_return_buff API.
1743 * Transmit operation:
1744 * The eth_port_send API supports Scatter-Gather which enables to
1745 * send a packet spanned over multiple buffers. This means that
1746 * for each packet info structure given by the user and put into
1747 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1748 * bit will be set in the packet info command status field. This
1749 * API also consider restriction regarding buffer alignments and
1751 * The user must return a Tx resource after ensuring the buffer
1752 * has been transmitted to enable the Tx ring indexes to update.
1755 * This device is on-board. No jumper diagram is necessary.
1757 * EXTERNAL INTERFACE
1759 * Prior to calling the initialization routine eth_port_init() the user
1760 * must set the following fields under mv643xx_private struct:
1761 * port_num User Ethernet port number.
1762 * port_mac_addr[6] User defined port MAC address.
1763 * port_config User port configuration value.
1764 * port_config_extend User port config extend value.
1765 * port_sdma_config User port SDMA config value.
1766 * port_serial_control User port serial control value.
1768 * This driver data flow is done using the struct pkt_info which
1769 * is a unified struct for Rx and Tx operations:
1771 * byte_cnt Tx/Rx descriptor buffer byte count.
1772 * l4i_chk CPU provided TCP Checksum. For Tx operation
1774 * cmd_sts Tx/Rx descriptor command status.
1775 * buf_ptr Tx/Rx descriptor buffer pointer.
1776 * return_info Tx/Rx user resource return information.
1780 /* SDMA command macros */
1781 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1782 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1787 static int ethernet_phy_get(unsigned int eth_port_num
);
1788 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
1790 /* Ethernet Port routines */
1791 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
1795 * eth_port_init - Initialize the Ethernet port driver
1798 * This function prepares the ethernet port to start its activity:
1799 * 1) Completes the ethernet port driver struct initialization toward port
1801 * 2) Resets the device to a quiescent state in case of warm reboot.
1802 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1803 * 4) Clean MAC tables. The reset status of those tables is unknown.
1804 * 5) Set PHY address.
1805 * Note: Call this routine prior to eth_port_start routine and after
1806 * setting user values in the user fields of Ethernet port control
1810 * struct mv643xx_private *mp Ethernet port control struct
1818 static void eth_port_init(struct mv643xx_private
*mp
)
1820 mp
->port_rx_queue_command
= 0;
1821 mp
->port_tx_queue_command
= 0;
1823 mp
->rx_resource_err
= 0;
1824 mp
->tx_resource_err
= 0;
1826 eth_port_reset(mp
->port_num
);
1828 eth_port_init_mac_tables(mp
->port_num
);
1830 ethernet_phy_reset(mp
->port_num
);
1834 * eth_port_start - Start the Ethernet port activity.
1837 * This routine prepares the Ethernet port for Rx and Tx activity:
1838 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1839 * has been initialized a descriptor's ring (using
1840 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1841 * 2. Initialize and enable the Ethernet configuration port by writing to
1842 * the port's configuration and command registers.
1843 * 3. Initialize and enable the SDMA by writing to the SDMA's
1844 * configuration and command registers. After completing these steps,
1845 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1847 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1848 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1849 * and ether_init_rx_desc_ring for Rx queues).
1852 * struct mv643xx_private *mp Ethernet port control struct
1855 * Ethernet port is ready to receive and transmit.
1860 static void eth_port_start(struct mv643xx_private
*mp
)
1862 unsigned int port_num
= mp
->port_num
;
1863 int tx_curr_desc
, rx_curr_desc
;
1865 /* Assignment of Tx CTRP of given queue */
1866 tx_curr_desc
= mp
->tx_curr_desc_q
;
1867 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1868 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
1870 /* Assignment of Rx CRDP of given queue */
1871 rx_curr_desc
= mp
->rx_curr_desc_q
;
1872 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1873 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
1875 /* Add the assigned Ethernet address to the port's address table */
1876 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
1878 /* Assign port configuration and command. */
1879 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num
), mp
->port_config
);
1881 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num
),
1882 mp
->port_config_extend
);
1885 /* Increase the Rx side buffer size if supporting GigE */
1886 if (mp
->port_serial_control
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
1887 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1888 (mp
->port_serial_control
& 0xfff1ffff) | (0x5 << 17));
1890 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1891 mp
->port_serial_control
);
1893 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1894 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
)) |
1895 MV643XX_ETH_SERIAL_PORT_ENABLE
);
1897 /* Assign port SDMA configuration */
1898 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num
),
1899 mp
->port_sdma_config
);
1901 /* Enable port Rx. */
1902 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
1903 mp
->port_rx_queue_command
);
1905 /* Disable port bandwidth limits by clearing MTU register */
1906 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
1910 * eth_port_uc_addr_set - This function Set the port Unicast address.
1913 * This function Set the port Ethernet MAC address.
1916 * unsigned int eth_port_num Port number.
1917 * char * p_addr Address to be set
1920 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1921 * To set the unicast table with the proper information.
1927 static void eth_port_uc_addr_set(unsigned int eth_port_num
,
1928 unsigned char *p_addr
)
1933 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
1934 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
1937 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num
), mac_l
);
1938 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num
), mac_h
);
1940 /* Accept frames of this address */
1941 eth_port_uc_addr(eth_port_num
, p_addr
[5], ACCEPT_MAC_ADDR
);
1947 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1948 * (MAC address) from the ethernet hw registers.
1951 * This function retrieves the port Ethernet MAC address.
1954 * unsigned int eth_port_num Port number.
1955 * char *MacAddr pointer where the MAC address is stored
1958 * Copy the MAC address to the location pointed to by MacAddr
1964 static void eth_port_uc_addr_get(struct net_device
*dev
, unsigned char *p_addr
)
1966 struct mv643xx_private
*mp
= netdev_priv(dev
);
1970 mac_h
= mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp
->port_num
));
1971 mac_l
= mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp
->port_num
));
1973 p_addr
[0] = (mac_h
>> 24) & 0xff;
1974 p_addr
[1] = (mac_h
>> 16) & 0xff;
1975 p_addr
[2] = (mac_h
>> 8) & 0xff;
1976 p_addr
[3] = mac_h
& 0xff;
1977 p_addr
[4] = (mac_l
>> 8) & 0xff;
1978 p_addr
[5] = mac_l
& 0xff;
1982 * eth_port_uc_addr - This function Set the port unicast address table
1985 * This function locates the proper entry in the Unicast table for the
1986 * specified MAC nibble and sets its properties according to function
1990 * unsigned int eth_port_num Port number.
1991 * unsigned char uc_nibble Unicast MAC Address last nibble.
1992 * int option 0 = Add, 1 = remove address.
1995 * This function add/removes MAC addresses from the port unicast address
1999 * true is output succeeded.
2000 * false if option parameter is invalid.
2003 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
2006 unsigned int unicast_reg
;
2007 unsigned int tbl_offset
;
2008 unsigned int reg_offset
;
2010 /* Locate the Unicast table entry */
2011 uc_nibble
= (0xf & uc_nibble
);
2012 tbl_offset
= (uc_nibble
/ 4) * 4; /* Register offset from unicast table base */
2013 reg_offset
= uc_nibble
% 4; /* Entry offset within the above register */
2016 case REJECT_MAC_ADDR
:
2017 /* Clear accepts frame bit at given unicast DA table entry */
2018 unicast_reg
= mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2019 (eth_port_num
) + tbl_offset
));
2021 unicast_reg
&= (0x0E << (8 * reg_offset
));
2023 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2024 (eth_port_num
) + tbl_offset
), unicast_reg
);
2027 case ACCEPT_MAC_ADDR
:
2028 /* Set accepts frame bit at unicast DA filter table entry */
2030 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2031 (eth_port_num
) + tbl_offset
));
2033 unicast_reg
|= (0x01 << (8 * reg_offset
));
2035 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2036 (eth_port_num
) + tbl_offset
), unicast_reg
);
2048 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2051 * Go through all the DA filter tables (Unicast, Special Multicast &
2052 * Other Multicast) and set each entry to 0.
2055 * unsigned int eth_port_num Ethernet Port number.
2058 * Multicast and Unicast packets are rejected.
2063 static void eth_port_init_mac_tables(unsigned int eth_port_num
)
2067 /* Clear DA filter unicast table (Ex_dFUT) */
2068 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2069 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2070 (eth_port_num
) + table_index
), 0);
2072 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2073 /* Clear DA filter special multicast table (Ex_dFSMT) */
2074 mv_write((MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2075 (eth_port_num
) + table_index
), 0);
2076 /* Clear DA filter other multicast table (Ex_dFOMT) */
2077 mv_write((MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2078 (eth_port_num
) + table_index
), 0);
2083 * eth_clear_mib_counters - Clear all MIB counters
2086 * This function clears all MIB counters of a specific ethernet port.
2087 * A read from the MIB counter will reset the counter.
2090 * unsigned int eth_port_num Ethernet Port number.
2093 * After reading all MIB counters, the counters resets.
2096 * MIB counter value.
2099 static void eth_clear_mib_counters(unsigned int eth_port_num
)
2103 /* Perform dummy reads from MIB counters */
2104 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2106 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num
) + i
);
2109 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2111 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2114 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2116 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2119 p
->good_octets_received
+=
2120 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2121 p
->good_octets_received
+=
2122 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2124 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2125 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2127 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2129 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2130 p
->good_octets_sent
+=
2131 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2133 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2134 offset
<= ETH_MIB_LATE_COLLISION
;
2136 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2140 * ethernet_phy_detect - Detect whether a phy is present
2143 * This function tests whether there is a PHY present on
2144 * the specified port.
2147 * unsigned int eth_port_num Ethernet Port number.
2154 * -ENODEV on failure
2157 static int ethernet_phy_detect(unsigned int port_num
)
2159 unsigned int phy_reg_data0
;
2162 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2163 auto_neg
= phy_reg_data0
& 0x1000;
2164 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2165 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2167 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2168 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2169 return -ENODEV
; /* change didn't take */
2171 phy_reg_data0
^= 0x1000;
2172 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2177 * ethernet_phy_get - Get the ethernet port PHY address.
2180 * This routine returns the given ethernet port PHY address.
2183 * unsigned int eth_port_num Ethernet Port number.
2192 static int ethernet_phy_get(unsigned int eth_port_num
)
2194 unsigned int reg_data
;
2196 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2198 return ((reg_data
>> (5 * eth_port_num
)) & 0x1f);
2202 * ethernet_phy_set - Set the ethernet port PHY address.
2205 * This routine sets the given ethernet port PHY address.
2208 * unsigned int eth_port_num Ethernet Port number.
2209 * int phy_addr PHY address.
2218 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
)
2221 int addr_shift
= 5 * eth_port_num
;
2223 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2224 reg_data
&= ~(0x1f << addr_shift
);
2225 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2226 mv_write(MV643XX_ETH_PHY_ADDR_REG
, reg_data
);
2230 * ethernet_phy_reset - Reset Ethernet port PHY.
2233 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2236 * unsigned int eth_port_num Ethernet Port number.
2245 static void ethernet_phy_reset(unsigned int eth_port_num
)
2247 unsigned int phy_reg_data
;
2250 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2251 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2252 eth_port_write_smi_reg(eth_port_num
, 0, phy_reg_data
);
2256 * eth_port_reset - Reset Ethernet port
2259 * This routine resets the chip by aborting any SDMA engine activity and
2260 * clearing the MIB counters. The Receiver and the Transmit unit are in
2261 * idle state after this command is performed and the port is disabled.
2264 * unsigned int eth_port_num Ethernet Port number.
2267 * Channel activity is halted.
2273 static void eth_port_reset(unsigned int port_num
)
2275 unsigned int reg_data
;
2277 /* Stop Tx port activity. Check port Tx activity. */
2278 reg_data
= mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
));
2280 if (reg_data
& 0xFF) {
2281 /* Issue stop command for active channels only */
2282 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
),
2285 /* Wait for all Tx activity to terminate. */
2286 /* Check port cause register that all Tx queues are stopped */
2287 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
))
2292 /* Stop Rx port activity. Check port Rx activity. */
2293 reg_data
= mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
));
2295 if (reg_data
& 0xFF) {
2296 /* Issue stop command for active channels only */
2297 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
2300 /* Wait for all Rx activity to terminate. */
2301 /* Check port cause register that all Rx queues are stopped */
2302 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
))
2307 /* Clear all MIB counters */
2308 eth_clear_mib_counters(port_num
);
2310 /* Reset the Enable bit in the Configuration Register */
2311 reg_data
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
2312 reg_data
&= ~MV643XX_ETH_SERIAL_PORT_ENABLE
;
2313 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2317 static int eth_port_autoneg_supported(unsigned int eth_port_num
)
2319 unsigned int phy_reg_data0
;
2321 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data0
);
2323 return phy_reg_data0
& 0x1000;
2326 static int eth_port_link_is_up(unsigned int eth_port_num
)
2328 unsigned int phy_reg_data1
;
2330 eth_port_read_smi_reg(eth_port_num
, 1, &phy_reg_data1
);
2332 if (eth_port_autoneg_supported(eth_port_num
)) {
2333 if (phy_reg_data1
& 0x20) /* auto-neg complete */
2335 } else if (phy_reg_data1
& 0x4) /* link up */
2342 * eth_port_read_smi_reg - Read PHY registers
2345 * This routine utilize the SMI interface to interact with the PHY in
2346 * order to perform PHY register read.
2349 * unsigned int port_num Ethernet Port number.
2350 * unsigned int phy_reg PHY register address offset.
2351 * unsigned int *value Register value buffer.
2354 * Write the value of a specified PHY register into given buffer.
2357 * false if the PHY is busy or read data is not in valid state.
2361 static void eth_port_read_smi_reg(unsigned int port_num
,
2362 unsigned int phy_reg
, unsigned int *value
)
2364 int phy_addr
= ethernet_phy_get(port_num
);
2365 unsigned long flags
;
2368 /* the SMI register is a shared resource */
2369 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2371 /* wait for the SMI register to become available */
2372 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2373 if (i
== PHY_WAIT_ITERATIONS
) {
2374 printk("mv643xx PHY busy timeout, port %d\n", port_num
);
2377 udelay(PHY_WAIT_MICRO_SECONDS
);
2380 mv_write(MV643XX_ETH_SMI_REG
,
2381 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2383 /* now wait for the data to be valid */
2384 for (i
= 0; !(mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2385 if (i
== PHY_WAIT_ITERATIONS
) {
2386 printk("mv643xx PHY read timeout, port %d\n", port_num
);
2389 udelay(PHY_WAIT_MICRO_SECONDS
);
2392 *value
= mv_read(MV643XX_ETH_SMI_REG
) & 0xffff;
2394 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2398 * eth_port_write_smi_reg - Write to PHY registers
2401 * This routine utilize the SMI interface to interact with the PHY in
2402 * order to perform writes to PHY registers.
2405 * unsigned int eth_port_num Ethernet Port number.
2406 * unsigned int phy_reg PHY register address offset.
2407 * unsigned int value Register value.
2410 * Write the given value to the specified PHY register.
2413 * false if the PHY is busy.
2417 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
2418 unsigned int phy_reg
, unsigned int value
)
2422 unsigned long flags
;
2424 phy_addr
= ethernet_phy_get(eth_port_num
);
2426 /* the SMI register is a shared resource */
2427 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2429 /* wait for the SMI register to become available */
2430 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2431 if (i
== PHY_WAIT_ITERATIONS
) {
2432 printk("mv643xx PHY busy timeout, port %d\n",
2436 udelay(PHY_WAIT_MICRO_SECONDS
);
2439 mv_write(MV643XX_ETH_SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2440 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2442 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2446 * eth_port_send - Send an Ethernet packet
2449 * This routine send a given packet described by p_pktinfo parameter. It
2450 * supports transmitting of a packet spaned over multiple buffers. The
2451 * routine updates 'curr' and 'first' indexes according to the packet
2452 * segment passed to the routine. In case the packet segment is first,
2453 * the 'first' index is update. In any case, the 'curr' index is updated.
2454 * If the routine get into Tx resource error it assigns 'curr' index as
2455 * 'first'. This way the function can abort Tx process of multiple
2456 * descriptors per packet.
2459 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2460 * struct pkt_info *p_pkt_info User packet buffer.
2463 * Tx ring 'curr' and 'first' indexes are updated.
2466 * ETH_QUEUE_FULL in case of Tx resource error.
2467 * ETH_ERROR in case the routine can not access Tx desc ring.
2468 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2472 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2474 * Modified to include the first descriptor pointer in case of SG
2476 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2477 struct pkt_info
*p_pkt_info
)
2479 int tx_desc_curr
, tx_desc_used
, tx_first_desc
, tx_next_desc
;
2480 struct eth_tx_desc
*current_descriptor
;
2481 struct eth_tx_desc
*first_descriptor
;
2484 /* Do not process Tx ring in case of Tx ring resource error */
2485 if (mp
->tx_resource_err
)
2486 return ETH_QUEUE_FULL
;
2489 * The hardware requires that each buffer that is <= 8 bytes
2490 * in length must be aligned on an 8 byte boundary.
2492 if (p_pkt_info
->byte_cnt
<= 8 && p_pkt_info
->buf_ptr
& 0x7) {
2494 "mv643xx_eth port %d: packet size <= 8 problem\n",
2500 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2502 /* Get the Tx Desc ring indexes */
2503 tx_desc_curr
= mp
->tx_curr_desc_q
;
2504 tx_desc_used
= mp
->tx_used_desc_q
;
2506 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2508 tx_next_desc
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2510 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2511 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2512 current_descriptor
->l4i_chk
= p_pkt_info
->l4i_chk
;
2513 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2515 command
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
|
2516 ETH_BUFFER_OWNED_BY_DMA
;
2517 if (command
& ETH_TX_FIRST_DESC
) {
2518 tx_first_desc
= tx_desc_curr
;
2519 mp
->tx_first_desc_q
= tx_first_desc
;
2520 first_descriptor
= current_descriptor
;
2521 mp
->tx_first_command
= command
;
2523 tx_first_desc
= mp
->tx_first_desc_q
;
2524 first_descriptor
= &mp
->p_tx_desc_area
[tx_first_desc
];
2525 BUG_ON(first_descriptor
== NULL
);
2526 current_descriptor
->cmd_sts
= command
;
2529 if (command
& ETH_TX_LAST_DESC
) {
2531 first_descriptor
->cmd_sts
= mp
->tx_first_command
;
2534 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2537 * Finish Tx packet. Update first desc in case of Tx resource
2539 tx_first_desc
= tx_next_desc
;
2540 mp
->tx_first_desc_q
= tx_first_desc
;
2543 /* Check for ring index overlap in the Tx desc ring */
2544 if (tx_next_desc
== tx_desc_used
) {
2545 mp
->tx_resource_err
= 1;
2546 mp
->tx_curr_desc_q
= tx_first_desc
;
2548 return ETH_QUEUE_LAST_RESOURCE
;
2551 mp
->tx_curr_desc_q
= tx_next_desc
;
2556 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2557 struct pkt_info
*p_pkt_info
)
2561 struct eth_tx_desc
*current_descriptor
;
2562 unsigned int command_status
;
2564 /* Do not process Tx ring in case of Tx ring resource error */
2565 if (mp
->tx_resource_err
)
2566 return ETH_QUEUE_FULL
;
2569 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2571 /* Get the Tx Desc ring indexes */
2572 tx_desc_curr
= mp
->tx_curr_desc_q
;
2573 tx_desc_used
= mp
->tx_used_desc_q
;
2574 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2576 command_status
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
;
2577 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2578 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2579 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2581 /* Set last desc with DMA ownership and interrupt enable. */
2583 current_descriptor
->cmd_sts
= command_status
|
2584 ETH_BUFFER_OWNED_BY_DMA
| ETH_TX_ENABLE_INTERRUPT
;
2587 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2589 /* Finish Tx packet. Update first desc in case of Tx resource error */
2590 tx_desc_curr
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2592 /* Update the current descriptor */
2593 mp
->tx_curr_desc_q
= tx_desc_curr
;
2595 /* Check for ring index overlap in the Tx desc ring */
2596 if (tx_desc_curr
== tx_desc_used
) {
2597 mp
->tx_resource_err
= 1;
2598 return ETH_QUEUE_LAST_RESOURCE
;
2606 * eth_tx_return_desc - Free all used Tx descriptors
2609 * This routine returns the transmitted packet information to the caller.
2610 * It uses the 'first' index to support Tx desc return in case a transmit
2611 * of a packet spanned over multiple buffer still in process.
2612 * In case the Tx queue was in "resource error" condition, where there are
2613 * no available Tx resources, the function resets the resource error flag.
2616 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2617 * struct pkt_info *p_pkt_info User packet buffer.
2620 * Tx ring 'first' and 'used' indexes are updated.
2623 * ETH_ERROR in case the routine can not access Tx desc ring.
2624 * ETH_RETRY in case there is transmission in process.
2625 * ETH_END_OF_JOB if the routine has nothing to release.
2629 static ETH_FUNC_RET_STATUS
eth_tx_return_desc(struct mv643xx_private
*mp
,
2630 struct pkt_info
*p_pkt_info
)
2633 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2634 int tx_busy_desc
= mp
->tx_first_desc_q
;
2636 int tx_busy_desc
= mp
->tx_curr_desc_q
;
2638 struct eth_tx_desc
*p_tx_desc_used
;
2639 unsigned int command_status
;
2641 /* Get the Tx Desc ring indexes */
2642 tx_desc_used
= mp
->tx_used_desc_q
;
2644 p_tx_desc_used
= &mp
->p_tx_desc_area
[tx_desc_used
];
2647 if (p_tx_desc_used
== NULL
)
2650 /* Stop release. About to overlap the current available Tx descriptor */
2651 if (tx_desc_used
== tx_busy_desc
&& !mp
->tx_resource_err
)
2652 return ETH_END_OF_JOB
;
2654 command_status
= p_tx_desc_used
->cmd_sts
;
2656 /* Still transmitting... */
2657 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
))
2660 /* Pass the packet information to the caller */
2661 p_pkt_info
->cmd_sts
= command_status
;
2662 p_pkt_info
->return_info
= mp
->tx_skb
[tx_desc_used
];
2663 p_pkt_info
->buf_ptr
= p_tx_desc_used
->buf_ptr
;
2664 p_pkt_info
->byte_cnt
= p_tx_desc_used
->byte_cnt
;
2665 mp
->tx_skb
[tx_desc_used
] = NULL
;
2667 /* Update the next descriptor to release. */
2668 mp
->tx_used_desc_q
= (tx_desc_used
+ 1) % mp
->tx_ring_size
;
2670 /* Any Tx return cancels the Tx resource error status */
2671 mp
->tx_resource_err
= 0;
2673 BUG_ON(mp
->tx_ring_skbs
== 0);
2680 * eth_port_receive - Get received information from Rx ring.
2683 * This routine returns the received data to the caller. There is no
2684 * data copying during routine operation. All information is returned
2685 * using pointer to packet information struct passed from the caller.
2686 * If the routine exhausts Rx ring resources then the resource error flag
2690 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2691 * struct pkt_info *p_pkt_info User packet buffer.
2694 * Rx ring current and used indexes are updated.
2697 * ETH_ERROR in case the routine can not access Rx desc ring.
2698 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2699 * ETH_END_OF_JOB if there is no received data.
2702 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
2703 struct pkt_info
*p_pkt_info
)
2705 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
2706 volatile struct eth_rx_desc
*p_rx_desc
;
2707 unsigned int command_status
;
2709 /* Do not process Rx ring in case of Rx ring resource error */
2710 if (mp
->rx_resource_err
)
2711 return ETH_QUEUE_FULL
;
2713 /* Get the Rx Desc ring 'curr and 'used' indexes */
2714 rx_curr_desc
= mp
->rx_curr_desc_q
;
2715 rx_used_desc
= mp
->rx_used_desc_q
;
2717 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
2719 /* The following parameters are used to save readings from memory */
2720 command_status
= p_rx_desc
->cmd_sts
;
2723 /* Nothing to receive... */
2724 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
))
2725 return ETH_END_OF_JOB
;
2727 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
2728 p_pkt_info
->cmd_sts
= command_status
;
2729 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
2730 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
2731 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
2733 /* Clean the return info field to indicate that the packet has been */
2734 /* moved to the upper layers */
2735 mp
->rx_skb
[rx_curr_desc
] = NULL
;
2737 /* Update current index in data structure */
2738 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
2739 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
2741 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2742 if (rx_next_curr_desc
== rx_used_desc
)
2743 mp
->rx_resource_err
= 1;
2749 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2752 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2753 * next 'used' descriptor and attached the returned buffer to it.
2754 * In case the Rx ring was in "resource error" condition, where there are
2755 * no available Rx resources, the function resets the resource error flag.
2758 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2759 * struct pkt_info *p_pkt_info Information on returned buffer.
2762 * New available Rx resource in Rx descriptor ring.
2765 * ETH_ERROR in case the routine can not access Rx desc ring.
2768 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
2769 struct pkt_info
*p_pkt_info
)
2771 int used_rx_desc
; /* Where to return Rx resource */
2772 volatile struct eth_rx_desc
*p_used_rx_desc
;
2774 /* Get 'used' Rx descriptor */
2775 used_rx_desc
= mp
->rx_used_desc_q
;
2776 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
2778 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
2779 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
2780 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
2782 /* Flush the write pipe */
2784 /* Return the descriptor to DMA ownership */
2786 p_used_rx_desc
->cmd_sts
=
2787 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
2790 /* Move the used descriptor pointer to the next descriptor */
2791 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
2793 /* Any Rx return cancels the Rx resource error status */
2794 mp
->rx_resource_err
= 0;
2799 /************* Begin ethtool support *************************/
2801 struct mv643xx_stats
{
2802 char stat_string
[ETH_GSTRING_LEN
];
2807 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
2808 offsetof(struct mv643xx_private, m)
2810 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
2811 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
2812 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
2813 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
2814 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
2815 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
2816 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
2817 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
2818 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
2819 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
2820 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
2821 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
2822 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
2823 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
2824 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
2825 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
2826 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
2827 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
2828 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
2829 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
2830 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
2831 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
2832 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
2833 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
2834 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
2835 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
2836 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
2837 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
2838 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
2839 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
2840 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
2841 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
2842 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
2843 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
2844 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
2845 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
2846 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
2847 { "collision", MV643XX_STAT(mib_counters
.collision
) },
2848 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
2851 #define MV643XX_STATS_LEN \
2852 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
2855 mv643xx_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*ecmd
)
2857 struct mv643xx_private
*mp
= netdev
->priv
;
2858 int port_num
= mp
->port_num
;
2859 int autoneg
= eth_port_autoneg_supported(port_num
);
2862 int half_duplex
= 0;
2863 int full_duplex
= 0;
2869 u32 pcs
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
2870 u32 psr
= mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num
));
2872 mode_10_bit
= psr
& MV643XX_ETH_PORT_STATUS_MODE_10_BIT
;
2875 ecmd
->supported
= SUPPORTED_10baseT_Half
;
2877 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
2878 SUPPORTED_10baseT_Full
|
2879 SUPPORTED_100baseT_Half
|
2880 SUPPORTED_100baseT_Full
|
2881 SUPPORTED_1000baseT_Full
|
2882 (autoneg
? SUPPORTED_Autoneg
: 0) |
2885 auto_duplex
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX
);
2886 auto_speed
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII
);
2888 ecmd
->advertising
= ADVERTISED_TP
;
2891 ecmd
->advertising
|= ADVERTISED_Autoneg
;
2897 if (pcs
& MV643XX_ETH_SET_FULL_DUPLEX_MODE
)
2908 if (pcs
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
2910 else if (pcs
& MV643XX_ETH_SET_MII_SPEED_TO_100
)
2916 if (speed_10
& half_duplex
)
2917 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
2918 if (speed_10
& full_duplex
)
2919 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
2920 if (speed_100
& half_duplex
)
2921 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
2922 if (speed_100
& full_duplex
)
2923 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
2925 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
2929 ecmd
->port
= PORT_TP
;
2930 ecmd
->phy_address
= ethernet_phy_get(port_num
);
2932 ecmd
->transceiver
= XCVR_EXTERNAL
;
2934 if (netif_carrier_ok(netdev
)) {
2936 ecmd
->speed
= SPEED_10
;
2938 if (psr
& MV643XX_ETH_PORT_STATUS_GMII_1000
)
2939 ecmd
->speed
= SPEED_1000
;
2940 else if (psr
& MV643XX_ETH_PORT_STATUS_MII_100
)
2941 ecmd
->speed
= SPEED_100
;
2943 ecmd
->speed
= SPEED_10
;
2946 if (psr
& MV643XX_ETH_PORT_STATUS_FULL_DUPLEX
)
2947 ecmd
->duplex
= DUPLEX_FULL
;
2949 ecmd
->duplex
= DUPLEX_HALF
;
2955 ecmd
->autoneg
= autoneg
? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
2960 mv643xx_get_drvinfo(struct net_device
*netdev
,
2961 struct ethtool_drvinfo
*drvinfo
)
2963 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
2964 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
2965 strncpy(drvinfo
->fw_version
, "N/A", 32);
2966 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
2967 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
2971 mv643xx_get_stats_count(struct net_device
*netdev
)
2973 return MV643XX_STATS_LEN
;
2977 mv643xx_get_ethtool_stats(struct net_device
*netdev
,
2978 struct ethtool_stats
*stats
, uint64_t *data
)
2980 struct mv643xx_private
*mp
= netdev
->priv
;
2983 eth_update_mib_counters(mp
);
2985 for(i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
2986 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
2987 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
2988 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
2993 mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
, uint8_t *data
)
2999 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
3000 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3001 mv643xx_gstrings_stats
[i
].stat_string
,
3008 static struct ethtool_ops mv643xx_ethtool_ops
= {
3009 .get_settings
= mv643xx_get_settings
,
3010 .get_drvinfo
= mv643xx_get_drvinfo
,
3011 .get_link
= ethtool_op_get_link
,
3012 .get_sg
= ethtool_op_get_sg
,
3013 .set_sg
= ethtool_op_set_sg
,
3014 .get_strings
= mv643xx_get_strings
,
3015 .get_stats_count
= mv643xx_get_stats_count
,
3016 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
3019 /************* End ethtool support *************************/