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[deliverable/linux.git] / drivers / net / mv643xx_eth.c
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
4 *
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
8 *
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
11 *
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 *
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
16 *
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
19 *
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
22 *
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
27 *
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
32 *
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
36 */
37
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/in.h>
41 #include <linux/ip.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
54 #include <linux/io.h>
55 #include <linux/types.h>
56 #include <linux/inet_lro.h>
57 #include <asm/system.h>
58
59 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
60 static char mv643xx_eth_driver_version[] = "1.4";
61
62
63 /*
64 * Registers shared between all ports.
65 */
66 #define PHY_ADDR 0x0000
67 #define SMI_REG 0x0004
68 #define SMI_BUSY 0x10000000
69 #define SMI_READ_VALID 0x08000000
70 #define SMI_OPCODE_READ 0x04000000
71 #define SMI_OPCODE_WRITE 0x00000000
72 #define ERR_INT_CAUSE 0x0080
73 #define ERR_INT_SMI_DONE 0x00000010
74 #define ERR_INT_MASK 0x0084
75 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
76 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
77 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
78 #define WINDOW_BAR_ENABLE 0x0290
79 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
80
81 /*
82 * Main per-port registers. These live at offset 0x0400 for
83 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
84 */
85 #define PORT_CONFIG 0x0000
86 #define UNICAST_PROMISCUOUS_MODE 0x00000001
87 #define PORT_CONFIG_EXT 0x0004
88 #define MAC_ADDR_LOW 0x0014
89 #define MAC_ADDR_HIGH 0x0018
90 #define SDMA_CONFIG 0x001c
91 #define PORT_SERIAL_CONTROL 0x003c
92 #define PORT_STATUS 0x0044
93 #define TX_FIFO_EMPTY 0x00000400
94 #define TX_IN_PROGRESS 0x00000080
95 #define PORT_SPEED_MASK 0x00000030
96 #define PORT_SPEED_1000 0x00000010
97 #define PORT_SPEED_100 0x00000020
98 #define PORT_SPEED_10 0x00000000
99 #define FLOW_CONTROL_ENABLED 0x00000008
100 #define FULL_DUPLEX 0x00000004
101 #define LINK_UP 0x00000002
102 #define TXQ_COMMAND 0x0048
103 #define TXQ_FIX_PRIO_CONF 0x004c
104 #define TX_BW_RATE 0x0050
105 #define TX_BW_MTU 0x0058
106 #define TX_BW_BURST 0x005c
107 #define INT_CAUSE 0x0060
108 #define INT_TX_END 0x07f80000
109 #define INT_RX 0x000003fc
110 #define INT_EXT 0x00000002
111 #define INT_CAUSE_EXT 0x0064
112 #define INT_EXT_LINK_PHY 0x00110000
113 #define INT_EXT_TX 0x000000ff
114 #define INT_MASK 0x0068
115 #define INT_MASK_EXT 0x006c
116 #define TX_FIFO_URGENT_THRESHOLD 0x0074
117 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
118 #define TX_BW_RATE_MOVED 0x00e0
119 #define TX_BW_MTU_MOVED 0x00e8
120 #define TX_BW_BURST_MOVED 0x00ec
121 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
122 #define RXQ_COMMAND 0x0280
123 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
124 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
125 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
126 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
127
128 /*
129 * Misc per-port registers.
130 */
131 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
132 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
133 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
134 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
135
136
137 /*
138 * SDMA configuration register.
139 */
140 #define RX_BURST_SIZE_4_64BIT (2 << 1)
141 #define RX_BURST_SIZE_16_64BIT (4 << 1)
142 #define BLM_RX_NO_SWAP (1 << 4)
143 #define BLM_TX_NO_SWAP (1 << 5)
144 #define TX_BURST_SIZE_4_64BIT (2 << 22)
145 #define TX_BURST_SIZE_16_64BIT (4 << 22)
146
147 #if defined(__BIG_ENDIAN)
148 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
149 (RX_BURST_SIZE_4_64BIT | \
150 TX_BURST_SIZE_4_64BIT)
151 #elif defined(__LITTLE_ENDIAN)
152 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
153 (RX_BURST_SIZE_4_64BIT | \
154 BLM_RX_NO_SWAP | \
155 BLM_TX_NO_SWAP | \
156 TX_BURST_SIZE_4_64BIT)
157 #else
158 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
159 #endif
160
161
162 /*
163 * Port serial control register.
164 */
165 #define SET_MII_SPEED_TO_100 (1 << 24)
166 #define SET_GMII_SPEED_TO_1000 (1 << 23)
167 #define SET_FULL_DUPLEX_MODE (1 << 21)
168 #define MAX_RX_PACKET_9700BYTE (5 << 17)
169 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
170 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
171 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
172 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
173 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
174 #define FORCE_LINK_PASS (1 << 1)
175 #define SERIAL_PORT_ENABLE (1 << 0)
176
177 #define DEFAULT_RX_QUEUE_SIZE 128
178 #define DEFAULT_TX_QUEUE_SIZE 256
179
180
181 /*
182 * RX/TX descriptors.
183 */
184 #if defined(__BIG_ENDIAN)
185 struct rx_desc {
186 u16 byte_cnt; /* Descriptor buffer byte count */
187 u16 buf_size; /* Buffer size */
188 u32 cmd_sts; /* Descriptor command status */
189 u32 next_desc_ptr; /* Next descriptor pointer */
190 u32 buf_ptr; /* Descriptor buffer pointer */
191 };
192
193 struct tx_desc {
194 u16 byte_cnt; /* buffer byte count */
195 u16 l4i_chk; /* CPU provided TCP checksum */
196 u32 cmd_sts; /* Command/status field */
197 u32 next_desc_ptr; /* Pointer to next descriptor */
198 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 };
200 #elif defined(__LITTLE_ENDIAN)
201 struct rx_desc {
202 u32 cmd_sts; /* Descriptor command status */
203 u16 buf_size; /* Buffer size */
204 u16 byte_cnt; /* Descriptor buffer byte count */
205 u32 buf_ptr; /* Descriptor buffer pointer */
206 u32 next_desc_ptr; /* Next descriptor pointer */
207 };
208
209 struct tx_desc {
210 u32 cmd_sts; /* Command/status field */
211 u16 l4i_chk; /* CPU provided TCP checksum */
212 u16 byte_cnt; /* buffer byte count */
213 u32 buf_ptr; /* pointer to buffer for this descriptor*/
214 u32 next_desc_ptr; /* Pointer to next descriptor */
215 };
216 #else
217 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
218 #endif
219
220 /* RX & TX descriptor command */
221 #define BUFFER_OWNED_BY_DMA 0x80000000
222
223 /* RX & TX descriptor status */
224 #define ERROR_SUMMARY 0x00000001
225
226 /* RX descriptor status */
227 #define LAYER_4_CHECKSUM_OK 0x40000000
228 #define RX_ENABLE_INTERRUPT 0x20000000
229 #define RX_FIRST_DESC 0x08000000
230 #define RX_LAST_DESC 0x04000000
231 #define RX_IP_HDR_OK 0x02000000
232 #define RX_PKT_IS_IPV4 0x01000000
233 #define RX_PKT_IS_ETHERNETV2 0x00800000
234 #define RX_PKT_LAYER4_TYPE_MASK 0x00600000
235 #define RX_PKT_LAYER4_TYPE_TCP_IPV4 0x00000000
236 #define RX_PKT_IS_VLAN_TAGGED 0x00080000
237
238 /* TX descriptor command */
239 #define TX_ENABLE_INTERRUPT 0x00800000
240 #define GEN_CRC 0x00400000
241 #define TX_FIRST_DESC 0x00200000
242 #define TX_LAST_DESC 0x00100000
243 #define ZERO_PADDING 0x00080000
244 #define GEN_IP_V4_CHECKSUM 0x00040000
245 #define GEN_TCP_UDP_CHECKSUM 0x00020000
246 #define UDP_FRAME 0x00010000
247 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
248 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
249
250 #define TX_IHL_SHIFT 11
251
252
253 /* global *******************************************************************/
254 struct mv643xx_eth_shared_private {
255 /*
256 * Ethernet controller base address.
257 */
258 void __iomem *base;
259
260 /*
261 * Points at the right SMI instance to use.
262 */
263 struct mv643xx_eth_shared_private *smi;
264
265 /*
266 * Provides access to local SMI interface.
267 */
268 struct mii_bus *smi_bus;
269
270 /*
271 * If we have access to the error interrupt pin (which is
272 * somewhat misnamed as it not only reflects internal errors
273 * but also reflects SMI completion), use that to wait for
274 * SMI access completion instead of polling the SMI busy bit.
275 */
276 int err_interrupt;
277 wait_queue_head_t smi_busy_wait;
278
279 /*
280 * Per-port MBUS window access register value.
281 */
282 u32 win_protect;
283
284 /*
285 * Hardware-specific parameters.
286 */
287 unsigned int t_clk;
288 int extended_rx_coal_limit;
289 int tx_bw_control;
290 };
291
292 #define TX_BW_CONTROL_ABSENT 0
293 #define TX_BW_CONTROL_OLD_LAYOUT 1
294 #define TX_BW_CONTROL_NEW_LAYOUT 2
295
296 static int mv643xx_eth_open(struct net_device *dev);
297 static int mv643xx_eth_stop(struct net_device *dev);
298
299
300 /* per-port *****************************************************************/
301 struct mib_counters {
302 u64 good_octets_received;
303 u32 bad_octets_received;
304 u32 internal_mac_transmit_err;
305 u32 good_frames_received;
306 u32 bad_frames_received;
307 u32 broadcast_frames_received;
308 u32 multicast_frames_received;
309 u32 frames_64_octets;
310 u32 frames_65_to_127_octets;
311 u32 frames_128_to_255_octets;
312 u32 frames_256_to_511_octets;
313 u32 frames_512_to_1023_octets;
314 u32 frames_1024_to_max_octets;
315 u64 good_octets_sent;
316 u32 good_frames_sent;
317 u32 excessive_collision;
318 u32 multicast_frames_sent;
319 u32 broadcast_frames_sent;
320 u32 unrec_mac_control_received;
321 u32 fc_sent;
322 u32 good_fc_received;
323 u32 bad_fc_received;
324 u32 undersize_received;
325 u32 fragments_received;
326 u32 oversize_received;
327 u32 jabber_received;
328 u32 mac_receive_error;
329 u32 bad_crc_event;
330 u32 collision;
331 u32 late_collision;
332 };
333
334 struct lro_counters {
335 u32 lro_aggregated;
336 u32 lro_flushed;
337 u32 lro_no_desc;
338 };
339
340 struct rx_queue {
341 int index;
342
343 int rx_ring_size;
344
345 int rx_desc_count;
346 int rx_curr_desc;
347 int rx_used_desc;
348
349 struct rx_desc *rx_desc_area;
350 dma_addr_t rx_desc_dma;
351 int rx_desc_area_size;
352 struct sk_buff **rx_skb;
353
354 #ifdef CONFIG_MV643XX_ETH_LRO
355 struct net_lro_mgr lro_mgr;
356 struct net_lro_desc lro_arr[8];
357 #endif
358 };
359
360 struct tx_queue {
361 int index;
362
363 int tx_ring_size;
364
365 int tx_desc_count;
366 int tx_curr_desc;
367 int tx_used_desc;
368
369 struct tx_desc *tx_desc_area;
370 dma_addr_t tx_desc_dma;
371 int tx_desc_area_size;
372
373 struct sk_buff_head tx_skb;
374
375 unsigned long tx_packets;
376 unsigned long tx_bytes;
377 unsigned long tx_dropped;
378 };
379
380 struct mv643xx_eth_private {
381 struct mv643xx_eth_shared_private *shared;
382 void __iomem *base;
383 int port_num;
384
385 struct net_device *dev;
386
387 struct phy_device *phy;
388
389 struct timer_list mib_counters_timer;
390 spinlock_t mib_counters_lock;
391 struct mib_counters mib_counters;
392
393 struct lro_counters lro_counters;
394
395 struct work_struct tx_timeout_task;
396
397 struct napi_struct napi;
398 u8 work_link;
399 u8 work_tx;
400 u8 work_tx_end;
401 u8 work_rx;
402 u8 work_rx_refill;
403 u8 work_rx_oom;
404
405 int skb_size;
406 struct sk_buff_head rx_recycle;
407
408 /*
409 * RX state.
410 */
411 int rx_ring_size;
412 unsigned long rx_desc_sram_addr;
413 int rx_desc_sram_size;
414 int rxq_count;
415 struct timer_list rx_oom;
416 struct rx_queue rxq[8];
417
418 /*
419 * TX state.
420 */
421 int tx_ring_size;
422 unsigned long tx_desc_sram_addr;
423 int tx_desc_sram_size;
424 int txq_count;
425 struct tx_queue txq[8];
426 };
427
428
429 /* port register accessors **************************************************/
430 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
431 {
432 return readl(mp->shared->base + offset);
433 }
434
435 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
436 {
437 return readl(mp->base + offset);
438 }
439
440 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
441 {
442 writel(data, mp->shared->base + offset);
443 }
444
445 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
446 {
447 writel(data, mp->base + offset);
448 }
449
450
451 /* rxq/txq helper functions *************************************************/
452 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
453 {
454 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
455 }
456
457 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
458 {
459 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
460 }
461
462 static void rxq_enable(struct rx_queue *rxq)
463 {
464 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
465 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
466 }
467
468 static void rxq_disable(struct rx_queue *rxq)
469 {
470 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
471 u8 mask = 1 << rxq->index;
472
473 wrlp(mp, RXQ_COMMAND, mask << 8);
474 while (rdlp(mp, RXQ_COMMAND) & mask)
475 udelay(10);
476 }
477
478 static void txq_reset_hw_ptr(struct tx_queue *txq)
479 {
480 struct mv643xx_eth_private *mp = txq_to_mp(txq);
481 u32 addr;
482
483 addr = (u32)txq->tx_desc_dma;
484 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
485 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
486 }
487
488 static void txq_enable(struct tx_queue *txq)
489 {
490 struct mv643xx_eth_private *mp = txq_to_mp(txq);
491 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
492 }
493
494 static void txq_disable(struct tx_queue *txq)
495 {
496 struct mv643xx_eth_private *mp = txq_to_mp(txq);
497 u8 mask = 1 << txq->index;
498
499 wrlp(mp, TXQ_COMMAND, mask << 8);
500 while (rdlp(mp, TXQ_COMMAND) & mask)
501 udelay(10);
502 }
503
504 static void txq_maybe_wake(struct tx_queue *txq)
505 {
506 struct mv643xx_eth_private *mp = txq_to_mp(txq);
507 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
508
509 if (netif_tx_queue_stopped(nq)) {
510 __netif_tx_lock(nq, smp_processor_id());
511 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
512 netif_tx_wake_queue(nq);
513 __netif_tx_unlock(nq);
514 }
515 }
516
517
518 /* rx napi ******************************************************************/
519 #ifdef CONFIG_MV643XX_ETH_LRO
520 static int
521 mv643xx_get_skb_header(struct sk_buff *skb, void **iphdr, void **tcph,
522 u64 *hdr_flags, void *priv)
523 {
524 unsigned long cmd_sts = (unsigned long)priv;
525
526 /*
527 * Make sure that this packet is Ethernet II, is not VLAN
528 * tagged, is IPv4, has a valid IP header, and is TCP.
529 */
530 if ((cmd_sts & (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
531 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_MASK |
532 RX_PKT_IS_VLAN_TAGGED)) !=
533 (RX_IP_HDR_OK | RX_PKT_IS_IPV4 |
534 RX_PKT_IS_ETHERNETV2 | RX_PKT_LAYER4_TYPE_TCP_IPV4))
535 return -1;
536
537 skb_reset_network_header(skb);
538 skb_set_transport_header(skb, ip_hdrlen(skb));
539 *iphdr = ip_hdr(skb);
540 *tcph = tcp_hdr(skb);
541 *hdr_flags = LRO_IPV4 | LRO_TCP;
542
543 return 0;
544 }
545 #endif
546
547 static int rxq_process(struct rx_queue *rxq, int budget)
548 {
549 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
550 struct net_device_stats *stats = &mp->dev->stats;
551 int lro_flush_needed;
552 int rx;
553
554 lro_flush_needed = 0;
555 rx = 0;
556 while (rx < budget && rxq->rx_desc_count) {
557 struct rx_desc *rx_desc;
558 unsigned int cmd_sts;
559 struct sk_buff *skb;
560 u16 byte_cnt;
561
562 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
563
564 cmd_sts = rx_desc->cmd_sts;
565 if (cmd_sts & BUFFER_OWNED_BY_DMA)
566 break;
567 rmb();
568
569 skb = rxq->rx_skb[rxq->rx_curr_desc];
570 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
571
572 rxq->rx_curr_desc++;
573 if (rxq->rx_curr_desc == rxq->rx_ring_size)
574 rxq->rx_curr_desc = 0;
575
576 dma_unmap_single(NULL, rx_desc->buf_ptr,
577 rx_desc->buf_size, DMA_FROM_DEVICE);
578 rxq->rx_desc_count--;
579 rx++;
580
581 mp->work_rx_refill |= 1 << rxq->index;
582
583 byte_cnt = rx_desc->byte_cnt;
584
585 /*
586 * Update statistics.
587 *
588 * Note that the descriptor byte count includes 2 dummy
589 * bytes automatically inserted by the hardware at the
590 * start of the packet (which we don't count), and a 4
591 * byte CRC at the end of the packet (which we do count).
592 */
593 stats->rx_packets++;
594 stats->rx_bytes += byte_cnt - 2;
595
596 /*
597 * In case we received a packet without first / last bits
598 * on, or the error summary bit is set, the packet needs
599 * to be dropped.
600 */
601 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
602 != (RX_FIRST_DESC | RX_LAST_DESC))
603 goto err;
604
605 /*
606 * The -4 is for the CRC in the trailer of the
607 * received packet
608 */
609 skb_put(skb, byte_cnt - 2 - 4);
610
611 if (cmd_sts & LAYER_4_CHECKSUM_OK)
612 skb->ip_summed = CHECKSUM_UNNECESSARY;
613 skb->protocol = eth_type_trans(skb, mp->dev);
614
615 #ifdef CONFIG_MV643XX_ETH_LRO
616 if (skb->dev->features & NETIF_F_LRO &&
617 skb->ip_summed == CHECKSUM_UNNECESSARY) {
618 lro_receive_skb(&rxq->lro_mgr, skb, (void *)cmd_sts);
619 lro_flush_needed = 1;
620 } else
621 #endif
622 netif_receive_skb(skb);
623
624 continue;
625
626 err:
627 stats->rx_dropped++;
628
629 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
630 (RX_FIRST_DESC | RX_LAST_DESC)) {
631 if (net_ratelimit())
632 dev_printk(KERN_ERR, &mp->dev->dev,
633 "received packet spanning "
634 "multiple descriptors\n");
635 }
636
637 if (cmd_sts & ERROR_SUMMARY)
638 stats->rx_errors++;
639
640 dev_kfree_skb(skb);
641 }
642
643 #ifdef CONFIG_MV643XX_ETH_LRO
644 if (lro_flush_needed)
645 lro_flush_all(&rxq->lro_mgr);
646 #endif
647
648 if (rx < budget)
649 mp->work_rx &= ~(1 << rxq->index);
650
651 return rx;
652 }
653
654 static int rxq_refill(struct rx_queue *rxq, int budget)
655 {
656 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
657 int refilled;
658
659 refilled = 0;
660 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
661 struct sk_buff *skb;
662 int unaligned;
663 int rx;
664 struct rx_desc *rx_desc;
665
666 skb = __skb_dequeue(&mp->rx_recycle);
667 if (skb == NULL)
668 skb = dev_alloc_skb(mp->skb_size +
669 dma_get_cache_alignment() - 1);
670
671 if (skb == NULL) {
672 mp->work_rx_oom |= 1 << rxq->index;
673 goto oom;
674 }
675
676 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
677 if (unaligned)
678 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
679
680 refilled++;
681 rxq->rx_desc_count++;
682
683 rx = rxq->rx_used_desc++;
684 if (rxq->rx_used_desc == rxq->rx_ring_size)
685 rxq->rx_used_desc = 0;
686
687 rx_desc = rxq->rx_desc_area + rx;
688
689 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
690 mp->skb_size, DMA_FROM_DEVICE);
691 rx_desc->buf_size = mp->skb_size;
692 rxq->rx_skb[rx] = skb;
693 wmb();
694 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
695 wmb();
696
697 /*
698 * The hardware automatically prepends 2 bytes of
699 * dummy data to each received packet, so that the
700 * IP header ends up 16-byte aligned.
701 */
702 skb_reserve(skb, 2);
703 }
704
705 if (refilled < budget)
706 mp->work_rx_refill &= ~(1 << rxq->index);
707
708 oom:
709 return refilled;
710 }
711
712
713 /* tx ***********************************************************************/
714 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
715 {
716 int frag;
717
718 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
719 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
720 if (fragp->size <= 8 && fragp->page_offset & 7)
721 return 1;
722 }
723
724 return 0;
725 }
726
727 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
728 {
729 int nr_frags = skb_shinfo(skb)->nr_frags;
730 int frag;
731
732 for (frag = 0; frag < nr_frags; frag++) {
733 skb_frag_t *this_frag;
734 int tx_index;
735 struct tx_desc *desc;
736
737 this_frag = &skb_shinfo(skb)->frags[frag];
738 tx_index = txq->tx_curr_desc++;
739 if (txq->tx_curr_desc == txq->tx_ring_size)
740 txq->tx_curr_desc = 0;
741 desc = &txq->tx_desc_area[tx_index];
742
743 /*
744 * The last fragment will generate an interrupt
745 * which will free the skb on TX completion.
746 */
747 if (frag == nr_frags - 1) {
748 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
749 ZERO_PADDING | TX_LAST_DESC |
750 TX_ENABLE_INTERRUPT;
751 } else {
752 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
753 }
754
755 desc->l4i_chk = 0;
756 desc->byte_cnt = this_frag->size;
757 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
758 this_frag->page_offset,
759 this_frag->size,
760 DMA_TO_DEVICE);
761 }
762 }
763
764 static inline __be16 sum16_as_be(__sum16 sum)
765 {
766 return (__force __be16)sum;
767 }
768
769 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
770 {
771 struct mv643xx_eth_private *mp = txq_to_mp(txq);
772 int nr_frags = skb_shinfo(skb)->nr_frags;
773 int tx_index;
774 struct tx_desc *desc;
775 u32 cmd_sts;
776 u16 l4i_chk;
777 int length;
778
779 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
780 l4i_chk = 0;
781
782 if (skb->ip_summed == CHECKSUM_PARTIAL) {
783 int tag_bytes;
784
785 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
786 skb->protocol != htons(ETH_P_8021Q));
787
788 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
789 if (unlikely(tag_bytes & ~12)) {
790 if (skb_checksum_help(skb) == 0)
791 goto no_csum;
792 kfree_skb(skb);
793 return 1;
794 }
795
796 if (tag_bytes & 4)
797 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
798 if (tag_bytes & 8)
799 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
800
801 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
802 GEN_IP_V4_CHECKSUM |
803 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
804
805 switch (ip_hdr(skb)->protocol) {
806 case IPPROTO_UDP:
807 cmd_sts |= UDP_FRAME;
808 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
809 break;
810 case IPPROTO_TCP:
811 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
812 break;
813 default:
814 BUG();
815 }
816 } else {
817 no_csum:
818 /* Errata BTS #50, IHL must be 5 if no HW checksum */
819 cmd_sts |= 5 << TX_IHL_SHIFT;
820 }
821
822 tx_index = txq->tx_curr_desc++;
823 if (txq->tx_curr_desc == txq->tx_ring_size)
824 txq->tx_curr_desc = 0;
825 desc = &txq->tx_desc_area[tx_index];
826
827 if (nr_frags) {
828 txq_submit_frag_skb(txq, skb);
829 length = skb_headlen(skb);
830 } else {
831 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
832 length = skb->len;
833 }
834
835 desc->l4i_chk = l4i_chk;
836 desc->byte_cnt = length;
837 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
838
839 __skb_queue_tail(&txq->tx_skb, skb);
840
841 /* ensure all other descriptors are written before first cmd_sts */
842 wmb();
843 desc->cmd_sts = cmd_sts;
844
845 /* clear TX_END status */
846 mp->work_tx_end &= ~(1 << txq->index);
847
848 /* ensure all descriptors are written before poking hardware */
849 wmb();
850 txq_enable(txq);
851
852 txq->tx_desc_count += nr_frags + 1;
853
854 return 0;
855 }
856
857 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
858 {
859 struct mv643xx_eth_private *mp = netdev_priv(dev);
860 int queue;
861 struct tx_queue *txq;
862 struct netdev_queue *nq;
863
864 queue = skb_get_queue_mapping(skb);
865 txq = mp->txq + queue;
866 nq = netdev_get_tx_queue(dev, queue);
867
868 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
869 txq->tx_dropped++;
870 dev_printk(KERN_DEBUG, &dev->dev,
871 "failed to linearize skb with tiny "
872 "unaligned fragment\n");
873 return NETDEV_TX_BUSY;
874 }
875
876 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
877 if (net_ratelimit())
878 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
879 kfree_skb(skb);
880 return NETDEV_TX_OK;
881 }
882
883 if (!txq_submit_skb(txq, skb)) {
884 int entries_left;
885
886 txq->tx_bytes += skb->len;
887 txq->tx_packets++;
888 dev->trans_start = jiffies;
889
890 entries_left = txq->tx_ring_size - txq->tx_desc_count;
891 if (entries_left < MAX_SKB_FRAGS + 1)
892 netif_tx_stop_queue(nq);
893 }
894
895 return NETDEV_TX_OK;
896 }
897
898
899 /* tx napi ******************************************************************/
900 static void txq_kick(struct tx_queue *txq)
901 {
902 struct mv643xx_eth_private *mp = txq_to_mp(txq);
903 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
904 u32 hw_desc_ptr;
905 u32 expected_ptr;
906
907 __netif_tx_lock(nq, smp_processor_id());
908
909 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
910 goto out;
911
912 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
913 expected_ptr = (u32)txq->tx_desc_dma +
914 txq->tx_curr_desc * sizeof(struct tx_desc);
915
916 if (hw_desc_ptr != expected_ptr)
917 txq_enable(txq);
918
919 out:
920 __netif_tx_unlock(nq);
921
922 mp->work_tx_end &= ~(1 << txq->index);
923 }
924
925 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
926 {
927 struct mv643xx_eth_private *mp = txq_to_mp(txq);
928 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
929 int reclaimed;
930
931 __netif_tx_lock(nq, smp_processor_id());
932
933 reclaimed = 0;
934 while (reclaimed < budget && txq->tx_desc_count > 0) {
935 int tx_index;
936 struct tx_desc *desc;
937 u32 cmd_sts;
938 struct sk_buff *skb;
939
940 tx_index = txq->tx_used_desc;
941 desc = &txq->tx_desc_area[tx_index];
942 cmd_sts = desc->cmd_sts;
943
944 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
945 if (!force)
946 break;
947 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
948 }
949
950 txq->tx_used_desc = tx_index + 1;
951 if (txq->tx_used_desc == txq->tx_ring_size)
952 txq->tx_used_desc = 0;
953
954 reclaimed++;
955 txq->tx_desc_count--;
956
957 skb = NULL;
958 if (cmd_sts & TX_LAST_DESC)
959 skb = __skb_dequeue(&txq->tx_skb);
960
961 if (cmd_sts & ERROR_SUMMARY) {
962 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
963 mp->dev->stats.tx_errors++;
964 }
965
966 if (cmd_sts & TX_FIRST_DESC) {
967 dma_unmap_single(NULL, desc->buf_ptr,
968 desc->byte_cnt, DMA_TO_DEVICE);
969 } else {
970 dma_unmap_page(NULL, desc->buf_ptr,
971 desc->byte_cnt, DMA_TO_DEVICE);
972 }
973
974 if (skb != NULL) {
975 if (skb_queue_len(&mp->rx_recycle) <
976 mp->rx_ring_size &&
977 skb_recycle_check(skb, mp->skb_size +
978 dma_get_cache_alignment() - 1))
979 __skb_queue_head(&mp->rx_recycle, skb);
980 else
981 dev_kfree_skb(skb);
982 }
983 }
984
985 __netif_tx_unlock(nq);
986
987 if (reclaimed < budget)
988 mp->work_tx &= ~(1 << txq->index);
989
990 return reclaimed;
991 }
992
993
994 /* tx rate control **********************************************************/
995 /*
996 * Set total maximum TX rate (shared by all TX queues for this port)
997 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
998 */
999 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
1000 {
1001 int token_rate;
1002 int mtu;
1003 int bucket_size;
1004
1005 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1006 if (token_rate > 1023)
1007 token_rate = 1023;
1008
1009 mtu = (mp->dev->mtu + 255) >> 8;
1010 if (mtu > 63)
1011 mtu = 63;
1012
1013 bucket_size = (burst + 255) >> 8;
1014 if (bucket_size > 65535)
1015 bucket_size = 65535;
1016
1017 switch (mp->shared->tx_bw_control) {
1018 case TX_BW_CONTROL_OLD_LAYOUT:
1019 wrlp(mp, TX_BW_RATE, token_rate);
1020 wrlp(mp, TX_BW_MTU, mtu);
1021 wrlp(mp, TX_BW_BURST, bucket_size);
1022 break;
1023 case TX_BW_CONTROL_NEW_LAYOUT:
1024 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
1025 wrlp(mp, TX_BW_MTU_MOVED, mtu);
1026 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
1027 break;
1028 }
1029 }
1030
1031 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
1032 {
1033 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1034 int token_rate;
1035 int bucket_size;
1036
1037 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
1038 if (token_rate > 1023)
1039 token_rate = 1023;
1040
1041 bucket_size = (burst + 255) >> 8;
1042 if (bucket_size > 65535)
1043 bucket_size = 65535;
1044
1045 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
1046 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
1047 }
1048
1049 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
1050 {
1051 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1052 int off;
1053 u32 val;
1054
1055 /*
1056 * Turn on fixed priority mode.
1057 */
1058 off = 0;
1059 switch (mp->shared->tx_bw_control) {
1060 case TX_BW_CONTROL_OLD_LAYOUT:
1061 off = TXQ_FIX_PRIO_CONF;
1062 break;
1063 case TX_BW_CONTROL_NEW_LAYOUT:
1064 off = TXQ_FIX_PRIO_CONF_MOVED;
1065 break;
1066 }
1067
1068 if (off) {
1069 val = rdlp(mp, off);
1070 val |= 1 << txq->index;
1071 wrlp(mp, off, val);
1072 }
1073 }
1074
1075 static void txq_set_wrr(struct tx_queue *txq, int weight)
1076 {
1077 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1078 int off;
1079 u32 val;
1080
1081 /*
1082 * Turn off fixed priority mode.
1083 */
1084 off = 0;
1085 switch (mp->shared->tx_bw_control) {
1086 case TX_BW_CONTROL_OLD_LAYOUT:
1087 off = TXQ_FIX_PRIO_CONF;
1088 break;
1089 case TX_BW_CONTROL_NEW_LAYOUT:
1090 off = TXQ_FIX_PRIO_CONF_MOVED;
1091 break;
1092 }
1093
1094 if (off) {
1095 val = rdlp(mp, off);
1096 val &= ~(1 << txq->index);
1097 wrlp(mp, off, val);
1098
1099 /*
1100 * Configure WRR weight for this queue.
1101 */
1102
1103 val = rdlp(mp, off);
1104 val = (val & ~0xff) | (weight & 0xff);
1105 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1106 }
1107 }
1108
1109
1110 /* mii management interface *************************************************/
1111 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1112 {
1113 struct mv643xx_eth_shared_private *msp = dev_id;
1114
1115 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1116 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1117 wake_up(&msp->smi_busy_wait);
1118 return IRQ_HANDLED;
1119 }
1120
1121 return IRQ_NONE;
1122 }
1123
1124 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1125 {
1126 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1127 }
1128
1129 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1130 {
1131 if (msp->err_interrupt == NO_IRQ) {
1132 int i;
1133
1134 for (i = 0; !smi_is_done(msp); i++) {
1135 if (i == 10)
1136 return -ETIMEDOUT;
1137 msleep(10);
1138 }
1139
1140 return 0;
1141 }
1142
1143 if (!smi_is_done(msp)) {
1144 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1145 msecs_to_jiffies(100));
1146 if (!smi_is_done(msp))
1147 return -ETIMEDOUT;
1148 }
1149
1150 return 0;
1151 }
1152
1153 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1154 {
1155 struct mv643xx_eth_shared_private *msp = bus->priv;
1156 void __iomem *smi_reg = msp->base + SMI_REG;
1157 int ret;
1158
1159 if (smi_wait_ready(msp)) {
1160 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1161 return -ETIMEDOUT;
1162 }
1163
1164 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1165
1166 if (smi_wait_ready(msp)) {
1167 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1168 return -ETIMEDOUT;
1169 }
1170
1171 ret = readl(smi_reg);
1172 if (!(ret & SMI_READ_VALID)) {
1173 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1174 return -ENODEV;
1175 }
1176
1177 return ret & 0xffff;
1178 }
1179
1180 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1181 {
1182 struct mv643xx_eth_shared_private *msp = bus->priv;
1183 void __iomem *smi_reg = msp->base + SMI_REG;
1184
1185 if (smi_wait_ready(msp)) {
1186 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1187 return -ETIMEDOUT;
1188 }
1189
1190 writel(SMI_OPCODE_WRITE | (reg << 21) |
1191 (addr << 16) | (val & 0xffff), smi_reg);
1192
1193 if (smi_wait_ready(msp)) {
1194 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1195 return -ETIMEDOUT;
1196 }
1197
1198 return 0;
1199 }
1200
1201
1202 /* statistics ***************************************************************/
1203 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1204 {
1205 struct mv643xx_eth_private *mp = netdev_priv(dev);
1206 struct net_device_stats *stats = &dev->stats;
1207 unsigned long tx_packets = 0;
1208 unsigned long tx_bytes = 0;
1209 unsigned long tx_dropped = 0;
1210 int i;
1211
1212 for (i = 0; i < mp->txq_count; i++) {
1213 struct tx_queue *txq = mp->txq + i;
1214
1215 tx_packets += txq->tx_packets;
1216 tx_bytes += txq->tx_bytes;
1217 tx_dropped += txq->tx_dropped;
1218 }
1219
1220 stats->tx_packets = tx_packets;
1221 stats->tx_bytes = tx_bytes;
1222 stats->tx_dropped = tx_dropped;
1223
1224 return stats;
1225 }
1226
1227 static void mv643xx_eth_grab_lro_stats(struct mv643xx_eth_private *mp)
1228 {
1229 u32 lro_aggregated = 0;
1230 u32 lro_flushed = 0;
1231 u32 lro_no_desc = 0;
1232 int i;
1233
1234 #ifdef CONFIG_MV643XX_ETH_LRO
1235 for (i = 0; i < mp->rxq_count; i++) {
1236 struct rx_queue *rxq = mp->rxq + i;
1237
1238 lro_aggregated += rxq->lro_mgr.stats.aggregated;
1239 lro_flushed += rxq->lro_mgr.stats.flushed;
1240 lro_no_desc += rxq->lro_mgr.stats.no_desc;
1241 }
1242 #endif
1243
1244 mp->lro_counters.lro_aggregated = lro_aggregated;
1245 mp->lro_counters.lro_flushed = lro_flushed;
1246 mp->lro_counters.lro_no_desc = lro_no_desc;
1247 }
1248
1249 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1250 {
1251 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1252 }
1253
1254 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1255 {
1256 int i;
1257
1258 for (i = 0; i < 0x80; i += 4)
1259 mib_read(mp, i);
1260 }
1261
1262 static void mib_counters_update(struct mv643xx_eth_private *mp)
1263 {
1264 struct mib_counters *p = &mp->mib_counters;
1265
1266 spin_lock(&mp->mib_counters_lock);
1267 p->good_octets_received += mib_read(mp, 0x00);
1268 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1269 p->bad_octets_received += mib_read(mp, 0x08);
1270 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1271 p->good_frames_received += mib_read(mp, 0x10);
1272 p->bad_frames_received += mib_read(mp, 0x14);
1273 p->broadcast_frames_received += mib_read(mp, 0x18);
1274 p->multicast_frames_received += mib_read(mp, 0x1c);
1275 p->frames_64_octets += mib_read(mp, 0x20);
1276 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1277 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1278 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1279 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1280 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1281 p->good_octets_sent += mib_read(mp, 0x38);
1282 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1283 p->good_frames_sent += mib_read(mp, 0x40);
1284 p->excessive_collision += mib_read(mp, 0x44);
1285 p->multicast_frames_sent += mib_read(mp, 0x48);
1286 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1287 p->unrec_mac_control_received += mib_read(mp, 0x50);
1288 p->fc_sent += mib_read(mp, 0x54);
1289 p->good_fc_received += mib_read(mp, 0x58);
1290 p->bad_fc_received += mib_read(mp, 0x5c);
1291 p->undersize_received += mib_read(mp, 0x60);
1292 p->fragments_received += mib_read(mp, 0x64);
1293 p->oversize_received += mib_read(mp, 0x68);
1294 p->jabber_received += mib_read(mp, 0x6c);
1295 p->mac_receive_error += mib_read(mp, 0x70);
1296 p->bad_crc_event += mib_read(mp, 0x74);
1297 p->collision += mib_read(mp, 0x78);
1298 p->late_collision += mib_read(mp, 0x7c);
1299 spin_unlock(&mp->mib_counters_lock);
1300
1301 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1302 }
1303
1304 static void mib_counters_timer_wrapper(unsigned long _mp)
1305 {
1306 struct mv643xx_eth_private *mp = (void *)_mp;
1307
1308 mib_counters_update(mp);
1309 }
1310
1311
1312 /* interrupt coalescing *****************************************************/
1313 /*
1314 * Hardware coalescing parameters are set in units of 64 t_clk
1315 * cycles. I.e.:
1316 *
1317 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1318 *
1319 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1320 *
1321 * In the ->set*() methods, we round the computed register value
1322 * to the nearest integer.
1323 */
1324 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1325 {
1326 u32 val = rdlp(mp, SDMA_CONFIG);
1327 u64 temp;
1328
1329 if (mp->shared->extended_rx_coal_limit)
1330 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1331 else
1332 temp = (val & 0x003fff00) >> 8;
1333
1334 temp *= 64000000;
1335 do_div(temp, mp->shared->t_clk);
1336
1337 return (unsigned int)temp;
1338 }
1339
1340 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1341 {
1342 u64 temp;
1343 u32 val;
1344
1345 temp = (u64)usec * mp->shared->t_clk;
1346 temp += 31999999;
1347 do_div(temp, 64000000);
1348
1349 val = rdlp(mp, SDMA_CONFIG);
1350 if (mp->shared->extended_rx_coal_limit) {
1351 if (temp > 0xffff)
1352 temp = 0xffff;
1353 val &= ~0x023fff80;
1354 val |= (temp & 0x8000) << 10;
1355 val |= (temp & 0x7fff) << 7;
1356 } else {
1357 if (temp > 0x3fff)
1358 temp = 0x3fff;
1359 val &= ~0x003fff00;
1360 val |= (temp & 0x3fff) << 8;
1361 }
1362 wrlp(mp, SDMA_CONFIG, val);
1363 }
1364
1365 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1366 {
1367 u64 temp;
1368
1369 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1370 temp *= 64000000;
1371 do_div(temp, mp->shared->t_clk);
1372
1373 return (unsigned int)temp;
1374 }
1375
1376 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1377 {
1378 u64 temp;
1379
1380 temp = (u64)usec * mp->shared->t_clk;
1381 temp += 31999999;
1382 do_div(temp, 64000000);
1383
1384 if (temp > 0x3fff)
1385 temp = 0x3fff;
1386
1387 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1388 }
1389
1390
1391 /* ethtool ******************************************************************/
1392 struct mv643xx_eth_stats {
1393 char stat_string[ETH_GSTRING_LEN];
1394 int sizeof_stat;
1395 int netdev_off;
1396 int mp_off;
1397 };
1398
1399 #define SSTAT(m) \
1400 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1401 offsetof(struct net_device, stats.m), -1 }
1402
1403 #define MIBSTAT(m) \
1404 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1405 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1406
1407 #define LROSTAT(m) \
1408 { #m, FIELD_SIZEOF(struct lro_counters, m), \
1409 -1, offsetof(struct mv643xx_eth_private, lro_counters.m) }
1410
1411 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1412 SSTAT(rx_packets),
1413 SSTAT(tx_packets),
1414 SSTAT(rx_bytes),
1415 SSTAT(tx_bytes),
1416 SSTAT(rx_errors),
1417 SSTAT(tx_errors),
1418 SSTAT(rx_dropped),
1419 SSTAT(tx_dropped),
1420 MIBSTAT(good_octets_received),
1421 MIBSTAT(bad_octets_received),
1422 MIBSTAT(internal_mac_transmit_err),
1423 MIBSTAT(good_frames_received),
1424 MIBSTAT(bad_frames_received),
1425 MIBSTAT(broadcast_frames_received),
1426 MIBSTAT(multicast_frames_received),
1427 MIBSTAT(frames_64_octets),
1428 MIBSTAT(frames_65_to_127_octets),
1429 MIBSTAT(frames_128_to_255_octets),
1430 MIBSTAT(frames_256_to_511_octets),
1431 MIBSTAT(frames_512_to_1023_octets),
1432 MIBSTAT(frames_1024_to_max_octets),
1433 MIBSTAT(good_octets_sent),
1434 MIBSTAT(good_frames_sent),
1435 MIBSTAT(excessive_collision),
1436 MIBSTAT(multicast_frames_sent),
1437 MIBSTAT(broadcast_frames_sent),
1438 MIBSTAT(unrec_mac_control_received),
1439 MIBSTAT(fc_sent),
1440 MIBSTAT(good_fc_received),
1441 MIBSTAT(bad_fc_received),
1442 MIBSTAT(undersize_received),
1443 MIBSTAT(fragments_received),
1444 MIBSTAT(oversize_received),
1445 MIBSTAT(jabber_received),
1446 MIBSTAT(mac_receive_error),
1447 MIBSTAT(bad_crc_event),
1448 MIBSTAT(collision),
1449 MIBSTAT(late_collision),
1450 LROSTAT(lro_aggregated),
1451 LROSTAT(lro_flushed),
1452 LROSTAT(lro_no_desc),
1453 };
1454
1455 static int
1456 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1457 struct ethtool_cmd *cmd)
1458 {
1459 int err;
1460
1461 err = phy_read_status(mp->phy);
1462 if (err == 0)
1463 err = phy_ethtool_gset(mp->phy, cmd);
1464
1465 /*
1466 * The MAC does not support 1000baseT_Half.
1467 */
1468 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1469 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1470
1471 return err;
1472 }
1473
1474 static int
1475 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1476 struct ethtool_cmd *cmd)
1477 {
1478 u32 port_status;
1479
1480 port_status = rdlp(mp, PORT_STATUS);
1481
1482 cmd->supported = SUPPORTED_MII;
1483 cmd->advertising = ADVERTISED_MII;
1484 switch (port_status & PORT_SPEED_MASK) {
1485 case PORT_SPEED_10:
1486 cmd->speed = SPEED_10;
1487 break;
1488 case PORT_SPEED_100:
1489 cmd->speed = SPEED_100;
1490 break;
1491 case PORT_SPEED_1000:
1492 cmd->speed = SPEED_1000;
1493 break;
1494 default:
1495 cmd->speed = -1;
1496 break;
1497 }
1498 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1499 cmd->port = PORT_MII;
1500 cmd->phy_address = 0;
1501 cmd->transceiver = XCVR_INTERNAL;
1502 cmd->autoneg = AUTONEG_DISABLE;
1503 cmd->maxtxpkt = 1;
1504 cmd->maxrxpkt = 1;
1505
1506 return 0;
1507 }
1508
1509 static int
1510 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1511 {
1512 struct mv643xx_eth_private *mp = netdev_priv(dev);
1513
1514 if (mp->phy != NULL)
1515 return mv643xx_eth_get_settings_phy(mp, cmd);
1516 else
1517 return mv643xx_eth_get_settings_phyless(mp, cmd);
1518 }
1519
1520 static int
1521 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1522 {
1523 struct mv643xx_eth_private *mp = netdev_priv(dev);
1524
1525 if (mp->phy == NULL)
1526 return -EINVAL;
1527
1528 /*
1529 * The MAC does not support 1000baseT_Half.
1530 */
1531 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1532
1533 return phy_ethtool_sset(mp->phy, cmd);
1534 }
1535
1536 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1537 struct ethtool_drvinfo *drvinfo)
1538 {
1539 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1540 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1541 strncpy(drvinfo->fw_version, "N/A", 32);
1542 strncpy(drvinfo->bus_info, "platform", 32);
1543 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1544 }
1545
1546 static int mv643xx_eth_nway_reset(struct net_device *dev)
1547 {
1548 struct mv643xx_eth_private *mp = netdev_priv(dev);
1549
1550 if (mp->phy == NULL)
1551 return -EINVAL;
1552
1553 return genphy_restart_aneg(mp->phy);
1554 }
1555
1556 static u32 mv643xx_eth_get_link(struct net_device *dev)
1557 {
1558 return !!netif_carrier_ok(dev);
1559 }
1560
1561 static int
1562 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1563 {
1564 struct mv643xx_eth_private *mp = netdev_priv(dev);
1565
1566 ec->rx_coalesce_usecs = get_rx_coal(mp);
1567 ec->tx_coalesce_usecs = get_tx_coal(mp);
1568
1569 return 0;
1570 }
1571
1572 static int
1573 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1574 {
1575 struct mv643xx_eth_private *mp = netdev_priv(dev);
1576
1577 set_rx_coal(mp, ec->rx_coalesce_usecs);
1578 set_tx_coal(mp, ec->tx_coalesce_usecs);
1579
1580 return 0;
1581 }
1582
1583 static void
1584 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1585 {
1586 struct mv643xx_eth_private *mp = netdev_priv(dev);
1587
1588 er->rx_max_pending = 4096;
1589 er->tx_max_pending = 4096;
1590 er->rx_mini_max_pending = 0;
1591 er->rx_jumbo_max_pending = 0;
1592
1593 er->rx_pending = mp->rx_ring_size;
1594 er->tx_pending = mp->tx_ring_size;
1595 er->rx_mini_pending = 0;
1596 er->rx_jumbo_pending = 0;
1597 }
1598
1599 static int
1600 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1601 {
1602 struct mv643xx_eth_private *mp = netdev_priv(dev);
1603
1604 if (er->rx_mini_pending || er->rx_jumbo_pending)
1605 return -EINVAL;
1606
1607 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1608 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1609
1610 if (netif_running(dev)) {
1611 mv643xx_eth_stop(dev);
1612 if (mv643xx_eth_open(dev)) {
1613 dev_printk(KERN_ERR, &dev->dev,
1614 "fatal error on re-opening device after "
1615 "ring param change\n");
1616 return -ENOMEM;
1617 }
1618 }
1619
1620 return 0;
1621 }
1622
1623 static u32
1624 mv643xx_eth_get_rx_csum(struct net_device *dev)
1625 {
1626 struct mv643xx_eth_private *mp = netdev_priv(dev);
1627
1628 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1629 }
1630
1631 static int
1632 mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1633 {
1634 struct mv643xx_eth_private *mp = netdev_priv(dev);
1635
1636 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1637
1638 return 0;
1639 }
1640
1641 static void mv643xx_eth_get_strings(struct net_device *dev,
1642 uint32_t stringset, uint8_t *data)
1643 {
1644 int i;
1645
1646 if (stringset == ETH_SS_STATS) {
1647 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1648 memcpy(data + i * ETH_GSTRING_LEN,
1649 mv643xx_eth_stats[i].stat_string,
1650 ETH_GSTRING_LEN);
1651 }
1652 }
1653 }
1654
1655 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1656 struct ethtool_stats *stats,
1657 uint64_t *data)
1658 {
1659 struct mv643xx_eth_private *mp = netdev_priv(dev);
1660 int i;
1661
1662 mv643xx_eth_get_stats(dev);
1663 mib_counters_update(mp);
1664 mv643xx_eth_grab_lro_stats(mp);
1665
1666 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1667 const struct mv643xx_eth_stats *stat;
1668 void *p;
1669
1670 stat = mv643xx_eth_stats + i;
1671
1672 if (stat->netdev_off >= 0)
1673 p = ((void *)mp->dev) + stat->netdev_off;
1674 else
1675 p = ((void *)mp) + stat->mp_off;
1676
1677 data[i] = (stat->sizeof_stat == 8) ?
1678 *(uint64_t *)p : *(uint32_t *)p;
1679 }
1680 }
1681
1682 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1683 {
1684 if (sset == ETH_SS_STATS)
1685 return ARRAY_SIZE(mv643xx_eth_stats);
1686
1687 return -EOPNOTSUPP;
1688 }
1689
1690 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1691 .get_settings = mv643xx_eth_get_settings,
1692 .set_settings = mv643xx_eth_set_settings,
1693 .get_drvinfo = mv643xx_eth_get_drvinfo,
1694 .nway_reset = mv643xx_eth_nway_reset,
1695 .get_link = mv643xx_eth_get_link,
1696 .get_coalesce = mv643xx_eth_get_coalesce,
1697 .set_coalesce = mv643xx_eth_set_coalesce,
1698 .get_ringparam = mv643xx_eth_get_ringparam,
1699 .set_ringparam = mv643xx_eth_set_ringparam,
1700 .get_rx_csum = mv643xx_eth_get_rx_csum,
1701 .set_rx_csum = mv643xx_eth_set_rx_csum,
1702 .set_tx_csum = ethtool_op_set_tx_csum,
1703 .set_sg = ethtool_op_set_sg,
1704 .get_strings = mv643xx_eth_get_strings,
1705 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1706 .get_flags = ethtool_op_get_flags,
1707 .set_flags = ethtool_op_set_flags,
1708 .get_sset_count = mv643xx_eth_get_sset_count,
1709 };
1710
1711
1712 /* address handling *********************************************************/
1713 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1714 {
1715 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1716 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1717
1718 addr[0] = (mac_h >> 24) & 0xff;
1719 addr[1] = (mac_h >> 16) & 0xff;
1720 addr[2] = (mac_h >> 8) & 0xff;
1721 addr[3] = mac_h & 0xff;
1722 addr[4] = (mac_l >> 8) & 0xff;
1723 addr[5] = mac_l & 0xff;
1724 }
1725
1726 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1727 {
1728 wrlp(mp, MAC_ADDR_HIGH,
1729 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1730 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1731 }
1732
1733 static u32 uc_addr_filter_mask(struct net_device *dev)
1734 {
1735 struct dev_addr_list *uc_ptr;
1736 u32 nibbles;
1737
1738 if (dev->flags & IFF_PROMISC)
1739 return 0;
1740
1741 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1742 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1743 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1744 return 0;
1745 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1746 return 0;
1747
1748 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1749 }
1750
1751 return nibbles;
1752 }
1753
1754 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1755 {
1756 struct mv643xx_eth_private *mp = netdev_priv(dev);
1757 u32 port_config;
1758 u32 nibbles;
1759 int i;
1760
1761 uc_addr_set(mp, dev->dev_addr);
1762
1763 port_config = rdlp(mp, PORT_CONFIG);
1764 nibbles = uc_addr_filter_mask(dev);
1765 if (!nibbles) {
1766 port_config |= UNICAST_PROMISCUOUS_MODE;
1767 wrlp(mp, PORT_CONFIG, port_config);
1768 return;
1769 }
1770
1771 for (i = 0; i < 16; i += 4) {
1772 int off = UNICAST_TABLE(mp->port_num) + i;
1773 u32 v;
1774
1775 v = 0;
1776 if (nibbles & 1)
1777 v |= 0x00000001;
1778 if (nibbles & 2)
1779 v |= 0x00000100;
1780 if (nibbles & 4)
1781 v |= 0x00010000;
1782 if (nibbles & 8)
1783 v |= 0x01000000;
1784 nibbles >>= 4;
1785
1786 wrl(mp, off, v);
1787 }
1788
1789 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1790 wrlp(mp, PORT_CONFIG, port_config);
1791 }
1792
1793 static int addr_crc(unsigned char *addr)
1794 {
1795 int crc = 0;
1796 int i;
1797
1798 for (i = 0; i < 6; i++) {
1799 int j;
1800
1801 crc = (crc ^ addr[i]) << 8;
1802 for (j = 7; j >= 0; j--) {
1803 if (crc & (0x100 << j))
1804 crc ^= 0x107 << j;
1805 }
1806 }
1807
1808 return crc;
1809 }
1810
1811 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1812 {
1813 struct mv643xx_eth_private *mp = netdev_priv(dev);
1814 u32 *mc_spec;
1815 u32 *mc_other;
1816 struct dev_addr_list *addr;
1817 int i;
1818
1819 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1820 int port_num;
1821 u32 accept;
1822 int i;
1823
1824 oom:
1825 port_num = mp->port_num;
1826 accept = 0x01010101;
1827 for (i = 0; i < 0x100; i += 4) {
1828 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1829 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1830 }
1831 return;
1832 }
1833
1834 mc_spec = kmalloc(0x200, GFP_KERNEL);
1835 if (mc_spec == NULL)
1836 goto oom;
1837 mc_other = mc_spec + (0x100 >> 2);
1838
1839 memset(mc_spec, 0, 0x100);
1840 memset(mc_other, 0, 0x100);
1841
1842 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1843 u8 *a = addr->da_addr;
1844 u32 *table;
1845 int entry;
1846
1847 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1848 table = mc_spec;
1849 entry = a[5];
1850 } else {
1851 table = mc_other;
1852 entry = addr_crc(a);
1853 }
1854
1855 table[entry >> 2] |= 1 << (8 * (entry & 3));
1856 }
1857
1858 for (i = 0; i < 0x100; i += 4) {
1859 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1860 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1861 }
1862
1863 kfree(mc_spec);
1864 }
1865
1866 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1867 {
1868 mv643xx_eth_program_unicast_filter(dev);
1869 mv643xx_eth_program_multicast_filter(dev);
1870 }
1871
1872 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1873 {
1874 struct sockaddr *sa = addr;
1875
1876 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1877
1878 netif_addr_lock_bh(dev);
1879 mv643xx_eth_program_unicast_filter(dev);
1880 netif_addr_unlock_bh(dev);
1881
1882 return 0;
1883 }
1884
1885
1886 /* rx/tx queue initialisation ***********************************************/
1887 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1888 {
1889 struct rx_queue *rxq = mp->rxq + index;
1890 struct rx_desc *rx_desc;
1891 int size;
1892 int i;
1893
1894 rxq->index = index;
1895
1896 rxq->rx_ring_size = mp->rx_ring_size;
1897
1898 rxq->rx_desc_count = 0;
1899 rxq->rx_curr_desc = 0;
1900 rxq->rx_used_desc = 0;
1901
1902 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1903
1904 if (index == 0 && size <= mp->rx_desc_sram_size) {
1905 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1906 mp->rx_desc_sram_size);
1907 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1908 } else {
1909 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1910 &rxq->rx_desc_dma,
1911 GFP_KERNEL);
1912 }
1913
1914 if (rxq->rx_desc_area == NULL) {
1915 dev_printk(KERN_ERR, &mp->dev->dev,
1916 "can't allocate rx ring (%d bytes)\n", size);
1917 goto out;
1918 }
1919 memset(rxq->rx_desc_area, 0, size);
1920
1921 rxq->rx_desc_area_size = size;
1922 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1923 GFP_KERNEL);
1924 if (rxq->rx_skb == NULL) {
1925 dev_printk(KERN_ERR, &mp->dev->dev,
1926 "can't allocate rx skb ring\n");
1927 goto out_free;
1928 }
1929
1930 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1931 for (i = 0; i < rxq->rx_ring_size; i++) {
1932 int nexti;
1933
1934 nexti = i + 1;
1935 if (nexti == rxq->rx_ring_size)
1936 nexti = 0;
1937
1938 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1939 nexti * sizeof(struct rx_desc);
1940 }
1941
1942 #ifdef CONFIG_MV643XX_ETH_LRO
1943 rxq->lro_mgr.dev = mp->dev;
1944 memset(&rxq->lro_mgr.stats, 0, sizeof(rxq->lro_mgr.stats));
1945 rxq->lro_mgr.features = LRO_F_NAPI;
1946 rxq->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1947 rxq->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1948 rxq->lro_mgr.max_desc = ARRAY_SIZE(rxq->lro_arr);
1949 rxq->lro_mgr.max_aggr = 32;
1950 rxq->lro_mgr.frag_align_pad = 0;
1951 rxq->lro_mgr.lro_arr = rxq->lro_arr;
1952 rxq->lro_mgr.get_skb_header = mv643xx_get_skb_header;
1953
1954 memset(&rxq->lro_arr, 0, sizeof(rxq->lro_arr));
1955 #endif
1956
1957 return 0;
1958
1959
1960 out_free:
1961 if (index == 0 && size <= mp->rx_desc_sram_size)
1962 iounmap(rxq->rx_desc_area);
1963 else
1964 dma_free_coherent(NULL, size,
1965 rxq->rx_desc_area,
1966 rxq->rx_desc_dma);
1967
1968 out:
1969 return -ENOMEM;
1970 }
1971
1972 static void rxq_deinit(struct rx_queue *rxq)
1973 {
1974 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1975 int i;
1976
1977 rxq_disable(rxq);
1978
1979 for (i = 0; i < rxq->rx_ring_size; i++) {
1980 if (rxq->rx_skb[i]) {
1981 dev_kfree_skb(rxq->rx_skb[i]);
1982 rxq->rx_desc_count--;
1983 }
1984 }
1985
1986 if (rxq->rx_desc_count) {
1987 dev_printk(KERN_ERR, &mp->dev->dev,
1988 "error freeing rx ring -- %d skbs stuck\n",
1989 rxq->rx_desc_count);
1990 }
1991
1992 if (rxq->index == 0 &&
1993 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1994 iounmap(rxq->rx_desc_area);
1995 else
1996 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1997 rxq->rx_desc_area, rxq->rx_desc_dma);
1998
1999 kfree(rxq->rx_skb);
2000 }
2001
2002 static int txq_init(struct mv643xx_eth_private *mp, int index)
2003 {
2004 struct tx_queue *txq = mp->txq + index;
2005 struct tx_desc *tx_desc;
2006 int size;
2007 int i;
2008
2009 txq->index = index;
2010
2011 txq->tx_ring_size = mp->tx_ring_size;
2012
2013 txq->tx_desc_count = 0;
2014 txq->tx_curr_desc = 0;
2015 txq->tx_used_desc = 0;
2016
2017 size = txq->tx_ring_size * sizeof(struct tx_desc);
2018
2019 if (index == 0 && size <= mp->tx_desc_sram_size) {
2020 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
2021 mp->tx_desc_sram_size);
2022 txq->tx_desc_dma = mp->tx_desc_sram_addr;
2023 } else {
2024 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
2025 &txq->tx_desc_dma,
2026 GFP_KERNEL);
2027 }
2028
2029 if (txq->tx_desc_area == NULL) {
2030 dev_printk(KERN_ERR, &mp->dev->dev,
2031 "can't allocate tx ring (%d bytes)\n", size);
2032 return -ENOMEM;
2033 }
2034 memset(txq->tx_desc_area, 0, size);
2035
2036 txq->tx_desc_area_size = size;
2037
2038 tx_desc = (struct tx_desc *)txq->tx_desc_area;
2039 for (i = 0; i < txq->tx_ring_size; i++) {
2040 struct tx_desc *txd = tx_desc + i;
2041 int nexti;
2042
2043 nexti = i + 1;
2044 if (nexti == txq->tx_ring_size)
2045 nexti = 0;
2046
2047 txd->cmd_sts = 0;
2048 txd->next_desc_ptr = txq->tx_desc_dma +
2049 nexti * sizeof(struct tx_desc);
2050 }
2051
2052 skb_queue_head_init(&txq->tx_skb);
2053
2054 return 0;
2055 }
2056
2057 static void txq_deinit(struct tx_queue *txq)
2058 {
2059 struct mv643xx_eth_private *mp = txq_to_mp(txq);
2060
2061 txq_disable(txq);
2062 txq_reclaim(txq, txq->tx_ring_size, 1);
2063
2064 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
2065
2066 if (txq->index == 0 &&
2067 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
2068 iounmap(txq->tx_desc_area);
2069 else
2070 dma_free_coherent(NULL, txq->tx_desc_area_size,
2071 txq->tx_desc_area, txq->tx_desc_dma);
2072 }
2073
2074
2075 /* netdev ops and related ***************************************************/
2076 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
2077 {
2078 u32 int_cause;
2079 u32 int_cause_ext;
2080
2081 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
2082 if (int_cause == 0)
2083 return 0;
2084
2085 int_cause_ext = 0;
2086 if (int_cause & INT_EXT)
2087 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
2088
2089 int_cause &= INT_TX_END | INT_RX;
2090 if (int_cause) {
2091 wrlp(mp, INT_CAUSE, ~int_cause);
2092 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
2093 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
2094 mp->work_rx |= (int_cause & INT_RX) >> 2;
2095 }
2096
2097 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
2098 if (int_cause_ext) {
2099 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
2100 if (int_cause_ext & INT_EXT_LINK_PHY)
2101 mp->work_link = 1;
2102 mp->work_tx |= int_cause_ext & INT_EXT_TX;
2103 }
2104
2105 return 1;
2106 }
2107
2108 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
2109 {
2110 struct net_device *dev = (struct net_device *)dev_id;
2111 struct mv643xx_eth_private *mp = netdev_priv(dev);
2112
2113 if (unlikely(!mv643xx_eth_collect_events(mp)))
2114 return IRQ_NONE;
2115
2116 wrlp(mp, INT_MASK, 0);
2117 napi_schedule(&mp->napi);
2118
2119 return IRQ_HANDLED;
2120 }
2121
2122 static void handle_link_event(struct mv643xx_eth_private *mp)
2123 {
2124 struct net_device *dev = mp->dev;
2125 u32 port_status;
2126 int speed;
2127 int duplex;
2128 int fc;
2129
2130 port_status = rdlp(mp, PORT_STATUS);
2131 if (!(port_status & LINK_UP)) {
2132 if (netif_carrier_ok(dev)) {
2133 int i;
2134
2135 printk(KERN_INFO "%s: link down\n", dev->name);
2136
2137 netif_carrier_off(dev);
2138
2139 for (i = 0; i < mp->txq_count; i++) {
2140 struct tx_queue *txq = mp->txq + i;
2141
2142 txq_reclaim(txq, txq->tx_ring_size, 1);
2143 txq_reset_hw_ptr(txq);
2144 }
2145 }
2146 return;
2147 }
2148
2149 switch (port_status & PORT_SPEED_MASK) {
2150 case PORT_SPEED_10:
2151 speed = 10;
2152 break;
2153 case PORT_SPEED_100:
2154 speed = 100;
2155 break;
2156 case PORT_SPEED_1000:
2157 speed = 1000;
2158 break;
2159 default:
2160 speed = -1;
2161 break;
2162 }
2163 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2164 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2165
2166 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2167 "flow control %sabled\n", dev->name,
2168 speed, duplex ? "full" : "half",
2169 fc ? "en" : "dis");
2170
2171 if (!netif_carrier_ok(dev))
2172 netif_carrier_on(dev);
2173 }
2174
2175 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2176 {
2177 struct mv643xx_eth_private *mp;
2178 int work_done;
2179
2180 mp = container_of(napi, struct mv643xx_eth_private, napi);
2181
2182 mp->work_rx_refill |= mp->work_rx_oom;
2183 mp->work_rx_oom = 0;
2184
2185 work_done = 0;
2186 while (work_done < budget) {
2187 u8 queue_mask;
2188 int queue;
2189 int work_tbd;
2190
2191 if (mp->work_link) {
2192 mp->work_link = 0;
2193 handle_link_event(mp);
2194 continue;
2195 }
2196
2197 queue_mask = mp->work_tx | mp->work_tx_end |
2198 mp->work_rx | mp->work_rx_refill;
2199 if (!queue_mask) {
2200 if (mv643xx_eth_collect_events(mp))
2201 continue;
2202 break;
2203 }
2204
2205 queue = fls(queue_mask) - 1;
2206 queue_mask = 1 << queue;
2207
2208 work_tbd = budget - work_done;
2209 if (work_tbd > 16)
2210 work_tbd = 16;
2211
2212 if (mp->work_tx_end & queue_mask) {
2213 txq_kick(mp->txq + queue);
2214 } else if (mp->work_tx & queue_mask) {
2215 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2216 txq_maybe_wake(mp->txq + queue);
2217 } else if (mp->work_rx & queue_mask) {
2218 work_done += rxq_process(mp->rxq + queue, work_tbd);
2219 } else if (mp->work_rx_refill & queue_mask) {
2220 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2221 } else {
2222 BUG();
2223 }
2224 }
2225
2226 if (work_done < budget) {
2227 if (mp->work_rx_oom)
2228 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2229 napi_complete(napi);
2230 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2231 }
2232
2233 return work_done;
2234 }
2235
2236 static inline void oom_timer_wrapper(unsigned long data)
2237 {
2238 struct mv643xx_eth_private *mp = (void *)data;
2239
2240 napi_schedule(&mp->napi);
2241 }
2242
2243 static void phy_reset(struct mv643xx_eth_private *mp)
2244 {
2245 int data;
2246
2247 data = phy_read(mp->phy, MII_BMCR);
2248 if (data < 0)
2249 return;
2250
2251 data |= BMCR_RESET;
2252 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2253 return;
2254
2255 do {
2256 data = phy_read(mp->phy, MII_BMCR);
2257 } while (data >= 0 && data & BMCR_RESET);
2258 }
2259
2260 static void port_start(struct mv643xx_eth_private *mp)
2261 {
2262 u32 pscr;
2263 int i;
2264
2265 /*
2266 * Perform PHY reset, if there is a PHY.
2267 */
2268 if (mp->phy != NULL) {
2269 struct ethtool_cmd cmd;
2270
2271 mv643xx_eth_get_settings(mp->dev, &cmd);
2272 phy_reset(mp);
2273 mv643xx_eth_set_settings(mp->dev, &cmd);
2274 }
2275
2276 /*
2277 * Configure basic link parameters.
2278 */
2279 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2280
2281 pscr |= SERIAL_PORT_ENABLE;
2282 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2283
2284 pscr |= DO_NOT_FORCE_LINK_FAIL;
2285 if (mp->phy == NULL)
2286 pscr |= FORCE_LINK_PASS;
2287 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2288
2289 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2290
2291 /*
2292 * Configure TX path and queues.
2293 */
2294 tx_set_rate(mp, 1000000000, 16777216);
2295 for (i = 0; i < mp->txq_count; i++) {
2296 struct tx_queue *txq = mp->txq + i;
2297
2298 txq_reset_hw_ptr(txq);
2299 txq_set_rate(txq, 1000000000, 16777216);
2300 txq_set_fixed_prio_mode(txq);
2301 }
2302
2303 /*
2304 * Add configured unicast address to address filter table.
2305 */
2306 mv643xx_eth_program_unicast_filter(mp->dev);
2307
2308 /*
2309 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2310 * frames to RX queue #0, and include the pseudo-header when
2311 * calculating receive checksums.
2312 */
2313 wrlp(mp, PORT_CONFIG, 0x02000000);
2314
2315 /*
2316 * Treat BPDUs as normal multicasts, and disable partition mode.
2317 */
2318 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2319
2320 /*
2321 * Enable the receive queues.
2322 */
2323 for (i = 0; i < mp->rxq_count; i++) {
2324 struct rx_queue *rxq = mp->rxq + i;
2325 u32 addr;
2326
2327 addr = (u32)rxq->rx_desc_dma;
2328 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2329 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2330
2331 rxq_enable(rxq);
2332 }
2333 }
2334
2335 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2336 {
2337 int skb_size;
2338
2339 /*
2340 * Reserve 2+14 bytes for an ethernet header (the hardware
2341 * automatically prepends 2 bytes of dummy data to each
2342 * received packet), 16 bytes for up to four VLAN tags, and
2343 * 4 bytes for the trailing FCS -- 36 bytes total.
2344 */
2345 skb_size = mp->dev->mtu + 36;
2346
2347 /*
2348 * Make sure that the skb size is a multiple of 8 bytes, as
2349 * the lower three bits of the receive descriptor's buffer
2350 * size field are ignored by the hardware.
2351 */
2352 mp->skb_size = (skb_size + 7) & ~7;
2353 }
2354
2355 static int mv643xx_eth_open(struct net_device *dev)
2356 {
2357 struct mv643xx_eth_private *mp = netdev_priv(dev);
2358 int err;
2359 int i;
2360
2361 wrlp(mp, INT_CAUSE, 0);
2362 wrlp(mp, INT_CAUSE_EXT, 0);
2363 rdlp(mp, INT_CAUSE_EXT);
2364
2365 err = request_irq(dev->irq, mv643xx_eth_irq,
2366 IRQF_SHARED, dev->name, dev);
2367 if (err) {
2368 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2369 return -EAGAIN;
2370 }
2371
2372 mv643xx_eth_recalc_skb_size(mp);
2373
2374 napi_enable(&mp->napi);
2375
2376 skb_queue_head_init(&mp->rx_recycle);
2377
2378 for (i = 0; i < mp->rxq_count; i++) {
2379 err = rxq_init(mp, i);
2380 if (err) {
2381 while (--i >= 0)
2382 rxq_deinit(mp->rxq + i);
2383 goto out;
2384 }
2385
2386 rxq_refill(mp->rxq + i, INT_MAX);
2387 }
2388
2389 if (mp->work_rx_oom) {
2390 mp->rx_oom.expires = jiffies + (HZ / 10);
2391 add_timer(&mp->rx_oom);
2392 }
2393
2394 for (i = 0; i < mp->txq_count; i++) {
2395 err = txq_init(mp, i);
2396 if (err) {
2397 while (--i >= 0)
2398 txq_deinit(mp->txq + i);
2399 goto out_free;
2400 }
2401 }
2402
2403 netif_carrier_off(dev);
2404
2405 port_start(mp);
2406
2407 set_rx_coal(mp, 0);
2408 set_tx_coal(mp, 0);
2409
2410 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2411 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2412
2413 return 0;
2414
2415
2416 out_free:
2417 for (i = 0; i < mp->rxq_count; i++)
2418 rxq_deinit(mp->rxq + i);
2419 out:
2420 free_irq(dev->irq, dev);
2421
2422 return err;
2423 }
2424
2425 static void port_reset(struct mv643xx_eth_private *mp)
2426 {
2427 unsigned int data;
2428 int i;
2429
2430 for (i = 0; i < mp->rxq_count; i++)
2431 rxq_disable(mp->rxq + i);
2432 for (i = 0; i < mp->txq_count; i++)
2433 txq_disable(mp->txq + i);
2434
2435 while (1) {
2436 u32 ps = rdlp(mp, PORT_STATUS);
2437
2438 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2439 break;
2440 udelay(10);
2441 }
2442
2443 /* Reset the Enable bit in the Configuration Register */
2444 data = rdlp(mp, PORT_SERIAL_CONTROL);
2445 data &= ~(SERIAL_PORT_ENABLE |
2446 DO_NOT_FORCE_LINK_FAIL |
2447 FORCE_LINK_PASS);
2448 wrlp(mp, PORT_SERIAL_CONTROL, data);
2449 }
2450
2451 static int mv643xx_eth_stop(struct net_device *dev)
2452 {
2453 struct mv643xx_eth_private *mp = netdev_priv(dev);
2454 int i;
2455
2456 wrlp(mp, INT_MASK_EXT, 0x00000000);
2457 wrlp(mp, INT_MASK, 0x00000000);
2458 rdlp(mp, INT_MASK);
2459
2460 del_timer_sync(&mp->mib_counters_timer);
2461
2462 napi_disable(&mp->napi);
2463
2464 del_timer_sync(&mp->rx_oom);
2465
2466 netif_carrier_off(dev);
2467
2468 free_irq(dev->irq, dev);
2469
2470 port_reset(mp);
2471 mv643xx_eth_get_stats(dev);
2472 mib_counters_update(mp);
2473
2474 skb_queue_purge(&mp->rx_recycle);
2475
2476 for (i = 0; i < mp->rxq_count; i++)
2477 rxq_deinit(mp->rxq + i);
2478 for (i = 0; i < mp->txq_count; i++)
2479 txq_deinit(mp->txq + i);
2480
2481 return 0;
2482 }
2483
2484 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2485 {
2486 struct mv643xx_eth_private *mp = netdev_priv(dev);
2487
2488 if (mp->phy != NULL)
2489 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2490
2491 return -EOPNOTSUPP;
2492 }
2493
2494 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2495 {
2496 struct mv643xx_eth_private *mp = netdev_priv(dev);
2497
2498 if (new_mtu < 64 || new_mtu > 9500)
2499 return -EINVAL;
2500
2501 dev->mtu = new_mtu;
2502 mv643xx_eth_recalc_skb_size(mp);
2503 tx_set_rate(mp, 1000000000, 16777216);
2504
2505 if (!netif_running(dev))
2506 return 0;
2507
2508 /*
2509 * Stop and then re-open the interface. This will allocate RX
2510 * skbs of the new MTU.
2511 * There is a possible danger that the open will not succeed,
2512 * due to memory being full.
2513 */
2514 mv643xx_eth_stop(dev);
2515 if (mv643xx_eth_open(dev)) {
2516 dev_printk(KERN_ERR, &dev->dev,
2517 "fatal error on re-opening device after "
2518 "MTU change\n");
2519 }
2520
2521 return 0;
2522 }
2523
2524 static void tx_timeout_task(struct work_struct *ugly)
2525 {
2526 struct mv643xx_eth_private *mp;
2527
2528 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2529 if (netif_running(mp->dev)) {
2530 netif_tx_stop_all_queues(mp->dev);
2531 port_reset(mp);
2532 port_start(mp);
2533 netif_tx_wake_all_queues(mp->dev);
2534 }
2535 }
2536
2537 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2538 {
2539 struct mv643xx_eth_private *mp = netdev_priv(dev);
2540
2541 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2542
2543 schedule_work(&mp->tx_timeout_task);
2544 }
2545
2546 #ifdef CONFIG_NET_POLL_CONTROLLER
2547 static void mv643xx_eth_netpoll(struct net_device *dev)
2548 {
2549 struct mv643xx_eth_private *mp = netdev_priv(dev);
2550
2551 wrlp(mp, INT_MASK, 0x00000000);
2552 rdlp(mp, INT_MASK);
2553
2554 mv643xx_eth_irq(dev->irq, dev);
2555
2556 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2557 }
2558 #endif
2559
2560
2561 /* platform glue ************************************************************/
2562 static void
2563 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2564 struct mbus_dram_target_info *dram)
2565 {
2566 void __iomem *base = msp->base;
2567 u32 win_enable;
2568 u32 win_protect;
2569 int i;
2570
2571 for (i = 0; i < 6; i++) {
2572 writel(0, base + WINDOW_BASE(i));
2573 writel(0, base + WINDOW_SIZE(i));
2574 if (i < 4)
2575 writel(0, base + WINDOW_REMAP_HIGH(i));
2576 }
2577
2578 win_enable = 0x3f;
2579 win_protect = 0;
2580
2581 for (i = 0; i < dram->num_cs; i++) {
2582 struct mbus_dram_window *cs = dram->cs + i;
2583
2584 writel((cs->base & 0xffff0000) |
2585 (cs->mbus_attr << 8) |
2586 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2587 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2588
2589 win_enable &= ~(1 << i);
2590 win_protect |= 3 << (2 * i);
2591 }
2592
2593 writel(win_enable, base + WINDOW_BAR_ENABLE);
2594 msp->win_protect = win_protect;
2595 }
2596
2597 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2598 {
2599 /*
2600 * Check whether we have a 14-bit coal limit field in bits
2601 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2602 * SDMA config register.
2603 */
2604 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2605 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2606 msp->extended_rx_coal_limit = 1;
2607 else
2608 msp->extended_rx_coal_limit = 0;
2609
2610 /*
2611 * Check whether the MAC supports TX rate control, and if
2612 * yes, whether its associated registers are in the old or
2613 * the new place.
2614 */
2615 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2616 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2617 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2618 } else {
2619 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2620 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2621 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2622 else
2623 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2624 }
2625 }
2626
2627 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2628 {
2629 static int mv643xx_eth_version_printed;
2630 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2631 struct mv643xx_eth_shared_private *msp;
2632 struct resource *res;
2633 int ret;
2634
2635 if (!mv643xx_eth_version_printed++)
2636 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2637 "driver version %s\n", mv643xx_eth_driver_version);
2638
2639 ret = -EINVAL;
2640 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2641 if (res == NULL)
2642 goto out;
2643
2644 ret = -ENOMEM;
2645 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2646 if (msp == NULL)
2647 goto out;
2648 memset(msp, 0, sizeof(*msp));
2649
2650 msp->base = ioremap(res->start, res->end - res->start + 1);
2651 if (msp->base == NULL)
2652 goto out_free;
2653
2654 /*
2655 * Set up and register SMI bus.
2656 */
2657 if (pd == NULL || pd->shared_smi == NULL) {
2658 msp->smi_bus = mdiobus_alloc();
2659 if (msp->smi_bus == NULL)
2660 goto out_unmap;
2661
2662 msp->smi_bus->priv = msp;
2663 msp->smi_bus->name = "mv643xx_eth smi";
2664 msp->smi_bus->read = smi_bus_read;
2665 msp->smi_bus->write = smi_bus_write,
2666 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2667 msp->smi_bus->parent = &pdev->dev;
2668 msp->smi_bus->phy_mask = 0xffffffff;
2669 if (mdiobus_register(msp->smi_bus) < 0)
2670 goto out_free_mii_bus;
2671 msp->smi = msp;
2672 } else {
2673 msp->smi = platform_get_drvdata(pd->shared_smi);
2674 }
2675
2676 msp->err_interrupt = NO_IRQ;
2677 init_waitqueue_head(&msp->smi_busy_wait);
2678
2679 /*
2680 * Check whether the error interrupt is hooked up.
2681 */
2682 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2683 if (res != NULL) {
2684 int err;
2685
2686 err = request_irq(res->start, mv643xx_eth_err_irq,
2687 IRQF_SHARED, "mv643xx_eth", msp);
2688 if (!err) {
2689 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2690 msp->err_interrupt = res->start;
2691 }
2692 }
2693
2694 /*
2695 * (Re-)program MBUS remapping windows if we are asked to.
2696 */
2697 if (pd != NULL && pd->dram != NULL)
2698 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2699
2700 /*
2701 * Detect hardware parameters.
2702 */
2703 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2704 infer_hw_params(msp);
2705
2706 platform_set_drvdata(pdev, msp);
2707
2708 return 0;
2709
2710 out_free_mii_bus:
2711 mdiobus_free(msp->smi_bus);
2712 out_unmap:
2713 iounmap(msp->base);
2714 out_free:
2715 kfree(msp);
2716 out:
2717 return ret;
2718 }
2719
2720 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2721 {
2722 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2723 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2724
2725 if (pd == NULL || pd->shared_smi == NULL) {
2726 mdiobus_unregister(msp->smi_bus);
2727 mdiobus_free(msp->smi_bus);
2728 }
2729 if (msp->err_interrupt != NO_IRQ)
2730 free_irq(msp->err_interrupt, msp);
2731 iounmap(msp->base);
2732 kfree(msp);
2733
2734 return 0;
2735 }
2736
2737 static struct platform_driver mv643xx_eth_shared_driver = {
2738 .probe = mv643xx_eth_shared_probe,
2739 .remove = mv643xx_eth_shared_remove,
2740 .driver = {
2741 .name = MV643XX_ETH_SHARED_NAME,
2742 .owner = THIS_MODULE,
2743 },
2744 };
2745
2746 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2747 {
2748 int addr_shift = 5 * mp->port_num;
2749 u32 data;
2750
2751 data = rdl(mp, PHY_ADDR);
2752 data &= ~(0x1f << addr_shift);
2753 data |= (phy_addr & 0x1f) << addr_shift;
2754 wrl(mp, PHY_ADDR, data);
2755 }
2756
2757 static int phy_addr_get(struct mv643xx_eth_private *mp)
2758 {
2759 unsigned int data;
2760
2761 data = rdl(mp, PHY_ADDR);
2762
2763 return (data >> (5 * mp->port_num)) & 0x1f;
2764 }
2765
2766 static void set_params(struct mv643xx_eth_private *mp,
2767 struct mv643xx_eth_platform_data *pd)
2768 {
2769 struct net_device *dev = mp->dev;
2770
2771 if (is_valid_ether_addr(pd->mac_addr))
2772 memcpy(dev->dev_addr, pd->mac_addr, 6);
2773 else
2774 uc_addr_get(mp, dev->dev_addr);
2775
2776 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2777 if (pd->rx_queue_size)
2778 mp->rx_ring_size = pd->rx_queue_size;
2779 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2780 mp->rx_desc_sram_size = pd->rx_sram_size;
2781
2782 mp->rxq_count = pd->rx_queue_count ? : 1;
2783
2784 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2785 if (pd->tx_queue_size)
2786 mp->tx_ring_size = pd->tx_queue_size;
2787 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2788 mp->tx_desc_sram_size = pd->tx_sram_size;
2789
2790 mp->txq_count = pd->tx_queue_count ? : 1;
2791 }
2792
2793 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2794 int phy_addr)
2795 {
2796 struct mii_bus *bus = mp->shared->smi->smi_bus;
2797 struct phy_device *phydev;
2798 int start;
2799 int num;
2800 int i;
2801
2802 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2803 start = phy_addr_get(mp) & 0x1f;
2804 num = 32;
2805 } else {
2806 start = phy_addr & 0x1f;
2807 num = 1;
2808 }
2809
2810 phydev = NULL;
2811 for (i = 0; i < num; i++) {
2812 int addr = (start + i) & 0x1f;
2813
2814 if (bus->phy_map[addr] == NULL)
2815 mdiobus_scan(bus, addr);
2816
2817 if (phydev == NULL) {
2818 phydev = bus->phy_map[addr];
2819 if (phydev != NULL)
2820 phy_addr_set(mp, addr);
2821 }
2822 }
2823
2824 return phydev;
2825 }
2826
2827 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2828 {
2829 struct phy_device *phy = mp->phy;
2830
2831 phy_reset(mp);
2832
2833 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2834
2835 if (speed == 0) {
2836 phy->autoneg = AUTONEG_ENABLE;
2837 phy->speed = 0;
2838 phy->duplex = 0;
2839 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2840 } else {
2841 phy->autoneg = AUTONEG_DISABLE;
2842 phy->advertising = 0;
2843 phy->speed = speed;
2844 phy->duplex = duplex;
2845 }
2846 phy_start_aneg(phy);
2847 }
2848
2849 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2850 {
2851 u32 pscr;
2852
2853 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2854 if (pscr & SERIAL_PORT_ENABLE) {
2855 pscr &= ~SERIAL_PORT_ENABLE;
2856 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2857 }
2858
2859 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2860 if (mp->phy == NULL) {
2861 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2862 if (speed == SPEED_1000)
2863 pscr |= SET_GMII_SPEED_TO_1000;
2864 else if (speed == SPEED_100)
2865 pscr |= SET_MII_SPEED_TO_100;
2866
2867 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2868
2869 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2870 if (duplex == DUPLEX_FULL)
2871 pscr |= SET_FULL_DUPLEX_MODE;
2872 }
2873
2874 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2875 }
2876
2877 static int mv643xx_eth_probe(struct platform_device *pdev)
2878 {
2879 struct mv643xx_eth_platform_data *pd;
2880 struct mv643xx_eth_private *mp;
2881 struct net_device *dev;
2882 struct resource *res;
2883 int err;
2884
2885 pd = pdev->dev.platform_data;
2886 if (pd == NULL) {
2887 dev_printk(KERN_ERR, &pdev->dev,
2888 "no mv643xx_eth_platform_data\n");
2889 return -ENODEV;
2890 }
2891
2892 if (pd->shared == NULL) {
2893 dev_printk(KERN_ERR, &pdev->dev,
2894 "no mv643xx_eth_platform_data->shared\n");
2895 return -ENODEV;
2896 }
2897
2898 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2899 if (!dev)
2900 return -ENOMEM;
2901
2902 mp = netdev_priv(dev);
2903 platform_set_drvdata(pdev, mp);
2904
2905 mp->shared = platform_get_drvdata(pd->shared);
2906 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2907 mp->port_num = pd->port_number;
2908
2909 mp->dev = dev;
2910
2911 set_params(mp, pd);
2912 dev->real_num_tx_queues = mp->txq_count;
2913
2914 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2915 mp->phy = phy_scan(mp, pd->phy_addr);
2916
2917 if (mp->phy != NULL)
2918 phy_init(mp, pd->speed, pd->duplex);
2919
2920 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2921
2922 init_pscr(mp, pd->speed, pd->duplex);
2923
2924
2925 mib_counters_clear(mp);
2926
2927 init_timer(&mp->mib_counters_timer);
2928 mp->mib_counters_timer.data = (unsigned long)mp;
2929 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2930 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2931 add_timer(&mp->mib_counters_timer);
2932
2933 spin_lock_init(&mp->mib_counters_lock);
2934
2935 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2936
2937 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2938
2939 init_timer(&mp->rx_oom);
2940 mp->rx_oom.data = (unsigned long)mp;
2941 mp->rx_oom.function = oom_timer_wrapper;
2942
2943
2944 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2945 BUG_ON(!res);
2946 dev->irq = res->start;
2947
2948 dev->get_stats = mv643xx_eth_get_stats;
2949 dev->hard_start_xmit = mv643xx_eth_xmit;
2950 dev->open = mv643xx_eth_open;
2951 dev->stop = mv643xx_eth_stop;
2952 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
2953 dev->set_mac_address = mv643xx_eth_set_mac_address;
2954 dev->do_ioctl = mv643xx_eth_ioctl;
2955 dev->change_mtu = mv643xx_eth_change_mtu;
2956 dev->tx_timeout = mv643xx_eth_tx_timeout;
2957 #ifdef CONFIG_NET_POLL_CONTROLLER
2958 dev->poll_controller = mv643xx_eth_netpoll;
2959 #endif
2960 dev->watchdog_timeo = 2 * HZ;
2961 dev->base_addr = 0;
2962
2963 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2964 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2965
2966 SET_NETDEV_DEV(dev, &pdev->dev);
2967
2968 if (mp->shared->win_protect)
2969 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2970
2971 err = register_netdev(dev);
2972 if (err)
2973 goto out;
2974
2975 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2976 mp->port_num, dev->dev_addr);
2977
2978 if (mp->tx_desc_sram_size > 0)
2979 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2980
2981 return 0;
2982
2983 out:
2984 free_netdev(dev);
2985
2986 return err;
2987 }
2988
2989 static int mv643xx_eth_remove(struct platform_device *pdev)
2990 {
2991 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2992
2993 unregister_netdev(mp->dev);
2994 if (mp->phy != NULL)
2995 phy_detach(mp->phy);
2996 flush_scheduled_work();
2997 free_netdev(mp->dev);
2998
2999 platform_set_drvdata(pdev, NULL);
3000
3001 return 0;
3002 }
3003
3004 static void mv643xx_eth_shutdown(struct platform_device *pdev)
3005 {
3006 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
3007
3008 /* Mask all interrupts on ethernet port */
3009 wrlp(mp, INT_MASK, 0);
3010 rdlp(mp, INT_MASK);
3011
3012 if (netif_running(mp->dev))
3013 port_reset(mp);
3014 }
3015
3016 static struct platform_driver mv643xx_eth_driver = {
3017 .probe = mv643xx_eth_probe,
3018 .remove = mv643xx_eth_remove,
3019 .shutdown = mv643xx_eth_shutdown,
3020 .driver = {
3021 .name = MV643XX_ETH_NAME,
3022 .owner = THIS_MODULE,
3023 },
3024 };
3025
3026 static int __init mv643xx_eth_init_module(void)
3027 {
3028 int rc;
3029
3030 rc = platform_driver_register(&mv643xx_eth_shared_driver);
3031 if (!rc) {
3032 rc = platform_driver_register(&mv643xx_eth_driver);
3033 if (rc)
3034 platform_driver_unregister(&mv643xx_eth_shared_driver);
3035 }
3036
3037 return rc;
3038 }
3039 module_init(mv643xx_eth_init_module);
3040
3041 static void __exit mv643xx_eth_cleanup_module(void)
3042 {
3043 platform_driver_unregister(&mv643xx_eth_driver);
3044 platform_driver_unregister(&mv643xx_eth_shared_driver);
3045 }
3046 module_exit(mv643xx_eth_cleanup_module);
3047
3048 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
3049 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
3050 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
3051 MODULE_LICENSE("GPL");
3052 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
3053 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
Linux kernel - Deliverables
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