2 * drivers/net/mv643xx_eth.c - Driver for MV643XX ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2005 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/tcp.h>
36 #include <linux/udp.h>
37 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
47 #include <asm/types.h>
48 #include <asm/pgtable.h>
49 #include <asm/system.h>
50 #include <asm/delay.h>
51 #include "mv643xx_eth.h"
54 * The first part is the high level driver of the gigE ethernet ports.
60 #define DMA_ALIGN 8 /* hw requires 8-byte alignment */
61 #define HW_IP_ALIGN 2 /* hw aligns IP header */
62 #define WRAP HW_IP_ALIGN + ETH_HLEN + VLAN_HLEN + FCS_LEN
63 #define RX_SKB_SIZE ((dev->mtu + WRAP + 7) & ~0x7)
65 #define INT_CAUSE_UNMASK_ALL 0x0007ffff
66 #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
67 #define INT_CAUSE_MASK_ALL 0x00000000
68 #define INT_CAUSE_MASK_ALL_EXT 0x00000000
69 #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL
70 #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT
72 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
73 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
75 #define MAX_DESCS_PER_SKB 1
78 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
79 #define PHY_WAIT_MICRO_SECONDS 10
81 /* Static function declarations */
82 static int eth_port_link_is_up(unsigned int eth_port_num
);
83 static void eth_port_uc_addr_get(struct net_device
*dev
,
84 unsigned char *MacAddr
);
85 static void eth_port_set_multicast_list(struct net_device
*);
86 static int mv643xx_eth_real_open(struct net_device
*);
87 static int mv643xx_eth_real_stop(struct net_device
*);
88 static int mv643xx_eth_change_mtu(struct net_device
*, int);
89 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*);
90 static void eth_port_init_mac_tables(unsigned int eth_port_num
);
92 static int mv643xx_poll(struct net_device
*dev
, int *budget
);
94 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
95 static int ethernet_phy_detect(unsigned int eth_port_num
);
96 static struct ethtool_ops mv643xx_ethtool_ops
;
98 static char mv643xx_driver_name
[] = "mv643xx_eth";
99 static char mv643xx_driver_version
[] = "1.0";
101 static void __iomem
*mv643xx_eth_shared_base
;
103 /* used to protect MV643XX_ETH_SMI_REG, which is shared across ports */
104 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
106 static inline u32
mv_read(int offset
)
108 void __iomem
*reg_base
;
110 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
112 return readl(reg_base
+ offset
);
115 static inline void mv_write(int offset
, u32 data
)
117 void __iomem
*reg_base
;
119 reg_base
= mv643xx_eth_shared_base
- MV643XX_ETH_SHARED_REGS
;
120 writel(data
, reg_base
+ offset
);
124 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
126 * Input : pointer to ethernet interface network device structure
128 * Output : 0 upon success, -EINVAL upon failure
130 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
132 if ((new_mtu
> 9500) || (new_mtu
< 64))
137 * Stop then re-open the interface. This will allocate RX skb's with
139 * There is a possible danger that the open will not successed, due
140 * to memory is full, which might fail the open function.
142 if (netif_running(dev
)) {
143 if (mv643xx_eth_real_stop(dev
))
145 "%s: Fatal error on stopping device\n",
147 if (mv643xx_eth_real_open(dev
))
149 "%s: Fatal error on opening device\n",
157 * mv643xx_eth_rx_task
159 * Fills / refills RX queue on a certain gigabit ethernet port
161 * Input : pointer to ethernet interface network device structure
164 static void mv643xx_eth_rx_task(void *data
)
166 struct net_device
*dev
= (struct net_device
*)data
;
167 struct mv643xx_private
*mp
= netdev_priv(dev
);
168 struct pkt_info pkt_info
;
172 if (test_and_set_bit(0, &mp
->rx_task_busy
))
173 panic("%s: Error in test_set_bit / clear_bit", dev
->name
);
175 while (mp
->rx_ring_skbs
< (mp
->rx_ring_size
- 5)) {
176 skb
= dev_alloc_skb(RX_SKB_SIZE
+ DMA_ALIGN
);
180 unaligned
= (u32
)skb
->data
& (DMA_ALIGN
- 1);
182 skb_reserve(skb
, DMA_ALIGN
- unaligned
);
183 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
184 pkt_info
.byte_cnt
= RX_SKB_SIZE
;
185 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, RX_SKB_SIZE
,
187 pkt_info
.return_info
= skb
;
188 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
190 "%s: Error allocating RX Ring\n", dev
->name
);
193 skb_reserve(skb
, HW_IP_ALIGN
);
195 clear_bit(0, &mp
->rx_task_busy
);
197 * If RX ring is empty of SKB, set a timer to try allocating
198 * again in a later time .
200 if ((mp
->rx_ring_skbs
== 0) && (mp
->rx_timer_flag
== 0)) {
201 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
203 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10);
204 add_timer(&mp
->timeout
);
205 mp
->rx_timer_flag
= 1;
207 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
209 /* Return interrupts */
210 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(mp
->port_num
),
211 INT_CAUSE_UNMASK_ALL
);
217 * mv643xx_eth_rx_task_timer_wrapper
219 * Timer routine to wake up RX queue filling task. This function is
220 * used only in case the RX queue is empty, and all alloc_skb has
221 * failed (due to out of memory event).
223 * Input : pointer to ethernet interface network device structure
226 static void mv643xx_eth_rx_task_timer_wrapper(unsigned long data
)
228 struct net_device
*dev
= (struct net_device
*)data
;
229 struct mv643xx_private
*mp
= netdev_priv(dev
);
231 mp
->rx_timer_flag
= 0;
232 mv643xx_eth_rx_task((void *)data
);
236 * mv643xx_eth_update_mac_address
238 * Update the MAC address of the port in the address table
240 * Input : pointer to ethernet interface network device structure
243 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
245 struct mv643xx_private
*mp
= netdev_priv(dev
);
246 unsigned int port_num
= mp
->port_num
;
248 eth_port_init_mac_tables(port_num
);
249 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
250 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
254 * mv643xx_eth_set_rx_mode
256 * Change from promiscuos to regular rx mode
258 * Input : pointer to ethernet interface network device structure
261 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
263 struct mv643xx_private
*mp
= netdev_priv(dev
);
265 if (dev
->flags
& IFF_PROMISC
)
266 mp
->port_config
|= (u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
268 mp
->port_config
&= ~(u32
) MV643XX_ETH_UNICAST_PROMISCUOUS_MODE
;
270 mv_write(MV643XX_ETH_PORT_CONFIG_REG(mp
->port_num
), mp
->port_config
);
272 eth_port_set_multicast_list(dev
);
276 * mv643xx_eth_set_mac_address
278 * Change the interface's mac address.
279 * No special hardware thing should be done because interface is always
280 * put in promiscuous mode.
282 * Input : pointer to ethernet interface network device structure and
283 * a pointer to the designated entry to be added to the cache.
284 * Output : zero upon success, negative upon failure
286 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
290 for (i
= 0; i
< 6; i
++)
291 /* +2 is for the offset of the HW addr type */
292 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
293 mv643xx_eth_update_mac_address(dev
);
298 * mv643xx_eth_tx_timeout
300 * Called upon a timeout on transmitting a packet
302 * Input : pointer to ethernet interface network device structure.
305 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
307 struct mv643xx_private
*mp
= netdev_priv(dev
);
309 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
311 /* Do the reset outside of interrupt context */
312 schedule_work(&mp
->tx_timeout_task
);
316 * mv643xx_eth_tx_timeout_task
318 * Actual routine to reset the adapter when a timeout on Tx has occurred
320 static void mv643xx_eth_tx_timeout_task(struct net_device
*dev
)
322 struct mv643xx_private
*mp
= netdev_priv(dev
);
324 netif_device_detach(dev
);
325 eth_port_reset(mp
->port_num
);
327 netif_device_attach(dev
);
331 * mv643xx_eth_free_tx_queue
333 * Input : dev - a pointer to the required interface
335 * Output : 0 if was able to release skb , nonzero otherwise
337 static int mv643xx_eth_free_tx_queue(struct net_device
*dev
,
338 unsigned int eth_int_cause_ext
)
340 struct mv643xx_private
*mp
= netdev_priv(dev
);
341 struct net_device_stats
*stats
= &mp
->stats
;
342 struct pkt_info pkt_info
;
345 if (!(eth_int_cause_ext
& (BIT0
| BIT8
)))
348 /* Check only queue 0 */
349 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
350 if (pkt_info
.cmd_sts
& BIT0
) {
351 printk("%s: Error in TX\n", dev
->name
);
355 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
356 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
360 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
364 if (pkt_info
.return_info
) {
365 dev_kfree_skb_irq(pkt_info
.return_info
);
374 * mv643xx_eth_receive
376 * This function is forward packets that are received from the port's
377 * queues toward kernel core or FastRoute them to another interface.
379 * Input : dev - a pointer to the required interface
380 * max - maximum number to receive (0 means unlimted)
382 * Output : number of served packets
385 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
387 static int mv643xx_eth_receive_queue(struct net_device
*dev
)
390 struct mv643xx_private
*mp
= netdev_priv(dev
);
391 struct net_device_stats
*stats
= &mp
->stats
;
392 unsigned int received_packets
= 0;
394 struct pkt_info pkt_info
;
397 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
399 while (eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
404 /* Update statistics. Note byte count includes 4 byte CRC count */
406 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
407 skb
= pkt_info
.return_info
;
409 * In case received a packet without first / last bits on OR
410 * the error summary bit is on, the packets needs to be dropeed.
412 if (((pkt_info
.cmd_sts
413 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
414 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
415 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
417 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
418 ETH_RX_LAST_DESC
)) !=
419 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
422 "%s: Received packet spread "
423 "on multiple descriptors\n",
426 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
429 dev_kfree_skb_irq(skb
);
432 * The -4 is for the CRC in the trailer of the
435 skb_put(skb
, pkt_info
.byte_cnt
- 4);
438 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
439 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
441 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
443 skb
->protocol
= eth_type_trans(skb
, dev
);
445 netif_receive_skb(skb
);
452 return received_packets
;
456 * mv643xx_eth_int_handler
458 * Main interrupt handler for the gigbit ethernet ports
460 * Input : irq - irq number (not used)
461 * dev_id - a pointer to the required interface's data structure
466 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
,
467 struct pt_regs
*regs
)
469 struct net_device
*dev
= (struct net_device
*)dev_id
;
470 struct mv643xx_private
*mp
= netdev_priv(dev
);
471 u32 eth_int_cause
, eth_int_cause_ext
= 0;
472 unsigned int port_num
= mp
->port_num
;
474 /* Read interrupt cause registers */
475 eth_int_cause
= mv_read(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
)) &
476 INT_CAUSE_UNMASK_ALL
;
478 if (eth_int_cause
& BIT1
)
479 eth_int_cause_ext
= mv_read(
480 MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
481 INT_CAUSE_UNMASK_ALL_EXT
;
484 if (!(eth_int_cause
& 0x0007fffd)) {
485 /* Dont ack the Rx interrupt */
488 * Clear specific ethernet port intrerrupt registers by
489 * acknowleding relevant bits.
491 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
),
493 if (eth_int_cause_ext
!= 0x0)
494 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG
495 (port_num
), ~eth_int_cause_ext
);
497 /* UDP change : We may need this */
498 if ((eth_int_cause_ext
& 0x0000ffff) &&
499 (mv643xx_eth_free_tx_queue(dev
, eth_int_cause_ext
) == 0) &&
500 (mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
501 netif_wake_queue(dev
);
504 if (netif_rx_schedule_prep(dev
)) {
505 /* Mask all the interrupts */
506 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), 0);
507 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG
509 /* ensure previous writes have taken effect */
510 mv_read(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
));
511 __netif_rx_schedule(dev
);
514 if (eth_int_cause
& (BIT2
| BIT11
))
515 mv643xx_eth_receive_queue(dev
, 0);
518 * After forwarded received packets to upper layer, add a task
519 * in an interrupts enabled context that refills the RX ring
522 #ifdef MV643XX_RX_QUEUE_FILL_ON_TASK
523 /* Unmask all interrupts on ethernet port */
524 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
526 /* wait for previous write to take effect */
527 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
529 queue_task(&mp
->rx_task
, &tq_immediate
);
530 mark_bh(IMMEDIATE_BH
);
532 mp
->rx_task
.func(dev
);
536 /* PHY status changed */
537 if (eth_int_cause_ext
& (BIT16
| BIT20
)) {
538 if (eth_port_link_is_up(port_num
)) {
539 netif_carrier_on(dev
);
540 netif_wake_queue(dev
);
542 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG
545 netif_carrier_off(dev
);
546 netif_stop_queue(dev
);
551 * If no real interrupt occured, exit.
552 * This can happen when using gigE interrupt coalescing mechanism.
554 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
563 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
566 * This routine sets the RX coalescing interrupt mechanism parameter.
567 * This parameter is a timeout counter, that counts in 64 t_clk
568 * chunks ; that when timeout event occurs a maskable interrupt
570 * The parameter is calculated using the tClk of the MV-643xx chip
571 * , and the required delay of the interrupt in usec.
574 * unsigned int eth_port_num Ethernet port number
575 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
576 * unsigned int delay Delay in usec
579 * Interrupt coalescing mechanism value is set in MV-643xx chip.
582 * The interrupt coalescing value set in the gigE port.
585 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num
,
586 unsigned int t_clk
, unsigned int delay
)
588 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
590 /* Set RX Coalescing mechanism */
591 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
),
592 ((coal
& 0x3fff) << 8) |
593 (mv_read(MV643XX_ETH_SDMA_CONFIG_REG(eth_port_num
))
601 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
604 * This routine sets the TX coalescing interrupt mechanism parameter.
605 * This parameter is a timeout counter, that counts in 64 t_clk
606 * chunks ; that when timeout event occurs a maskable interrupt
608 * The parameter is calculated using the t_cLK frequency of the
609 * MV-643xx chip and the required delay in the interrupt in uSec
612 * unsigned int eth_port_num Ethernet port number
613 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
614 * unsigned int delay Delay in uSeconds
617 * Interrupt coalescing mechanism value is set in MV-643xx chip.
620 * The interrupt coalescing value set in the gigE port.
623 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num
,
624 unsigned int t_clk
, unsigned int delay
)
627 coal
= ((t_clk
/ 1000000) * delay
) / 64;
628 /* Set TX Coalescing mechanism */
629 mv_write(MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num
),
637 * This function is called when openning the network device. The function
638 * should initialize all the hardware, initialize cyclic Rx/Tx
639 * descriptors chain and buffers and allocate an IRQ to the network
642 * Input : a pointer to the network device structure
644 * Output : zero of success , nonzero if fails.
647 static int mv643xx_eth_open(struct net_device
*dev
)
649 struct mv643xx_private
*mp
= netdev_priv(dev
);
650 unsigned int port_num
= mp
->port_num
;
653 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
654 SA_SHIRQ
| SA_SAMPLE_RANDOM
, dev
->name
, dev
);
656 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
661 if (mv643xx_eth_real_open(dev
)) {
662 printk("%s: Error opening interface\n", dev
->name
);
663 free_irq(dev
->irq
, dev
);
671 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
674 * This function prepares a Rx chained list of descriptors and packet
675 * buffers in a form of a ring. The routine must be called after port
676 * initialization routine and before port start routine.
677 * The Ethernet SDMA engine uses CPU bus addresses to access the various
678 * devices in the system (i.e. DRAM). This function uses the ethernet
679 * struct 'virtual to physical' routine (set by the user) to set the ring
680 * with physical addresses.
683 * struct mv643xx_private *mp Ethernet Port Control srtuct.
686 * The routine updates the Ethernet port control struct with information
687 * regarding the Rx descriptors and buffers.
692 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
694 volatile struct eth_rx_desc
*p_rx_desc
;
695 int rx_desc_num
= mp
->rx_ring_size
;
698 /* initialize the next_desc_ptr links in the Rx descriptors ring */
699 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
700 for (i
= 0; i
< rx_desc_num
; i
++) {
701 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
702 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
705 /* Save Rx desc pointer to driver struct. */
706 mp
->rx_curr_desc_q
= 0;
707 mp
->rx_used_desc_q
= 0;
709 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
711 /* Add the queue to the list of RX queues of this port */
712 mp
->port_rx_queue_command
|= 1;
716 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
719 * This function prepares a Tx chained list of descriptors and packet
720 * buffers in a form of a ring. The routine must be called after port
721 * initialization routine and before port start routine.
722 * The Ethernet SDMA engine uses CPU bus addresses to access the various
723 * devices in the system (i.e. DRAM). This function uses the ethernet
724 * struct 'virtual to physical' routine (set by the user) to set the ring
725 * with physical addresses.
728 * struct mv643xx_private *mp Ethernet Port Control srtuct.
731 * The routine updates the Ethernet port control struct with information
732 * regarding the Tx descriptors and buffers.
737 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
739 int tx_desc_num
= mp
->tx_ring_size
;
740 struct eth_tx_desc
*p_tx_desc
;
743 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
744 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
745 for (i
= 0; i
< tx_desc_num
; i
++) {
746 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
747 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
750 mp
->tx_curr_desc_q
= 0;
751 mp
->tx_used_desc_q
= 0;
752 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
753 mp
->tx_first_desc_q
= 0;
756 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
758 /* Add the queue to the list of Tx queues of this port */
759 mp
->port_tx_queue_command
|= 1;
762 /* Helper function for mv643xx_eth_open */
763 static int mv643xx_eth_real_open(struct net_device
*dev
)
765 struct mv643xx_private
*mp
= netdev_priv(dev
);
766 unsigned int port_num
= mp
->port_num
;
770 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
772 /* Set the MAC Address */
773 memcpy(mp
->port_mac_addr
, dev
->dev_addr
, 6);
777 INIT_WORK(&mp
->rx_task
, (void (*)(void *))mv643xx_eth_rx_task
, dev
);
779 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
780 mp
->timeout
.function
= mv643xx_eth_rx_task_timer_wrapper
;
781 mp
->timeout
.data
= (unsigned long)dev
;
783 mp
->rx_task_busy
= 0;
784 mp
->rx_timer_flag
= 0;
786 /* Allocate RX and TX skb rings */
787 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
790 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
793 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
796 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
801 /* Allocate TX ring */
802 mp
->tx_ring_skbs
= 0;
803 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
804 mp
->tx_desc_area_size
= size
;
806 if (mp
->tx_sram_size
) {
807 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
809 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
811 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
815 if (!mp
->p_tx_desc_area
) {
816 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
822 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
823 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
825 ether_init_tx_desc_ring(mp
);
827 /* Allocate RX ring */
828 mp
->rx_ring_skbs
= 0;
829 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
830 mp
->rx_desc_area_size
= size
;
832 if (mp
->rx_sram_size
) {
833 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
835 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
837 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
841 if (!mp
->p_rx_desc_area
) {
842 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
844 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
846 if (mp
->rx_sram_size
)
847 iounmap(mp
->p_tx_desc_area
);
849 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
850 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
855 memset((void *)mp
->p_rx_desc_area
, 0, size
);
857 ether_init_rx_desc_ring(mp
);
859 mv643xx_eth_rx_task(dev
); /* Fill RX ring with skb's */
863 /* Interrupt Coalescing */
867 eth_port_set_rx_coal(port_num
, 133000000, MV643XX_RX_COAL
);
871 eth_port_set_tx_coal(port_num
, 133000000, MV643XX_TX_COAL
);
873 /* Clear any pending ethernet port interrupts */
874 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
875 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
877 /* Unmask phy and link status changes interrupts */
878 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
879 INT_CAUSE_UNMASK_ALL_EXT
);
881 /* Unmask RX buffer and TX end interrupt */
882 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
883 INT_CAUSE_UNMASK_ALL
);
887 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
889 struct mv643xx_private
*mp
= netdev_priv(dev
);
890 unsigned int port_num
= mp
->port_num
;
894 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
896 /* Free outstanding skb's on TX rings */
897 for (curr
= 0; mp
->tx_ring_skbs
&& curr
< mp
->tx_ring_size
; curr
++) {
898 if (mp
->tx_skb
[curr
]) {
899 dev_kfree_skb(mp
->tx_skb
[curr
]);
903 if (mp
->tx_ring_skbs
)
904 printk("%s: Error on Tx descriptor free - could not free %d"
905 " descriptors\n", dev
->name
, mp
->tx_ring_skbs
);
908 if (mp
->tx_sram_size
)
909 iounmap(mp
->p_tx_desc_area
);
911 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
912 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
915 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
917 struct mv643xx_private
*mp
= netdev_priv(dev
);
918 unsigned int port_num
= mp
->port_num
;
922 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
), 0x0000ff00);
924 /* Free preallocated skb's on RX rings */
925 for (curr
= 0; mp
->rx_ring_skbs
&& curr
< mp
->rx_ring_size
; curr
++) {
926 if (mp
->rx_skb
[curr
]) {
927 dev_kfree_skb(mp
->rx_skb
[curr
]);
932 if (mp
->rx_ring_skbs
)
934 "%s: Error in freeing Rx Ring. %d skb's still"
935 " stuck in RX Ring - ignoring them\n", dev
->name
,
938 if (mp
->rx_sram_size
)
939 iounmap(mp
->p_rx_desc_area
);
941 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
942 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
948 * This function is used when closing the network device.
949 * It updates the hardware,
950 * release all memory that holds buffers and descriptors and release the IRQ.
951 * Input : a pointer to the device structure
952 * Output : zero if success , nonzero if fails
955 /* Helper function for mv643xx_eth_stop */
957 static int mv643xx_eth_real_stop(struct net_device
*dev
)
959 struct mv643xx_private
*mp
= netdev_priv(dev
);
960 unsigned int port_num
= mp
->port_num
;
962 /* Mask RX buffer and TX end interrupt */
963 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
), 0);
965 /* Mask phy and link status changes interrupts */
966 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
), 0);
968 /* ensure previous writes have taken effect */
969 mv_read(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
));
972 netif_poll_disable(dev
);
974 netif_carrier_off(dev
);
975 netif_stop_queue(dev
);
977 eth_port_reset(mp
->port_num
);
979 mv643xx_eth_free_tx_rings(dev
);
980 mv643xx_eth_free_rx_rings(dev
);
983 netif_poll_enable(dev
);
989 static int mv643xx_eth_stop(struct net_device
*dev
)
991 mv643xx_eth_real_stop(dev
);
993 free_irq(dev
->irq
, dev
);
999 static void mv643xx_tx(struct net_device
*dev
)
1001 struct mv643xx_private
*mp
= netdev_priv(dev
);
1002 struct pkt_info pkt_info
;
1004 while (eth_tx_return_desc(mp
, &pkt_info
) == ETH_OK
) {
1005 if (pkt_info
.cmd_sts
& ETH_TX_FIRST_DESC
)
1006 dma_unmap_single(NULL
, pkt_info
.buf_ptr
,
1010 dma_unmap_page(NULL
, pkt_info
.buf_ptr
,
1014 if (pkt_info
.return_info
)
1015 dev_kfree_skb_irq(pkt_info
.return_info
);
1018 if (netif_queue_stopped(dev
) &&
1019 mp
->tx_ring_size
> mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
)
1020 netif_wake_queue(dev
);
1026 * This function is used in case of NAPI
1028 static int mv643xx_poll(struct net_device
*dev
, int *budget
)
1030 struct mv643xx_private
*mp
= netdev_priv(dev
);
1031 int done
= 1, orig_budget
, work_done
;
1032 unsigned int port_num
= mp
->port_num
;
1034 #ifdef MV643XX_TX_FAST_REFILL
1035 if (++mp
->tx_clean_threshold
> 5) {
1037 mp
->tx_clean_threshold
= 0;
1041 if ((mv_read(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1042 != (u32
) mp
->rx_used_desc_q
) {
1043 orig_budget
= *budget
;
1044 if (orig_budget
> dev
->quota
)
1045 orig_budget
= dev
->quota
;
1046 work_done
= mv643xx_eth_receive_queue(dev
, orig_budget
);
1047 mp
->rx_task
.func(dev
);
1048 *budget
-= work_done
;
1049 dev
->quota
-= work_done
;
1050 if (work_done
>= orig_budget
)
1055 netif_rx_complete(dev
);
1056 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_REG(port_num
), 0);
1057 mv_write(MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1058 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1059 INT_CAUSE_UNMASK_ALL
);
1060 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1061 INT_CAUSE_UNMASK_ALL_EXT
);
1064 return done
? 0 : 1;
1068 /* Hardware can't handle unaligned fragments smaller than 9 bytes.
1069 * This helper function detects that case.
1072 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
1077 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1078 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1079 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7)
1088 * mv643xx_eth_start_xmit
1090 * This function is queues a packet in the Tx descriptor for
1093 * Input : skb - a pointer to socket buffer
1094 * dev - a pointer to the required port
1096 * Output : zero upon success
1098 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1100 struct mv643xx_private
*mp
= netdev_priv(dev
);
1101 struct net_device_stats
*stats
= &mp
->stats
;
1102 ETH_FUNC_RET_STATUS status
;
1103 unsigned long flags
;
1104 struct pkt_info pkt_info
;
1106 if (netif_queue_stopped(dev
)) {
1108 "%s: Tried sending packet when interface is stopped\n",
1113 /* This is a hard error, log it. */
1114 if ((mp
->tx_ring_size
- mp
->tx_ring_skbs
) <=
1115 (skb_shinfo(skb
)->nr_frags
+ 1)) {
1116 netif_stop_queue(dev
);
1118 "%s: Bug in mv643xx_eth - Trying to transmit when"
1119 " queue full !\n", dev
->name
);
1123 /* Paranoid check - this shouldn't happen */
1125 stats
->tx_dropped
++;
1126 printk(KERN_ERR
"mv64320_eth paranoid check failed\n");
1130 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1131 if (has_tiny_unaligned_frags(skb
)) {
1132 if ((skb_linearize(skb
, GFP_ATOMIC
) != 0)) {
1133 stats
->tx_dropped
++;
1134 printk(KERN_DEBUG
"%s: failed to linearize tiny "
1135 "unaligned fragment\n", dev
->name
);
1140 spin_lock_irqsave(&mp
->lock
, flags
);
1142 if (!skb_shinfo(skb
)->nr_frags
) {
1143 if (skb
->ip_summed
!= CHECKSUM_HW
) {
1144 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1145 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1148 5 << ETH_TX_IHL_SHIFT
;
1149 pkt_info
.l4i_chk
= 0;
1152 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
|
1155 ETH_GEN_TCP_UDP_CHECKSUM
|
1156 ETH_GEN_IP_V_4_CHECKSUM
|
1157 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1158 /* CPU already calculated pseudo header checksum. */
1159 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) {
1160 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1161 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1162 } else if (skb
->nh
.iph
->protocol
== IPPROTO_TCP
)
1163 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1166 "%s: chksum proto != TCP or UDP\n",
1168 spin_unlock_irqrestore(&mp
->lock
, flags
);
1172 pkt_info
.byte_cnt
= skb
->len
;
1173 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1175 pkt_info
.return_info
= skb
;
1176 status
= eth_port_send(mp
, &pkt_info
);
1177 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1178 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1180 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1184 /* first frag which is skb header */
1185 pkt_info
.byte_cnt
= skb_headlen(skb
);
1186 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
1189 pkt_info
.l4i_chk
= 0;
1190 pkt_info
.return_info
= 0;
1192 if (skb
->ip_summed
!= CHECKSUM_HW
)
1193 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1194 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1195 5 << ETH_TX_IHL_SHIFT
;
1197 pkt_info
.cmd_sts
= ETH_TX_FIRST_DESC
|
1198 ETH_GEN_TCP_UDP_CHECKSUM
|
1199 ETH_GEN_IP_V_4_CHECKSUM
|
1200 skb
->nh
.iph
->ihl
<< ETH_TX_IHL_SHIFT
;
1201 /* CPU already calculated pseudo header checksum. */
1202 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
) {
1203 pkt_info
.cmd_sts
|= ETH_UDP_FRAME
;
1204 pkt_info
.l4i_chk
= skb
->h
.uh
->check
;
1205 } else if (skb
->nh
.iph
->protocol
== IPPROTO_TCP
)
1206 pkt_info
.l4i_chk
= skb
->h
.th
->check
;
1209 "%s: chksum proto != TCP or UDP\n",
1211 spin_unlock_irqrestore(&mp
->lock
, flags
);
1216 status
= eth_port_send(mp
, &pkt_info
);
1217 if (status
!= ETH_OK
) {
1218 if ((status
== ETH_ERROR
))
1220 "%s: Error on transmitting packet\n",
1222 if (status
== ETH_QUEUE_FULL
)
1223 printk("Error on Queue Full \n");
1224 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1225 printk("Tx resource error \n");
1227 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1229 /* Check for the remaining frags */
1230 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1231 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1232 pkt_info
.l4i_chk
= 0x0000;
1233 pkt_info
.cmd_sts
= 0x00000000;
1235 /* Last Frag enables interrupt and frees the skb */
1236 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1237 pkt_info
.cmd_sts
|= ETH_TX_ENABLE_INTERRUPT
|
1239 pkt_info
.return_info
= skb
;
1241 pkt_info
.return_info
= 0;
1243 pkt_info
.l4i_chk
= 0;
1244 pkt_info
.byte_cnt
= this_frag
->size
;
1246 pkt_info
.buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1247 this_frag
->page_offset
,
1251 status
= eth_port_send(mp
, &pkt_info
);
1253 if (status
!= ETH_OK
) {
1254 if ((status
== ETH_ERROR
))
1255 printk(KERN_ERR
"%s: Error on "
1256 "transmitting packet\n",
1259 if (status
== ETH_QUEUE_LAST_RESOURCE
)
1260 printk("Tx resource error \n");
1262 if (status
== ETH_QUEUE_FULL
)
1263 printk("Queue is full \n");
1265 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1269 spin_lock_irqsave(&mp
->lock
, flags
);
1271 pkt_info
.cmd_sts
= ETH_TX_ENABLE_INTERRUPT
| ETH_TX_FIRST_DESC
|
1273 pkt_info
.l4i_chk
= 0;
1274 pkt_info
.byte_cnt
= skb
->len
;
1275 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
, skb
->len
,
1277 pkt_info
.return_info
= skb
;
1278 status
= eth_port_send(mp
, &pkt_info
);
1279 if ((status
== ETH_ERROR
) || (status
== ETH_QUEUE_FULL
))
1280 printk(KERN_ERR
"%s: Error on transmitting packet\n",
1282 stats
->tx_bytes
+= pkt_info
.byte_cnt
;
1285 /* Check if TX queue can handle another skb. If not, then
1286 * signal higher layers to stop requesting TX
1288 if (mp
->tx_ring_size
<= (mp
->tx_ring_skbs
+ MAX_DESCS_PER_SKB
))
1290 * Stop getting skb's from upper layers.
1291 * Getting skb's from upper layers will be enabled again after
1292 * packets are released.
1294 netif_stop_queue(dev
);
1296 /* Update statistics and start of transmittion time */
1297 stats
->tx_packets
++;
1298 dev
->trans_start
= jiffies
;
1300 spin_unlock_irqrestore(&mp
->lock
, flags
);
1302 return 0; /* success */
1306 * mv643xx_eth_get_stats
1308 * Returns a pointer to the interface statistics.
1310 * Input : dev - a pointer to the required interface
1312 * Output : a pointer to the interface's statistics
1315 static struct net_device_stats
*mv643xx_eth_get_stats(struct net_device
*dev
)
1317 struct mv643xx_private
*mp
= netdev_priv(dev
);
1322 #ifdef CONFIG_NET_POLL_CONTROLLER
1323 static inline void mv643xx_enable_irq(struct mv643xx_private
*mp
)
1325 int port_num
= mp
->port_num
;
1326 unsigned long flags
;
1328 spin_lock_irqsave(&mp
->lock
, flags
);
1329 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1330 INT_CAUSE_UNMASK_ALL
);
1331 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1332 INT_CAUSE_UNMASK_ALL_EXT
);
1333 spin_unlock_irqrestore(&mp
->lock
, flags
);
1336 static inline void mv643xx_disable_irq(struct mv643xx_private
*mp
)
1338 int port_num
= mp
->port_num
;
1339 unsigned long flags
;
1341 spin_lock_irqsave(&mp
->lock
, flags
);
1342 mv_write(MV643XX_ETH_INTERRUPT_MASK_REG(port_num
),
1343 INT_CAUSE_MASK_ALL
);
1344 mv_write(MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port_num
),
1345 INT_CAUSE_MASK_ALL_EXT
);
1346 spin_unlock_irqrestore(&mp
->lock
, flags
);
1349 static void mv643xx_netpoll(struct net_device
*netdev
)
1351 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1353 mv643xx_disable_irq(mp
);
1354 mv643xx_eth_int_handler(netdev
->irq
, netdev
, NULL
);
1355 mv643xx_enable_irq(mp
);
1362 * First function called after registering the network device.
1363 * It's purpose is to initialize the device as an ethernet device,
1364 * fill the ethernet device structure with pointers * to functions,
1365 * and set the MAC address of the interface
1367 * Input : struct device *
1368 * Output : -ENOMEM if failed , 0 if success
1370 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1372 struct mv643xx_eth_platform_data
*pd
;
1373 int port_num
= pdev
->id
;
1374 struct mv643xx_private
*mp
;
1375 struct net_device
*dev
;
1377 struct resource
*res
;
1380 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1384 platform_set_drvdata(pdev
, dev
);
1386 mp
= netdev_priv(dev
);
1388 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1390 dev
->irq
= res
->start
;
1392 mp
->port_num
= port_num
;
1394 dev
->open
= mv643xx_eth_open
;
1395 dev
->stop
= mv643xx_eth_stop
;
1396 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1397 dev
->get_stats
= mv643xx_eth_get_stats
;
1398 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1399 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1401 /* No need to Tx Timeout */
1402 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1404 dev
->poll
= mv643xx_poll
;
1408 #ifdef CONFIG_NET_POLL_CONTROLLER
1409 dev
->poll_controller
= mv643xx_netpoll
;
1412 dev
->watchdog_timeo
= 2 * HZ
;
1413 dev
->tx_queue_len
= mp
->tx_ring_size
;
1415 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1416 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1418 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1419 #ifdef MAX_SKB_FRAGS
1421 * Zero copy can only work if we use Discovery II memory. Else, we will
1422 * have to map the buffers to ISA memory which is only 16 MB
1424 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_HW_CSUM
;
1428 /* Configure the timeout task */
1429 INIT_WORK(&mp
->tx_timeout_task
,
1430 (void (*)(void *))mv643xx_eth_tx_timeout_task
, dev
);
1432 spin_lock_init(&mp
->lock
);
1434 /* set default config values */
1435 eth_port_uc_addr_get(dev
, dev
->dev_addr
);
1436 mp
->port_config
= MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE
;
1437 mp
->port_config_extend
= MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE
;
1438 mp
->port_sdma_config
= MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE
;
1439 mp
->port_serial_control
= MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE
;
1440 mp
->rx_ring_size
= MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1441 mp
->tx_ring_size
= MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1443 pd
= pdev
->dev
.platform_data
;
1445 if (pd
->mac_addr
!= NULL
)
1446 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1448 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1449 ethernet_phy_set(port_num
, pd
->phy_addr
);
1451 if (pd
->port_config
|| pd
->force_port_config
)
1452 mp
->port_config
= pd
->port_config
;
1454 if (pd
->port_config_extend
|| pd
->force_port_config_extend
)
1455 mp
->port_config_extend
= pd
->port_config_extend
;
1457 if (pd
->port_sdma_config
|| pd
->force_port_sdma_config
)
1458 mp
->port_sdma_config
= pd
->port_sdma_config
;
1460 if (pd
->port_serial_control
|| pd
->force_port_serial_control
)
1461 mp
->port_serial_control
= pd
->port_serial_control
;
1463 if (pd
->rx_queue_size
)
1464 mp
->rx_ring_size
= pd
->rx_queue_size
;
1466 if (pd
->tx_queue_size
)
1467 mp
->tx_ring_size
= pd
->tx_queue_size
;
1469 if (pd
->tx_sram_size
) {
1470 mp
->tx_sram_size
= pd
->tx_sram_size
;
1471 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1474 if (pd
->rx_sram_size
) {
1475 mp
->rx_sram_size
= pd
->rx_sram_size
;
1476 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1480 err
= ethernet_phy_detect(port_num
);
1482 pr_debug("MV643xx ethernet port %d: "
1483 "No PHY detected at addr %d\n",
1484 port_num
, ethernet_phy_get(port_num
));
1488 err
= register_netdev(dev
);
1494 "%s: port %d with MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
1495 dev
->name
, port_num
, p
[0], p
[1], p
[2], p
[3], p
[4], p
[5]);
1497 if (dev
->features
& NETIF_F_SG
)
1498 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1500 if (dev
->features
& NETIF_F_IP_CSUM
)
1501 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1504 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1505 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1509 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1514 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1517 if (mp
->tx_sram_size
> 0)
1518 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1528 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1530 struct net_device
*dev
= platform_get_drvdata(pdev
);
1532 unregister_netdev(dev
);
1533 flush_scheduled_work();
1536 platform_set_drvdata(pdev
, NULL
);
1540 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1542 struct resource
*res
;
1544 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1546 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1550 mv643xx_eth_shared_base
= ioremap(res
->start
,
1551 MV643XX_ETH_SHARED_REGS_SIZE
);
1552 if (mv643xx_eth_shared_base
== NULL
)
1559 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
1561 iounmap(mv643xx_eth_shared_base
);
1562 mv643xx_eth_shared_base
= NULL
;
1567 static struct platform_driver mv643xx_eth_driver
= {
1568 .probe
= mv643xx_eth_probe
,
1569 .remove
= mv643xx_eth_remove
,
1571 .name
= MV643XX_ETH_NAME
,
1575 static struct platform_driver mv643xx_eth_shared_driver
= {
1576 .probe
= mv643xx_eth_shared_probe
,
1577 .remove
= mv643xx_eth_shared_remove
,
1579 .name
= MV643XX_ETH_SHARED_NAME
,
1584 * mv643xx_init_module
1586 * Registers the network drivers into the Linux kernel
1592 static int __init
mv643xx_init_module(void)
1596 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
1598 rc
= platform_driver_register(&mv643xx_eth_driver
);
1600 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1606 * mv643xx_cleanup_module
1608 * Registers the network drivers into the Linux kernel
1614 static void __exit
mv643xx_cleanup_module(void)
1616 platform_driver_unregister(&mv643xx_eth_driver
);
1617 platform_driver_unregister(&mv643xx_eth_shared_driver
);
1620 module_init(mv643xx_init_module
);
1621 module_exit(mv643xx_cleanup_module
);
1623 MODULE_LICENSE("GPL");
1624 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
1625 " and Dale Farnsworth");
1626 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
1629 * The second part is the low level driver of the gigE ethernet ports.
1633 * Marvell's Gigabit Ethernet controller low level driver
1636 * This file introduce low level API to Marvell's Gigabit Ethernet
1637 * controller. This Gigabit Ethernet Controller driver API controls
1638 * 1) Operations (i.e. port init, start, reset etc').
1639 * 2) Data flow (i.e. port send, receive etc').
1640 * Each Gigabit Ethernet port is controlled via
1641 * struct mv643xx_private.
1642 * This struct includes user configuration information as well as
1643 * driver internal data needed for its operations.
1645 * Supported Features:
1646 * - This low level driver is OS independent. Allocating memory for
1647 * the descriptor rings and buffers are not within the scope of
1649 * - The user is free from Rx/Tx queue managing.
1650 * - This low level driver introduce functionality API that enable
1651 * the to operate Marvell's Gigabit Ethernet Controller in a
1653 * - Simple Gigabit Ethernet port operation API.
1654 * - Simple Gigabit Ethernet port data flow API.
1655 * - Data flow and operation API support per queue functionality.
1656 * - Support cached descriptors for better performance.
1657 * - Enable access to all four DRAM banks and internal SRAM memory
1659 * - PHY access and control API.
1660 * - Port control register configuration API.
1661 * - Full control over Unicast and Multicast MAC configurations.
1665 * Initialization phase
1666 * This phase complete the initialization of the the
1667 * mv643xx_private struct.
1668 * User information regarding port configuration has to be set
1669 * prior to calling the port initialization routine.
1671 * In this phase any port Tx/Rx activity is halted, MIB counters
1672 * are cleared, PHY address is set according to user parameter and
1673 * access to DRAM and internal SRAM memory spaces.
1675 * Driver ring initialization
1676 * Allocating memory for the descriptor rings and buffers is not
1677 * within the scope of this driver. Thus, the user is required to
1678 * allocate memory for the descriptors ring and buffers. Those
1679 * memory parameters are used by the Rx and Tx ring initialization
1680 * routines in order to curve the descriptor linked list in a form
1682 * Note: Pay special attention to alignment issues when using
1683 * cached descriptors/buffers. In this phase the driver store
1684 * information in the mv643xx_private struct regarding each queue
1688 * This phase prepares the Ethernet port for Rx and Tx activity.
1689 * It uses the information stored in the mv643xx_private struct to
1690 * initialize the various port registers.
1693 * All packet references to/from the driver are done using
1695 * This struct is a unified struct used with Rx and Tx operations.
1696 * This way the user is not required to be familiar with neither
1697 * Tx nor Rx descriptors structures.
1698 * The driver's descriptors rings are management by indexes.
1699 * Those indexes controls the ring resources and used to indicate
1700 * a SW resource error:
1702 * This index points to the current available resource for use. For
1703 * example in Rx process this index will point to the descriptor
1704 * that will be passed to the user upon calling the receive
1705 * routine. In Tx process, this index will point to the descriptor
1706 * that will be assigned with the user packet info and transmitted.
1708 * This index points to the descriptor that need to restore its
1709 * resources. For example in Rx process, using the Rx buffer return
1710 * API will attach the buffer returned in packet info to the
1711 * descriptor pointed by 'used'. In Tx process, using the Tx
1712 * descriptor return will merely return the user packet info with
1713 * the command status of the transmitted buffer pointed by the
1714 * 'used' index. Nevertheless, it is essential to use this routine
1715 * to update the 'used' index.
1717 * This index supports Tx Scatter-Gather. It points to the first
1718 * descriptor of a packet assembled of multiple buffers. For
1719 * example when in middle of Such packet we have a Tx resource
1720 * error the 'curr' index get the value of 'first' to indicate
1721 * that the ring returned to its state before trying to transmit
1724 * Receive operation:
1725 * The eth_port_receive API set the packet information struct,
1726 * passed by the caller, with received information from the
1727 * 'current' SDMA descriptor.
1728 * It is the user responsibility to return this resource back
1729 * to the Rx descriptor ring to enable the reuse of this source.
1730 * Return Rx resource is done using the eth_rx_return_buff API.
1732 * Transmit operation:
1733 * The eth_port_send API supports Scatter-Gather which enables to
1734 * send a packet spanned over multiple buffers. This means that
1735 * for each packet info structure given by the user and put into
1736 * the Tx descriptors ring, will be transmitted only if the 'LAST'
1737 * bit will be set in the packet info command status field. This
1738 * API also consider restriction regarding buffer alignments and
1740 * The user must return a Tx resource after ensuring the buffer
1741 * has been transmitted to enable the Tx ring indexes to update.
1744 * This device is on-board. No jumper diagram is necessary.
1746 * EXTERNAL INTERFACE
1748 * Prior to calling the initialization routine eth_port_init() the user
1749 * must set the following fields under mv643xx_private struct:
1750 * port_num User Ethernet port number.
1751 * port_mac_addr[6] User defined port MAC address.
1752 * port_config User port configuration value.
1753 * port_config_extend User port config extend value.
1754 * port_sdma_config User port SDMA config value.
1755 * port_serial_control User port serial control value.
1757 * This driver data flow is done using the struct pkt_info which
1758 * is a unified struct for Rx and Tx operations:
1760 * byte_cnt Tx/Rx descriptor buffer byte count.
1761 * l4i_chk CPU provided TCP Checksum. For Tx operation
1763 * cmd_sts Tx/Rx descriptor command status.
1764 * buf_ptr Tx/Rx descriptor buffer pointer.
1765 * return_info Tx/Rx user resource return information.
1769 /* SDMA command macros */
1770 #define ETH_ENABLE_TX_QUEUE(eth_port) \
1771 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), 1)
1776 static int ethernet_phy_get(unsigned int eth_port_num
);
1777 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
1779 /* Ethernet Port routines */
1780 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
1784 * eth_port_init - Initialize the Ethernet port driver
1787 * This function prepares the ethernet port to start its activity:
1788 * 1) Completes the ethernet port driver struct initialization toward port
1790 * 2) Resets the device to a quiescent state in case of warm reboot.
1791 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
1792 * 4) Clean MAC tables. The reset status of those tables is unknown.
1793 * 5) Set PHY address.
1794 * Note: Call this routine prior to eth_port_start routine and after
1795 * setting user values in the user fields of Ethernet port control
1799 * struct mv643xx_private *mp Ethernet port control struct
1807 static void eth_port_init(struct mv643xx_private
*mp
)
1809 mp
->port_rx_queue_command
= 0;
1810 mp
->port_tx_queue_command
= 0;
1812 mp
->rx_resource_err
= 0;
1813 mp
->tx_resource_err
= 0;
1815 eth_port_reset(mp
->port_num
);
1817 eth_port_init_mac_tables(mp
->port_num
);
1819 ethernet_phy_reset(mp
->port_num
);
1823 * eth_port_start - Start the Ethernet port activity.
1826 * This routine prepares the Ethernet port for Rx and Tx activity:
1827 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
1828 * has been initialized a descriptor's ring (using
1829 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
1830 * 2. Initialize and enable the Ethernet configuration port by writing to
1831 * the port's configuration and command registers.
1832 * 3. Initialize and enable the SDMA by writing to the SDMA's
1833 * configuration and command registers. After completing these steps,
1834 * the ethernet port SDMA can starts to perform Rx and Tx activities.
1836 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
1837 * to calling this function (use ether_init_tx_desc_ring for Tx queues
1838 * and ether_init_rx_desc_ring for Rx queues).
1841 * struct mv643xx_private *mp Ethernet port control struct
1844 * Ethernet port is ready to receive and transmit.
1849 static void eth_port_start(struct mv643xx_private
*mp
)
1851 unsigned int port_num
= mp
->port_num
;
1852 int tx_curr_desc
, rx_curr_desc
;
1854 /* Assignment of Tx CTRP of given queue */
1855 tx_curr_desc
= mp
->tx_curr_desc_q
;
1856 mv_write(MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1857 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
1859 /* Assignment of Rx CRDP of given queue */
1860 rx_curr_desc
= mp
->rx_curr_desc_q
;
1861 mv_write(MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
1862 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
1864 /* Add the assigned Ethernet address to the port's address table */
1865 eth_port_uc_addr_set(port_num
, mp
->port_mac_addr
);
1867 /* Assign port configuration and command. */
1868 mv_write(MV643XX_ETH_PORT_CONFIG_REG(port_num
), mp
->port_config
);
1870 mv_write(MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port_num
),
1871 mp
->port_config_extend
);
1874 /* Increase the Rx side buffer size if supporting GigE */
1875 if (mp
->port_serial_control
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
1876 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1877 (mp
->port_serial_control
& 0xfff1ffff) | (0x5 << 17));
1879 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1880 mp
->port_serial_control
);
1882 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
),
1883 mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
)) |
1884 MV643XX_ETH_SERIAL_PORT_ENABLE
);
1886 /* Assign port SDMA configuration */
1887 mv_write(MV643XX_ETH_SDMA_CONFIG_REG(port_num
),
1888 mp
->port_sdma_config
);
1890 /* Enable port Rx. */
1891 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
1892 mp
->port_rx_queue_command
);
1894 /* Disable port bandwidth limits by clearing MTU register */
1895 mv_write(MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
1899 * eth_port_uc_addr_set - This function Set the port Unicast address.
1902 * This function Set the port Ethernet MAC address.
1905 * unsigned int eth_port_num Port number.
1906 * char * p_addr Address to be set
1909 * Set MAC address low and high registers. also calls eth_port_uc_addr()
1910 * To set the unicast table with the proper information.
1916 static void eth_port_uc_addr_set(unsigned int eth_port_num
,
1917 unsigned char *p_addr
)
1922 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
1923 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
1926 mv_write(MV643XX_ETH_MAC_ADDR_LOW(eth_port_num
), mac_l
);
1927 mv_write(MV643XX_ETH_MAC_ADDR_HIGH(eth_port_num
), mac_h
);
1929 /* Accept frames of this address */
1930 eth_port_uc_addr(eth_port_num
, p_addr
[5], ACCEPT_MAC_ADDR
);
1936 * eth_port_uc_addr_get - This function retrieves the port Unicast address
1937 * (MAC address) from the ethernet hw registers.
1940 * This function retrieves the port Ethernet MAC address.
1943 * unsigned int eth_port_num Port number.
1944 * char *MacAddr pointer where the MAC address is stored
1947 * Copy the MAC address to the location pointed to by MacAddr
1953 static void eth_port_uc_addr_get(struct net_device
*dev
, unsigned char *p_addr
)
1955 struct mv643xx_private
*mp
= netdev_priv(dev
);
1959 mac_h
= mv_read(MV643XX_ETH_MAC_ADDR_HIGH(mp
->port_num
));
1960 mac_l
= mv_read(MV643XX_ETH_MAC_ADDR_LOW(mp
->port_num
));
1962 p_addr
[0] = (mac_h
>> 24) & 0xff;
1963 p_addr
[1] = (mac_h
>> 16) & 0xff;
1964 p_addr
[2] = (mac_h
>> 8) & 0xff;
1965 p_addr
[3] = mac_h
& 0xff;
1966 p_addr
[4] = (mac_l
>> 8) & 0xff;
1967 p_addr
[5] = mac_l
& 0xff;
1971 * eth_port_uc_addr - This function Set the port unicast address table
1974 * This function locates the proper entry in the Unicast table for the
1975 * specified MAC nibble and sets its properties according to function
1979 * unsigned int eth_port_num Port number.
1980 * unsigned char uc_nibble Unicast MAC Address last nibble.
1981 * int option 0 = Add, 1 = remove address.
1984 * This function add/removes MAC addresses from the port unicast address
1988 * true is output succeeded.
1989 * false if option parameter is invalid.
1992 static int eth_port_uc_addr(unsigned int eth_port_num
, unsigned char uc_nibble
,
1995 unsigned int unicast_reg
;
1996 unsigned int tbl_offset
;
1997 unsigned int reg_offset
;
1999 /* Locate the Unicast table entry */
2000 uc_nibble
= (0xf & uc_nibble
);
2001 tbl_offset
= (uc_nibble
/ 4) * 4; /* Register offset from unicast table base */
2002 reg_offset
= uc_nibble
% 4; /* Entry offset within the above register */
2005 case REJECT_MAC_ADDR
:
2006 /* Clear accepts frame bit at given unicast DA table entry */
2007 unicast_reg
= mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2008 (eth_port_num
) + tbl_offset
));
2010 unicast_reg
&= (0x0E << (8 * reg_offset
));
2012 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2013 (eth_port_num
) + tbl_offset
), unicast_reg
);
2016 case ACCEPT_MAC_ADDR
:
2017 /* Set accepts frame bit at unicast DA filter table entry */
2019 mv_read((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2020 (eth_port_num
) + tbl_offset
));
2022 unicast_reg
|= (0x01 << (8 * reg_offset
));
2024 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2025 (eth_port_num
) + tbl_offset
), unicast_reg
);
2037 * The entries in each table are indexed by a hash of a packet's MAC
2038 * address. One bit in each entry determines whether the packet is
2039 * accepted. There are 4 entries (each 8 bits wide) in each register
2040 * of the table. The bits in each entry are defined as follows:
2041 * 0 Accept=1, Drop=0
2042 * 3-1 Queue (ETH_Q0=0)
2045 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
)
2047 unsigned int table_reg
;
2048 unsigned int tbl_offset
;
2049 unsigned int reg_offset
;
2051 tbl_offset
= (entry
/ 4) * 4; /* Register offset of DA table entry */
2052 reg_offset
= entry
% 4; /* Entry offset within the register */
2054 /* Set "accepts frame bit" at specified table entry */
2055 table_reg
= mv_read(table
+ tbl_offset
);
2056 table_reg
|= 0x01 << (8 * reg_offset
);
2057 mv_write(table
+ tbl_offset
, table_reg
);
2061 * eth_port_mc_addr - Multicast address settings.
2063 * The MV device supports multicast using two tables:
2064 * 1) Special Multicast Table for MAC addresses of the form
2065 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2066 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2067 * Table entries in the DA-Filter table.
2068 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2069 * is used as an index to the Other Multicast Table entries in the
2070 * DA-Filter table. This function calculates the CRC-8bit value.
2071 * In either case, eth_port_set_filter_table_entry() is then called
2072 * to set to set the actual table entry.
2074 static void eth_port_mc_addr(unsigned int eth_port_num
, unsigned char *p_addr
)
2078 unsigned char crc_result
= 0;
2084 if ((p_addr
[0] == 0x01) && (p_addr
[1] == 0x00) &&
2085 (p_addr
[2] == 0x5E) && (p_addr
[3] == 0x00) && (p_addr
[4] == 0x00)) {
2086 table
= MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2088 eth_port_set_filter_table_entry(table
, p_addr
[5]);
2092 /* Calculate CRC-8 out of the given address */
2093 mac_h
= (p_addr
[0] << 8) | (p_addr
[1]);
2094 mac_l
= (p_addr
[2] << 24) | (p_addr
[3] << 16) |
2095 (p_addr
[4] << 8) | (p_addr
[5] << 0);
2097 for (i
= 0; i
< 32; i
++)
2098 mac_array
[i
] = (mac_l
>> i
) & 0x1;
2099 for (i
= 32; i
< 48; i
++)
2100 mac_array
[i
] = (mac_h
>> (i
- 32)) & 0x1;
2102 crc
[0] = mac_array
[45] ^ mac_array
[43] ^ mac_array
[40] ^ mac_array
[39] ^
2103 mac_array
[35] ^ mac_array
[34] ^ mac_array
[31] ^ mac_array
[30] ^
2104 mac_array
[28] ^ mac_array
[23] ^ mac_array
[21] ^ mac_array
[19] ^
2105 mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^ mac_array
[12] ^
2106 mac_array
[8] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[0];
2108 crc
[1] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2109 mac_array
[41] ^ mac_array
[39] ^ mac_array
[36] ^ mac_array
[34] ^
2110 mac_array
[32] ^ mac_array
[30] ^ mac_array
[29] ^ mac_array
[28] ^
2111 mac_array
[24] ^ mac_array
[23] ^ mac_array
[22] ^ mac_array
[21] ^
2112 mac_array
[20] ^ mac_array
[18] ^ mac_array
[17] ^ mac_array
[16] ^
2113 mac_array
[15] ^ mac_array
[14] ^ mac_array
[13] ^ mac_array
[12] ^
2114 mac_array
[9] ^ mac_array
[6] ^ mac_array
[1] ^ mac_array
[0];
2116 crc
[2] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[44] ^ mac_array
[43] ^
2117 mac_array
[42] ^ mac_array
[39] ^ mac_array
[37] ^ mac_array
[34] ^
2118 mac_array
[33] ^ mac_array
[29] ^ mac_array
[28] ^ mac_array
[25] ^
2119 mac_array
[24] ^ mac_array
[22] ^ mac_array
[17] ^ mac_array
[15] ^
2120 mac_array
[13] ^ mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^
2121 mac_array
[6] ^ mac_array
[2] ^ mac_array
[1] ^ mac_array
[0];
2123 crc
[3] = mac_array
[47] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2124 mac_array
[40] ^ mac_array
[38] ^ mac_array
[35] ^ mac_array
[34] ^
2125 mac_array
[30] ^ mac_array
[29] ^ mac_array
[26] ^ mac_array
[25] ^
2126 mac_array
[23] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^
2127 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[7] ^
2128 mac_array
[3] ^ mac_array
[2] ^ mac_array
[1];
2130 crc
[4] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[41] ^
2131 mac_array
[39] ^ mac_array
[36] ^ mac_array
[35] ^ mac_array
[31] ^
2132 mac_array
[30] ^ mac_array
[27] ^ mac_array
[26] ^ mac_array
[24] ^
2133 mac_array
[19] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[14] ^
2134 mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^ mac_array
[4] ^
2135 mac_array
[3] ^ mac_array
[2];
2137 crc
[5] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[45] ^ mac_array
[42] ^
2138 mac_array
[40] ^ mac_array
[37] ^ mac_array
[36] ^ mac_array
[32] ^
2139 mac_array
[31] ^ mac_array
[28] ^ mac_array
[27] ^ mac_array
[25] ^
2140 mac_array
[20] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[15] ^
2141 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[5] ^
2142 mac_array
[4] ^ mac_array
[3];
2144 crc
[6] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[43] ^ mac_array
[41] ^
2145 mac_array
[38] ^ mac_array
[37] ^ mac_array
[33] ^ mac_array
[32] ^
2146 mac_array
[29] ^ mac_array
[28] ^ mac_array
[26] ^ mac_array
[21] ^
2147 mac_array
[19] ^ mac_array
[17] ^ mac_array
[16] ^ mac_array
[14] ^
2148 mac_array
[12] ^ mac_array
[10] ^ mac_array
[6] ^ mac_array
[5] ^
2151 crc
[7] = mac_array
[47] ^ mac_array
[44] ^ mac_array
[42] ^ mac_array
[39] ^
2152 mac_array
[38] ^ mac_array
[34] ^ mac_array
[33] ^ mac_array
[30] ^
2153 mac_array
[29] ^ mac_array
[27] ^ mac_array
[22] ^ mac_array
[20] ^
2154 mac_array
[18] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[13] ^
2155 mac_array
[11] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[5];
2157 for (i
= 0; i
< 8; i
++)
2158 crc_result
= crc_result
| (crc
[i
] << i
);
2160 table
= MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
);
2161 eth_port_set_filter_table_entry(table
, crc_result
);
2165 * Set the entire multicast list based on dev->mc_list.
2167 static void eth_port_set_multicast_list(struct net_device
*dev
)
2170 struct dev_mc_list
*mc_list
;
2173 struct mv643xx_private
*mp
= netdev_priv(dev
);
2174 unsigned int eth_port_num
= mp
->port_num
;
2176 /* If the device is in promiscuous mode or in all multicast mode,
2177 * we will fully populate both multicast tables with accept.
2178 * This is guaranteed to yield a match on all multicast addresses...
2180 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
)) {
2181 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2182 /* Set all entries in DA filter special multicast
2184 * Set for ETH_Q0 for now
2186 * 0 Accept=1, Drop=0
2187 * 3-1 Queue ETH_Q0=0
2190 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2192 /* Set all entries in DA filter other multicast
2194 * Set for ETH_Q0 for now
2196 * 0 Accept=1, Drop=0
2197 * 3-1 Queue ETH_Q0=0
2200 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2205 /* We will clear out multicast tables every time we get the list.
2206 * Then add the entire new list...
2208 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2209 /* Clear DA filter special multicast table (Ex_dFSMT) */
2210 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2211 (eth_port_num
) + table_index
, 0);
2213 /* Clear DA filter other multicast table (Ex_dFOMT) */
2214 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2215 (eth_port_num
) + table_index
, 0);
2218 /* Get pointer to net_device multicast list and add each one... */
2219 for (i
= 0, mc_list
= dev
->mc_list
;
2220 (i
< 256) && (mc_list
!= NULL
) && (i
< dev
->mc_count
);
2221 i
++, mc_list
= mc_list
->next
)
2222 if (mc_list
->dmi_addrlen
== 6)
2223 eth_port_mc_addr(eth_port_num
, mc_list
->dmi_addr
);
2227 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2230 * Go through all the DA filter tables (Unicast, Special Multicast &
2231 * Other Multicast) and set each entry to 0.
2234 * unsigned int eth_port_num Ethernet Port number.
2237 * Multicast and Unicast packets are rejected.
2242 static void eth_port_init_mac_tables(unsigned int eth_port_num
)
2246 /* Clear DA filter unicast table (Ex_dFUT) */
2247 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2248 mv_write((MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE
2249 (eth_port_num
) + table_index
), 0);
2251 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2252 /* Clear DA filter special multicast table (Ex_dFSMT) */
2253 mv_write(MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2254 (eth_port_num
) + table_index
, 0);
2255 /* Clear DA filter other multicast table (Ex_dFOMT) */
2256 mv_write(MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2257 (eth_port_num
) + table_index
, 0);
2262 * eth_clear_mib_counters - Clear all MIB counters
2265 * This function clears all MIB counters of a specific ethernet port.
2266 * A read from the MIB counter will reset the counter.
2269 * unsigned int eth_port_num Ethernet Port number.
2272 * After reading all MIB counters, the counters resets.
2275 * MIB counter value.
2278 static void eth_clear_mib_counters(unsigned int eth_port_num
)
2282 /* Perform dummy reads from MIB counters */
2283 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2285 mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(eth_port_num
) + i
);
2288 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2290 return mv_read(MV643XX_ETH_MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2293 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2295 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2298 p
->good_octets_received
+=
2299 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2300 p
->good_octets_received
+=
2301 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2303 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2304 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2306 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2308 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2309 p
->good_octets_sent
+=
2310 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2312 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2313 offset
<= ETH_MIB_LATE_COLLISION
;
2315 *(u32
*)((char *)p
+ offset
) = read_mib(mp
, offset
);
2319 * ethernet_phy_detect - Detect whether a phy is present
2322 * This function tests whether there is a PHY present on
2323 * the specified port.
2326 * unsigned int eth_port_num Ethernet Port number.
2333 * -ENODEV on failure
2336 static int ethernet_phy_detect(unsigned int port_num
)
2338 unsigned int phy_reg_data0
;
2341 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2342 auto_neg
= phy_reg_data0
& 0x1000;
2343 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2344 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2346 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2347 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2348 return -ENODEV
; /* change didn't take */
2350 phy_reg_data0
^= 0x1000;
2351 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2356 * ethernet_phy_get - Get the ethernet port PHY address.
2359 * This routine returns the given ethernet port PHY address.
2362 * unsigned int eth_port_num Ethernet Port number.
2371 static int ethernet_phy_get(unsigned int eth_port_num
)
2373 unsigned int reg_data
;
2375 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2377 return ((reg_data
>> (5 * eth_port_num
)) & 0x1f);
2381 * ethernet_phy_set - Set the ethernet port PHY address.
2384 * This routine sets the given ethernet port PHY address.
2387 * unsigned int eth_port_num Ethernet Port number.
2388 * int phy_addr PHY address.
2397 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
)
2400 int addr_shift
= 5 * eth_port_num
;
2402 reg_data
= mv_read(MV643XX_ETH_PHY_ADDR_REG
);
2403 reg_data
&= ~(0x1f << addr_shift
);
2404 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2405 mv_write(MV643XX_ETH_PHY_ADDR_REG
, reg_data
);
2409 * ethernet_phy_reset - Reset Ethernet port PHY.
2412 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2415 * unsigned int eth_port_num Ethernet Port number.
2424 static void ethernet_phy_reset(unsigned int eth_port_num
)
2426 unsigned int phy_reg_data
;
2429 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2430 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2431 eth_port_write_smi_reg(eth_port_num
, 0, phy_reg_data
);
2435 * eth_port_reset - Reset Ethernet port
2438 * This routine resets the chip by aborting any SDMA engine activity and
2439 * clearing the MIB counters. The Receiver and the Transmit unit are in
2440 * idle state after this command is performed and the port is disabled.
2443 * unsigned int eth_port_num Ethernet Port number.
2446 * Channel activity is halted.
2452 static void eth_port_reset(unsigned int port_num
)
2454 unsigned int reg_data
;
2456 /* Stop Tx port activity. Check port Tx activity. */
2457 reg_data
= mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
));
2459 if (reg_data
& 0xFF) {
2460 /* Issue stop command for active channels only */
2461 mv_write(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
),
2464 /* Wait for all Tx activity to terminate. */
2465 /* Check port cause register that all Tx queues are stopped */
2466 while (mv_read(MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port_num
))
2471 /* Stop Rx port activity. Check port Rx activity. */
2472 reg_data
= mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
));
2474 if (reg_data
& 0xFF) {
2475 /* Issue stop command for active channels only */
2476 mv_write(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
),
2479 /* Wait for all Rx activity to terminate. */
2480 /* Check port cause register that all Rx queues are stopped */
2481 while (mv_read(MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port_num
))
2486 /* Clear all MIB counters */
2487 eth_clear_mib_counters(port_num
);
2489 /* Reset the Enable bit in the Configuration Register */
2490 reg_data
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
2491 reg_data
&= ~MV643XX_ETH_SERIAL_PORT_ENABLE
;
2492 mv_write(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2496 static int eth_port_autoneg_supported(unsigned int eth_port_num
)
2498 unsigned int phy_reg_data0
;
2500 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data0
);
2502 return phy_reg_data0
& 0x1000;
2505 static int eth_port_link_is_up(unsigned int eth_port_num
)
2507 unsigned int phy_reg_data1
;
2509 eth_port_read_smi_reg(eth_port_num
, 1, &phy_reg_data1
);
2511 if (eth_port_autoneg_supported(eth_port_num
)) {
2512 if (phy_reg_data1
& 0x20) /* auto-neg complete */
2514 } else if (phy_reg_data1
& 0x4) /* link up */
2521 * eth_port_read_smi_reg - Read PHY registers
2524 * This routine utilize the SMI interface to interact with the PHY in
2525 * order to perform PHY register read.
2528 * unsigned int port_num Ethernet Port number.
2529 * unsigned int phy_reg PHY register address offset.
2530 * unsigned int *value Register value buffer.
2533 * Write the value of a specified PHY register into given buffer.
2536 * false if the PHY is busy or read data is not in valid state.
2540 static void eth_port_read_smi_reg(unsigned int port_num
,
2541 unsigned int phy_reg
, unsigned int *value
)
2543 int phy_addr
= ethernet_phy_get(port_num
);
2544 unsigned long flags
;
2547 /* the SMI register is a shared resource */
2548 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2550 /* wait for the SMI register to become available */
2551 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2552 if (i
== PHY_WAIT_ITERATIONS
) {
2553 printk("mv643xx PHY busy timeout, port %d\n", port_num
);
2556 udelay(PHY_WAIT_MICRO_SECONDS
);
2559 mv_write(MV643XX_ETH_SMI_REG
,
2560 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2562 /* now wait for the data to be valid */
2563 for (i
= 0; !(mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2564 if (i
== PHY_WAIT_ITERATIONS
) {
2565 printk("mv643xx PHY read timeout, port %d\n", port_num
);
2568 udelay(PHY_WAIT_MICRO_SECONDS
);
2571 *value
= mv_read(MV643XX_ETH_SMI_REG
) & 0xffff;
2573 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2577 * eth_port_write_smi_reg - Write to PHY registers
2580 * This routine utilize the SMI interface to interact with the PHY in
2581 * order to perform writes to PHY registers.
2584 * unsigned int eth_port_num Ethernet Port number.
2585 * unsigned int phy_reg PHY register address offset.
2586 * unsigned int value Register value.
2589 * Write the given value to the specified PHY register.
2592 * false if the PHY is busy.
2596 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
2597 unsigned int phy_reg
, unsigned int value
)
2601 unsigned long flags
;
2603 phy_addr
= ethernet_phy_get(eth_port_num
);
2605 /* the SMI register is a shared resource */
2606 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2608 /* wait for the SMI register to become available */
2609 for (i
= 0; mv_read(MV643XX_ETH_SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2610 if (i
== PHY_WAIT_ITERATIONS
) {
2611 printk("mv643xx PHY busy timeout, port %d\n",
2615 udelay(PHY_WAIT_MICRO_SECONDS
);
2618 mv_write(MV643XX_ETH_SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2619 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2621 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2625 * eth_port_send - Send an Ethernet packet
2628 * This routine send a given packet described by p_pktinfo parameter. It
2629 * supports transmitting of a packet spaned over multiple buffers. The
2630 * routine updates 'curr' and 'first' indexes according to the packet
2631 * segment passed to the routine. In case the packet segment is first,
2632 * the 'first' index is update. In any case, the 'curr' index is updated.
2633 * If the routine get into Tx resource error it assigns 'curr' index as
2634 * 'first'. This way the function can abort Tx process of multiple
2635 * descriptors per packet.
2638 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2639 * struct pkt_info *p_pkt_info User packet buffer.
2642 * Tx ring 'curr' and 'first' indexes are updated.
2645 * ETH_QUEUE_FULL in case of Tx resource error.
2646 * ETH_ERROR in case the routine can not access Tx desc ring.
2647 * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource.
2651 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2653 * Modified to include the first descriptor pointer in case of SG
2655 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2656 struct pkt_info
*p_pkt_info
)
2658 int tx_desc_curr
, tx_desc_used
, tx_first_desc
, tx_next_desc
;
2659 struct eth_tx_desc
*current_descriptor
;
2660 struct eth_tx_desc
*first_descriptor
;
2662 unsigned long flags
;
2664 /* Do not process Tx ring in case of Tx ring resource error */
2665 if (mp
->tx_resource_err
)
2666 return ETH_QUEUE_FULL
;
2669 * The hardware requires that each buffer that is <= 8 bytes
2670 * in length must be aligned on an 8 byte boundary.
2672 if (p_pkt_info
->byte_cnt
<= 8 && p_pkt_info
->buf_ptr
& 0x7) {
2674 "mv643xx_eth port %d: packet size <= 8 problem\n",
2679 spin_lock_irqsave(&mp
->lock
, flags
);
2682 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2684 /* Get the Tx Desc ring indexes */
2685 tx_desc_curr
= mp
->tx_curr_desc_q
;
2686 tx_desc_used
= mp
->tx_used_desc_q
;
2688 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2690 tx_next_desc
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2692 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2693 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2694 current_descriptor
->l4i_chk
= p_pkt_info
->l4i_chk
;
2695 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2697 command
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
|
2698 ETH_BUFFER_OWNED_BY_DMA
;
2699 if (command
& ETH_TX_FIRST_DESC
) {
2700 tx_first_desc
= tx_desc_curr
;
2701 mp
->tx_first_desc_q
= tx_first_desc
;
2702 first_descriptor
= current_descriptor
;
2703 mp
->tx_first_command
= command
;
2705 tx_first_desc
= mp
->tx_first_desc_q
;
2706 first_descriptor
= &mp
->p_tx_desc_area
[tx_first_desc
];
2707 BUG_ON(first_descriptor
== NULL
);
2708 current_descriptor
->cmd_sts
= command
;
2711 if (command
& ETH_TX_LAST_DESC
) {
2713 first_descriptor
->cmd_sts
= mp
->tx_first_command
;
2716 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2719 * Finish Tx packet. Update first desc in case of Tx resource
2721 tx_first_desc
= tx_next_desc
;
2722 mp
->tx_first_desc_q
= tx_first_desc
;
2725 /* Check for ring index overlap in the Tx desc ring */
2726 if (tx_next_desc
== tx_desc_used
) {
2727 mp
->tx_resource_err
= 1;
2728 mp
->tx_curr_desc_q
= tx_first_desc
;
2730 spin_unlock_irqrestore(&mp
->lock
, flags
);
2732 return ETH_QUEUE_LAST_RESOURCE
;
2735 mp
->tx_curr_desc_q
= tx_next_desc
;
2737 spin_unlock_irqrestore(&mp
->lock
, flags
);
2742 static ETH_FUNC_RET_STATUS
eth_port_send(struct mv643xx_private
*mp
,
2743 struct pkt_info
*p_pkt_info
)
2747 struct eth_tx_desc
*current_descriptor
;
2748 unsigned int command_status
;
2749 unsigned long flags
;
2751 /* Do not process Tx ring in case of Tx ring resource error */
2752 if (mp
->tx_resource_err
)
2753 return ETH_QUEUE_FULL
;
2755 spin_lock_irqsave(&mp
->lock
, flags
);
2758 BUG_ON(mp
->tx_ring_skbs
> mp
->tx_ring_size
);
2760 /* Get the Tx Desc ring indexes */
2761 tx_desc_curr
= mp
->tx_curr_desc_q
;
2762 tx_desc_used
= mp
->tx_used_desc_q
;
2763 current_descriptor
= &mp
->p_tx_desc_area
[tx_desc_curr
];
2765 command_status
= p_pkt_info
->cmd_sts
| ETH_ZERO_PADDING
| ETH_GEN_CRC
;
2766 current_descriptor
->buf_ptr
= p_pkt_info
->buf_ptr
;
2767 current_descriptor
->byte_cnt
= p_pkt_info
->byte_cnt
;
2768 mp
->tx_skb
[tx_desc_curr
] = p_pkt_info
->return_info
;
2770 /* Set last desc with DMA ownership and interrupt enable. */
2772 current_descriptor
->cmd_sts
= command_status
|
2773 ETH_BUFFER_OWNED_BY_DMA
| ETH_TX_ENABLE_INTERRUPT
;
2776 ETH_ENABLE_TX_QUEUE(mp
->port_num
);
2778 /* Finish Tx packet. Update first desc in case of Tx resource error */
2779 tx_desc_curr
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
2781 /* Update the current descriptor */
2782 mp
->tx_curr_desc_q
= tx_desc_curr
;
2784 /* Check for ring index overlap in the Tx desc ring */
2785 if (tx_desc_curr
== tx_desc_used
) {
2786 mp
->tx_resource_err
= 1;
2788 spin_unlock_irqrestore(&mp
->lock
, flags
);
2789 return ETH_QUEUE_LAST_RESOURCE
;
2792 spin_unlock_irqrestore(&mp
->lock
, flags
);
2798 * eth_tx_return_desc - Free all used Tx descriptors
2801 * This routine returns the transmitted packet information to the caller.
2802 * It uses the 'first' index to support Tx desc return in case a transmit
2803 * of a packet spanned over multiple buffer still in process.
2804 * In case the Tx queue was in "resource error" condition, where there are
2805 * no available Tx resources, the function resets the resource error flag.
2808 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2809 * struct pkt_info *p_pkt_info User packet buffer.
2812 * Tx ring 'first' and 'used' indexes are updated.
2816 * ETH_ERROR otherwise.
2819 static ETH_FUNC_RET_STATUS
eth_tx_return_desc(struct mv643xx_private
*mp
,
2820 struct pkt_info
*p_pkt_info
)
2824 struct eth_tx_desc
*p_tx_desc_used
;
2825 unsigned int command_status
;
2826 unsigned long flags
;
2829 spin_lock_irqsave(&mp
->lock
, flags
);
2831 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
2832 tx_busy_desc
= mp
->tx_first_desc_q
;
2834 tx_busy_desc
= mp
->tx_curr_desc_q
;
2837 /* Get the Tx Desc ring indexes */
2838 tx_desc_used
= mp
->tx_used_desc_q
;
2840 p_tx_desc_used
= &mp
->p_tx_desc_area
[tx_desc_used
];
2843 if (p_tx_desc_used
== NULL
) {
2848 /* Stop release. About to overlap the current available Tx descriptor */
2849 if (tx_desc_used
== tx_busy_desc
&& !mp
->tx_resource_err
) {
2854 command_status
= p_tx_desc_used
->cmd_sts
;
2856 /* Still transmitting... */
2857 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
2862 /* Pass the packet information to the caller */
2863 p_pkt_info
->cmd_sts
= command_status
;
2864 p_pkt_info
->return_info
= mp
->tx_skb
[tx_desc_used
];
2865 p_pkt_info
->buf_ptr
= p_tx_desc_used
->buf_ptr
;
2866 p_pkt_info
->byte_cnt
= p_tx_desc_used
->byte_cnt
;
2867 mp
->tx_skb
[tx_desc_used
] = NULL
;
2869 /* Update the next descriptor to release. */
2870 mp
->tx_used_desc_q
= (tx_desc_used
+ 1) % mp
->tx_ring_size
;
2872 /* Any Tx return cancels the Tx resource error status */
2873 mp
->tx_resource_err
= 0;
2875 BUG_ON(mp
->tx_ring_skbs
== 0);
2879 spin_unlock_irqrestore(&mp
->lock
, flags
);
2885 * eth_port_receive - Get received information from Rx ring.
2888 * This routine returns the received data to the caller. There is no
2889 * data copying during routine operation. All information is returned
2890 * using pointer to packet information struct passed from the caller.
2891 * If the routine exhausts Rx ring resources then the resource error flag
2895 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2896 * struct pkt_info *p_pkt_info User packet buffer.
2899 * Rx ring current and used indexes are updated.
2902 * ETH_ERROR in case the routine can not access Rx desc ring.
2903 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
2904 * ETH_END_OF_JOB if there is no received data.
2907 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
2908 struct pkt_info
*p_pkt_info
)
2910 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
2911 volatile struct eth_rx_desc
*p_rx_desc
;
2912 unsigned int command_status
;
2913 unsigned long flags
;
2915 /* Do not process Rx ring in case of Rx ring resource error */
2916 if (mp
->rx_resource_err
)
2917 return ETH_QUEUE_FULL
;
2919 spin_lock_irqsave(&mp
->lock
, flags
);
2921 /* Get the Rx Desc ring 'curr and 'used' indexes */
2922 rx_curr_desc
= mp
->rx_curr_desc_q
;
2923 rx_used_desc
= mp
->rx_used_desc_q
;
2925 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
2927 /* The following parameters are used to save readings from memory */
2928 command_status
= p_rx_desc
->cmd_sts
;
2931 /* Nothing to receive... */
2932 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
2933 spin_unlock_irqrestore(&mp
->lock
, flags
);
2934 return ETH_END_OF_JOB
;
2937 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
2938 p_pkt_info
->cmd_sts
= command_status
;
2939 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
2940 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
2941 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
2943 /* Clean the return info field to indicate that the packet has been */
2944 /* moved to the upper layers */
2945 mp
->rx_skb
[rx_curr_desc
] = NULL
;
2947 /* Update current index in data structure */
2948 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
2949 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
2951 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
2952 if (rx_next_curr_desc
== rx_used_desc
)
2953 mp
->rx_resource_err
= 1;
2955 spin_unlock_irqrestore(&mp
->lock
, flags
);
2961 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
2964 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
2965 * next 'used' descriptor and attached the returned buffer to it.
2966 * In case the Rx ring was in "resource error" condition, where there are
2967 * no available Rx resources, the function resets the resource error flag.
2970 * struct mv643xx_private *mp Ethernet Port Control srtuct.
2971 * struct pkt_info *p_pkt_info Information on returned buffer.
2974 * New available Rx resource in Rx descriptor ring.
2977 * ETH_ERROR in case the routine can not access Rx desc ring.
2980 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
2981 struct pkt_info
*p_pkt_info
)
2983 int used_rx_desc
; /* Where to return Rx resource */
2984 volatile struct eth_rx_desc
*p_used_rx_desc
;
2985 unsigned long flags
;
2987 spin_lock_irqsave(&mp
->lock
, flags
);
2989 /* Get 'used' Rx descriptor */
2990 used_rx_desc
= mp
->rx_used_desc_q
;
2991 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
2993 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
2994 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
2995 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
2997 /* Flush the write pipe */
2999 /* Return the descriptor to DMA ownership */
3001 p_used_rx_desc
->cmd_sts
=
3002 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
3005 /* Move the used descriptor pointer to the next descriptor */
3006 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
3008 /* Any Rx return cancels the Rx resource error status */
3009 mp
->rx_resource_err
= 0;
3011 spin_unlock_irqrestore(&mp
->lock
, flags
);
3016 /************* Begin ethtool support *************************/
3018 struct mv643xx_stats
{
3019 char stat_string
[ETH_GSTRING_LEN
];
3024 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3025 offsetof(struct mv643xx_private, m)
3027 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
3028 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
3029 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
3030 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
3031 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
3032 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
3033 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
3034 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
3035 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
3036 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
3037 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
3038 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
3039 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
3040 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
3041 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
3042 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
3043 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
3044 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
3045 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
3046 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
3047 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
3048 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
3049 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
3050 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
3051 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
3052 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
3053 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
3054 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
3055 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
3056 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
3057 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
3058 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
3059 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
3060 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
3061 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
3062 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
3063 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
3064 { "collision", MV643XX_STAT(mib_counters
.collision
) },
3065 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
3068 #define MV643XX_STATS_LEN \
3069 sizeof(mv643xx_gstrings_stats) / sizeof(struct mv643xx_stats)
3072 mv643xx_get_settings(struct net_device
*netdev
, struct ethtool_cmd
*ecmd
)
3074 struct mv643xx_private
*mp
= netdev
->priv
;
3075 int port_num
= mp
->port_num
;
3076 int autoneg
= eth_port_autoneg_supported(port_num
);
3079 int half_duplex
= 0;
3080 int full_duplex
= 0;
3086 u32 pcs
= mv_read(MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port_num
));
3087 u32 psr
= mv_read(MV643XX_ETH_PORT_STATUS_REG(port_num
));
3089 mode_10_bit
= psr
& MV643XX_ETH_PORT_STATUS_MODE_10_BIT
;
3092 ecmd
->supported
= SUPPORTED_10baseT_Half
;
3094 ecmd
->supported
= (SUPPORTED_10baseT_Half
|
3095 SUPPORTED_10baseT_Full
|
3096 SUPPORTED_100baseT_Half
|
3097 SUPPORTED_100baseT_Full
|
3098 SUPPORTED_1000baseT_Full
|
3099 (autoneg
? SUPPORTED_Autoneg
: 0) |
3102 auto_duplex
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX
);
3103 auto_speed
= !(pcs
& MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII
);
3105 ecmd
->advertising
= ADVERTISED_TP
;
3108 ecmd
->advertising
|= ADVERTISED_Autoneg
;
3114 if (pcs
& MV643XX_ETH_SET_FULL_DUPLEX_MODE
)
3125 if (pcs
& MV643XX_ETH_SET_GMII_SPEED_TO_1000
)
3127 else if (pcs
& MV643XX_ETH_SET_MII_SPEED_TO_100
)
3133 if (speed_10
& half_duplex
)
3134 ecmd
->advertising
|= ADVERTISED_10baseT_Half
;
3135 if (speed_10
& full_duplex
)
3136 ecmd
->advertising
|= ADVERTISED_10baseT_Full
;
3137 if (speed_100
& half_duplex
)
3138 ecmd
->advertising
|= ADVERTISED_100baseT_Half
;
3139 if (speed_100
& full_duplex
)
3140 ecmd
->advertising
|= ADVERTISED_100baseT_Full
;
3142 ecmd
->advertising
|= ADVERTISED_1000baseT_Full
;
3146 ecmd
->port
= PORT_TP
;
3147 ecmd
->phy_address
= ethernet_phy_get(port_num
);
3149 ecmd
->transceiver
= XCVR_EXTERNAL
;
3151 if (netif_carrier_ok(netdev
)) {
3153 ecmd
->speed
= SPEED_10
;
3155 if (psr
& MV643XX_ETH_PORT_STATUS_GMII_1000
)
3156 ecmd
->speed
= SPEED_1000
;
3157 else if (psr
& MV643XX_ETH_PORT_STATUS_MII_100
)
3158 ecmd
->speed
= SPEED_100
;
3160 ecmd
->speed
= SPEED_10
;
3163 if (psr
& MV643XX_ETH_PORT_STATUS_FULL_DUPLEX
)
3164 ecmd
->duplex
= DUPLEX_FULL
;
3166 ecmd
->duplex
= DUPLEX_HALF
;
3172 ecmd
->autoneg
= autoneg
? AUTONEG_ENABLE
: AUTONEG_DISABLE
;
3177 mv643xx_get_drvinfo(struct net_device
*netdev
,
3178 struct ethtool_drvinfo
*drvinfo
)
3180 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
3181 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
3182 strncpy(drvinfo
->fw_version
, "N/A", 32);
3183 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
3184 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
3188 mv643xx_get_stats_count(struct net_device
*netdev
)
3190 return MV643XX_STATS_LEN
;
3194 mv643xx_get_ethtool_stats(struct net_device
*netdev
,
3195 struct ethtool_stats
*stats
, uint64_t *data
)
3197 struct mv643xx_private
*mp
= netdev
->priv
;
3200 eth_update_mib_counters(mp
);
3202 for(i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
3203 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
3204 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
3205 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
3210 mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
, uint8_t *data
)
3216 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
3217 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3218 mv643xx_gstrings_stats
[i
].stat_string
,
3225 static struct ethtool_ops mv643xx_ethtool_ops
= {
3226 .get_settings
= mv643xx_get_settings
,
3227 .get_drvinfo
= mv643xx_get_drvinfo
,
3228 .get_link
= ethtool_op_get_link
,
3229 .get_sg
= ethtool_op_get_sg
,
3230 .set_sg
= ethtool_op_set_sg
,
3231 .get_strings
= mv643xx_get_strings
,
3232 .get_stats_count
= mv643xx_get_stats_count
,
3233 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
3236 /************* End ethtool support *************************/