2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/spinlock.h>
49 #include <linux/workqueue.h>
50 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
55 #include <asm/types.h>
56 #include <asm/pgtable.h>
57 #include <asm/system.h>
58 #include <asm/delay.h>
59 #include <asm/dma-mapping.h>
61 #define MV643XX_CHECKSUM_OFFLOAD_TX
63 #define MV643XX_TX_FAST_REFILL
66 #define MV643XX_TX_COAL 100
68 #define MV643XX_RX_COAL 100
71 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
72 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74 #define MAX_DESCS_PER_SKB 1
77 #define ETH_VLAN_HLEN 4
79 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
80 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
81 ETH_VLAN_HLEN + ETH_FCS_LEN)
82 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
83 dma_get_cache_alignment())
86 * Registers shared between all ports.
88 #define PHY_ADDR_REG 0x0000
89 #define SMI_REG 0x0004
94 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
95 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
96 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
97 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
98 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
99 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
100 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
101 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
102 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
103 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
104 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
105 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
106 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
107 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
108 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
109 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
110 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
111 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
112 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
113 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
114 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
116 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
117 #define UNICAST_NORMAL_MODE (0 << 0)
118 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
119 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
120 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
121 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
122 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
123 #define RECEIVE_BC_IF_IP (0 << 8)
124 #define REJECT_BC_IF_IP (1 << 8)
125 #define RECEIVE_BC_IF_ARP (0 << 9)
126 #define REJECT_BC_IF_ARP (1 << 9)
127 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
128 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
129 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
130 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
131 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
132 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
133 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
134 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
136 #define PORT_CONFIG_DEFAULT_VALUE \
137 UNICAST_NORMAL_MODE | \
138 DEFAULT_RX_QUEUE(0) | \
139 DEFAULT_RX_ARP_QUEUE(0) | \
140 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
142 RECEIVE_BC_IF_ARP | \
143 CAPTURE_TCP_FRAMES_DIS | \
144 CAPTURE_UDP_FRAMES_DIS | \
145 DEFAULT_RX_TCP_QUEUE(0) | \
146 DEFAULT_RX_UDP_QUEUE(0) | \
147 DEFAULT_RX_BPDU_QUEUE(0)
149 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
150 #define CLASSIFY_EN (1 << 0)
151 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
152 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
153 #define PARTITION_DISABLE (0 << 2)
154 #define PARTITION_ENABLE (1 << 2)
156 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
157 SPAN_BPDU_PACKETS_AS_NORMAL | \
160 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
161 #define RIFB (1 << 0)
162 #define RX_BURST_SIZE_1_64BIT (0 << 1)
163 #define RX_BURST_SIZE_2_64BIT (1 << 1)
164 #define RX_BURST_SIZE_4_64BIT (2 << 1)
165 #define RX_BURST_SIZE_8_64BIT (3 << 1)
166 #define RX_BURST_SIZE_16_64BIT (4 << 1)
167 #define BLM_RX_NO_SWAP (1 << 4)
168 #define BLM_RX_BYTE_SWAP (0 << 4)
169 #define BLM_TX_NO_SWAP (1 << 5)
170 #define BLM_TX_BYTE_SWAP (0 << 5)
171 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
172 #define DESCRIPTORS_NO_SWAP (0 << 6)
173 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
174 #define TX_BURST_SIZE_1_64BIT (0 << 22)
175 #define TX_BURST_SIZE_2_64BIT (1 << 22)
176 #define TX_BURST_SIZE_4_64BIT (2 << 22)
177 #define TX_BURST_SIZE_8_64BIT (3 << 22)
178 #define TX_BURST_SIZE_16_64BIT (4 << 22)
180 #if defined(__BIG_ENDIAN)
181 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
182 RX_BURST_SIZE_4_64BIT | \
184 TX_BURST_SIZE_4_64BIT
185 #elif defined(__LITTLE_ENDIAN)
186 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
187 RX_BURST_SIZE_4_64BIT | \
191 TX_BURST_SIZE_4_64BIT
193 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
196 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
197 #define SERIAL_PORT_DISABLE (0 << 0)
198 #define SERIAL_PORT_ENABLE (1 << 0)
199 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
200 #define FORCE_LINK_PASS (1 << 1)
201 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
202 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
203 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
204 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
205 #define ADV_NO_FLOW_CTRL (0 << 4)
206 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
207 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
208 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
209 #define FORCE_BP_MODE_NO_JAM (0 << 7)
210 #define FORCE_BP_MODE_JAM_TX (1 << 7)
211 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
212 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
213 #define FORCE_LINK_FAIL (0 << 10)
214 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
215 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
216 #define RETRANSMIT_FOREVER (1 << 11)
217 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
218 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
219 #define DTE_ADV_0 (0 << 14)
220 #define DTE_ADV_1 (1 << 14)
221 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
222 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
223 #define AUTO_NEG_NO_CHANGE (0 << 16)
224 #define RESTART_AUTO_NEG (1 << 16)
225 #define MAX_RX_PACKET_1518BYTE (0 << 17)
226 #define MAX_RX_PACKET_1522BYTE (1 << 17)
227 #define MAX_RX_PACKET_1552BYTE (2 << 17)
228 #define MAX_RX_PACKET_9022BYTE (3 << 17)
229 #define MAX_RX_PACKET_9192BYTE (4 << 17)
230 #define MAX_RX_PACKET_9700BYTE (5 << 17)
231 #define MAX_RX_PACKET_MASK (7 << 17)
232 #define CLR_EXT_LOOPBACK (0 << 20)
233 #define SET_EXT_LOOPBACK (1 << 20)
234 #define SET_HALF_DUPLEX_MODE (0 << 21)
235 #define SET_FULL_DUPLEX_MODE (1 << 21)
236 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
237 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
238 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
239 #define SET_GMII_SPEED_TO_1000 (1 << 23)
240 #define SET_MII_SPEED_TO_10 (0 << 24)
241 #define SET_MII_SPEED_TO_100 (1 << 24)
243 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
244 DO_NOT_FORCE_LINK_PASS | \
245 ENABLE_AUTO_NEG_FOR_DUPLX | \
246 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
247 ADV_SYMMETRIC_FLOW_CTRL | \
248 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
249 FORCE_BP_MODE_NO_JAM | \
250 (1 << 9) /* reserved */ | \
251 DO_NOT_FORCE_LINK_FAIL | \
252 RETRANSMIT_16_ATTEMPTS | \
253 ENABLE_AUTO_NEG_SPEED_GMII | \
255 DISABLE_AUTO_NEG_BYPASS | \
256 AUTO_NEG_NO_CHANGE | \
257 MAX_RX_PACKET_9700BYTE | \
259 SET_FULL_DUPLEX_MODE | \
260 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
262 /* These macros describe Ethernet Serial Status reg (PSR) bits */
263 #define PORT_STATUS_MODE_10_BIT (1 << 0)
264 #define PORT_STATUS_LINK_UP (1 << 1)
265 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
266 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
267 #define PORT_STATUS_GMII_1000 (1 << 4)
268 #define PORT_STATUS_MII_100 (1 << 5)
269 /* PSR bit 6 is undocumented */
270 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
271 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
272 #define PORT_STATUS_PARTITION (1 << 9)
273 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
274 /* PSR bits 11-31 are reserved */
276 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
277 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
281 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
282 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
284 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
285 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
286 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
287 #define ETH_INT_CAUSE_EXT 0x00000002
288 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
290 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
291 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
292 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
293 #define ETH_INT_CAUSE_PHY 0x00010000
294 #define ETH_INT_CAUSE_STATE 0x00100000
295 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
298 #define ETH_INT_MASK_ALL 0x00000000
299 #define ETH_INT_MASK_ALL_EXT 0x00000000
301 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
302 #define PHY_WAIT_MICRO_SECONDS 10
304 /* Buffer offset from buffer pointer */
305 #define RX_BUF_OFFSET 0x2
307 /* Gigabit Ethernet Unit Global Registers */
309 /* MIB Counters register definitions */
310 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
311 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
312 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
313 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
314 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
315 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
316 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
317 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
318 #define ETH_MIB_FRAMES_64_OCTETS 0x20
319 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
320 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
321 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
322 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
323 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
324 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
325 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
326 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
327 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
328 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
329 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
330 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
331 #define ETH_MIB_FC_SENT 0x54
332 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
333 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
334 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
335 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
336 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
337 #define ETH_MIB_JABBER_RECEIVED 0x6c
338 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
339 #define ETH_MIB_BAD_CRC_EVENT 0x74
340 #define ETH_MIB_COLLISION 0x78
341 #define ETH_MIB_LATE_COLLISION 0x7c
343 /* Port serial status reg (PSR) */
344 #define ETH_INTERFACE_PCM 0x00000001
345 #define ETH_LINK_IS_UP 0x00000002
346 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
347 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
348 #define ETH_GMII_SPEED_1000 0x00000010
349 #define ETH_MII_SPEED_100 0x00000020
350 #define ETH_TX_IN_PROGRESS 0x00000080
351 #define ETH_BYPASS_ACTIVE 0x00000100
352 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
353 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
356 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
357 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
358 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
359 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
361 /* Interrupt Cause Register Bit Definitions */
363 /* SDMA command status fields macros */
365 /* Tx & Rx descriptors status */
366 #define ETH_ERROR_SUMMARY 0x00000001
368 /* Tx & Rx descriptors command */
369 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
371 /* Tx descriptors status */
372 #define ETH_LC_ERROR 0
373 #define ETH_UR_ERROR 0x00000002
374 #define ETH_RL_ERROR 0x00000004
375 #define ETH_LLC_SNAP_FORMAT 0x00000200
377 /* Rx descriptors status */
378 #define ETH_OVERRUN_ERROR 0x00000002
379 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
380 #define ETH_RESOURCE_ERROR 0x00000006
381 #define ETH_VLAN_TAGGED 0x00080000
382 #define ETH_BPDU_FRAME 0x00100000
383 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
384 #define ETH_OTHER_FRAME_TYPE 0x00400000
385 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
386 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
387 #define ETH_FRAME_HEADER_OK 0x02000000
388 #define ETH_RX_LAST_DESC 0x04000000
389 #define ETH_RX_FIRST_DESC 0x08000000
390 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
391 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
392 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
394 /* Rx descriptors byte count */
395 #define ETH_FRAME_FRAGMENTED 0x00000004
397 /* Tx descriptors command */
398 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
399 #define ETH_FRAME_SET_TO_VLAN 0x00008000
400 #define ETH_UDP_FRAME 0x00010000
401 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
402 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
403 #define ETH_ZERO_PADDING 0x00080000
404 #define ETH_TX_LAST_DESC 0x00100000
405 #define ETH_TX_FIRST_DESC 0x00200000
406 #define ETH_GEN_CRC 0x00400000
407 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
408 #define ETH_AUTO_MODE 0x40000000
410 #define ETH_TX_IHL_SHIFT 11
414 typedef enum _eth_func_ret_status
{
415 ETH_OK
, /* Returned as expected. */
416 ETH_ERROR
, /* Fundamental error. */
417 ETH_RETRY
, /* Could not process request. Try later.*/
418 ETH_END_OF_JOB
, /* Ring has nothing to process. */
419 ETH_QUEUE_FULL
, /* Ring resource error. */
420 ETH_QUEUE_LAST_RESOURCE
/* Ring resources about to exhaust. */
421 } ETH_FUNC_RET_STATUS
;
423 /* These are for big-endian machines. Little endian needs different
426 #if defined(__BIG_ENDIAN)
428 u16 byte_cnt
; /* Descriptor buffer byte count */
429 u16 buf_size
; /* Buffer size */
430 u32 cmd_sts
; /* Descriptor command status */
431 u32 next_desc_ptr
; /* Next descriptor pointer */
432 u32 buf_ptr
; /* Descriptor buffer pointer */
436 u16 byte_cnt
; /* buffer byte count */
437 u16 l4i_chk
; /* CPU provided TCP checksum */
438 u32 cmd_sts
; /* Command/status field */
439 u32 next_desc_ptr
; /* Pointer to next descriptor */
440 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
442 #elif defined(__LITTLE_ENDIAN)
444 u32 cmd_sts
; /* Descriptor command status */
445 u16 buf_size
; /* Buffer size */
446 u16 byte_cnt
; /* Descriptor buffer byte count */
447 u32 buf_ptr
; /* Descriptor buffer pointer */
448 u32 next_desc_ptr
; /* Next descriptor pointer */
452 u32 cmd_sts
; /* Command/status field */
453 u16 l4i_chk
; /* CPU provided TCP checksum */
454 u16 byte_cnt
; /* buffer byte count */
455 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
456 u32 next_desc_ptr
; /* Pointer to next descriptor */
459 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
462 /* Unified struct for Rx and Tx operations. The user is not required to */
463 /* be familier with neither Tx nor Rx descriptors. */
465 unsigned short byte_cnt
; /* Descriptor buffer byte count */
466 unsigned short l4i_chk
; /* Tx CPU provided TCP Checksum */
467 unsigned int cmd_sts
; /* Descriptor command status */
468 dma_addr_t buf_ptr
; /* Descriptor buffer pointer */
469 struct sk_buff
*return_info
; /* User resource return information */
472 /* Ethernet port specific information */
473 struct mv643xx_mib_counters
{
474 u64 good_octets_received
;
475 u32 bad_octets_received
;
476 u32 internal_mac_transmit_err
;
477 u32 good_frames_received
;
478 u32 bad_frames_received
;
479 u32 broadcast_frames_received
;
480 u32 multicast_frames_received
;
481 u32 frames_64_octets
;
482 u32 frames_65_to_127_octets
;
483 u32 frames_128_to_255_octets
;
484 u32 frames_256_to_511_octets
;
485 u32 frames_512_to_1023_octets
;
486 u32 frames_1024_to_max_octets
;
487 u64 good_octets_sent
;
488 u32 good_frames_sent
;
489 u32 excessive_collision
;
490 u32 multicast_frames_sent
;
491 u32 broadcast_frames_sent
;
492 u32 unrec_mac_control_received
;
494 u32 good_fc_received
;
496 u32 undersize_received
;
497 u32 fragments_received
;
498 u32 oversize_received
;
500 u32 mac_receive_error
;
506 struct mv643xx_private
{
507 int port_num
; /* User Ethernet port number */
509 u32 rx_sram_addr
; /* Base address of rx sram area */
510 u32 rx_sram_size
; /* Size of rx sram area */
511 u32 tx_sram_addr
; /* Base address of tx sram area */
512 u32 tx_sram_size
; /* Size of tx sram area */
514 int rx_resource_err
; /* Rx ring resource error flag */
516 /* Tx/Rx rings managment indexes fields. For driver use */
518 /* Next available and first returning Rx resource */
519 int rx_curr_desc_q
, rx_used_desc_q
;
521 /* Next available and first returning Tx resource */
522 int tx_curr_desc_q
, tx_used_desc_q
;
524 #ifdef MV643XX_TX_FAST_REFILL
525 u32 tx_clean_threshold
;
528 struct eth_rx_desc
*p_rx_desc_area
;
529 dma_addr_t rx_desc_dma
;
530 int rx_desc_area_size
;
531 struct sk_buff
**rx_skb
;
533 struct eth_tx_desc
*p_tx_desc_area
;
534 dma_addr_t tx_desc_dma
;
535 int tx_desc_area_size
;
536 struct sk_buff
**tx_skb
;
538 struct work_struct tx_timeout_task
;
540 struct net_device
*dev
;
541 struct napi_struct napi
;
542 struct net_device_stats stats
;
543 struct mv643xx_mib_counters mib_counters
;
545 /* Size of Tx Ring per queue */
547 /* Number of tx descriptors in use */
549 /* Size of Rx Ring per queue */
551 /* Number of rx descriptors in use */
555 * Used in case RX Ring is empty, which can be caused when
556 * system does not have resources (skb's)
558 struct timer_list timeout
;
562 struct mii_if_info mii
;
565 /* Static function declarations */
566 static void eth_port_init(struct mv643xx_private
*mp
);
567 static void eth_port_reset(struct mv643xx_private
*mp
);
568 static void eth_port_start(struct net_device
*dev
);
570 static void ethernet_phy_reset(struct mv643xx_private
*mp
);
572 static void eth_port_write_smi_reg(struct mv643xx_private
*mp
,
573 unsigned int phy_reg
, unsigned int value
);
575 static void eth_port_read_smi_reg(struct mv643xx_private
*mp
,
576 unsigned int phy_reg
, unsigned int *value
);
578 static void eth_clear_mib_counters(struct mv643xx_private
*mp
);
580 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
581 struct pkt_info
*p_pkt_info
);
582 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
583 struct pkt_info
*p_pkt_info
);
585 static void eth_port_uc_addr_get(struct mv643xx_private
*mp
,
586 unsigned char *p_addr
);
587 static void eth_port_uc_addr_set(struct mv643xx_private
*mp
,
588 unsigned char *p_addr
);
589 static void eth_port_set_multicast_list(struct net_device
*);
590 static void mv643xx_eth_port_enable_tx(struct mv643xx_private
*mp
,
591 unsigned int queues
);
592 static void mv643xx_eth_port_enable_rx(struct mv643xx_private
*mp
,
593 unsigned int queues
);
594 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private
*mp
);
595 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private
*mp
);
596 static int mv643xx_eth_open(struct net_device
*);
597 static int mv643xx_eth_stop(struct net_device
*);
598 static void eth_port_init_mac_tables(struct mv643xx_private
*mp
);
600 static int mv643xx_poll(struct napi_struct
*napi
, int budget
);
602 static int ethernet_phy_get(struct mv643xx_private
*mp
);
603 static void ethernet_phy_set(struct mv643xx_private
*mp
, int phy_addr
);
604 static int ethernet_phy_detect(struct mv643xx_private
*mp
);
605 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
);
606 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
);
607 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
);
608 static const struct ethtool_ops mv643xx_ethtool_ops
;
610 static char mv643xx_driver_name
[] = "mv643xx_eth";
611 static char mv643xx_driver_version
[] = "1.0";
613 static void __iomem
*mv643xx_eth_base
;
615 /* used to protect SMI_REG, which is shared across ports */
616 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
618 static inline u32
mv_read(int offset
)
620 return readl(mv643xx_eth_base
+ offset
);
623 static inline void mv_write(int offset
, u32 data
)
625 writel(data
, mv643xx_eth_base
+ offset
);
629 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
631 * Input : pointer to ethernet interface network device structure
633 * Output : 0 upon success, -EINVAL upon failure
635 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
637 if ((new_mtu
> 9500) || (new_mtu
< 64))
641 if (!netif_running(dev
))
645 * Stop and then re-open the interface. This will allocate RX
646 * skbs of the new MTU.
647 * There is a possible danger that the open will not succeed,
648 * due to memory being full, which might fail the open function.
650 mv643xx_eth_stop(dev
);
651 if (mv643xx_eth_open(dev
)) {
652 printk(KERN_ERR
"%s: Fatal error on opening device\n",
660 * mv643xx_eth_rx_refill_descs
662 * Fills / refills RX queue on a certain gigabit ethernet port
664 * Input : pointer to ethernet interface network device structure
667 static void mv643xx_eth_rx_refill_descs(struct net_device
*dev
)
669 struct mv643xx_private
*mp
= netdev_priv(dev
);
670 struct pkt_info pkt_info
;
674 while (mp
->rx_desc_count
< mp
->rx_ring_size
) {
675 skb
= dev_alloc_skb(ETH_RX_SKB_SIZE
+ dma_get_cache_alignment());
679 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
681 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
682 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
683 pkt_info
.byte_cnt
= ETH_RX_SKB_SIZE
;
684 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
685 ETH_RX_SKB_SIZE
, DMA_FROM_DEVICE
);
686 pkt_info
.return_info
= skb
;
687 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
689 "%s: Error allocating RX Ring\n", dev
->name
);
692 skb_reserve(skb
, ETH_HW_IP_ALIGN
);
695 * If RX ring is empty of SKB, set a timer to try allocating
696 * again at a later time.
698 if (mp
->rx_desc_count
== 0) {
699 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
700 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10); /* 100 mSec */
701 add_timer(&mp
->timeout
);
706 * mv643xx_eth_rx_refill_descs_timer_wrapper
708 * Timer routine to wake up RX queue filling task. This function is
709 * used only in case the RX queue is empty, and all alloc_skb has
710 * failed (due to out of memory event).
712 * Input : pointer to ethernet interface network device structure
715 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data
)
717 mv643xx_eth_rx_refill_descs((struct net_device
*)data
);
721 * mv643xx_eth_update_mac_address
723 * Update the MAC address of the port in the address table
725 * Input : pointer to ethernet interface network device structure
728 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
730 struct mv643xx_private
*mp
= netdev_priv(dev
);
732 eth_port_init_mac_tables(mp
);
733 eth_port_uc_addr_set(mp
, dev
->dev_addr
);
737 * mv643xx_eth_set_rx_mode
739 * Change from promiscuos to regular rx mode
741 * Input : pointer to ethernet interface network device structure
744 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
746 struct mv643xx_private
*mp
= netdev_priv(dev
);
749 config_reg
= mv_read(PORT_CONFIG_REG(mp
->port_num
));
750 if (dev
->flags
& IFF_PROMISC
)
751 config_reg
|= (u32
) UNICAST_PROMISCUOUS_MODE
;
753 config_reg
&= ~(u32
) UNICAST_PROMISCUOUS_MODE
;
754 mv_write(PORT_CONFIG_REG(mp
->port_num
), config_reg
);
756 eth_port_set_multicast_list(dev
);
760 * mv643xx_eth_set_mac_address
762 * Change the interface's mac address.
763 * No special hardware thing should be done because interface is always
764 * put in promiscuous mode.
766 * Input : pointer to ethernet interface network device structure and
767 * a pointer to the designated entry to be added to the cache.
768 * Output : zero upon success, negative upon failure
770 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
774 for (i
= 0; i
< 6; i
++)
775 /* +2 is for the offset of the HW addr type */
776 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
777 mv643xx_eth_update_mac_address(dev
);
782 * mv643xx_eth_tx_timeout
784 * Called upon a timeout on transmitting a packet
786 * Input : pointer to ethernet interface network device structure.
789 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
791 struct mv643xx_private
*mp
= netdev_priv(dev
);
793 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
795 /* Do the reset outside of interrupt context */
796 schedule_work(&mp
->tx_timeout_task
);
800 * mv643xx_eth_tx_timeout_task
802 * Actual routine to reset the adapter when a timeout on Tx has occurred
804 static void mv643xx_eth_tx_timeout_task(struct work_struct
*ugly
)
806 struct mv643xx_private
*mp
= container_of(ugly
, struct mv643xx_private
,
808 struct net_device
*dev
= mp
->dev
;
810 if (!netif_running(dev
))
813 netif_stop_queue(dev
);
818 if (mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
819 netif_wake_queue(dev
);
823 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
825 * If force is non-zero, frees uncompleted descriptors as well
827 static int mv643xx_eth_free_tx_descs(struct net_device
*dev
, int force
)
829 struct mv643xx_private
*mp
= netdev_priv(dev
);
830 struct eth_tx_desc
*desc
;
839 while (mp
->tx_desc_count
> 0) {
840 spin_lock_irqsave(&mp
->lock
, flags
);
842 /* tx_desc_count might have changed before acquiring the lock */
843 if (mp
->tx_desc_count
<= 0) {
844 spin_unlock_irqrestore(&mp
->lock
, flags
);
848 tx_index
= mp
->tx_used_desc_q
;
849 desc
= &mp
->p_tx_desc_area
[tx_index
];
850 cmd_sts
= desc
->cmd_sts
;
852 if (!force
&& (cmd_sts
& ETH_BUFFER_OWNED_BY_DMA
)) {
853 spin_unlock_irqrestore(&mp
->lock
, flags
);
857 mp
->tx_used_desc_q
= (tx_index
+ 1) % mp
->tx_ring_size
;
860 addr
= desc
->buf_ptr
;
861 count
= desc
->byte_cnt
;
862 skb
= mp
->tx_skb
[tx_index
];
864 mp
->tx_skb
[tx_index
] = NULL
;
866 if (cmd_sts
& ETH_ERROR_SUMMARY
) {
867 printk("%s: Error in TX\n", dev
->name
);
868 dev
->stats
.tx_errors
++;
871 spin_unlock_irqrestore(&mp
->lock
, flags
);
873 if (cmd_sts
& ETH_TX_FIRST_DESC
)
874 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
876 dma_unmap_page(NULL
, addr
, count
, DMA_TO_DEVICE
);
879 dev_kfree_skb_irq(skb
);
887 static void mv643xx_eth_free_completed_tx_descs(struct net_device
*dev
)
889 struct mv643xx_private
*mp
= netdev_priv(dev
);
891 if (mv643xx_eth_free_tx_descs(dev
, 0) &&
892 mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
893 netif_wake_queue(dev
);
896 static void mv643xx_eth_free_all_tx_descs(struct net_device
*dev
)
898 mv643xx_eth_free_tx_descs(dev
, 1);
902 * mv643xx_eth_receive
904 * This function is forward packets that are received from the port's
905 * queues toward kernel core or FastRoute them to another interface.
907 * Input : dev - a pointer to the required interface
908 * max - maximum number to receive (0 means unlimted)
910 * Output : number of served packets
912 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
914 struct mv643xx_private
*mp
= netdev_priv(dev
);
915 struct net_device_stats
*stats
= &dev
->stats
;
916 unsigned int received_packets
= 0;
918 struct pkt_info pkt_info
;
920 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
921 dma_unmap_single(NULL
, pkt_info
.buf_ptr
, ETH_RX_SKB_SIZE
,
928 * Note byte count includes 4 byte CRC count
931 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
932 skb
= pkt_info
.return_info
;
934 * In case received a packet without first / last bits on OR
935 * the error summary bit is on, the packets needs to be dropeed.
937 if (((pkt_info
.cmd_sts
938 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
939 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
940 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
942 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
943 ETH_RX_LAST_DESC
)) !=
944 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
947 "%s: Received packet spread "
948 "on multiple descriptors\n",
951 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
954 dev_kfree_skb_irq(skb
);
957 * The -4 is for the CRC in the trailer of the
960 skb_put(skb
, pkt_info
.byte_cnt
- 4);
962 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
963 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
965 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
967 skb
->protocol
= eth_type_trans(skb
, dev
);
969 netif_receive_skb(skb
);
974 dev
->last_rx
= jiffies
;
976 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
978 return received_packets
;
981 /* Set the mv643xx port configuration register for the speed/duplex mode. */
982 static void mv643xx_eth_update_pscr(struct net_device
*dev
,
983 struct ethtool_cmd
*ecmd
)
985 struct mv643xx_private
*mp
= netdev_priv(dev
);
986 int port_num
= mp
->port_num
;
990 o_pscr
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
993 /* clear speed, duplex and rx buffer size fields */
994 n_pscr
&= ~(SET_MII_SPEED_TO_100
|
995 SET_GMII_SPEED_TO_1000
|
996 SET_FULL_DUPLEX_MODE
|
999 if (ecmd
->duplex
== DUPLEX_FULL
)
1000 n_pscr
|= SET_FULL_DUPLEX_MODE
;
1002 if (ecmd
->speed
== SPEED_1000
)
1003 n_pscr
|= SET_GMII_SPEED_TO_1000
|
1004 MAX_RX_PACKET_9700BYTE
;
1006 if (ecmd
->speed
== SPEED_100
)
1007 n_pscr
|= SET_MII_SPEED_TO_100
;
1008 n_pscr
|= MAX_RX_PACKET_1522BYTE
;
1011 if (n_pscr
!= o_pscr
) {
1012 if ((o_pscr
& SERIAL_PORT_ENABLE
) == 0)
1013 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1015 queues
= mv643xx_eth_port_disable_tx(mp
);
1017 o_pscr
&= ~SERIAL_PORT_ENABLE
;
1018 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), o_pscr
);
1019 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1020 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1022 mv643xx_eth_port_enable_tx(mp
, queues
);
1028 * mv643xx_eth_int_handler
1030 * Main interrupt handler for the gigbit ethernet ports
1032 * Input : irq - irq number (not used)
1033 * dev_id - a pointer to the required interface's data structure
1038 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
)
1040 struct net_device
*dev
= (struct net_device
*)dev_id
;
1041 struct mv643xx_private
*mp
= netdev_priv(dev
);
1042 u32 eth_int_cause
, eth_int_cause_ext
= 0;
1043 unsigned int port_num
= mp
->port_num
;
1045 /* Read interrupt cause registers */
1046 eth_int_cause
= mv_read(INTERRUPT_CAUSE_REG(port_num
)) &
1048 if (eth_int_cause
& ETH_INT_CAUSE_EXT
) {
1049 eth_int_cause_ext
= mv_read(
1050 INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
1051 ETH_INT_UNMASK_ALL_EXT
;
1052 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
),
1053 ~eth_int_cause_ext
);
1056 /* PHY status changed */
1057 if (eth_int_cause_ext
& (ETH_INT_CAUSE_PHY
| ETH_INT_CAUSE_STATE
)) {
1058 struct ethtool_cmd cmd
;
1060 if (mii_link_ok(&mp
->mii
)) {
1061 mii_ethtool_gset(&mp
->mii
, &cmd
);
1062 mv643xx_eth_update_pscr(dev
, &cmd
);
1063 mv643xx_eth_port_enable_tx(mp
, ETH_TX_QUEUES_ENABLED
);
1064 if (!netif_carrier_ok(dev
)) {
1065 netif_carrier_on(dev
);
1066 if (mp
->tx_ring_size
- mp
->tx_desc_count
>=
1068 netif_wake_queue(dev
);
1070 } else if (netif_carrier_ok(dev
)) {
1071 netif_stop_queue(dev
);
1072 netif_carrier_off(dev
);
1077 if (eth_int_cause
& ETH_INT_CAUSE_RX
) {
1078 /* schedule the NAPI poll routine to maintain port */
1079 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1081 /* wait for previous write to complete */
1082 mv_read(INTERRUPT_MASK_REG(port_num
));
1084 netif_rx_schedule(dev
, &mp
->napi
);
1087 if (eth_int_cause
& ETH_INT_CAUSE_RX
)
1088 mv643xx_eth_receive_queue(dev
, INT_MAX
);
1090 if (eth_int_cause_ext
& ETH_INT_CAUSE_TX
)
1091 mv643xx_eth_free_completed_tx_descs(dev
);
1094 * If no real interrupt occured, exit.
1095 * This can happen when using gigE interrupt coalescing mechanism.
1097 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
1106 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1109 * This routine sets the RX coalescing interrupt mechanism parameter.
1110 * This parameter is a timeout counter, that counts in 64 t_clk
1111 * chunks ; that when timeout event occurs a maskable interrupt
1113 * The parameter is calculated using the tClk of the MV-643xx chip
1114 * , and the required delay of the interrupt in usec.
1117 * struct mv643xx_private *mp Ethernet port
1118 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1119 * unsigned int delay Delay in usec
1122 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1125 * The interrupt coalescing value set in the gigE port.
1128 static unsigned int eth_port_set_rx_coal(struct mv643xx_private
*mp
,
1129 unsigned int t_clk
, unsigned int delay
)
1131 unsigned int port_num
= mp
->port_num
;
1132 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
1134 /* Set RX Coalescing mechanism */
1135 mv_write(SDMA_CONFIG_REG(port_num
),
1136 ((coal
& 0x3fff) << 8) |
1137 (mv_read(SDMA_CONFIG_REG(port_num
))
1145 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
1148 * This routine sets the TX coalescing interrupt mechanism parameter.
1149 * This parameter is a timeout counter, that counts in 64 t_clk
1150 * chunks ; that when timeout event occurs a maskable interrupt
1152 * The parameter is calculated using the t_cLK frequency of the
1153 * MV-643xx chip and the required delay in the interrupt in uSec
1156 * struct mv643xx_private *mp Ethernet port
1157 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1158 * unsigned int delay Delay in uSeconds
1161 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1164 * The interrupt coalescing value set in the gigE port.
1167 static unsigned int eth_port_set_tx_coal(struct mv643xx_private
*mp
,
1168 unsigned int t_clk
, unsigned int delay
)
1170 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
1172 /* Set TX Coalescing mechanism */
1173 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(mp
->port_num
), coal
<< 4);
1179 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1182 * This function prepares a Rx chained list of descriptors and packet
1183 * buffers in a form of a ring. The routine must be called after port
1184 * initialization routine and before port start routine.
1185 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1186 * devices in the system (i.e. DRAM). This function uses the ethernet
1187 * struct 'virtual to physical' routine (set by the user) to set the ring
1188 * with physical addresses.
1191 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1194 * The routine updates the Ethernet port control struct with information
1195 * regarding the Rx descriptors and buffers.
1200 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
1202 volatile struct eth_rx_desc
*p_rx_desc
;
1203 int rx_desc_num
= mp
->rx_ring_size
;
1206 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1207 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
1208 for (i
= 0; i
< rx_desc_num
; i
++) {
1209 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
1210 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
1213 /* Save Rx desc pointer to driver struct. */
1214 mp
->rx_curr_desc_q
= 0;
1215 mp
->rx_used_desc_q
= 0;
1217 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
1221 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1224 * This function prepares a Tx chained list of descriptors and packet
1225 * buffers in a form of a ring. The routine must be called after port
1226 * initialization routine and before port start routine.
1227 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1228 * devices in the system (i.e. DRAM). This function uses the ethernet
1229 * struct 'virtual to physical' routine (set by the user) to set the ring
1230 * with physical addresses.
1233 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1236 * The routine updates the Ethernet port control struct with information
1237 * regarding the Tx descriptors and buffers.
1242 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
1244 int tx_desc_num
= mp
->tx_ring_size
;
1245 struct eth_tx_desc
*p_tx_desc
;
1248 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1249 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
1250 for (i
= 0; i
< tx_desc_num
; i
++) {
1251 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
1252 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
1255 mp
->tx_curr_desc_q
= 0;
1256 mp
->tx_used_desc_q
= 0;
1258 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
1261 static int mv643xx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1263 struct mv643xx_private
*mp
= netdev_priv(dev
);
1266 spin_lock_irq(&mp
->lock
);
1267 err
= mii_ethtool_sset(&mp
->mii
, cmd
);
1268 spin_unlock_irq(&mp
->lock
);
1273 static int mv643xx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1275 struct mv643xx_private
*mp
= netdev_priv(dev
);
1278 spin_lock_irq(&mp
->lock
);
1279 err
= mii_ethtool_gset(&mp
->mii
, cmd
);
1280 spin_unlock_irq(&mp
->lock
);
1282 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1283 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1284 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1292 * This function is called when openning the network device. The function
1293 * should initialize all the hardware, initialize cyclic Rx/Tx
1294 * descriptors chain and buffers and allocate an IRQ to the network
1297 * Input : a pointer to the network device structure
1299 * Output : zero of success , nonzero if fails.
1302 static int mv643xx_eth_open(struct net_device
*dev
)
1304 struct mv643xx_private
*mp
= netdev_priv(dev
);
1305 unsigned int port_num
= mp
->port_num
;
1309 /* Clear any pending ethernet port interrupts */
1310 mv_write(INTERRUPT_CAUSE_REG(port_num
), 0);
1311 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1312 /* wait for previous write to complete */
1313 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num
));
1315 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
1316 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
1318 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
1325 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
1326 mp
->timeout
.function
= mv643xx_eth_rx_refill_descs_timer_wrapper
;
1327 mp
->timeout
.data
= (unsigned long)dev
;
1329 /* Allocate RX and TX skb rings */
1330 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
1333 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
1337 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
1340 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
1342 goto out_free_rx_skb
;
1345 /* Allocate TX ring */
1346 mp
->tx_desc_count
= 0;
1347 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
1348 mp
->tx_desc_area_size
= size
;
1350 if (mp
->tx_sram_size
) {
1351 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
1353 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
1355 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
1359 if (!mp
->p_tx_desc_area
) {
1360 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
1363 goto out_free_tx_skb
;
1365 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
1366 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
1368 ether_init_tx_desc_ring(mp
);
1370 /* Allocate RX ring */
1371 mp
->rx_desc_count
= 0;
1372 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
1373 mp
->rx_desc_area_size
= size
;
1375 if (mp
->rx_sram_size
) {
1376 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
1378 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
1380 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1384 if (!mp
->p_rx_desc_area
) {
1385 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
1387 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
1389 if (mp
->rx_sram_size
)
1390 iounmap(mp
->p_tx_desc_area
);
1392 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
1393 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
1395 goto out_free_tx_skb
;
1397 memset((void *)mp
->p_rx_desc_area
, 0, size
);
1399 ether_init_rx_desc_ring(mp
);
1401 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
1404 napi_enable(&mp
->napi
);
1407 eth_port_start(dev
);
1409 /* Interrupt Coalescing */
1413 eth_port_set_rx_coal(mp
, 133000000, MV643XX_RX_COAL
);
1417 eth_port_set_tx_coal(mp
, 133000000, MV643XX_TX_COAL
);
1419 /* Unmask phy and link status changes interrupts */
1420 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num
), ETH_INT_UNMASK_ALL_EXT
);
1422 /* Unmask RX buffer and TX end interrupt */
1423 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1432 free_irq(dev
->irq
, dev
);
1437 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
1439 struct mv643xx_private
*mp
= netdev_priv(dev
);
1441 /* Stop Tx Queues */
1442 mv643xx_eth_port_disable_tx(mp
);
1444 /* Free outstanding skb's on TX ring */
1445 mv643xx_eth_free_all_tx_descs(dev
);
1447 BUG_ON(mp
->tx_used_desc_q
!= mp
->tx_curr_desc_q
);
1450 if (mp
->tx_sram_size
)
1451 iounmap(mp
->p_tx_desc_area
);
1453 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
1454 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
1457 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
1459 struct mv643xx_private
*mp
= netdev_priv(dev
);
1462 /* Stop RX Queues */
1463 mv643xx_eth_port_disable_rx(mp
);
1465 /* Free preallocated skb's on RX rings */
1466 for (curr
= 0; mp
->rx_desc_count
&& curr
< mp
->rx_ring_size
; curr
++) {
1467 if (mp
->rx_skb
[curr
]) {
1468 dev_kfree_skb(mp
->rx_skb
[curr
]);
1469 mp
->rx_desc_count
--;
1473 if (mp
->rx_desc_count
)
1475 "%s: Error in freeing Rx Ring. %d skb's still"
1476 " stuck in RX Ring - ignoring them\n", dev
->name
,
1479 if (mp
->rx_sram_size
)
1480 iounmap(mp
->p_rx_desc_area
);
1482 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
1483 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
1489 * This function is used when closing the network device.
1490 * It updates the hardware,
1491 * release all memory that holds buffers and descriptors and release the IRQ.
1492 * Input : a pointer to the device structure
1493 * Output : zero if success , nonzero if fails
1496 static int mv643xx_eth_stop(struct net_device
*dev
)
1498 struct mv643xx_private
*mp
= netdev_priv(dev
);
1499 unsigned int port_num
= mp
->port_num
;
1501 /* Mask all interrupts on ethernet port */
1502 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1503 /* wait for previous write to complete */
1504 mv_read(INTERRUPT_MASK_REG(port_num
));
1507 napi_disable(&mp
->napi
);
1509 netif_carrier_off(dev
);
1510 netif_stop_queue(dev
);
1514 mv643xx_eth_free_tx_rings(dev
);
1515 mv643xx_eth_free_rx_rings(dev
);
1517 free_irq(dev
->irq
, dev
);
1526 * This function is used in case of NAPI
1528 static int mv643xx_poll(struct napi_struct
*napi
, int budget
)
1530 struct mv643xx_private
*mp
= container_of(napi
, struct mv643xx_private
, napi
);
1531 struct net_device
*dev
= mp
->dev
;
1532 unsigned int port_num
= mp
->port_num
;
1535 #ifdef MV643XX_TX_FAST_REFILL
1536 if (++mp
->tx_clean_threshold
> 5) {
1537 mv643xx_eth_free_completed_tx_descs(dev
);
1538 mp
->tx_clean_threshold
= 0;
1543 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1544 != (u32
) mp
->rx_used_desc_q
)
1545 work_done
= mv643xx_eth_receive_queue(dev
, budget
);
1547 if (work_done
< budget
) {
1548 netif_rx_complete(dev
, napi
);
1549 mv_write(INTERRUPT_CAUSE_REG(port_num
), 0);
1550 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1551 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1559 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1561 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1562 * This helper function detects that case.
1565 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
1570 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1571 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1572 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7)
1579 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1581 static int eth_alloc_tx_desc_index(struct mv643xx_private
*mp
)
1585 BUG_ON(mp
->tx_desc_count
>= mp
->tx_ring_size
);
1587 tx_desc_curr
= mp
->tx_curr_desc_q
;
1588 mp
->tx_curr_desc_q
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
1590 BUG_ON(mp
->tx_curr_desc_q
== mp
->tx_used_desc_q
);
1592 return tx_desc_curr
;
1596 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1598 * Ensure the data for each fragment to be transmitted is mapped properly,
1599 * then fill in descriptors in the tx hw queue.
1601 static void eth_tx_fill_frag_descs(struct mv643xx_private
*mp
,
1602 struct sk_buff
*skb
)
1606 struct eth_tx_desc
*desc
;
1608 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1609 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1611 tx_index
= eth_alloc_tx_desc_index(mp
);
1612 desc
= &mp
->p_tx_desc_area
[tx_index
];
1614 desc
->cmd_sts
= ETH_BUFFER_OWNED_BY_DMA
;
1615 /* Last Frag enables interrupt and frees the skb */
1616 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1617 desc
->cmd_sts
|= ETH_ZERO_PADDING
|
1619 ETH_TX_ENABLE_INTERRUPT
;
1620 mp
->tx_skb
[tx_index
] = skb
;
1622 mp
->tx_skb
[tx_index
] = NULL
;
1624 desc
= &mp
->p_tx_desc_area
[tx_index
];
1626 desc
->byte_cnt
= this_frag
->size
;
1627 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1628 this_frag
->page_offset
,
1634 static inline __be16
sum16_as_be(__sum16 sum
)
1636 return (__force __be16
)sum
;
1640 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1642 * Ensure the data for an skb to be transmitted is mapped properly,
1643 * then fill in descriptors in the tx hw queue and start the hardware.
1645 static void eth_tx_submit_descs_for_skb(struct mv643xx_private
*mp
,
1646 struct sk_buff
*skb
)
1649 struct eth_tx_desc
*desc
;
1652 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
1654 cmd_sts
= ETH_TX_FIRST_DESC
| ETH_GEN_CRC
| ETH_BUFFER_OWNED_BY_DMA
;
1656 tx_index
= eth_alloc_tx_desc_index(mp
);
1657 desc
= &mp
->p_tx_desc_area
[tx_index
];
1660 eth_tx_fill_frag_descs(mp
, skb
);
1662 length
= skb_headlen(skb
);
1663 mp
->tx_skb
[tx_index
] = NULL
;
1665 cmd_sts
|= ETH_ZERO_PADDING
|
1667 ETH_TX_ENABLE_INTERRUPT
;
1669 mp
->tx_skb
[tx_index
] = skb
;
1672 desc
->byte_cnt
= length
;
1673 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
1675 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1676 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
));
1678 cmd_sts
|= ETH_GEN_TCP_UDP_CHECKSUM
|
1679 ETH_GEN_IP_V_4_CHECKSUM
|
1680 ip_hdr(skb
)->ihl
<< ETH_TX_IHL_SHIFT
;
1682 switch (ip_hdr(skb
)->protocol
) {
1684 cmd_sts
|= ETH_UDP_FRAME
;
1685 desc
->l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
1688 desc
->l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
1694 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1695 cmd_sts
|= 5 << ETH_TX_IHL_SHIFT
;
1699 /* ensure all other descriptors are written before first cmd_sts */
1701 desc
->cmd_sts
= cmd_sts
;
1703 /* ensure all descriptors are written before poking hardware */
1705 mv643xx_eth_port_enable_tx(mp
, ETH_TX_QUEUES_ENABLED
);
1707 mp
->tx_desc_count
+= nr_frags
+ 1;
1711 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1714 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1716 struct mv643xx_private
*mp
= netdev_priv(dev
);
1717 struct net_device_stats
*stats
= &dev
->stats
;
1718 unsigned long flags
;
1720 BUG_ON(netif_queue_stopped(dev
));
1722 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
1723 stats
->tx_dropped
++;
1724 printk(KERN_DEBUG
"%s: failed to linearize tiny "
1725 "unaligned fragment\n", dev
->name
);
1726 return NETDEV_TX_BUSY
;
1729 spin_lock_irqsave(&mp
->lock
, flags
);
1731 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
) {
1732 printk(KERN_ERR
"%s: transmit with queue full\n", dev
->name
);
1733 netif_stop_queue(dev
);
1734 spin_unlock_irqrestore(&mp
->lock
, flags
);
1735 return NETDEV_TX_BUSY
;
1738 eth_tx_submit_descs_for_skb(mp
, skb
);
1739 stats
->tx_bytes
+= skb
->len
;
1740 stats
->tx_packets
++;
1741 dev
->trans_start
= jiffies
;
1743 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
)
1744 netif_stop_queue(dev
);
1746 spin_unlock_irqrestore(&mp
->lock
, flags
);
1748 return NETDEV_TX_OK
;
1751 #ifdef CONFIG_NET_POLL_CONTROLLER
1752 static void mv643xx_netpoll(struct net_device
*netdev
)
1754 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1755 int port_num
= mp
->port_num
;
1757 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1758 /* wait for previous write to complete */
1759 mv_read(INTERRUPT_MASK_REG(port_num
));
1761 mv643xx_eth_int_handler(netdev
->irq
, netdev
);
1763 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1767 static void mv643xx_init_ethtool_cmd(struct net_device
*dev
, int phy_address
,
1768 int speed
, int duplex
,
1769 struct ethtool_cmd
*cmd
)
1771 struct mv643xx_private
*mp
= netdev_priv(dev
);
1773 memset(cmd
, 0, sizeof(*cmd
));
1775 cmd
->port
= PORT_MII
;
1776 cmd
->transceiver
= XCVR_INTERNAL
;
1777 cmd
->phy_address
= phy_address
;
1780 cmd
->autoneg
= AUTONEG_ENABLE
;
1781 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1782 cmd
->speed
= SPEED_100
;
1783 cmd
->advertising
= ADVERTISED_10baseT_Half
|
1784 ADVERTISED_10baseT_Full
|
1785 ADVERTISED_100baseT_Half
|
1786 ADVERTISED_100baseT_Full
;
1787 if (mp
->mii
.supports_gmii
)
1788 cmd
->advertising
|= ADVERTISED_1000baseT_Full
;
1790 cmd
->autoneg
= AUTONEG_DISABLE
;
1792 cmd
->duplex
= duplex
;
1799 * First function called after registering the network device.
1800 * It's purpose is to initialize the device as an ethernet device,
1801 * fill the ethernet device structure with pointers * to functions,
1802 * and set the MAC address of the interface
1804 * Input : struct device *
1805 * Output : -ENOMEM if failed , 0 if success
1807 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1809 struct mv643xx_eth_platform_data
*pd
;
1811 struct mv643xx_private
*mp
;
1812 struct net_device
*dev
;
1814 struct resource
*res
;
1816 struct ethtool_cmd cmd
;
1817 int duplex
= DUPLEX_HALF
;
1818 int speed
= 0; /* default to auto-negotiation */
1819 DECLARE_MAC_BUF(mac
);
1821 pd
= pdev
->dev
.platform_data
;
1823 printk(KERN_ERR
"No mv643xx_eth_platform_data\n");
1827 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1831 platform_set_drvdata(pdev
, dev
);
1833 mp
= netdev_priv(dev
);
1836 netif_napi_add(dev
, &mp
->napi
, mv643xx_poll
, 64);
1839 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1841 dev
->irq
= res
->start
;
1843 dev
->open
= mv643xx_eth_open
;
1844 dev
->stop
= mv643xx_eth_stop
;
1845 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1846 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1847 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1849 /* No need to Tx Timeout */
1850 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1852 #ifdef CONFIG_NET_POLL_CONTROLLER
1853 dev
->poll_controller
= mv643xx_netpoll
;
1856 dev
->watchdog_timeo
= 2 * HZ
;
1858 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1859 dev
->do_ioctl
= mv643xx_eth_do_ioctl
;
1860 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1862 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1863 #ifdef MAX_SKB_FRAGS
1865 * Zero copy can only work if we use Discovery II memory. Else, we will
1866 * have to map the buffers to ISA memory which is only 16 MB
1868 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
1872 /* Configure the timeout task */
1873 INIT_WORK(&mp
->tx_timeout_task
, mv643xx_eth_tx_timeout_task
);
1875 spin_lock_init(&mp
->lock
);
1877 port_num
= mp
->port_num
= pd
->port_number
;
1879 /* set default config values */
1880 eth_port_uc_addr_get(mp
, dev
->dev_addr
);
1881 mp
->rx_ring_size
= PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1882 mp
->tx_ring_size
= PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1884 if (is_valid_ether_addr(pd
->mac_addr
))
1885 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1887 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1888 ethernet_phy_set(mp
, pd
->phy_addr
);
1890 if (pd
->rx_queue_size
)
1891 mp
->rx_ring_size
= pd
->rx_queue_size
;
1893 if (pd
->tx_queue_size
)
1894 mp
->tx_ring_size
= pd
->tx_queue_size
;
1896 if (pd
->tx_sram_size
) {
1897 mp
->tx_sram_size
= pd
->tx_sram_size
;
1898 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1901 if (pd
->rx_sram_size
) {
1902 mp
->rx_sram_size
= pd
->rx_sram_size
;
1903 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1906 duplex
= pd
->duplex
;
1909 /* Hook up MII support for ethtool */
1911 mp
->mii
.mdio_read
= mv643xx_mdio_read
;
1912 mp
->mii
.mdio_write
= mv643xx_mdio_write
;
1913 mp
->mii
.phy_id
= ethernet_phy_get(mp
);
1914 mp
->mii
.phy_id_mask
= 0x3f;
1915 mp
->mii
.reg_num_mask
= 0x1f;
1917 err
= ethernet_phy_detect(mp
);
1919 pr_debug("MV643xx ethernet port %d: "
1920 "No PHY detected at addr %d\n",
1921 port_num
, ethernet_phy_get(mp
));
1925 ethernet_phy_reset(mp
);
1926 mp
->mii
.supports_gmii
= mii_check_gmii_support(&mp
->mii
);
1927 mv643xx_init_ethtool_cmd(dev
, mp
->mii
.phy_id
, speed
, duplex
, &cmd
);
1928 mv643xx_eth_update_pscr(dev
, &cmd
);
1929 mv643xx_set_settings(dev
, &cmd
);
1931 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1932 err
= register_netdev(dev
);
1938 "%s: port %d with MAC address %s\n",
1939 dev
->name
, port_num
, print_mac(mac
, p
));
1941 if (dev
->features
& NETIF_F_SG
)
1942 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1944 if (dev
->features
& NETIF_F_IP_CSUM
)
1945 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1948 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1949 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1953 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1958 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1961 if (mp
->tx_sram_size
> 0)
1962 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1972 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1974 struct net_device
*dev
= platform_get_drvdata(pdev
);
1976 unregister_netdev(dev
);
1977 flush_scheduled_work();
1980 platform_set_drvdata(pdev
, NULL
);
1984 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1986 struct resource
*res
;
1988 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1990 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1994 mv643xx_eth_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1995 if (mv643xx_eth_base
== NULL
)
2002 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2004 iounmap(mv643xx_eth_base
);
2005 mv643xx_eth_base
= NULL
;
2010 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
2012 struct net_device
*dev
= platform_get_drvdata(pdev
);
2013 struct mv643xx_private
*mp
= netdev_priv(dev
);
2014 unsigned int port_num
= mp
->port_num
;
2016 /* Mask all interrupts on ethernet port */
2017 mv_write(INTERRUPT_MASK_REG(port_num
), 0);
2018 mv_read (INTERRUPT_MASK_REG(port_num
));
2023 static struct platform_driver mv643xx_eth_driver
= {
2024 .probe
= mv643xx_eth_probe
,
2025 .remove
= mv643xx_eth_remove
,
2026 .shutdown
= mv643xx_eth_shutdown
,
2028 .name
= MV643XX_ETH_NAME
,
2032 static struct platform_driver mv643xx_eth_shared_driver
= {
2033 .probe
= mv643xx_eth_shared_probe
,
2034 .remove
= mv643xx_eth_shared_remove
,
2036 .name
= MV643XX_ETH_SHARED_NAME
,
2041 * mv643xx_init_module
2043 * Registers the network drivers into the Linux kernel
2049 static int __init
mv643xx_init_module(void)
2053 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
2055 rc
= platform_driver_register(&mv643xx_eth_driver
);
2057 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2063 * mv643xx_cleanup_module
2065 * Registers the network drivers into the Linux kernel
2071 static void __exit
mv643xx_cleanup_module(void)
2073 platform_driver_unregister(&mv643xx_eth_driver
);
2074 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2077 module_init(mv643xx_init_module
);
2078 module_exit(mv643xx_cleanup_module
);
2080 MODULE_LICENSE("GPL");
2081 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2082 " and Dale Farnsworth");
2083 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2084 MODULE_ALIAS("platform:mv643xx_eth");
2087 * The second part is the low level driver of the gigE ethernet ports.
2091 * Marvell's Gigabit Ethernet controller low level driver
2094 * This file introduce low level API to Marvell's Gigabit Ethernet
2095 * controller. This Gigabit Ethernet Controller driver API controls
2096 * 1) Operations (i.e. port init, start, reset etc').
2097 * 2) Data flow (i.e. port send, receive etc').
2098 * Each Gigabit Ethernet port is controlled via
2099 * struct mv643xx_private.
2100 * This struct includes user configuration information as well as
2101 * driver internal data needed for its operations.
2103 * Supported Features:
2104 * - This low level driver is OS independent. Allocating memory for
2105 * the descriptor rings and buffers are not within the scope of
2107 * - The user is free from Rx/Tx queue managing.
2108 * - This low level driver introduce functionality API that enable
2109 * the to operate Marvell's Gigabit Ethernet Controller in a
2111 * - Simple Gigabit Ethernet port operation API.
2112 * - Simple Gigabit Ethernet port data flow API.
2113 * - Data flow and operation API support per queue functionality.
2114 * - Support cached descriptors for better performance.
2115 * - Enable access to all four DRAM banks and internal SRAM memory
2117 * - PHY access and control API.
2118 * - Port control register configuration API.
2119 * - Full control over Unicast and Multicast MAC configurations.
2123 * Initialization phase
2124 * This phase complete the initialization of the the
2125 * mv643xx_private struct.
2126 * User information regarding port configuration has to be set
2127 * prior to calling the port initialization routine.
2129 * In this phase any port Tx/Rx activity is halted, MIB counters
2130 * are cleared, PHY address is set according to user parameter and
2131 * access to DRAM and internal SRAM memory spaces.
2133 * Driver ring initialization
2134 * Allocating memory for the descriptor rings and buffers is not
2135 * within the scope of this driver. Thus, the user is required to
2136 * allocate memory for the descriptors ring and buffers. Those
2137 * memory parameters are used by the Rx and Tx ring initialization
2138 * routines in order to curve the descriptor linked list in a form
2140 * Note: Pay special attention to alignment issues when using
2141 * cached descriptors/buffers. In this phase the driver store
2142 * information in the mv643xx_private struct regarding each queue
2146 * This phase prepares the Ethernet port for Rx and Tx activity.
2147 * It uses the information stored in the mv643xx_private struct to
2148 * initialize the various port registers.
2151 * All packet references to/from the driver are done using
2153 * This struct is a unified struct used with Rx and Tx operations.
2154 * This way the user is not required to be familiar with neither
2155 * Tx nor Rx descriptors structures.
2156 * The driver's descriptors rings are management by indexes.
2157 * Those indexes controls the ring resources and used to indicate
2158 * a SW resource error:
2160 * This index points to the current available resource for use. For
2161 * example in Rx process this index will point to the descriptor
2162 * that will be passed to the user upon calling the receive
2163 * routine. In Tx process, this index will point to the descriptor
2164 * that will be assigned with the user packet info and transmitted.
2166 * This index points to the descriptor that need to restore its
2167 * resources. For example in Rx process, using the Rx buffer return
2168 * API will attach the buffer returned in packet info to the
2169 * descriptor pointed by 'used'. In Tx process, using the Tx
2170 * descriptor return will merely return the user packet info with
2171 * the command status of the transmitted buffer pointed by the
2172 * 'used' index. Nevertheless, it is essential to use this routine
2173 * to update the 'used' index.
2175 * This index supports Tx Scatter-Gather. It points to the first
2176 * descriptor of a packet assembled of multiple buffers. For
2177 * example when in middle of Such packet we have a Tx resource
2178 * error the 'curr' index get the value of 'first' to indicate
2179 * that the ring returned to its state before trying to transmit
2182 * Receive operation:
2183 * The eth_port_receive API set the packet information struct,
2184 * passed by the caller, with received information from the
2185 * 'current' SDMA descriptor.
2186 * It is the user responsibility to return this resource back
2187 * to the Rx descriptor ring to enable the reuse of this source.
2188 * Return Rx resource is done using the eth_rx_return_buff API.
2190 * Prior to calling the initialization routine eth_port_init() the user
2191 * must set the following fields under mv643xx_private struct:
2192 * port_num User Ethernet port number.
2193 * port_config User port configuration value.
2194 * port_config_extend User port config extend value.
2195 * port_sdma_config User port SDMA config value.
2196 * port_serial_control User port serial control value.
2198 * This driver data flow is done using the struct pkt_info which
2199 * is a unified struct for Rx and Tx operations:
2201 * byte_cnt Tx/Rx descriptor buffer byte count.
2202 * l4i_chk CPU provided TCP Checksum. For Tx operation
2204 * cmd_sts Tx/Rx descriptor command status.
2205 * buf_ptr Tx/Rx descriptor buffer pointer.
2206 * return_info Tx/Rx user resource return information.
2209 /* Ethernet Port routines */
2210 static void eth_port_set_filter_table_entry(struct mv643xx_private
*mp
,
2211 int table
, unsigned char entry
);
2214 * eth_port_init - Initialize the Ethernet port driver
2217 * This function prepares the ethernet port to start its activity:
2218 * 1) Completes the ethernet port driver struct initialization toward port
2220 * 2) Resets the device to a quiescent state in case of warm reboot.
2221 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2222 * 4) Clean MAC tables. The reset status of those tables is unknown.
2223 * 5) Set PHY address.
2224 * Note: Call this routine prior to eth_port_start routine and after
2225 * setting user values in the user fields of Ethernet port control
2229 * struct mv643xx_private *mp Ethernet port control struct
2237 static void eth_port_init(struct mv643xx_private
*mp
)
2239 mp
->rx_resource_err
= 0;
2243 eth_port_init_mac_tables(mp
);
2247 * eth_port_start - Start the Ethernet port activity.
2250 * This routine prepares the Ethernet port for Rx and Tx activity:
2251 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2252 * has been initialized a descriptor's ring (using
2253 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2254 * 2. Initialize and enable the Ethernet configuration port by writing to
2255 * the port's configuration and command registers.
2256 * 3. Initialize and enable the SDMA by writing to the SDMA's
2257 * configuration and command registers. After completing these steps,
2258 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2260 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2261 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2262 * and ether_init_rx_desc_ring for Rx queues).
2265 * dev - a pointer to the required interface
2268 * Ethernet port is ready to receive and transmit.
2273 static void eth_port_start(struct net_device
*dev
)
2275 struct mv643xx_private
*mp
= netdev_priv(dev
);
2276 unsigned int port_num
= mp
->port_num
;
2277 int tx_curr_desc
, rx_curr_desc
;
2279 struct ethtool_cmd ethtool_cmd
;
2281 /* Assignment of Tx CTRP of given queue */
2282 tx_curr_desc
= mp
->tx_curr_desc_q
;
2283 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
2284 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
2286 /* Assignment of Rx CRDP of given queue */
2287 rx_curr_desc
= mp
->rx_curr_desc_q
;
2288 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
2289 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
2291 /* Add the assigned Ethernet address to the port's address table */
2292 eth_port_uc_addr_set(mp
, dev
->dev_addr
);
2294 /* Assign port configuration and command. */
2295 mv_write(PORT_CONFIG_REG(port_num
),
2296 PORT_CONFIG_DEFAULT_VALUE
);
2298 mv_write(PORT_CONFIG_EXTEND_REG(port_num
),
2299 PORT_CONFIG_EXTEND_DEFAULT_VALUE
);
2301 pscr
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
2303 pscr
&= ~(SERIAL_PORT_ENABLE
| FORCE_LINK_PASS
);
2304 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2306 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
|
2307 DISABLE_AUTO_NEG_SPEED_GMII
|
2308 DISABLE_AUTO_NEG_FOR_DUPLX
|
2309 DO_NOT_FORCE_LINK_FAIL
|
2310 SERIAL_PORT_CONTROL_RESERVED
;
2312 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2314 pscr
|= SERIAL_PORT_ENABLE
;
2315 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2317 /* Assign port SDMA configuration */
2318 mv_write(SDMA_CONFIG_REG(port_num
),
2319 PORT_SDMA_CONFIG_DEFAULT_VALUE
);
2321 /* Enable port Rx. */
2322 mv643xx_eth_port_enable_rx(mp
, ETH_RX_QUEUES_ENABLED
);
2324 /* Disable port bandwidth limits by clearing MTU register */
2325 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
2327 /* save phy settings across reset */
2328 mv643xx_get_settings(dev
, ðtool_cmd
);
2329 ethernet_phy_reset(mp
);
2330 mv643xx_set_settings(dev
, ðtool_cmd
);
2334 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2336 static void eth_port_uc_addr_set(struct mv643xx_private
*mp
,
2337 unsigned char *p_addr
)
2339 unsigned int port_num
= mp
->port_num
;
2344 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
2345 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
2348 mv_write(MAC_ADDR_LOW(port_num
), mac_l
);
2349 mv_write(MAC_ADDR_HIGH(port_num
), mac_h
);
2351 /* Accept frames with this address */
2352 table
= DA_FILTER_UNICAST_TABLE_BASE(port_num
);
2353 eth_port_set_filter_table_entry(mp
, table
, p_addr
[5] & 0x0f);
2357 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2359 static void eth_port_uc_addr_get(struct mv643xx_private
*mp
,
2360 unsigned char *p_addr
)
2362 unsigned int port_num
= mp
->port_num
;
2366 mac_h
= mv_read(MAC_ADDR_HIGH(port_num
));
2367 mac_l
= mv_read(MAC_ADDR_LOW(port_num
));
2369 p_addr
[0] = (mac_h
>> 24) & 0xff;
2370 p_addr
[1] = (mac_h
>> 16) & 0xff;
2371 p_addr
[2] = (mac_h
>> 8) & 0xff;
2372 p_addr
[3] = mac_h
& 0xff;
2373 p_addr
[4] = (mac_l
>> 8) & 0xff;
2374 p_addr
[5] = mac_l
& 0xff;
2378 * The entries in each table are indexed by a hash of a packet's MAC
2379 * address. One bit in each entry determines whether the packet is
2380 * accepted. There are 4 entries (each 8 bits wide) in each register
2381 * of the table. The bits in each entry are defined as follows:
2382 * 0 Accept=1, Drop=0
2383 * 3-1 Queue (ETH_Q0=0)
2386 static void eth_port_set_filter_table_entry(struct mv643xx_private
*mp
,
2387 int table
, unsigned char entry
)
2389 unsigned int table_reg
;
2390 unsigned int tbl_offset
;
2391 unsigned int reg_offset
;
2393 tbl_offset
= (entry
/ 4) * 4; /* Register offset of DA table entry */
2394 reg_offset
= entry
% 4; /* Entry offset within the register */
2396 /* Set "accepts frame bit" at specified table entry */
2397 table_reg
= mv_read(table
+ tbl_offset
);
2398 table_reg
|= 0x01 << (8 * reg_offset
);
2399 mv_write(table
+ tbl_offset
, table_reg
);
2403 * eth_port_mc_addr - Multicast address settings.
2405 * The MV device supports multicast using two tables:
2406 * 1) Special Multicast Table for MAC addresses of the form
2407 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2408 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2409 * Table entries in the DA-Filter table.
2410 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2411 * is used as an index to the Other Multicast Table entries in the
2412 * DA-Filter table. This function calculates the CRC-8bit value.
2413 * In either case, eth_port_set_filter_table_entry() is then called
2414 * to set to set the actual table entry.
2416 static void eth_port_mc_addr(struct mv643xx_private
*mp
, unsigned char *p_addr
)
2418 unsigned int port_num
= mp
->port_num
;
2421 unsigned char crc_result
= 0;
2427 if ((p_addr
[0] == 0x01) && (p_addr
[1] == 0x00) &&
2428 (p_addr
[2] == 0x5E) && (p_addr
[3] == 0x00) && (p_addr
[4] == 0x00)) {
2429 table
= DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num
);
2430 eth_port_set_filter_table_entry(mp
, table
, p_addr
[5]);
2434 /* Calculate CRC-8 out of the given address */
2435 mac_h
= (p_addr
[0] << 8) | (p_addr
[1]);
2436 mac_l
= (p_addr
[2] << 24) | (p_addr
[3] << 16) |
2437 (p_addr
[4] << 8) | (p_addr
[5] << 0);
2439 for (i
= 0; i
< 32; i
++)
2440 mac_array
[i
] = (mac_l
>> i
) & 0x1;
2441 for (i
= 32; i
< 48; i
++)
2442 mac_array
[i
] = (mac_h
>> (i
- 32)) & 0x1;
2444 crc
[0] = mac_array
[45] ^ mac_array
[43] ^ mac_array
[40] ^ mac_array
[39] ^
2445 mac_array
[35] ^ mac_array
[34] ^ mac_array
[31] ^ mac_array
[30] ^
2446 mac_array
[28] ^ mac_array
[23] ^ mac_array
[21] ^ mac_array
[19] ^
2447 mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^ mac_array
[12] ^
2448 mac_array
[8] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[0];
2450 crc
[1] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2451 mac_array
[41] ^ mac_array
[39] ^ mac_array
[36] ^ mac_array
[34] ^
2452 mac_array
[32] ^ mac_array
[30] ^ mac_array
[29] ^ mac_array
[28] ^
2453 mac_array
[24] ^ mac_array
[23] ^ mac_array
[22] ^ mac_array
[21] ^
2454 mac_array
[20] ^ mac_array
[18] ^ mac_array
[17] ^ mac_array
[16] ^
2455 mac_array
[15] ^ mac_array
[14] ^ mac_array
[13] ^ mac_array
[12] ^
2456 mac_array
[9] ^ mac_array
[6] ^ mac_array
[1] ^ mac_array
[0];
2458 crc
[2] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[44] ^ mac_array
[43] ^
2459 mac_array
[42] ^ mac_array
[39] ^ mac_array
[37] ^ mac_array
[34] ^
2460 mac_array
[33] ^ mac_array
[29] ^ mac_array
[28] ^ mac_array
[25] ^
2461 mac_array
[24] ^ mac_array
[22] ^ mac_array
[17] ^ mac_array
[15] ^
2462 mac_array
[13] ^ mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^
2463 mac_array
[6] ^ mac_array
[2] ^ mac_array
[1] ^ mac_array
[0];
2465 crc
[3] = mac_array
[47] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2466 mac_array
[40] ^ mac_array
[38] ^ mac_array
[35] ^ mac_array
[34] ^
2467 mac_array
[30] ^ mac_array
[29] ^ mac_array
[26] ^ mac_array
[25] ^
2468 mac_array
[23] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^
2469 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[7] ^
2470 mac_array
[3] ^ mac_array
[2] ^ mac_array
[1];
2472 crc
[4] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[41] ^
2473 mac_array
[39] ^ mac_array
[36] ^ mac_array
[35] ^ mac_array
[31] ^
2474 mac_array
[30] ^ mac_array
[27] ^ mac_array
[26] ^ mac_array
[24] ^
2475 mac_array
[19] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[14] ^
2476 mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^ mac_array
[4] ^
2477 mac_array
[3] ^ mac_array
[2];
2479 crc
[5] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[45] ^ mac_array
[42] ^
2480 mac_array
[40] ^ mac_array
[37] ^ mac_array
[36] ^ mac_array
[32] ^
2481 mac_array
[31] ^ mac_array
[28] ^ mac_array
[27] ^ mac_array
[25] ^
2482 mac_array
[20] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[15] ^
2483 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[5] ^
2484 mac_array
[4] ^ mac_array
[3];
2486 crc
[6] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[43] ^ mac_array
[41] ^
2487 mac_array
[38] ^ mac_array
[37] ^ mac_array
[33] ^ mac_array
[32] ^
2488 mac_array
[29] ^ mac_array
[28] ^ mac_array
[26] ^ mac_array
[21] ^
2489 mac_array
[19] ^ mac_array
[17] ^ mac_array
[16] ^ mac_array
[14] ^
2490 mac_array
[12] ^ mac_array
[10] ^ mac_array
[6] ^ mac_array
[5] ^
2493 crc
[7] = mac_array
[47] ^ mac_array
[44] ^ mac_array
[42] ^ mac_array
[39] ^
2494 mac_array
[38] ^ mac_array
[34] ^ mac_array
[33] ^ mac_array
[30] ^
2495 mac_array
[29] ^ mac_array
[27] ^ mac_array
[22] ^ mac_array
[20] ^
2496 mac_array
[18] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[13] ^
2497 mac_array
[11] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[5];
2499 for (i
= 0; i
< 8; i
++)
2500 crc_result
= crc_result
| (crc
[i
] << i
);
2502 table
= DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num
);
2503 eth_port_set_filter_table_entry(mp
, table
, crc_result
);
2507 * Set the entire multicast list based on dev->mc_list.
2509 static void eth_port_set_multicast_list(struct net_device
*dev
)
2512 struct dev_mc_list
*mc_list
;
2515 struct mv643xx_private
*mp
= netdev_priv(dev
);
2516 unsigned int eth_port_num
= mp
->port_num
;
2518 /* If the device is in promiscuous mode or in all multicast mode,
2519 * we will fully populate both multicast tables with accept.
2520 * This is guaranteed to yield a match on all multicast addresses...
2522 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
)) {
2523 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2524 /* Set all entries in DA filter special multicast
2526 * Set for ETH_Q0 for now
2528 * 0 Accept=1, Drop=0
2529 * 3-1 Queue ETH_Q0=0
2532 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2534 /* Set all entries in DA filter other multicast
2536 * Set for ETH_Q0 for now
2538 * 0 Accept=1, Drop=0
2539 * 3-1 Queue ETH_Q0=0
2542 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2547 /* We will clear out multicast tables every time we get the list.
2548 * Then add the entire new list...
2550 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2551 /* Clear DA filter special multicast table (Ex_dFSMT) */
2552 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2553 (eth_port_num
) + table_index
, 0);
2555 /* Clear DA filter other multicast table (Ex_dFOMT) */
2556 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2557 (eth_port_num
) + table_index
, 0);
2560 /* Get pointer to net_device multicast list and add each one... */
2561 for (i
= 0, mc_list
= dev
->mc_list
;
2562 (i
< 256) && (mc_list
!= NULL
) && (i
< dev
->mc_count
);
2563 i
++, mc_list
= mc_list
->next
)
2564 if (mc_list
->dmi_addrlen
== 6)
2565 eth_port_mc_addr(mp
, mc_list
->dmi_addr
);
2569 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2572 * Go through all the DA filter tables (Unicast, Special Multicast &
2573 * Other Multicast) and set each entry to 0.
2576 * struct mv643xx_private *mp Ethernet Port.
2579 * Multicast and Unicast packets are rejected.
2584 static void eth_port_init_mac_tables(struct mv643xx_private
*mp
)
2586 unsigned int port_num
= mp
->port_num
;
2589 /* Clear DA filter unicast table (Ex_dFUT) */
2590 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2591 mv_write(DA_FILTER_UNICAST_TABLE_BASE(port_num
) +
2594 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2595 /* Clear DA filter special multicast table (Ex_dFSMT) */
2596 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port_num
) +
2598 /* Clear DA filter other multicast table (Ex_dFOMT) */
2599 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port_num
) +
2605 * eth_clear_mib_counters - Clear all MIB counters
2608 * This function clears all MIB counters of a specific ethernet port.
2609 * A read from the MIB counter will reset the counter.
2612 * struct mv643xx_private *mp Ethernet Port.
2615 * After reading all MIB counters, the counters resets.
2618 * MIB counter value.
2621 static void eth_clear_mib_counters(struct mv643xx_private
*mp
)
2623 unsigned int port_num
= mp
->port_num
;
2626 /* Perform dummy reads from MIB counters */
2627 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2629 mv_read(MIB_COUNTERS_BASE(port_num
) + i
);
2632 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2634 return mv_read(MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2637 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2639 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2642 p
->good_octets_received
+=
2643 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2644 p
->good_octets_received
+=
2645 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2647 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2648 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2650 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2652 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2653 p
->good_octets_sent
+=
2654 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2656 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2657 offset
<= ETH_MIB_LATE_COLLISION
;
2659 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2663 * ethernet_phy_detect - Detect whether a phy is present
2666 * This function tests whether there is a PHY present on
2667 * the specified port.
2670 * struct mv643xx_private *mp Ethernet Port.
2677 * -ENODEV on failure
2680 static int ethernet_phy_detect(struct mv643xx_private
*mp
)
2682 unsigned int phy_reg_data0
;
2685 eth_port_read_smi_reg(mp
, 0, &phy_reg_data0
);
2686 auto_neg
= phy_reg_data0
& 0x1000;
2687 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2688 eth_port_write_smi_reg(mp
, 0, phy_reg_data0
);
2690 eth_port_read_smi_reg(mp
, 0, &phy_reg_data0
);
2691 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2692 return -ENODEV
; /* change didn't take */
2694 phy_reg_data0
^= 0x1000;
2695 eth_port_write_smi_reg(mp
, 0, phy_reg_data0
);
2700 * ethernet_phy_get - Get the ethernet port PHY address.
2703 * This routine returns the given ethernet port PHY address.
2706 * struct mv643xx_private *mp Ethernet Port.
2715 static int ethernet_phy_get(struct mv643xx_private
*mp
)
2717 unsigned int reg_data
;
2719 reg_data
= mv_read(PHY_ADDR_REG
);
2721 return ((reg_data
>> (5 * mp
->port_num
)) & 0x1f);
2725 * ethernet_phy_set - Set the ethernet port PHY address.
2728 * This routine sets the given ethernet port PHY address.
2731 * struct mv643xx_private *mp Ethernet Port.
2732 * int phy_addr PHY address.
2741 static void ethernet_phy_set(struct mv643xx_private
*mp
, int phy_addr
)
2744 int addr_shift
= 5 * mp
->port_num
;
2746 reg_data
= mv_read(PHY_ADDR_REG
);
2747 reg_data
&= ~(0x1f << addr_shift
);
2748 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2749 mv_write(PHY_ADDR_REG
, reg_data
);
2753 * ethernet_phy_reset - Reset Ethernet port PHY.
2756 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2759 * struct mv643xx_private *mp Ethernet Port.
2768 static void ethernet_phy_reset(struct mv643xx_private
*mp
)
2770 unsigned int phy_reg_data
;
2773 eth_port_read_smi_reg(mp
, 0, &phy_reg_data
);
2774 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2775 eth_port_write_smi_reg(mp
, 0, phy_reg_data
);
2777 /* wait for PHY to come out of reset */
2780 eth_port_read_smi_reg(mp
, 0, &phy_reg_data
);
2781 } while (phy_reg_data
& 0x8000);
2784 static void mv643xx_eth_port_enable_tx(struct mv643xx_private
*mp
,
2785 unsigned int queues
)
2787 mv_write(TRANSMIT_QUEUE_COMMAND_REG(mp
->port_num
), queues
);
2790 static void mv643xx_eth_port_enable_rx(struct mv643xx_private
*mp
,
2791 unsigned int queues
)
2793 mv_write(RECEIVE_QUEUE_COMMAND_REG(mp
->port_num
), queues
);
2796 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_private
*mp
)
2798 unsigned int port_num
= mp
->port_num
;
2801 /* Stop Tx port activity. Check port Tx activity. */
2802 queues
= mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num
)) & 0xFF;
2804 /* Issue stop command for active queues only */
2805 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num
), (queues
<< 8));
2807 /* Wait for all Tx activity to terminate. */
2808 /* Check port cause register that all Tx queues are stopped */
2809 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num
)) & 0xFF)
2810 udelay(PHY_WAIT_MICRO_SECONDS
);
2812 /* Wait for Tx FIFO to empty */
2813 while (mv_read(PORT_STATUS_REG(port_num
)) &
2814 ETH_PORT_TX_FIFO_EMPTY
)
2815 udelay(PHY_WAIT_MICRO_SECONDS
);
2821 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_private
*mp
)
2823 unsigned int port_num
= mp
->port_num
;
2826 /* Stop Rx port activity. Check port Rx activity. */
2827 queues
= mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num
)) & 0xFF;
2829 /* Issue stop command for active queues only */
2830 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num
), (queues
<< 8));
2832 /* Wait for all Rx activity to terminate. */
2833 /* Check port cause register that all Rx queues are stopped */
2834 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num
)) & 0xFF)
2835 udelay(PHY_WAIT_MICRO_SECONDS
);
2842 * eth_port_reset - Reset Ethernet port
2845 * This routine resets the chip by aborting any SDMA engine activity and
2846 * clearing the MIB counters. The Receiver and the Transmit unit are in
2847 * idle state after this command is performed and the port is disabled.
2850 * struct mv643xx_private *mp Ethernet Port.
2853 * Channel activity is halted.
2859 static void eth_port_reset(struct mv643xx_private
*mp
)
2861 unsigned int port_num
= mp
->port_num
;
2862 unsigned int reg_data
;
2864 mv643xx_eth_port_disable_tx(mp
);
2865 mv643xx_eth_port_disable_rx(mp
);
2867 /* Clear all MIB counters */
2868 eth_clear_mib_counters(mp
);
2870 /* Reset the Enable bit in the Configuration Register */
2871 reg_data
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
2872 reg_data
&= ~(SERIAL_PORT_ENABLE
|
2873 DO_NOT_FORCE_LINK_FAIL
|
2875 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2880 * eth_port_read_smi_reg - Read PHY registers
2883 * This routine utilize the SMI interface to interact with the PHY in
2884 * order to perform PHY register read.
2887 * struct mv643xx_private *mp Ethernet Port.
2888 * unsigned int phy_reg PHY register address offset.
2889 * unsigned int *value Register value buffer.
2892 * Write the value of a specified PHY register into given buffer.
2895 * false if the PHY is busy or read data is not in valid state.
2899 static void eth_port_read_smi_reg(struct mv643xx_private
*mp
,
2900 unsigned int phy_reg
, unsigned int *value
)
2902 int phy_addr
= ethernet_phy_get(mp
);
2903 unsigned long flags
;
2906 /* the SMI register is a shared resource */
2907 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2909 /* wait for the SMI register to become available */
2910 for (i
= 0; mv_read(SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2911 if (i
== PHY_WAIT_ITERATIONS
) {
2912 printk("mv643xx PHY busy timeout, port %d\n",
2916 udelay(PHY_WAIT_MICRO_SECONDS
);
2920 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2922 /* now wait for the data to be valid */
2923 for (i
= 0; !(mv_read(SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2924 if (i
== PHY_WAIT_ITERATIONS
) {
2925 printk("mv643xx PHY read timeout, port %d\n",
2929 udelay(PHY_WAIT_MICRO_SECONDS
);
2932 *value
= mv_read(SMI_REG
) & 0xffff;
2934 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2938 * eth_port_write_smi_reg - Write to PHY registers
2941 * This routine utilize the SMI interface to interact with the PHY in
2942 * order to perform writes to PHY registers.
2945 * struct mv643xx_private *mp Ethernet Port.
2946 * unsigned int phy_reg PHY register address offset.
2947 * unsigned int value Register value.
2950 * Write the given value to the specified PHY register.
2953 * false if the PHY is busy.
2957 static void eth_port_write_smi_reg(struct mv643xx_private
*mp
,
2958 unsigned int phy_reg
, unsigned int value
)
2962 unsigned long flags
;
2964 phy_addr
= ethernet_phy_get(mp
);
2966 /* the SMI register is a shared resource */
2967 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2969 /* wait for the SMI register to become available */
2970 for (i
= 0; mv_read(SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2971 if (i
== PHY_WAIT_ITERATIONS
) {
2972 printk("mv643xx PHY busy timeout, port %d\n",
2976 udelay(PHY_WAIT_MICRO_SECONDS
);
2979 mv_write(SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2980 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2982 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2986 * Wrappers for MII support library.
2988 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
2990 struct mv643xx_private
*mp
= netdev_priv(dev
);
2993 eth_port_read_smi_reg(mp
, location
, &val
);
2997 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
)
2999 struct mv643xx_private
*mp
= netdev_priv(dev
);
3000 eth_port_write_smi_reg(mp
, location
, val
);
3004 * eth_port_receive - Get received information from Rx ring.
3007 * This routine returns the received data to the caller. There is no
3008 * data copying during routine operation. All information is returned
3009 * using pointer to packet information struct passed from the caller.
3010 * If the routine exhausts Rx ring resources then the resource error flag
3014 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3015 * struct pkt_info *p_pkt_info User packet buffer.
3018 * Rx ring current and used indexes are updated.
3021 * ETH_ERROR in case the routine can not access Rx desc ring.
3022 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3023 * ETH_END_OF_JOB if there is no received data.
3026 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
3027 struct pkt_info
*p_pkt_info
)
3029 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
3030 volatile struct eth_rx_desc
*p_rx_desc
;
3031 unsigned int command_status
;
3032 unsigned long flags
;
3034 /* Do not process Rx ring in case of Rx ring resource error */
3035 if (mp
->rx_resource_err
)
3036 return ETH_QUEUE_FULL
;
3038 spin_lock_irqsave(&mp
->lock
, flags
);
3040 /* Get the Rx Desc ring 'curr and 'used' indexes */
3041 rx_curr_desc
= mp
->rx_curr_desc_q
;
3042 rx_used_desc
= mp
->rx_used_desc_q
;
3044 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
3046 /* The following parameters are used to save readings from memory */
3047 command_status
= p_rx_desc
->cmd_sts
;
3050 /* Nothing to receive... */
3051 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
3052 spin_unlock_irqrestore(&mp
->lock
, flags
);
3053 return ETH_END_OF_JOB
;
3056 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
3057 p_pkt_info
->cmd_sts
= command_status
;
3058 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
3059 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
3060 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
3063 * Clean the return info field to indicate that the
3064 * packet has been moved to the upper layers
3066 mp
->rx_skb
[rx_curr_desc
] = NULL
;
3068 /* Update current index in data structure */
3069 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
3070 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
3072 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
3073 if (rx_next_curr_desc
== rx_used_desc
)
3074 mp
->rx_resource_err
= 1;
3076 spin_unlock_irqrestore(&mp
->lock
, flags
);
3082 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3085 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3086 * next 'used' descriptor and attached the returned buffer to it.
3087 * In case the Rx ring was in "resource error" condition, where there are
3088 * no available Rx resources, the function resets the resource error flag.
3091 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3092 * struct pkt_info *p_pkt_info Information on returned buffer.
3095 * New available Rx resource in Rx descriptor ring.
3098 * ETH_ERROR in case the routine can not access Rx desc ring.
3101 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
3102 struct pkt_info
*p_pkt_info
)
3104 int used_rx_desc
; /* Where to return Rx resource */
3105 volatile struct eth_rx_desc
*p_used_rx_desc
;
3106 unsigned long flags
;
3108 spin_lock_irqsave(&mp
->lock
, flags
);
3110 /* Get 'used' Rx descriptor */
3111 used_rx_desc
= mp
->rx_used_desc_q
;
3112 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
3114 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
3115 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
3116 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
3118 /* Flush the write pipe */
3120 /* Return the descriptor to DMA ownership */
3122 p_used_rx_desc
->cmd_sts
=
3123 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
3126 /* Move the used descriptor pointer to the next descriptor */
3127 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
3129 /* Any Rx return cancels the Rx resource error status */
3130 mp
->rx_resource_err
= 0;
3132 spin_unlock_irqrestore(&mp
->lock
, flags
);
3137 /************* Begin ethtool support *************************/
3139 struct mv643xx_stats
{
3140 char stat_string
[ETH_GSTRING_LEN
];
3145 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
3146 offsetof(struct mv643xx_private, m)
3148 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
3149 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
3150 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
3151 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
3152 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
3153 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
3154 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
3155 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
3156 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
3157 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
3158 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
3159 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
3160 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
3161 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
3162 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
3163 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
3164 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
3165 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
3166 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
3167 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
3168 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
3169 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
3170 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
3171 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
3172 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
3173 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
3174 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
3175 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
3176 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
3177 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
3178 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
3179 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
3180 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
3181 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
3182 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
3183 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
3184 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
3185 { "collision", MV643XX_STAT(mib_counters
.collision
) },
3186 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
3189 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
3191 static void mv643xx_get_drvinfo(struct net_device
*netdev
,
3192 struct ethtool_drvinfo
*drvinfo
)
3194 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
3195 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
3196 strncpy(drvinfo
->fw_version
, "N/A", 32);
3197 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
3198 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
3201 static int mv643xx_get_sset_count(struct net_device
*netdev
, int sset
)
3205 return MV643XX_STATS_LEN
;
3211 static void mv643xx_get_ethtool_stats(struct net_device
*netdev
,
3212 struct ethtool_stats
*stats
, uint64_t *data
)
3214 struct mv643xx_private
*mp
= netdev
->priv
;
3217 eth_update_mib_counters(mp
);
3219 for (i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
3220 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
3221 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
3222 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
3226 static void mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
,
3233 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
3234 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3235 mv643xx_gstrings_stats
[i
].stat_string
,
3242 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
3244 struct mv643xx_private
*mp
= netdev_priv(dev
);
3246 return mii_link_ok(&mp
->mii
);
3249 static int mv643xx_eth_nway_restart(struct net_device
*dev
)
3251 struct mv643xx_private
*mp
= netdev_priv(dev
);
3253 return mii_nway_restart(&mp
->mii
);
3256 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3258 struct mv643xx_private
*mp
= netdev_priv(dev
);
3260 return generic_mii_ioctl(&mp
->mii
, if_mii(ifr
), cmd
, NULL
);
3263 static const struct ethtool_ops mv643xx_ethtool_ops
= {
3264 .get_settings
= mv643xx_get_settings
,
3265 .set_settings
= mv643xx_set_settings
,
3266 .get_drvinfo
= mv643xx_get_drvinfo
,
3267 .get_link
= mv643xx_eth_get_link
,
3268 .set_sg
= ethtool_op_set_sg
,
3269 .get_sset_count
= mv643xx_get_sset_count
,
3270 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
3271 .get_strings
= mv643xx_get_strings
,
3272 .nway_reset
= mv643xx_eth_nway_restart
,
3275 /************* End ethtool support *************************/