2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/spinlock.h>
49 #include <linux/workqueue.h>
50 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
55 #include <asm/types.h>
56 #include <asm/pgtable.h>
57 #include <asm/system.h>
58 #include <asm/delay.h>
59 #include <asm/dma-mapping.h>
61 #define MV643XX_CHECKSUM_OFFLOAD_TX
63 #define MV643XX_TX_FAST_REFILL
66 #define MV643XX_TX_COAL 100
68 #define MV643XX_RX_COAL 100
71 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
72 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
74 #define MAX_DESCS_PER_SKB 1
77 #define ETH_VLAN_HLEN 4
79 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
80 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
81 ETH_VLAN_HLEN + ETH_FCS_LEN)
82 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
83 dma_get_cache_alignment())
86 * Registers shared between all ports.
88 #define PHY_ADDR_REG 0x0000
89 #define SMI_REG 0x0004
94 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
95 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
96 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
97 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
98 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
99 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
100 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
101 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
102 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
103 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
104 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
105 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
106 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
107 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
108 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
109 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
110 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
111 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
112 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
113 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
114 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
116 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
117 #define UNICAST_NORMAL_MODE (0 << 0)
118 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
119 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
120 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
121 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
122 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
123 #define RECEIVE_BC_IF_IP (0 << 8)
124 #define REJECT_BC_IF_IP (1 << 8)
125 #define RECEIVE_BC_IF_ARP (0 << 9)
126 #define REJECT_BC_IF_ARP (1 << 9)
127 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
128 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
129 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
130 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
131 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
132 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
133 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
134 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
136 #define PORT_CONFIG_DEFAULT_VALUE \
137 UNICAST_NORMAL_MODE | \
138 DEFAULT_RX_QUEUE(0) | \
139 DEFAULT_RX_ARP_QUEUE(0) | \
140 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
142 RECEIVE_BC_IF_ARP | \
143 CAPTURE_TCP_FRAMES_DIS | \
144 CAPTURE_UDP_FRAMES_DIS | \
145 DEFAULT_RX_TCP_QUEUE(0) | \
146 DEFAULT_RX_UDP_QUEUE(0) | \
147 DEFAULT_RX_BPDU_QUEUE(0)
149 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
150 #define CLASSIFY_EN (1 << 0)
151 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
152 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
153 #define PARTITION_DISABLE (0 << 2)
154 #define PARTITION_ENABLE (1 << 2)
156 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
157 SPAN_BPDU_PACKETS_AS_NORMAL | \
160 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
161 #define RIFB (1 << 0)
162 #define RX_BURST_SIZE_1_64BIT (0 << 1)
163 #define RX_BURST_SIZE_2_64BIT (1 << 1)
164 #define RX_BURST_SIZE_4_64BIT (2 << 1)
165 #define RX_BURST_SIZE_8_64BIT (3 << 1)
166 #define RX_BURST_SIZE_16_64BIT (4 << 1)
167 #define BLM_RX_NO_SWAP (1 << 4)
168 #define BLM_RX_BYTE_SWAP (0 << 4)
169 #define BLM_TX_NO_SWAP (1 << 5)
170 #define BLM_TX_BYTE_SWAP (0 << 5)
171 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
172 #define DESCRIPTORS_NO_SWAP (0 << 6)
173 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
174 #define TX_BURST_SIZE_1_64BIT (0 << 22)
175 #define TX_BURST_SIZE_2_64BIT (1 << 22)
176 #define TX_BURST_SIZE_4_64BIT (2 << 22)
177 #define TX_BURST_SIZE_8_64BIT (3 << 22)
178 #define TX_BURST_SIZE_16_64BIT (4 << 22)
180 #if defined(__BIG_ENDIAN)
181 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
182 RX_BURST_SIZE_4_64BIT | \
184 TX_BURST_SIZE_4_64BIT
185 #elif defined(__LITTLE_ENDIAN)
186 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
187 RX_BURST_SIZE_4_64BIT | \
191 TX_BURST_SIZE_4_64BIT
193 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
196 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
197 #define SERIAL_PORT_DISABLE (0 << 0)
198 #define SERIAL_PORT_ENABLE (1 << 0)
199 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
200 #define FORCE_LINK_PASS (1 << 1)
201 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
202 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
203 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
204 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
205 #define ADV_NO_FLOW_CTRL (0 << 4)
206 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
207 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
208 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
209 #define FORCE_BP_MODE_NO_JAM (0 << 7)
210 #define FORCE_BP_MODE_JAM_TX (1 << 7)
211 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
212 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
213 #define FORCE_LINK_FAIL (0 << 10)
214 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
215 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
216 #define RETRANSMIT_FOREVER (1 << 11)
217 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
218 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
219 #define DTE_ADV_0 (0 << 14)
220 #define DTE_ADV_1 (1 << 14)
221 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
222 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
223 #define AUTO_NEG_NO_CHANGE (0 << 16)
224 #define RESTART_AUTO_NEG (1 << 16)
225 #define MAX_RX_PACKET_1518BYTE (0 << 17)
226 #define MAX_RX_PACKET_1522BYTE (1 << 17)
227 #define MAX_RX_PACKET_1552BYTE (2 << 17)
228 #define MAX_RX_PACKET_9022BYTE (3 << 17)
229 #define MAX_RX_PACKET_9192BYTE (4 << 17)
230 #define MAX_RX_PACKET_9700BYTE (5 << 17)
231 #define MAX_RX_PACKET_MASK (7 << 17)
232 #define CLR_EXT_LOOPBACK (0 << 20)
233 #define SET_EXT_LOOPBACK (1 << 20)
234 #define SET_HALF_DUPLEX_MODE (0 << 21)
235 #define SET_FULL_DUPLEX_MODE (1 << 21)
236 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
237 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
238 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
239 #define SET_GMII_SPEED_TO_1000 (1 << 23)
240 #define SET_MII_SPEED_TO_10 (0 << 24)
241 #define SET_MII_SPEED_TO_100 (1 << 24)
243 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
244 DO_NOT_FORCE_LINK_PASS | \
245 ENABLE_AUTO_NEG_FOR_DUPLX | \
246 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
247 ADV_SYMMETRIC_FLOW_CTRL | \
248 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
249 FORCE_BP_MODE_NO_JAM | \
250 (1 << 9) /* reserved */ | \
251 DO_NOT_FORCE_LINK_FAIL | \
252 RETRANSMIT_16_ATTEMPTS | \
253 ENABLE_AUTO_NEG_SPEED_GMII | \
255 DISABLE_AUTO_NEG_BYPASS | \
256 AUTO_NEG_NO_CHANGE | \
257 MAX_RX_PACKET_9700BYTE | \
259 SET_FULL_DUPLEX_MODE | \
260 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
262 /* These macros describe Ethernet Serial Status reg (PSR) bits */
263 #define PORT_STATUS_MODE_10_BIT (1 << 0)
264 #define PORT_STATUS_LINK_UP (1 << 1)
265 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
266 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
267 #define PORT_STATUS_GMII_1000 (1 << 4)
268 #define PORT_STATUS_MII_100 (1 << 5)
269 /* PSR bit 6 is undocumented */
270 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
271 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
272 #define PORT_STATUS_PARTITION (1 << 9)
273 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
274 /* PSR bits 11-31 are reserved */
276 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
277 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
281 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
282 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
284 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
285 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
286 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
287 #define ETH_INT_CAUSE_EXT 0x00000002
288 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
290 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
291 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
292 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
293 #define ETH_INT_CAUSE_PHY 0x00010000
294 #define ETH_INT_CAUSE_STATE 0x00100000
295 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
298 #define ETH_INT_MASK_ALL 0x00000000
299 #define ETH_INT_MASK_ALL_EXT 0x00000000
301 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
302 #define PHY_WAIT_MICRO_SECONDS 10
304 /* Buffer offset from buffer pointer */
305 #define RX_BUF_OFFSET 0x2
307 /* Gigabit Ethernet Unit Global Registers */
309 /* MIB Counters register definitions */
310 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
311 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
312 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
313 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
314 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
315 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
316 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
317 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
318 #define ETH_MIB_FRAMES_64_OCTETS 0x20
319 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
320 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
321 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
322 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
323 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
324 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
325 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
326 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
327 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
328 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
329 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
330 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
331 #define ETH_MIB_FC_SENT 0x54
332 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
333 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
334 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
335 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
336 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
337 #define ETH_MIB_JABBER_RECEIVED 0x6c
338 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
339 #define ETH_MIB_BAD_CRC_EVENT 0x74
340 #define ETH_MIB_COLLISION 0x78
341 #define ETH_MIB_LATE_COLLISION 0x7c
343 /* Port serial status reg (PSR) */
344 #define ETH_INTERFACE_PCM 0x00000001
345 #define ETH_LINK_IS_UP 0x00000002
346 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
347 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
348 #define ETH_GMII_SPEED_1000 0x00000010
349 #define ETH_MII_SPEED_100 0x00000020
350 #define ETH_TX_IN_PROGRESS 0x00000080
351 #define ETH_BYPASS_ACTIVE 0x00000100
352 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
353 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
356 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
357 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
358 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
359 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
361 /* Interrupt Cause Register Bit Definitions */
363 /* SDMA command status fields macros */
365 /* Tx & Rx descriptors status */
366 #define ETH_ERROR_SUMMARY 0x00000001
368 /* Tx & Rx descriptors command */
369 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
371 /* Tx descriptors status */
372 #define ETH_LC_ERROR 0
373 #define ETH_UR_ERROR 0x00000002
374 #define ETH_RL_ERROR 0x00000004
375 #define ETH_LLC_SNAP_FORMAT 0x00000200
377 /* Rx descriptors status */
378 #define ETH_OVERRUN_ERROR 0x00000002
379 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
380 #define ETH_RESOURCE_ERROR 0x00000006
381 #define ETH_VLAN_TAGGED 0x00080000
382 #define ETH_BPDU_FRAME 0x00100000
383 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
384 #define ETH_OTHER_FRAME_TYPE 0x00400000
385 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
386 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
387 #define ETH_FRAME_HEADER_OK 0x02000000
388 #define ETH_RX_LAST_DESC 0x04000000
389 #define ETH_RX_FIRST_DESC 0x08000000
390 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
391 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
392 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
394 /* Rx descriptors byte count */
395 #define ETH_FRAME_FRAGMENTED 0x00000004
397 /* Tx descriptors command */
398 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
399 #define ETH_FRAME_SET_TO_VLAN 0x00008000
400 #define ETH_UDP_FRAME 0x00010000
401 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
402 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
403 #define ETH_ZERO_PADDING 0x00080000
404 #define ETH_TX_LAST_DESC 0x00100000
405 #define ETH_TX_FIRST_DESC 0x00200000
406 #define ETH_GEN_CRC 0x00400000
407 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
408 #define ETH_AUTO_MODE 0x40000000
410 #define ETH_TX_IHL_SHIFT 11
414 typedef enum _eth_func_ret_status
{
415 ETH_OK
, /* Returned as expected. */
416 ETH_ERROR
, /* Fundamental error. */
417 ETH_RETRY
, /* Could not process request. Try later.*/
418 ETH_END_OF_JOB
, /* Ring has nothing to process. */
419 ETH_QUEUE_FULL
, /* Ring resource error. */
420 ETH_QUEUE_LAST_RESOURCE
/* Ring resources about to exhaust. */
421 } ETH_FUNC_RET_STATUS
;
423 /* These are for big-endian machines. Little endian needs different
426 #if defined(__BIG_ENDIAN)
428 u16 byte_cnt
; /* Descriptor buffer byte count */
429 u16 buf_size
; /* Buffer size */
430 u32 cmd_sts
; /* Descriptor command status */
431 u32 next_desc_ptr
; /* Next descriptor pointer */
432 u32 buf_ptr
; /* Descriptor buffer pointer */
436 u16 byte_cnt
; /* buffer byte count */
437 u16 l4i_chk
; /* CPU provided TCP checksum */
438 u32 cmd_sts
; /* Command/status field */
439 u32 next_desc_ptr
; /* Pointer to next descriptor */
440 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
442 #elif defined(__LITTLE_ENDIAN)
444 u32 cmd_sts
; /* Descriptor command status */
445 u16 buf_size
; /* Buffer size */
446 u16 byte_cnt
; /* Descriptor buffer byte count */
447 u32 buf_ptr
; /* Descriptor buffer pointer */
448 u32 next_desc_ptr
; /* Next descriptor pointer */
452 u32 cmd_sts
; /* Command/status field */
453 u16 l4i_chk
; /* CPU provided TCP checksum */
454 u16 byte_cnt
; /* buffer byte count */
455 u32 buf_ptr
; /* pointer to buffer for this descriptor*/
456 u32 next_desc_ptr
; /* Pointer to next descriptor */
459 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
462 /* Unified struct for Rx and Tx operations. The user is not required to */
463 /* be familier with neither Tx nor Rx descriptors. */
465 unsigned short byte_cnt
; /* Descriptor buffer byte count */
466 unsigned short l4i_chk
; /* Tx CPU provided TCP Checksum */
467 unsigned int cmd_sts
; /* Descriptor command status */
468 dma_addr_t buf_ptr
; /* Descriptor buffer pointer */
469 struct sk_buff
*return_info
; /* User resource return information */
472 /* Ethernet port specific information */
473 struct mv643xx_mib_counters
{
474 u64 good_octets_received
;
475 u32 bad_octets_received
;
476 u32 internal_mac_transmit_err
;
477 u32 good_frames_received
;
478 u32 bad_frames_received
;
479 u32 broadcast_frames_received
;
480 u32 multicast_frames_received
;
481 u32 frames_64_octets
;
482 u32 frames_65_to_127_octets
;
483 u32 frames_128_to_255_octets
;
484 u32 frames_256_to_511_octets
;
485 u32 frames_512_to_1023_octets
;
486 u32 frames_1024_to_max_octets
;
487 u64 good_octets_sent
;
488 u32 good_frames_sent
;
489 u32 excessive_collision
;
490 u32 multicast_frames_sent
;
491 u32 broadcast_frames_sent
;
492 u32 unrec_mac_control_received
;
494 u32 good_fc_received
;
496 u32 undersize_received
;
497 u32 fragments_received
;
498 u32 oversize_received
;
500 u32 mac_receive_error
;
506 struct mv643xx_private
{
507 int port_num
; /* User Ethernet port number */
509 u32 rx_sram_addr
; /* Base address of rx sram area */
510 u32 rx_sram_size
; /* Size of rx sram area */
511 u32 tx_sram_addr
; /* Base address of tx sram area */
512 u32 tx_sram_size
; /* Size of tx sram area */
514 int rx_resource_err
; /* Rx ring resource error flag */
516 /* Tx/Rx rings managment indexes fields. For driver use */
518 /* Next available and first returning Rx resource */
519 int rx_curr_desc_q
, rx_used_desc_q
;
521 /* Next available and first returning Tx resource */
522 int tx_curr_desc_q
, tx_used_desc_q
;
524 #ifdef MV643XX_TX_FAST_REFILL
525 u32 tx_clean_threshold
;
528 struct eth_rx_desc
*p_rx_desc_area
;
529 dma_addr_t rx_desc_dma
;
530 int rx_desc_area_size
;
531 struct sk_buff
**rx_skb
;
533 struct eth_tx_desc
*p_tx_desc_area
;
534 dma_addr_t tx_desc_dma
;
535 int tx_desc_area_size
;
536 struct sk_buff
**tx_skb
;
538 struct work_struct tx_timeout_task
;
540 struct net_device
*dev
;
541 struct napi_struct napi
;
542 struct net_device_stats stats
;
543 struct mv643xx_mib_counters mib_counters
;
545 /* Size of Tx Ring per queue */
547 /* Number of tx descriptors in use */
549 /* Size of Rx Ring per queue */
551 /* Number of rx descriptors in use */
555 * Used in case RX Ring is empty, which can be caused when
556 * system does not have resources (skb's)
558 struct timer_list timeout
;
562 struct mii_if_info mii
;
565 /* Static function declarations */
566 static void eth_port_init(struct mv643xx_private
*mp
);
567 static void eth_port_reset(unsigned int eth_port_num
);
568 static void eth_port_start(struct net_device
*dev
);
570 static void ethernet_phy_reset(unsigned int eth_port_num
);
572 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
573 unsigned int phy_reg
, unsigned int value
);
575 static void eth_port_read_smi_reg(unsigned int eth_port_num
,
576 unsigned int phy_reg
, unsigned int *value
);
578 static void eth_clear_mib_counters(unsigned int eth_port_num
);
580 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
581 struct pkt_info
*p_pkt_info
);
582 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
583 struct pkt_info
*p_pkt_info
);
585 static void eth_port_uc_addr_get(unsigned int port_num
, unsigned char *p_addr
);
586 static void eth_port_uc_addr_set(unsigned int port_num
, unsigned char *p_addr
);
587 static void eth_port_set_multicast_list(struct net_device
*);
588 static void mv643xx_eth_port_enable_tx(unsigned int port_num
,
589 unsigned int queues
);
590 static void mv643xx_eth_port_enable_rx(unsigned int port_num
,
591 unsigned int queues
);
592 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num
);
593 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num
);
594 static int mv643xx_eth_open(struct net_device
*);
595 static int mv643xx_eth_stop(struct net_device
*);
596 static void eth_port_init_mac_tables(unsigned int eth_port_num
);
598 static int mv643xx_poll(struct napi_struct
*napi
, int budget
);
600 static int ethernet_phy_get(unsigned int eth_port_num
);
601 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
602 static int ethernet_phy_detect(unsigned int eth_port_num
);
603 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
);
604 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
);
605 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
);
606 static const struct ethtool_ops mv643xx_ethtool_ops
;
608 static char mv643xx_driver_name
[] = "mv643xx_eth";
609 static char mv643xx_driver_version
[] = "1.0";
611 static void __iomem
*mv643xx_eth_base
;
613 /* used to protect SMI_REG, which is shared across ports */
614 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock
);
616 static inline u32
mv_read(int offset
)
618 return readl(mv643xx_eth_base
+ offset
);
621 static inline void mv_write(int offset
, u32 data
)
623 writel(data
, mv643xx_eth_base
+ offset
);
627 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
629 * Input : pointer to ethernet interface network device structure
631 * Output : 0 upon success, -EINVAL upon failure
633 static int mv643xx_eth_change_mtu(struct net_device
*dev
, int new_mtu
)
635 if ((new_mtu
> 9500) || (new_mtu
< 64))
639 if (!netif_running(dev
))
643 * Stop and then re-open the interface. This will allocate RX
644 * skbs of the new MTU.
645 * There is a possible danger that the open will not succeed,
646 * due to memory being full, which might fail the open function.
648 mv643xx_eth_stop(dev
);
649 if (mv643xx_eth_open(dev
)) {
650 printk(KERN_ERR
"%s: Fatal error on opening device\n",
658 * mv643xx_eth_rx_refill_descs
660 * Fills / refills RX queue on a certain gigabit ethernet port
662 * Input : pointer to ethernet interface network device structure
665 static void mv643xx_eth_rx_refill_descs(struct net_device
*dev
)
667 struct mv643xx_private
*mp
= netdev_priv(dev
);
668 struct pkt_info pkt_info
;
672 while (mp
->rx_desc_count
< mp
->rx_ring_size
) {
673 skb
= dev_alloc_skb(ETH_RX_SKB_SIZE
+ dma_get_cache_alignment());
677 unaligned
= (u32
)skb
->data
& (dma_get_cache_alignment() - 1);
679 skb_reserve(skb
, dma_get_cache_alignment() - unaligned
);
680 pkt_info
.cmd_sts
= ETH_RX_ENABLE_INTERRUPT
;
681 pkt_info
.byte_cnt
= ETH_RX_SKB_SIZE
;
682 pkt_info
.buf_ptr
= dma_map_single(NULL
, skb
->data
,
683 ETH_RX_SKB_SIZE
, DMA_FROM_DEVICE
);
684 pkt_info
.return_info
= skb
;
685 if (eth_rx_return_buff(mp
, &pkt_info
) != ETH_OK
) {
687 "%s: Error allocating RX Ring\n", dev
->name
);
690 skb_reserve(skb
, ETH_HW_IP_ALIGN
);
693 * If RX ring is empty of SKB, set a timer to try allocating
694 * again at a later time.
696 if (mp
->rx_desc_count
== 0) {
697 printk(KERN_INFO
"%s: Rx ring is empty\n", dev
->name
);
698 mp
->timeout
.expires
= jiffies
+ (HZ
/ 10); /* 100 mSec */
699 add_timer(&mp
->timeout
);
704 * mv643xx_eth_rx_refill_descs_timer_wrapper
706 * Timer routine to wake up RX queue filling task. This function is
707 * used only in case the RX queue is empty, and all alloc_skb has
708 * failed (due to out of memory event).
710 * Input : pointer to ethernet interface network device structure
713 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data
)
715 mv643xx_eth_rx_refill_descs((struct net_device
*)data
);
719 * mv643xx_eth_update_mac_address
721 * Update the MAC address of the port in the address table
723 * Input : pointer to ethernet interface network device structure
726 static void mv643xx_eth_update_mac_address(struct net_device
*dev
)
728 struct mv643xx_private
*mp
= netdev_priv(dev
);
729 unsigned int port_num
= mp
->port_num
;
731 eth_port_init_mac_tables(port_num
);
732 eth_port_uc_addr_set(port_num
, dev
->dev_addr
);
736 * mv643xx_eth_set_rx_mode
738 * Change from promiscuos to regular rx mode
740 * Input : pointer to ethernet interface network device structure
743 static void mv643xx_eth_set_rx_mode(struct net_device
*dev
)
745 struct mv643xx_private
*mp
= netdev_priv(dev
);
748 config_reg
= mv_read(PORT_CONFIG_REG(mp
->port_num
));
749 if (dev
->flags
& IFF_PROMISC
)
750 config_reg
|= (u32
) UNICAST_PROMISCUOUS_MODE
;
752 config_reg
&= ~(u32
) UNICAST_PROMISCUOUS_MODE
;
753 mv_write(PORT_CONFIG_REG(mp
->port_num
), config_reg
);
755 eth_port_set_multicast_list(dev
);
759 * mv643xx_eth_set_mac_address
761 * Change the interface's mac address.
762 * No special hardware thing should be done because interface is always
763 * put in promiscuous mode.
765 * Input : pointer to ethernet interface network device structure and
766 * a pointer to the designated entry to be added to the cache.
767 * Output : zero upon success, negative upon failure
769 static int mv643xx_eth_set_mac_address(struct net_device
*dev
, void *addr
)
773 for (i
= 0; i
< 6; i
++)
774 /* +2 is for the offset of the HW addr type */
775 dev
->dev_addr
[i
] = ((unsigned char *)addr
)[i
+ 2];
776 mv643xx_eth_update_mac_address(dev
);
781 * mv643xx_eth_tx_timeout
783 * Called upon a timeout on transmitting a packet
785 * Input : pointer to ethernet interface network device structure.
788 static void mv643xx_eth_tx_timeout(struct net_device
*dev
)
790 struct mv643xx_private
*mp
= netdev_priv(dev
);
792 printk(KERN_INFO
"%s: TX timeout ", dev
->name
);
794 /* Do the reset outside of interrupt context */
795 schedule_work(&mp
->tx_timeout_task
);
799 * mv643xx_eth_tx_timeout_task
801 * Actual routine to reset the adapter when a timeout on Tx has occurred
803 static void mv643xx_eth_tx_timeout_task(struct work_struct
*ugly
)
805 struct mv643xx_private
*mp
= container_of(ugly
, struct mv643xx_private
,
807 struct net_device
*dev
= mp
->dev
;
809 if (!netif_running(dev
))
812 netif_stop_queue(dev
);
814 eth_port_reset(mp
->port_num
);
817 if (mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
818 netif_wake_queue(dev
);
822 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
824 * If force is non-zero, frees uncompleted descriptors as well
826 static int mv643xx_eth_free_tx_descs(struct net_device
*dev
, int force
)
828 struct mv643xx_private
*mp
= netdev_priv(dev
);
829 struct eth_tx_desc
*desc
;
838 while (mp
->tx_desc_count
> 0) {
839 spin_lock_irqsave(&mp
->lock
, flags
);
841 /* tx_desc_count might have changed before acquiring the lock */
842 if (mp
->tx_desc_count
<= 0) {
843 spin_unlock_irqrestore(&mp
->lock
, flags
);
847 tx_index
= mp
->tx_used_desc_q
;
848 desc
= &mp
->p_tx_desc_area
[tx_index
];
849 cmd_sts
= desc
->cmd_sts
;
851 if (!force
&& (cmd_sts
& ETH_BUFFER_OWNED_BY_DMA
)) {
852 spin_unlock_irqrestore(&mp
->lock
, flags
);
856 mp
->tx_used_desc_q
= (tx_index
+ 1) % mp
->tx_ring_size
;
859 addr
= desc
->buf_ptr
;
860 count
= desc
->byte_cnt
;
861 skb
= mp
->tx_skb
[tx_index
];
863 mp
->tx_skb
[tx_index
] = NULL
;
865 if (cmd_sts
& ETH_ERROR_SUMMARY
) {
866 printk("%s: Error in TX\n", dev
->name
);
867 dev
->stats
.tx_errors
++;
870 spin_unlock_irqrestore(&mp
->lock
, flags
);
872 if (cmd_sts
& ETH_TX_FIRST_DESC
)
873 dma_unmap_single(NULL
, addr
, count
, DMA_TO_DEVICE
);
875 dma_unmap_page(NULL
, addr
, count
, DMA_TO_DEVICE
);
878 dev_kfree_skb_irq(skb
);
886 static void mv643xx_eth_free_completed_tx_descs(struct net_device
*dev
)
888 struct mv643xx_private
*mp
= netdev_priv(dev
);
890 if (mv643xx_eth_free_tx_descs(dev
, 0) &&
891 mp
->tx_ring_size
- mp
->tx_desc_count
>= MAX_DESCS_PER_SKB
)
892 netif_wake_queue(dev
);
895 static void mv643xx_eth_free_all_tx_descs(struct net_device
*dev
)
897 mv643xx_eth_free_tx_descs(dev
, 1);
901 * mv643xx_eth_receive
903 * This function is forward packets that are received from the port's
904 * queues toward kernel core or FastRoute them to another interface.
906 * Input : dev - a pointer to the required interface
907 * max - maximum number to receive (0 means unlimted)
909 * Output : number of served packets
911 static int mv643xx_eth_receive_queue(struct net_device
*dev
, int budget
)
913 struct mv643xx_private
*mp
= netdev_priv(dev
);
914 struct net_device_stats
*stats
= &dev
->stats
;
915 unsigned int received_packets
= 0;
917 struct pkt_info pkt_info
;
919 while (budget
-- > 0 && eth_port_receive(mp
, &pkt_info
) == ETH_OK
) {
920 dma_unmap_single(NULL
, pkt_info
.buf_ptr
, ETH_RX_SKB_SIZE
,
927 * Note byte count includes 4 byte CRC count
930 stats
->rx_bytes
+= pkt_info
.byte_cnt
;
931 skb
= pkt_info
.return_info
;
933 * In case received a packet without first / last bits on OR
934 * the error summary bit is on, the packets needs to be dropeed.
936 if (((pkt_info
.cmd_sts
937 & (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) !=
938 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
))
939 || (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)) {
941 if ((pkt_info
.cmd_sts
& (ETH_RX_FIRST_DESC
|
942 ETH_RX_LAST_DESC
)) !=
943 (ETH_RX_FIRST_DESC
| ETH_RX_LAST_DESC
)) {
946 "%s: Received packet spread "
947 "on multiple descriptors\n",
950 if (pkt_info
.cmd_sts
& ETH_ERROR_SUMMARY
)
953 dev_kfree_skb_irq(skb
);
956 * The -4 is for the CRC in the trailer of the
959 skb_put(skb
, pkt_info
.byte_cnt
- 4);
961 if (pkt_info
.cmd_sts
& ETH_LAYER_4_CHECKSUM_OK
) {
962 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
964 (pkt_info
.cmd_sts
& 0x0007fff8) >> 3);
966 skb
->protocol
= eth_type_trans(skb
, dev
);
968 netif_receive_skb(skb
);
973 dev
->last_rx
= jiffies
;
975 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
977 return received_packets
;
980 /* Set the mv643xx port configuration register for the speed/duplex mode. */
981 static void mv643xx_eth_update_pscr(struct net_device
*dev
,
982 struct ethtool_cmd
*ecmd
)
984 struct mv643xx_private
*mp
= netdev_priv(dev
);
985 int port_num
= mp
->port_num
;
989 o_pscr
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
992 /* clear speed, duplex and rx buffer size fields */
993 n_pscr
&= ~(SET_MII_SPEED_TO_100
|
994 SET_GMII_SPEED_TO_1000
|
995 SET_FULL_DUPLEX_MODE
|
998 if (ecmd
->duplex
== DUPLEX_FULL
)
999 n_pscr
|= SET_FULL_DUPLEX_MODE
;
1001 if (ecmd
->speed
== SPEED_1000
)
1002 n_pscr
|= SET_GMII_SPEED_TO_1000
|
1003 MAX_RX_PACKET_9700BYTE
;
1005 if (ecmd
->speed
== SPEED_100
)
1006 n_pscr
|= SET_MII_SPEED_TO_100
;
1007 n_pscr
|= MAX_RX_PACKET_1522BYTE
;
1010 if (n_pscr
!= o_pscr
) {
1011 if ((o_pscr
& SERIAL_PORT_ENABLE
) == 0)
1012 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1014 queues
= mv643xx_eth_port_disable_tx(port_num
);
1016 o_pscr
&= ~SERIAL_PORT_ENABLE
;
1017 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), o_pscr
);
1018 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1019 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), n_pscr
);
1021 mv643xx_eth_port_enable_tx(port_num
, queues
);
1027 * mv643xx_eth_int_handler
1029 * Main interrupt handler for the gigbit ethernet ports
1031 * Input : irq - irq number (not used)
1032 * dev_id - a pointer to the required interface's data structure
1037 static irqreturn_t
mv643xx_eth_int_handler(int irq
, void *dev_id
)
1039 struct net_device
*dev
= (struct net_device
*)dev_id
;
1040 struct mv643xx_private
*mp
= netdev_priv(dev
);
1041 u32 eth_int_cause
, eth_int_cause_ext
= 0;
1042 unsigned int port_num
= mp
->port_num
;
1044 /* Read interrupt cause registers */
1045 eth_int_cause
= mv_read(INTERRUPT_CAUSE_REG(port_num
)) &
1047 if (eth_int_cause
& ETH_INT_CAUSE_EXT
) {
1048 eth_int_cause_ext
= mv_read(
1049 INTERRUPT_CAUSE_EXTEND_REG(port_num
)) &
1050 ETH_INT_UNMASK_ALL_EXT
;
1051 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
),
1052 ~eth_int_cause_ext
);
1055 /* PHY status changed */
1056 if (eth_int_cause_ext
& (ETH_INT_CAUSE_PHY
| ETH_INT_CAUSE_STATE
)) {
1057 struct ethtool_cmd cmd
;
1059 if (mii_link_ok(&mp
->mii
)) {
1060 mii_ethtool_gset(&mp
->mii
, &cmd
);
1061 mv643xx_eth_update_pscr(dev
, &cmd
);
1062 mv643xx_eth_port_enable_tx(port_num
,
1063 ETH_TX_QUEUES_ENABLED
);
1064 if (!netif_carrier_ok(dev
)) {
1065 netif_carrier_on(dev
);
1066 if (mp
->tx_ring_size
- mp
->tx_desc_count
>=
1068 netif_wake_queue(dev
);
1070 } else if (netif_carrier_ok(dev
)) {
1071 netif_stop_queue(dev
);
1072 netif_carrier_off(dev
);
1077 if (eth_int_cause
& ETH_INT_CAUSE_RX
) {
1078 /* schedule the NAPI poll routine to maintain port */
1079 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1081 /* wait for previous write to complete */
1082 mv_read(INTERRUPT_MASK_REG(port_num
));
1084 netif_rx_schedule(dev
, &mp
->napi
);
1087 if (eth_int_cause
& ETH_INT_CAUSE_RX
)
1088 mv643xx_eth_receive_queue(dev
, INT_MAX
);
1090 if (eth_int_cause_ext
& ETH_INT_CAUSE_TX
)
1091 mv643xx_eth_free_completed_tx_descs(dev
);
1094 * If no real interrupt occured, exit.
1095 * This can happen when using gigE interrupt coalescing mechanism.
1097 if ((eth_int_cause
== 0x0) && (eth_int_cause_ext
== 0x0))
1106 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1109 * This routine sets the RX coalescing interrupt mechanism parameter.
1110 * This parameter is a timeout counter, that counts in 64 t_clk
1111 * chunks ; that when timeout event occurs a maskable interrupt
1113 * The parameter is calculated using the tClk of the MV-643xx chip
1114 * , and the required delay of the interrupt in usec.
1117 * unsigned int eth_port_num Ethernet port number
1118 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1119 * unsigned int delay Delay in usec
1122 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1125 * The interrupt coalescing value set in the gigE port.
1128 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num
,
1129 unsigned int t_clk
, unsigned int delay
)
1131 unsigned int coal
= ((t_clk
/ 1000000) * delay
) / 64;
1133 /* Set RX Coalescing mechanism */
1134 mv_write(SDMA_CONFIG_REG(eth_port_num
),
1135 ((coal
& 0x3fff) << 8) |
1136 (mv_read(SDMA_CONFIG_REG(eth_port_num
))
1144 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
1147 * This routine sets the TX coalescing interrupt mechanism parameter.
1148 * This parameter is a timeout counter, that counts in 64 t_clk
1149 * chunks ; that when timeout event occurs a maskable interrupt
1151 * The parameter is calculated using the t_cLK frequency of the
1152 * MV-643xx chip and the required delay in the interrupt in uSec
1155 * unsigned int eth_port_num Ethernet port number
1156 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1157 * unsigned int delay Delay in uSeconds
1160 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1163 * The interrupt coalescing value set in the gigE port.
1166 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num
,
1167 unsigned int t_clk
, unsigned int delay
)
1170 coal
= ((t_clk
/ 1000000) * delay
) / 64;
1171 /* Set TX Coalescing mechanism */
1172 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num
), coal
<< 4);
1177 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1180 * This function prepares a Rx chained list of descriptors and packet
1181 * buffers in a form of a ring. The routine must be called after port
1182 * initialization routine and before port start routine.
1183 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1184 * devices in the system (i.e. DRAM). This function uses the ethernet
1185 * struct 'virtual to physical' routine (set by the user) to set the ring
1186 * with physical addresses.
1189 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1192 * The routine updates the Ethernet port control struct with information
1193 * regarding the Rx descriptors and buffers.
1198 static void ether_init_rx_desc_ring(struct mv643xx_private
*mp
)
1200 volatile struct eth_rx_desc
*p_rx_desc
;
1201 int rx_desc_num
= mp
->rx_ring_size
;
1204 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1205 p_rx_desc
= (struct eth_rx_desc
*)mp
->p_rx_desc_area
;
1206 for (i
= 0; i
< rx_desc_num
; i
++) {
1207 p_rx_desc
[i
].next_desc_ptr
= mp
->rx_desc_dma
+
1208 ((i
+ 1) % rx_desc_num
) * sizeof(struct eth_rx_desc
);
1211 /* Save Rx desc pointer to driver struct. */
1212 mp
->rx_curr_desc_q
= 0;
1213 mp
->rx_used_desc_q
= 0;
1215 mp
->rx_desc_area_size
= rx_desc_num
* sizeof(struct eth_rx_desc
);
1219 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1222 * This function prepares a Tx chained list of descriptors and packet
1223 * buffers in a form of a ring. The routine must be called after port
1224 * initialization routine and before port start routine.
1225 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1226 * devices in the system (i.e. DRAM). This function uses the ethernet
1227 * struct 'virtual to physical' routine (set by the user) to set the ring
1228 * with physical addresses.
1231 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1234 * The routine updates the Ethernet port control struct with information
1235 * regarding the Tx descriptors and buffers.
1240 static void ether_init_tx_desc_ring(struct mv643xx_private
*mp
)
1242 int tx_desc_num
= mp
->tx_ring_size
;
1243 struct eth_tx_desc
*p_tx_desc
;
1246 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1247 p_tx_desc
= (struct eth_tx_desc
*)mp
->p_tx_desc_area
;
1248 for (i
= 0; i
< tx_desc_num
; i
++) {
1249 p_tx_desc
[i
].next_desc_ptr
= mp
->tx_desc_dma
+
1250 ((i
+ 1) % tx_desc_num
) * sizeof(struct eth_tx_desc
);
1253 mp
->tx_curr_desc_q
= 0;
1254 mp
->tx_used_desc_q
= 0;
1256 mp
->tx_desc_area_size
= tx_desc_num
* sizeof(struct eth_tx_desc
);
1259 static int mv643xx_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1261 struct mv643xx_private
*mp
= netdev_priv(dev
);
1264 spin_lock_irq(&mp
->lock
);
1265 err
= mii_ethtool_sset(&mp
->mii
, cmd
);
1266 spin_unlock_irq(&mp
->lock
);
1271 static int mv643xx_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1273 struct mv643xx_private
*mp
= netdev_priv(dev
);
1276 spin_lock_irq(&mp
->lock
);
1277 err
= mii_ethtool_gset(&mp
->mii
, cmd
);
1278 spin_unlock_irq(&mp
->lock
);
1280 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1281 cmd
->supported
&= ~SUPPORTED_1000baseT_Half
;
1282 cmd
->advertising
&= ~ADVERTISED_1000baseT_Half
;
1290 * This function is called when openning the network device. The function
1291 * should initialize all the hardware, initialize cyclic Rx/Tx
1292 * descriptors chain and buffers and allocate an IRQ to the network
1295 * Input : a pointer to the network device structure
1297 * Output : zero of success , nonzero if fails.
1300 static int mv643xx_eth_open(struct net_device
*dev
)
1302 struct mv643xx_private
*mp
= netdev_priv(dev
);
1303 unsigned int port_num
= mp
->port_num
;
1307 /* Clear any pending ethernet port interrupts */
1308 mv_write(INTERRUPT_CAUSE_REG(port_num
), 0);
1309 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1310 /* wait for previous write to complete */
1311 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num
));
1313 err
= request_irq(dev
->irq
, mv643xx_eth_int_handler
,
1314 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
, dev
->name
, dev
);
1316 printk(KERN_ERR
"Can not assign IRQ number to MV643XX_eth%d\n",
1323 memset(&mp
->timeout
, 0, sizeof(struct timer_list
));
1324 mp
->timeout
.function
= mv643xx_eth_rx_refill_descs_timer_wrapper
;
1325 mp
->timeout
.data
= (unsigned long)dev
;
1327 /* Allocate RX and TX skb rings */
1328 mp
->rx_skb
= kmalloc(sizeof(*mp
->rx_skb
) * mp
->rx_ring_size
,
1331 printk(KERN_ERR
"%s: Cannot allocate Rx skb ring\n", dev
->name
);
1335 mp
->tx_skb
= kmalloc(sizeof(*mp
->tx_skb
) * mp
->tx_ring_size
,
1338 printk(KERN_ERR
"%s: Cannot allocate Tx skb ring\n", dev
->name
);
1340 goto out_free_rx_skb
;
1343 /* Allocate TX ring */
1344 mp
->tx_desc_count
= 0;
1345 size
= mp
->tx_ring_size
* sizeof(struct eth_tx_desc
);
1346 mp
->tx_desc_area_size
= size
;
1348 if (mp
->tx_sram_size
) {
1349 mp
->p_tx_desc_area
= ioremap(mp
->tx_sram_addr
,
1351 mp
->tx_desc_dma
= mp
->tx_sram_addr
;
1353 mp
->p_tx_desc_area
= dma_alloc_coherent(NULL
, size
,
1357 if (!mp
->p_tx_desc_area
) {
1358 printk(KERN_ERR
"%s: Cannot allocate Tx Ring (size %d bytes)\n",
1361 goto out_free_tx_skb
;
1363 BUG_ON((u32
) mp
->p_tx_desc_area
& 0xf); /* check 16-byte alignment */
1364 memset((void *)mp
->p_tx_desc_area
, 0, mp
->tx_desc_area_size
);
1366 ether_init_tx_desc_ring(mp
);
1368 /* Allocate RX ring */
1369 mp
->rx_desc_count
= 0;
1370 size
= mp
->rx_ring_size
* sizeof(struct eth_rx_desc
);
1371 mp
->rx_desc_area_size
= size
;
1373 if (mp
->rx_sram_size
) {
1374 mp
->p_rx_desc_area
= ioremap(mp
->rx_sram_addr
,
1376 mp
->rx_desc_dma
= mp
->rx_sram_addr
;
1378 mp
->p_rx_desc_area
= dma_alloc_coherent(NULL
, size
,
1382 if (!mp
->p_rx_desc_area
) {
1383 printk(KERN_ERR
"%s: Cannot allocate Rx ring (size %d bytes)\n",
1385 printk(KERN_ERR
"%s: Freeing previously allocated TX queues...",
1387 if (mp
->rx_sram_size
)
1388 iounmap(mp
->p_tx_desc_area
);
1390 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
1391 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
1393 goto out_free_tx_skb
;
1395 memset((void *)mp
->p_rx_desc_area
, 0, size
);
1397 ether_init_rx_desc_ring(mp
);
1399 mv643xx_eth_rx_refill_descs(dev
); /* Fill RX ring with skb's */
1402 napi_enable(&mp
->napi
);
1405 eth_port_start(dev
);
1407 /* Interrupt Coalescing */
1411 eth_port_set_rx_coal(port_num
, 133000000, MV643XX_RX_COAL
);
1415 eth_port_set_tx_coal(port_num
, 133000000, MV643XX_TX_COAL
);
1417 /* Unmask phy and link status changes interrupts */
1418 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num
), ETH_INT_UNMASK_ALL_EXT
);
1420 /* Unmask RX buffer and TX end interrupt */
1421 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1430 free_irq(dev
->irq
, dev
);
1435 static void mv643xx_eth_free_tx_rings(struct net_device
*dev
)
1437 struct mv643xx_private
*mp
= netdev_priv(dev
);
1439 /* Stop Tx Queues */
1440 mv643xx_eth_port_disable_tx(mp
->port_num
);
1442 /* Free outstanding skb's on TX ring */
1443 mv643xx_eth_free_all_tx_descs(dev
);
1445 BUG_ON(mp
->tx_used_desc_q
!= mp
->tx_curr_desc_q
);
1448 if (mp
->tx_sram_size
)
1449 iounmap(mp
->p_tx_desc_area
);
1451 dma_free_coherent(NULL
, mp
->tx_desc_area_size
,
1452 mp
->p_tx_desc_area
, mp
->tx_desc_dma
);
1455 static void mv643xx_eth_free_rx_rings(struct net_device
*dev
)
1457 struct mv643xx_private
*mp
= netdev_priv(dev
);
1458 unsigned int port_num
= mp
->port_num
;
1461 /* Stop RX Queues */
1462 mv643xx_eth_port_disable_rx(port_num
);
1464 /* Free preallocated skb's on RX rings */
1465 for (curr
= 0; mp
->rx_desc_count
&& curr
< mp
->rx_ring_size
; curr
++) {
1466 if (mp
->rx_skb
[curr
]) {
1467 dev_kfree_skb(mp
->rx_skb
[curr
]);
1468 mp
->rx_desc_count
--;
1472 if (mp
->rx_desc_count
)
1474 "%s: Error in freeing Rx Ring. %d skb's still"
1475 " stuck in RX Ring - ignoring them\n", dev
->name
,
1478 if (mp
->rx_sram_size
)
1479 iounmap(mp
->p_rx_desc_area
);
1481 dma_free_coherent(NULL
, mp
->rx_desc_area_size
,
1482 mp
->p_rx_desc_area
, mp
->rx_desc_dma
);
1488 * This function is used when closing the network device.
1489 * It updates the hardware,
1490 * release all memory that holds buffers and descriptors and release the IRQ.
1491 * Input : a pointer to the device structure
1492 * Output : zero if success , nonzero if fails
1495 static int mv643xx_eth_stop(struct net_device
*dev
)
1497 struct mv643xx_private
*mp
= netdev_priv(dev
);
1498 unsigned int port_num
= mp
->port_num
;
1500 /* Mask all interrupts on ethernet port */
1501 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1502 /* wait for previous write to complete */
1503 mv_read(INTERRUPT_MASK_REG(port_num
));
1506 napi_disable(&mp
->napi
);
1508 netif_carrier_off(dev
);
1509 netif_stop_queue(dev
);
1511 eth_port_reset(mp
->port_num
);
1513 mv643xx_eth_free_tx_rings(dev
);
1514 mv643xx_eth_free_rx_rings(dev
);
1516 free_irq(dev
->irq
, dev
);
1525 * This function is used in case of NAPI
1527 static int mv643xx_poll(struct napi_struct
*napi
, int budget
)
1529 struct mv643xx_private
*mp
= container_of(napi
, struct mv643xx_private
, napi
);
1530 struct net_device
*dev
= mp
->dev
;
1531 unsigned int port_num
= mp
->port_num
;
1534 #ifdef MV643XX_TX_FAST_REFILL
1535 if (++mp
->tx_clean_threshold
> 5) {
1536 mv643xx_eth_free_completed_tx_descs(dev
);
1537 mp
->tx_clean_threshold
= 0;
1542 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num
)))
1543 != (u32
) mp
->rx_used_desc_q
)
1544 work_done
= mv643xx_eth_receive_queue(dev
, budget
);
1546 if (work_done
< budget
) {
1547 netif_rx_complete(dev
, napi
);
1548 mv_write(INTERRUPT_CAUSE_REG(port_num
), 0);
1549 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num
), 0);
1550 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1558 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1560 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1561 * This helper function detects that case.
1564 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff
*skb
)
1569 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1570 fragp
= &skb_shinfo(skb
)->frags
[frag
];
1571 if (fragp
->size
<= 8 && fragp
->page_offset
& 0x7)
1578 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1580 static int eth_alloc_tx_desc_index(struct mv643xx_private
*mp
)
1584 BUG_ON(mp
->tx_desc_count
>= mp
->tx_ring_size
);
1586 tx_desc_curr
= mp
->tx_curr_desc_q
;
1587 mp
->tx_curr_desc_q
= (tx_desc_curr
+ 1) % mp
->tx_ring_size
;
1589 BUG_ON(mp
->tx_curr_desc_q
== mp
->tx_used_desc_q
);
1591 return tx_desc_curr
;
1595 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1597 * Ensure the data for each fragment to be transmitted is mapped properly,
1598 * then fill in descriptors in the tx hw queue.
1600 static void eth_tx_fill_frag_descs(struct mv643xx_private
*mp
,
1601 struct sk_buff
*skb
)
1605 struct eth_tx_desc
*desc
;
1607 for (frag
= 0; frag
< skb_shinfo(skb
)->nr_frags
; frag
++) {
1608 skb_frag_t
*this_frag
= &skb_shinfo(skb
)->frags
[frag
];
1610 tx_index
= eth_alloc_tx_desc_index(mp
);
1611 desc
= &mp
->p_tx_desc_area
[tx_index
];
1613 desc
->cmd_sts
= ETH_BUFFER_OWNED_BY_DMA
;
1614 /* Last Frag enables interrupt and frees the skb */
1615 if (frag
== (skb_shinfo(skb
)->nr_frags
- 1)) {
1616 desc
->cmd_sts
|= ETH_ZERO_PADDING
|
1618 ETH_TX_ENABLE_INTERRUPT
;
1619 mp
->tx_skb
[tx_index
] = skb
;
1621 mp
->tx_skb
[tx_index
] = NULL
;
1623 desc
= &mp
->p_tx_desc_area
[tx_index
];
1625 desc
->byte_cnt
= this_frag
->size
;
1626 desc
->buf_ptr
= dma_map_page(NULL
, this_frag
->page
,
1627 this_frag
->page_offset
,
1633 static inline __be16
sum16_as_be(__sum16 sum
)
1635 return (__force __be16
)sum
;
1639 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1641 * Ensure the data for an skb to be transmitted is mapped properly,
1642 * then fill in descriptors in the tx hw queue and start the hardware.
1644 static void eth_tx_submit_descs_for_skb(struct mv643xx_private
*mp
,
1645 struct sk_buff
*skb
)
1648 struct eth_tx_desc
*desc
;
1651 int nr_frags
= skb_shinfo(skb
)->nr_frags
;
1653 cmd_sts
= ETH_TX_FIRST_DESC
| ETH_GEN_CRC
| ETH_BUFFER_OWNED_BY_DMA
;
1655 tx_index
= eth_alloc_tx_desc_index(mp
);
1656 desc
= &mp
->p_tx_desc_area
[tx_index
];
1659 eth_tx_fill_frag_descs(mp
, skb
);
1661 length
= skb_headlen(skb
);
1662 mp
->tx_skb
[tx_index
] = NULL
;
1664 cmd_sts
|= ETH_ZERO_PADDING
|
1666 ETH_TX_ENABLE_INTERRUPT
;
1668 mp
->tx_skb
[tx_index
] = skb
;
1671 desc
->byte_cnt
= length
;
1672 desc
->buf_ptr
= dma_map_single(NULL
, skb
->data
, length
, DMA_TO_DEVICE
);
1674 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1675 BUG_ON(skb
->protocol
!= htons(ETH_P_IP
));
1677 cmd_sts
|= ETH_GEN_TCP_UDP_CHECKSUM
|
1678 ETH_GEN_IP_V_4_CHECKSUM
|
1679 ip_hdr(skb
)->ihl
<< ETH_TX_IHL_SHIFT
;
1681 switch (ip_hdr(skb
)->protocol
) {
1683 cmd_sts
|= ETH_UDP_FRAME
;
1684 desc
->l4i_chk
= ntohs(sum16_as_be(udp_hdr(skb
)->check
));
1687 desc
->l4i_chk
= ntohs(sum16_as_be(tcp_hdr(skb
)->check
));
1693 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1694 cmd_sts
|= 5 << ETH_TX_IHL_SHIFT
;
1698 /* ensure all other descriptors are written before first cmd_sts */
1700 desc
->cmd_sts
= cmd_sts
;
1702 /* ensure all descriptors are written before poking hardware */
1704 mv643xx_eth_port_enable_tx(mp
->port_num
, ETH_TX_QUEUES_ENABLED
);
1706 mp
->tx_desc_count
+= nr_frags
+ 1;
1710 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1713 static int mv643xx_eth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1715 struct mv643xx_private
*mp
= netdev_priv(dev
);
1716 struct net_device_stats
*stats
= &dev
->stats
;
1717 unsigned long flags
;
1719 BUG_ON(netif_queue_stopped(dev
));
1721 if (has_tiny_unaligned_frags(skb
) && __skb_linearize(skb
)) {
1722 stats
->tx_dropped
++;
1723 printk(KERN_DEBUG
"%s: failed to linearize tiny "
1724 "unaligned fragment\n", dev
->name
);
1725 return NETDEV_TX_BUSY
;
1728 spin_lock_irqsave(&mp
->lock
, flags
);
1730 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
) {
1731 printk(KERN_ERR
"%s: transmit with queue full\n", dev
->name
);
1732 netif_stop_queue(dev
);
1733 spin_unlock_irqrestore(&mp
->lock
, flags
);
1734 return NETDEV_TX_BUSY
;
1737 eth_tx_submit_descs_for_skb(mp
, skb
);
1738 stats
->tx_bytes
+= skb
->len
;
1739 stats
->tx_packets
++;
1740 dev
->trans_start
= jiffies
;
1742 if (mp
->tx_ring_size
- mp
->tx_desc_count
< MAX_DESCS_PER_SKB
)
1743 netif_stop_queue(dev
);
1745 spin_unlock_irqrestore(&mp
->lock
, flags
);
1747 return NETDEV_TX_OK
;
1750 #ifdef CONFIG_NET_POLL_CONTROLLER
1751 static void mv643xx_netpoll(struct net_device
*netdev
)
1753 struct mv643xx_private
*mp
= netdev_priv(netdev
);
1754 int port_num
= mp
->port_num
;
1756 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_MASK_ALL
);
1757 /* wait for previous write to complete */
1758 mv_read(INTERRUPT_MASK_REG(port_num
));
1760 mv643xx_eth_int_handler(netdev
->irq
, netdev
);
1762 mv_write(INTERRUPT_MASK_REG(port_num
), ETH_INT_UNMASK_ALL
);
1766 static void mv643xx_init_ethtool_cmd(struct net_device
*dev
, int phy_address
,
1767 int speed
, int duplex
,
1768 struct ethtool_cmd
*cmd
)
1770 struct mv643xx_private
*mp
= netdev_priv(dev
);
1772 memset(cmd
, 0, sizeof(*cmd
));
1774 cmd
->port
= PORT_MII
;
1775 cmd
->transceiver
= XCVR_INTERNAL
;
1776 cmd
->phy_address
= phy_address
;
1779 cmd
->autoneg
= AUTONEG_ENABLE
;
1780 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1781 cmd
->speed
= SPEED_100
;
1782 cmd
->advertising
= ADVERTISED_10baseT_Half
|
1783 ADVERTISED_10baseT_Full
|
1784 ADVERTISED_100baseT_Half
|
1785 ADVERTISED_100baseT_Full
;
1786 if (mp
->mii
.supports_gmii
)
1787 cmd
->advertising
|= ADVERTISED_1000baseT_Full
;
1789 cmd
->autoneg
= AUTONEG_DISABLE
;
1791 cmd
->duplex
= duplex
;
1798 * First function called after registering the network device.
1799 * It's purpose is to initialize the device as an ethernet device,
1800 * fill the ethernet device structure with pointers * to functions,
1801 * and set the MAC address of the interface
1803 * Input : struct device *
1804 * Output : -ENOMEM if failed , 0 if success
1806 static int mv643xx_eth_probe(struct platform_device
*pdev
)
1808 struct mv643xx_eth_platform_data
*pd
;
1810 struct mv643xx_private
*mp
;
1811 struct net_device
*dev
;
1813 struct resource
*res
;
1815 struct ethtool_cmd cmd
;
1816 int duplex
= DUPLEX_HALF
;
1817 int speed
= 0; /* default to auto-negotiation */
1818 DECLARE_MAC_BUF(mac
);
1820 pd
= pdev
->dev
.platform_data
;
1822 printk(KERN_ERR
"No mv643xx_eth_platform_data\n");
1826 dev
= alloc_etherdev(sizeof(struct mv643xx_private
));
1830 platform_set_drvdata(pdev
, dev
);
1832 mp
= netdev_priv(dev
);
1835 netif_napi_add(dev
, &mp
->napi
, mv643xx_poll
, 64);
1838 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
1840 dev
->irq
= res
->start
;
1842 dev
->open
= mv643xx_eth_open
;
1843 dev
->stop
= mv643xx_eth_stop
;
1844 dev
->hard_start_xmit
= mv643xx_eth_start_xmit
;
1845 dev
->set_mac_address
= mv643xx_eth_set_mac_address
;
1846 dev
->set_multicast_list
= mv643xx_eth_set_rx_mode
;
1848 /* No need to Tx Timeout */
1849 dev
->tx_timeout
= mv643xx_eth_tx_timeout
;
1851 #ifdef CONFIG_NET_POLL_CONTROLLER
1852 dev
->poll_controller
= mv643xx_netpoll
;
1855 dev
->watchdog_timeo
= 2 * HZ
;
1857 dev
->change_mtu
= mv643xx_eth_change_mtu
;
1858 dev
->do_ioctl
= mv643xx_eth_do_ioctl
;
1859 SET_ETHTOOL_OPS(dev
, &mv643xx_ethtool_ops
);
1861 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1862 #ifdef MAX_SKB_FRAGS
1864 * Zero copy can only work if we use Discovery II memory. Else, we will
1865 * have to map the buffers to ISA memory which is only 16 MB
1867 dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
;
1871 /* Configure the timeout task */
1872 INIT_WORK(&mp
->tx_timeout_task
, mv643xx_eth_tx_timeout_task
);
1874 spin_lock_init(&mp
->lock
);
1876 port_num
= mp
->port_num
= pd
->port_number
;
1878 /* set default config values */
1879 eth_port_uc_addr_get(port_num
, dev
->dev_addr
);
1880 mp
->rx_ring_size
= PORT_DEFAULT_RECEIVE_QUEUE_SIZE
;
1881 mp
->tx_ring_size
= PORT_DEFAULT_TRANSMIT_QUEUE_SIZE
;
1883 if (is_valid_ether_addr(pd
->mac_addr
))
1884 memcpy(dev
->dev_addr
, pd
->mac_addr
, 6);
1886 if (pd
->phy_addr
|| pd
->force_phy_addr
)
1887 ethernet_phy_set(port_num
, pd
->phy_addr
);
1889 if (pd
->rx_queue_size
)
1890 mp
->rx_ring_size
= pd
->rx_queue_size
;
1892 if (pd
->tx_queue_size
)
1893 mp
->tx_ring_size
= pd
->tx_queue_size
;
1895 if (pd
->tx_sram_size
) {
1896 mp
->tx_sram_size
= pd
->tx_sram_size
;
1897 mp
->tx_sram_addr
= pd
->tx_sram_addr
;
1900 if (pd
->rx_sram_size
) {
1901 mp
->rx_sram_size
= pd
->rx_sram_size
;
1902 mp
->rx_sram_addr
= pd
->rx_sram_addr
;
1905 duplex
= pd
->duplex
;
1908 /* Hook up MII support for ethtool */
1910 mp
->mii
.mdio_read
= mv643xx_mdio_read
;
1911 mp
->mii
.mdio_write
= mv643xx_mdio_write
;
1912 mp
->mii
.phy_id
= ethernet_phy_get(port_num
);
1913 mp
->mii
.phy_id_mask
= 0x3f;
1914 mp
->mii
.reg_num_mask
= 0x1f;
1916 err
= ethernet_phy_detect(port_num
);
1918 pr_debug("MV643xx ethernet port %d: "
1919 "No PHY detected at addr %d\n",
1920 port_num
, ethernet_phy_get(port_num
));
1924 ethernet_phy_reset(port_num
);
1925 mp
->mii
.supports_gmii
= mii_check_gmii_support(&mp
->mii
);
1926 mv643xx_init_ethtool_cmd(dev
, mp
->mii
.phy_id
, speed
, duplex
, &cmd
);
1927 mv643xx_eth_update_pscr(dev
, &cmd
);
1928 mv643xx_set_settings(dev
, &cmd
);
1930 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1931 err
= register_netdev(dev
);
1937 "%s: port %d with MAC address %s\n",
1938 dev
->name
, port_num
, print_mac(mac
, p
));
1940 if (dev
->features
& NETIF_F_SG
)
1941 printk(KERN_NOTICE
"%s: Scatter Gather Enabled\n", dev
->name
);
1943 if (dev
->features
& NETIF_F_IP_CSUM
)
1944 printk(KERN_NOTICE
"%s: TX TCP/IP Checksumming Supported\n",
1947 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1948 printk(KERN_NOTICE
"%s: RX TCP/UDP Checksum Offload ON \n", dev
->name
);
1952 printk(KERN_NOTICE
"%s: TX and RX Interrupt Coalescing ON \n",
1957 printk(KERN_NOTICE
"%s: RX NAPI Enabled \n", dev
->name
);
1960 if (mp
->tx_sram_size
> 0)
1961 printk(KERN_NOTICE
"%s: Using SRAM\n", dev
->name
);
1971 static int mv643xx_eth_remove(struct platform_device
*pdev
)
1973 struct net_device
*dev
= platform_get_drvdata(pdev
);
1975 unregister_netdev(dev
);
1976 flush_scheduled_work();
1979 platform_set_drvdata(pdev
, NULL
);
1983 static int mv643xx_eth_shared_probe(struct platform_device
*pdev
)
1985 struct resource
*res
;
1987 printk(KERN_NOTICE
"MV-643xx 10/100/1000 Ethernet Driver\n");
1989 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1993 mv643xx_eth_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
1994 if (mv643xx_eth_base
== NULL
)
2001 static int mv643xx_eth_shared_remove(struct platform_device
*pdev
)
2003 iounmap(mv643xx_eth_base
);
2004 mv643xx_eth_base
= NULL
;
2009 static void mv643xx_eth_shutdown(struct platform_device
*pdev
)
2011 struct net_device
*dev
= platform_get_drvdata(pdev
);
2012 struct mv643xx_private
*mp
= netdev_priv(dev
);
2013 unsigned int port_num
= mp
->port_num
;
2015 /* Mask all interrupts on ethernet port */
2016 mv_write(INTERRUPT_MASK_REG(port_num
), 0);
2017 mv_read (INTERRUPT_MASK_REG(port_num
));
2019 eth_port_reset(port_num
);
2022 static struct platform_driver mv643xx_eth_driver
= {
2023 .probe
= mv643xx_eth_probe
,
2024 .remove
= mv643xx_eth_remove
,
2025 .shutdown
= mv643xx_eth_shutdown
,
2027 .name
= MV643XX_ETH_NAME
,
2031 static struct platform_driver mv643xx_eth_shared_driver
= {
2032 .probe
= mv643xx_eth_shared_probe
,
2033 .remove
= mv643xx_eth_shared_remove
,
2035 .name
= MV643XX_ETH_SHARED_NAME
,
2040 * mv643xx_init_module
2042 * Registers the network drivers into the Linux kernel
2048 static int __init
mv643xx_init_module(void)
2052 rc
= platform_driver_register(&mv643xx_eth_shared_driver
);
2054 rc
= platform_driver_register(&mv643xx_eth_driver
);
2056 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2062 * mv643xx_cleanup_module
2064 * Registers the network drivers into the Linux kernel
2070 static void __exit
mv643xx_cleanup_module(void)
2072 platform_driver_unregister(&mv643xx_eth_driver
);
2073 platform_driver_unregister(&mv643xx_eth_shared_driver
);
2076 module_init(mv643xx_init_module
);
2077 module_exit(mv643xx_cleanup_module
);
2079 MODULE_LICENSE("GPL");
2080 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2081 " and Dale Farnsworth");
2082 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2083 MODULE_ALIAS("platform:mv643xx_eth");
2086 * The second part is the low level driver of the gigE ethernet ports.
2090 * Marvell's Gigabit Ethernet controller low level driver
2093 * This file introduce low level API to Marvell's Gigabit Ethernet
2094 * controller. This Gigabit Ethernet Controller driver API controls
2095 * 1) Operations (i.e. port init, start, reset etc').
2096 * 2) Data flow (i.e. port send, receive etc').
2097 * Each Gigabit Ethernet port is controlled via
2098 * struct mv643xx_private.
2099 * This struct includes user configuration information as well as
2100 * driver internal data needed for its operations.
2102 * Supported Features:
2103 * - This low level driver is OS independent. Allocating memory for
2104 * the descriptor rings and buffers are not within the scope of
2106 * - The user is free from Rx/Tx queue managing.
2107 * - This low level driver introduce functionality API that enable
2108 * the to operate Marvell's Gigabit Ethernet Controller in a
2110 * - Simple Gigabit Ethernet port operation API.
2111 * - Simple Gigabit Ethernet port data flow API.
2112 * - Data flow and operation API support per queue functionality.
2113 * - Support cached descriptors for better performance.
2114 * - Enable access to all four DRAM banks and internal SRAM memory
2116 * - PHY access and control API.
2117 * - Port control register configuration API.
2118 * - Full control over Unicast and Multicast MAC configurations.
2122 * Initialization phase
2123 * This phase complete the initialization of the the
2124 * mv643xx_private struct.
2125 * User information regarding port configuration has to be set
2126 * prior to calling the port initialization routine.
2128 * In this phase any port Tx/Rx activity is halted, MIB counters
2129 * are cleared, PHY address is set according to user parameter and
2130 * access to DRAM and internal SRAM memory spaces.
2132 * Driver ring initialization
2133 * Allocating memory for the descriptor rings and buffers is not
2134 * within the scope of this driver. Thus, the user is required to
2135 * allocate memory for the descriptors ring and buffers. Those
2136 * memory parameters are used by the Rx and Tx ring initialization
2137 * routines in order to curve the descriptor linked list in a form
2139 * Note: Pay special attention to alignment issues when using
2140 * cached descriptors/buffers. In this phase the driver store
2141 * information in the mv643xx_private struct regarding each queue
2145 * This phase prepares the Ethernet port for Rx and Tx activity.
2146 * It uses the information stored in the mv643xx_private struct to
2147 * initialize the various port registers.
2150 * All packet references to/from the driver are done using
2152 * This struct is a unified struct used with Rx and Tx operations.
2153 * This way the user is not required to be familiar with neither
2154 * Tx nor Rx descriptors structures.
2155 * The driver's descriptors rings are management by indexes.
2156 * Those indexes controls the ring resources and used to indicate
2157 * a SW resource error:
2159 * This index points to the current available resource for use. For
2160 * example in Rx process this index will point to the descriptor
2161 * that will be passed to the user upon calling the receive
2162 * routine. In Tx process, this index will point to the descriptor
2163 * that will be assigned with the user packet info and transmitted.
2165 * This index points to the descriptor that need to restore its
2166 * resources. For example in Rx process, using the Rx buffer return
2167 * API will attach the buffer returned in packet info to the
2168 * descriptor pointed by 'used'. In Tx process, using the Tx
2169 * descriptor return will merely return the user packet info with
2170 * the command status of the transmitted buffer pointed by the
2171 * 'used' index. Nevertheless, it is essential to use this routine
2172 * to update the 'used' index.
2174 * This index supports Tx Scatter-Gather. It points to the first
2175 * descriptor of a packet assembled of multiple buffers. For
2176 * example when in middle of Such packet we have a Tx resource
2177 * error the 'curr' index get the value of 'first' to indicate
2178 * that the ring returned to its state before trying to transmit
2181 * Receive operation:
2182 * The eth_port_receive API set the packet information struct,
2183 * passed by the caller, with received information from the
2184 * 'current' SDMA descriptor.
2185 * It is the user responsibility to return this resource back
2186 * to the Rx descriptor ring to enable the reuse of this source.
2187 * Return Rx resource is done using the eth_rx_return_buff API.
2189 * Prior to calling the initialization routine eth_port_init() the user
2190 * must set the following fields under mv643xx_private struct:
2191 * port_num User Ethernet port number.
2192 * port_config User port configuration value.
2193 * port_config_extend User port config extend value.
2194 * port_sdma_config User port SDMA config value.
2195 * port_serial_control User port serial control value.
2197 * This driver data flow is done using the struct pkt_info which
2198 * is a unified struct for Rx and Tx operations:
2200 * byte_cnt Tx/Rx descriptor buffer byte count.
2201 * l4i_chk CPU provided TCP Checksum. For Tx operation
2203 * cmd_sts Tx/Rx descriptor command status.
2204 * buf_ptr Tx/Rx descriptor buffer pointer.
2205 * return_info Tx/Rx user resource return information.
2209 static int ethernet_phy_get(unsigned int eth_port_num
);
2210 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
);
2212 /* Ethernet Port routines */
2213 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
);
2216 * eth_port_init - Initialize the Ethernet port driver
2219 * This function prepares the ethernet port to start its activity:
2220 * 1) Completes the ethernet port driver struct initialization toward port
2222 * 2) Resets the device to a quiescent state in case of warm reboot.
2223 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2224 * 4) Clean MAC tables. The reset status of those tables is unknown.
2225 * 5) Set PHY address.
2226 * Note: Call this routine prior to eth_port_start routine and after
2227 * setting user values in the user fields of Ethernet port control
2231 * struct mv643xx_private *mp Ethernet port control struct
2239 static void eth_port_init(struct mv643xx_private
*mp
)
2241 mp
->rx_resource_err
= 0;
2243 eth_port_reset(mp
->port_num
);
2245 eth_port_init_mac_tables(mp
->port_num
);
2249 * eth_port_start - Start the Ethernet port activity.
2252 * This routine prepares the Ethernet port for Rx and Tx activity:
2253 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2254 * has been initialized a descriptor's ring (using
2255 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2256 * 2. Initialize and enable the Ethernet configuration port by writing to
2257 * the port's configuration and command registers.
2258 * 3. Initialize and enable the SDMA by writing to the SDMA's
2259 * configuration and command registers. After completing these steps,
2260 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2262 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2263 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2264 * and ether_init_rx_desc_ring for Rx queues).
2267 * dev - a pointer to the required interface
2270 * Ethernet port is ready to receive and transmit.
2275 static void eth_port_start(struct net_device
*dev
)
2277 struct mv643xx_private
*mp
= netdev_priv(dev
);
2278 unsigned int port_num
= mp
->port_num
;
2279 int tx_curr_desc
, rx_curr_desc
;
2281 struct ethtool_cmd ethtool_cmd
;
2283 /* Assignment of Tx CTRP of given queue */
2284 tx_curr_desc
= mp
->tx_curr_desc_q
;
2285 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
2286 (u32
)((struct eth_tx_desc
*)mp
->tx_desc_dma
+ tx_curr_desc
));
2288 /* Assignment of Rx CRDP of given queue */
2289 rx_curr_desc
= mp
->rx_curr_desc_q
;
2290 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num
),
2291 (u32
)((struct eth_rx_desc
*)mp
->rx_desc_dma
+ rx_curr_desc
));
2293 /* Add the assigned Ethernet address to the port's address table */
2294 eth_port_uc_addr_set(port_num
, dev
->dev_addr
);
2296 /* Assign port configuration and command. */
2297 mv_write(PORT_CONFIG_REG(port_num
),
2298 PORT_CONFIG_DEFAULT_VALUE
);
2300 mv_write(PORT_CONFIG_EXTEND_REG(port_num
),
2301 PORT_CONFIG_EXTEND_DEFAULT_VALUE
);
2303 pscr
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
2305 pscr
&= ~(SERIAL_PORT_ENABLE
| FORCE_LINK_PASS
);
2306 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2308 pscr
|= DISABLE_AUTO_NEG_FOR_FLOW_CTRL
|
2309 DISABLE_AUTO_NEG_SPEED_GMII
|
2310 DISABLE_AUTO_NEG_FOR_DUPLX
|
2311 DO_NOT_FORCE_LINK_FAIL
|
2312 SERIAL_PORT_CONTROL_RESERVED
;
2314 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2316 pscr
|= SERIAL_PORT_ENABLE
;
2317 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), pscr
);
2319 /* Assign port SDMA configuration */
2320 mv_write(SDMA_CONFIG_REG(port_num
),
2321 PORT_SDMA_CONFIG_DEFAULT_VALUE
);
2323 /* Enable port Rx. */
2324 mv643xx_eth_port_enable_rx(port_num
, ETH_RX_QUEUES_ENABLED
);
2326 /* Disable port bandwidth limits by clearing MTU register */
2327 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num
), 0);
2329 /* save phy settings across reset */
2330 mv643xx_get_settings(dev
, ðtool_cmd
);
2331 ethernet_phy_reset(mp
->port_num
);
2332 mv643xx_set_settings(dev
, ðtool_cmd
);
2336 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2338 static void eth_port_uc_addr_set(unsigned int port_num
, unsigned char *p_addr
)
2344 mac_l
= (p_addr
[4] << 8) | (p_addr
[5]);
2345 mac_h
= (p_addr
[0] << 24) | (p_addr
[1] << 16) | (p_addr
[2] << 8) |
2348 mv_write(MAC_ADDR_LOW(port_num
), mac_l
);
2349 mv_write(MAC_ADDR_HIGH(port_num
), mac_h
);
2351 /* Accept frames with this address */
2352 table
= DA_FILTER_UNICAST_TABLE_BASE(port_num
);
2353 eth_port_set_filter_table_entry(table
, p_addr
[5] & 0x0f);
2357 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2359 static void eth_port_uc_addr_get(unsigned int port_num
, unsigned char *p_addr
)
2364 mac_h
= mv_read(MAC_ADDR_HIGH(port_num
));
2365 mac_l
= mv_read(MAC_ADDR_LOW(port_num
));
2367 p_addr
[0] = (mac_h
>> 24) & 0xff;
2368 p_addr
[1] = (mac_h
>> 16) & 0xff;
2369 p_addr
[2] = (mac_h
>> 8) & 0xff;
2370 p_addr
[3] = mac_h
& 0xff;
2371 p_addr
[4] = (mac_l
>> 8) & 0xff;
2372 p_addr
[5] = mac_l
& 0xff;
2376 * The entries in each table are indexed by a hash of a packet's MAC
2377 * address. One bit in each entry determines whether the packet is
2378 * accepted. There are 4 entries (each 8 bits wide) in each register
2379 * of the table. The bits in each entry are defined as follows:
2380 * 0 Accept=1, Drop=0
2381 * 3-1 Queue (ETH_Q0=0)
2384 static void eth_port_set_filter_table_entry(int table
, unsigned char entry
)
2386 unsigned int table_reg
;
2387 unsigned int tbl_offset
;
2388 unsigned int reg_offset
;
2390 tbl_offset
= (entry
/ 4) * 4; /* Register offset of DA table entry */
2391 reg_offset
= entry
% 4; /* Entry offset within the register */
2393 /* Set "accepts frame bit" at specified table entry */
2394 table_reg
= mv_read(table
+ tbl_offset
);
2395 table_reg
|= 0x01 << (8 * reg_offset
);
2396 mv_write(table
+ tbl_offset
, table_reg
);
2400 * eth_port_mc_addr - Multicast address settings.
2402 * The MV device supports multicast using two tables:
2403 * 1) Special Multicast Table for MAC addresses of the form
2404 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2405 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2406 * Table entries in the DA-Filter table.
2407 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2408 * is used as an index to the Other Multicast Table entries in the
2409 * DA-Filter table. This function calculates the CRC-8bit value.
2410 * In either case, eth_port_set_filter_table_entry() is then called
2411 * to set to set the actual table entry.
2413 static void eth_port_mc_addr(unsigned int eth_port_num
, unsigned char *p_addr
)
2417 unsigned char crc_result
= 0;
2423 if ((p_addr
[0] == 0x01) && (p_addr
[1] == 0x00) &&
2424 (p_addr
[2] == 0x5E) && (p_addr
[3] == 0x00) && (p_addr
[4] == 0x00)) {
2425 table
= DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2427 eth_port_set_filter_table_entry(table
, p_addr
[5]);
2431 /* Calculate CRC-8 out of the given address */
2432 mac_h
= (p_addr
[0] << 8) | (p_addr
[1]);
2433 mac_l
= (p_addr
[2] << 24) | (p_addr
[3] << 16) |
2434 (p_addr
[4] << 8) | (p_addr
[5] << 0);
2436 for (i
= 0; i
< 32; i
++)
2437 mac_array
[i
] = (mac_l
>> i
) & 0x1;
2438 for (i
= 32; i
< 48; i
++)
2439 mac_array
[i
] = (mac_h
>> (i
- 32)) & 0x1;
2441 crc
[0] = mac_array
[45] ^ mac_array
[43] ^ mac_array
[40] ^ mac_array
[39] ^
2442 mac_array
[35] ^ mac_array
[34] ^ mac_array
[31] ^ mac_array
[30] ^
2443 mac_array
[28] ^ mac_array
[23] ^ mac_array
[21] ^ mac_array
[19] ^
2444 mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^ mac_array
[12] ^
2445 mac_array
[8] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[0];
2447 crc
[1] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2448 mac_array
[41] ^ mac_array
[39] ^ mac_array
[36] ^ mac_array
[34] ^
2449 mac_array
[32] ^ mac_array
[30] ^ mac_array
[29] ^ mac_array
[28] ^
2450 mac_array
[24] ^ mac_array
[23] ^ mac_array
[22] ^ mac_array
[21] ^
2451 mac_array
[20] ^ mac_array
[18] ^ mac_array
[17] ^ mac_array
[16] ^
2452 mac_array
[15] ^ mac_array
[14] ^ mac_array
[13] ^ mac_array
[12] ^
2453 mac_array
[9] ^ mac_array
[6] ^ mac_array
[1] ^ mac_array
[0];
2455 crc
[2] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[44] ^ mac_array
[43] ^
2456 mac_array
[42] ^ mac_array
[39] ^ mac_array
[37] ^ mac_array
[34] ^
2457 mac_array
[33] ^ mac_array
[29] ^ mac_array
[28] ^ mac_array
[25] ^
2458 mac_array
[24] ^ mac_array
[22] ^ mac_array
[17] ^ mac_array
[15] ^
2459 mac_array
[13] ^ mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^
2460 mac_array
[6] ^ mac_array
[2] ^ mac_array
[1] ^ mac_array
[0];
2462 crc
[3] = mac_array
[47] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[43] ^
2463 mac_array
[40] ^ mac_array
[38] ^ mac_array
[35] ^ mac_array
[34] ^
2464 mac_array
[30] ^ mac_array
[29] ^ mac_array
[26] ^ mac_array
[25] ^
2465 mac_array
[23] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[14] ^
2466 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[7] ^
2467 mac_array
[3] ^ mac_array
[2] ^ mac_array
[1];
2469 crc
[4] = mac_array
[46] ^ mac_array
[45] ^ mac_array
[44] ^ mac_array
[41] ^
2470 mac_array
[39] ^ mac_array
[36] ^ mac_array
[35] ^ mac_array
[31] ^
2471 mac_array
[30] ^ mac_array
[27] ^ mac_array
[26] ^ mac_array
[24] ^
2472 mac_array
[19] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[14] ^
2473 mac_array
[12] ^ mac_array
[10] ^ mac_array
[8] ^ mac_array
[4] ^
2474 mac_array
[3] ^ mac_array
[2];
2476 crc
[5] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[45] ^ mac_array
[42] ^
2477 mac_array
[40] ^ mac_array
[37] ^ mac_array
[36] ^ mac_array
[32] ^
2478 mac_array
[31] ^ mac_array
[28] ^ mac_array
[27] ^ mac_array
[25] ^
2479 mac_array
[20] ^ mac_array
[18] ^ mac_array
[16] ^ mac_array
[15] ^
2480 mac_array
[13] ^ mac_array
[11] ^ mac_array
[9] ^ mac_array
[5] ^
2481 mac_array
[4] ^ mac_array
[3];
2483 crc
[6] = mac_array
[47] ^ mac_array
[46] ^ mac_array
[43] ^ mac_array
[41] ^
2484 mac_array
[38] ^ mac_array
[37] ^ mac_array
[33] ^ mac_array
[32] ^
2485 mac_array
[29] ^ mac_array
[28] ^ mac_array
[26] ^ mac_array
[21] ^
2486 mac_array
[19] ^ mac_array
[17] ^ mac_array
[16] ^ mac_array
[14] ^
2487 mac_array
[12] ^ mac_array
[10] ^ mac_array
[6] ^ mac_array
[5] ^
2490 crc
[7] = mac_array
[47] ^ mac_array
[44] ^ mac_array
[42] ^ mac_array
[39] ^
2491 mac_array
[38] ^ mac_array
[34] ^ mac_array
[33] ^ mac_array
[30] ^
2492 mac_array
[29] ^ mac_array
[27] ^ mac_array
[22] ^ mac_array
[20] ^
2493 mac_array
[18] ^ mac_array
[17] ^ mac_array
[15] ^ mac_array
[13] ^
2494 mac_array
[11] ^ mac_array
[7] ^ mac_array
[6] ^ mac_array
[5];
2496 for (i
= 0; i
< 8; i
++)
2497 crc_result
= crc_result
| (crc
[i
] << i
);
2499 table
= DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
);
2500 eth_port_set_filter_table_entry(table
, crc_result
);
2504 * Set the entire multicast list based on dev->mc_list.
2506 static void eth_port_set_multicast_list(struct net_device
*dev
)
2509 struct dev_mc_list
*mc_list
;
2512 struct mv643xx_private
*mp
= netdev_priv(dev
);
2513 unsigned int eth_port_num
= mp
->port_num
;
2515 /* If the device is in promiscuous mode or in all multicast mode,
2516 * we will fully populate both multicast tables with accept.
2517 * This is guaranteed to yield a match on all multicast addresses...
2519 if ((dev
->flags
& IFF_PROMISC
) || (dev
->flags
& IFF_ALLMULTI
)) {
2520 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2521 /* Set all entries in DA filter special multicast
2523 * Set for ETH_Q0 for now
2525 * 0 Accept=1, Drop=0
2526 * 3-1 Queue ETH_Q0=0
2529 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2531 /* Set all entries in DA filter other multicast
2533 * Set for ETH_Q0 for now
2535 * 0 Accept=1, Drop=0
2536 * 3-1 Queue ETH_Q0=0
2539 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num
) + table_index
, 0x01010101);
2544 /* We will clear out multicast tables every time we get the list.
2545 * Then add the entire new list...
2547 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2548 /* Clear DA filter special multicast table (Ex_dFSMT) */
2549 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2550 (eth_port_num
) + table_index
, 0);
2552 /* Clear DA filter other multicast table (Ex_dFOMT) */
2553 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2554 (eth_port_num
) + table_index
, 0);
2557 /* Get pointer to net_device multicast list and add each one... */
2558 for (i
= 0, mc_list
= dev
->mc_list
;
2559 (i
< 256) && (mc_list
!= NULL
) && (i
< dev
->mc_count
);
2560 i
++, mc_list
= mc_list
->next
)
2561 if (mc_list
->dmi_addrlen
== 6)
2562 eth_port_mc_addr(eth_port_num
, mc_list
->dmi_addr
);
2566 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2569 * Go through all the DA filter tables (Unicast, Special Multicast &
2570 * Other Multicast) and set each entry to 0.
2573 * unsigned int eth_port_num Ethernet Port number.
2576 * Multicast and Unicast packets are rejected.
2581 static void eth_port_init_mac_tables(unsigned int eth_port_num
)
2585 /* Clear DA filter unicast table (Ex_dFUT) */
2586 for (table_index
= 0; table_index
<= 0xC; table_index
+= 4)
2587 mv_write(DA_FILTER_UNICAST_TABLE_BASE
2588 (eth_port_num
) + table_index
, 0);
2590 for (table_index
= 0; table_index
<= 0xFC; table_index
+= 4) {
2591 /* Clear DA filter special multicast table (Ex_dFSMT) */
2592 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2593 (eth_port_num
) + table_index
, 0);
2594 /* Clear DA filter other multicast table (Ex_dFOMT) */
2595 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2596 (eth_port_num
) + table_index
, 0);
2601 * eth_clear_mib_counters - Clear all MIB counters
2604 * This function clears all MIB counters of a specific ethernet port.
2605 * A read from the MIB counter will reset the counter.
2608 * unsigned int eth_port_num Ethernet Port number.
2611 * After reading all MIB counters, the counters resets.
2614 * MIB counter value.
2617 static void eth_clear_mib_counters(unsigned int eth_port_num
)
2621 /* Perform dummy reads from MIB counters */
2622 for (i
= ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
; i
< ETH_MIB_LATE_COLLISION
;
2624 mv_read(MIB_COUNTERS_BASE(eth_port_num
) + i
);
2627 static inline u32
read_mib(struct mv643xx_private
*mp
, int offset
)
2629 return mv_read(MIB_COUNTERS_BASE(mp
->port_num
) + offset
);
2632 static void eth_update_mib_counters(struct mv643xx_private
*mp
)
2634 struct mv643xx_mib_counters
*p
= &mp
->mib_counters
;
2637 p
->good_octets_received
+=
2638 read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW
);
2639 p
->good_octets_received
+=
2640 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH
) << 32;
2642 for (offset
= ETH_MIB_BAD_OCTETS_RECEIVED
;
2643 offset
<= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS
;
2645 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2647 p
->good_octets_sent
+= read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_LOW
);
2648 p
->good_octets_sent
+=
2649 (u64
)read_mib(mp
, ETH_MIB_GOOD_OCTETS_SENT_HIGH
) << 32;
2651 for (offset
= ETH_MIB_GOOD_FRAMES_SENT
;
2652 offset
<= ETH_MIB_LATE_COLLISION
;
2654 *(u32
*)((char *)p
+ offset
) += read_mib(mp
, offset
);
2658 * ethernet_phy_detect - Detect whether a phy is present
2661 * This function tests whether there is a PHY present on
2662 * the specified port.
2665 * unsigned int eth_port_num Ethernet Port number.
2672 * -ENODEV on failure
2675 static int ethernet_phy_detect(unsigned int port_num
)
2677 unsigned int phy_reg_data0
;
2680 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2681 auto_neg
= phy_reg_data0
& 0x1000;
2682 phy_reg_data0
^= 0x1000; /* invert auto_neg */
2683 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2685 eth_port_read_smi_reg(port_num
, 0, &phy_reg_data0
);
2686 if ((phy_reg_data0
& 0x1000) == auto_neg
)
2687 return -ENODEV
; /* change didn't take */
2689 phy_reg_data0
^= 0x1000;
2690 eth_port_write_smi_reg(port_num
, 0, phy_reg_data0
);
2695 * ethernet_phy_get - Get the ethernet port PHY address.
2698 * This routine returns the given ethernet port PHY address.
2701 * unsigned int eth_port_num Ethernet Port number.
2710 static int ethernet_phy_get(unsigned int eth_port_num
)
2712 unsigned int reg_data
;
2714 reg_data
= mv_read(PHY_ADDR_REG
);
2716 return ((reg_data
>> (5 * eth_port_num
)) & 0x1f);
2720 * ethernet_phy_set - Set the ethernet port PHY address.
2723 * This routine sets the given ethernet port PHY address.
2726 * unsigned int eth_port_num Ethernet Port number.
2727 * int phy_addr PHY address.
2736 static void ethernet_phy_set(unsigned int eth_port_num
, int phy_addr
)
2739 int addr_shift
= 5 * eth_port_num
;
2741 reg_data
= mv_read(PHY_ADDR_REG
);
2742 reg_data
&= ~(0x1f << addr_shift
);
2743 reg_data
|= (phy_addr
& 0x1f) << addr_shift
;
2744 mv_write(PHY_ADDR_REG
, reg_data
);
2748 * ethernet_phy_reset - Reset Ethernet port PHY.
2751 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2754 * unsigned int eth_port_num Ethernet Port number.
2763 static void ethernet_phy_reset(unsigned int eth_port_num
)
2765 unsigned int phy_reg_data
;
2768 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2769 phy_reg_data
|= 0x8000; /* Set bit 15 to reset the PHY */
2770 eth_port_write_smi_reg(eth_port_num
, 0, phy_reg_data
);
2772 /* wait for PHY to come out of reset */
2775 eth_port_read_smi_reg(eth_port_num
, 0, &phy_reg_data
);
2776 } while (phy_reg_data
& 0x8000);
2779 static void mv643xx_eth_port_enable_tx(unsigned int port_num
,
2780 unsigned int queues
)
2782 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num
), queues
);
2785 static void mv643xx_eth_port_enable_rx(unsigned int port_num
,
2786 unsigned int queues
)
2788 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num
), queues
);
2791 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num
)
2795 /* Stop Tx port activity. Check port Tx activity. */
2796 queues
= mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num
)) & 0xFF;
2798 /* Issue stop command for active queues only */
2799 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num
), (queues
<< 8));
2801 /* Wait for all Tx activity to terminate. */
2802 /* Check port cause register that all Tx queues are stopped */
2803 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num
)) & 0xFF)
2804 udelay(PHY_WAIT_MICRO_SECONDS
);
2806 /* Wait for Tx FIFO to empty */
2807 while (mv_read(PORT_STATUS_REG(port_num
)) &
2808 ETH_PORT_TX_FIFO_EMPTY
)
2809 udelay(PHY_WAIT_MICRO_SECONDS
);
2815 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num
)
2819 /* Stop Rx port activity. Check port Rx activity. */
2820 queues
= mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num
)) & 0xFF;
2822 /* Issue stop command for active queues only */
2823 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num
), (queues
<< 8));
2825 /* Wait for all Rx activity to terminate. */
2826 /* Check port cause register that all Rx queues are stopped */
2827 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num
)) & 0xFF)
2828 udelay(PHY_WAIT_MICRO_SECONDS
);
2835 * eth_port_reset - Reset Ethernet port
2838 * This routine resets the chip by aborting any SDMA engine activity and
2839 * clearing the MIB counters. The Receiver and the Transmit unit are in
2840 * idle state after this command is performed and the port is disabled.
2843 * unsigned int eth_port_num Ethernet Port number.
2846 * Channel activity is halted.
2852 static void eth_port_reset(unsigned int port_num
)
2854 unsigned int reg_data
;
2856 mv643xx_eth_port_disable_tx(port_num
);
2857 mv643xx_eth_port_disable_rx(port_num
);
2859 /* Clear all MIB counters */
2860 eth_clear_mib_counters(port_num
);
2862 /* Reset the Enable bit in the Configuration Register */
2863 reg_data
= mv_read(PORT_SERIAL_CONTROL_REG(port_num
));
2864 reg_data
&= ~(SERIAL_PORT_ENABLE
|
2865 DO_NOT_FORCE_LINK_FAIL
|
2867 mv_write(PORT_SERIAL_CONTROL_REG(port_num
), reg_data
);
2872 * eth_port_read_smi_reg - Read PHY registers
2875 * This routine utilize the SMI interface to interact with the PHY in
2876 * order to perform PHY register read.
2879 * unsigned int port_num Ethernet Port number.
2880 * unsigned int phy_reg PHY register address offset.
2881 * unsigned int *value Register value buffer.
2884 * Write the value of a specified PHY register into given buffer.
2887 * false if the PHY is busy or read data is not in valid state.
2891 static void eth_port_read_smi_reg(unsigned int port_num
,
2892 unsigned int phy_reg
, unsigned int *value
)
2894 int phy_addr
= ethernet_phy_get(port_num
);
2895 unsigned long flags
;
2898 /* the SMI register is a shared resource */
2899 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2901 /* wait for the SMI register to become available */
2902 for (i
= 0; mv_read(SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2903 if (i
== PHY_WAIT_ITERATIONS
) {
2904 printk("mv643xx PHY busy timeout, port %d\n", port_num
);
2907 udelay(PHY_WAIT_MICRO_SECONDS
);
2911 (phy_addr
<< 16) | (phy_reg
<< 21) | ETH_SMI_OPCODE_READ
);
2913 /* now wait for the data to be valid */
2914 for (i
= 0; !(mv_read(SMI_REG
) & ETH_SMI_READ_VALID
); i
++) {
2915 if (i
== PHY_WAIT_ITERATIONS
) {
2916 printk("mv643xx PHY read timeout, port %d\n", port_num
);
2919 udelay(PHY_WAIT_MICRO_SECONDS
);
2922 *value
= mv_read(SMI_REG
) & 0xffff;
2924 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2928 * eth_port_write_smi_reg - Write to PHY registers
2931 * This routine utilize the SMI interface to interact with the PHY in
2932 * order to perform writes to PHY registers.
2935 * unsigned int eth_port_num Ethernet Port number.
2936 * unsigned int phy_reg PHY register address offset.
2937 * unsigned int value Register value.
2940 * Write the given value to the specified PHY register.
2943 * false if the PHY is busy.
2947 static void eth_port_write_smi_reg(unsigned int eth_port_num
,
2948 unsigned int phy_reg
, unsigned int value
)
2952 unsigned long flags
;
2954 phy_addr
= ethernet_phy_get(eth_port_num
);
2956 /* the SMI register is a shared resource */
2957 spin_lock_irqsave(&mv643xx_eth_phy_lock
, flags
);
2959 /* wait for the SMI register to become available */
2960 for (i
= 0; mv_read(SMI_REG
) & ETH_SMI_BUSY
; i
++) {
2961 if (i
== PHY_WAIT_ITERATIONS
) {
2962 printk("mv643xx PHY busy timeout, port %d\n",
2966 udelay(PHY_WAIT_MICRO_SECONDS
);
2969 mv_write(SMI_REG
, (phy_addr
<< 16) | (phy_reg
<< 21) |
2970 ETH_SMI_OPCODE_WRITE
| (value
& 0xffff));
2972 spin_unlock_irqrestore(&mv643xx_eth_phy_lock
, flags
);
2976 * Wrappers for MII support library.
2978 static int mv643xx_mdio_read(struct net_device
*dev
, int phy_id
, int location
)
2981 struct mv643xx_private
*mp
= netdev_priv(dev
);
2983 eth_port_read_smi_reg(mp
->port_num
, location
, &val
);
2987 static void mv643xx_mdio_write(struct net_device
*dev
, int phy_id
, int location
, int val
)
2989 struct mv643xx_private
*mp
= netdev_priv(dev
);
2990 eth_port_write_smi_reg(mp
->port_num
, location
, val
);
2994 * eth_port_receive - Get received information from Rx ring.
2997 * This routine returns the received data to the caller. There is no
2998 * data copying during routine operation. All information is returned
2999 * using pointer to packet information struct passed from the caller.
3000 * If the routine exhausts Rx ring resources then the resource error flag
3004 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3005 * struct pkt_info *p_pkt_info User packet buffer.
3008 * Rx ring current and used indexes are updated.
3011 * ETH_ERROR in case the routine can not access Rx desc ring.
3012 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3013 * ETH_END_OF_JOB if there is no received data.
3016 static ETH_FUNC_RET_STATUS
eth_port_receive(struct mv643xx_private
*mp
,
3017 struct pkt_info
*p_pkt_info
)
3019 int rx_next_curr_desc
, rx_curr_desc
, rx_used_desc
;
3020 volatile struct eth_rx_desc
*p_rx_desc
;
3021 unsigned int command_status
;
3022 unsigned long flags
;
3024 /* Do not process Rx ring in case of Rx ring resource error */
3025 if (mp
->rx_resource_err
)
3026 return ETH_QUEUE_FULL
;
3028 spin_lock_irqsave(&mp
->lock
, flags
);
3030 /* Get the Rx Desc ring 'curr and 'used' indexes */
3031 rx_curr_desc
= mp
->rx_curr_desc_q
;
3032 rx_used_desc
= mp
->rx_used_desc_q
;
3034 p_rx_desc
= &mp
->p_rx_desc_area
[rx_curr_desc
];
3036 /* The following parameters are used to save readings from memory */
3037 command_status
= p_rx_desc
->cmd_sts
;
3040 /* Nothing to receive... */
3041 if (command_status
& (ETH_BUFFER_OWNED_BY_DMA
)) {
3042 spin_unlock_irqrestore(&mp
->lock
, flags
);
3043 return ETH_END_OF_JOB
;
3046 p_pkt_info
->byte_cnt
= (p_rx_desc
->byte_cnt
) - RX_BUF_OFFSET
;
3047 p_pkt_info
->cmd_sts
= command_status
;
3048 p_pkt_info
->buf_ptr
= (p_rx_desc
->buf_ptr
) + RX_BUF_OFFSET
;
3049 p_pkt_info
->return_info
= mp
->rx_skb
[rx_curr_desc
];
3050 p_pkt_info
->l4i_chk
= p_rx_desc
->buf_size
;
3053 * Clean the return info field to indicate that the
3054 * packet has been moved to the upper layers
3056 mp
->rx_skb
[rx_curr_desc
] = NULL
;
3058 /* Update current index in data structure */
3059 rx_next_curr_desc
= (rx_curr_desc
+ 1) % mp
->rx_ring_size
;
3060 mp
->rx_curr_desc_q
= rx_next_curr_desc
;
3062 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
3063 if (rx_next_curr_desc
== rx_used_desc
)
3064 mp
->rx_resource_err
= 1;
3066 spin_unlock_irqrestore(&mp
->lock
, flags
);
3072 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3075 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3076 * next 'used' descriptor and attached the returned buffer to it.
3077 * In case the Rx ring was in "resource error" condition, where there are
3078 * no available Rx resources, the function resets the resource error flag.
3081 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3082 * struct pkt_info *p_pkt_info Information on returned buffer.
3085 * New available Rx resource in Rx descriptor ring.
3088 * ETH_ERROR in case the routine can not access Rx desc ring.
3091 static ETH_FUNC_RET_STATUS
eth_rx_return_buff(struct mv643xx_private
*mp
,
3092 struct pkt_info
*p_pkt_info
)
3094 int used_rx_desc
; /* Where to return Rx resource */
3095 volatile struct eth_rx_desc
*p_used_rx_desc
;
3096 unsigned long flags
;
3098 spin_lock_irqsave(&mp
->lock
, flags
);
3100 /* Get 'used' Rx descriptor */
3101 used_rx_desc
= mp
->rx_used_desc_q
;
3102 p_used_rx_desc
= &mp
->p_rx_desc_area
[used_rx_desc
];
3104 p_used_rx_desc
->buf_ptr
= p_pkt_info
->buf_ptr
;
3105 p_used_rx_desc
->buf_size
= p_pkt_info
->byte_cnt
;
3106 mp
->rx_skb
[used_rx_desc
] = p_pkt_info
->return_info
;
3108 /* Flush the write pipe */
3110 /* Return the descriptor to DMA ownership */
3112 p_used_rx_desc
->cmd_sts
=
3113 ETH_BUFFER_OWNED_BY_DMA
| ETH_RX_ENABLE_INTERRUPT
;
3116 /* Move the used descriptor pointer to the next descriptor */
3117 mp
->rx_used_desc_q
= (used_rx_desc
+ 1) % mp
->rx_ring_size
;
3119 /* Any Rx return cancels the Rx resource error status */
3120 mp
->rx_resource_err
= 0;
3122 spin_unlock_irqrestore(&mp
->lock
, flags
);
3127 /************* Begin ethtool support *************************/
3129 struct mv643xx_stats
{
3130 char stat_string
[ETH_GSTRING_LEN
];
3135 #define MV643XX_STAT(m) FIELD_SIZEOF(struct mv643xx_private, m), \
3136 offsetof(struct mv643xx_private, m)
3138 static const struct mv643xx_stats mv643xx_gstrings_stats
[] = {
3139 { "rx_packets", MV643XX_STAT(stats
.rx_packets
) },
3140 { "tx_packets", MV643XX_STAT(stats
.tx_packets
) },
3141 { "rx_bytes", MV643XX_STAT(stats
.rx_bytes
) },
3142 { "tx_bytes", MV643XX_STAT(stats
.tx_bytes
) },
3143 { "rx_errors", MV643XX_STAT(stats
.rx_errors
) },
3144 { "tx_errors", MV643XX_STAT(stats
.tx_errors
) },
3145 { "rx_dropped", MV643XX_STAT(stats
.rx_dropped
) },
3146 { "tx_dropped", MV643XX_STAT(stats
.tx_dropped
) },
3147 { "good_octets_received", MV643XX_STAT(mib_counters
.good_octets_received
) },
3148 { "bad_octets_received", MV643XX_STAT(mib_counters
.bad_octets_received
) },
3149 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters
.internal_mac_transmit_err
) },
3150 { "good_frames_received", MV643XX_STAT(mib_counters
.good_frames_received
) },
3151 { "bad_frames_received", MV643XX_STAT(mib_counters
.bad_frames_received
) },
3152 { "broadcast_frames_received", MV643XX_STAT(mib_counters
.broadcast_frames_received
) },
3153 { "multicast_frames_received", MV643XX_STAT(mib_counters
.multicast_frames_received
) },
3154 { "frames_64_octets", MV643XX_STAT(mib_counters
.frames_64_octets
) },
3155 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters
.frames_65_to_127_octets
) },
3156 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters
.frames_128_to_255_octets
) },
3157 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters
.frames_256_to_511_octets
) },
3158 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters
.frames_512_to_1023_octets
) },
3159 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters
.frames_1024_to_max_octets
) },
3160 { "good_octets_sent", MV643XX_STAT(mib_counters
.good_octets_sent
) },
3161 { "good_frames_sent", MV643XX_STAT(mib_counters
.good_frames_sent
) },
3162 { "excessive_collision", MV643XX_STAT(mib_counters
.excessive_collision
) },
3163 { "multicast_frames_sent", MV643XX_STAT(mib_counters
.multicast_frames_sent
) },
3164 { "broadcast_frames_sent", MV643XX_STAT(mib_counters
.broadcast_frames_sent
) },
3165 { "unrec_mac_control_received", MV643XX_STAT(mib_counters
.unrec_mac_control_received
) },
3166 { "fc_sent", MV643XX_STAT(mib_counters
.fc_sent
) },
3167 { "good_fc_received", MV643XX_STAT(mib_counters
.good_fc_received
) },
3168 { "bad_fc_received", MV643XX_STAT(mib_counters
.bad_fc_received
) },
3169 { "undersize_received", MV643XX_STAT(mib_counters
.undersize_received
) },
3170 { "fragments_received", MV643XX_STAT(mib_counters
.fragments_received
) },
3171 { "oversize_received", MV643XX_STAT(mib_counters
.oversize_received
) },
3172 { "jabber_received", MV643XX_STAT(mib_counters
.jabber_received
) },
3173 { "mac_receive_error", MV643XX_STAT(mib_counters
.mac_receive_error
) },
3174 { "bad_crc_event", MV643XX_STAT(mib_counters
.bad_crc_event
) },
3175 { "collision", MV643XX_STAT(mib_counters
.collision
) },
3176 { "late_collision", MV643XX_STAT(mib_counters
.late_collision
) },
3179 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
3181 static void mv643xx_get_drvinfo(struct net_device
*netdev
,
3182 struct ethtool_drvinfo
*drvinfo
)
3184 strncpy(drvinfo
->driver
, mv643xx_driver_name
, 32);
3185 strncpy(drvinfo
->version
, mv643xx_driver_version
, 32);
3186 strncpy(drvinfo
->fw_version
, "N/A", 32);
3187 strncpy(drvinfo
->bus_info
, "mv643xx", 32);
3188 drvinfo
->n_stats
= MV643XX_STATS_LEN
;
3191 static int mv643xx_get_sset_count(struct net_device
*netdev
, int sset
)
3195 return MV643XX_STATS_LEN
;
3201 static void mv643xx_get_ethtool_stats(struct net_device
*netdev
,
3202 struct ethtool_stats
*stats
, uint64_t *data
)
3204 struct mv643xx_private
*mp
= netdev
->priv
;
3207 eth_update_mib_counters(mp
);
3209 for (i
= 0; i
< MV643XX_STATS_LEN
; i
++) {
3210 char *p
= (char *)mp
+mv643xx_gstrings_stats
[i
].stat_offset
;
3211 data
[i
] = (mv643xx_gstrings_stats
[i
].sizeof_stat
==
3212 sizeof(uint64_t)) ? *(uint64_t *)p
: *(uint32_t *)p
;
3216 static void mv643xx_get_strings(struct net_device
*netdev
, uint32_t stringset
,
3223 for (i
=0; i
< MV643XX_STATS_LEN
; i
++) {
3224 memcpy(data
+ i
* ETH_GSTRING_LEN
,
3225 mv643xx_gstrings_stats
[i
].stat_string
,
3232 static u32
mv643xx_eth_get_link(struct net_device
*dev
)
3234 struct mv643xx_private
*mp
= netdev_priv(dev
);
3236 return mii_link_ok(&mp
->mii
);
3239 static int mv643xx_eth_nway_restart(struct net_device
*dev
)
3241 struct mv643xx_private
*mp
= netdev_priv(dev
);
3243 return mii_nway_restart(&mp
->mii
);
3246 static int mv643xx_eth_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
3248 struct mv643xx_private
*mp
= netdev_priv(dev
);
3250 return generic_mii_ioctl(&mp
->mii
, if_mii(ifr
), cmd
, NULL
);
3253 static const struct ethtool_ops mv643xx_ethtool_ops
= {
3254 .get_settings
= mv643xx_get_settings
,
3255 .set_settings
= mv643xx_set_settings
,
3256 .get_drvinfo
= mv643xx_get_drvinfo
,
3257 .get_link
= mv643xx_eth_get_link
,
3258 .set_sg
= ethtool_op_set_sg
,
3259 .get_sset_count
= mv643xx_get_sset_count
,
3260 .get_ethtool_stats
= mv643xx_get_ethtool_stats
,
3261 .get_strings
= mv643xx_get_strings
,
3262 .nway_reset
= mv643xx_eth_nway_restart
,
3265 /************* End ethtool support *************************/