drivers/net/mv643xx_eth.h

   1 #ifndef __MV643XX_ETH_H__
   2 #define __MV643XX_ETH_H__
   3
   4 #include <linux/module.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/workqueue.h>
   8 #include <linux/mii.h>
   9
  10 #include <linux/mv643xx.h>
  11
  12 #define BIT0    0x00000001
  13 #define BIT1    0x00000002
  14 #define BIT2    0x00000004
  15 #define BIT3    0x00000008
  16 #define BIT4    0x00000010
  17 #define BIT5    0x00000020
  18 #define BIT6    0x00000040
  19 #define BIT7    0x00000080
  20 #define BIT8    0x00000100
  21 #define BIT9    0x00000200
  22 #define BIT10   0x00000400
  23 #define BIT11   0x00000800
  24 #define BIT12   0x00001000
  25 #define BIT13   0x00002000
  26 #define BIT14   0x00004000
  27 #define BIT15   0x00008000
  28 #define BIT16   0x00010000
  29 #define BIT17   0x00020000
  30 #define BIT18   0x00040000
  31 #define BIT19   0x00080000
  32 #define BIT20   0x00100000
  33 #define BIT21   0x00200000
  34 #define BIT22   0x00400000
  35 #define BIT23   0x00800000
  36 #define BIT24   0x01000000
  37 #define BIT25   0x02000000
  38 #define BIT26   0x04000000
  39 #define BIT27   0x08000000
  40 #define BIT28   0x10000000
  41 #define BIT29   0x20000000
  42 #define BIT30   0x40000000
  43 #define BIT31   0x80000000
  44
  45 /*
  46  *  The first part is the high level driver of the gigE ethernet ports.
  47  */
  48
  49 /* Checksum offload for Tx works for most packets, but
  50  * fails if previous packet sent did not use hw csum
  51  */
  52 #define MV643XX_CHECKSUM_OFFLOAD_TX
  53 #define MV643XX_NAPI
  54 #define MV643XX_TX_FAST_REFILL
  55 #undef  MV643XX_RX_QUEUE_FILL_ON_TASK   /* Does not work, yet */
  56 #undef  MV643XX_COAL
  57
  58 /*
  59  * Number of RX / TX descriptors on RX / TX rings.
  60  * Note that allocating RX descriptors is done by allocating the RX
  61  * ring AND a preallocated RX buffers (skb's) for each descriptor.
  62  * The TX descriptors only allocates the TX descriptors ring,
  63  * with no pre allocated TX buffers (skb's are allocated by higher layers.
  64  */
  65
  66 /* Default TX ring size is 1000 descriptors */
  67 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
  68
  69 /* Default RX ring size is 400 descriptors */
  70 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
  71
  72 #define MV643XX_TX_COAL 100
  73 #ifdef MV643XX_COAL
  74 #define MV643XX_RX_COAL 100
  75 #endif
  76
  77 /*
  78  * The second part is the low level driver of the gigE ethernet ports.
  79  */
  80
  81 /*
  82  * Header File for : MV-643xx network interface header
  83  *
  84  * DESCRIPTION:
  85  *      This header file contains macros typedefs and function declaration for
  86  *      the Marvell Gig Bit Ethernet Controller.
  87  *
  88  * DEPENDENCIES:
  89  *      None.
  90  *
  91  */
  92
  93 /* Buffer offset from buffer pointer */
  94 #define RX_BUF_OFFSET                           0x2
  95
  96 /* Gigabit Ethernet Unit Global Registers */
  97
  98 /* MIB Counters register definitions */
  99 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW        0x0
 100 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH       0x4
 101 #define ETH_MIB_BAD_OCTETS_RECEIVED             0x8
 102 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR       0xc
 103 #define ETH_MIB_GOOD_FRAMES_RECEIVED            0x10
 104 #define ETH_MIB_BAD_FRAMES_RECEIVED             0x14
 105 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED       0x18
 106 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED       0x1c
 107 #define ETH_MIB_FRAMES_64_OCTETS                0x20
 108 #define ETH_MIB_FRAMES_65_TO_127_OCTETS         0x24
 109 #define ETH_MIB_FRAMES_128_TO_255_OCTETS        0x28
 110 #define ETH_MIB_FRAMES_256_TO_511_OCTETS        0x2c
 111 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS       0x30
 112 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS       0x34
 113 #define ETH_MIB_GOOD_OCTETS_SENT_LOW            0x38
 114 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH           0x3c
 115 #define ETH_MIB_GOOD_FRAMES_SENT                0x40
 116 #define ETH_MIB_EXCESSIVE_COLLISION             0x44
 117 #define ETH_MIB_MULTICAST_FRAMES_SENT           0x48
 118 #define ETH_MIB_BROADCAST_FRAMES_SENT           0x4c
 119 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED      0x50
 120 #define ETH_MIB_FC_SENT                         0x54
 121 #define ETH_MIB_GOOD_FC_RECEIVED                0x58
 122 #define ETH_MIB_BAD_FC_RECEIVED                 0x5c
 123 #define ETH_MIB_UNDERSIZE_RECEIVED              0x60
 124 #define ETH_MIB_FRAGMENTS_RECEIVED              0x64
 125 #define ETH_MIB_OVERSIZE_RECEIVED               0x68
 126 #define ETH_MIB_JABBER_RECEIVED                 0x6c
 127 #define ETH_MIB_MAC_RECEIVE_ERROR               0x70
 128 #define ETH_MIB_BAD_CRC_EVENT                   0x74
 129 #define ETH_MIB_COLLISION                       0x78
 130 #define ETH_MIB_LATE_COLLISION                  0x7c
 131
 132 /* Port serial status reg (PSR) */
 133 #define ETH_INTERFACE_GMII_MII                  0
 134 #define ETH_INTERFACE_PCM                       BIT0
 135 #define ETH_LINK_IS_DOWN                        0
 136 #define ETH_LINK_IS_UP                          BIT1
 137 #define ETH_PORT_AT_HALF_DUPLEX                 0
 138 #define ETH_PORT_AT_FULL_DUPLEX                 BIT2
 139 #define ETH_RX_FLOW_CTRL_DISABLED               0
 140 #define ETH_RX_FLOW_CTRL_ENBALED                BIT3
 141 #define ETH_GMII_SPEED_100_10                   0
 142 #define ETH_GMII_SPEED_1000                     BIT4
 143 #define ETH_MII_SPEED_10                        0
 144 #define ETH_MII_SPEED_100                       BIT5
 145 #define ETH_NO_TX                               0
 146 #define ETH_TX_IN_PROGRESS                      BIT7
 147 #define ETH_BYPASS_NO_ACTIVE                    0
 148 #define ETH_BYPASS_ACTIVE                       BIT8
 149 #define ETH_PORT_NOT_AT_PARTITION_STATE         0
 150 #define ETH_PORT_AT_PARTITION_STATE             BIT9
 151 #define ETH_PORT_TX_FIFO_NOT_EMPTY              0
 152 #define ETH_PORT_TX_FIFO_EMPTY                  BIT10
 153
 154 #define ETH_DEFAULT_RX_BPDU_QUEUE_3             (BIT23 | BIT22)
 155 #define ETH_DEFAULT_RX_BPDU_QUEUE_4             BIT24
 156 #define ETH_DEFAULT_RX_BPDU_QUEUE_5             (BIT24 | BIT22)
 157 #define ETH_DEFAULT_RX_BPDU_QUEUE_6             (BIT24 | BIT23)
 158 #define ETH_DEFAULT_RX_BPDU_QUEUE_7             (BIT24 | BIT23 | BIT22)
 159
 160 /* SMI reg */
 161 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 162 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 163 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 164 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress     */
 165
 166 /* SDMA command status fields macros */
 167
 168 /* Tx & Rx descriptors status */
 169 #define ETH_ERROR_SUMMARY                       (BIT0)
 170
 171 /* Tx & Rx descriptors command */
 172 #define ETH_BUFFER_OWNED_BY_DMA                 (BIT31)
 173
 174 /* Tx descriptors status */
 175 #define ETH_LC_ERROR                            (0    )
 176 #define ETH_UR_ERROR                            (BIT1 )
 177 #define ETH_RL_ERROR                            (BIT2 )
 178 #define ETH_LLC_SNAP_FORMAT                     (BIT9 )
 179
 180 /* Rx descriptors status */
 181 #define ETH_CRC_ERROR                           (0    )
 182 #define ETH_OVERRUN_ERROR                       (BIT1 )
 183 #define ETH_MAX_FRAME_LENGTH_ERROR              (BIT2 )
 184 #define ETH_RESOURCE_ERROR                      ((BIT2 | BIT1))
 185 #define ETH_VLAN_TAGGED                         (BIT19)
 186 #define ETH_BPDU_FRAME                          (BIT20)
 187 #define ETH_TCP_FRAME_OVER_IP_V_4               (0    )
 188 #define ETH_UDP_FRAME_OVER_IP_V_4               (BIT21)
 189 #define ETH_OTHER_FRAME_TYPE                    (BIT22)
 190 #define ETH_LAYER_2_IS_ETH_V_2                  (BIT23)
 191 #define ETH_FRAME_TYPE_IP_V_4                   (BIT24)
 192 #define ETH_FRAME_HEADER_OK                     (BIT25)
 193 #define ETH_RX_LAST_DESC                        (BIT26)
 194 #define ETH_RX_FIRST_DESC                       (BIT27)
 195 #define ETH_UNKNOWN_DESTINATION_ADDR            (BIT28)
 196 #define ETH_RX_ENABLE_INTERRUPT                 (BIT29)
 197 #define ETH_LAYER_4_CHECKSUM_OK                 (BIT30)
 198
 199 /* Rx descriptors byte count */
 200 #define ETH_FRAME_FRAGMENTED                    (BIT2)
 201
 202 /* Tx descriptors command */
 203 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 204 #define ETH_FRAME_SET_TO_VLAN                   (BIT15)
 205 #define ETH_TCP_FRAME                           (0    )
 206 #define ETH_UDP_FRAME                           (BIT16)
 207 #define ETH_GEN_TCP_UDP_CHECKSUM                (BIT17)
 208 #define ETH_GEN_IP_V_4_CHECKSUM                 (BIT18)
 209 #define ETH_ZERO_PADDING                        (BIT19)
 210 #define ETH_TX_LAST_DESC                        (BIT20)
 211 #define ETH_TX_FIRST_DESC                       (BIT21)
 212 #define ETH_GEN_CRC                             (BIT22)
 213 #define ETH_TX_ENABLE_INTERRUPT                 (BIT23)
 214 #define ETH_AUTO_MODE                           (BIT30)
 215
 216 #define ETH_TX_IHL_SHIFT                        11
 217
 218 /* typedefs */
 219
 220 typedef enum _eth_func_ret_status {
 221         ETH_OK,                 /* Returned as expected.                */
 222         ETH_ERROR,              /* Fundamental error.                   */
 223         ETH_RETRY,              /* Could not process request. Try later.*/
 224         ETH_END_OF_JOB,         /* Ring has nothing to process.         */
 225         ETH_QUEUE_FULL,         /* Ring resource error.                 */
 226         ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust.     */
 227 } ETH_FUNC_RET_STATUS;
 228
 229 typedef enum _eth_target {
 230         ETH_TARGET_DRAM,
 231         ETH_TARGET_DEVICE,
 232         ETH_TARGET_CBS,
 233         ETH_TARGET_PCI0,
 234         ETH_TARGET_PCI1
 235 } ETH_TARGET;
 236
 237 /* These are for big-endian machines.  Little endian needs different
 238  * definitions.
 239  */
 240 #if defined(__BIG_ENDIAN)
 241 struct eth_rx_desc {
 242         u16 byte_cnt;           /* Descriptor buffer byte count         */
 243         u16 buf_size;           /* Buffer size                          */
 244         u32 cmd_sts;            /* Descriptor command status            */
 245         u32 next_desc_ptr;      /* Next descriptor pointer              */
 246         u32 buf_ptr;            /* Descriptor buffer pointer            */
 247 };
 248
 249 struct eth_tx_desc {
 250         u16 byte_cnt;           /* buffer byte count                    */
 251         u16 l4i_chk;            /* CPU provided TCP checksum            */
 252         u32 cmd_sts;            /* Command/status field                 */
 253         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 254         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 255 };
 256
 257 #elif defined(__LITTLE_ENDIAN)
 258 struct eth_rx_desc {
 259         u32 cmd_sts;            /* Descriptor command status            */
 260         u16 buf_size;           /* Buffer size                          */
 261         u16 byte_cnt;           /* Descriptor buffer byte count         */
 262         u32 buf_ptr;            /* Descriptor buffer pointer            */
 263         u32 next_desc_ptr;      /* Next descriptor pointer              */
 264 };
 265
 266 struct eth_tx_desc {
 267         u32 cmd_sts;            /* Command/status field                 */
 268         u16 l4i_chk;            /* CPU provided TCP checksum            */
 269         u16 byte_cnt;           /* buffer byte count                    */
 270         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 271         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 272 };
 273 #else
 274 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
 275 #endif
 276
 277 /* Unified struct for Rx and Tx operations. The user is not required to */
 278 /* be familier with neither Tx nor Rx descriptors.                      */
 279 struct pkt_info {
 280         unsigned short byte_cnt;        /* Descriptor buffer byte count */
 281         unsigned short l4i_chk;         /* Tx CPU provided TCP Checksum */
 282         unsigned int cmd_sts;           /* Descriptor command status    */
 283         dma_addr_t buf_ptr;             /* Descriptor buffer pointer    */
 284         struct sk_buff *return_info;    /* User resource return information */
 285 };
 286
 287 /* Ethernet port specific infomation */
 288
 289 struct mv643xx_mib_counters {
 290         u64 good_octets_received;
 291         u32 bad_octets_received;
 292         u32 internal_mac_transmit_err;
 293         u32 good_frames_received;
 294         u32 bad_frames_received;
 295         u32 broadcast_frames_received;
 296         u32 multicast_frames_received;
 297         u32 frames_64_octets;
 298         u32 frames_65_to_127_octets;
 299         u32 frames_128_to_255_octets;
 300         u32 frames_256_to_511_octets;
 301         u32 frames_512_to_1023_octets;
 302         u32 frames_1024_to_max_octets;
 303         u64 good_octets_sent;
 304         u32 good_frames_sent;
 305         u32 excessive_collision;
 306         u32 multicast_frames_sent;
 307         u32 broadcast_frames_sent;
 308         u32 unrec_mac_control_received;
 309         u32 fc_sent;
 310         u32 good_fc_received;
 311         u32 bad_fc_received;
 312         u32 undersize_received;
 313         u32 fragments_received;
 314         u32 oversize_received;
 315         u32 jabber_received;
 316         u32 mac_receive_error;
 317         u32 bad_crc_event;
 318         u32 collision;
 319         u32 late_collision;
 320 };
 321
 322 struct mv643xx_private {
 323         int port_num;                   /* User Ethernet port number    */
 324         u32 port_tx_queue_command;      /* Port active Tx queues summary*/
 325         u32 port_rx_queue_command;      /* Port active Rx queues summary*/
 326
 327         u32 rx_sram_addr;               /* Base address of rx sram area */
 328         u32 rx_sram_size;               /* Size of rx sram area         */
 329         u32 tx_sram_addr;               /* Base address of tx sram area */
 330         u32 tx_sram_size;               /* Size of tx sram area         */
 331
 332         int rx_resource_err;            /* Rx ring resource error flag */
 333         int tx_resource_err;            /* Tx ring resource error flag */
 334
 335         /* Tx/Rx rings managment indexes fields. For driver use */
 336
 337         /* Next available and first returning Rx resource */
 338         int rx_curr_desc_q, rx_used_desc_q;
 339
 340         /* Next available and first returning Tx resource */
 341         int tx_curr_desc_q, tx_used_desc_q;
 342 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
 343         int tx_first_desc_q;
 344         u32 tx_first_command;
 345 #endif
 346
 347 #ifdef MV643XX_TX_FAST_REFILL
 348         u32 tx_clean_threshold;
 349 #endif
 350
 351         struct eth_rx_desc *p_rx_desc_area;
 352         dma_addr_t rx_desc_dma;
 353         unsigned int rx_desc_area_size;
 354         struct sk_buff **rx_skb;
 355
 356         struct eth_tx_desc *p_tx_desc_area;
 357         dma_addr_t tx_desc_dma;
 358         unsigned int tx_desc_area_size;
 359         struct sk_buff **tx_skb;
 360
 361         struct work_struct tx_timeout_task;
 362
 363         /*
 364          * Former struct mv643xx_eth_priv members start here
 365          */
 366         struct net_device_stats stats;
 367         struct mv643xx_mib_counters mib_counters;
 368         spinlock_t lock;
 369         /* Size of Tx Ring per queue */
 370         unsigned int tx_ring_size;
 371         /* Number of tx descriptors in use */
 372         unsigned int tx_desc_count;
 373         /* Size of Rx Ring per queue */
 374         unsigned int rx_ring_size;
 375         /* Number of rx descriptors in use */
 376         unsigned int rx_desc_count;
 377
 378         /*
 379          * rx_task used to fill RX ring out of bottom half context
 380          */
 381         struct work_struct rx_task;
 382
 383         /*
 384          * Used in case RX Ring is empty, which can be caused when
 385          * system does not have resources (skb's)
 386          */
 387         struct timer_list timeout;
 388         long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
 389         unsigned rx_timer_flag;
 390
 391         u32 rx_int_coal;
 392         u32 tx_int_coal;
 393         struct mii_if_info mii;
 394 };
 395
 396 /* ethernet.h API list */
 397
 398 /* Port operation control routines */
 399 static void eth_port_init(struct mv643xx_private *mp);
 400 static void eth_port_reset(unsigned int eth_port_num);
 401 static void eth_port_start(struct net_device *dev);
 402
 403 /* Port MAC address routines */
 404 static void eth_port_uc_addr_set(unsigned int eth_port_num,
 405                                  unsigned char *p_addr);
 406
 407 /* PHY and MIB routines */
 408 static void ethernet_phy_reset(unsigned int eth_port_num);
 409
 410 static void eth_port_write_smi_reg(unsigned int eth_port_num,
 411                                    unsigned int phy_reg, unsigned int value);
 412
 413 static void eth_port_read_smi_reg(unsigned int eth_port_num,
 414                                   unsigned int phy_reg, unsigned int *value);
 415
 416 static void eth_clear_mib_counters(unsigned int eth_port_num);
 417
 418 /* Port data flow control routines */
 419 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
 420                                          struct pkt_info *p_pkt_info);
 421 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
 422                                               struct pkt_info *p_pkt_info);
 423 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
 424                                             struct pkt_info *p_pkt_info);
 425 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
 426                                               struct pkt_info *p_pkt_info);
 427
 428 #endif                          /* __MV643XX_ETH_H__ */