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Merge branch 'upstream-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/linvil...
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.1.0"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 #define MYRI10GE_ALLOC_ORDER 0
96 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
99 struct myri10ge_rx_buffer_state {
100 struct page *page;
101 int page_offset;
102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104 };
105
106 struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111 };
112
113 struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117 };
118
119 struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
127 int cnt;
128 int fill_cnt;
129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
131 int watchdog_needed;
132 };
133
134 struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146 };
147
148 struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153 };
154
155 struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
163 int big_bytes;
164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
179 __be32 link_state;
180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
182 __be32 __iomem *intr_coal_delay_ptr;
183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
191 int watchdog_tx_req;
192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
198 u8 mac_addr[6]; /* eeprom mac address */
199 unsigned long serial_number;
200 int vendor_specific_offset;
201 int fw_multicast_support;
202 u32 read_dma;
203 u32 write_dma;
204 u32 read_write_dma;
205 u32 link_changes;
206 u32 msg_enable;
207 };
208
209 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
210 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
211
212 static char *myri10ge_fw_name = NULL;
213 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
214 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
215
216 static int myri10ge_ecrc_enable = 1;
217 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
218 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
219
220 static int myri10ge_max_intr_slots = 1024;
221 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
222 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
223
224 static int myri10ge_small_bytes = -1; /* -1 == auto */
225 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
226 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
227
228 static int myri10ge_msi = 1; /* enable msi by default */
229 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
230 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
231
232 static int myri10ge_intr_coal_delay = 25;
233 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
234 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
235
236 static int myri10ge_flow_control = 1;
237 module_param(myri10ge_flow_control, int, S_IRUGO);
238 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
239
240 static int myri10ge_deassert_wait = 1;
241 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
242 MODULE_PARM_DESC(myri10ge_deassert_wait,
243 "Wait when deasserting legacy interrupts\n");
244
245 static int myri10ge_force_firmware = 0;
246 module_param(myri10ge_force_firmware, int, S_IRUGO);
247 MODULE_PARM_DESC(myri10ge_force_firmware,
248 "Force firmware to assume aligned completions\n");
249
250 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
251 module_param(myri10ge_initial_mtu, int, S_IRUGO);
252 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
253
254 static int myri10ge_napi_weight = 64;
255 module_param(myri10ge_napi_weight, int, S_IRUGO);
256 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
257
258 static int myri10ge_watchdog_timeout = 1;
259 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
260 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
261
262 static int myri10ge_max_irq_loops = 1048576;
263 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
264 MODULE_PARM_DESC(myri10ge_max_irq_loops,
265 "Set stuck legacy IRQ detection threshold\n");
266
267 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
268
269 static int myri10ge_debug = -1; /* defaults above */
270 module_param(myri10ge_debug, int, 0);
271 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
272
273 static int myri10ge_fill_thresh = 256;
274 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
275 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
276
277 #define MYRI10GE_FW_OFFSET 1024*1024
278 #define MYRI10GE_HIGHPART_TO_U32(X) \
279 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
280 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
281
282 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
283
284 static inline void put_be32(__be32 val, __be32 __iomem * p)
285 {
286 __raw_writel((__force __u32) val, (__force void __iomem *)p);
287 }
288
289 static int
290 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
291 struct myri10ge_cmd *data, int atomic)
292 {
293 struct mcp_cmd *buf;
294 char buf_bytes[sizeof(*buf) + 8];
295 struct mcp_cmd_response *response = mgp->cmd;
296 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
297 u32 dma_low, dma_high, result, value;
298 int sleep_total = 0;
299
300 /* ensure buf is aligned to 8 bytes */
301 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
302
303 buf->data0 = htonl(data->data0);
304 buf->data1 = htonl(data->data1);
305 buf->data2 = htonl(data->data2);
306 buf->cmd = htonl(cmd);
307 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
308 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
309
310 buf->response_addr.low = htonl(dma_low);
311 buf->response_addr.high = htonl(dma_high);
312 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
313 mb();
314 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
315
316 /* wait up to 15ms. Longest command is the DMA benchmark,
317 * which is capped at 5ms, but runs from a timeout handler
318 * that runs every 7.8ms. So a 15ms timeout leaves us with
319 * a 2.2ms margin
320 */
321 if (atomic) {
322 /* if atomic is set, do not sleep,
323 * and try to get the completion quickly
324 * (1ms will be enough for those commands) */
325 for (sleep_total = 0;
326 sleep_total < 1000
327 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
328 sleep_total += 10)
329 udelay(10);
330 } else {
331 /* use msleep for most command */
332 for (sleep_total = 0;
333 sleep_total < 15
334 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
335 sleep_total++)
336 msleep(1);
337 }
338
339 result = ntohl(response->result);
340 value = ntohl(response->data);
341 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
342 if (result == 0) {
343 data->data0 = value;
344 return 0;
345 } else if (result == MXGEFW_CMD_UNKNOWN) {
346 return -ENOSYS;
347 } else {
348 dev_err(&mgp->pdev->dev,
349 "command %d failed, result = %d\n",
350 cmd, result);
351 return -ENXIO;
352 }
353 }
354
355 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
356 cmd, result);
357 return -EAGAIN;
358 }
359
360 /*
361 * The eeprom strings on the lanaiX have the format
362 * SN=x\0
363 * MAC=x:x:x:x:x:x\0
364 * PT:ddd mmm xx xx:xx:xx xx\0
365 * PV:ddd mmm xx xx:xx:xx xx\0
366 */
367 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
368 {
369 char *ptr, *limit;
370 int i;
371
372 ptr = mgp->eeprom_strings;
373 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
374
375 while (*ptr != '\0' && ptr < limit) {
376 if (memcmp(ptr, "MAC=", 4) == 0) {
377 ptr += 4;
378 mgp->mac_addr_string = ptr;
379 for (i = 0; i < 6; i++) {
380 if ((ptr + 2) > limit)
381 goto abort;
382 mgp->mac_addr[i] =
383 simple_strtoul(ptr, &ptr, 16);
384 ptr += 1;
385 }
386 }
387 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
388 ptr += 3;
389 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
390 }
391 while (ptr < limit && *ptr++) ;
392 }
393
394 return 0;
395
396 abort:
397 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
398 return -ENXIO;
399 }
400
401 /*
402 * Enable or disable periodic RDMAs from the host to make certain
403 * chipsets resend dropped PCIe messages
404 */
405
406 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
407 {
408 char __iomem *submit;
409 __be32 buf[16];
410 u32 dma_low, dma_high;
411 int i;
412
413 /* clear confirmation addr */
414 mgp->cmd->data = 0;
415 mb();
416
417 /* send a rdma command to the PCIe engine, and wait for the
418 * response in the confirmation address. The firmware should
419 * write a -1 there to indicate it is alive and well
420 */
421 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
422 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
423
424 buf[0] = htonl(dma_high); /* confirm addr MSW */
425 buf[1] = htonl(dma_low); /* confirm addr LSW */
426 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
427 buf[3] = htonl(dma_high); /* dummy addr MSW */
428 buf[4] = htonl(dma_low); /* dummy addr LSW */
429 buf[5] = htonl(enable); /* enable? */
430
431 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
432
433 myri10ge_pio_copy(submit, &buf, sizeof(buf));
434 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
435 msleep(1);
436 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
437 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
438 (enable ? "enable" : "disable"));
439 }
440
441 static int
442 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
443 struct mcp_gen_header *hdr)
444 {
445 struct device *dev = &mgp->pdev->dev;
446 int major, minor;
447
448 /* check firmware type */
449 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
450 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
451 return -EINVAL;
452 }
453
454 /* save firmware version for ethtool */
455 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
456
457 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
458
459 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
460 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
461 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
462 MXGEFW_VERSION_MINOR);
463 return -EINVAL;
464 }
465 return 0;
466 }
467
468 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
469 {
470 unsigned crc, reread_crc;
471 const struct firmware *fw;
472 struct device *dev = &mgp->pdev->dev;
473 struct mcp_gen_header *hdr;
474 size_t hdr_offset;
475 int status;
476 unsigned i;
477
478 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
479 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
480 mgp->fw_name);
481 status = -EINVAL;
482 goto abort_with_nothing;
483 }
484
485 /* check size */
486
487 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
488 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
489 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
490 status = -EINVAL;
491 goto abort_with_fw;
492 }
493
494 /* check id */
495 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
496 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
497 dev_err(dev, "Bad firmware file\n");
498 status = -EINVAL;
499 goto abort_with_fw;
500 }
501 hdr = (void *)(fw->data + hdr_offset);
502
503 status = myri10ge_validate_firmware(mgp, hdr);
504 if (status != 0)
505 goto abort_with_fw;
506
507 crc = crc32(~0, fw->data, fw->size);
508 for (i = 0; i < fw->size; i += 256) {
509 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
510 fw->data + i,
511 min(256U, (unsigned)(fw->size - i)));
512 mb();
513 readb(mgp->sram);
514 }
515 /* corruption checking is good for parity recovery and buggy chipset */
516 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
517 reread_crc = crc32(~0, fw->data, fw->size);
518 if (crc != reread_crc) {
519 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
520 (unsigned)fw->size, reread_crc, crc);
521 status = -EIO;
522 goto abort_with_fw;
523 }
524 *size = (u32) fw->size;
525
526 abort_with_fw:
527 release_firmware(fw);
528
529 abort_with_nothing:
530 return status;
531 }
532
533 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
534 {
535 struct mcp_gen_header *hdr;
536 struct device *dev = &mgp->pdev->dev;
537 const size_t bytes = sizeof(struct mcp_gen_header);
538 size_t hdr_offset;
539 int status;
540
541 /* find running firmware header */
542 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
543
544 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
545 dev_err(dev, "Running firmware has bad header offset (%d)\n",
546 (int)hdr_offset);
547 return -EIO;
548 }
549
550 /* copy header of running firmware from SRAM to host memory to
551 * validate firmware */
552 hdr = kmalloc(bytes, GFP_KERNEL);
553 if (hdr == NULL) {
554 dev_err(dev, "could not malloc firmware hdr\n");
555 return -ENOMEM;
556 }
557 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
558 status = myri10ge_validate_firmware(mgp, hdr);
559 kfree(hdr);
560 return status;
561 }
562
563 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
564 {
565 char __iomem *submit;
566 __be32 buf[16];
567 u32 dma_low, dma_high, size;
568 int status, i;
569
570 size = 0;
571 status = myri10ge_load_hotplug_firmware(mgp, &size);
572 if (status) {
573 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
574
575 /* Do not attempt to adopt firmware if there
576 * was a bad crc */
577 if (status == -EIO)
578 return status;
579
580 status = myri10ge_adopt_running_firmware(mgp);
581 if (status != 0) {
582 dev_err(&mgp->pdev->dev,
583 "failed to adopt running firmware\n");
584 return status;
585 }
586 dev_info(&mgp->pdev->dev,
587 "Successfully adopted running firmware\n");
588 if (mgp->tx.boundary == 4096) {
589 dev_warn(&mgp->pdev->dev,
590 "Using firmware currently running on NIC"
591 ". For optimal\n");
592 dev_warn(&mgp->pdev->dev,
593 "performance consider loading optimized "
594 "firmware\n");
595 dev_warn(&mgp->pdev->dev, "via hotplug\n");
596 }
597
598 mgp->fw_name = "adopted";
599 mgp->tx.boundary = 2048;
600 return status;
601 }
602
603 /* clear confirmation addr */
604 mgp->cmd->data = 0;
605 mb();
606
607 /* send a reload command to the bootstrap MCP, and wait for the
608 * response in the confirmation address. The firmware should
609 * write a -1 there to indicate it is alive and well
610 */
611 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
612 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
613
614 buf[0] = htonl(dma_high); /* confirm addr MSW */
615 buf[1] = htonl(dma_low); /* confirm addr LSW */
616 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
617
618 /* FIX: All newest firmware should un-protect the bottom of
619 * the sram before handoff. However, the very first interfaces
620 * do not. Therefore the handoff copy must skip the first 8 bytes
621 */
622 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
623 buf[4] = htonl(size - 8); /* length of code */
624 buf[5] = htonl(8); /* where to copy to */
625 buf[6] = htonl(0); /* where to jump to */
626
627 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
628
629 myri10ge_pio_copy(submit, &buf, sizeof(buf));
630 mb();
631 msleep(1);
632 mb();
633 i = 0;
634 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
635 msleep(1);
636 i++;
637 }
638 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
639 dev_err(&mgp->pdev->dev, "handoff failed\n");
640 return -ENXIO;
641 }
642 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
643 myri10ge_dummy_rdma(mgp, 1);
644
645 return 0;
646 }
647
648 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
649 {
650 struct myri10ge_cmd cmd;
651 int status;
652
653 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
654 | (addr[2] << 8) | addr[3]);
655
656 cmd.data1 = ((addr[4] << 8) | (addr[5]));
657
658 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
659 return status;
660 }
661
662 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
663 {
664 struct myri10ge_cmd cmd;
665 int status, ctl;
666
667 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
668 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
669
670 if (status) {
671 printk(KERN_ERR
672 "myri10ge: %s: Failed to set flow control mode\n",
673 mgp->dev->name);
674 return status;
675 }
676 mgp->pause = pause;
677 return 0;
678 }
679
680 static void
681 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
682 {
683 struct myri10ge_cmd cmd;
684 int status, ctl;
685
686 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
687 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
688 if (status)
689 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
690 mgp->dev->name);
691 }
692
693 static int myri10ge_reset(struct myri10ge_priv *mgp)
694 {
695 struct myri10ge_cmd cmd;
696 int status;
697 size_t bytes;
698 u32 len;
699
700 /* try to send a reset command to the card to see if it
701 * is alive */
702 memset(&cmd, 0, sizeof(cmd));
703 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
704 if (status != 0) {
705 dev_err(&mgp->pdev->dev, "failed reset\n");
706 return -ENXIO;
707 }
708
709 /* Now exchange information about interrupts */
710
711 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
712 memset(mgp->rx_done.entry, 0, bytes);
713 cmd.data0 = (u32) bytes;
714 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
715 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
716 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
717 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
718
719 status |=
720 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
721 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
722 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
723 &cmd, 0);
724 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
725
726 status |= myri10ge_send_cmd
727 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
728 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
729 if (status != 0) {
730 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
731 return status;
732 }
733 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
734
735 /* Run a small DMA test.
736 * The magic multipliers to the length tell the firmware
737 * to do DMA read, write, or read+write tests. The
738 * results are returned in cmd.data0. The upper 16
739 * bits or the return is the number of transfers completed.
740 * The lower 16 bits is the time in 0.5us ticks that the
741 * transfers took to complete.
742 */
743
744 len = mgp->tx.boundary;
745
746 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
747 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
748 cmd.data2 = len * 0x10000;
749 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
750 if (status == 0)
751 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
752 (cmd.data0 & 0xffff);
753 else
754 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
755 status);
756 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
757 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
758 cmd.data2 = len * 0x1;
759 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
760 if (status == 0)
761 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
762 (cmd.data0 & 0xffff);
763 else
764 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
765 status);
766
767 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
768 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
769 cmd.data2 = len * 0x10001;
770 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
771 if (status == 0)
772 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
773 (cmd.data0 & 0xffff);
774 else
775 dev_warn(&mgp->pdev->dev,
776 "DMA read/write benchmark failed: %d\n", status);
777
778 memset(mgp->rx_done.entry, 0, bytes);
779
780 /* reset mcp/driver shared state back to 0 */
781 mgp->tx.req = 0;
782 mgp->tx.done = 0;
783 mgp->tx.pkt_start = 0;
784 mgp->tx.pkt_done = 0;
785 mgp->rx_big.cnt = 0;
786 mgp->rx_small.cnt = 0;
787 mgp->rx_done.idx = 0;
788 mgp->rx_done.cnt = 0;
789 mgp->link_changes = 0;
790 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
791 myri10ge_change_promisc(mgp, 0, 0);
792 myri10ge_change_pause(mgp, mgp->pause);
793 return status;
794 }
795
796 static inline void
797 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
798 struct mcp_kreq_ether_recv *src)
799 {
800 __be32 low;
801
802 low = src->addr_low;
803 src->addr_low = htonl(DMA_32BIT_MASK);
804 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
805 mb();
806 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
807 mb();
808 src->addr_low = low;
809 put_be32(low, &dst->addr_low);
810 mb();
811 }
812
813 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
814 {
815 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
816
817 if ((skb->protocol == htons(ETH_P_8021Q)) &&
818 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
819 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
820 skb->csum = hw_csum;
821 skb->ip_summed = CHECKSUM_COMPLETE;
822 }
823 }
824
825 static inline void
826 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
827 struct skb_frag_struct *rx_frags, int len, int hlen)
828 {
829 struct skb_frag_struct *skb_frags;
830
831 skb->len = skb->data_len = len;
832 skb->truesize = len + sizeof(struct sk_buff);
833 /* attach the page(s) */
834
835 skb_frags = skb_shinfo(skb)->frags;
836 while (len > 0) {
837 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
838 len -= rx_frags->size;
839 skb_frags++;
840 rx_frags++;
841 skb_shinfo(skb)->nr_frags++;
842 }
843
844 /* pskb_may_pull is not available in irq context, but
845 * skb_pull() (for ether_pad and eth_type_trans()) requires
846 * the beginning of the packet in skb_headlen(), move it
847 * manually */
848 memcpy(skb->data, va, hlen);
849 skb_shinfo(skb)->frags[0].page_offset += hlen;
850 skb_shinfo(skb)->frags[0].size -= hlen;
851 skb->data_len -= hlen;
852 skb->tail += hlen;
853 skb_pull(skb, MXGEFW_PAD);
854 }
855
856 static void
857 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
858 int bytes, int watchdog)
859 {
860 struct page *page;
861 int idx;
862
863 if (unlikely(rx->watchdog_needed && !watchdog))
864 return;
865
866 /* try to refill entire ring */
867 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
868 idx = rx->fill_cnt & rx->mask;
869
870 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
871 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
872 /* we can use part of previous page */
873 get_page(rx->page);
874 } else {
875 /* we need a new page */
876 page =
877 alloc_pages(GFP_ATOMIC | __GFP_COMP,
878 MYRI10GE_ALLOC_ORDER);
879 if (unlikely(page == NULL)) {
880 if (rx->fill_cnt - rx->cnt < 16)
881 rx->watchdog_needed = 1;
882 return;
883 }
884 rx->page = page;
885 rx->page_offset = 0;
886 rx->bus = pci_map_page(mgp->pdev, page, 0,
887 MYRI10GE_ALLOC_SIZE,
888 PCI_DMA_FROMDEVICE);
889 }
890 rx->info[idx].page = rx->page;
891 rx->info[idx].page_offset = rx->page_offset;
892 /* note that this is the address of the start of the
893 * page */
894 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
895 rx->shadow[idx].addr_low =
896 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
897 rx->shadow[idx].addr_high =
898 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
899
900 /* start next packet on a cacheline boundary */
901 rx->page_offset += SKB_DATA_ALIGN(bytes);
902 rx->fill_cnt++;
903
904 /* copy 8 descriptors to the firmware at a time */
905 if ((idx & 7) == 7) {
906 if (rx->wc_fifo == NULL)
907 myri10ge_submit_8rx(&rx->lanai[idx - 7],
908 &rx->shadow[idx - 7]);
909 else {
910 mb();
911 myri10ge_pio_copy(rx->wc_fifo,
912 &rx->shadow[idx - 7], 64);
913 }
914 }
915 }
916 }
917
918 static inline void
919 myri10ge_unmap_rx_page(struct pci_dev *pdev,
920 struct myri10ge_rx_buffer_state *info, int bytes)
921 {
922 /* unmap the recvd page if we're the only or last user of it */
923 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
924 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
925 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
926 & ~(MYRI10GE_ALLOC_SIZE - 1)),
927 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
928 }
929 }
930
931 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
932 * page into an skb */
933
934 static inline int
935 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
936 int bytes, int len, __wsum csum)
937 {
938 struct sk_buff *skb;
939 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
940 int i, idx, hlen, remainder;
941 struct pci_dev *pdev = mgp->pdev;
942 struct net_device *dev = mgp->dev;
943 u8 *va;
944
945 len += MXGEFW_PAD;
946 idx = rx->cnt & rx->mask;
947 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
948 prefetch(va);
949 /* Fill skb_frag_struct(s) with data from our receive */
950 for (i = 0, remainder = len; remainder > 0; i++) {
951 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
952 rx_frags[i].page = rx->info[idx].page;
953 rx_frags[i].page_offset = rx->info[idx].page_offset;
954 if (remainder < MYRI10GE_ALLOC_SIZE)
955 rx_frags[i].size = remainder;
956 else
957 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
958 rx->cnt++;
959 idx = rx->cnt & rx->mask;
960 remainder -= MYRI10GE_ALLOC_SIZE;
961 }
962
963 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
964
965 /* allocate an skb to attach the page(s) to. */
966
967 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
968 if (unlikely(skb == NULL)) {
969 mgp->stats.rx_dropped++;
970 do {
971 i--;
972 put_page(rx_frags[i].page);
973 } while (i != 0);
974 return 0;
975 }
976
977 /* Attach the pages to the skb, and trim off any padding */
978 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
979 if (skb_shinfo(skb)->frags[0].size <= 0) {
980 put_page(skb_shinfo(skb)->frags[0].page);
981 skb_shinfo(skb)->nr_frags = 0;
982 }
983 skb->protocol = eth_type_trans(skb, dev);
984 skb->dev = dev;
985
986 if (mgp->csum_flag) {
987 if ((skb->protocol == htons(ETH_P_IP)) ||
988 (skb->protocol == htons(ETH_P_IPV6))) {
989 skb->csum = csum;
990 skb->ip_summed = CHECKSUM_COMPLETE;
991 } else
992 myri10ge_vlan_ip_csum(skb, csum);
993 }
994 netif_receive_skb(skb);
995 dev->last_rx = jiffies;
996 return 1;
997 }
998
999 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1000 {
1001 struct pci_dev *pdev = mgp->pdev;
1002 struct myri10ge_tx_buf *tx = &mgp->tx;
1003 struct sk_buff *skb;
1004 int idx, len;
1005 int limit = 0;
1006
1007 while (tx->pkt_done != mcp_index) {
1008 idx = tx->done & tx->mask;
1009 skb = tx->info[idx].skb;
1010
1011 /* Mark as free */
1012 tx->info[idx].skb = NULL;
1013 if (tx->info[idx].last) {
1014 tx->pkt_done++;
1015 tx->info[idx].last = 0;
1016 }
1017 tx->done++;
1018 len = pci_unmap_len(&tx->info[idx], len);
1019 pci_unmap_len_set(&tx->info[idx], len, 0);
1020 if (skb) {
1021 mgp->stats.tx_bytes += skb->len;
1022 mgp->stats.tx_packets++;
1023 dev_kfree_skb_irq(skb);
1024 if (len)
1025 pci_unmap_single(pdev,
1026 pci_unmap_addr(&tx->info[idx],
1027 bus), len,
1028 PCI_DMA_TODEVICE);
1029 } else {
1030 if (len)
1031 pci_unmap_page(pdev,
1032 pci_unmap_addr(&tx->info[idx],
1033 bus), len,
1034 PCI_DMA_TODEVICE);
1035 }
1036
1037 /* limit potential for livelock by only handling
1038 * 2 full tx rings per call */
1039 if (unlikely(++limit > 2 * tx->mask))
1040 break;
1041 }
1042 /* start the queue if we've stopped it */
1043 if (netif_queue_stopped(mgp->dev)
1044 && tx->req - tx->done < (tx->mask >> 1)) {
1045 mgp->wake_queue++;
1046 netif_wake_queue(mgp->dev);
1047 }
1048 }
1049
1050 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1051 {
1052 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1053 unsigned long rx_bytes = 0;
1054 unsigned long rx_packets = 0;
1055 unsigned long rx_ok;
1056
1057 int idx = rx_done->idx;
1058 int cnt = rx_done->cnt;
1059 u16 length;
1060 __wsum checksum;
1061
1062 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1063 length = ntohs(rx_done->entry[idx].length);
1064 rx_done->entry[idx].length = 0;
1065 checksum = csum_unfold(rx_done->entry[idx].checksum);
1066 if (length <= mgp->small_bytes)
1067 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1068 mgp->small_bytes,
1069 length, checksum);
1070 else
1071 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1072 mgp->big_bytes,
1073 length, checksum);
1074 rx_packets += rx_ok;
1075 rx_bytes += rx_ok * (unsigned long)length;
1076 cnt++;
1077 idx = cnt & (myri10ge_max_intr_slots - 1);
1078
1079 /* limit potential for livelock by only handling a
1080 * limited number of frames. */
1081 (*limit)--;
1082 }
1083 rx_done->idx = idx;
1084 rx_done->cnt = cnt;
1085 mgp->stats.rx_packets += rx_packets;
1086 mgp->stats.rx_bytes += rx_bytes;
1087
1088 /* restock receive rings if needed */
1089 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1090 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1091 mgp->small_bytes + MXGEFW_PAD, 0);
1092 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1093 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1094
1095 }
1096
1097 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1098 {
1099 struct mcp_irq_data *stats = mgp->fw_stats;
1100
1101 if (unlikely(stats->stats_updated)) {
1102 if (mgp->link_state != stats->link_up) {
1103 mgp->link_state = stats->link_up;
1104 if (mgp->link_state) {
1105 if (netif_msg_link(mgp))
1106 printk(KERN_INFO
1107 "myri10ge: %s: link up\n",
1108 mgp->dev->name);
1109 netif_carrier_on(mgp->dev);
1110 mgp->link_changes++;
1111 } else {
1112 if (netif_msg_link(mgp))
1113 printk(KERN_INFO
1114 "myri10ge: %s: link down\n",
1115 mgp->dev->name);
1116 netif_carrier_off(mgp->dev);
1117 mgp->link_changes++;
1118 }
1119 }
1120 if (mgp->rdma_tags_available !=
1121 ntohl(mgp->fw_stats->rdma_tags_available)) {
1122 mgp->rdma_tags_available =
1123 ntohl(mgp->fw_stats->rdma_tags_available);
1124 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1125 "%d tags left\n", mgp->dev->name,
1126 mgp->rdma_tags_available);
1127 }
1128 mgp->down_cnt += stats->link_down;
1129 if (stats->link_down)
1130 wake_up(&mgp->down_wq);
1131 }
1132 }
1133
1134 static int myri10ge_poll(struct net_device *netdev, int *budget)
1135 {
1136 struct myri10ge_priv *mgp = netdev_priv(netdev);
1137 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1138 int limit, orig_limit, work_done;
1139
1140 /* process as many rx events as NAPI will allow */
1141 limit = min(*budget, netdev->quota);
1142 orig_limit = limit;
1143 myri10ge_clean_rx_done(mgp, &limit);
1144 work_done = orig_limit - limit;
1145 *budget -= work_done;
1146 netdev->quota -= work_done;
1147
1148 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1149 netif_rx_complete(netdev);
1150 put_be32(htonl(3), mgp->irq_claim);
1151 return 0;
1152 }
1153 return 1;
1154 }
1155
1156 static irqreturn_t myri10ge_intr(int irq, void *arg)
1157 {
1158 struct myri10ge_priv *mgp = arg;
1159 struct mcp_irq_data *stats = mgp->fw_stats;
1160 struct myri10ge_tx_buf *tx = &mgp->tx;
1161 u32 send_done_count;
1162 int i;
1163
1164 /* make sure it is our IRQ, and that the DMA has finished */
1165 if (unlikely(!stats->valid))
1166 return (IRQ_NONE);
1167
1168 /* low bit indicates receives are present, so schedule
1169 * napi poll handler */
1170 if (stats->valid & 1)
1171 netif_rx_schedule(mgp->dev);
1172
1173 if (!mgp->msi_enabled) {
1174 put_be32(0, mgp->irq_deassert);
1175 if (!myri10ge_deassert_wait)
1176 stats->valid = 0;
1177 mb();
1178 } else
1179 stats->valid = 0;
1180
1181 /* Wait for IRQ line to go low, if using INTx */
1182 i = 0;
1183 while (1) {
1184 i++;
1185 /* check for transmit completes and receives */
1186 send_done_count = ntohl(stats->send_done_count);
1187 if (send_done_count != tx->pkt_done)
1188 myri10ge_tx_done(mgp, (int)send_done_count);
1189 if (unlikely(i > myri10ge_max_irq_loops)) {
1190 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1191 mgp->dev->name);
1192 stats->valid = 0;
1193 schedule_work(&mgp->watchdog_work);
1194 }
1195 if (likely(stats->valid == 0))
1196 break;
1197 cpu_relax();
1198 barrier();
1199 }
1200
1201 myri10ge_check_statblock(mgp);
1202
1203 put_be32(htonl(3), mgp->irq_claim + 1);
1204 return (IRQ_HANDLED);
1205 }
1206
1207 static int
1208 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1209 {
1210 cmd->autoneg = AUTONEG_DISABLE;
1211 cmd->speed = SPEED_10000;
1212 cmd->duplex = DUPLEX_FULL;
1213 return 0;
1214 }
1215
1216 static void
1217 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1218 {
1219 struct myri10ge_priv *mgp = netdev_priv(netdev);
1220
1221 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1222 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1223 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1224 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1225 }
1226
1227 static int
1228 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1229 {
1230 struct myri10ge_priv *mgp = netdev_priv(netdev);
1231 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1232 return 0;
1233 }
1234
1235 static int
1236 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1237 {
1238 struct myri10ge_priv *mgp = netdev_priv(netdev);
1239
1240 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1241 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1242 return 0;
1243 }
1244
1245 static void
1246 myri10ge_get_pauseparam(struct net_device *netdev,
1247 struct ethtool_pauseparam *pause)
1248 {
1249 struct myri10ge_priv *mgp = netdev_priv(netdev);
1250
1251 pause->autoneg = 0;
1252 pause->rx_pause = mgp->pause;
1253 pause->tx_pause = mgp->pause;
1254 }
1255
1256 static int
1257 myri10ge_set_pauseparam(struct net_device *netdev,
1258 struct ethtool_pauseparam *pause)
1259 {
1260 struct myri10ge_priv *mgp = netdev_priv(netdev);
1261
1262 if (pause->tx_pause != mgp->pause)
1263 return myri10ge_change_pause(mgp, pause->tx_pause);
1264 if (pause->rx_pause != mgp->pause)
1265 return myri10ge_change_pause(mgp, pause->tx_pause);
1266 if (pause->autoneg != 0)
1267 return -EINVAL;
1268 return 0;
1269 }
1270
1271 static void
1272 myri10ge_get_ringparam(struct net_device *netdev,
1273 struct ethtool_ringparam *ring)
1274 {
1275 struct myri10ge_priv *mgp = netdev_priv(netdev);
1276
1277 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1278 ring->rx_max_pending = mgp->rx_big.mask + 1;
1279 ring->rx_jumbo_max_pending = 0;
1280 ring->tx_max_pending = mgp->rx_small.mask + 1;
1281 ring->rx_mini_pending = ring->rx_mini_max_pending;
1282 ring->rx_pending = ring->rx_max_pending;
1283 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1284 ring->tx_pending = ring->tx_max_pending;
1285 }
1286
1287 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1288 {
1289 struct myri10ge_priv *mgp = netdev_priv(netdev);
1290 if (mgp->csum_flag)
1291 return 1;
1292 else
1293 return 0;
1294 }
1295
1296 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1297 {
1298 struct myri10ge_priv *mgp = netdev_priv(netdev);
1299 if (csum_enabled)
1300 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1301 else
1302 mgp->csum_flag = 0;
1303 return 0;
1304 }
1305
1306 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1307 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1308 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1309 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1310 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1311 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1312 "tx_heartbeat_errors", "tx_window_errors",
1313 /* device-specific stats */
1314 "tx_boundary", "WC", "irq", "MSI",
1315 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1316 "serial_number", "tx_pkt_start", "tx_pkt_done",
1317 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1318 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1319 "link_changes", "link_up", "dropped_link_overflow",
1320 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
1321 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1322 "dropped_no_big_buffer"
1323 };
1324
1325 #define MYRI10GE_NET_STATS_LEN 21
1326 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1327
1328 static void
1329 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1330 {
1331 switch (stringset) {
1332 case ETH_SS_STATS:
1333 memcpy(data, *myri10ge_gstrings_stats,
1334 sizeof(myri10ge_gstrings_stats));
1335 break;
1336 }
1337 }
1338
1339 static int myri10ge_get_stats_count(struct net_device *netdev)
1340 {
1341 return MYRI10GE_STATS_LEN;
1342 }
1343
1344 static void
1345 myri10ge_get_ethtool_stats(struct net_device *netdev,
1346 struct ethtool_stats *stats, u64 * data)
1347 {
1348 struct myri10ge_priv *mgp = netdev_priv(netdev);
1349 int i;
1350
1351 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1352 data[i] = ((unsigned long *)&mgp->stats)[i];
1353
1354 data[i++] = (unsigned int)mgp->tx.boundary;
1355 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1356 data[i++] = (unsigned int)mgp->pdev->irq;
1357 data[i++] = (unsigned int)mgp->msi_enabled;
1358 data[i++] = (unsigned int)mgp->read_dma;
1359 data[i++] = (unsigned int)mgp->write_dma;
1360 data[i++] = (unsigned int)mgp->read_write_dma;
1361 data[i++] = (unsigned int)mgp->serial_number;
1362 data[i++] = (unsigned int)mgp->tx.pkt_start;
1363 data[i++] = (unsigned int)mgp->tx.pkt_done;
1364 data[i++] = (unsigned int)mgp->tx.req;
1365 data[i++] = (unsigned int)mgp->tx.done;
1366 data[i++] = (unsigned int)mgp->rx_small.cnt;
1367 data[i++] = (unsigned int)mgp->rx_big.cnt;
1368 data[i++] = (unsigned int)mgp->wake_queue;
1369 data[i++] = (unsigned int)mgp->stop_queue;
1370 data[i++] = (unsigned int)mgp->watchdog_resets;
1371 data[i++] = (unsigned int)mgp->tx_linearized;
1372 data[i++] = (unsigned int)mgp->link_changes;
1373 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1374 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1375 data[i++] =
1376 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1377 data[i++] =
1378 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1379 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1380 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1381 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1382 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1383 }
1384
1385 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1386 {
1387 struct myri10ge_priv *mgp = netdev_priv(netdev);
1388 mgp->msg_enable = value;
1389 }
1390
1391 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1392 {
1393 struct myri10ge_priv *mgp = netdev_priv(netdev);
1394 return mgp->msg_enable;
1395 }
1396
1397 static const struct ethtool_ops myri10ge_ethtool_ops = {
1398 .get_settings = myri10ge_get_settings,
1399 .get_drvinfo = myri10ge_get_drvinfo,
1400 .get_coalesce = myri10ge_get_coalesce,
1401 .set_coalesce = myri10ge_set_coalesce,
1402 .get_pauseparam = myri10ge_get_pauseparam,
1403 .set_pauseparam = myri10ge_set_pauseparam,
1404 .get_ringparam = myri10ge_get_ringparam,
1405 .get_rx_csum = myri10ge_get_rx_csum,
1406 .set_rx_csum = myri10ge_set_rx_csum,
1407 .get_tx_csum = ethtool_op_get_tx_csum,
1408 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1409 .get_sg = ethtool_op_get_sg,
1410 .set_sg = ethtool_op_set_sg,
1411 #ifdef NETIF_F_TSO
1412 .get_tso = ethtool_op_get_tso,
1413 .set_tso = ethtool_op_set_tso,
1414 #endif
1415 .get_strings = myri10ge_get_strings,
1416 .get_stats_count = myri10ge_get_stats_count,
1417 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1418 .set_msglevel = myri10ge_set_msglevel,
1419 .get_msglevel = myri10ge_get_msglevel
1420 };
1421
1422 static int myri10ge_allocate_rings(struct net_device *dev)
1423 {
1424 struct myri10ge_priv *mgp;
1425 struct myri10ge_cmd cmd;
1426 int tx_ring_size, rx_ring_size;
1427 int tx_ring_entries, rx_ring_entries;
1428 int i, status;
1429 size_t bytes;
1430
1431 mgp = netdev_priv(dev);
1432
1433 /* get ring sizes */
1434
1435 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1436 tx_ring_size = cmd.data0;
1437 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1438 rx_ring_size = cmd.data0;
1439
1440 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1441 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1442 mgp->tx.mask = tx_ring_entries - 1;
1443 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1444
1445 /* allocate the host shadow rings */
1446
1447 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1448 * sizeof(*mgp->tx.req_list);
1449 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1450 if (mgp->tx.req_bytes == NULL)
1451 goto abort_with_nothing;
1452
1453 /* ensure req_list entries are aligned to 8 bytes */
1454 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1455 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1456
1457 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1458 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1459 if (mgp->rx_small.shadow == NULL)
1460 goto abort_with_tx_req_bytes;
1461
1462 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1463 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1464 if (mgp->rx_big.shadow == NULL)
1465 goto abort_with_rx_small_shadow;
1466
1467 /* allocate the host info rings */
1468
1469 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1470 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1471 if (mgp->tx.info == NULL)
1472 goto abort_with_rx_big_shadow;
1473
1474 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1475 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1476 if (mgp->rx_small.info == NULL)
1477 goto abort_with_tx_info;
1478
1479 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1480 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1481 if (mgp->rx_big.info == NULL)
1482 goto abort_with_rx_small_info;
1483
1484 /* Fill the receive rings */
1485 mgp->rx_big.cnt = 0;
1486 mgp->rx_small.cnt = 0;
1487 mgp->rx_big.fill_cnt = 0;
1488 mgp->rx_small.fill_cnt = 0;
1489 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1490 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1491 mgp->rx_small.watchdog_needed = 0;
1492 mgp->rx_big.watchdog_needed = 0;
1493 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1494 mgp->small_bytes + MXGEFW_PAD, 0);
1495
1496 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1497 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1498 dev->name, mgp->rx_small.fill_cnt);
1499 goto abort_with_rx_small_ring;
1500 }
1501
1502 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1503 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1504 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1505 dev->name, mgp->rx_big.fill_cnt);
1506 goto abort_with_rx_big_ring;
1507 }
1508
1509 return 0;
1510
1511 abort_with_rx_big_ring:
1512 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1513 int idx = i & mgp->rx_big.mask;
1514 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1515 mgp->big_bytes);
1516 put_page(mgp->rx_big.info[idx].page);
1517 }
1518
1519 abort_with_rx_small_ring:
1520 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1521 int idx = i & mgp->rx_small.mask;
1522 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1523 mgp->small_bytes + MXGEFW_PAD);
1524 put_page(mgp->rx_small.info[idx].page);
1525 }
1526
1527 kfree(mgp->rx_big.info);
1528
1529 abort_with_rx_small_info:
1530 kfree(mgp->rx_small.info);
1531
1532 abort_with_tx_info:
1533 kfree(mgp->tx.info);
1534
1535 abort_with_rx_big_shadow:
1536 kfree(mgp->rx_big.shadow);
1537
1538 abort_with_rx_small_shadow:
1539 kfree(mgp->rx_small.shadow);
1540
1541 abort_with_tx_req_bytes:
1542 kfree(mgp->tx.req_bytes);
1543 mgp->tx.req_bytes = NULL;
1544 mgp->tx.req_list = NULL;
1545
1546 abort_with_nothing:
1547 return status;
1548 }
1549
1550 static void myri10ge_free_rings(struct net_device *dev)
1551 {
1552 struct myri10ge_priv *mgp;
1553 struct sk_buff *skb;
1554 struct myri10ge_tx_buf *tx;
1555 int i, len, idx;
1556
1557 mgp = netdev_priv(dev);
1558
1559 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1560 idx = i & mgp->rx_big.mask;
1561 if (i == mgp->rx_big.fill_cnt - 1)
1562 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1563 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1564 mgp->big_bytes);
1565 put_page(mgp->rx_big.info[idx].page);
1566 }
1567
1568 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1569 idx = i & mgp->rx_small.mask;
1570 if (i == mgp->rx_small.fill_cnt - 1)
1571 mgp->rx_small.info[idx].page_offset =
1572 MYRI10GE_ALLOC_SIZE;
1573 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1574 mgp->small_bytes + MXGEFW_PAD);
1575 put_page(mgp->rx_small.info[idx].page);
1576 }
1577 tx = &mgp->tx;
1578 while (tx->done != tx->req) {
1579 idx = tx->done & tx->mask;
1580 skb = tx->info[idx].skb;
1581
1582 /* Mark as free */
1583 tx->info[idx].skb = NULL;
1584 tx->done++;
1585 len = pci_unmap_len(&tx->info[idx], len);
1586 pci_unmap_len_set(&tx->info[idx], len, 0);
1587 if (skb) {
1588 mgp->stats.tx_dropped++;
1589 dev_kfree_skb_any(skb);
1590 if (len)
1591 pci_unmap_single(mgp->pdev,
1592 pci_unmap_addr(&tx->info[idx],
1593 bus), len,
1594 PCI_DMA_TODEVICE);
1595 } else {
1596 if (len)
1597 pci_unmap_page(mgp->pdev,
1598 pci_unmap_addr(&tx->info[idx],
1599 bus), len,
1600 PCI_DMA_TODEVICE);
1601 }
1602 }
1603 kfree(mgp->rx_big.info);
1604
1605 kfree(mgp->rx_small.info);
1606
1607 kfree(mgp->tx.info);
1608
1609 kfree(mgp->rx_big.shadow);
1610
1611 kfree(mgp->rx_small.shadow);
1612
1613 kfree(mgp->tx.req_bytes);
1614 mgp->tx.req_bytes = NULL;
1615 mgp->tx.req_list = NULL;
1616 }
1617
1618 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1619 {
1620 struct pci_dev *pdev = mgp->pdev;
1621 int status;
1622
1623 if (myri10ge_msi) {
1624 status = pci_enable_msi(pdev);
1625 if (status != 0)
1626 dev_err(&pdev->dev,
1627 "Error %d setting up MSI; falling back to xPIC\n",
1628 status);
1629 else
1630 mgp->msi_enabled = 1;
1631 } else {
1632 mgp->msi_enabled = 0;
1633 }
1634 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1635 mgp->dev->name, mgp);
1636 if (status != 0) {
1637 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1638 if (mgp->msi_enabled)
1639 pci_disable_msi(pdev);
1640 }
1641 return status;
1642 }
1643
1644 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1645 {
1646 struct pci_dev *pdev = mgp->pdev;
1647
1648 free_irq(pdev->irq, mgp);
1649 if (mgp->msi_enabled)
1650 pci_disable_msi(pdev);
1651 }
1652
1653 static int myri10ge_open(struct net_device *dev)
1654 {
1655 struct myri10ge_priv *mgp;
1656 struct myri10ge_cmd cmd;
1657 int status, big_pow2;
1658
1659 mgp = netdev_priv(dev);
1660
1661 if (mgp->running != MYRI10GE_ETH_STOPPED)
1662 return -EBUSY;
1663
1664 mgp->running = MYRI10GE_ETH_STARTING;
1665 status = myri10ge_reset(mgp);
1666 if (status != 0) {
1667 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1668 goto abort_with_nothing;
1669 }
1670
1671 status = myri10ge_request_irq(mgp);
1672 if (status != 0)
1673 goto abort_with_nothing;
1674
1675 /* decide what small buffer size to use. For good TCP rx
1676 * performance, it is important to not receive 1514 byte
1677 * frames into jumbo buffers, as it confuses the socket buffer
1678 * accounting code, leading to drops and erratic performance.
1679 */
1680
1681 if (dev->mtu <= ETH_DATA_LEN)
1682 /* enough for a TCP header */
1683 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1684 ? (128 - MXGEFW_PAD)
1685 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1686 else
1687 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1688 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1689
1690 /* Override the small buffer size? */
1691 if (myri10ge_small_bytes > 0)
1692 mgp->small_bytes = myri10ge_small_bytes;
1693
1694 /* get the lanai pointers to the send and receive rings */
1695
1696 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1697 mgp->tx.lanai =
1698 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1699
1700 status |=
1701 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1702 mgp->rx_small.lanai =
1703 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1704
1705 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1706 mgp->rx_big.lanai =
1707 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1708
1709 if (status != 0) {
1710 printk(KERN_ERR
1711 "myri10ge: %s: failed to get ring sizes or locations\n",
1712 dev->name);
1713 mgp->running = MYRI10GE_ETH_STOPPED;
1714 goto abort_with_irq;
1715 }
1716
1717 if (mgp->mtrr >= 0) {
1718 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1719 mgp->rx_small.wc_fifo =
1720 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1721 mgp->rx_big.wc_fifo =
1722 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1723 } else {
1724 mgp->tx.wc_fifo = NULL;
1725 mgp->rx_small.wc_fifo = NULL;
1726 mgp->rx_big.wc_fifo = NULL;
1727 }
1728
1729 /* Firmware needs the big buff size as a power of 2. Lie and
1730 * tell him the buffer is larger, because we only use 1
1731 * buffer/pkt, and the mtu will prevent overruns.
1732 */
1733 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1734 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1735 while ((big_pow2 & (big_pow2 - 1)) != 0)
1736 big_pow2++;
1737 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1738 } else {
1739 big_pow2 = MYRI10GE_ALLOC_SIZE;
1740 mgp->big_bytes = big_pow2;
1741 }
1742
1743 status = myri10ge_allocate_rings(dev);
1744 if (status != 0)
1745 goto abort_with_irq;
1746
1747 /* now give firmware buffers sizes, and MTU */
1748 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1749 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1750 cmd.data0 = mgp->small_bytes;
1751 status |=
1752 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1753 cmd.data0 = big_pow2;
1754 status |=
1755 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1756 if (status) {
1757 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1758 dev->name);
1759 goto abort_with_rings;
1760 }
1761
1762 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1763 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1764 cmd.data2 = sizeof(struct mcp_irq_data);
1765 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1766 if (status == -ENOSYS) {
1767 dma_addr_t bus = mgp->fw_stats_bus;
1768 bus += offsetof(struct mcp_irq_data, send_done_count);
1769 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1770 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1771 status = myri10ge_send_cmd(mgp,
1772 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1773 &cmd, 0);
1774 /* Firmware cannot support multicast without STATS_DMA_V2 */
1775 mgp->fw_multicast_support = 0;
1776 } else {
1777 mgp->fw_multicast_support = 1;
1778 }
1779 if (status) {
1780 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1781 dev->name);
1782 goto abort_with_rings;
1783 }
1784
1785 mgp->link_state = htonl(~0U);
1786 mgp->rdma_tags_available = 15;
1787
1788 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1789
1790 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1791 if (status) {
1792 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1793 dev->name);
1794 goto abort_with_rings;
1795 }
1796
1797 mgp->wake_queue = 0;
1798 mgp->stop_queue = 0;
1799 mgp->running = MYRI10GE_ETH_RUNNING;
1800 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1801 add_timer(&mgp->watchdog_timer);
1802 netif_wake_queue(dev);
1803 return 0;
1804
1805 abort_with_rings:
1806 myri10ge_free_rings(dev);
1807
1808 abort_with_irq:
1809 myri10ge_free_irq(mgp);
1810
1811 abort_with_nothing:
1812 mgp->running = MYRI10GE_ETH_STOPPED;
1813 return -ENOMEM;
1814 }
1815
1816 static int myri10ge_close(struct net_device *dev)
1817 {
1818 struct myri10ge_priv *mgp;
1819 struct myri10ge_cmd cmd;
1820 int status, old_down_cnt;
1821
1822 mgp = netdev_priv(dev);
1823
1824 if (mgp->running != MYRI10GE_ETH_RUNNING)
1825 return 0;
1826
1827 if (mgp->tx.req_bytes == NULL)
1828 return 0;
1829
1830 del_timer_sync(&mgp->watchdog_timer);
1831 mgp->running = MYRI10GE_ETH_STOPPING;
1832 netif_poll_disable(mgp->dev);
1833 netif_carrier_off(dev);
1834 netif_stop_queue(dev);
1835 old_down_cnt = mgp->down_cnt;
1836 mb();
1837 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1838 if (status)
1839 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1840 dev->name);
1841
1842 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1843 if (old_down_cnt == mgp->down_cnt)
1844 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1845
1846 netif_tx_disable(dev);
1847 myri10ge_free_irq(mgp);
1848 myri10ge_free_rings(dev);
1849
1850 mgp->running = MYRI10GE_ETH_STOPPED;
1851 return 0;
1852 }
1853
1854 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1855 * backwards one at a time and handle ring wraps */
1856
1857 static inline void
1858 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1859 struct mcp_kreq_ether_send *src, int cnt)
1860 {
1861 int idx, starting_slot;
1862 starting_slot = tx->req;
1863 while (cnt > 1) {
1864 cnt--;
1865 idx = (starting_slot + cnt) & tx->mask;
1866 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1867 mb();
1868 }
1869 }
1870
1871 /*
1872 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1873 * at most 32 bytes at a time, so as to avoid involving the software
1874 * pio handler in the nic. We re-write the first segment's flags
1875 * to mark them valid only after writing the entire chain.
1876 */
1877
1878 static inline void
1879 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1880 int cnt)
1881 {
1882 int idx, i;
1883 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1884 struct mcp_kreq_ether_send *srcp;
1885 u8 last_flags;
1886
1887 idx = tx->req & tx->mask;
1888
1889 last_flags = src->flags;
1890 src->flags = 0;
1891 mb();
1892 dst = dstp = &tx->lanai[idx];
1893 srcp = src;
1894
1895 if ((idx + cnt) < tx->mask) {
1896 for (i = 0; i < (cnt - 1); i += 2) {
1897 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1898 mb(); /* force write every 32 bytes */
1899 srcp += 2;
1900 dstp += 2;
1901 }
1902 } else {
1903 /* submit all but the first request, and ensure
1904 * that it is submitted below */
1905 myri10ge_submit_req_backwards(tx, src, cnt);
1906 i = 0;
1907 }
1908 if (i < cnt) {
1909 /* submit the first request */
1910 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1911 mb(); /* barrier before setting valid flag */
1912 }
1913
1914 /* re-write the last 32-bits with the valid flags */
1915 src->flags = last_flags;
1916 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1917 tx->req += cnt;
1918 mb();
1919 }
1920
1921 static inline void
1922 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1923 struct mcp_kreq_ether_send *src, int cnt)
1924 {
1925 tx->req += cnt;
1926 mb();
1927 while (cnt >= 4) {
1928 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1929 mb();
1930 src += 4;
1931 cnt -= 4;
1932 }
1933 if (cnt > 0) {
1934 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1935 * needs to be so that we don't overrun it */
1936 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1937 src, 64);
1938 mb();
1939 }
1940 }
1941
1942 /*
1943 * Transmit a packet. We need to split the packet so that a single
1944 * segment does not cross myri10ge->tx.boundary, so this makes segment
1945 * counting tricky. So rather than try to count segments up front, we
1946 * just give up if there are too few segments to hold a reasonably
1947 * fragmented packet currently available. If we run
1948 * out of segments while preparing a packet for DMA, we just linearize
1949 * it and try again.
1950 */
1951
1952 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1953 {
1954 struct myri10ge_priv *mgp = netdev_priv(dev);
1955 struct mcp_kreq_ether_send *req;
1956 struct myri10ge_tx_buf *tx = &mgp->tx;
1957 struct skb_frag_struct *frag;
1958 dma_addr_t bus;
1959 u32 low;
1960 __be32 high_swapped;
1961 unsigned int len;
1962 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1963 u16 pseudo_hdr_offset, cksum_offset;
1964 int cum_len, seglen, boundary, rdma_count;
1965 u8 flags, odd_flag;
1966
1967 again:
1968 req = tx->req_list;
1969 avail = tx->mask - 1 - (tx->req - tx->done);
1970
1971 mss = 0;
1972 max_segments = MXGEFW_MAX_SEND_DESC;
1973
1974 #ifdef NETIF_F_TSO
1975 if (skb->len > (dev->mtu + ETH_HLEN)) {
1976 mss = skb_shinfo(skb)->gso_size;
1977 if (mss != 0)
1978 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1979 }
1980 #endif /*NETIF_F_TSO */
1981
1982 if ((unlikely(avail < max_segments))) {
1983 /* we are out of transmit resources */
1984 mgp->stop_queue++;
1985 netif_stop_queue(dev);
1986 return 1;
1987 }
1988
1989 /* Setup checksum offloading, if needed */
1990 cksum_offset = 0;
1991 pseudo_hdr_offset = 0;
1992 odd_flag = 0;
1993 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1994 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1995 cksum_offset = (skb->h.raw - skb->data);
1996 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
1997 /* If the headers are excessively large, then we must
1998 * fall back to a software checksum */
1999 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2000 if (skb_checksum_help(skb))
2001 goto drop;
2002 cksum_offset = 0;
2003 pseudo_hdr_offset = 0;
2004 } else {
2005 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2006 flags |= MXGEFW_FLAGS_CKSUM;
2007 }
2008 }
2009
2010 cum_len = 0;
2011
2012 #ifdef NETIF_F_TSO
2013 if (mss) { /* TSO */
2014 /* this removes any CKSUM flag from before */
2015 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2016
2017 /* negative cum_len signifies to the
2018 * send loop that we are still in the
2019 * header portion of the TSO packet.
2020 * TSO header must be at most 134 bytes long */
2021 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2022
2023 /* for TSO, pseudo_hdr_offset holds mss.
2024 * The firmware figures out where to put
2025 * the checksum by parsing the header. */
2026 pseudo_hdr_offset = mss;
2027 } else
2028 #endif /*NETIF_F_TSO */
2029 /* Mark small packets, and pad out tiny packets */
2030 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2031 flags |= MXGEFW_FLAGS_SMALL;
2032
2033 /* pad frames to at least ETH_ZLEN bytes */
2034 if (unlikely(skb->len < ETH_ZLEN)) {
2035 if (skb_padto(skb, ETH_ZLEN)) {
2036 /* The packet is gone, so we must
2037 * return 0 */
2038 mgp->stats.tx_dropped += 1;
2039 return 0;
2040 }
2041 /* adjust the len to account for the zero pad
2042 * so that the nic can know how long it is */
2043 skb->len = ETH_ZLEN;
2044 }
2045 }
2046
2047 /* map the skb for DMA */
2048 len = skb->len - skb->data_len;
2049 idx = tx->req & tx->mask;
2050 tx->info[idx].skb = skb;
2051 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2052 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2053 pci_unmap_len_set(&tx->info[idx], len, len);
2054
2055 frag_cnt = skb_shinfo(skb)->nr_frags;
2056 frag_idx = 0;
2057 count = 0;
2058 rdma_count = 0;
2059
2060 /* "rdma_count" is the number of RDMAs belonging to the
2061 * current packet BEFORE the current send request. For
2062 * non-TSO packets, this is equal to "count".
2063 * For TSO packets, rdma_count needs to be reset
2064 * to 0 after a segment cut.
2065 *
2066 * The rdma_count field of the send request is
2067 * the number of RDMAs of the packet starting at
2068 * that request. For TSO send requests with one ore more cuts
2069 * in the middle, this is the number of RDMAs starting
2070 * after the last cut in the request. All previous
2071 * segments before the last cut implicitly have 1 RDMA.
2072 *
2073 * Since the number of RDMAs is not known beforehand,
2074 * it must be filled-in retroactively - after each
2075 * segmentation cut or at the end of the entire packet.
2076 */
2077
2078 while (1) {
2079 /* Break the SKB or Fragment up into pieces which
2080 * do not cross mgp->tx.boundary */
2081 low = MYRI10GE_LOWPART_TO_U32(bus);
2082 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2083 while (len) {
2084 u8 flags_next;
2085 int cum_len_next;
2086
2087 if (unlikely(count == max_segments))
2088 goto abort_linearize;
2089
2090 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2091 seglen = boundary - low;
2092 if (seglen > len)
2093 seglen = len;
2094 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2095 cum_len_next = cum_len + seglen;
2096 #ifdef NETIF_F_TSO
2097 if (mss) { /* TSO */
2098 (req - rdma_count)->rdma_count = rdma_count + 1;
2099
2100 if (likely(cum_len >= 0)) { /* payload */
2101 int next_is_first, chop;
2102
2103 chop = (cum_len_next > mss);
2104 cum_len_next = cum_len_next % mss;
2105 next_is_first = (cum_len_next == 0);
2106 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2107 flags_next |= next_is_first *
2108 MXGEFW_FLAGS_FIRST;
2109 rdma_count |= -(chop | next_is_first);
2110 rdma_count += chop & !next_is_first;
2111 } else if (likely(cum_len_next >= 0)) { /* header ends */
2112 int small;
2113
2114 rdma_count = -1;
2115 cum_len_next = 0;
2116 seglen = -cum_len;
2117 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2118 flags_next = MXGEFW_FLAGS_TSO_PLD |
2119 MXGEFW_FLAGS_FIRST |
2120 (small * MXGEFW_FLAGS_SMALL);
2121 }
2122 }
2123 #endif /* NETIF_F_TSO */
2124 req->addr_high = high_swapped;
2125 req->addr_low = htonl(low);
2126 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2127 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2128 req->rdma_count = 1;
2129 req->length = htons(seglen);
2130 req->cksum_offset = cksum_offset;
2131 req->flags = flags | ((cum_len & 1) * odd_flag);
2132
2133 low += seglen;
2134 len -= seglen;
2135 cum_len = cum_len_next;
2136 flags = flags_next;
2137 req++;
2138 count++;
2139 rdma_count++;
2140 if (unlikely(cksum_offset > seglen))
2141 cksum_offset -= seglen;
2142 else
2143 cksum_offset = 0;
2144 }
2145 if (frag_idx == frag_cnt)
2146 break;
2147
2148 /* map next fragment for DMA */
2149 idx = (count + tx->req) & tx->mask;
2150 frag = &skb_shinfo(skb)->frags[frag_idx];
2151 frag_idx++;
2152 len = frag->size;
2153 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2154 len, PCI_DMA_TODEVICE);
2155 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2156 pci_unmap_len_set(&tx->info[idx], len, len);
2157 }
2158
2159 (req - rdma_count)->rdma_count = rdma_count;
2160 #ifdef NETIF_F_TSO
2161 if (mss)
2162 do {
2163 req--;
2164 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2165 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2166 MXGEFW_FLAGS_FIRST)));
2167 #endif
2168 idx = ((count - 1) + tx->req) & tx->mask;
2169 tx->info[idx].last = 1;
2170 if (tx->wc_fifo == NULL)
2171 myri10ge_submit_req(tx, tx->req_list, count);
2172 else
2173 myri10ge_submit_req_wc(tx, tx->req_list, count);
2174 tx->pkt_start++;
2175 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2176 mgp->stop_queue++;
2177 netif_stop_queue(dev);
2178 }
2179 dev->trans_start = jiffies;
2180 return 0;
2181
2182 abort_linearize:
2183 /* Free any DMA resources we've alloced and clear out the skb
2184 * slot so as to not trip up assertions, and to avoid a
2185 * double-free if linearizing fails */
2186
2187 last_idx = (idx + 1) & tx->mask;
2188 idx = tx->req & tx->mask;
2189 tx->info[idx].skb = NULL;
2190 do {
2191 len = pci_unmap_len(&tx->info[idx], len);
2192 if (len) {
2193 if (tx->info[idx].skb != NULL)
2194 pci_unmap_single(mgp->pdev,
2195 pci_unmap_addr(&tx->info[idx],
2196 bus), len,
2197 PCI_DMA_TODEVICE);
2198 else
2199 pci_unmap_page(mgp->pdev,
2200 pci_unmap_addr(&tx->info[idx],
2201 bus), len,
2202 PCI_DMA_TODEVICE);
2203 pci_unmap_len_set(&tx->info[idx], len, 0);
2204 tx->info[idx].skb = NULL;
2205 }
2206 idx = (idx + 1) & tx->mask;
2207 } while (idx != last_idx);
2208 if (skb_is_gso(skb)) {
2209 printk(KERN_ERR
2210 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2211 mgp->dev->name);
2212 goto drop;
2213 }
2214
2215 if (skb_linearize(skb))
2216 goto drop;
2217
2218 mgp->tx_linearized++;
2219 goto again;
2220
2221 drop:
2222 dev_kfree_skb_any(skb);
2223 mgp->stats.tx_dropped += 1;
2224 return 0;
2225
2226 }
2227
2228 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2229 {
2230 struct myri10ge_priv *mgp = netdev_priv(dev);
2231 return &mgp->stats;
2232 }
2233
2234 static void myri10ge_set_multicast_list(struct net_device *dev)
2235 {
2236 struct myri10ge_cmd cmd;
2237 struct myri10ge_priv *mgp;
2238 struct dev_mc_list *mc_list;
2239 __be32 data[2] = { 0, 0 };
2240 int err;
2241
2242 mgp = netdev_priv(dev);
2243 /* can be called from atomic contexts,
2244 * pass 1 to force atomicity in myri10ge_send_cmd() */
2245 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2246
2247 /* This firmware is known to not support multicast */
2248 if (!mgp->fw_multicast_support)
2249 return;
2250
2251 /* Disable multicast filtering */
2252
2253 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2254 if (err != 0) {
2255 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2256 " error status: %d\n", dev->name, err);
2257 goto abort;
2258 }
2259
2260 if (dev->flags & IFF_ALLMULTI) {
2261 /* request to disable multicast filtering, so quit here */
2262 return;
2263 }
2264
2265 /* Flush the filters */
2266
2267 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2268 &cmd, 1);
2269 if (err != 0) {
2270 printk(KERN_ERR
2271 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2272 ", error status: %d\n", dev->name, err);
2273 goto abort;
2274 }
2275
2276 /* Walk the multicast list, and add each address */
2277 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2278 memcpy(data, &mc_list->dmi_addr, 6);
2279 cmd.data0 = ntohl(data[0]);
2280 cmd.data1 = ntohl(data[1]);
2281 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2282 &cmd, 1);
2283
2284 if (err != 0) {
2285 printk(KERN_ERR "myri10ge: %s: Failed "
2286 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2287 "%d\t", dev->name, err);
2288 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2289 ((unsigned char *)&mc_list->dmi_addr)[0],
2290 ((unsigned char *)&mc_list->dmi_addr)[1],
2291 ((unsigned char *)&mc_list->dmi_addr)[2],
2292 ((unsigned char *)&mc_list->dmi_addr)[3],
2293 ((unsigned char *)&mc_list->dmi_addr)[4],
2294 ((unsigned char *)&mc_list->dmi_addr)[5]
2295 );
2296 goto abort;
2297 }
2298 }
2299 /* Enable multicast filtering */
2300 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2301 if (err != 0) {
2302 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2303 "error status: %d\n", dev->name, err);
2304 goto abort;
2305 }
2306
2307 return;
2308
2309 abort:
2310 return;
2311 }
2312
2313 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2314 {
2315 struct sockaddr *sa = addr;
2316 struct myri10ge_priv *mgp = netdev_priv(dev);
2317 int status;
2318
2319 if (!is_valid_ether_addr(sa->sa_data))
2320 return -EADDRNOTAVAIL;
2321
2322 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2323 if (status != 0) {
2324 printk(KERN_ERR
2325 "myri10ge: %s: changing mac address failed with %d\n",
2326 dev->name, status);
2327 return status;
2328 }
2329
2330 /* change the dev structure */
2331 memcpy(dev->dev_addr, sa->sa_data, 6);
2332 return 0;
2333 }
2334
2335 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2336 {
2337 struct myri10ge_priv *mgp = netdev_priv(dev);
2338 int error = 0;
2339
2340 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2341 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2342 dev->name, new_mtu);
2343 return -EINVAL;
2344 }
2345 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2346 dev->name, dev->mtu, new_mtu);
2347 if (mgp->running) {
2348 /* if we change the mtu on an active device, we must
2349 * reset the device so the firmware sees the change */
2350 myri10ge_close(dev);
2351 dev->mtu = new_mtu;
2352 myri10ge_open(dev);
2353 } else
2354 dev->mtu = new_mtu;
2355
2356 return error;
2357 }
2358
2359 /*
2360 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2361 * Only do it if the bridge is a root port since we don't want to disturb
2362 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2363 */
2364
2365 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2366 {
2367 struct pci_dev *bridge = mgp->pdev->bus->self;
2368 struct device *dev = &mgp->pdev->dev;
2369 unsigned cap;
2370 unsigned err_cap;
2371 u16 val;
2372 u8 ext_type;
2373 int ret;
2374
2375 if (!myri10ge_ecrc_enable || !bridge)
2376 return;
2377
2378 /* check that the bridge is a root port */
2379 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2380 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2381 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2382 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2383 if (myri10ge_ecrc_enable > 1) {
2384 struct pci_dev *old_bridge = bridge;
2385
2386 /* Walk the hierarchy up to the root port
2387 * where ECRC has to be enabled */
2388 do {
2389 bridge = bridge->bus->self;
2390 if (!bridge) {
2391 dev_err(dev,
2392 "Failed to find root port"
2393 " to force ECRC\n");
2394 return;
2395 }
2396 cap =
2397 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2398 pci_read_config_word(bridge,
2399 cap + PCI_CAP_FLAGS, &val);
2400 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2401 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2402
2403 dev_info(dev,
2404 "Forcing ECRC on non-root port %s"
2405 " (enabling on root port %s)\n",
2406 pci_name(old_bridge), pci_name(bridge));
2407 } else {
2408 dev_err(dev,
2409 "Not enabling ECRC on non-root port %s\n",
2410 pci_name(bridge));
2411 return;
2412 }
2413 }
2414
2415 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2416 if (!cap)
2417 return;
2418
2419 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2420 if (ret) {
2421 dev_err(dev, "failed reading ext-conf-space of %s\n",
2422 pci_name(bridge));
2423 dev_err(dev, "\t pci=nommconf in use? "
2424 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2425 return;
2426 }
2427 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2428 return;
2429
2430 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2431 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2432 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2433 mgp->tx.boundary = 4096;
2434 mgp->fw_name = myri10ge_fw_aligned;
2435 }
2436
2437 /*
2438 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2439 * when the PCI-E Completion packets are aligned on an 8-byte
2440 * boundary. Some PCI-E chip sets always align Completion packets; on
2441 * the ones that do not, the alignment can be enforced by enabling
2442 * ECRC generation (if supported).
2443 *
2444 * When PCI-E Completion packets are not aligned, it is actually more
2445 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2446 *
2447 * If the driver can neither enable ECRC nor verify that it has
2448 * already been enabled, then it must use a firmware image which works
2449 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2450 * should also ensure that it never gives the device a Read-DMA which is
2451 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2452 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2453 * firmware image, and set tx.boundary to 4KB.
2454 */
2455
2456 #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2457 #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2458
2459 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2460 {
2461 struct pci_dev *bridge = mgp->pdev->bus->self;
2462
2463 mgp->tx.boundary = 2048;
2464 mgp->fw_name = myri10ge_fw_unaligned;
2465
2466 if (myri10ge_force_firmware == 0) {
2467 int link_width, exp_cap;
2468 u16 lnk;
2469
2470 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2471 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2472 link_width = (lnk >> 4) & 0x3f;
2473
2474 myri10ge_enable_ecrc(mgp);
2475
2476 /* Check to see if Link is less than 8 or if the
2477 * upstream bridge is known to provide aligned
2478 * completions */
2479 if (link_width < 8) {
2480 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2481 link_width);
2482 mgp->tx.boundary = 4096;
2483 mgp->fw_name = myri10ge_fw_aligned;
2484 } else if (bridge &&
2485 /* ServerWorks HT2000/HT1000 */
2486 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2487 && bridge->device ==
2488 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2489 /* All Intel E5000 PCIE ports */
2490 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2491 && bridge->device >=
2492 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2493 && bridge->device <=
2494 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
2495 dev_info(&mgp->pdev->dev,
2496 "Assuming aligned completions (0x%x:0x%x)\n",
2497 bridge->vendor, bridge->device);
2498 mgp->tx.boundary = 4096;
2499 mgp->fw_name = myri10ge_fw_aligned;
2500 }
2501 } else {
2502 if (myri10ge_force_firmware == 1) {
2503 dev_info(&mgp->pdev->dev,
2504 "Assuming aligned completions (forced)\n");
2505 mgp->tx.boundary = 4096;
2506 mgp->fw_name = myri10ge_fw_aligned;
2507 } else {
2508 dev_info(&mgp->pdev->dev,
2509 "Assuming unaligned completions (forced)\n");
2510 mgp->tx.boundary = 2048;
2511 mgp->fw_name = myri10ge_fw_unaligned;
2512 }
2513 }
2514 if (myri10ge_fw_name != NULL) {
2515 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2516 myri10ge_fw_name);
2517 mgp->fw_name = myri10ge_fw_name;
2518 }
2519 }
2520
2521 #ifdef CONFIG_PM
2522
2523 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2524 {
2525 struct myri10ge_priv *mgp;
2526 struct net_device *netdev;
2527
2528 mgp = pci_get_drvdata(pdev);
2529 if (mgp == NULL)
2530 return -EINVAL;
2531 netdev = mgp->dev;
2532
2533 netif_device_detach(netdev);
2534 if (netif_running(netdev)) {
2535 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2536 rtnl_lock();
2537 myri10ge_close(netdev);
2538 rtnl_unlock();
2539 }
2540 myri10ge_dummy_rdma(mgp, 0);
2541 pci_save_state(pdev);
2542 pci_disable_device(pdev);
2543
2544 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2545 }
2546
2547 static int myri10ge_resume(struct pci_dev *pdev)
2548 {
2549 struct myri10ge_priv *mgp;
2550 struct net_device *netdev;
2551 int status;
2552 u16 vendor;
2553
2554 mgp = pci_get_drvdata(pdev);
2555 if (mgp == NULL)
2556 return -EINVAL;
2557 netdev = mgp->dev;
2558 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2559 msleep(5); /* give card time to respond */
2560 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2561 if (vendor == 0xffff) {
2562 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2563 mgp->dev->name);
2564 return -EIO;
2565 }
2566
2567 status = pci_restore_state(pdev);
2568 if (status)
2569 return status;
2570
2571 status = pci_enable_device(pdev);
2572 if (status) {
2573 dev_err(&pdev->dev, "failed to enable device\n");
2574 return status;
2575 }
2576
2577 pci_set_master(pdev);
2578
2579 myri10ge_reset(mgp);
2580 myri10ge_dummy_rdma(mgp, 1);
2581
2582 /* Save configuration space to be restored if the
2583 * nic resets due to a parity error */
2584 pci_save_state(pdev);
2585
2586 if (netif_running(netdev)) {
2587 rtnl_lock();
2588 status = myri10ge_open(netdev);
2589 rtnl_unlock();
2590 if (status != 0)
2591 goto abort_with_enabled;
2592
2593 }
2594 netif_device_attach(netdev);
2595
2596 return 0;
2597
2598 abort_with_enabled:
2599 pci_disable_device(pdev);
2600 return -EIO;
2601
2602 }
2603
2604 #endif /* CONFIG_PM */
2605
2606 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2607 {
2608 struct pci_dev *pdev = mgp->pdev;
2609 int vs = mgp->vendor_specific_offset;
2610 u32 reboot;
2611
2612 /*enter read32 mode */
2613 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2614
2615 /*read REBOOT_STATUS (0xfffffff0) */
2616 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2617 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2618 return reboot;
2619 }
2620
2621 /*
2622 * This watchdog is used to check whether the board has suffered
2623 * from a parity error and needs to be recovered.
2624 */
2625 static void myri10ge_watchdog(struct work_struct *work)
2626 {
2627 struct myri10ge_priv *mgp =
2628 container_of(work, struct myri10ge_priv, watchdog_work);
2629 u32 reboot;
2630 int status;
2631 u16 cmd, vendor;
2632
2633 mgp->watchdog_resets++;
2634 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2635 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2636 /* Bus master DMA disabled? Check to see
2637 * if the card rebooted due to a parity error
2638 * For now, just report it */
2639 reboot = myri10ge_read_reboot(mgp);
2640 printk(KERN_ERR
2641 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2642 mgp->dev->name, reboot);
2643 /*
2644 * A rebooted nic will come back with config space as
2645 * it was after power was applied to PCIe bus.
2646 * Attempt to restore config space which was saved
2647 * when the driver was loaded, or the last time the
2648 * nic was resumed from power saving mode.
2649 */
2650 pci_restore_state(mgp->pdev);
2651
2652 /* save state again for accounting reasons */
2653 pci_save_state(mgp->pdev);
2654
2655 } else {
2656 /* if we get back -1's from our slot, perhaps somebody
2657 * powered off our card. Don't try to reset it in
2658 * this case */
2659 if (cmd == 0xffff) {
2660 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2661 if (vendor == 0xffff) {
2662 printk(KERN_ERR
2663 "myri10ge: %s: device disappeared!\n",
2664 mgp->dev->name);
2665 return;
2666 }
2667 }
2668 /* Perhaps it is a software error. Try to reset */
2669
2670 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2671 mgp->dev->name);
2672 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2673 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2674 mgp->tx.pkt_start, mgp->tx.pkt_done,
2675 (int)ntohl(mgp->fw_stats->send_done_count));
2676 msleep(2000);
2677 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2678 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2679 mgp->tx.pkt_start, mgp->tx.pkt_done,
2680 (int)ntohl(mgp->fw_stats->send_done_count));
2681 }
2682 rtnl_lock();
2683 myri10ge_close(mgp->dev);
2684 status = myri10ge_load_firmware(mgp);
2685 if (status != 0)
2686 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2687 mgp->dev->name);
2688 else
2689 myri10ge_open(mgp->dev);
2690 rtnl_unlock();
2691 }
2692
2693 /*
2694 * We use our own timer routine rather than relying upon
2695 * netdev->tx_timeout because we have a very large hardware transmit
2696 * queue. Due to the large queue, the netdev->tx_timeout function
2697 * cannot detect a NIC with a parity error in a timely fashion if the
2698 * NIC is lightly loaded.
2699 */
2700 static void myri10ge_watchdog_timer(unsigned long arg)
2701 {
2702 struct myri10ge_priv *mgp;
2703
2704 mgp = (struct myri10ge_priv *)arg;
2705
2706 if (mgp->rx_small.watchdog_needed) {
2707 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2708 mgp->small_bytes + MXGEFW_PAD, 1);
2709 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2710 myri10ge_fill_thresh)
2711 mgp->rx_small.watchdog_needed = 0;
2712 }
2713 if (mgp->rx_big.watchdog_needed) {
2714 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2715 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2716 myri10ge_fill_thresh)
2717 mgp->rx_big.watchdog_needed = 0;
2718 }
2719
2720 if (mgp->tx.req != mgp->tx.done &&
2721 mgp->tx.done == mgp->watchdog_tx_done &&
2722 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2723 /* nic seems like it might be stuck.. */
2724 schedule_work(&mgp->watchdog_work);
2725 else
2726 /* rearm timer */
2727 mod_timer(&mgp->watchdog_timer,
2728 jiffies + myri10ge_watchdog_timeout * HZ);
2729
2730 mgp->watchdog_tx_done = mgp->tx.done;
2731 mgp->watchdog_tx_req = mgp->tx.req;
2732 }
2733
2734 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2735 {
2736 struct net_device *netdev;
2737 struct myri10ge_priv *mgp;
2738 struct device *dev = &pdev->dev;
2739 size_t bytes;
2740 int i;
2741 int status = -ENXIO;
2742 int cap;
2743 int dac_enabled;
2744 u16 val;
2745
2746 netdev = alloc_etherdev(sizeof(*mgp));
2747 if (netdev == NULL) {
2748 dev_err(dev, "Could not allocate ethernet device\n");
2749 return -ENOMEM;
2750 }
2751
2752 mgp = netdev_priv(netdev);
2753 memset(mgp, 0, sizeof(*mgp));
2754 mgp->dev = netdev;
2755 mgp->pdev = pdev;
2756 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2757 mgp->pause = myri10ge_flow_control;
2758 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2759 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2760 init_waitqueue_head(&mgp->down_wq);
2761
2762 if (pci_enable_device(pdev)) {
2763 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2764 status = -ENODEV;
2765 goto abort_with_netdev;
2766 }
2767 myri10ge_select_firmware(mgp);
2768
2769 /* Find the vendor-specific cap so we can check
2770 * the reboot register later on */
2771 mgp->vendor_specific_offset
2772 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2773
2774 /* Set our max read request to 4KB */
2775 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2776 if (cap < 64) {
2777 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2778 goto abort_with_netdev;
2779 }
2780 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2781 if (status != 0) {
2782 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2783 status);
2784 goto abort_with_netdev;
2785 }
2786 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2787 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2788 if (status != 0) {
2789 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2790 status);
2791 goto abort_with_netdev;
2792 }
2793
2794 pci_set_master(pdev);
2795 dac_enabled = 1;
2796 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2797 if (status != 0) {
2798 dac_enabled = 0;
2799 dev_err(&pdev->dev,
2800 "64-bit pci address mask was refused, trying 32-bit");
2801 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2802 }
2803 if (status != 0) {
2804 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2805 goto abort_with_netdev;
2806 }
2807 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2808 &mgp->cmd_bus, GFP_KERNEL);
2809 if (mgp->cmd == NULL)
2810 goto abort_with_netdev;
2811
2812 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2813 &mgp->fw_stats_bus, GFP_KERNEL);
2814 if (mgp->fw_stats == NULL)
2815 goto abort_with_cmd;
2816
2817 mgp->board_span = pci_resource_len(pdev, 0);
2818 mgp->iomem_base = pci_resource_start(pdev, 0);
2819 mgp->mtrr = -1;
2820 #ifdef CONFIG_MTRR
2821 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2822 MTRR_TYPE_WRCOMB, 1);
2823 #endif
2824 /* Hack. need to get rid of these magic numbers */
2825 mgp->sram_size =
2826 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2827 if (mgp->sram_size > mgp->board_span) {
2828 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2829 mgp->board_span);
2830 goto abort_with_wc;
2831 }
2832 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2833 if (mgp->sram == NULL) {
2834 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2835 mgp->board_span, mgp->iomem_base);
2836 status = -ENXIO;
2837 goto abort_with_wc;
2838 }
2839 memcpy_fromio(mgp->eeprom_strings,
2840 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2841 MYRI10GE_EEPROM_STRINGS_SIZE);
2842 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2843 status = myri10ge_read_mac_addr(mgp);
2844 if (status)
2845 goto abort_with_ioremap;
2846
2847 for (i = 0; i < ETH_ALEN; i++)
2848 netdev->dev_addr[i] = mgp->mac_addr[i];
2849
2850 /* allocate rx done ring */
2851 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2852 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2853 &mgp->rx_done.bus, GFP_KERNEL);
2854 if (mgp->rx_done.entry == NULL)
2855 goto abort_with_ioremap;
2856 memset(mgp->rx_done.entry, 0, bytes);
2857
2858 status = myri10ge_load_firmware(mgp);
2859 if (status != 0) {
2860 dev_err(&pdev->dev, "failed to load firmware\n");
2861 goto abort_with_rx_done;
2862 }
2863
2864 status = myri10ge_reset(mgp);
2865 if (status != 0) {
2866 dev_err(&pdev->dev, "failed reset\n");
2867 goto abort_with_firmware;
2868 }
2869
2870 pci_set_drvdata(pdev, mgp);
2871 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2872 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2873 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2874 myri10ge_initial_mtu = 68;
2875 netdev->mtu = myri10ge_initial_mtu;
2876 netdev->open = myri10ge_open;
2877 netdev->stop = myri10ge_close;
2878 netdev->hard_start_xmit = myri10ge_xmit;
2879 netdev->get_stats = myri10ge_get_stats;
2880 netdev->base_addr = mgp->iomem_base;
2881 netdev->irq = pdev->irq;
2882 netdev->change_mtu = myri10ge_change_mtu;
2883 netdev->set_multicast_list = myri10ge_set_multicast_list;
2884 netdev->set_mac_address = myri10ge_set_mac_address;
2885 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2886 if (dac_enabled)
2887 netdev->features |= NETIF_F_HIGHDMA;
2888 netdev->poll = myri10ge_poll;
2889 netdev->weight = myri10ge_napi_weight;
2890
2891 /* Save configuration space to be restored if the
2892 * nic resets due to a parity error */
2893 pci_save_state(pdev);
2894
2895 /* Setup the watchdog timer */
2896 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2897 (unsigned long)mgp);
2898
2899 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2900 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
2901 status = register_netdev(netdev);
2902 if (status != 0) {
2903 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2904 goto abort_with_state;
2905 }
2906 dev_info(dev, "%d, tx bndry %d, fw %s, WC %s\n",
2907 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2908 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2909
2910 return 0;
2911
2912 abort_with_state:
2913 pci_restore_state(pdev);
2914
2915 abort_with_firmware:
2916 myri10ge_dummy_rdma(mgp, 0);
2917
2918 abort_with_rx_done:
2919 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2920 dma_free_coherent(&pdev->dev, bytes,
2921 mgp->rx_done.entry, mgp->rx_done.bus);
2922
2923 abort_with_ioremap:
2924 iounmap(mgp->sram);
2925
2926 abort_with_wc:
2927 #ifdef CONFIG_MTRR
2928 if (mgp->mtrr >= 0)
2929 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2930 #endif
2931 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2932 mgp->fw_stats, mgp->fw_stats_bus);
2933
2934 abort_with_cmd:
2935 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2936 mgp->cmd, mgp->cmd_bus);
2937
2938 abort_with_netdev:
2939
2940 free_netdev(netdev);
2941 return status;
2942 }
2943
2944 /*
2945 * myri10ge_remove
2946 *
2947 * Does what is necessary to shutdown one Myrinet device. Called
2948 * once for each Myrinet card by the kernel when a module is
2949 * unloaded.
2950 */
2951 static void myri10ge_remove(struct pci_dev *pdev)
2952 {
2953 struct myri10ge_priv *mgp;
2954 struct net_device *netdev;
2955 size_t bytes;
2956
2957 mgp = pci_get_drvdata(pdev);
2958 if (mgp == NULL)
2959 return;
2960
2961 flush_scheduled_work();
2962 netdev = mgp->dev;
2963 unregister_netdev(netdev);
2964
2965 myri10ge_dummy_rdma(mgp, 0);
2966
2967 /* avoid a memory leak */
2968 pci_restore_state(pdev);
2969
2970 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2971 dma_free_coherent(&pdev->dev, bytes,
2972 mgp->rx_done.entry, mgp->rx_done.bus);
2973
2974 iounmap(mgp->sram);
2975
2976 #ifdef CONFIG_MTRR
2977 if (mgp->mtrr >= 0)
2978 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2979 #endif
2980 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2981 mgp->fw_stats, mgp->fw_stats_bus);
2982
2983 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2984 mgp->cmd, mgp->cmd_bus);
2985
2986 free_netdev(netdev);
2987 pci_set_drvdata(pdev, NULL);
2988 }
2989
2990 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
2991
2992 static struct pci_device_id myri10ge_pci_tbl[] = {
2993 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
2994 {0},
2995 };
2996
2997 static struct pci_driver myri10ge_driver = {
2998 .name = "myri10ge",
2999 .probe = myri10ge_probe,
3000 .remove = myri10ge_remove,
3001 .id_table = myri10ge_pci_tbl,
3002 #ifdef CONFIG_PM
3003 .suspend = myri10ge_suspend,
3004 .resume = myri10ge_resume,
3005 #endif
3006 };
3007
3008 static __init int myri10ge_init_module(void)
3009 {
3010 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3011 MYRI10GE_VERSION_STR);
3012 return pci_register_driver(&myri10ge_driver);
3013 }
3014
3015 module_init(myri10ge_init_module);
3016
3017 static __exit void myri10ge_cleanup_module(void)
3018 {
3019 pci_unregister_driver(&myri10ge_driver);
3020 }
3021
3022 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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