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Merge branch 'intx' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/misc-2.6
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.0.0"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 struct myri10ge_rx_buffer_state {
96 struct sk_buff *skb;
97 DECLARE_PCI_UNMAP_ADDR(bus)
98 DECLARE_PCI_UNMAP_LEN(len)
99 };
100
101 struct myri10ge_tx_buffer_state {
102 struct sk_buff *skb;
103 int last;
104 DECLARE_PCI_UNMAP_ADDR(bus)
105 DECLARE_PCI_UNMAP_LEN(len)
106 };
107
108 struct myri10ge_cmd {
109 u32 data0;
110 u32 data1;
111 u32 data2;
112 };
113
114 struct myri10ge_rx_buf {
115 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
116 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
117 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
118 struct myri10ge_rx_buffer_state *info;
119 int cnt;
120 int alloc_fail;
121 int mask; /* number of rx slots -1 */
122 };
123
124 struct myri10ge_tx_buf {
125 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
126 u8 __iomem *wc_fifo; /* w/c send fifo address */
127 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
128 char *req_bytes;
129 struct myri10ge_tx_buffer_state *info;
130 int mask; /* number of transmit slots -1 */
131 int boundary; /* boundary transmits cannot cross */
132 int req ____cacheline_aligned; /* transmit slots submitted */
133 int pkt_start; /* packets started */
134 int done ____cacheline_aligned; /* transmit slots completed */
135 int pkt_done; /* packets completed */
136 };
137
138 struct myri10ge_rx_done {
139 struct mcp_slot *entry;
140 dma_addr_t bus;
141 int cnt;
142 int idx;
143 };
144
145 struct myri10ge_priv {
146 int running; /* running? */
147 int csum_flag; /* rx_csums? */
148 struct myri10ge_tx_buf tx; /* transmit ring */
149 struct myri10ge_rx_buf rx_small;
150 struct myri10ge_rx_buf rx_big;
151 struct myri10ge_rx_done rx_done;
152 int small_bytes;
153 struct net_device *dev;
154 struct net_device_stats stats;
155 u8 __iomem *sram;
156 int sram_size;
157 unsigned long board_span;
158 unsigned long iomem_base;
159 __be32 __iomem *irq_claim;
160 __be32 __iomem *irq_deassert;
161 char *mac_addr_string;
162 struct mcp_cmd_response *cmd;
163 dma_addr_t cmd_bus;
164 struct mcp_irq_data *fw_stats;
165 dma_addr_t fw_stats_bus;
166 struct pci_dev *pdev;
167 int msi_enabled;
168 __be32 link_state;
169 unsigned int rdma_tags_available;
170 int intr_coal_delay;
171 __be32 __iomem *intr_coal_delay_ptr;
172 int mtrr;
173 int wake_queue;
174 int stop_queue;
175 int down_cnt;
176 wait_queue_head_t down_wq;
177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer;
179 int watchdog_tx_done;
180 int watchdog_tx_req;
181 int watchdog_resets;
182 int tx_linearized;
183 int pause;
184 char *fw_name;
185 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
186 char fw_version[128];
187 u8 mac_addr[6]; /* eeprom mac address */
188 unsigned long serial_number;
189 int vendor_specific_offset;
190 int fw_multicast_support;
191 u32 devctl;
192 u16 msi_flags;
193 u32 read_dma;
194 u32 write_dma;
195 u32 read_write_dma;
196 u32 link_changes;
197 u32 msg_enable;
198 };
199
200 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
201 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
202
203 static char *myri10ge_fw_name = NULL;
204 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
205 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
206
207 static int myri10ge_ecrc_enable = 1;
208 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
209 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
210
211 static int myri10ge_max_intr_slots = 1024;
212 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
213 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
214
215 static int myri10ge_small_bytes = -1; /* -1 == auto */
216 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
217 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
218
219 static int myri10ge_msi = 1; /* enable msi by default */
220 module_param(myri10ge_msi, int, S_IRUGO);
221 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
222
223 static int myri10ge_intr_coal_delay = 25;
224 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
225 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
226
227 static int myri10ge_flow_control = 1;
228 module_param(myri10ge_flow_control, int, S_IRUGO);
229 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
230
231 static int myri10ge_deassert_wait = 1;
232 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
233 MODULE_PARM_DESC(myri10ge_deassert_wait,
234 "Wait when deasserting legacy interrupts\n");
235
236 static int myri10ge_force_firmware = 0;
237 module_param(myri10ge_force_firmware, int, S_IRUGO);
238 MODULE_PARM_DESC(myri10ge_force_firmware,
239 "Force firmware to assume aligned completions\n");
240
241 static int myri10ge_skb_cross_4k = 0;
242 module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR);
243 MODULE_PARM_DESC(myri10ge_skb_cross_4k,
244 "Can a small skb cross a 4KB boundary?\n");
245
246 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
247 module_param(myri10ge_initial_mtu, int, S_IRUGO);
248 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
249
250 static int myri10ge_napi_weight = 64;
251 module_param(myri10ge_napi_weight, int, S_IRUGO);
252 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
253
254 static int myri10ge_watchdog_timeout = 1;
255 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
256 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
257
258 static int myri10ge_max_irq_loops = 1048576;
259 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
260 MODULE_PARM_DESC(myri10ge_max_irq_loops,
261 "Set stuck legacy IRQ detection threshold\n");
262
263 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
264
265 static int myri10ge_debug = -1; /* defaults above */
266 module_param(myri10ge_debug, int, 0);
267 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
268
269 #define MYRI10GE_FW_OFFSET 1024*1024
270 #define MYRI10GE_HIGHPART_TO_U32(X) \
271 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
272 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
273
274 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
275
276 static inline void put_be32(__be32 val, __be32 __iomem *p)
277 {
278 __raw_writel((__force __u32)val, (__force void __iomem *)p);
279 }
280
281 static int
282 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
283 struct myri10ge_cmd *data, int atomic)
284 {
285 struct mcp_cmd *buf;
286 char buf_bytes[sizeof(*buf) + 8];
287 struct mcp_cmd_response *response = mgp->cmd;
288 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
289 u32 dma_low, dma_high, result, value;
290 int sleep_total = 0;
291
292 /* ensure buf is aligned to 8 bytes */
293 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
294
295 buf->data0 = htonl(data->data0);
296 buf->data1 = htonl(data->data1);
297 buf->data2 = htonl(data->data2);
298 buf->cmd = htonl(cmd);
299 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
300 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
301
302 buf->response_addr.low = htonl(dma_low);
303 buf->response_addr.high = htonl(dma_high);
304 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
305 mb();
306 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
307
308 /* wait up to 15ms. Longest command is the DMA benchmark,
309 * which is capped at 5ms, but runs from a timeout handler
310 * that runs every 7.8ms. So a 15ms timeout leaves us with
311 * a 2.2ms margin
312 */
313 if (atomic) {
314 /* if atomic is set, do not sleep,
315 * and try to get the completion quickly
316 * (1ms will be enough for those commands) */
317 for (sleep_total = 0;
318 sleep_total < 1000
319 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
320 sleep_total += 10)
321 udelay(10);
322 } else {
323 /* use msleep for most command */
324 for (sleep_total = 0;
325 sleep_total < 15
326 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
327 sleep_total++)
328 msleep(1);
329 }
330
331 result = ntohl(response->result);
332 value = ntohl(response->data);
333 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
334 if (result == 0) {
335 data->data0 = value;
336 return 0;
337 } else if (result == MXGEFW_CMD_UNKNOWN) {
338 return -ENOSYS;
339 } else {
340 dev_err(&mgp->pdev->dev,
341 "command %d failed, result = %d\n",
342 cmd, result);
343 return -ENXIO;
344 }
345 }
346
347 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
348 cmd, result);
349 return -EAGAIN;
350 }
351
352 /*
353 * The eeprom strings on the lanaiX have the format
354 * SN=x\0
355 * MAC=x:x:x:x:x:x\0
356 * PT:ddd mmm xx xx:xx:xx xx\0
357 * PV:ddd mmm xx xx:xx:xx xx\0
358 */
359 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
360 {
361 char *ptr, *limit;
362 int i;
363
364 ptr = mgp->eeprom_strings;
365 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
366
367 while (*ptr != '\0' && ptr < limit) {
368 if (memcmp(ptr, "MAC=", 4) == 0) {
369 ptr += 4;
370 mgp->mac_addr_string = ptr;
371 for (i = 0; i < 6; i++) {
372 if ((ptr + 2) > limit)
373 goto abort;
374 mgp->mac_addr[i] =
375 simple_strtoul(ptr, &ptr, 16);
376 ptr += 1;
377 }
378 }
379 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
380 ptr += 3;
381 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
382 }
383 while (ptr < limit && *ptr++) ;
384 }
385
386 return 0;
387
388 abort:
389 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
390 return -ENXIO;
391 }
392
393 /*
394 * Enable or disable periodic RDMAs from the host to make certain
395 * chipsets resend dropped PCIe messages
396 */
397
398 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
399 {
400 char __iomem *submit;
401 __be32 buf[16];
402 u32 dma_low, dma_high;
403 int i;
404
405 /* clear confirmation addr */
406 mgp->cmd->data = 0;
407 mb();
408
409 /* send a rdma command to the PCIe engine, and wait for the
410 * response in the confirmation address. The firmware should
411 * write a -1 there to indicate it is alive and well
412 */
413 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
414 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
415
416 buf[0] = htonl(dma_high); /* confirm addr MSW */
417 buf[1] = htonl(dma_low); /* confirm addr LSW */
418 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
419 buf[3] = htonl(dma_high); /* dummy addr MSW */
420 buf[4] = htonl(dma_low); /* dummy addr LSW */
421 buf[5] = htonl(enable); /* enable? */
422
423 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
424
425 myri10ge_pio_copy(submit, &buf, sizeof(buf));
426 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
427 msleep(1);
428 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
429 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
430 (enable ? "enable" : "disable"));
431 }
432
433 static int
434 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
435 struct mcp_gen_header *hdr)
436 {
437 struct device *dev = &mgp->pdev->dev;
438 int major, minor;
439
440 /* check firmware type */
441 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
442 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
443 return -EINVAL;
444 }
445
446 /* save firmware version for ethtool */
447 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
448
449 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
450
451 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
452 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
453 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
454 MXGEFW_VERSION_MINOR);
455 return -EINVAL;
456 }
457 return 0;
458 }
459
460 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
461 {
462 unsigned crc, reread_crc;
463 const struct firmware *fw;
464 struct device *dev = &mgp->pdev->dev;
465 struct mcp_gen_header *hdr;
466 size_t hdr_offset;
467 int status;
468 unsigned i;
469
470 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
471 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
472 mgp->fw_name);
473 status = -EINVAL;
474 goto abort_with_nothing;
475 }
476
477 /* check size */
478
479 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
480 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
481 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
482 status = -EINVAL;
483 goto abort_with_fw;
484 }
485
486 /* check id */
487 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
488 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
489 dev_err(dev, "Bad firmware file\n");
490 status = -EINVAL;
491 goto abort_with_fw;
492 }
493 hdr = (void *)(fw->data + hdr_offset);
494
495 status = myri10ge_validate_firmware(mgp, hdr);
496 if (status != 0)
497 goto abort_with_fw;
498
499 crc = crc32(~0, fw->data, fw->size);
500 for (i = 0; i < fw->size; i += 256) {
501 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
502 fw->data + i,
503 min(256U, (unsigned)(fw->size - i)));
504 mb();
505 readb(mgp->sram);
506 }
507 /* corruption checking is good for parity recovery and buggy chipset */
508 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
509 reread_crc = crc32(~0, fw->data, fw->size);
510 if (crc != reread_crc) {
511 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
512 (unsigned)fw->size, reread_crc, crc);
513 status = -EIO;
514 goto abort_with_fw;
515 }
516 *size = (u32) fw->size;
517
518 abort_with_fw:
519 release_firmware(fw);
520
521 abort_with_nothing:
522 return status;
523 }
524
525 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
526 {
527 struct mcp_gen_header *hdr;
528 struct device *dev = &mgp->pdev->dev;
529 const size_t bytes = sizeof(struct mcp_gen_header);
530 size_t hdr_offset;
531 int status;
532
533 /* find running firmware header */
534 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
535
536 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
537 dev_err(dev, "Running firmware has bad header offset (%d)\n",
538 (int)hdr_offset);
539 return -EIO;
540 }
541
542 /* copy header of running firmware from SRAM to host memory to
543 * validate firmware */
544 hdr = kmalloc(bytes, GFP_KERNEL);
545 if (hdr == NULL) {
546 dev_err(dev, "could not malloc firmware hdr\n");
547 return -ENOMEM;
548 }
549 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
550 status = myri10ge_validate_firmware(mgp, hdr);
551 kfree(hdr);
552 return status;
553 }
554
555 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
556 {
557 char __iomem *submit;
558 __be32 buf[16];
559 u32 dma_low, dma_high, size;
560 int status, i;
561
562 size = 0;
563 status = myri10ge_load_hotplug_firmware(mgp, &size);
564 if (status) {
565 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
566
567 /* Do not attempt to adopt firmware if there
568 * was a bad crc */
569 if (status == -EIO)
570 return status;
571
572 status = myri10ge_adopt_running_firmware(mgp);
573 if (status != 0) {
574 dev_err(&mgp->pdev->dev,
575 "failed to adopt running firmware\n");
576 return status;
577 }
578 dev_info(&mgp->pdev->dev,
579 "Successfully adopted running firmware\n");
580 if (mgp->tx.boundary == 4096) {
581 dev_warn(&mgp->pdev->dev,
582 "Using firmware currently running on NIC"
583 ". For optimal\n");
584 dev_warn(&mgp->pdev->dev,
585 "performance consider loading optimized "
586 "firmware\n");
587 dev_warn(&mgp->pdev->dev, "via hotplug\n");
588 }
589
590 mgp->fw_name = "adopted";
591 mgp->tx.boundary = 2048;
592 return status;
593 }
594
595 /* clear confirmation addr */
596 mgp->cmd->data = 0;
597 mb();
598
599 /* send a reload command to the bootstrap MCP, and wait for the
600 * response in the confirmation address. The firmware should
601 * write a -1 there to indicate it is alive and well
602 */
603 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
604 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
605
606 buf[0] = htonl(dma_high); /* confirm addr MSW */
607 buf[1] = htonl(dma_low); /* confirm addr LSW */
608 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
609
610 /* FIX: All newest firmware should un-protect the bottom of
611 * the sram before handoff. However, the very first interfaces
612 * do not. Therefore the handoff copy must skip the first 8 bytes
613 */
614 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
615 buf[4] = htonl(size - 8); /* length of code */
616 buf[5] = htonl(8); /* where to copy to */
617 buf[6] = htonl(0); /* where to jump to */
618
619 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
620
621 myri10ge_pio_copy(submit, &buf, sizeof(buf));
622 mb();
623 msleep(1);
624 mb();
625 i = 0;
626 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
627 msleep(1);
628 i++;
629 }
630 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
631 dev_err(&mgp->pdev->dev, "handoff failed\n");
632 return -ENXIO;
633 }
634 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
635 myri10ge_dummy_rdma(mgp, 1);
636
637 return 0;
638 }
639
640 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
641 {
642 struct myri10ge_cmd cmd;
643 int status;
644
645 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
646 | (addr[2] << 8) | addr[3]);
647
648 cmd.data1 = ((addr[4] << 8) | (addr[5]));
649
650 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
651 return status;
652 }
653
654 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
655 {
656 struct myri10ge_cmd cmd;
657 int status, ctl;
658
659 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
660 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
661
662 if (status) {
663 printk(KERN_ERR
664 "myri10ge: %s: Failed to set flow control mode\n",
665 mgp->dev->name);
666 return status;
667 }
668 mgp->pause = pause;
669 return 0;
670 }
671
672 static void
673 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
674 {
675 struct myri10ge_cmd cmd;
676 int status, ctl;
677
678 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
679 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
680 if (status)
681 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
682 mgp->dev->name);
683 }
684
685 static int myri10ge_reset(struct myri10ge_priv *mgp)
686 {
687 struct myri10ge_cmd cmd;
688 int status;
689 size_t bytes;
690 u32 len;
691
692 /* try to send a reset command to the card to see if it
693 * is alive */
694 memset(&cmd, 0, sizeof(cmd));
695 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
696 if (status != 0) {
697 dev_err(&mgp->pdev->dev, "failed reset\n");
698 return -ENXIO;
699 }
700
701 /* Now exchange information about interrupts */
702
703 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
704 memset(mgp->rx_done.entry, 0, bytes);
705 cmd.data0 = (u32) bytes;
706 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
707 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
708 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
709 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
710
711 status |=
712 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
713 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
714 if (!mgp->msi_enabled) {
715 status |= myri10ge_send_cmd
716 (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
717 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
718
719 }
720 status |= myri10ge_send_cmd
721 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
722 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
723 if (status != 0) {
724 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
725 return status;
726 }
727 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
728
729 /* Run a small DMA test.
730 * The magic multipliers to the length tell the firmware
731 * to do DMA read, write, or read+write tests. The
732 * results are returned in cmd.data0. The upper 16
733 * bits or the return is the number of transfers completed.
734 * The lower 16 bits is the time in 0.5us ticks that the
735 * transfers took to complete.
736 */
737
738 len = mgp->tx.boundary;
739
740 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
741 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
742 cmd.data2 = len * 0x10000;
743 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
744 if (status == 0)
745 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
746 (cmd.data0 & 0xffff);
747 else
748 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
749 status);
750 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
751 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
752 cmd.data2 = len * 0x1;
753 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
754 if (status == 0)
755 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
756 (cmd.data0 & 0xffff);
757 else
758 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
759 status);
760
761 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
762 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
763 cmd.data2 = len * 0x10001;
764 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
765 if (status == 0)
766 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
767 (cmd.data0 & 0xffff);
768 else
769 dev_warn(&mgp->pdev->dev,
770 "DMA read/write benchmark failed: %d\n", status);
771
772 memset(mgp->rx_done.entry, 0, bytes);
773
774 /* reset mcp/driver shared state back to 0 */
775 mgp->tx.req = 0;
776 mgp->tx.done = 0;
777 mgp->tx.pkt_start = 0;
778 mgp->tx.pkt_done = 0;
779 mgp->rx_big.cnt = 0;
780 mgp->rx_small.cnt = 0;
781 mgp->rx_done.idx = 0;
782 mgp->rx_done.cnt = 0;
783 mgp->link_changes = 0;
784 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
785 myri10ge_change_promisc(mgp, 0, 0);
786 myri10ge_change_pause(mgp, mgp->pause);
787 return status;
788 }
789
790 static inline void
791 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
792 struct mcp_kreq_ether_recv *src)
793 {
794 __be32 low;
795
796 low = src->addr_low;
797 src->addr_low = htonl(DMA_32BIT_MASK);
798 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
799 mb();
800 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
801 mb();
802 src->addr_low = low;
803 put_be32(low, &dst->addr_low);
804 mb();
805 }
806
807 /*
808 * Set of routines to get a new receive buffer. Any buffer which
809 * crosses a 4KB boundary must start on a 4KB boundary due to PCIe
810 * wdma restrictions. We also try to align any smaller allocation to
811 * at least a 16 byte boundary for efficiency. We assume the linux
812 * memory allocator works by powers of 2, and will not return memory
813 * smaller than 2KB which crosses a 4KB boundary. If it does, we fall
814 * back to allocating 2x as much space as required.
815 *
816 * We intend to replace large (>4KB) skb allocations by using
817 * pages directly and building a fraglist in the near future.
818 */
819
820 static inline struct sk_buff *myri10ge_alloc_big(struct net_device *dev,
821 int bytes)
822 {
823 struct sk_buff *skb;
824 unsigned long data, roundup;
825
826 skb = netdev_alloc_skb(dev, bytes + 4096 + MXGEFW_PAD);
827 if (skb == NULL)
828 return NULL;
829
830 /* Correct skb->truesize so that socket buffer
831 * accounting is not confused the rounding we must
832 * do to satisfy alignment constraints.
833 */
834 skb->truesize -= 4096;
835
836 data = (unsigned long)(skb->data);
837 roundup = (-data) & (4095);
838 skb_reserve(skb, roundup);
839 return skb;
840 }
841
842 /* Allocate 2x as much space as required and use whichever portion
843 * does not cross a 4KB boundary */
844 static inline struct sk_buff *myri10ge_alloc_small_safe(struct net_device *dev,
845 unsigned int bytes)
846 {
847 struct sk_buff *skb;
848 unsigned long data, boundary;
849
850 skb = netdev_alloc_skb(dev, 2 * (bytes + MXGEFW_PAD) - 1);
851 if (unlikely(skb == NULL))
852 return NULL;
853
854 /* Correct skb->truesize so that socket buffer
855 * accounting is not confused the rounding we must
856 * do to satisfy alignment constraints.
857 */
858 skb->truesize -= bytes + MXGEFW_PAD;
859
860 data = (unsigned long)(skb->data);
861 boundary = (data + 4095UL) & ~4095UL;
862 if ((boundary - data) >= (bytes + MXGEFW_PAD))
863 return skb;
864
865 skb_reserve(skb, boundary - data);
866 return skb;
867 }
868
869 /* Allocate just enough space, and verify that the allocated
870 * space does not cross a 4KB boundary */
871 static inline struct sk_buff *myri10ge_alloc_small(struct net_device *dev,
872 int bytes)
873 {
874 struct sk_buff *skb;
875 unsigned long roundup, data, end;
876
877 skb = netdev_alloc_skb(dev, bytes + 16 + MXGEFW_PAD);
878 if (unlikely(skb == NULL))
879 return NULL;
880
881 /* Round allocated buffer to 16 byte boundary */
882 data = (unsigned long)(skb->data);
883 roundup = (-data) & 15UL;
884 skb_reserve(skb, roundup);
885 /* Verify that the data buffer does not cross a page boundary */
886 data = (unsigned long)(skb->data);
887 end = data + bytes + MXGEFW_PAD - 1;
888 if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) {
889 printk(KERN_NOTICE
890 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
891 myri10ge_skb_cross_4k = 1;
892 dev_kfree_skb_any(skb);
893 skb = myri10ge_alloc_small_safe(dev, bytes);
894 }
895 return skb;
896 }
897
898 static inline int
899 myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct myri10ge_priv *mgp,
900 int bytes, int idx)
901 {
902 struct net_device *dev = mgp->dev;
903 struct pci_dev *pdev = mgp->pdev;
904 struct sk_buff *skb;
905 dma_addr_t bus;
906 int len, retval = 0;
907
908 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
909
910 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
911 skb = myri10ge_alloc_big(dev, bytes);
912 else if (myri10ge_skb_cross_4k)
913 skb = myri10ge_alloc_small_safe(dev, bytes);
914 else
915 skb = myri10ge_alloc_small(dev, bytes);
916
917 if (unlikely(skb == NULL)) {
918 rx->alloc_fail++;
919 retval = -ENOBUFS;
920 goto done;
921 }
922
923 /* set len so that it only covers the area we
924 * need mapped for DMA */
925 len = bytes + MXGEFW_PAD;
926
927 bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE);
928 rx->info[idx].skb = skb;
929 pci_unmap_addr_set(&rx->info[idx], bus, bus);
930 pci_unmap_len_set(&rx->info[idx], len, len);
931 rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus));
932 rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
933
934 done:
935 /* copy 8 descriptors (64-bytes) to the mcp at a time */
936 if ((idx & 7) == 7) {
937 if (rx->wc_fifo == NULL)
938 myri10ge_submit_8rx(&rx->lanai[idx - 7],
939 &rx->shadow[idx - 7]);
940 else {
941 mb();
942 myri10ge_pio_copy(rx->wc_fifo,
943 &rx->shadow[idx - 7], 64);
944 }
945 }
946 return retval;
947 }
948
949 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
950 {
951 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
952
953 if ((skb->protocol == htons(ETH_P_8021Q)) &&
954 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
955 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
956 skb->csum = hw_csum;
957 skb->ip_summed = CHECKSUM_COMPLETE;
958 }
959 }
960
961 static inline unsigned long
962 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
963 int bytes, int len, __wsum csum)
964 {
965 dma_addr_t bus;
966 struct sk_buff *skb;
967 int idx, unmap_len;
968
969 idx = rx->cnt & rx->mask;
970 rx->cnt++;
971
972 /* save a pointer to the received skb */
973 skb = rx->info[idx].skb;
974 bus = pci_unmap_addr(&rx->info[idx], bus);
975 unmap_len = pci_unmap_len(&rx->info[idx], len);
976
977 /* try to replace the received skb */
978 if (myri10ge_getbuf(rx, mgp, bytes, idx)) {
979 /* drop the frame -- the old skbuf is re-cycled */
980 mgp->stats.rx_dropped += 1;
981 return 0;
982 }
983
984 /* unmap the recvd skb */
985 pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE);
986
987 /* mcp implicitly skips 1st bytes so that packet is properly
988 * aligned */
989 skb_reserve(skb, MXGEFW_PAD);
990
991 /* set the length of the frame */
992 skb_put(skb, len);
993
994 skb->protocol = eth_type_trans(skb, mgp->dev);
995 if (mgp->csum_flag) {
996 if ((skb->protocol == htons(ETH_P_IP)) ||
997 (skb->protocol == htons(ETH_P_IPV6))) {
998 skb->csum = csum;
999 skb->ip_summed = CHECKSUM_COMPLETE;
1000 } else
1001 myri10ge_vlan_ip_csum(skb, csum);
1002 }
1003
1004 netif_receive_skb(skb);
1005 mgp->dev->last_rx = jiffies;
1006 return 1;
1007 }
1008
1009 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1010 {
1011 struct pci_dev *pdev = mgp->pdev;
1012 struct myri10ge_tx_buf *tx = &mgp->tx;
1013 struct sk_buff *skb;
1014 int idx, len;
1015 int limit = 0;
1016
1017 while (tx->pkt_done != mcp_index) {
1018 idx = tx->done & tx->mask;
1019 skb = tx->info[idx].skb;
1020
1021 /* Mark as free */
1022 tx->info[idx].skb = NULL;
1023 if (tx->info[idx].last) {
1024 tx->pkt_done++;
1025 tx->info[idx].last = 0;
1026 }
1027 tx->done++;
1028 len = pci_unmap_len(&tx->info[idx], len);
1029 pci_unmap_len_set(&tx->info[idx], len, 0);
1030 if (skb) {
1031 mgp->stats.tx_bytes += skb->len;
1032 mgp->stats.tx_packets++;
1033 dev_kfree_skb_irq(skb);
1034 if (len)
1035 pci_unmap_single(pdev,
1036 pci_unmap_addr(&tx->info[idx],
1037 bus), len,
1038 PCI_DMA_TODEVICE);
1039 } else {
1040 if (len)
1041 pci_unmap_page(pdev,
1042 pci_unmap_addr(&tx->info[idx],
1043 bus), len,
1044 PCI_DMA_TODEVICE);
1045 }
1046
1047 /* limit potential for livelock by only handling
1048 * 2 full tx rings per call */
1049 if (unlikely(++limit > 2 * tx->mask))
1050 break;
1051 }
1052 /* start the queue if we've stopped it */
1053 if (netif_queue_stopped(mgp->dev)
1054 && tx->req - tx->done < (tx->mask >> 1)) {
1055 mgp->wake_queue++;
1056 netif_wake_queue(mgp->dev);
1057 }
1058 }
1059
1060 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1061 {
1062 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1063 unsigned long rx_bytes = 0;
1064 unsigned long rx_packets = 0;
1065 unsigned long rx_ok;
1066
1067 int idx = rx_done->idx;
1068 int cnt = rx_done->cnt;
1069 u16 length;
1070 __wsum checksum;
1071
1072 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1073 length = ntohs(rx_done->entry[idx].length);
1074 rx_done->entry[idx].length = 0;
1075 checksum = csum_unfold(rx_done->entry[idx].checksum);
1076 if (length <= mgp->small_bytes)
1077 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1078 mgp->small_bytes,
1079 length, checksum);
1080 else
1081 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1082 mgp->dev->mtu + ETH_HLEN,
1083 length, checksum);
1084 rx_packets += rx_ok;
1085 rx_bytes += rx_ok * (unsigned long)length;
1086 cnt++;
1087 idx = cnt & (myri10ge_max_intr_slots - 1);
1088
1089 /* limit potential for livelock by only handling a
1090 * limited number of frames. */
1091 (*limit)--;
1092 }
1093 rx_done->idx = idx;
1094 rx_done->cnt = cnt;
1095 mgp->stats.rx_packets += rx_packets;
1096 mgp->stats.rx_bytes += rx_bytes;
1097 }
1098
1099 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1100 {
1101 struct mcp_irq_data *stats = mgp->fw_stats;
1102
1103 if (unlikely(stats->stats_updated)) {
1104 if (mgp->link_state != stats->link_up) {
1105 mgp->link_state = stats->link_up;
1106 if (mgp->link_state) {
1107 if (netif_msg_link(mgp))
1108 printk(KERN_INFO
1109 "myri10ge: %s: link up\n",
1110 mgp->dev->name);
1111 netif_carrier_on(mgp->dev);
1112 mgp->link_changes++;
1113 } else {
1114 if (netif_msg_link(mgp))
1115 printk(KERN_INFO
1116 "myri10ge: %s: link down\n",
1117 mgp->dev->name);
1118 netif_carrier_off(mgp->dev);
1119 mgp->link_changes++;
1120 }
1121 }
1122 if (mgp->rdma_tags_available !=
1123 ntohl(mgp->fw_stats->rdma_tags_available)) {
1124 mgp->rdma_tags_available =
1125 ntohl(mgp->fw_stats->rdma_tags_available);
1126 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1127 "%d tags left\n", mgp->dev->name,
1128 mgp->rdma_tags_available);
1129 }
1130 mgp->down_cnt += stats->link_down;
1131 if (stats->link_down)
1132 wake_up(&mgp->down_wq);
1133 }
1134 }
1135
1136 static int myri10ge_poll(struct net_device *netdev, int *budget)
1137 {
1138 struct myri10ge_priv *mgp = netdev_priv(netdev);
1139 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1140 int limit, orig_limit, work_done;
1141
1142 /* process as many rx events as NAPI will allow */
1143 limit = min(*budget, netdev->quota);
1144 orig_limit = limit;
1145 myri10ge_clean_rx_done(mgp, &limit);
1146 work_done = orig_limit - limit;
1147 *budget -= work_done;
1148 netdev->quota -= work_done;
1149
1150 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1151 netif_rx_complete(netdev);
1152 put_be32(htonl(3), mgp->irq_claim);
1153 return 0;
1154 }
1155 return 1;
1156 }
1157
1158 static irqreturn_t myri10ge_intr(int irq, void *arg)
1159 {
1160 struct myri10ge_priv *mgp = arg;
1161 struct mcp_irq_data *stats = mgp->fw_stats;
1162 struct myri10ge_tx_buf *tx = &mgp->tx;
1163 u32 send_done_count;
1164 int i;
1165
1166 /* make sure it is our IRQ, and that the DMA has finished */
1167 if (unlikely(!stats->valid))
1168 return (IRQ_NONE);
1169
1170 /* low bit indicates receives are present, so schedule
1171 * napi poll handler */
1172 if (stats->valid & 1)
1173 netif_rx_schedule(mgp->dev);
1174
1175 if (!mgp->msi_enabled) {
1176 put_be32(0, mgp->irq_deassert);
1177 if (!myri10ge_deassert_wait)
1178 stats->valid = 0;
1179 mb();
1180 } else
1181 stats->valid = 0;
1182
1183 /* Wait for IRQ line to go low, if using INTx */
1184 i = 0;
1185 while (1) {
1186 i++;
1187 /* check for transmit completes and receives */
1188 send_done_count = ntohl(stats->send_done_count);
1189 if (send_done_count != tx->pkt_done)
1190 myri10ge_tx_done(mgp, (int)send_done_count);
1191 if (unlikely(i > myri10ge_max_irq_loops)) {
1192 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1193 mgp->dev->name);
1194 stats->valid = 0;
1195 schedule_work(&mgp->watchdog_work);
1196 }
1197 if (likely(stats->valid == 0))
1198 break;
1199 cpu_relax();
1200 barrier();
1201 }
1202
1203 myri10ge_check_statblock(mgp);
1204
1205 put_be32(htonl(3), mgp->irq_claim + 1);
1206 return (IRQ_HANDLED);
1207 }
1208
1209 static int
1210 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1211 {
1212 cmd->autoneg = AUTONEG_DISABLE;
1213 cmd->speed = SPEED_10000;
1214 cmd->duplex = DUPLEX_FULL;
1215 return 0;
1216 }
1217
1218 static void
1219 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1220 {
1221 struct myri10ge_priv *mgp = netdev_priv(netdev);
1222
1223 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1224 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1225 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1226 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1227 }
1228
1229 static int
1230 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1231 {
1232 struct myri10ge_priv *mgp = netdev_priv(netdev);
1233 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1234 return 0;
1235 }
1236
1237 static int
1238 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1239 {
1240 struct myri10ge_priv *mgp = netdev_priv(netdev);
1241
1242 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1243 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1244 return 0;
1245 }
1246
1247 static void
1248 myri10ge_get_pauseparam(struct net_device *netdev,
1249 struct ethtool_pauseparam *pause)
1250 {
1251 struct myri10ge_priv *mgp = netdev_priv(netdev);
1252
1253 pause->autoneg = 0;
1254 pause->rx_pause = mgp->pause;
1255 pause->tx_pause = mgp->pause;
1256 }
1257
1258 static int
1259 myri10ge_set_pauseparam(struct net_device *netdev,
1260 struct ethtool_pauseparam *pause)
1261 {
1262 struct myri10ge_priv *mgp = netdev_priv(netdev);
1263
1264 if (pause->tx_pause != mgp->pause)
1265 return myri10ge_change_pause(mgp, pause->tx_pause);
1266 if (pause->rx_pause != mgp->pause)
1267 return myri10ge_change_pause(mgp, pause->tx_pause);
1268 if (pause->autoneg != 0)
1269 return -EINVAL;
1270 return 0;
1271 }
1272
1273 static void
1274 myri10ge_get_ringparam(struct net_device *netdev,
1275 struct ethtool_ringparam *ring)
1276 {
1277 struct myri10ge_priv *mgp = netdev_priv(netdev);
1278
1279 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1280 ring->rx_max_pending = mgp->rx_big.mask + 1;
1281 ring->rx_jumbo_max_pending = 0;
1282 ring->tx_max_pending = mgp->rx_small.mask + 1;
1283 ring->rx_mini_pending = ring->rx_mini_max_pending;
1284 ring->rx_pending = ring->rx_max_pending;
1285 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1286 ring->tx_pending = ring->tx_max_pending;
1287 }
1288
1289 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1290 {
1291 struct myri10ge_priv *mgp = netdev_priv(netdev);
1292 if (mgp->csum_flag)
1293 return 1;
1294 else
1295 return 0;
1296 }
1297
1298 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1299 {
1300 struct myri10ge_priv *mgp = netdev_priv(netdev);
1301 if (csum_enabled)
1302 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1303 else
1304 mgp->csum_flag = 0;
1305 return 0;
1306 }
1307
1308 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1309 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1310 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1311 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1312 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1313 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1314 "tx_heartbeat_errors", "tx_window_errors",
1315 /* device-specific stats */
1316 "tx_boundary", "WC", "irq", "MSI",
1317 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1318 "serial_number", "tx_pkt_start", "tx_pkt_done",
1319 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1320 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1321 "link_changes", "link_up", "dropped_link_overflow",
1322 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
1323 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1324 "dropped_no_big_buffer"
1325 };
1326
1327 #define MYRI10GE_NET_STATS_LEN 21
1328 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1329
1330 static void
1331 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1332 {
1333 switch (stringset) {
1334 case ETH_SS_STATS:
1335 memcpy(data, *myri10ge_gstrings_stats,
1336 sizeof(myri10ge_gstrings_stats));
1337 break;
1338 }
1339 }
1340
1341 static int myri10ge_get_stats_count(struct net_device *netdev)
1342 {
1343 return MYRI10GE_STATS_LEN;
1344 }
1345
1346 static void
1347 myri10ge_get_ethtool_stats(struct net_device *netdev,
1348 struct ethtool_stats *stats, u64 * data)
1349 {
1350 struct myri10ge_priv *mgp = netdev_priv(netdev);
1351 int i;
1352
1353 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1354 data[i] = ((unsigned long *)&mgp->stats)[i];
1355
1356 data[i++] = (unsigned int)mgp->tx.boundary;
1357 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1358 data[i++] = (unsigned int)mgp->pdev->irq;
1359 data[i++] = (unsigned int)mgp->msi_enabled;
1360 data[i++] = (unsigned int)mgp->read_dma;
1361 data[i++] = (unsigned int)mgp->write_dma;
1362 data[i++] = (unsigned int)mgp->read_write_dma;
1363 data[i++] = (unsigned int)mgp->serial_number;
1364 data[i++] = (unsigned int)mgp->tx.pkt_start;
1365 data[i++] = (unsigned int)mgp->tx.pkt_done;
1366 data[i++] = (unsigned int)mgp->tx.req;
1367 data[i++] = (unsigned int)mgp->tx.done;
1368 data[i++] = (unsigned int)mgp->rx_small.cnt;
1369 data[i++] = (unsigned int)mgp->rx_big.cnt;
1370 data[i++] = (unsigned int)mgp->wake_queue;
1371 data[i++] = (unsigned int)mgp->stop_queue;
1372 data[i++] = (unsigned int)mgp->watchdog_resets;
1373 data[i++] = (unsigned int)mgp->tx_linearized;
1374 data[i++] = (unsigned int)mgp->link_changes;
1375 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1376 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1377 data[i++] =
1378 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1379 data[i++] =
1380 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1381 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1382 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1383 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1384 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1385 }
1386
1387 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1388 {
1389 struct myri10ge_priv *mgp = netdev_priv(netdev);
1390 mgp->msg_enable = value;
1391 }
1392
1393 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1394 {
1395 struct myri10ge_priv *mgp = netdev_priv(netdev);
1396 return mgp->msg_enable;
1397 }
1398
1399 static const struct ethtool_ops myri10ge_ethtool_ops = {
1400 .get_settings = myri10ge_get_settings,
1401 .get_drvinfo = myri10ge_get_drvinfo,
1402 .get_coalesce = myri10ge_get_coalesce,
1403 .set_coalesce = myri10ge_set_coalesce,
1404 .get_pauseparam = myri10ge_get_pauseparam,
1405 .set_pauseparam = myri10ge_set_pauseparam,
1406 .get_ringparam = myri10ge_get_ringparam,
1407 .get_rx_csum = myri10ge_get_rx_csum,
1408 .set_rx_csum = myri10ge_set_rx_csum,
1409 .get_tx_csum = ethtool_op_get_tx_csum,
1410 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1411 .get_sg = ethtool_op_get_sg,
1412 .set_sg = ethtool_op_set_sg,
1413 #ifdef NETIF_F_TSO
1414 .get_tso = ethtool_op_get_tso,
1415 .set_tso = ethtool_op_set_tso,
1416 #endif
1417 .get_strings = myri10ge_get_strings,
1418 .get_stats_count = myri10ge_get_stats_count,
1419 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1420 .set_msglevel = myri10ge_set_msglevel,
1421 .get_msglevel = myri10ge_get_msglevel
1422 };
1423
1424 static int myri10ge_allocate_rings(struct net_device *dev)
1425 {
1426 struct myri10ge_priv *mgp;
1427 struct myri10ge_cmd cmd;
1428 int tx_ring_size, rx_ring_size;
1429 int tx_ring_entries, rx_ring_entries;
1430 int i, status;
1431 size_t bytes;
1432
1433 mgp = netdev_priv(dev);
1434
1435 /* get ring sizes */
1436
1437 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1438 tx_ring_size = cmd.data0;
1439 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1440 rx_ring_size = cmd.data0;
1441
1442 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1443 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1444 mgp->tx.mask = tx_ring_entries - 1;
1445 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1446
1447 /* allocate the host shadow rings */
1448
1449 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1450 * sizeof(*mgp->tx.req_list);
1451 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1452 if (mgp->tx.req_bytes == NULL)
1453 goto abort_with_nothing;
1454
1455 /* ensure req_list entries are aligned to 8 bytes */
1456 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1457 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1458
1459 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1460 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1461 if (mgp->rx_small.shadow == NULL)
1462 goto abort_with_tx_req_bytes;
1463
1464 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1465 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1466 if (mgp->rx_big.shadow == NULL)
1467 goto abort_with_rx_small_shadow;
1468
1469 /* allocate the host info rings */
1470
1471 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1472 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1473 if (mgp->tx.info == NULL)
1474 goto abort_with_rx_big_shadow;
1475
1476 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1477 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1478 if (mgp->rx_small.info == NULL)
1479 goto abort_with_tx_info;
1480
1481 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1482 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1483 if (mgp->rx_big.info == NULL)
1484 goto abort_with_rx_small_info;
1485
1486 /* Fill the receive rings */
1487
1488 for (i = 0; i <= mgp->rx_small.mask; i++) {
1489 status = myri10ge_getbuf(&mgp->rx_small, mgp,
1490 mgp->small_bytes, i);
1491 if (status) {
1492 printk(KERN_ERR
1493 "myri10ge: %s: alloced only %d small bufs\n",
1494 dev->name, i);
1495 goto abort_with_rx_small_ring;
1496 }
1497 }
1498
1499 for (i = 0; i <= mgp->rx_big.mask; i++) {
1500 status =
1501 myri10ge_getbuf(&mgp->rx_big, mgp, dev->mtu + ETH_HLEN, i);
1502 if (status) {
1503 printk(KERN_ERR
1504 "myri10ge: %s: alloced only %d big bufs\n",
1505 dev->name, i);
1506 goto abort_with_rx_big_ring;
1507 }
1508 }
1509
1510 return 0;
1511
1512 abort_with_rx_big_ring:
1513 for (i = 0; i <= mgp->rx_big.mask; i++) {
1514 if (mgp->rx_big.info[i].skb != NULL)
1515 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1516 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1517 pci_unmap_single(mgp->pdev,
1518 pci_unmap_addr(&mgp->rx_big.info[i],
1519 bus),
1520 pci_unmap_len(&mgp->rx_big.info[i],
1521 len),
1522 PCI_DMA_FROMDEVICE);
1523 }
1524
1525 abort_with_rx_small_ring:
1526 for (i = 0; i <= mgp->rx_small.mask; i++) {
1527 if (mgp->rx_small.info[i].skb != NULL)
1528 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1529 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1530 pci_unmap_single(mgp->pdev,
1531 pci_unmap_addr(&mgp->rx_small.info[i],
1532 bus),
1533 pci_unmap_len(&mgp->rx_small.info[i],
1534 len),
1535 PCI_DMA_FROMDEVICE);
1536 }
1537 kfree(mgp->rx_big.info);
1538
1539 abort_with_rx_small_info:
1540 kfree(mgp->rx_small.info);
1541
1542 abort_with_tx_info:
1543 kfree(mgp->tx.info);
1544
1545 abort_with_rx_big_shadow:
1546 kfree(mgp->rx_big.shadow);
1547
1548 abort_with_rx_small_shadow:
1549 kfree(mgp->rx_small.shadow);
1550
1551 abort_with_tx_req_bytes:
1552 kfree(mgp->tx.req_bytes);
1553 mgp->tx.req_bytes = NULL;
1554 mgp->tx.req_list = NULL;
1555
1556 abort_with_nothing:
1557 return status;
1558 }
1559
1560 static void myri10ge_free_rings(struct net_device *dev)
1561 {
1562 struct myri10ge_priv *mgp;
1563 struct sk_buff *skb;
1564 struct myri10ge_tx_buf *tx;
1565 int i, len, idx;
1566
1567 mgp = netdev_priv(dev);
1568
1569 for (i = 0; i <= mgp->rx_big.mask; i++) {
1570 if (mgp->rx_big.info[i].skb != NULL)
1571 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1572 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1573 pci_unmap_single(mgp->pdev,
1574 pci_unmap_addr(&mgp->rx_big.info[i],
1575 bus),
1576 pci_unmap_len(&mgp->rx_big.info[i],
1577 len),
1578 PCI_DMA_FROMDEVICE);
1579 }
1580
1581 for (i = 0; i <= mgp->rx_small.mask; i++) {
1582 if (mgp->rx_small.info[i].skb != NULL)
1583 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1584 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1585 pci_unmap_single(mgp->pdev,
1586 pci_unmap_addr(&mgp->rx_small.info[i],
1587 bus),
1588 pci_unmap_len(&mgp->rx_small.info[i],
1589 len),
1590 PCI_DMA_FROMDEVICE);
1591 }
1592
1593 tx = &mgp->tx;
1594 while (tx->done != tx->req) {
1595 idx = tx->done & tx->mask;
1596 skb = tx->info[idx].skb;
1597
1598 /* Mark as free */
1599 tx->info[idx].skb = NULL;
1600 tx->done++;
1601 len = pci_unmap_len(&tx->info[idx], len);
1602 pci_unmap_len_set(&tx->info[idx], len, 0);
1603 if (skb) {
1604 mgp->stats.tx_dropped++;
1605 dev_kfree_skb_any(skb);
1606 if (len)
1607 pci_unmap_single(mgp->pdev,
1608 pci_unmap_addr(&tx->info[idx],
1609 bus), len,
1610 PCI_DMA_TODEVICE);
1611 } else {
1612 if (len)
1613 pci_unmap_page(mgp->pdev,
1614 pci_unmap_addr(&tx->info[idx],
1615 bus), len,
1616 PCI_DMA_TODEVICE);
1617 }
1618 }
1619 kfree(mgp->rx_big.info);
1620
1621 kfree(mgp->rx_small.info);
1622
1623 kfree(mgp->tx.info);
1624
1625 kfree(mgp->rx_big.shadow);
1626
1627 kfree(mgp->rx_small.shadow);
1628
1629 kfree(mgp->tx.req_bytes);
1630 mgp->tx.req_bytes = NULL;
1631 mgp->tx.req_list = NULL;
1632 }
1633
1634 static int myri10ge_open(struct net_device *dev)
1635 {
1636 struct myri10ge_priv *mgp;
1637 struct myri10ge_cmd cmd;
1638 int status, big_pow2;
1639
1640 mgp = netdev_priv(dev);
1641
1642 if (mgp->running != MYRI10GE_ETH_STOPPED)
1643 return -EBUSY;
1644
1645 mgp->running = MYRI10GE_ETH_STARTING;
1646 status = myri10ge_reset(mgp);
1647 if (status != 0) {
1648 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1649 mgp->running = MYRI10GE_ETH_STOPPED;
1650 return -ENXIO;
1651 }
1652
1653 /* decide what small buffer size to use. For good TCP rx
1654 * performance, it is important to not receive 1514 byte
1655 * frames into jumbo buffers, as it confuses the socket buffer
1656 * accounting code, leading to drops and erratic performance.
1657 */
1658
1659 if (dev->mtu <= ETH_DATA_LEN)
1660 mgp->small_bytes = 128; /* enough for a TCP header */
1661 else
1662 mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */
1663
1664 /* Override the small buffer size? */
1665 if (myri10ge_small_bytes > 0)
1666 mgp->small_bytes = myri10ge_small_bytes;
1667
1668 /* If the user sets an obscenely small MTU, adjust the small
1669 * bytes down to nearly nothing */
1670 if (mgp->small_bytes >= (dev->mtu + ETH_HLEN))
1671 mgp->small_bytes = 64;
1672
1673 /* get the lanai pointers to the send and receive rings */
1674
1675 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1676 mgp->tx.lanai =
1677 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1678
1679 status |=
1680 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1681 mgp->rx_small.lanai =
1682 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1683
1684 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1685 mgp->rx_big.lanai =
1686 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1687
1688 if (status != 0) {
1689 printk(KERN_ERR
1690 "myri10ge: %s: failed to get ring sizes or locations\n",
1691 dev->name);
1692 mgp->running = MYRI10GE_ETH_STOPPED;
1693 return -ENXIO;
1694 }
1695
1696 if (mgp->mtrr >= 0) {
1697 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1698 mgp->rx_small.wc_fifo =
1699 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1700 mgp->rx_big.wc_fifo =
1701 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1702 } else {
1703 mgp->tx.wc_fifo = NULL;
1704 mgp->rx_small.wc_fifo = NULL;
1705 mgp->rx_big.wc_fifo = NULL;
1706 }
1707
1708 status = myri10ge_allocate_rings(dev);
1709 if (status != 0)
1710 goto abort_with_nothing;
1711
1712 /* Firmware needs the big buff size as a power of 2. Lie and
1713 * tell him the buffer is larger, because we only use 1
1714 * buffer/pkt, and the mtu will prevent overruns.
1715 */
1716 big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD;
1717 while ((big_pow2 & (big_pow2 - 1)) != 0)
1718 big_pow2++;
1719
1720 /* now give firmware buffers sizes, and MTU */
1721 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1722 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1723 cmd.data0 = mgp->small_bytes;
1724 status |=
1725 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1726 cmd.data0 = big_pow2;
1727 status |=
1728 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1729 if (status) {
1730 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1731 dev->name);
1732 goto abort_with_rings;
1733 }
1734
1735 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1736 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1737 cmd.data2 = sizeof(struct mcp_irq_data);
1738 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1739 if (status == -ENOSYS) {
1740 dma_addr_t bus = mgp->fw_stats_bus;
1741 bus += offsetof(struct mcp_irq_data, send_done_count);
1742 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1743 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1744 status = myri10ge_send_cmd(mgp,
1745 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1746 &cmd, 0);
1747 /* Firmware cannot support multicast without STATS_DMA_V2 */
1748 mgp->fw_multicast_support = 0;
1749 } else {
1750 mgp->fw_multicast_support = 1;
1751 }
1752 if (status) {
1753 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1754 dev->name);
1755 goto abort_with_rings;
1756 }
1757
1758 mgp->link_state = htonl(~0U);
1759 mgp->rdma_tags_available = 15;
1760
1761 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1762
1763 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1764 if (status) {
1765 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1766 dev->name);
1767 goto abort_with_rings;
1768 }
1769
1770 mgp->wake_queue = 0;
1771 mgp->stop_queue = 0;
1772 mgp->running = MYRI10GE_ETH_RUNNING;
1773 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1774 add_timer(&mgp->watchdog_timer);
1775 netif_wake_queue(dev);
1776 return 0;
1777
1778 abort_with_rings:
1779 myri10ge_free_rings(dev);
1780
1781 abort_with_nothing:
1782 mgp->running = MYRI10GE_ETH_STOPPED;
1783 return -ENOMEM;
1784 }
1785
1786 static int myri10ge_close(struct net_device *dev)
1787 {
1788 struct myri10ge_priv *mgp;
1789 struct myri10ge_cmd cmd;
1790 int status, old_down_cnt;
1791
1792 mgp = netdev_priv(dev);
1793
1794 if (mgp->running != MYRI10GE_ETH_RUNNING)
1795 return 0;
1796
1797 if (mgp->tx.req_bytes == NULL)
1798 return 0;
1799
1800 del_timer_sync(&mgp->watchdog_timer);
1801 mgp->running = MYRI10GE_ETH_STOPPING;
1802 netif_poll_disable(mgp->dev);
1803 netif_carrier_off(dev);
1804 netif_stop_queue(dev);
1805 old_down_cnt = mgp->down_cnt;
1806 mb();
1807 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1808 if (status)
1809 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1810 dev->name);
1811
1812 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1813 if (old_down_cnt == mgp->down_cnt)
1814 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1815
1816 netif_tx_disable(dev);
1817
1818 myri10ge_free_rings(dev);
1819
1820 mgp->running = MYRI10GE_ETH_STOPPED;
1821 return 0;
1822 }
1823
1824 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1825 * backwards one at a time and handle ring wraps */
1826
1827 static inline void
1828 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1829 struct mcp_kreq_ether_send *src, int cnt)
1830 {
1831 int idx, starting_slot;
1832 starting_slot = tx->req;
1833 while (cnt > 1) {
1834 cnt--;
1835 idx = (starting_slot + cnt) & tx->mask;
1836 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1837 mb();
1838 }
1839 }
1840
1841 /*
1842 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1843 * at most 32 bytes at a time, so as to avoid involving the software
1844 * pio handler in the nic. We re-write the first segment's flags
1845 * to mark them valid only after writing the entire chain.
1846 */
1847
1848 static inline void
1849 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1850 int cnt)
1851 {
1852 int idx, i;
1853 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1854 struct mcp_kreq_ether_send *srcp;
1855 u8 last_flags;
1856
1857 idx = tx->req & tx->mask;
1858
1859 last_flags = src->flags;
1860 src->flags = 0;
1861 mb();
1862 dst = dstp = &tx->lanai[idx];
1863 srcp = src;
1864
1865 if ((idx + cnt) < tx->mask) {
1866 for (i = 0; i < (cnt - 1); i += 2) {
1867 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1868 mb(); /* force write every 32 bytes */
1869 srcp += 2;
1870 dstp += 2;
1871 }
1872 } else {
1873 /* submit all but the first request, and ensure
1874 * that it is submitted below */
1875 myri10ge_submit_req_backwards(tx, src, cnt);
1876 i = 0;
1877 }
1878 if (i < cnt) {
1879 /* submit the first request */
1880 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1881 mb(); /* barrier before setting valid flag */
1882 }
1883
1884 /* re-write the last 32-bits with the valid flags */
1885 src->flags = last_flags;
1886 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1887 tx->req += cnt;
1888 mb();
1889 }
1890
1891 static inline void
1892 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1893 struct mcp_kreq_ether_send *src, int cnt)
1894 {
1895 tx->req += cnt;
1896 mb();
1897 while (cnt >= 4) {
1898 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1899 mb();
1900 src += 4;
1901 cnt -= 4;
1902 }
1903 if (cnt > 0) {
1904 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1905 * needs to be so that we don't overrun it */
1906 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1907 src, 64);
1908 mb();
1909 }
1910 }
1911
1912 /*
1913 * Transmit a packet. We need to split the packet so that a single
1914 * segment does not cross myri10ge->tx.boundary, so this makes segment
1915 * counting tricky. So rather than try to count segments up front, we
1916 * just give up if there are too few segments to hold a reasonably
1917 * fragmented packet currently available. If we run
1918 * out of segments while preparing a packet for DMA, we just linearize
1919 * it and try again.
1920 */
1921
1922 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1923 {
1924 struct myri10ge_priv *mgp = netdev_priv(dev);
1925 struct mcp_kreq_ether_send *req;
1926 struct myri10ge_tx_buf *tx = &mgp->tx;
1927 struct skb_frag_struct *frag;
1928 dma_addr_t bus;
1929 u32 low;
1930 __be32 high_swapped;
1931 unsigned int len;
1932 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1933 u16 pseudo_hdr_offset, cksum_offset;
1934 int cum_len, seglen, boundary, rdma_count;
1935 u8 flags, odd_flag;
1936
1937 again:
1938 req = tx->req_list;
1939 avail = tx->mask - 1 - (tx->req - tx->done);
1940
1941 mss = 0;
1942 max_segments = MXGEFW_MAX_SEND_DESC;
1943
1944 #ifdef NETIF_F_TSO
1945 if (skb->len > (dev->mtu + ETH_HLEN)) {
1946 mss = skb_shinfo(skb)->gso_size;
1947 if (mss != 0)
1948 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1949 }
1950 #endif /*NETIF_F_TSO */
1951
1952 if ((unlikely(avail < max_segments))) {
1953 /* we are out of transmit resources */
1954 mgp->stop_queue++;
1955 netif_stop_queue(dev);
1956 return 1;
1957 }
1958
1959 /* Setup checksum offloading, if needed */
1960 cksum_offset = 0;
1961 pseudo_hdr_offset = 0;
1962 odd_flag = 0;
1963 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1964 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1965 cksum_offset = (skb->h.raw - skb->data);
1966 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
1967 /* If the headers are excessively large, then we must
1968 * fall back to a software checksum */
1969 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
1970 if (skb_checksum_help(skb))
1971 goto drop;
1972 cksum_offset = 0;
1973 pseudo_hdr_offset = 0;
1974 } else {
1975 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1976 flags |= MXGEFW_FLAGS_CKSUM;
1977 }
1978 }
1979
1980 cum_len = 0;
1981
1982 #ifdef NETIF_F_TSO
1983 if (mss) { /* TSO */
1984 /* this removes any CKSUM flag from before */
1985 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
1986
1987 /* negative cum_len signifies to the
1988 * send loop that we are still in the
1989 * header portion of the TSO packet.
1990 * TSO header must be at most 134 bytes long */
1991 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1992
1993 /* for TSO, pseudo_hdr_offset holds mss.
1994 * The firmware figures out where to put
1995 * the checksum by parsing the header. */
1996 pseudo_hdr_offset = mss;
1997 } else
1998 #endif /*NETIF_F_TSO */
1999 /* Mark small packets, and pad out tiny packets */
2000 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2001 flags |= MXGEFW_FLAGS_SMALL;
2002
2003 /* pad frames to at least ETH_ZLEN bytes */
2004 if (unlikely(skb->len < ETH_ZLEN)) {
2005 if (skb_padto(skb, ETH_ZLEN)) {
2006 /* The packet is gone, so we must
2007 * return 0 */
2008 mgp->stats.tx_dropped += 1;
2009 return 0;
2010 }
2011 /* adjust the len to account for the zero pad
2012 * so that the nic can know how long it is */
2013 skb->len = ETH_ZLEN;
2014 }
2015 }
2016
2017 /* map the skb for DMA */
2018 len = skb->len - skb->data_len;
2019 idx = tx->req & tx->mask;
2020 tx->info[idx].skb = skb;
2021 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2022 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2023 pci_unmap_len_set(&tx->info[idx], len, len);
2024
2025 frag_cnt = skb_shinfo(skb)->nr_frags;
2026 frag_idx = 0;
2027 count = 0;
2028 rdma_count = 0;
2029
2030 /* "rdma_count" is the number of RDMAs belonging to the
2031 * current packet BEFORE the current send request. For
2032 * non-TSO packets, this is equal to "count".
2033 * For TSO packets, rdma_count needs to be reset
2034 * to 0 after a segment cut.
2035 *
2036 * The rdma_count field of the send request is
2037 * the number of RDMAs of the packet starting at
2038 * that request. For TSO send requests with one ore more cuts
2039 * in the middle, this is the number of RDMAs starting
2040 * after the last cut in the request. All previous
2041 * segments before the last cut implicitly have 1 RDMA.
2042 *
2043 * Since the number of RDMAs is not known beforehand,
2044 * it must be filled-in retroactively - after each
2045 * segmentation cut or at the end of the entire packet.
2046 */
2047
2048 while (1) {
2049 /* Break the SKB or Fragment up into pieces which
2050 * do not cross mgp->tx.boundary */
2051 low = MYRI10GE_LOWPART_TO_U32(bus);
2052 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2053 while (len) {
2054 u8 flags_next;
2055 int cum_len_next;
2056
2057 if (unlikely(count == max_segments))
2058 goto abort_linearize;
2059
2060 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2061 seglen = boundary - low;
2062 if (seglen > len)
2063 seglen = len;
2064 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2065 cum_len_next = cum_len + seglen;
2066 #ifdef NETIF_F_TSO
2067 if (mss) { /* TSO */
2068 (req - rdma_count)->rdma_count = rdma_count + 1;
2069
2070 if (likely(cum_len >= 0)) { /* payload */
2071 int next_is_first, chop;
2072
2073 chop = (cum_len_next > mss);
2074 cum_len_next = cum_len_next % mss;
2075 next_is_first = (cum_len_next == 0);
2076 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2077 flags_next |= next_is_first *
2078 MXGEFW_FLAGS_FIRST;
2079 rdma_count |= -(chop | next_is_first);
2080 rdma_count += chop & !next_is_first;
2081 } else if (likely(cum_len_next >= 0)) { /* header ends */
2082 int small;
2083
2084 rdma_count = -1;
2085 cum_len_next = 0;
2086 seglen = -cum_len;
2087 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2088 flags_next = MXGEFW_FLAGS_TSO_PLD |
2089 MXGEFW_FLAGS_FIRST |
2090 (small * MXGEFW_FLAGS_SMALL);
2091 }
2092 }
2093 #endif /* NETIF_F_TSO */
2094 req->addr_high = high_swapped;
2095 req->addr_low = htonl(low);
2096 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2097 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2098 req->rdma_count = 1;
2099 req->length = htons(seglen);
2100 req->cksum_offset = cksum_offset;
2101 req->flags = flags | ((cum_len & 1) * odd_flag);
2102
2103 low += seglen;
2104 len -= seglen;
2105 cum_len = cum_len_next;
2106 flags = flags_next;
2107 req++;
2108 count++;
2109 rdma_count++;
2110 if (unlikely(cksum_offset > seglen))
2111 cksum_offset -= seglen;
2112 else
2113 cksum_offset = 0;
2114 }
2115 if (frag_idx == frag_cnt)
2116 break;
2117
2118 /* map next fragment for DMA */
2119 idx = (count + tx->req) & tx->mask;
2120 frag = &skb_shinfo(skb)->frags[frag_idx];
2121 frag_idx++;
2122 len = frag->size;
2123 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2124 len, PCI_DMA_TODEVICE);
2125 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2126 pci_unmap_len_set(&tx->info[idx], len, len);
2127 }
2128
2129 (req - rdma_count)->rdma_count = rdma_count;
2130 #ifdef NETIF_F_TSO
2131 if (mss)
2132 do {
2133 req--;
2134 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2135 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2136 MXGEFW_FLAGS_FIRST)));
2137 #endif
2138 idx = ((count - 1) + tx->req) & tx->mask;
2139 tx->info[idx].last = 1;
2140 if (tx->wc_fifo == NULL)
2141 myri10ge_submit_req(tx, tx->req_list, count);
2142 else
2143 myri10ge_submit_req_wc(tx, tx->req_list, count);
2144 tx->pkt_start++;
2145 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2146 mgp->stop_queue++;
2147 netif_stop_queue(dev);
2148 }
2149 dev->trans_start = jiffies;
2150 return 0;
2151
2152 abort_linearize:
2153 /* Free any DMA resources we've alloced and clear out the skb
2154 * slot so as to not trip up assertions, and to avoid a
2155 * double-free if linearizing fails */
2156
2157 last_idx = (idx + 1) & tx->mask;
2158 idx = tx->req & tx->mask;
2159 tx->info[idx].skb = NULL;
2160 do {
2161 len = pci_unmap_len(&tx->info[idx], len);
2162 if (len) {
2163 if (tx->info[idx].skb != NULL)
2164 pci_unmap_single(mgp->pdev,
2165 pci_unmap_addr(&tx->info[idx],
2166 bus), len,
2167 PCI_DMA_TODEVICE);
2168 else
2169 pci_unmap_page(mgp->pdev,
2170 pci_unmap_addr(&tx->info[idx],
2171 bus), len,
2172 PCI_DMA_TODEVICE);
2173 pci_unmap_len_set(&tx->info[idx], len, 0);
2174 tx->info[idx].skb = NULL;
2175 }
2176 idx = (idx + 1) & tx->mask;
2177 } while (idx != last_idx);
2178 if (skb_is_gso(skb)) {
2179 printk(KERN_ERR
2180 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2181 mgp->dev->name);
2182 goto drop;
2183 }
2184
2185 if (skb_linearize(skb))
2186 goto drop;
2187
2188 mgp->tx_linearized++;
2189 goto again;
2190
2191 drop:
2192 dev_kfree_skb_any(skb);
2193 mgp->stats.tx_dropped += 1;
2194 return 0;
2195
2196 }
2197
2198 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2199 {
2200 struct myri10ge_priv *mgp = netdev_priv(dev);
2201 return &mgp->stats;
2202 }
2203
2204 static void myri10ge_set_multicast_list(struct net_device *dev)
2205 {
2206 struct myri10ge_cmd cmd;
2207 struct myri10ge_priv *mgp;
2208 struct dev_mc_list *mc_list;
2209 __be32 data[2] = {0, 0};
2210 int err;
2211
2212 mgp = netdev_priv(dev);
2213 /* can be called from atomic contexts,
2214 * pass 1 to force atomicity in myri10ge_send_cmd() */
2215 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2216
2217 /* This firmware is known to not support multicast */
2218 if (!mgp->fw_multicast_support)
2219 return;
2220
2221 /* Disable multicast filtering */
2222
2223 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2224 if (err != 0) {
2225 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2226 " error status: %d\n", dev->name, err);
2227 goto abort;
2228 }
2229
2230 if (dev->flags & IFF_ALLMULTI) {
2231 /* request to disable multicast filtering, so quit here */
2232 return;
2233 }
2234
2235 /* Flush the filters */
2236
2237 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2238 &cmd, 1);
2239 if (err != 0) {
2240 printk(KERN_ERR
2241 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2242 ", error status: %d\n", dev->name, err);
2243 goto abort;
2244 }
2245
2246 /* Walk the multicast list, and add each address */
2247 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2248 memcpy(data, &mc_list->dmi_addr, 6);
2249 cmd.data0 = ntohl(data[0]);
2250 cmd.data1 = ntohl(data[1]);
2251 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2252 &cmd, 1);
2253
2254 if (err != 0) {
2255 printk(KERN_ERR "myri10ge: %s: Failed "
2256 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2257 "%d\t", dev->name, err);
2258 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2259 ((unsigned char *)&mc_list->dmi_addr)[0],
2260 ((unsigned char *)&mc_list->dmi_addr)[1],
2261 ((unsigned char *)&mc_list->dmi_addr)[2],
2262 ((unsigned char *)&mc_list->dmi_addr)[3],
2263 ((unsigned char *)&mc_list->dmi_addr)[4],
2264 ((unsigned char *)&mc_list->dmi_addr)[5]
2265 );
2266 goto abort;
2267 }
2268 }
2269 /* Enable multicast filtering */
2270 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2271 if (err != 0) {
2272 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2273 "error status: %d\n", dev->name, err);
2274 goto abort;
2275 }
2276
2277 return;
2278
2279 abort:
2280 return;
2281 }
2282
2283 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2284 {
2285 struct sockaddr *sa = addr;
2286 struct myri10ge_priv *mgp = netdev_priv(dev);
2287 int status;
2288
2289 if (!is_valid_ether_addr(sa->sa_data))
2290 return -EADDRNOTAVAIL;
2291
2292 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2293 if (status != 0) {
2294 printk(KERN_ERR
2295 "myri10ge: %s: changing mac address failed with %d\n",
2296 dev->name, status);
2297 return status;
2298 }
2299
2300 /* change the dev structure */
2301 memcpy(dev->dev_addr, sa->sa_data, 6);
2302 return 0;
2303 }
2304
2305 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2306 {
2307 struct myri10ge_priv *mgp = netdev_priv(dev);
2308 int error = 0;
2309
2310 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2311 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2312 dev->name, new_mtu);
2313 return -EINVAL;
2314 }
2315 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2316 dev->name, dev->mtu, new_mtu);
2317 if (mgp->running) {
2318 /* if we change the mtu on an active device, we must
2319 * reset the device so the firmware sees the change */
2320 myri10ge_close(dev);
2321 dev->mtu = new_mtu;
2322 myri10ge_open(dev);
2323 } else
2324 dev->mtu = new_mtu;
2325
2326 return error;
2327 }
2328
2329 /*
2330 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2331 * Only do it if the bridge is a root port since we don't want to disturb
2332 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2333 */
2334
2335 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2336 {
2337 struct pci_dev *bridge = mgp->pdev->bus->self;
2338 struct device *dev = &mgp->pdev->dev;
2339 unsigned cap;
2340 unsigned err_cap;
2341 u16 val;
2342 u8 ext_type;
2343 int ret;
2344
2345 if (!myri10ge_ecrc_enable || !bridge)
2346 return;
2347
2348 /* check that the bridge is a root port */
2349 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2350 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2351 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2352 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2353 if (myri10ge_ecrc_enable > 1) {
2354 struct pci_dev *old_bridge = bridge;
2355
2356 /* Walk the hierarchy up to the root port
2357 * where ECRC has to be enabled */
2358 do {
2359 bridge = bridge->bus->self;
2360 if (!bridge) {
2361 dev_err(dev,
2362 "Failed to find root port"
2363 " to force ECRC\n");
2364 return;
2365 }
2366 cap =
2367 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2368 pci_read_config_word(bridge,
2369 cap + PCI_CAP_FLAGS, &val);
2370 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2371 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2372
2373 dev_info(dev,
2374 "Forcing ECRC on non-root port %s"
2375 " (enabling on root port %s)\n",
2376 pci_name(old_bridge), pci_name(bridge));
2377 } else {
2378 dev_err(dev,
2379 "Not enabling ECRC on non-root port %s\n",
2380 pci_name(bridge));
2381 return;
2382 }
2383 }
2384
2385 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2386 if (!cap)
2387 return;
2388
2389 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2390 if (ret) {
2391 dev_err(dev, "failed reading ext-conf-space of %s\n",
2392 pci_name(bridge));
2393 dev_err(dev, "\t pci=nommconf in use? "
2394 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2395 return;
2396 }
2397 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2398 return;
2399
2400 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2401 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2402 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2403 mgp->tx.boundary = 4096;
2404 mgp->fw_name = myri10ge_fw_aligned;
2405 }
2406
2407 /*
2408 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2409 * when the PCI-E Completion packets are aligned on an 8-byte
2410 * boundary. Some PCI-E chip sets always align Completion packets; on
2411 * the ones that do not, the alignment can be enforced by enabling
2412 * ECRC generation (if supported).
2413 *
2414 * When PCI-E Completion packets are not aligned, it is actually more
2415 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2416 *
2417 * If the driver can neither enable ECRC nor verify that it has
2418 * already been enabled, then it must use a firmware image which works
2419 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2420 * should also ensure that it never gives the device a Read-DMA which is
2421 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2422 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2423 * firmware image, and set tx.boundary to 4KB.
2424 */
2425
2426 #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2427 #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2428
2429 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2430 {
2431 struct pci_dev *bridge = mgp->pdev->bus->self;
2432
2433 mgp->tx.boundary = 2048;
2434 mgp->fw_name = myri10ge_fw_unaligned;
2435
2436 if (myri10ge_force_firmware == 0) {
2437 int link_width, exp_cap;
2438 u16 lnk;
2439
2440 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2441 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2442 link_width = (lnk >> 4) & 0x3f;
2443
2444 myri10ge_enable_ecrc(mgp);
2445
2446 /* Check to see if Link is less than 8 or if the
2447 * upstream bridge is known to provide aligned
2448 * completions */
2449 if (link_width < 8) {
2450 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2451 link_width);
2452 mgp->tx.boundary = 4096;
2453 mgp->fw_name = myri10ge_fw_aligned;
2454 } else if (bridge &&
2455 /* ServerWorks HT2000/HT1000 */
2456 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2457 && bridge->device ==
2458 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2459 /* All Intel E5000 PCIE ports */
2460 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2461 && bridge->device >=
2462 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2463 && bridge->device <=
2464 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
2465 dev_info(&mgp->pdev->dev,
2466 "Assuming aligned completions (0x%x:0x%x)\n",
2467 bridge->vendor, bridge->device);
2468 mgp->tx.boundary = 4096;
2469 mgp->fw_name = myri10ge_fw_aligned;
2470 }
2471 } else {
2472 if (myri10ge_force_firmware == 1) {
2473 dev_info(&mgp->pdev->dev,
2474 "Assuming aligned completions (forced)\n");
2475 mgp->tx.boundary = 4096;
2476 mgp->fw_name = myri10ge_fw_aligned;
2477 } else {
2478 dev_info(&mgp->pdev->dev,
2479 "Assuming unaligned completions (forced)\n");
2480 mgp->tx.boundary = 2048;
2481 mgp->fw_name = myri10ge_fw_unaligned;
2482 }
2483 }
2484 if (myri10ge_fw_name != NULL) {
2485 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2486 myri10ge_fw_name);
2487 mgp->fw_name = myri10ge_fw_name;
2488 }
2489 }
2490
2491 static void myri10ge_save_state(struct myri10ge_priv *mgp)
2492 {
2493 struct pci_dev *pdev = mgp->pdev;
2494 int cap;
2495
2496 pci_save_state(pdev);
2497 /* now save PCIe and MSI state that Linux will not
2498 * save for us */
2499 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2500 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2501 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2502 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2503 }
2504
2505 static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2506 {
2507 struct pci_dev *pdev = mgp->pdev;
2508 int cap;
2509
2510 /* restore PCIe and MSI state that linux will not */
2511 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2512 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2513 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2514 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2515
2516 pci_restore_state(pdev);
2517 }
2518
2519 #ifdef CONFIG_PM
2520
2521 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2522 {
2523 struct myri10ge_priv *mgp;
2524 struct net_device *netdev;
2525
2526 mgp = pci_get_drvdata(pdev);
2527 if (mgp == NULL)
2528 return -EINVAL;
2529 netdev = mgp->dev;
2530
2531 netif_device_detach(netdev);
2532 if (netif_running(netdev)) {
2533 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2534 rtnl_lock();
2535 myri10ge_close(netdev);
2536 rtnl_unlock();
2537 }
2538 myri10ge_dummy_rdma(mgp, 0);
2539 free_irq(pdev->irq, mgp);
2540 myri10ge_save_state(mgp);
2541 pci_disable_device(pdev);
2542 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2543 return 0;
2544 }
2545
2546 static int myri10ge_resume(struct pci_dev *pdev)
2547 {
2548 struct myri10ge_priv *mgp;
2549 struct net_device *netdev;
2550 int status;
2551 u16 vendor;
2552
2553 mgp = pci_get_drvdata(pdev);
2554 if (mgp == NULL)
2555 return -EINVAL;
2556 netdev = mgp->dev;
2557 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2558 msleep(5); /* give card time to respond */
2559 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2560 if (vendor == 0xffff) {
2561 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2562 mgp->dev->name);
2563 return -EIO;
2564 }
2565 myri10ge_restore_state(mgp);
2566
2567 status = pci_enable_device(pdev);
2568 if (status < 0) {
2569 dev_err(&pdev->dev, "failed to enable device\n");
2570 return -EIO;
2571 }
2572
2573 pci_set_master(pdev);
2574
2575 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2576 netdev->name, mgp);
2577 if (status != 0) {
2578 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2579 goto abort_with_enabled;
2580 }
2581
2582 myri10ge_reset(mgp);
2583 myri10ge_dummy_rdma(mgp, 1);
2584
2585 /* Save configuration space to be restored if the
2586 * nic resets due to a parity error */
2587 myri10ge_save_state(mgp);
2588
2589 if (netif_running(netdev)) {
2590 rtnl_lock();
2591 myri10ge_open(netdev);
2592 rtnl_unlock();
2593 }
2594 netif_device_attach(netdev);
2595
2596 return 0;
2597
2598 abort_with_enabled:
2599 pci_disable_device(pdev);
2600 return -EIO;
2601
2602 }
2603
2604 #endif /* CONFIG_PM */
2605
2606 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2607 {
2608 struct pci_dev *pdev = mgp->pdev;
2609 int vs = mgp->vendor_specific_offset;
2610 u32 reboot;
2611
2612 /*enter read32 mode */
2613 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2614
2615 /*read REBOOT_STATUS (0xfffffff0) */
2616 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2617 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2618 return reboot;
2619 }
2620
2621 /*
2622 * This watchdog is used to check whether the board has suffered
2623 * from a parity error and needs to be recovered.
2624 */
2625 static void myri10ge_watchdog(struct work_struct *work)
2626 {
2627 struct myri10ge_priv *mgp =
2628 container_of(work, struct myri10ge_priv, watchdog_work);
2629 u32 reboot;
2630 int status;
2631 u16 cmd, vendor;
2632
2633 mgp->watchdog_resets++;
2634 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2635 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2636 /* Bus master DMA disabled? Check to see
2637 * if the card rebooted due to a parity error
2638 * For now, just report it */
2639 reboot = myri10ge_read_reboot(mgp);
2640 printk(KERN_ERR
2641 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2642 mgp->dev->name, reboot);
2643 /*
2644 * A rebooted nic will come back with config space as
2645 * it was after power was applied to PCIe bus.
2646 * Attempt to restore config space which was saved
2647 * when the driver was loaded, or the last time the
2648 * nic was resumed from power saving mode.
2649 */
2650 myri10ge_restore_state(mgp);
2651 } else {
2652 /* if we get back -1's from our slot, perhaps somebody
2653 * powered off our card. Don't try to reset it in
2654 * this case */
2655 if (cmd == 0xffff) {
2656 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2657 if (vendor == 0xffff) {
2658 printk(KERN_ERR
2659 "myri10ge: %s: device disappeared!\n",
2660 mgp->dev->name);
2661 return;
2662 }
2663 }
2664 /* Perhaps it is a software error. Try to reset */
2665
2666 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2667 mgp->dev->name);
2668 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2669 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2670 mgp->tx.pkt_start, mgp->tx.pkt_done,
2671 (int)ntohl(mgp->fw_stats->send_done_count));
2672 msleep(2000);
2673 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2674 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2675 mgp->tx.pkt_start, mgp->tx.pkt_done,
2676 (int)ntohl(mgp->fw_stats->send_done_count));
2677 }
2678 rtnl_lock();
2679 myri10ge_close(mgp->dev);
2680 status = myri10ge_load_firmware(mgp);
2681 if (status != 0)
2682 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2683 mgp->dev->name);
2684 else
2685 myri10ge_open(mgp->dev);
2686 rtnl_unlock();
2687 }
2688
2689 /*
2690 * We use our own timer routine rather than relying upon
2691 * netdev->tx_timeout because we have a very large hardware transmit
2692 * queue. Due to the large queue, the netdev->tx_timeout function
2693 * cannot detect a NIC with a parity error in a timely fashion if the
2694 * NIC is lightly loaded.
2695 */
2696 static void myri10ge_watchdog_timer(unsigned long arg)
2697 {
2698 struct myri10ge_priv *mgp;
2699
2700 mgp = (struct myri10ge_priv *)arg;
2701 if (mgp->tx.req != mgp->tx.done &&
2702 mgp->tx.done == mgp->watchdog_tx_done &&
2703 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2704 /* nic seems like it might be stuck.. */
2705 schedule_work(&mgp->watchdog_work);
2706 else
2707 /* rearm timer */
2708 mod_timer(&mgp->watchdog_timer,
2709 jiffies + myri10ge_watchdog_timeout * HZ);
2710
2711 mgp->watchdog_tx_done = mgp->tx.done;
2712 mgp->watchdog_tx_req = mgp->tx.req;
2713 }
2714
2715 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2716 {
2717 struct net_device *netdev;
2718 struct myri10ge_priv *mgp;
2719 struct device *dev = &pdev->dev;
2720 size_t bytes;
2721 int i;
2722 int status = -ENXIO;
2723 int cap;
2724 int dac_enabled;
2725 u16 val;
2726
2727 netdev = alloc_etherdev(sizeof(*mgp));
2728 if (netdev == NULL) {
2729 dev_err(dev, "Could not allocate ethernet device\n");
2730 return -ENOMEM;
2731 }
2732
2733 mgp = netdev_priv(netdev);
2734 memset(mgp, 0, sizeof(*mgp));
2735 mgp->dev = netdev;
2736 mgp->pdev = pdev;
2737 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2738 mgp->pause = myri10ge_flow_control;
2739 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2740 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2741 init_waitqueue_head(&mgp->down_wq);
2742
2743 if (pci_enable_device(pdev)) {
2744 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2745 status = -ENODEV;
2746 goto abort_with_netdev;
2747 }
2748 myri10ge_select_firmware(mgp);
2749
2750 /* Find the vendor-specific cap so we can check
2751 * the reboot register later on */
2752 mgp->vendor_specific_offset
2753 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2754
2755 /* Set our max read request to 4KB */
2756 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2757 if (cap < 64) {
2758 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2759 goto abort_with_netdev;
2760 }
2761 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2762 if (status != 0) {
2763 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2764 status);
2765 goto abort_with_netdev;
2766 }
2767 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2768 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2769 if (status != 0) {
2770 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2771 status);
2772 goto abort_with_netdev;
2773 }
2774
2775 pci_set_master(pdev);
2776 dac_enabled = 1;
2777 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2778 if (status != 0) {
2779 dac_enabled = 0;
2780 dev_err(&pdev->dev,
2781 "64-bit pci address mask was refused, trying 32-bit");
2782 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2783 }
2784 if (status != 0) {
2785 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2786 goto abort_with_netdev;
2787 }
2788 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2789 &mgp->cmd_bus, GFP_KERNEL);
2790 if (mgp->cmd == NULL)
2791 goto abort_with_netdev;
2792
2793 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2794 &mgp->fw_stats_bus, GFP_KERNEL);
2795 if (mgp->fw_stats == NULL)
2796 goto abort_with_cmd;
2797
2798 mgp->board_span = pci_resource_len(pdev, 0);
2799 mgp->iomem_base = pci_resource_start(pdev, 0);
2800 mgp->mtrr = -1;
2801 #ifdef CONFIG_MTRR
2802 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2803 MTRR_TYPE_WRCOMB, 1);
2804 #endif
2805 /* Hack. need to get rid of these magic numbers */
2806 mgp->sram_size =
2807 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2808 if (mgp->sram_size > mgp->board_span) {
2809 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2810 mgp->board_span);
2811 goto abort_with_wc;
2812 }
2813 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2814 if (mgp->sram == NULL) {
2815 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2816 mgp->board_span, mgp->iomem_base);
2817 status = -ENXIO;
2818 goto abort_with_wc;
2819 }
2820 memcpy_fromio(mgp->eeprom_strings,
2821 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2822 MYRI10GE_EEPROM_STRINGS_SIZE);
2823 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2824 status = myri10ge_read_mac_addr(mgp);
2825 if (status)
2826 goto abort_with_ioremap;
2827
2828 for (i = 0; i < ETH_ALEN; i++)
2829 netdev->dev_addr[i] = mgp->mac_addr[i];
2830
2831 /* allocate rx done ring */
2832 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2833 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2834 &mgp->rx_done.bus, GFP_KERNEL);
2835 if (mgp->rx_done.entry == NULL)
2836 goto abort_with_ioremap;
2837 memset(mgp->rx_done.entry, 0, bytes);
2838
2839 status = myri10ge_load_firmware(mgp);
2840 if (status != 0) {
2841 dev_err(&pdev->dev, "failed to load firmware\n");
2842 goto abort_with_rx_done;
2843 }
2844
2845 status = myri10ge_reset(mgp);
2846 if (status != 0) {
2847 dev_err(&pdev->dev, "failed reset\n");
2848 goto abort_with_firmware;
2849 }
2850
2851 if (myri10ge_msi) {
2852 status = pci_enable_msi(pdev);
2853 if (status != 0)
2854 dev_err(&pdev->dev,
2855 "Error %d setting up MSI; falling back to xPIC\n",
2856 status);
2857 else
2858 mgp->msi_enabled = 1;
2859 }
2860
2861 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2862 netdev->name, mgp);
2863 if (status != 0) {
2864 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2865 goto abort_with_firmware;
2866 }
2867
2868 pci_set_drvdata(pdev, mgp);
2869 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2870 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2871 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2872 myri10ge_initial_mtu = 68;
2873 netdev->mtu = myri10ge_initial_mtu;
2874 netdev->open = myri10ge_open;
2875 netdev->stop = myri10ge_close;
2876 netdev->hard_start_xmit = myri10ge_xmit;
2877 netdev->get_stats = myri10ge_get_stats;
2878 netdev->base_addr = mgp->iomem_base;
2879 netdev->irq = pdev->irq;
2880 netdev->change_mtu = myri10ge_change_mtu;
2881 netdev->set_multicast_list = myri10ge_set_multicast_list;
2882 netdev->set_mac_address = myri10ge_set_mac_address;
2883 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2884 if (dac_enabled)
2885 netdev->features |= NETIF_F_HIGHDMA;
2886 netdev->poll = myri10ge_poll;
2887 netdev->weight = myri10ge_napi_weight;
2888
2889 /* Save configuration space to be restored if the
2890 * nic resets due to a parity error */
2891 myri10ge_save_state(mgp);
2892
2893 /* Setup the watchdog timer */
2894 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2895 (unsigned long)mgp);
2896
2897 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2898 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
2899 status = register_netdev(netdev);
2900 if (status != 0) {
2901 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2902 goto abort_with_irq;
2903 }
2904 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2905 (mgp->msi_enabled ? "MSI" : "xPIC"),
2906 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2907 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2908
2909 return 0;
2910
2911 abort_with_irq:
2912 free_irq(pdev->irq, mgp);
2913 if (mgp->msi_enabled)
2914 pci_disable_msi(pdev);
2915
2916 abort_with_firmware:
2917 myri10ge_dummy_rdma(mgp, 0);
2918
2919 abort_with_rx_done:
2920 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2921 dma_free_coherent(&pdev->dev, bytes,
2922 mgp->rx_done.entry, mgp->rx_done.bus);
2923
2924 abort_with_ioremap:
2925 iounmap(mgp->sram);
2926
2927 abort_with_wc:
2928 #ifdef CONFIG_MTRR
2929 if (mgp->mtrr >= 0)
2930 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2931 #endif
2932 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2933 mgp->fw_stats, mgp->fw_stats_bus);
2934
2935 abort_with_cmd:
2936 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2937 mgp->cmd, mgp->cmd_bus);
2938
2939 abort_with_netdev:
2940
2941 free_netdev(netdev);
2942 return status;
2943 }
2944
2945 /*
2946 * myri10ge_remove
2947 *
2948 * Does what is necessary to shutdown one Myrinet device. Called
2949 * once for each Myrinet card by the kernel when a module is
2950 * unloaded.
2951 */
2952 static void myri10ge_remove(struct pci_dev *pdev)
2953 {
2954 struct myri10ge_priv *mgp;
2955 struct net_device *netdev;
2956 size_t bytes;
2957
2958 mgp = pci_get_drvdata(pdev);
2959 if (mgp == NULL)
2960 return;
2961
2962 flush_scheduled_work();
2963 netdev = mgp->dev;
2964 unregister_netdev(netdev);
2965 free_irq(pdev->irq, mgp);
2966 if (mgp->msi_enabled)
2967 pci_disable_msi(pdev);
2968
2969 myri10ge_dummy_rdma(mgp, 0);
2970
2971 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2972 dma_free_coherent(&pdev->dev, bytes,
2973 mgp->rx_done.entry, mgp->rx_done.bus);
2974
2975 iounmap(mgp->sram);
2976
2977 #ifdef CONFIG_MTRR
2978 if (mgp->mtrr >= 0)
2979 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2980 #endif
2981 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2982 mgp->fw_stats, mgp->fw_stats_bus);
2983
2984 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2985 mgp->cmd, mgp->cmd_bus);
2986
2987 free_netdev(netdev);
2988 pci_set_drvdata(pdev, NULL);
2989 }
2990
2991 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
2992
2993 static struct pci_device_id myri10ge_pci_tbl[] = {
2994 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
2995 {0},
2996 };
2997
2998 static struct pci_driver myri10ge_driver = {
2999 .name = "myri10ge",
3000 .probe = myri10ge_probe,
3001 .remove = myri10ge_remove,
3002 .id_table = myri10ge_pci_tbl,
3003 #ifdef CONFIG_PM
3004 .suspend = myri10ge_suspend,
3005 .resume = myri10ge_resume,
3006 #endif
3007 };
3008
3009 static __init int myri10ge_init_module(void)
3010 {
3011 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3012 MYRI10GE_VERSION_STR);
3013 return pci_register_driver(&myri10ge_driver);
3014 }
3015
3016 module_init(myri10ge_init_module);
3017
3018 static __exit void myri10ge_cleanup_module(void)
3019 {
3020 pci_unregister_driver(&myri10ge_driver);
3021 }
3022
3023 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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