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Merge branch 'upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/linville...
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.0.0"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA 0xffffffff
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 struct myri10ge_rx_buffer_state {
96 struct sk_buff *skb;
97 DECLARE_PCI_UNMAP_ADDR(bus)
98 DECLARE_PCI_UNMAP_LEN(len)
99 };
100
101 struct myri10ge_tx_buffer_state {
102 struct sk_buff *skb;
103 int last;
104 DECLARE_PCI_UNMAP_ADDR(bus)
105 DECLARE_PCI_UNMAP_LEN(len)
106 };
107
108 struct myri10ge_cmd {
109 u32 data0;
110 u32 data1;
111 u32 data2;
112 };
113
114 struct myri10ge_rx_buf {
115 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
116 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
117 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
118 struct myri10ge_rx_buffer_state *info;
119 int cnt;
120 int alloc_fail;
121 int mask; /* number of rx slots -1 */
122 };
123
124 struct myri10ge_tx_buf {
125 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
126 u8 __iomem *wc_fifo; /* w/c send fifo address */
127 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
128 char *req_bytes;
129 struct myri10ge_tx_buffer_state *info;
130 int mask; /* number of transmit slots -1 */
131 int boundary; /* boundary transmits cannot cross */
132 int req ____cacheline_aligned; /* transmit slots submitted */
133 int pkt_start; /* packets started */
134 int done ____cacheline_aligned; /* transmit slots completed */
135 int pkt_done; /* packets completed */
136 };
137
138 struct myri10ge_rx_done {
139 struct mcp_slot *entry;
140 dma_addr_t bus;
141 int cnt;
142 int idx;
143 };
144
145 struct myri10ge_priv {
146 int running; /* running? */
147 int csum_flag; /* rx_csums? */
148 struct myri10ge_tx_buf tx; /* transmit ring */
149 struct myri10ge_rx_buf rx_small;
150 struct myri10ge_rx_buf rx_big;
151 struct myri10ge_rx_done rx_done;
152 int small_bytes;
153 struct net_device *dev;
154 struct net_device_stats stats;
155 u8 __iomem *sram;
156 int sram_size;
157 unsigned long board_span;
158 unsigned long iomem_base;
159 u32 __iomem *irq_claim;
160 u32 __iomem *irq_deassert;
161 char *mac_addr_string;
162 struct mcp_cmd_response *cmd;
163 dma_addr_t cmd_bus;
164 struct mcp_irq_data *fw_stats;
165 dma_addr_t fw_stats_bus;
166 struct pci_dev *pdev;
167 int msi_enabled;
168 unsigned int link_state;
169 unsigned int rdma_tags_available;
170 int intr_coal_delay;
171 u32 __iomem *intr_coal_delay_ptr;
172 int mtrr;
173 int wake_queue;
174 int stop_queue;
175 int down_cnt;
176 wait_queue_head_t down_wq;
177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer;
179 int watchdog_tx_done;
180 int watchdog_tx_req;
181 int watchdog_resets;
182 int tx_linearized;
183 int pause;
184 char *fw_name;
185 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
186 char fw_version[128];
187 u8 mac_addr[6]; /* eeprom mac address */
188 unsigned long serial_number;
189 int vendor_specific_offset;
190 u32 devctl;
191 u16 msi_flags;
192 u32 read_dma;
193 u32 write_dma;
194 u32 read_write_dma;
195 };
196
197 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
198 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
199
200 static char *myri10ge_fw_name = NULL;
201 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
202 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
203
204 static int myri10ge_ecrc_enable = 1;
205 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
206 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
207
208 static int myri10ge_max_intr_slots = 1024;
209 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
210 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
211
212 static int myri10ge_small_bytes = -1; /* -1 == auto */
213 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
214 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
215
216 static int myri10ge_msi = 1; /* enable msi by default */
217 module_param(myri10ge_msi, int, S_IRUGO);
218 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
219
220 static int myri10ge_intr_coal_delay = 25;
221 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
222 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
223
224 static int myri10ge_flow_control = 1;
225 module_param(myri10ge_flow_control, int, S_IRUGO);
226 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
227
228 static int myri10ge_deassert_wait = 1;
229 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
230 MODULE_PARM_DESC(myri10ge_deassert_wait,
231 "Wait when deasserting legacy interrupts\n");
232
233 static int myri10ge_force_firmware = 0;
234 module_param(myri10ge_force_firmware, int, S_IRUGO);
235 MODULE_PARM_DESC(myri10ge_force_firmware,
236 "Force firmware to assume aligned completions\n");
237
238 static int myri10ge_skb_cross_4k = 0;
239 module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR);
240 MODULE_PARM_DESC(myri10ge_skb_cross_4k,
241 "Can a small skb cross a 4KB boundary?\n");
242
243 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
244 module_param(myri10ge_initial_mtu, int, S_IRUGO);
245 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
246
247 static int myri10ge_napi_weight = 64;
248 module_param(myri10ge_napi_weight, int, S_IRUGO);
249 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
250
251 static int myri10ge_watchdog_timeout = 1;
252 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
253 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
254
255 static int myri10ge_max_irq_loops = 1048576;
256 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
257 MODULE_PARM_DESC(myri10ge_max_irq_loops,
258 "Set stuck legacy IRQ detection threshold\n");
259
260 #define MYRI10GE_FW_OFFSET 1024*1024
261 #define MYRI10GE_HIGHPART_TO_U32(X) \
262 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
263 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
264
265 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
266
267 static int
268 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
269 struct myri10ge_cmd *data, int atomic)
270 {
271 struct mcp_cmd *buf;
272 char buf_bytes[sizeof(*buf) + 8];
273 struct mcp_cmd_response *response = mgp->cmd;
274 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
275 u32 dma_low, dma_high, result, value;
276 int sleep_total = 0;
277
278 /* ensure buf is aligned to 8 bytes */
279 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
280
281 buf->data0 = htonl(data->data0);
282 buf->data1 = htonl(data->data1);
283 buf->data2 = htonl(data->data2);
284 buf->cmd = htonl(cmd);
285 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
286 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
287
288 buf->response_addr.low = htonl(dma_low);
289 buf->response_addr.high = htonl(dma_high);
290 response->result = MYRI10GE_NO_RESPONSE_RESULT;
291 mb();
292 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
293
294 /* wait up to 15ms. Longest command is the DMA benchmark,
295 * which is capped at 5ms, but runs from a timeout handler
296 * that runs every 7.8ms. So a 15ms timeout leaves us with
297 * a 2.2ms margin
298 */
299 if (atomic) {
300 /* if atomic is set, do not sleep,
301 * and try to get the completion quickly
302 * (1ms will be enough for those commands) */
303 for (sleep_total = 0;
304 sleep_total < 1000
305 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
306 sleep_total += 10)
307 udelay(10);
308 } else {
309 /* use msleep for most command */
310 for (sleep_total = 0;
311 sleep_total < 15
312 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
313 sleep_total++)
314 msleep(1);
315 }
316
317 result = ntohl(response->result);
318 value = ntohl(response->data);
319 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
320 if (result == 0) {
321 data->data0 = value;
322 return 0;
323 } else {
324 dev_err(&mgp->pdev->dev,
325 "command %d failed, result = %d\n",
326 cmd, result);
327 return -ENXIO;
328 }
329 }
330
331 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
332 cmd, result);
333 return -EAGAIN;
334 }
335
336 /*
337 * The eeprom strings on the lanaiX have the format
338 * SN=x\0
339 * MAC=x:x:x:x:x:x\0
340 * PT:ddd mmm xx xx:xx:xx xx\0
341 * PV:ddd mmm xx xx:xx:xx xx\0
342 */
343 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
344 {
345 char *ptr, *limit;
346 int i;
347
348 ptr = mgp->eeprom_strings;
349 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
350
351 while (*ptr != '\0' && ptr < limit) {
352 if (memcmp(ptr, "MAC=", 4) == 0) {
353 ptr += 4;
354 mgp->mac_addr_string = ptr;
355 for (i = 0; i < 6; i++) {
356 if ((ptr + 2) > limit)
357 goto abort;
358 mgp->mac_addr[i] =
359 simple_strtoul(ptr, &ptr, 16);
360 ptr += 1;
361 }
362 }
363 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
364 ptr += 3;
365 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
366 }
367 while (ptr < limit && *ptr++) ;
368 }
369
370 return 0;
371
372 abort:
373 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
374 return -ENXIO;
375 }
376
377 /*
378 * Enable or disable periodic RDMAs from the host to make certain
379 * chipsets resend dropped PCIe messages
380 */
381
382 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
383 {
384 char __iomem *submit;
385 u32 buf[16];
386 u32 dma_low, dma_high;
387 int i;
388
389 /* clear confirmation addr */
390 mgp->cmd->data = 0;
391 mb();
392
393 /* send a rdma command to the PCIe engine, and wait for the
394 * response in the confirmation address. The firmware should
395 * write a -1 there to indicate it is alive and well
396 */
397 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
398 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
399
400 buf[0] = htonl(dma_high); /* confirm addr MSW */
401 buf[1] = htonl(dma_low); /* confirm addr LSW */
402 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
403 buf[3] = htonl(dma_high); /* dummy addr MSW */
404 buf[4] = htonl(dma_low); /* dummy addr LSW */
405 buf[5] = htonl(enable); /* enable? */
406
407 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
408
409 myri10ge_pio_copy(submit, &buf, sizeof(buf));
410 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
411 msleep(1);
412 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
413 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
414 (enable ? "enable" : "disable"));
415 }
416
417 static int
418 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
419 struct mcp_gen_header *hdr)
420 {
421 struct device *dev = &mgp->pdev->dev;
422 int major, minor;
423
424 /* check firmware type */
425 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
426 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
427 return -EINVAL;
428 }
429
430 /* save firmware version for ethtool */
431 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
432
433 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
434
435 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
436 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
437 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
438 MXGEFW_VERSION_MINOR);
439 return -EINVAL;
440 }
441 return 0;
442 }
443
444 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
445 {
446 unsigned crc, reread_crc;
447 const struct firmware *fw;
448 struct device *dev = &mgp->pdev->dev;
449 struct mcp_gen_header *hdr;
450 size_t hdr_offset;
451 int status;
452 unsigned i;
453
454 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
455 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
456 mgp->fw_name);
457 status = -EINVAL;
458 goto abort_with_nothing;
459 }
460
461 /* check size */
462
463 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
464 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
465 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
466 status = -EINVAL;
467 goto abort_with_fw;
468 }
469
470 /* check id */
471 hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
472 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
473 dev_err(dev, "Bad firmware file\n");
474 status = -EINVAL;
475 goto abort_with_fw;
476 }
477 hdr = (void *)(fw->data + hdr_offset);
478
479 status = myri10ge_validate_firmware(mgp, hdr);
480 if (status != 0)
481 goto abort_with_fw;
482
483 crc = crc32(~0, fw->data, fw->size);
484 for (i = 0; i < fw->size; i += 256) {
485 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
486 fw->data + i,
487 min(256U, (unsigned)(fw->size - i)));
488 mb();
489 readb(mgp->sram);
490 }
491 /* corruption checking is good for parity recovery and buggy chipset */
492 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
493 reread_crc = crc32(~0, fw->data, fw->size);
494 if (crc != reread_crc) {
495 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
496 (unsigned)fw->size, reread_crc, crc);
497 status = -EIO;
498 goto abort_with_fw;
499 }
500 *size = (u32) fw->size;
501
502 abort_with_fw:
503 release_firmware(fw);
504
505 abort_with_nothing:
506 return status;
507 }
508
509 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
510 {
511 struct mcp_gen_header *hdr;
512 struct device *dev = &mgp->pdev->dev;
513 const size_t bytes = sizeof(struct mcp_gen_header);
514 size_t hdr_offset;
515 int status;
516
517 /* find running firmware header */
518 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
519
520 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
521 dev_err(dev, "Running firmware has bad header offset (%d)\n",
522 (int)hdr_offset);
523 return -EIO;
524 }
525
526 /* copy header of running firmware from SRAM to host memory to
527 * validate firmware */
528 hdr = kmalloc(bytes, GFP_KERNEL);
529 if (hdr == NULL) {
530 dev_err(dev, "could not malloc firmware hdr\n");
531 return -ENOMEM;
532 }
533 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
534 status = myri10ge_validate_firmware(mgp, hdr);
535 kfree(hdr);
536 return status;
537 }
538
539 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
540 {
541 char __iomem *submit;
542 u32 buf[16];
543 u32 dma_low, dma_high, size;
544 int status, i;
545
546 size = 0;
547 status = myri10ge_load_hotplug_firmware(mgp, &size);
548 if (status) {
549 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
550
551 /* Do not attempt to adopt firmware if there
552 * was a bad crc */
553 if (status == -EIO)
554 return status;
555
556 status = myri10ge_adopt_running_firmware(mgp);
557 if (status != 0) {
558 dev_err(&mgp->pdev->dev,
559 "failed to adopt running firmware\n");
560 return status;
561 }
562 dev_info(&mgp->pdev->dev,
563 "Successfully adopted running firmware\n");
564 if (mgp->tx.boundary == 4096) {
565 dev_warn(&mgp->pdev->dev,
566 "Using firmware currently running on NIC"
567 ". For optimal\n");
568 dev_warn(&mgp->pdev->dev,
569 "performance consider loading optimized "
570 "firmware\n");
571 dev_warn(&mgp->pdev->dev, "via hotplug\n");
572 }
573
574 mgp->fw_name = "adopted";
575 mgp->tx.boundary = 2048;
576 return status;
577 }
578
579 /* clear confirmation addr */
580 mgp->cmd->data = 0;
581 mb();
582
583 /* send a reload command to the bootstrap MCP, and wait for the
584 * response in the confirmation address. The firmware should
585 * write a -1 there to indicate it is alive and well
586 */
587 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
588 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
589
590 buf[0] = htonl(dma_high); /* confirm addr MSW */
591 buf[1] = htonl(dma_low); /* confirm addr LSW */
592 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
593
594 /* FIX: All newest firmware should un-protect the bottom of
595 * the sram before handoff. However, the very first interfaces
596 * do not. Therefore the handoff copy must skip the first 8 bytes
597 */
598 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
599 buf[4] = htonl(size - 8); /* length of code */
600 buf[5] = htonl(8); /* where to copy to */
601 buf[6] = htonl(0); /* where to jump to */
602
603 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
604
605 myri10ge_pio_copy(submit, &buf, sizeof(buf));
606 mb();
607 msleep(1);
608 mb();
609 i = 0;
610 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
611 msleep(1);
612 i++;
613 }
614 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
615 dev_err(&mgp->pdev->dev, "handoff failed\n");
616 return -ENXIO;
617 }
618 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
619 myri10ge_dummy_rdma(mgp, 1);
620
621 return 0;
622 }
623
624 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
625 {
626 struct myri10ge_cmd cmd;
627 int status;
628
629 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
630 | (addr[2] << 8) | addr[3]);
631
632 cmd.data1 = ((addr[4] << 8) | (addr[5]));
633
634 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
635 return status;
636 }
637
638 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
639 {
640 struct myri10ge_cmd cmd;
641 int status, ctl;
642
643 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
644 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
645
646 if (status) {
647 printk(KERN_ERR
648 "myri10ge: %s: Failed to set flow control mode\n",
649 mgp->dev->name);
650 return status;
651 }
652 mgp->pause = pause;
653 return 0;
654 }
655
656 static void
657 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
658 {
659 struct myri10ge_cmd cmd;
660 int status, ctl;
661
662 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
663 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
664 if (status)
665 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
666 mgp->dev->name);
667 }
668
669 static int myri10ge_reset(struct myri10ge_priv *mgp)
670 {
671 struct myri10ge_cmd cmd;
672 int status;
673 size_t bytes;
674 u32 len;
675
676 /* try to send a reset command to the card to see if it
677 * is alive */
678 memset(&cmd, 0, sizeof(cmd));
679 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
680 if (status != 0) {
681 dev_err(&mgp->pdev->dev, "failed reset\n");
682 return -ENXIO;
683 }
684
685 /* Now exchange information about interrupts */
686
687 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
688 memset(mgp->rx_done.entry, 0, bytes);
689 cmd.data0 = (u32) bytes;
690 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
691 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
692 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
693 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
694
695 status |=
696 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
697 mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0);
698 if (!mgp->msi_enabled) {
699 status |= myri10ge_send_cmd
700 (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
701 mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0);
702
703 }
704 status |= myri10ge_send_cmd
705 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
706 mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0);
707 if (status != 0) {
708 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
709 return status;
710 }
711 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
712
713 /* Run a small DMA test.
714 * The magic multipliers to the length tell the firmware
715 * to do DMA read, write, or read+write tests. The
716 * results are returned in cmd.data0. The upper 16
717 * bits or the return is the number of transfers completed.
718 * The lower 16 bits is the time in 0.5us ticks that the
719 * transfers took to complete.
720 */
721
722 len = mgp->tx.boundary;
723
724 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
725 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
726 cmd.data2 = len * 0x10000;
727 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
728 if (status == 0)
729 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
730 (cmd.data0 & 0xffff);
731 else
732 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
733 status);
734 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
735 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
736 cmd.data2 = len * 0x1;
737 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
738 if (status == 0)
739 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
740 (cmd.data0 & 0xffff);
741 else
742 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
743 status);
744
745 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
746 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
747 cmd.data2 = len * 0x10001;
748 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
749 if (status == 0)
750 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
751 (cmd.data0 & 0xffff);
752 else
753 dev_warn(&mgp->pdev->dev,
754 "DMA read/write benchmark failed: %d\n", status);
755
756 memset(mgp->rx_done.entry, 0, bytes);
757
758 /* reset mcp/driver shared state back to 0 */
759 mgp->tx.req = 0;
760 mgp->tx.done = 0;
761 mgp->tx.pkt_start = 0;
762 mgp->tx.pkt_done = 0;
763 mgp->rx_big.cnt = 0;
764 mgp->rx_small.cnt = 0;
765 mgp->rx_done.idx = 0;
766 mgp->rx_done.cnt = 0;
767 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
768 myri10ge_change_promisc(mgp, 0, 0);
769 myri10ge_change_pause(mgp, mgp->pause);
770 return status;
771 }
772
773 static inline void
774 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
775 struct mcp_kreq_ether_recv *src)
776 {
777 u32 low;
778
779 low = src->addr_low;
780 src->addr_low = DMA_32BIT_MASK;
781 myri10ge_pio_copy(dst, src, 8 * sizeof(*src));
782 mb();
783 src->addr_low = low;
784 __raw_writel(low, &dst->addr_low);
785 mb();
786 }
787
788 /*
789 * Set of routines to get a new receive buffer. Any buffer which
790 * crosses a 4KB boundary must start on a 4KB boundary due to PCIe
791 * wdma restrictions. We also try to align any smaller allocation to
792 * at least a 16 byte boundary for efficiency. We assume the linux
793 * memory allocator works by powers of 2, and will not return memory
794 * smaller than 2KB which crosses a 4KB boundary. If it does, we fall
795 * back to allocating 2x as much space as required.
796 *
797 * We intend to replace large (>4KB) skb allocations by using
798 * pages directly and building a fraglist in the near future.
799 */
800
801 static inline struct sk_buff *myri10ge_alloc_big(struct net_device *dev,
802 int bytes)
803 {
804 struct sk_buff *skb;
805 unsigned long data, roundup;
806
807 skb = netdev_alloc_skb(dev, bytes + 4096 + MXGEFW_PAD);
808 if (skb == NULL)
809 return NULL;
810
811 /* Correct skb->truesize so that socket buffer
812 * accounting is not confused the rounding we must
813 * do to satisfy alignment constraints.
814 */
815 skb->truesize -= 4096;
816
817 data = (unsigned long)(skb->data);
818 roundup = (-data) & (4095);
819 skb_reserve(skb, roundup);
820 return skb;
821 }
822
823 /* Allocate 2x as much space as required and use whichever portion
824 * does not cross a 4KB boundary */
825 static inline struct sk_buff *myri10ge_alloc_small_safe(struct net_device *dev,
826 unsigned int bytes)
827 {
828 struct sk_buff *skb;
829 unsigned long data, boundary;
830
831 skb = netdev_alloc_skb(dev, 2 * (bytes + MXGEFW_PAD) - 1);
832 if (unlikely(skb == NULL))
833 return NULL;
834
835 /* Correct skb->truesize so that socket buffer
836 * accounting is not confused the rounding we must
837 * do to satisfy alignment constraints.
838 */
839 skb->truesize -= bytes + MXGEFW_PAD;
840
841 data = (unsigned long)(skb->data);
842 boundary = (data + 4095UL) & ~4095UL;
843 if ((boundary - data) >= (bytes + MXGEFW_PAD))
844 return skb;
845
846 skb_reserve(skb, boundary - data);
847 return skb;
848 }
849
850 /* Allocate just enough space, and verify that the allocated
851 * space does not cross a 4KB boundary */
852 static inline struct sk_buff *myri10ge_alloc_small(struct net_device *dev,
853 int bytes)
854 {
855 struct sk_buff *skb;
856 unsigned long roundup, data, end;
857
858 skb = netdev_alloc_skb(dev, bytes + 16 + MXGEFW_PAD);
859 if (unlikely(skb == NULL))
860 return NULL;
861
862 /* Round allocated buffer to 16 byte boundary */
863 data = (unsigned long)(skb->data);
864 roundup = (-data) & 15UL;
865 skb_reserve(skb, roundup);
866 /* Verify that the data buffer does not cross a page boundary */
867 data = (unsigned long)(skb->data);
868 end = data + bytes + MXGEFW_PAD - 1;
869 if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) {
870 printk(KERN_NOTICE
871 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
872 myri10ge_skb_cross_4k = 1;
873 dev_kfree_skb_any(skb);
874 skb = myri10ge_alloc_small_safe(dev, bytes);
875 }
876 return skb;
877 }
878
879 static inline int
880 myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct myri10ge_priv *mgp,
881 int bytes, int idx)
882 {
883 struct net_device *dev = mgp->dev;
884 struct pci_dev *pdev = mgp->pdev;
885 struct sk_buff *skb;
886 dma_addr_t bus;
887 int len, retval = 0;
888
889 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
890
891 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
892 skb = myri10ge_alloc_big(dev, bytes);
893 else if (myri10ge_skb_cross_4k)
894 skb = myri10ge_alloc_small_safe(dev, bytes);
895 else
896 skb = myri10ge_alloc_small(dev, bytes);
897
898 if (unlikely(skb == NULL)) {
899 rx->alloc_fail++;
900 retval = -ENOBUFS;
901 goto done;
902 }
903
904 /* set len so that it only covers the area we
905 * need mapped for DMA */
906 len = bytes + MXGEFW_PAD;
907
908 bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE);
909 rx->info[idx].skb = skb;
910 pci_unmap_addr_set(&rx->info[idx], bus, bus);
911 pci_unmap_len_set(&rx->info[idx], len, len);
912 rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus));
913 rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
914
915 done:
916 /* copy 8 descriptors (64-bytes) to the mcp at a time */
917 if ((idx & 7) == 7) {
918 if (rx->wc_fifo == NULL)
919 myri10ge_submit_8rx(&rx->lanai[idx - 7],
920 &rx->shadow[idx - 7]);
921 else {
922 mb();
923 myri10ge_pio_copy(rx->wc_fifo,
924 &rx->shadow[idx - 7], 64);
925 }
926 }
927 return retval;
928 }
929
930 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
931 {
932 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
933
934 if ((skb->protocol == ntohs(ETH_P_8021Q)) &&
935 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
936 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
937 skb->csum = hw_csum;
938 skb->ip_summed = CHECKSUM_HW;
939 }
940 }
941
942 static inline unsigned long
943 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
944 int bytes, int len, int csum)
945 {
946 dma_addr_t bus;
947 struct sk_buff *skb;
948 int idx, unmap_len;
949
950 idx = rx->cnt & rx->mask;
951 rx->cnt++;
952
953 /* save a pointer to the received skb */
954 skb = rx->info[idx].skb;
955 bus = pci_unmap_addr(&rx->info[idx], bus);
956 unmap_len = pci_unmap_len(&rx->info[idx], len);
957
958 /* try to replace the received skb */
959 if (myri10ge_getbuf(rx, mgp, bytes, idx)) {
960 /* drop the frame -- the old skbuf is re-cycled */
961 mgp->stats.rx_dropped += 1;
962 return 0;
963 }
964
965 /* unmap the recvd skb */
966 pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE);
967
968 /* mcp implicitly skips 1st bytes so that packet is properly
969 * aligned */
970 skb_reserve(skb, MXGEFW_PAD);
971
972 /* set the length of the frame */
973 skb_put(skb, len);
974
975 skb->protocol = eth_type_trans(skb, mgp->dev);
976 if (mgp->csum_flag) {
977 if ((skb->protocol == ntohs(ETH_P_IP)) ||
978 (skb->protocol == ntohs(ETH_P_IPV6))) {
979 skb->csum = ntohs((u16) csum);
980 skb->ip_summed = CHECKSUM_HW;
981 } else
982 myri10ge_vlan_ip_csum(skb, ntohs((u16) csum));
983 }
984
985 netif_receive_skb(skb);
986 mgp->dev->last_rx = jiffies;
987 return 1;
988 }
989
990 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
991 {
992 struct pci_dev *pdev = mgp->pdev;
993 struct myri10ge_tx_buf *tx = &mgp->tx;
994 struct sk_buff *skb;
995 int idx, len;
996 int limit = 0;
997
998 while (tx->pkt_done != mcp_index) {
999 idx = tx->done & tx->mask;
1000 skb = tx->info[idx].skb;
1001
1002 /* Mark as free */
1003 tx->info[idx].skb = NULL;
1004 if (tx->info[idx].last) {
1005 tx->pkt_done++;
1006 tx->info[idx].last = 0;
1007 }
1008 tx->done++;
1009 len = pci_unmap_len(&tx->info[idx], len);
1010 pci_unmap_len_set(&tx->info[idx], len, 0);
1011 if (skb) {
1012 mgp->stats.tx_bytes += skb->len;
1013 mgp->stats.tx_packets++;
1014 dev_kfree_skb_irq(skb);
1015 if (len)
1016 pci_unmap_single(pdev,
1017 pci_unmap_addr(&tx->info[idx],
1018 bus), len,
1019 PCI_DMA_TODEVICE);
1020 } else {
1021 if (len)
1022 pci_unmap_page(pdev,
1023 pci_unmap_addr(&tx->info[idx],
1024 bus), len,
1025 PCI_DMA_TODEVICE);
1026 }
1027
1028 /* limit potential for livelock by only handling
1029 * 2 full tx rings per call */
1030 if (unlikely(++limit > 2 * tx->mask))
1031 break;
1032 }
1033 /* start the queue if we've stopped it */
1034 if (netif_queue_stopped(mgp->dev)
1035 && tx->req - tx->done < (tx->mask >> 1)) {
1036 mgp->wake_queue++;
1037 netif_wake_queue(mgp->dev);
1038 }
1039 }
1040
1041 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1042 {
1043 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1044 unsigned long rx_bytes = 0;
1045 unsigned long rx_packets = 0;
1046 unsigned long rx_ok;
1047
1048 int idx = rx_done->idx;
1049 int cnt = rx_done->cnt;
1050 u16 length;
1051 u16 checksum;
1052
1053 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1054 length = ntohs(rx_done->entry[idx].length);
1055 rx_done->entry[idx].length = 0;
1056 checksum = ntohs(rx_done->entry[idx].checksum);
1057 if (length <= mgp->small_bytes)
1058 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1059 mgp->small_bytes,
1060 length, checksum);
1061 else
1062 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1063 mgp->dev->mtu + ETH_HLEN,
1064 length, checksum);
1065 rx_packets += rx_ok;
1066 rx_bytes += rx_ok * (unsigned long)length;
1067 cnt++;
1068 idx = cnt & (myri10ge_max_intr_slots - 1);
1069
1070 /* limit potential for livelock by only handling a
1071 * limited number of frames. */
1072 (*limit)--;
1073 }
1074 rx_done->idx = idx;
1075 rx_done->cnt = cnt;
1076 mgp->stats.rx_packets += rx_packets;
1077 mgp->stats.rx_bytes += rx_bytes;
1078 }
1079
1080 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1081 {
1082 struct mcp_irq_data *stats = mgp->fw_stats;
1083
1084 if (unlikely(stats->stats_updated)) {
1085 if (mgp->link_state != stats->link_up) {
1086 mgp->link_state = stats->link_up;
1087 if (mgp->link_state) {
1088 printk(KERN_INFO "myri10ge: %s: link up\n",
1089 mgp->dev->name);
1090 netif_carrier_on(mgp->dev);
1091 } else {
1092 printk(KERN_INFO "myri10ge: %s: link down\n",
1093 mgp->dev->name);
1094 netif_carrier_off(mgp->dev);
1095 }
1096 }
1097 if (mgp->rdma_tags_available !=
1098 ntohl(mgp->fw_stats->rdma_tags_available)) {
1099 mgp->rdma_tags_available =
1100 ntohl(mgp->fw_stats->rdma_tags_available);
1101 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1102 "%d tags left\n", mgp->dev->name,
1103 mgp->rdma_tags_available);
1104 }
1105 mgp->down_cnt += stats->link_down;
1106 if (stats->link_down)
1107 wake_up(&mgp->down_wq);
1108 }
1109 }
1110
1111 static int myri10ge_poll(struct net_device *netdev, int *budget)
1112 {
1113 struct myri10ge_priv *mgp = netdev_priv(netdev);
1114 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1115 int limit, orig_limit, work_done;
1116
1117 /* process as many rx events as NAPI will allow */
1118 limit = min(*budget, netdev->quota);
1119 orig_limit = limit;
1120 myri10ge_clean_rx_done(mgp, &limit);
1121 work_done = orig_limit - limit;
1122 *budget -= work_done;
1123 netdev->quota -= work_done;
1124
1125 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1126 netif_rx_complete(netdev);
1127 __raw_writel(htonl(3), mgp->irq_claim);
1128 return 0;
1129 }
1130 return 1;
1131 }
1132
1133 static irqreturn_t myri10ge_intr(int irq, void *arg, struct pt_regs *regs)
1134 {
1135 struct myri10ge_priv *mgp = arg;
1136 struct mcp_irq_data *stats = mgp->fw_stats;
1137 struct myri10ge_tx_buf *tx = &mgp->tx;
1138 u32 send_done_count;
1139 int i;
1140
1141 /* make sure it is our IRQ, and that the DMA has finished */
1142 if (unlikely(!stats->valid))
1143 return (IRQ_NONE);
1144
1145 /* low bit indicates receives are present, so schedule
1146 * napi poll handler */
1147 if (stats->valid & 1)
1148 netif_rx_schedule(mgp->dev);
1149
1150 if (!mgp->msi_enabled) {
1151 __raw_writel(0, mgp->irq_deassert);
1152 if (!myri10ge_deassert_wait)
1153 stats->valid = 0;
1154 mb();
1155 } else
1156 stats->valid = 0;
1157
1158 /* Wait for IRQ line to go low, if using INTx */
1159 i = 0;
1160 while (1) {
1161 i++;
1162 /* check for transmit completes and receives */
1163 send_done_count = ntohl(stats->send_done_count);
1164 if (send_done_count != tx->pkt_done)
1165 myri10ge_tx_done(mgp, (int)send_done_count);
1166 if (unlikely(i > myri10ge_max_irq_loops)) {
1167 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1168 mgp->dev->name);
1169 stats->valid = 0;
1170 schedule_work(&mgp->watchdog_work);
1171 }
1172 if (likely(stats->valid == 0))
1173 break;
1174 cpu_relax();
1175 barrier();
1176 }
1177
1178 myri10ge_check_statblock(mgp);
1179
1180 __raw_writel(htonl(3), mgp->irq_claim + 1);
1181 return (IRQ_HANDLED);
1182 }
1183
1184 static int
1185 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1186 {
1187 cmd->autoneg = AUTONEG_DISABLE;
1188 cmd->speed = SPEED_10000;
1189 cmd->duplex = DUPLEX_FULL;
1190 return 0;
1191 }
1192
1193 static void
1194 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1195 {
1196 struct myri10ge_priv *mgp = netdev_priv(netdev);
1197
1198 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1199 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1200 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1201 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1202 }
1203
1204 static int
1205 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1206 {
1207 struct myri10ge_priv *mgp = netdev_priv(netdev);
1208 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1209 return 0;
1210 }
1211
1212 static int
1213 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1214 {
1215 struct myri10ge_priv *mgp = netdev_priv(netdev);
1216
1217 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1218 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1219 return 0;
1220 }
1221
1222 static void
1223 myri10ge_get_pauseparam(struct net_device *netdev,
1224 struct ethtool_pauseparam *pause)
1225 {
1226 struct myri10ge_priv *mgp = netdev_priv(netdev);
1227
1228 pause->autoneg = 0;
1229 pause->rx_pause = mgp->pause;
1230 pause->tx_pause = mgp->pause;
1231 }
1232
1233 static int
1234 myri10ge_set_pauseparam(struct net_device *netdev,
1235 struct ethtool_pauseparam *pause)
1236 {
1237 struct myri10ge_priv *mgp = netdev_priv(netdev);
1238
1239 if (pause->tx_pause != mgp->pause)
1240 return myri10ge_change_pause(mgp, pause->tx_pause);
1241 if (pause->rx_pause != mgp->pause)
1242 return myri10ge_change_pause(mgp, pause->tx_pause);
1243 if (pause->autoneg != 0)
1244 return -EINVAL;
1245 return 0;
1246 }
1247
1248 static void
1249 myri10ge_get_ringparam(struct net_device *netdev,
1250 struct ethtool_ringparam *ring)
1251 {
1252 struct myri10ge_priv *mgp = netdev_priv(netdev);
1253
1254 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1255 ring->rx_max_pending = mgp->rx_big.mask + 1;
1256 ring->rx_jumbo_max_pending = 0;
1257 ring->tx_max_pending = mgp->rx_small.mask + 1;
1258 ring->rx_mini_pending = ring->rx_mini_max_pending;
1259 ring->rx_pending = ring->rx_max_pending;
1260 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1261 ring->tx_pending = ring->tx_max_pending;
1262 }
1263
1264 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1265 {
1266 struct myri10ge_priv *mgp = netdev_priv(netdev);
1267 if (mgp->csum_flag)
1268 return 1;
1269 else
1270 return 0;
1271 }
1272
1273 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1274 {
1275 struct myri10ge_priv *mgp = netdev_priv(netdev);
1276 if (csum_enabled)
1277 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1278 else
1279 mgp->csum_flag = 0;
1280 return 0;
1281 }
1282
1283 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1284 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1285 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1286 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1287 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1288 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1289 "tx_heartbeat_errors", "tx_window_errors",
1290 /* device-specific stats */
1291 "tx_boundary", "WC", "irq", "MSI",
1292 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1293 "serial_number", "tx_pkt_start", "tx_pkt_done",
1294 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1295 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1296 "link_up", "dropped_link_overflow", "dropped_link_error_or_filtered",
1297 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1298 "dropped_no_big_buffer"
1299 };
1300
1301 #define MYRI10GE_NET_STATS_LEN 21
1302 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1303
1304 static void
1305 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1306 {
1307 switch (stringset) {
1308 case ETH_SS_STATS:
1309 memcpy(data, *myri10ge_gstrings_stats,
1310 sizeof(myri10ge_gstrings_stats));
1311 break;
1312 }
1313 }
1314
1315 static int myri10ge_get_stats_count(struct net_device *netdev)
1316 {
1317 return MYRI10GE_STATS_LEN;
1318 }
1319
1320 static void
1321 myri10ge_get_ethtool_stats(struct net_device *netdev,
1322 struct ethtool_stats *stats, u64 * data)
1323 {
1324 struct myri10ge_priv *mgp = netdev_priv(netdev);
1325 int i;
1326
1327 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1328 data[i] = ((unsigned long *)&mgp->stats)[i];
1329
1330 data[i++] = (unsigned int)mgp->tx.boundary;
1331 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1332 data[i++] = (unsigned int)mgp->pdev->irq;
1333 data[i++] = (unsigned int)mgp->msi_enabled;
1334 data[i++] = (unsigned int)mgp->read_dma;
1335 data[i++] = (unsigned int)mgp->write_dma;
1336 data[i++] = (unsigned int)mgp->read_write_dma;
1337 data[i++] = (unsigned int)mgp->serial_number;
1338 data[i++] = (unsigned int)mgp->tx.pkt_start;
1339 data[i++] = (unsigned int)mgp->tx.pkt_done;
1340 data[i++] = (unsigned int)mgp->tx.req;
1341 data[i++] = (unsigned int)mgp->tx.done;
1342 data[i++] = (unsigned int)mgp->rx_small.cnt;
1343 data[i++] = (unsigned int)mgp->rx_big.cnt;
1344 data[i++] = (unsigned int)mgp->wake_queue;
1345 data[i++] = (unsigned int)mgp->stop_queue;
1346 data[i++] = (unsigned int)mgp->watchdog_resets;
1347 data[i++] = (unsigned int)mgp->tx_linearized;
1348 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1349 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1350 data[i++] =
1351 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1352 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1353 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1354 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1355 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1356 }
1357
1358 static struct ethtool_ops myri10ge_ethtool_ops = {
1359 .get_settings = myri10ge_get_settings,
1360 .get_drvinfo = myri10ge_get_drvinfo,
1361 .get_coalesce = myri10ge_get_coalesce,
1362 .set_coalesce = myri10ge_set_coalesce,
1363 .get_pauseparam = myri10ge_get_pauseparam,
1364 .set_pauseparam = myri10ge_set_pauseparam,
1365 .get_ringparam = myri10ge_get_ringparam,
1366 .get_rx_csum = myri10ge_get_rx_csum,
1367 .set_rx_csum = myri10ge_set_rx_csum,
1368 .get_tx_csum = ethtool_op_get_tx_csum,
1369 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1370 .get_sg = ethtool_op_get_sg,
1371 .set_sg = ethtool_op_set_sg,
1372 #ifdef NETIF_F_TSO
1373 .get_tso = ethtool_op_get_tso,
1374 .set_tso = ethtool_op_set_tso,
1375 #endif
1376 .get_strings = myri10ge_get_strings,
1377 .get_stats_count = myri10ge_get_stats_count,
1378 .get_ethtool_stats = myri10ge_get_ethtool_stats
1379 };
1380
1381 static int myri10ge_allocate_rings(struct net_device *dev)
1382 {
1383 struct myri10ge_priv *mgp;
1384 struct myri10ge_cmd cmd;
1385 int tx_ring_size, rx_ring_size;
1386 int tx_ring_entries, rx_ring_entries;
1387 int i, status;
1388 size_t bytes;
1389
1390 mgp = netdev_priv(dev);
1391
1392 /* get ring sizes */
1393
1394 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1395 tx_ring_size = cmd.data0;
1396 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1397 rx_ring_size = cmd.data0;
1398
1399 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1400 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1401 mgp->tx.mask = tx_ring_entries - 1;
1402 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1403
1404 /* allocate the host shadow rings */
1405
1406 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1407 * sizeof(*mgp->tx.req_list);
1408 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1409 if (mgp->tx.req_bytes == NULL)
1410 goto abort_with_nothing;
1411
1412 /* ensure req_list entries are aligned to 8 bytes */
1413 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1414 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1415
1416 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1417 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1418 if (mgp->rx_small.shadow == NULL)
1419 goto abort_with_tx_req_bytes;
1420
1421 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1422 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1423 if (mgp->rx_big.shadow == NULL)
1424 goto abort_with_rx_small_shadow;
1425
1426 /* allocate the host info rings */
1427
1428 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1429 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1430 if (mgp->tx.info == NULL)
1431 goto abort_with_rx_big_shadow;
1432
1433 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1434 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1435 if (mgp->rx_small.info == NULL)
1436 goto abort_with_tx_info;
1437
1438 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1439 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1440 if (mgp->rx_big.info == NULL)
1441 goto abort_with_rx_small_info;
1442
1443 /* Fill the receive rings */
1444
1445 for (i = 0; i <= mgp->rx_small.mask; i++) {
1446 status = myri10ge_getbuf(&mgp->rx_small, mgp,
1447 mgp->small_bytes, i);
1448 if (status) {
1449 printk(KERN_ERR
1450 "myri10ge: %s: alloced only %d small bufs\n",
1451 dev->name, i);
1452 goto abort_with_rx_small_ring;
1453 }
1454 }
1455
1456 for (i = 0; i <= mgp->rx_big.mask; i++) {
1457 status =
1458 myri10ge_getbuf(&mgp->rx_big, mgp, dev->mtu + ETH_HLEN, i);
1459 if (status) {
1460 printk(KERN_ERR
1461 "myri10ge: %s: alloced only %d big bufs\n",
1462 dev->name, i);
1463 goto abort_with_rx_big_ring;
1464 }
1465 }
1466
1467 return 0;
1468
1469 abort_with_rx_big_ring:
1470 for (i = 0; i <= mgp->rx_big.mask; i++) {
1471 if (mgp->rx_big.info[i].skb != NULL)
1472 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1473 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1474 pci_unmap_single(mgp->pdev,
1475 pci_unmap_addr(&mgp->rx_big.info[i],
1476 bus),
1477 pci_unmap_len(&mgp->rx_big.info[i],
1478 len),
1479 PCI_DMA_FROMDEVICE);
1480 }
1481
1482 abort_with_rx_small_ring:
1483 for (i = 0; i <= mgp->rx_small.mask; i++) {
1484 if (mgp->rx_small.info[i].skb != NULL)
1485 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1486 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1487 pci_unmap_single(mgp->pdev,
1488 pci_unmap_addr(&mgp->rx_small.info[i],
1489 bus),
1490 pci_unmap_len(&mgp->rx_small.info[i],
1491 len),
1492 PCI_DMA_FROMDEVICE);
1493 }
1494 kfree(mgp->rx_big.info);
1495
1496 abort_with_rx_small_info:
1497 kfree(mgp->rx_small.info);
1498
1499 abort_with_tx_info:
1500 kfree(mgp->tx.info);
1501
1502 abort_with_rx_big_shadow:
1503 kfree(mgp->rx_big.shadow);
1504
1505 abort_with_rx_small_shadow:
1506 kfree(mgp->rx_small.shadow);
1507
1508 abort_with_tx_req_bytes:
1509 kfree(mgp->tx.req_bytes);
1510 mgp->tx.req_bytes = NULL;
1511 mgp->tx.req_list = NULL;
1512
1513 abort_with_nothing:
1514 return status;
1515 }
1516
1517 static void myri10ge_free_rings(struct net_device *dev)
1518 {
1519 struct myri10ge_priv *mgp;
1520 struct sk_buff *skb;
1521 struct myri10ge_tx_buf *tx;
1522 int i, len, idx;
1523
1524 mgp = netdev_priv(dev);
1525
1526 for (i = 0; i <= mgp->rx_big.mask; i++) {
1527 if (mgp->rx_big.info[i].skb != NULL)
1528 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1529 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1530 pci_unmap_single(mgp->pdev,
1531 pci_unmap_addr(&mgp->rx_big.info[i],
1532 bus),
1533 pci_unmap_len(&mgp->rx_big.info[i],
1534 len),
1535 PCI_DMA_FROMDEVICE);
1536 }
1537
1538 for (i = 0; i <= mgp->rx_small.mask; i++) {
1539 if (mgp->rx_small.info[i].skb != NULL)
1540 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1541 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1542 pci_unmap_single(mgp->pdev,
1543 pci_unmap_addr(&mgp->rx_small.info[i],
1544 bus),
1545 pci_unmap_len(&mgp->rx_small.info[i],
1546 len),
1547 PCI_DMA_FROMDEVICE);
1548 }
1549
1550 tx = &mgp->tx;
1551 while (tx->done != tx->req) {
1552 idx = tx->done & tx->mask;
1553 skb = tx->info[idx].skb;
1554
1555 /* Mark as free */
1556 tx->info[idx].skb = NULL;
1557 tx->done++;
1558 len = pci_unmap_len(&tx->info[idx], len);
1559 pci_unmap_len_set(&tx->info[idx], len, 0);
1560 if (skb) {
1561 mgp->stats.tx_dropped++;
1562 dev_kfree_skb_any(skb);
1563 if (len)
1564 pci_unmap_single(mgp->pdev,
1565 pci_unmap_addr(&tx->info[idx],
1566 bus), len,
1567 PCI_DMA_TODEVICE);
1568 } else {
1569 if (len)
1570 pci_unmap_page(mgp->pdev,
1571 pci_unmap_addr(&tx->info[idx],
1572 bus), len,
1573 PCI_DMA_TODEVICE);
1574 }
1575 }
1576 kfree(mgp->rx_big.info);
1577
1578 kfree(mgp->rx_small.info);
1579
1580 kfree(mgp->tx.info);
1581
1582 kfree(mgp->rx_big.shadow);
1583
1584 kfree(mgp->rx_small.shadow);
1585
1586 kfree(mgp->tx.req_bytes);
1587 mgp->tx.req_bytes = NULL;
1588 mgp->tx.req_list = NULL;
1589 }
1590
1591 static int myri10ge_open(struct net_device *dev)
1592 {
1593 struct myri10ge_priv *mgp;
1594 struct myri10ge_cmd cmd;
1595 int status, big_pow2;
1596
1597 mgp = netdev_priv(dev);
1598
1599 if (mgp->running != MYRI10GE_ETH_STOPPED)
1600 return -EBUSY;
1601
1602 mgp->running = MYRI10GE_ETH_STARTING;
1603 status = myri10ge_reset(mgp);
1604 if (status != 0) {
1605 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1606 mgp->running = MYRI10GE_ETH_STOPPED;
1607 return -ENXIO;
1608 }
1609
1610 /* decide what small buffer size to use. For good TCP rx
1611 * performance, it is important to not receive 1514 byte
1612 * frames into jumbo buffers, as it confuses the socket buffer
1613 * accounting code, leading to drops and erratic performance.
1614 */
1615
1616 if (dev->mtu <= ETH_DATA_LEN)
1617 mgp->small_bytes = 128; /* enough for a TCP header */
1618 else
1619 mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */
1620
1621 /* Override the small buffer size? */
1622 if (myri10ge_small_bytes > 0)
1623 mgp->small_bytes = myri10ge_small_bytes;
1624
1625 /* If the user sets an obscenely small MTU, adjust the small
1626 * bytes down to nearly nothing */
1627 if (mgp->small_bytes >= (dev->mtu + ETH_HLEN))
1628 mgp->small_bytes = 64;
1629
1630 /* get the lanai pointers to the send and receive rings */
1631
1632 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1633 mgp->tx.lanai =
1634 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1635
1636 status |=
1637 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1638 mgp->rx_small.lanai =
1639 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1640
1641 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1642 mgp->rx_big.lanai =
1643 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1644
1645 if (status != 0) {
1646 printk(KERN_ERR
1647 "myri10ge: %s: failed to get ring sizes or locations\n",
1648 dev->name);
1649 mgp->running = MYRI10GE_ETH_STOPPED;
1650 return -ENXIO;
1651 }
1652
1653 if (mgp->mtrr >= 0) {
1654 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1655 mgp->rx_small.wc_fifo =
1656 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1657 mgp->rx_big.wc_fifo =
1658 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1659 } else {
1660 mgp->tx.wc_fifo = NULL;
1661 mgp->rx_small.wc_fifo = NULL;
1662 mgp->rx_big.wc_fifo = NULL;
1663 }
1664
1665 status = myri10ge_allocate_rings(dev);
1666 if (status != 0)
1667 goto abort_with_nothing;
1668
1669 /* Firmware needs the big buff size as a power of 2. Lie and
1670 * tell him the buffer is larger, because we only use 1
1671 * buffer/pkt, and the mtu will prevent overruns.
1672 */
1673 big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD;
1674 while ((big_pow2 & (big_pow2 - 1)) != 0)
1675 big_pow2++;
1676
1677 /* now give firmware buffers sizes, and MTU */
1678 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1679 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1680 cmd.data0 = mgp->small_bytes;
1681 status |=
1682 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1683 cmd.data0 = big_pow2;
1684 status |=
1685 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1686 if (status) {
1687 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1688 dev->name);
1689 goto abort_with_rings;
1690 }
1691
1692 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1693 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1694 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA, &cmd, 0);
1695 if (status) {
1696 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1697 dev->name);
1698 goto abort_with_rings;
1699 }
1700
1701 mgp->link_state = -1;
1702 mgp->rdma_tags_available = 15;
1703
1704 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1705
1706 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1707 if (status) {
1708 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1709 dev->name);
1710 goto abort_with_rings;
1711 }
1712
1713 mgp->wake_queue = 0;
1714 mgp->stop_queue = 0;
1715 mgp->running = MYRI10GE_ETH_RUNNING;
1716 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1717 add_timer(&mgp->watchdog_timer);
1718 netif_wake_queue(dev);
1719 return 0;
1720
1721 abort_with_rings:
1722 myri10ge_free_rings(dev);
1723
1724 abort_with_nothing:
1725 mgp->running = MYRI10GE_ETH_STOPPED;
1726 return -ENOMEM;
1727 }
1728
1729 static int myri10ge_close(struct net_device *dev)
1730 {
1731 struct myri10ge_priv *mgp;
1732 struct myri10ge_cmd cmd;
1733 int status, old_down_cnt;
1734
1735 mgp = netdev_priv(dev);
1736
1737 if (mgp->running != MYRI10GE_ETH_RUNNING)
1738 return 0;
1739
1740 if (mgp->tx.req_bytes == NULL)
1741 return 0;
1742
1743 del_timer_sync(&mgp->watchdog_timer);
1744 mgp->running = MYRI10GE_ETH_STOPPING;
1745 netif_poll_disable(mgp->dev);
1746 netif_carrier_off(dev);
1747 netif_stop_queue(dev);
1748 old_down_cnt = mgp->down_cnt;
1749 mb();
1750 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1751 if (status)
1752 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1753 dev->name);
1754
1755 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1756 if (old_down_cnt == mgp->down_cnt)
1757 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1758
1759 netif_tx_disable(dev);
1760
1761 myri10ge_free_rings(dev);
1762
1763 mgp->running = MYRI10GE_ETH_STOPPED;
1764 return 0;
1765 }
1766
1767 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1768 * backwards one at a time and handle ring wraps */
1769
1770 static inline void
1771 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1772 struct mcp_kreq_ether_send *src, int cnt)
1773 {
1774 int idx, starting_slot;
1775 starting_slot = tx->req;
1776 while (cnt > 1) {
1777 cnt--;
1778 idx = (starting_slot + cnt) & tx->mask;
1779 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1780 mb();
1781 }
1782 }
1783
1784 /*
1785 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1786 * at most 32 bytes at a time, so as to avoid involving the software
1787 * pio handler in the nic. We re-write the first segment's flags
1788 * to mark them valid only after writing the entire chain.
1789 */
1790
1791 static inline void
1792 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1793 int cnt)
1794 {
1795 int idx, i;
1796 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1797 struct mcp_kreq_ether_send *srcp;
1798 u8 last_flags;
1799
1800 idx = tx->req & tx->mask;
1801
1802 last_flags = src->flags;
1803 src->flags = 0;
1804 mb();
1805 dst = dstp = &tx->lanai[idx];
1806 srcp = src;
1807
1808 if ((idx + cnt) < tx->mask) {
1809 for (i = 0; i < (cnt - 1); i += 2) {
1810 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1811 mb(); /* force write every 32 bytes */
1812 srcp += 2;
1813 dstp += 2;
1814 }
1815 } else {
1816 /* submit all but the first request, and ensure
1817 * that it is submitted below */
1818 myri10ge_submit_req_backwards(tx, src, cnt);
1819 i = 0;
1820 }
1821 if (i < cnt) {
1822 /* submit the first request */
1823 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1824 mb(); /* barrier before setting valid flag */
1825 }
1826
1827 /* re-write the last 32-bits with the valid flags */
1828 src->flags = last_flags;
1829 __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3);
1830 tx->req += cnt;
1831 mb();
1832 }
1833
1834 static inline void
1835 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1836 struct mcp_kreq_ether_send *src, int cnt)
1837 {
1838 tx->req += cnt;
1839 mb();
1840 while (cnt >= 4) {
1841 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1842 mb();
1843 src += 4;
1844 cnt -= 4;
1845 }
1846 if (cnt > 0) {
1847 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1848 * needs to be so that we don't overrun it */
1849 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1850 src, 64);
1851 mb();
1852 }
1853 }
1854
1855 /*
1856 * Transmit a packet. We need to split the packet so that a single
1857 * segment does not cross myri10ge->tx.boundary, so this makes segment
1858 * counting tricky. So rather than try to count segments up front, we
1859 * just give up if there are too few segments to hold a reasonably
1860 * fragmented packet currently available. If we run
1861 * out of segments while preparing a packet for DMA, we just linearize
1862 * it and try again.
1863 */
1864
1865 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1866 {
1867 struct myri10ge_priv *mgp = netdev_priv(dev);
1868 struct mcp_kreq_ether_send *req;
1869 struct myri10ge_tx_buf *tx = &mgp->tx;
1870 struct skb_frag_struct *frag;
1871 dma_addr_t bus;
1872 u32 low, high_swapped;
1873 unsigned int len;
1874 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1875 u16 pseudo_hdr_offset, cksum_offset;
1876 int cum_len, seglen, boundary, rdma_count;
1877 u8 flags, odd_flag;
1878
1879 again:
1880 req = tx->req_list;
1881 avail = tx->mask - 1 - (tx->req - tx->done);
1882
1883 mss = 0;
1884 max_segments = MXGEFW_MAX_SEND_DESC;
1885
1886 #ifdef NETIF_F_TSO
1887 if (skb->len > (dev->mtu + ETH_HLEN)) {
1888 mss = skb_shinfo(skb)->gso_size;
1889 if (mss != 0)
1890 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1891 }
1892 #endif /*NETIF_F_TSO */
1893
1894 if ((unlikely(avail < max_segments))) {
1895 /* we are out of transmit resources */
1896 mgp->stop_queue++;
1897 netif_stop_queue(dev);
1898 return 1;
1899 }
1900
1901 /* Setup checksum offloading, if needed */
1902 cksum_offset = 0;
1903 pseudo_hdr_offset = 0;
1904 odd_flag = 0;
1905 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1906 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1907 cksum_offset = (skb->h.raw - skb->data);
1908 pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data;
1909 /* If the headers are excessively large, then we must
1910 * fall back to a software checksum */
1911 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
1912 if (skb_checksum_help(skb, 0))
1913 goto drop;
1914 cksum_offset = 0;
1915 pseudo_hdr_offset = 0;
1916 } else {
1917 pseudo_hdr_offset = htons(pseudo_hdr_offset);
1918 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1919 flags |= MXGEFW_FLAGS_CKSUM;
1920 }
1921 }
1922
1923 cum_len = 0;
1924
1925 #ifdef NETIF_F_TSO
1926 if (mss) { /* TSO */
1927 /* this removes any CKSUM flag from before */
1928 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
1929
1930 /* negative cum_len signifies to the
1931 * send loop that we are still in the
1932 * header portion of the TSO packet.
1933 * TSO header must be at most 134 bytes long */
1934 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1935
1936 /* for TSO, pseudo_hdr_offset holds mss.
1937 * The firmware figures out where to put
1938 * the checksum by parsing the header. */
1939 pseudo_hdr_offset = htons(mss);
1940 } else
1941 #endif /*NETIF_F_TSO */
1942 /* Mark small packets, and pad out tiny packets */
1943 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
1944 flags |= MXGEFW_FLAGS_SMALL;
1945
1946 /* pad frames to at least ETH_ZLEN bytes */
1947 if (unlikely(skb->len < ETH_ZLEN)) {
1948 if (skb_padto(skb, ETH_ZLEN)) {
1949 /* The packet is gone, so we must
1950 * return 0 */
1951 mgp->stats.tx_dropped += 1;
1952 return 0;
1953 }
1954 /* adjust the len to account for the zero pad
1955 * so that the nic can know how long it is */
1956 skb->len = ETH_ZLEN;
1957 }
1958 }
1959
1960 /* map the skb for DMA */
1961 len = skb->len - skb->data_len;
1962 idx = tx->req & tx->mask;
1963 tx->info[idx].skb = skb;
1964 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
1965 pci_unmap_addr_set(&tx->info[idx], bus, bus);
1966 pci_unmap_len_set(&tx->info[idx], len, len);
1967
1968 frag_cnt = skb_shinfo(skb)->nr_frags;
1969 frag_idx = 0;
1970 count = 0;
1971 rdma_count = 0;
1972
1973 /* "rdma_count" is the number of RDMAs belonging to the
1974 * current packet BEFORE the current send request. For
1975 * non-TSO packets, this is equal to "count".
1976 * For TSO packets, rdma_count needs to be reset
1977 * to 0 after a segment cut.
1978 *
1979 * The rdma_count field of the send request is
1980 * the number of RDMAs of the packet starting at
1981 * that request. For TSO send requests with one ore more cuts
1982 * in the middle, this is the number of RDMAs starting
1983 * after the last cut in the request. All previous
1984 * segments before the last cut implicitly have 1 RDMA.
1985 *
1986 * Since the number of RDMAs is not known beforehand,
1987 * it must be filled-in retroactively - after each
1988 * segmentation cut or at the end of the entire packet.
1989 */
1990
1991 while (1) {
1992 /* Break the SKB or Fragment up into pieces which
1993 * do not cross mgp->tx.boundary */
1994 low = MYRI10GE_LOWPART_TO_U32(bus);
1995 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
1996 while (len) {
1997 u8 flags_next;
1998 int cum_len_next;
1999
2000 if (unlikely(count == max_segments))
2001 goto abort_linearize;
2002
2003 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2004 seglen = boundary - low;
2005 if (seglen > len)
2006 seglen = len;
2007 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2008 cum_len_next = cum_len + seglen;
2009 #ifdef NETIF_F_TSO
2010 if (mss) { /* TSO */
2011 (req - rdma_count)->rdma_count = rdma_count + 1;
2012
2013 if (likely(cum_len >= 0)) { /* payload */
2014 int next_is_first, chop;
2015
2016 chop = (cum_len_next > mss);
2017 cum_len_next = cum_len_next % mss;
2018 next_is_first = (cum_len_next == 0);
2019 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2020 flags_next |= next_is_first *
2021 MXGEFW_FLAGS_FIRST;
2022 rdma_count |= -(chop | next_is_first);
2023 rdma_count += chop & !next_is_first;
2024 } else if (likely(cum_len_next >= 0)) { /* header ends */
2025 int small;
2026
2027 rdma_count = -1;
2028 cum_len_next = 0;
2029 seglen = -cum_len;
2030 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2031 flags_next = MXGEFW_FLAGS_TSO_PLD |
2032 MXGEFW_FLAGS_FIRST |
2033 (small * MXGEFW_FLAGS_SMALL);
2034 }
2035 }
2036 #endif /* NETIF_F_TSO */
2037 req->addr_high = high_swapped;
2038 req->addr_low = htonl(low);
2039 req->pseudo_hdr_offset = pseudo_hdr_offset;
2040 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2041 req->rdma_count = 1;
2042 req->length = htons(seglen);
2043 req->cksum_offset = cksum_offset;
2044 req->flags = flags | ((cum_len & 1) * odd_flag);
2045
2046 low += seglen;
2047 len -= seglen;
2048 cum_len = cum_len_next;
2049 flags = flags_next;
2050 req++;
2051 count++;
2052 rdma_count++;
2053 if (unlikely(cksum_offset > seglen))
2054 cksum_offset -= seglen;
2055 else
2056 cksum_offset = 0;
2057 }
2058 if (frag_idx == frag_cnt)
2059 break;
2060
2061 /* map next fragment for DMA */
2062 idx = (count + tx->req) & tx->mask;
2063 frag = &skb_shinfo(skb)->frags[frag_idx];
2064 frag_idx++;
2065 len = frag->size;
2066 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2067 len, PCI_DMA_TODEVICE);
2068 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2069 pci_unmap_len_set(&tx->info[idx], len, len);
2070 }
2071
2072 (req - rdma_count)->rdma_count = rdma_count;
2073 #ifdef NETIF_F_TSO
2074 if (mss)
2075 do {
2076 req--;
2077 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2078 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2079 MXGEFW_FLAGS_FIRST)));
2080 #endif
2081 idx = ((count - 1) + tx->req) & tx->mask;
2082 tx->info[idx].last = 1;
2083 if (tx->wc_fifo == NULL)
2084 myri10ge_submit_req(tx, tx->req_list, count);
2085 else
2086 myri10ge_submit_req_wc(tx, tx->req_list, count);
2087 tx->pkt_start++;
2088 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2089 mgp->stop_queue++;
2090 netif_stop_queue(dev);
2091 }
2092 dev->trans_start = jiffies;
2093 return 0;
2094
2095 abort_linearize:
2096 /* Free any DMA resources we've alloced and clear out the skb
2097 * slot so as to not trip up assertions, and to avoid a
2098 * double-free if linearizing fails */
2099
2100 last_idx = (idx + 1) & tx->mask;
2101 idx = tx->req & tx->mask;
2102 tx->info[idx].skb = NULL;
2103 do {
2104 len = pci_unmap_len(&tx->info[idx], len);
2105 if (len) {
2106 if (tx->info[idx].skb != NULL)
2107 pci_unmap_single(mgp->pdev,
2108 pci_unmap_addr(&tx->info[idx],
2109 bus), len,
2110 PCI_DMA_TODEVICE);
2111 else
2112 pci_unmap_page(mgp->pdev,
2113 pci_unmap_addr(&tx->info[idx],
2114 bus), len,
2115 PCI_DMA_TODEVICE);
2116 pci_unmap_len_set(&tx->info[idx], len, 0);
2117 tx->info[idx].skb = NULL;
2118 }
2119 idx = (idx + 1) & tx->mask;
2120 } while (idx != last_idx);
2121 if (skb_is_gso(skb)) {
2122 printk(KERN_ERR
2123 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2124 mgp->dev->name);
2125 goto drop;
2126 }
2127
2128 if (skb_linearize(skb))
2129 goto drop;
2130
2131 mgp->tx_linearized++;
2132 goto again;
2133
2134 drop:
2135 dev_kfree_skb_any(skb);
2136 mgp->stats.tx_dropped += 1;
2137 return 0;
2138
2139 }
2140
2141 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2142 {
2143 struct myri10ge_priv *mgp = netdev_priv(dev);
2144 return &mgp->stats;
2145 }
2146
2147 static void myri10ge_set_multicast_list(struct net_device *dev)
2148 {
2149 /* can be called from atomic contexts,
2150 * pass 1 to force atomicity in myri10ge_send_cmd() */
2151 myri10ge_change_promisc(netdev_priv(dev), dev->flags & IFF_PROMISC, 1);
2152 }
2153
2154 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2155 {
2156 struct sockaddr *sa = addr;
2157 struct myri10ge_priv *mgp = netdev_priv(dev);
2158 int status;
2159
2160 if (!is_valid_ether_addr(sa->sa_data))
2161 return -EADDRNOTAVAIL;
2162
2163 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2164 if (status != 0) {
2165 printk(KERN_ERR
2166 "myri10ge: %s: changing mac address failed with %d\n",
2167 dev->name, status);
2168 return status;
2169 }
2170
2171 /* change the dev structure */
2172 memcpy(dev->dev_addr, sa->sa_data, 6);
2173 return 0;
2174 }
2175
2176 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2177 {
2178 struct myri10ge_priv *mgp = netdev_priv(dev);
2179 int error = 0;
2180
2181 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2182 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2183 dev->name, new_mtu);
2184 return -EINVAL;
2185 }
2186 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2187 dev->name, dev->mtu, new_mtu);
2188 if (mgp->running) {
2189 /* if we change the mtu on an active device, we must
2190 * reset the device so the firmware sees the change */
2191 myri10ge_close(dev);
2192 dev->mtu = new_mtu;
2193 myri10ge_open(dev);
2194 } else
2195 dev->mtu = new_mtu;
2196
2197 return error;
2198 }
2199
2200 /*
2201 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2202 * Only do it if the bridge is a root port since we don't want to disturb
2203 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2204 */
2205
2206 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2207 {
2208 struct pci_dev *bridge = mgp->pdev->bus->self;
2209 struct device *dev = &mgp->pdev->dev;
2210 unsigned cap;
2211 unsigned err_cap;
2212 u16 val;
2213 u8 ext_type;
2214 int ret;
2215
2216 if (!myri10ge_ecrc_enable || !bridge)
2217 return;
2218
2219 /* check that the bridge is a root port */
2220 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2221 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2222 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2223 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2224 if (myri10ge_ecrc_enable > 1) {
2225 struct pci_dev *old_bridge = bridge;
2226
2227 /* Walk the hierarchy up to the root port
2228 * where ECRC has to be enabled */
2229 do {
2230 bridge = bridge->bus->self;
2231 if (!bridge) {
2232 dev_err(dev,
2233 "Failed to find root port"
2234 " to force ECRC\n");
2235 return;
2236 }
2237 cap =
2238 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2239 pci_read_config_word(bridge,
2240 cap + PCI_CAP_FLAGS, &val);
2241 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2242 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2243
2244 dev_info(dev,
2245 "Forcing ECRC on non-root port %s"
2246 " (enabling on root port %s)\n",
2247 pci_name(old_bridge), pci_name(bridge));
2248 } else {
2249 dev_err(dev,
2250 "Not enabling ECRC on non-root port %s\n",
2251 pci_name(bridge));
2252 return;
2253 }
2254 }
2255
2256 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2257 if (!cap)
2258 return;
2259
2260 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2261 if (ret) {
2262 dev_err(dev, "failed reading ext-conf-space of %s\n",
2263 pci_name(bridge));
2264 dev_err(dev, "\t pci=nommconf in use? "
2265 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2266 return;
2267 }
2268 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2269 return;
2270
2271 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2272 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2273 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2274 mgp->tx.boundary = 4096;
2275 mgp->fw_name = myri10ge_fw_aligned;
2276 }
2277
2278 /*
2279 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2280 * when the PCI-E Completion packets are aligned on an 8-byte
2281 * boundary. Some PCI-E chip sets always align Completion packets; on
2282 * the ones that do not, the alignment can be enforced by enabling
2283 * ECRC generation (if supported).
2284 *
2285 * When PCI-E Completion packets are not aligned, it is actually more
2286 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2287 *
2288 * If the driver can neither enable ECRC nor verify that it has
2289 * already been enabled, then it must use a firmware image which works
2290 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2291 * should also ensure that it never gives the device a Read-DMA which is
2292 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2293 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2294 * firmware image, and set tx.boundary to 4KB.
2295 */
2296
2297 #define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
2298
2299 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2300 {
2301 struct pci_dev *bridge = mgp->pdev->bus->self;
2302
2303 mgp->tx.boundary = 2048;
2304 mgp->fw_name = myri10ge_fw_unaligned;
2305
2306 if (myri10ge_force_firmware == 0) {
2307 myri10ge_enable_ecrc(mgp);
2308
2309 /* Check to see if the upstream bridge is known to
2310 * provide aligned completions */
2311 if (bridge
2312 /* ServerWorks HT2000/HT1000 */
2313 && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2314 && bridge->device ==
2315 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) {
2316 dev_info(&mgp->pdev->dev,
2317 "Assuming aligned completions (0x%x:0x%x)\n",
2318 bridge->vendor, bridge->device);
2319 mgp->tx.boundary = 4096;
2320 mgp->fw_name = myri10ge_fw_aligned;
2321 }
2322 } else {
2323 if (myri10ge_force_firmware == 1) {
2324 dev_info(&mgp->pdev->dev,
2325 "Assuming aligned completions (forced)\n");
2326 mgp->tx.boundary = 4096;
2327 mgp->fw_name = myri10ge_fw_aligned;
2328 } else {
2329 dev_info(&mgp->pdev->dev,
2330 "Assuming unaligned completions (forced)\n");
2331 mgp->tx.boundary = 2048;
2332 mgp->fw_name = myri10ge_fw_unaligned;
2333 }
2334 }
2335 if (myri10ge_fw_name != NULL) {
2336 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2337 myri10ge_fw_name);
2338 mgp->fw_name = myri10ge_fw_name;
2339 }
2340 }
2341
2342 static void myri10ge_save_state(struct myri10ge_priv *mgp)
2343 {
2344 struct pci_dev *pdev = mgp->pdev;
2345 int cap;
2346
2347 pci_save_state(pdev);
2348 /* now save PCIe and MSI state that Linux will not
2349 * save for us */
2350 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2351 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2352 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2353 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2354 }
2355
2356 static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2357 {
2358 struct pci_dev *pdev = mgp->pdev;
2359 int cap;
2360
2361 /* restore PCIe and MSI state that linux will not */
2362 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2363 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2364 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2365 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2366
2367 pci_restore_state(pdev);
2368 }
2369
2370 #ifdef CONFIG_PM
2371
2372 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2373 {
2374 struct myri10ge_priv *mgp;
2375 struct net_device *netdev;
2376
2377 mgp = pci_get_drvdata(pdev);
2378 if (mgp == NULL)
2379 return -EINVAL;
2380 netdev = mgp->dev;
2381
2382 netif_device_detach(netdev);
2383 if (netif_running(netdev)) {
2384 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2385 rtnl_lock();
2386 myri10ge_close(netdev);
2387 rtnl_unlock();
2388 }
2389 myri10ge_dummy_rdma(mgp, 0);
2390 free_irq(pdev->irq, mgp);
2391 myri10ge_save_state(mgp);
2392 pci_disable_device(pdev);
2393 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2394 return 0;
2395 }
2396
2397 static int myri10ge_resume(struct pci_dev *pdev)
2398 {
2399 struct myri10ge_priv *mgp;
2400 struct net_device *netdev;
2401 int status;
2402 u16 vendor;
2403
2404 mgp = pci_get_drvdata(pdev);
2405 if (mgp == NULL)
2406 return -EINVAL;
2407 netdev = mgp->dev;
2408 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2409 msleep(5); /* give card time to respond */
2410 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2411 if (vendor == 0xffff) {
2412 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2413 mgp->dev->name);
2414 return -EIO;
2415 }
2416 myri10ge_restore_state(mgp);
2417
2418 status = pci_enable_device(pdev);
2419 if (status < 0) {
2420 dev_err(&pdev->dev, "failed to enable device\n");
2421 return -EIO;
2422 }
2423
2424 pci_set_master(pdev);
2425
2426 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2427 netdev->name, mgp);
2428 if (status != 0) {
2429 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2430 goto abort_with_enabled;
2431 }
2432
2433 myri10ge_reset(mgp);
2434 myri10ge_dummy_rdma(mgp, 1);
2435
2436 /* Save configuration space to be restored if the
2437 * nic resets due to a parity error */
2438 myri10ge_save_state(mgp);
2439
2440 if (netif_running(netdev)) {
2441 rtnl_lock();
2442 myri10ge_open(netdev);
2443 rtnl_unlock();
2444 }
2445 netif_device_attach(netdev);
2446
2447 return 0;
2448
2449 abort_with_enabled:
2450 pci_disable_device(pdev);
2451 return -EIO;
2452
2453 }
2454
2455 #endif /* CONFIG_PM */
2456
2457 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2458 {
2459 struct pci_dev *pdev = mgp->pdev;
2460 int vs = mgp->vendor_specific_offset;
2461 u32 reboot;
2462
2463 /*enter read32 mode */
2464 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2465
2466 /*read REBOOT_STATUS (0xfffffff0) */
2467 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2468 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2469 return reboot;
2470 }
2471
2472 /*
2473 * This watchdog is used to check whether the board has suffered
2474 * from a parity error and needs to be recovered.
2475 */
2476 static void myri10ge_watchdog(void *arg)
2477 {
2478 struct myri10ge_priv *mgp = arg;
2479 u32 reboot;
2480 int status;
2481 u16 cmd, vendor;
2482
2483 mgp->watchdog_resets++;
2484 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2485 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2486 /* Bus master DMA disabled? Check to see
2487 * if the card rebooted due to a parity error
2488 * For now, just report it */
2489 reboot = myri10ge_read_reboot(mgp);
2490 printk(KERN_ERR
2491 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2492 mgp->dev->name, reboot);
2493 /*
2494 * A rebooted nic will come back with config space as
2495 * it was after power was applied to PCIe bus.
2496 * Attempt to restore config space which was saved
2497 * when the driver was loaded, or the last time the
2498 * nic was resumed from power saving mode.
2499 */
2500 myri10ge_restore_state(mgp);
2501 } else {
2502 /* if we get back -1's from our slot, perhaps somebody
2503 * powered off our card. Don't try to reset it in
2504 * this case */
2505 if (cmd == 0xffff) {
2506 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2507 if (vendor == 0xffff) {
2508 printk(KERN_ERR
2509 "myri10ge: %s: device disappeared!\n",
2510 mgp->dev->name);
2511 return;
2512 }
2513 }
2514 /* Perhaps it is a software error. Try to reset */
2515
2516 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2517 mgp->dev->name);
2518 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2519 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2520 mgp->tx.pkt_start, mgp->tx.pkt_done,
2521 (int)ntohl(mgp->fw_stats->send_done_count));
2522 msleep(2000);
2523 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2524 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2525 mgp->tx.pkt_start, mgp->tx.pkt_done,
2526 (int)ntohl(mgp->fw_stats->send_done_count));
2527 }
2528 rtnl_lock();
2529 myri10ge_close(mgp->dev);
2530 status = myri10ge_load_firmware(mgp);
2531 if (status != 0)
2532 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2533 mgp->dev->name);
2534 else
2535 myri10ge_open(mgp->dev);
2536 rtnl_unlock();
2537 }
2538
2539 /*
2540 * We use our own timer routine rather than relying upon
2541 * netdev->tx_timeout because we have a very large hardware transmit
2542 * queue. Due to the large queue, the netdev->tx_timeout function
2543 * cannot detect a NIC with a parity error in a timely fashion if the
2544 * NIC is lightly loaded.
2545 */
2546 static void myri10ge_watchdog_timer(unsigned long arg)
2547 {
2548 struct myri10ge_priv *mgp;
2549
2550 mgp = (struct myri10ge_priv *)arg;
2551 if (mgp->tx.req != mgp->tx.done &&
2552 mgp->tx.done == mgp->watchdog_tx_done &&
2553 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2554 /* nic seems like it might be stuck.. */
2555 schedule_work(&mgp->watchdog_work);
2556 else
2557 /* rearm timer */
2558 mod_timer(&mgp->watchdog_timer,
2559 jiffies + myri10ge_watchdog_timeout * HZ);
2560
2561 mgp->watchdog_tx_done = mgp->tx.done;
2562 mgp->watchdog_tx_req = mgp->tx.req;
2563 }
2564
2565 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2566 {
2567 struct net_device *netdev;
2568 struct myri10ge_priv *mgp;
2569 struct device *dev = &pdev->dev;
2570 size_t bytes;
2571 int i;
2572 int status = -ENXIO;
2573 int cap;
2574 int dac_enabled;
2575 u16 val;
2576
2577 netdev = alloc_etherdev(sizeof(*mgp));
2578 if (netdev == NULL) {
2579 dev_err(dev, "Could not allocate ethernet device\n");
2580 return -ENOMEM;
2581 }
2582
2583 mgp = netdev_priv(netdev);
2584 memset(mgp, 0, sizeof(*mgp));
2585 mgp->dev = netdev;
2586 mgp->pdev = pdev;
2587 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2588 mgp->pause = myri10ge_flow_control;
2589 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2590 init_waitqueue_head(&mgp->down_wq);
2591
2592 if (pci_enable_device(pdev)) {
2593 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2594 status = -ENODEV;
2595 goto abort_with_netdev;
2596 }
2597 myri10ge_select_firmware(mgp);
2598
2599 /* Find the vendor-specific cap so we can check
2600 * the reboot register later on */
2601 mgp->vendor_specific_offset
2602 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2603
2604 /* Set our max read request to 4KB */
2605 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2606 if (cap < 64) {
2607 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2608 goto abort_with_netdev;
2609 }
2610 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2611 if (status != 0) {
2612 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2613 status);
2614 goto abort_with_netdev;
2615 }
2616 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2617 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2618 if (status != 0) {
2619 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2620 status);
2621 goto abort_with_netdev;
2622 }
2623
2624 pci_set_master(pdev);
2625 dac_enabled = 1;
2626 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2627 if (status != 0) {
2628 dac_enabled = 0;
2629 dev_err(&pdev->dev,
2630 "64-bit pci address mask was refused, trying 32-bit");
2631 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2632 }
2633 if (status != 0) {
2634 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2635 goto abort_with_netdev;
2636 }
2637 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2638 &mgp->cmd_bus, GFP_KERNEL);
2639 if (mgp->cmd == NULL)
2640 goto abort_with_netdev;
2641
2642 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2643 &mgp->fw_stats_bus, GFP_KERNEL);
2644 if (mgp->fw_stats == NULL)
2645 goto abort_with_cmd;
2646
2647 mgp->board_span = pci_resource_len(pdev, 0);
2648 mgp->iomem_base = pci_resource_start(pdev, 0);
2649 mgp->mtrr = -1;
2650 #ifdef CONFIG_MTRR
2651 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2652 MTRR_TYPE_WRCOMB, 1);
2653 #endif
2654 /* Hack. need to get rid of these magic numbers */
2655 mgp->sram_size =
2656 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2657 if (mgp->sram_size > mgp->board_span) {
2658 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2659 mgp->board_span);
2660 goto abort_with_wc;
2661 }
2662 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2663 if (mgp->sram == NULL) {
2664 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2665 mgp->board_span, mgp->iomem_base);
2666 status = -ENXIO;
2667 goto abort_with_wc;
2668 }
2669 memcpy_fromio(mgp->eeprom_strings,
2670 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2671 MYRI10GE_EEPROM_STRINGS_SIZE);
2672 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2673 status = myri10ge_read_mac_addr(mgp);
2674 if (status)
2675 goto abort_with_ioremap;
2676
2677 for (i = 0; i < ETH_ALEN; i++)
2678 netdev->dev_addr[i] = mgp->mac_addr[i];
2679
2680 /* allocate rx done ring */
2681 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2682 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2683 &mgp->rx_done.bus, GFP_KERNEL);
2684 if (mgp->rx_done.entry == NULL)
2685 goto abort_with_ioremap;
2686 memset(mgp->rx_done.entry, 0, bytes);
2687
2688 status = myri10ge_load_firmware(mgp);
2689 if (status != 0) {
2690 dev_err(&pdev->dev, "failed to load firmware\n");
2691 goto abort_with_rx_done;
2692 }
2693
2694 status = myri10ge_reset(mgp);
2695 if (status != 0) {
2696 dev_err(&pdev->dev, "failed reset\n");
2697 goto abort_with_firmware;
2698 }
2699
2700 if (myri10ge_msi) {
2701 status = pci_enable_msi(pdev);
2702 if (status != 0)
2703 dev_err(&pdev->dev,
2704 "Error %d setting up MSI; falling back to xPIC\n",
2705 status);
2706 else
2707 mgp->msi_enabled = 1;
2708 }
2709
2710 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2711 netdev->name, mgp);
2712 if (status != 0) {
2713 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2714 goto abort_with_firmware;
2715 }
2716
2717 pci_set_drvdata(pdev, mgp);
2718 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2719 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2720 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2721 myri10ge_initial_mtu = 68;
2722 netdev->mtu = myri10ge_initial_mtu;
2723 netdev->open = myri10ge_open;
2724 netdev->stop = myri10ge_close;
2725 netdev->hard_start_xmit = myri10ge_xmit;
2726 netdev->get_stats = myri10ge_get_stats;
2727 netdev->base_addr = mgp->iomem_base;
2728 netdev->irq = pdev->irq;
2729 netdev->change_mtu = myri10ge_change_mtu;
2730 netdev->set_multicast_list = myri10ge_set_multicast_list;
2731 netdev->set_mac_address = myri10ge_set_mac_address;
2732 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2733 if (dac_enabled)
2734 netdev->features |= NETIF_F_HIGHDMA;
2735 netdev->poll = myri10ge_poll;
2736 netdev->weight = myri10ge_napi_weight;
2737
2738 /* Save configuration space to be restored if the
2739 * nic resets due to a parity error */
2740 myri10ge_save_state(mgp);
2741
2742 /* Setup the watchdog timer */
2743 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2744 (unsigned long)mgp);
2745
2746 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2747 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp);
2748 status = register_netdev(netdev);
2749 if (status != 0) {
2750 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2751 goto abort_with_irq;
2752 }
2753 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2754 (mgp->msi_enabled ? "MSI" : "xPIC"),
2755 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2756 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2757
2758 return 0;
2759
2760 abort_with_irq:
2761 free_irq(pdev->irq, mgp);
2762 if (mgp->msi_enabled)
2763 pci_disable_msi(pdev);
2764
2765 abort_with_firmware:
2766 myri10ge_dummy_rdma(mgp, 0);
2767
2768 abort_with_rx_done:
2769 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2770 dma_free_coherent(&pdev->dev, bytes,
2771 mgp->rx_done.entry, mgp->rx_done.bus);
2772
2773 abort_with_ioremap:
2774 iounmap(mgp->sram);
2775
2776 abort_with_wc:
2777 #ifdef CONFIG_MTRR
2778 if (mgp->mtrr >= 0)
2779 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2780 #endif
2781 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2782 mgp->fw_stats, mgp->fw_stats_bus);
2783
2784 abort_with_cmd:
2785 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2786 mgp->cmd, mgp->cmd_bus);
2787
2788 abort_with_netdev:
2789
2790 free_netdev(netdev);
2791 return status;
2792 }
2793
2794 /*
2795 * myri10ge_remove
2796 *
2797 * Does what is necessary to shutdown one Myrinet device. Called
2798 * once for each Myrinet card by the kernel when a module is
2799 * unloaded.
2800 */
2801 static void myri10ge_remove(struct pci_dev *pdev)
2802 {
2803 struct myri10ge_priv *mgp;
2804 struct net_device *netdev;
2805 size_t bytes;
2806
2807 mgp = pci_get_drvdata(pdev);
2808 if (mgp == NULL)
2809 return;
2810
2811 flush_scheduled_work();
2812 netdev = mgp->dev;
2813 unregister_netdev(netdev);
2814 free_irq(pdev->irq, mgp);
2815 if (mgp->msi_enabled)
2816 pci_disable_msi(pdev);
2817
2818 myri10ge_dummy_rdma(mgp, 0);
2819
2820 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2821 dma_free_coherent(&pdev->dev, bytes,
2822 mgp->rx_done.entry, mgp->rx_done.bus);
2823
2824 iounmap(mgp->sram);
2825
2826 #ifdef CONFIG_MTRR
2827 if (mgp->mtrr >= 0)
2828 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2829 #endif
2830 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2831 mgp->fw_stats, mgp->fw_stats_bus);
2832
2833 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2834 mgp->cmd, mgp->cmd_bus);
2835
2836 free_netdev(netdev);
2837 pci_set_drvdata(pdev, NULL);
2838 }
2839
2840 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
2841
2842 static struct pci_device_id myri10ge_pci_tbl[] = {
2843 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
2844 {0},
2845 };
2846
2847 static struct pci_driver myri10ge_driver = {
2848 .name = "myri10ge",
2849 .probe = myri10ge_probe,
2850 .remove = myri10ge_remove,
2851 .id_table = myri10ge_pci_tbl,
2852 #ifdef CONFIG_PM
2853 .suspend = myri10ge_suspend,
2854 .resume = myri10ge_resume,
2855 #endif
2856 };
2857
2858 static __init int myri10ge_init_module(void)
2859 {
2860 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
2861 MYRI10GE_VERSION_STR);
2862 return pci_register_driver(&myri10ge_driver);
2863 }
2864
2865 module_init(myri10ge_init_module);
2866
2867 static __exit void myri10ge_cleanup_module(void)
2868 {
2869 pci_unregister_driver(&myri10ge_driver);
2870 }
2871
2872 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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