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[PATCH] myri10ge: use netif_msg_link
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.0.0"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA 0xffffffff
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 struct myri10ge_rx_buffer_state {
96 struct sk_buff *skb;
97 DECLARE_PCI_UNMAP_ADDR(bus)
98 DECLARE_PCI_UNMAP_LEN(len)
99 };
100
101 struct myri10ge_tx_buffer_state {
102 struct sk_buff *skb;
103 int last;
104 DECLARE_PCI_UNMAP_ADDR(bus)
105 DECLARE_PCI_UNMAP_LEN(len)
106 };
107
108 struct myri10ge_cmd {
109 u32 data0;
110 u32 data1;
111 u32 data2;
112 };
113
114 struct myri10ge_rx_buf {
115 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
116 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
117 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
118 struct myri10ge_rx_buffer_state *info;
119 int cnt;
120 int alloc_fail;
121 int mask; /* number of rx slots -1 */
122 };
123
124 struct myri10ge_tx_buf {
125 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
126 u8 __iomem *wc_fifo; /* w/c send fifo address */
127 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
128 char *req_bytes;
129 struct myri10ge_tx_buffer_state *info;
130 int mask; /* number of transmit slots -1 */
131 int boundary; /* boundary transmits cannot cross */
132 int req ____cacheline_aligned; /* transmit slots submitted */
133 int pkt_start; /* packets started */
134 int done ____cacheline_aligned; /* transmit slots completed */
135 int pkt_done; /* packets completed */
136 };
137
138 struct myri10ge_rx_done {
139 struct mcp_slot *entry;
140 dma_addr_t bus;
141 int cnt;
142 int idx;
143 };
144
145 struct myri10ge_priv {
146 int running; /* running? */
147 int csum_flag; /* rx_csums? */
148 struct myri10ge_tx_buf tx; /* transmit ring */
149 struct myri10ge_rx_buf rx_small;
150 struct myri10ge_rx_buf rx_big;
151 struct myri10ge_rx_done rx_done;
152 int small_bytes;
153 struct net_device *dev;
154 struct net_device_stats stats;
155 u8 __iomem *sram;
156 int sram_size;
157 unsigned long board_span;
158 unsigned long iomem_base;
159 u32 __iomem *irq_claim;
160 u32 __iomem *irq_deassert;
161 char *mac_addr_string;
162 struct mcp_cmd_response *cmd;
163 dma_addr_t cmd_bus;
164 struct mcp_irq_data *fw_stats;
165 dma_addr_t fw_stats_bus;
166 struct pci_dev *pdev;
167 int msi_enabled;
168 unsigned int link_state;
169 unsigned int rdma_tags_available;
170 int intr_coal_delay;
171 u32 __iomem *intr_coal_delay_ptr;
172 int mtrr;
173 int wake_queue;
174 int stop_queue;
175 int down_cnt;
176 wait_queue_head_t down_wq;
177 struct work_struct watchdog_work;
178 struct timer_list watchdog_timer;
179 int watchdog_tx_done;
180 int watchdog_tx_req;
181 int watchdog_resets;
182 int tx_linearized;
183 int pause;
184 char *fw_name;
185 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
186 char fw_version[128];
187 u8 mac_addr[6]; /* eeprom mac address */
188 unsigned long serial_number;
189 int vendor_specific_offset;
190 u32 devctl;
191 u16 msi_flags;
192 u32 read_dma;
193 u32 write_dma;
194 u32 read_write_dma;
195 u32 link_changes;
196 u32 msg_enable;
197 };
198
199 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
200 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
201
202 static char *myri10ge_fw_name = NULL;
203 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
204 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
205
206 static int myri10ge_ecrc_enable = 1;
207 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
208 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
209
210 static int myri10ge_max_intr_slots = 1024;
211 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
212 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
213
214 static int myri10ge_small_bytes = -1; /* -1 == auto */
215 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
216 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
217
218 static int myri10ge_msi = 1; /* enable msi by default */
219 module_param(myri10ge_msi, int, S_IRUGO);
220 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
221
222 static int myri10ge_intr_coal_delay = 25;
223 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
224 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
225
226 static int myri10ge_flow_control = 1;
227 module_param(myri10ge_flow_control, int, S_IRUGO);
228 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
229
230 static int myri10ge_deassert_wait = 1;
231 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
232 MODULE_PARM_DESC(myri10ge_deassert_wait,
233 "Wait when deasserting legacy interrupts\n");
234
235 static int myri10ge_force_firmware = 0;
236 module_param(myri10ge_force_firmware, int, S_IRUGO);
237 MODULE_PARM_DESC(myri10ge_force_firmware,
238 "Force firmware to assume aligned completions\n");
239
240 static int myri10ge_skb_cross_4k = 0;
241 module_param(myri10ge_skb_cross_4k, int, S_IRUGO | S_IWUSR);
242 MODULE_PARM_DESC(myri10ge_skb_cross_4k,
243 "Can a small skb cross a 4KB boundary?\n");
244
245 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
246 module_param(myri10ge_initial_mtu, int, S_IRUGO);
247 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
248
249 static int myri10ge_napi_weight = 64;
250 module_param(myri10ge_napi_weight, int, S_IRUGO);
251 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
252
253 static int myri10ge_watchdog_timeout = 1;
254 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
255 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
256
257 static int myri10ge_max_irq_loops = 1048576;
258 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
259 MODULE_PARM_DESC(myri10ge_max_irq_loops,
260 "Set stuck legacy IRQ detection threshold\n");
261
262 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
263
264 static int myri10ge_debug = -1; /* defaults above */
265 module_param(myri10ge_debug, int, 0);
266 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
267
268 #define MYRI10GE_FW_OFFSET 1024*1024
269 #define MYRI10GE_HIGHPART_TO_U32(X) \
270 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
271 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
272
273 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
274
275 static int
276 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
277 struct myri10ge_cmd *data, int atomic)
278 {
279 struct mcp_cmd *buf;
280 char buf_bytes[sizeof(*buf) + 8];
281 struct mcp_cmd_response *response = mgp->cmd;
282 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
283 u32 dma_low, dma_high, result, value;
284 int sleep_total = 0;
285
286 /* ensure buf is aligned to 8 bytes */
287 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
288
289 buf->data0 = htonl(data->data0);
290 buf->data1 = htonl(data->data1);
291 buf->data2 = htonl(data->data2);
292 buf->cmd = htonl(cmd);
293 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
294 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
295
296 buf->response_addr.low = htonl(dma_low);
297 buf->response_addr.high = htonl(dma_high);
298 response->result = MYRI10GE_NO_RESPONSE_RESULT;
299 mb();
300 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
301
302 /* wait up to 15ms. Longest command is the DMA benchmark,
303 * which is capped at 5ms, but runs from a timeout handler
304 * that runs every 7.8ms. So a 15ms timeout leaves us with
305 * a 2.2ms margin
306 */
307 if (atomic) {
308 /* if atomic is set, do not sleep,
309 * and try to get the completion quickly
310 * (1ms will be enough for those commands) */
311 for (sleep_total = 0;
312 sleep_total < 1000
313 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
314 sleep_total += 10)
315 udelay(10);
316 } else {
317 /* use msleep for most command */
318 for (sleep_total = 0;
319 sleep_total < 15
320 && response->result == MYRI10GE_NO_RESPONSE_RESULT;
321 sleep_total++)
322 msleep(1);
323 }
324
325 result = ntohl(response->result);
326 value = ntohl(response->data);
327 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
328 if (result == 0) {
329 data->data0 = value;
330 return 0;
331 } else {
332 dev_err(&mgp->pdev->dev,
333 "command %d failed, result = %d\n",
334 cmd, result);
335 return -ENXIO;
336 }
337 }
338
339 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
340 cmd, result);
341 return -EAGAIN;
342 }
343
344 /*
345 * The eeprom strings on the lanaiX have the format
346 * SN=x\0
347 * MAC=x:x:x:x:x:x\0
348 * PT:ddd mmm xx xx:xx:xx xx\0
349 * PV:ddd mmm xx xx:xx:xx xx\0
350 */
351 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
352 {
353 char *ptr, *limit;
354 int i;
355
356 ptr = mgp->eeprom_strings;
357 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
358
359 while (*ptr != '\0' && ptr < limit) {
360 if (memcmp(ptr, "MAC=", 4) == 0) {
361 ptr += 4;
362 mgp->mac_addr_string = ptr;
363 for (i = 0; i < 6; i++) {
364 if ((ptr + 2) > limit)
365 goto abort;
366 mgp->mac_addr[i] =
367 simple_strtoul(ptr, &ptr, 16);
368 ptr += 1;
369 }
370 }
371 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
372 ptr += 3;
373 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
374 }
375 while (ptr < limit && *ptr++) ;
376 }
377
378 return 0;
379
380 abort:
381 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
382 return -ENXIO;
383 }
384
385 /*
386 * Enable or disable periodic RDMAs from the host to make certain
387 * chipsets resend dropped PCIe messages
388 */
389
390 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
391 {
392 char __iomem *submit;
393 u32 buf[16];
394 u32 dma_low, dma_high;
395 int i;
396
397 /* clear confirmation addr */
398 mgp->cmd->data = 0;
399 mb();
400
401 /* send a rdma command to the PCIe engine, and wait for the
402 * response in the confirmation address. The firmware should
403 * write a -1 there to indicate it is alive and well
404 */
405 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
406 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
407
408 buf[0] = htonl(dma_high); /* confirm addr MSW */
409 buf[1] = htonl(dma_low); /* confirm addr LSW */
410 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
411 buf[3] = htonl(dma_high); /* dummy addr MSW */
412 buf[4] = htonl(dma_low); /* dummy addr LSW */
413 buf[5] = htonl(enable); /* enable? */
414
415 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
416
417 myri10ge_pio_copy(submit, &buf, sizeof(buf));
418 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
419 msleep(1);
420 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
421 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
422 (enable ? "enable" : "disable"));
423 }
424
425 static int
426 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
427 struct mcp_gen_header *hdr)
428 {
429 struct device *dev = &mgp->pdev->dev;
430 int major, minor;
431
432 /* check firmware type */
433 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
434 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
435 return -EINVAL;
436 }
437
438 /* save firmware version for ethtool */
439 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
440
441 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
442
443 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
444 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
445 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
446 MXGEFW_VERSION_MINOR);
447 return -EINVAL;
448 }
449 return 0;
450 }
451
452 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
453 {
454 unsigned crc, reread_crc;
455 const struct firmware *fw;
456 struct device *dev = &mgp->pdev->dev;
457 struct mcp_gen_header *hdr;
458 size_t hdr_offset;
459 int status;
460 unsigned i;
461
462 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
463 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
464 mgp->fw_name);
465 status = -EINVAL;
466 goto abort_with_nothing;
467 }
468
469 /* check size */
470
471 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
472 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
473 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
474 status = -EINVAL;
475 goto abort_with_fw;
476 }
477
478 /* check id */
479 hdr_offset = ntohl(*(u32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
480 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
481 dev_err(dev, "Bad firmware file\n");
482 status = -EINVAL;
483 goto abort_with_fw;
484 }
485 hdr = (void *)(fw->data + hdr_offset);
486
487 status = myri10ge_validate_firmware(mgp, hdr);
488 if (status != 0)
489 goto abort_with_fw;
490
491 crc = crc32(~0, fw->data, fw->size);
492 for (i = 0; i < fw->size; i += 256) {
493 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
494 fw->data + i,
495 min(256U, (unsigned)(fw->size - i)));
496 mb();
497 readb(mgp->sram);
498 }
499 /* corruption checking is good for parity recovery and buggy chipset */
500 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
501 reread_crc = crc32(~0, fw->data, fw->size);
502 if (crc != reread_crc) {
503 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
504 (unsigned)fw->size, reread_crc, crc);
505 status = -EIO;
506 goto abort_with_fw;
507 }
508 *size = (u32) fw->size;
509
510 abort_with_fw:
511 release_firmware(fw);
512
513 abort_with_nothing:
514 return status;
515 }
516
517 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
518 {
519 struct mcp_gen_header *hdr;
520 struct device *dev = &mgp->pdev->dev;
521 const size_t bytes = sizeof(struct mcp_gen_header);
522 size_t hdr_offset;
523 int status;
524
525 /* find running firmware header */
526 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
527
528 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
529 dev_err(dev, "Running firmware has bad header offset (%d)\n",
530 (int)hdr_offset);
531 return -EIO;
532 }
533
534 /* copy header of running firmware from SRAM to host memory to
535 * validate firmware */
536 hdr = kmalloc(bytes, GFP_KERNEL);
537 if (hdr == NULL) {
538 dev_err(dev, "could not malloc firmware hdr\n");
539 return -ENOMEM;
540 }
541 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
542 status = myri10ge_validate_firmware(mgp, hdr);
543 kfree(hdr);
544 return status;
545 }
546
547 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
548 {
549 char __iomem *submit;
550 u32 buf[16];
551 u32 dma_low, dma_high, size;
552 int status, i;
553
554 size = 0;
555 status = myri10ge_load_hotplug_firmware(mgp, &size);
556 if (status) {
557 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
558
559 /* Do not attempt to adopt firmware if there
560 * was a bad crc */
561 if (status == -EIO)
562 return status;
563
564 status = myri10ge_adopt_running_firmware(mgp);
565 if (status != 0) {
566 dev_err(&mgp->pdev->dev,
567 "failed to adopt running firmware\n");
568 return status;
569 }
570 dev_info(&mgp->pdev->dev,
571 "Successfully adopted running firmware\n");
572 if (mgp->tx.boundary == 4096) {
573 dev_warn(&mgp->pdev->dev,
574 "Using firmware currently running on NIC"
575 ". For optimal\n");
576 dev_warn(&mgp->pdev->dev,
577 "performance consider loading optimized "
578 "firmware\n");
579 dev_warn(&mgp->pdev->dev, "via hotplug\n");
580 }
581
582 mgp->fw_name = "adopted";
583 mgp->tx.boundary = 2048;
584 return status;
585 }
586
587 /* clear confirmation addr */
588 mgp->cmd->data = 0;
589 mb();
590
591 /* send a reload command to the bootstrap MCP, and wait for the
592 * response in the confirmation address. The firmware should
593 * write a -1 there to indicate it is alive and well
594 */
595 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
596 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
597
598 buf[0] = htonl(dma_high); /* confirm addr MSW */
599 buf[1] = htonl(dma_low); /* confirm addr LSW */
600 buf[2] = htonl(MYRI10GE_NO_CONFIRM_DATA); /* confirm data */
601
602 /* FIX: All newest firmware should un-protect the bottom of
603 * the sram before handoff. However, the very first interfaces
604 * do not. Therefore the handoff copy must skip the first 8 bytes
605 */
606 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
607 buf[4] = htonl(size - 8); /* length of code */
608 buf[5] = htonl(8); /* where to copy to */
609 buf[6] = htonl(0); /* where to jump to */
610
611 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
612
613 myri10ge_pio_copy(submit, &buf, sizeof(buf));
614 mb();
615 msleep(1);
616 mb();
617 i = 0;
618 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
619 msleep(1);
620 i++;
621 }
622 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
623 dev_err(&mgp->pdev->dev, "handoff failed\n");
624 return -ENXIO;
625 }
626 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
627 myri10ge_dummy_rdma(mgp, 1);
628
629 return 0;
630 }
631
632 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
633 {
634 struct myri10ge_cmd cmd;
635 int status;
636
637 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
638 | (addr[2] << 8) | addr[3]);
639
640 cmd.data1 = ((addr[4] << 8) | (addr[5]));
641
642 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
643 return status;
644 }
645
646 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
647 {
648 struct myri10ge_cmd cmd;
649 int status, ctl;
650
651 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
652 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
653
654 if (status) {
655 printk(KERN_ERR
656 "myri10ge: %s: Failed to set flow control mode\n",
657 mgp->dev->name);
658 return status;
659 }
660 mgp->pause = pause;
661 return 0;
662 }
663
664 static void
665 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
666 {
667 struct myri10ge_cmd cmd;
668 int status, ctl;
669
670 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
671 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
672 if (status)
673 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
674 mgp->dev->name);
675 }
676
677 static int myri10ge_reset(struct myri10ge_priv *mgp)
678 {
679 struct myri10ge_cmd cmd;
680 int status;
681 size_t bytes;
682 u32 len;
683
684 /* try to send a reset command to the card to see if it
685 * is alive */
686 memset(&cmd, 0, sizeof(cmd));
687 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
688 if (status != 0) {
689 dev_err(&mgp->pdev->dev, "failed reset\n");
690 return -ENXIO;
691 }
692
693 /* Now exchange information about interrupts */
694
695 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
696 memset(mgp->rx_done.entry, 0, bytes);
697 cmd.data0 = (u32) bytes;
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
699 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
700 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
701 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
702
703 status |=
704 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
705 mgp->irq_claim = (__iomem u32 *) (mgp->sram + cmd.data0);
706 if (!mgp->msi_enabled) {
707 status |= myri10ge_send_cmd
708 (mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, &cmd, 0);
709 mgp->irq_deassert = (__iomem u32 *) (mgp->sram + cmd.data0);
710
711 }
712 status |= myri10ge_send_cmd
713 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
714 mgp->intr_coal_delay_ptr = (__iomem u32 *) (mgp->sram + cmd.data0);
715 if (status != 0) {
716 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
717 return status;
718 }
719 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
720
721 /* Run a small DMA test.
722 * The magic multipliers to the length tell the firmware
723 * to do DMA read, write, or read+write tests. The
724 * results are returned in cmd.data0. The upper 16
725 * bits or the return is the number of transfers completed.
726 * The lower 16 bits is the time in 0.5us ticks that the
727 * transfers took to complete.
728 */
729
730 len = mgp->tx.boundary;
731
732 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
733 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
734 cmd.data2 = len * 0x10000;
735 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
736 if (status == 0)
737 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
738 (cmd.data0 & 0xffff);
739 else
740 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
741 status);
742 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
743 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
744 cmd.data2 = len * 0x1;
745 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
746 if (status == 0)
747 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
748 (cmd.data0 & 0xffff);
749 else
750 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
751 status);
752
753 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
754 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
755 cmd.data2 = len * 0x10001;
756 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
757 if (status == 0)
758 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
759 (cmd.data0 & 0xffff);
760 else
761 dev_warn(&mgp->pdev->dev,
762 "DMA read/write benchmark failed: %d\n", status);
763
764 memset(mgp->rx_done.entry, 0, bytes);
765
766 /* reset mcp/driver shared state back to 0 */
767 mgp->tx.req = 0;
768 mgp->tx.done = 0;
769 mgp->tx.pkt_start = 0;
770 mgp->tx.pkt_done = 0;
771 mgp->rx_big.cnt = 0;
772 mgp->rx_small.cnt = 0;
773 mgp->rx_done.idx = 0;
774 mgp->rx_done.cnt = 0;
775 mgp->link_changes = 0;
776 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
777 myri10ge_change_promisc(mgp, 0, 0);
778 myri10ge_change_pause(mgp, mgp->pause);
779 return status;
780 }
781
782 static inline void
783 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
784 struct mcp_kreq_ether_recv *src)
785 {
786 u32 low;
787
788 low = src->addr_low;
789 src->addr_low = DMA_32BIT_MASK;
790 myri10ge_pio_copy(dst, src, 8 * sizeof(*src));
791 mb();
792 src->addr_low = low;
793 __raw_writel(low, &dst->addr_low);
794 mb();
795 }
796
797 /*
798 * Set of routines to get a new receive buffer. Any buffer which
799 * crosses a 4KB boundary must start on a 4KB boundary due to PCIe
800 * wdma restrictions. We also try to align any smaller allocation to
801 * at least a 16 byte boundary for efficiency. We assume the linux
802 * memory allocator works by powers of 2, and will not return memory
803 * smaller than 2KB which crosses a 4KB boundary. If it does, we fall
804 * back to allocating 2x as much space as required.
805 *
806 * We intend to replace large (>4KB) skb allocations by using
807 * pages directly and building a fraglist in the near future.
808 */
809
810 static inline struct sk_buff *myri10ge_alloc_big(struct net_device *dev,
811 int bytes)
812 {
813 struct sk_buff *skb;
814 unsigned long data, roundup;
815
816 skb = netdev_alloc_skb(dev, bytes + 4096 + MXGEFW_PAD);
817 if (skb == NULL)
818 return NULL;
819
820 /* Correct skb->truesize so that socket buffer
821 * accounting is not confused the rounding we must
822 * do to satisfy alignment constraints.
823 */
824 skb->truesize -= 4096;
825
826 data = (unsigned long)(skb->data);
827 roundup = (-data) & (4095);
828 skb_reserve(skb, roundup);
829 return skb;
830 }
831
832 /* Allocate 2x as much space as required and use whichever portion
833 * does not cross a 4KB boundary */
834 static inline struct sk_buff *myri10ge_alloc_small_safe(struct net_device *dev,
835 unsigned int bytes)
836 {
837 struct sk_buff *skb;
838 unsigned long data, boundary;
839
840 skb = netdev_alloc_skb(dev, 2 * (bytes + MXGEFW_PAD) - 1);
841 if (unlikely(skb == NULL))
842 return NULL;
843
844 /* Correct skb->truesize so that socket buffer
845 * accounting is not confused the rounding we must
846 * do to satisfy alignment constraints.
847 */
848 skb->truesize -= bytes + MXGEFW_PAD;
849
850 data = (unsigned long)(skb->data);
851 boundary = (data + 4095UL) & ~4095UL;
852 if ((boundary - data) >= (bytes + MXGEFW_PAD))
853 return skb;
854
855 skb_reserve(skb, boundary - data);
856 return skb;
857 }
858
859 /* Allocate just enough space, and verify that the allocated
860 * space does not cross a 4KB boundary */
861 static inline struct sk_buff *myri10ge_alloc_small(struct net_device *dev,
862 int bytes)
863 {
864 struct sk_buff *skb;
865 unsigned long roundup, data, end;
866
867 skb = netdev_alloc_skb(dev, bytes + 16 + MXGEFW_PAD);
868 if (unlikely(skb == NULL))
869 return NULL;
870
871 /* Round allocated buffer to 16 byte boundary */
872 data = (unsigned long)(skb->data);
873 roundup = (-data) & 15UL;
874 skb_reserve(skb, roundup);
875 /* Verify that the data buffer does not cross a page boundary */
876 data = (unsigned long)(skb->data);
877 end = data + bytes + MXGEFW_PAD - 1;
878 if (unlikely(((end >> 12) != (data >> 12)) && (data & 4095UL))) {
879 printk(KERN_NOTICE
880 "myri10ge_alloc_small: small skb crossed 4KB boundary\n");
881 myri10ge_skb_cross_4k = 1;
882 dev_kfree_skb_any(skb);
883 skb = myri10ge_alloc_small_safe(dev, bytes);
884 }
885 return skb;
886 }
887
888 static inline int
889 myri10ge_getbuf(struct myri10ge_rx_buf *rx, struct myri10ge_priv *mgp,
890 int bytes, int idx)
891 {
892 struct net_device *dev = mgp->dev;
893 struct pci_dev *pdev = mgp->pdev;
894 struct sk_buff *skb;
895 dma_addr_t bus;
896 int len, retval = 0;
897
898 bytes += VLAN_HLEN; /* account for 802.1q vlan tag */
899
900 if ((bytes + MXGEFW_PAD) > (4096 - 16) /* linux overhead */ )
901 skb = myri10ge_alloc_big(dev, bytes);
902 else if (myri10ge_skb_cross_4k)
903 skb = myri10ge_alloc_small_safe(dev, bytes);
904 else
905 skb = myri10ge_alloc_small(dev, bytes);
906
907 if (unlikely(skb == NULL)) {
908 rx->alloc_fail++;
909 retval = -ENOBUFS;
910 goto done;
911 }
912
913 /* set len so that it only covers the area we
914 * need mapped for DMA */
915 len = bytes + MXGEFW_PAD;
916
917 bus = pci_map_single(pdev, skb->data, len, PCI_DMA_FROMDEVICE);
918 rx->info[idx].skb = skb;
919 pci_unmap_addr_set(&rx->info[idx], bus, bus);
920 pci_unmap_len_set(&rx->info[idx], len, len);
921 rx->shadow[idx].addr_low = htonl(MYRI10GE_LOWPART_TO_U32(bus));
922 rx->shadow[idx].addr_high = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
923
924 done:
925 /* copy 8 descriptors (64-bytes) to the mcp at a time */
926 if ((idx & 7) == 7) {
927 if (rx->wc_fifo == NULL)
928 myri10ge_submit_8rx(&rx->lanai[idx - 7],
929 &rx->shadow[idx - 7]);
930 else {
931 mb();
932 myri10ge_pio_copy(rx->wc_fifo,
933 &rx->shadow[idx - 7], 64);
934 }
935 }
936 return retval;
937 }
938
939 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, u16 hw_csum)
940 {
941 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
942
943 if ((skb->protocol == ntohs(ETH_P_8021Q)) &&
944 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
945 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
946 skb->csum = hw_csum;
947 skb->ip_summed = CHECKSUM_HW;
948 }
949 }
950
951 static inline unsigned long
952 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
953 int bytes, int len, int csum)
954 {
955 dma_addr_t bus;
956 struct sk_buff *skb;
957 int idx, unmap_len;
958
959 idx = rx->cnt & rx->mask;
960 rx->cnt++;
961
962 /* save a pointer to the received skb */
963 skb = rx->info[idx].skb;
964 bus = pci_unmap_addr(&rx->info[idx], bus);
965 unmap_len = pci_unmap_len(&rx->info[idx], len);
966
967 /* try to replace the received skb */
968 if (myri10ge_getbuf(rx, mgp, bytes, idx)) {
969 /* drop the frame -- the old skbuf is re-cycled */
970 mgp->stats.rx_dropped += 1;
971 return 0;
972 }
973
974 /* unmap the recvd skb */
975 pci_unmap_single(mgp->pdev, bus, unmap_len, PCI_DMA_FROMDEVICE);
976
977 /* mcp implicitly skips 1st bytes so that packet is properly
978 * aligned */
979 skb_reserve(skb, MXGEFW_PAD);
980
981 /* set the length of the frame */
982 skb_put(skb, len);
983
984 skb->protocol = eth_type_trans(skb, mgp->dev);
985 if (mgp->csum_flag) {
986 if ((skb->protocol == ntohs(ETH_P_IP)) ||
987 (skb->protocol == ntohs(ETH_P_IPV6))) {
988 skb->csum = ntohs((u16) csum);
989 skb->ip_summed = CHECKSUM_HW;
990 } else
991 myri10ge_vlan_ip_csum(skb, ntohs((u16) csum));
992 }
993
994 netif_receive_skb(skb);
995 mgp->dev->last_rx = jiffies;
996 return 1;
997 }
998
999 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1000 {
1001 struct pci_dev *pdev = mgp->pdev;
1002 struct myri10ge_tx_buf *tx = &mgp->tx;
1003 struct sk_buff *skb;
1004 int idx, len;
1005 int limit = 0;
1006
1007 while (tx->pkt_done != mcp_index) {
1008 idx = tx->done & tx->mask;
1009 skb = tx->info[idx].skb;
1010
1011 /* Mark as free */
1012 tx->info[idx].skb = NULL;
1013 if (tx->info[idx].last) {
1014 tx->pkt_done++;
1015 tx->info[idx].last = 0;
1016 }
1017 tx->done++;
1018 len = pci_unmap_len(&tx->info[idx], len);
1019 pci_unmap_len_set(&tx->info[idx], len, 0);
1020 if (skb) {
1021 mgp->stats.tx_bytes += skb->len;
1022 mgp->stats.tx_packets++;
1023 dev_kfree_skb_irq(skb);
1024 if (len)
1025 pci_unmap_single(pdev,
1026 pci_unmap_addr(&tx->info[idx],
1027 bus), len,
1028 PCI_DMA_TODEVICE);
1029 } else {
1030 if (len)
1031 pci_unmap_page(pdev,
1032 pci_unmap_addr(&tx->info[idx],
1033 bus), len,
1034 PCI_DMA_TODEVICE);
1035 }
1036
1037 /* limit potential for livelock by only handling
1038 * 2 full tx rings per call */
1039 if (unlikely(++limit > 2 * tx->mask))
1040 break;
1041 }
1042 /* start the queue if we've stopped it */
1043 if (netif_queue_stopped(mgp->dev)
1044 && tx->req - tx->done < (tx->mask >> 1)) {
1045 mgp->wake_queue++;
1046 netif_wake_queue(mgp->dev);
1047 }
1048 }
1049
1050 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1051 {
1052 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1053 unsigned long rx_bytes = 0;
1054 unsigned long rx_packets = 0;
1055 unsigned long rx_ok;
1056
1057 int idx = rx_done->idx;
1058 int cnt = rx_done->cnt;
1059 u16 length;
1060 u16 checksum;
1061
1062 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1063 length = ntohs(rx_done->entry[idx].length);
1064 rx_done->entry[idx].length = 0;
1065 checksum = ntohs(rx_done->entry[idx].checksum);
1066 if (length <= mgp->small_bytes)
1067 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1068 mgp->small_bytes,
1069 length, checksum);
1070 else
1071 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1072 mgp->dev->mtu + ETH_HLEN,
1073 length, checksum);
1074 rx_packets += rx_ok;
1075 rx_bytes += rx_ok * (unsigned long)length;
1076 cnt++;
1077 idx = cnt & (myri10ge_max_intr_slots - 1);
1078
1079 /* limit potential for livelock by only handling a
1080 * limited number of frames. */
1081 (*limit)--;
1082 }
1083 rx_done->idx = idx;
1084 rx_done->cnt = cnt;
1085 mgp->stats.rx_packets += rx_packets;
1086 mgp->stats.rx_bytes += rx_bytes;
1087 }
1088
1089 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1090 {
1091 struct mcp_irq_data *stats = mgp->fw_stats;
1092
1093 if (unlikely(stats->stats_updated)) {
1094 if (mgp->link_state != stats->link_up) {
1095 mgp->link_state = stats->link_up;
1096 if (mgp->link_state) {
1097 if (netif_msg_link(mgp))
1098 printk(KERN_INFO
1099 "myri10ge: %s: link up\n",
1100 mgp->dev->name);
1101 netif_carrier_on(mgp->dev);
1102 mgp->link_changes++;
1103 } else {
1104 if (netif_msg_link(mgp))
1105 printk(KERN_INFO
1106 "myri10ge: %s: link down\n",
1107 mgp->dev->name);
1108 netif_carrier_off(mgp->dev);
1109 mgp->link_changes++;
1110 }
1111 }
1112 if (mgp->rdma_tags_available !=
1113 ntohl(mgp->fw_stats->rdma_tags_available)) {
1114 mgp->rdma_tags_available =
1115 ntohl(mgp->fw_stats->rdma_tags_available);
1116 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1117 "%d tags left\n", mgp->dev->name,
1118 mgp->rdma_tags_available);
1119 }
1120 mgp->down_cnt += stats->link_down;
1121 if (stats->link_down)
1122 wake_up(&mgp->down_wq);
1123 }
1124 }
1125
1126 static int myri10ge_poll(struct net_device *netdev, int *budget)
1127 {
1128 struct myri10ge_priv *mgp = netdev_priv(netdev);
1129 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1130 int limit, orig_limit, work_done;
1131
1132 /* process as many rx events as NAPI will allow */
1133 limit = min(*budget, netdev->quota);
1134 orig_limit = limit;
1135 myri10ge_clean_rx_done(mgp, &limit);
1136 work_done = orig_limit - limit;
1137 *budget -= work_done;
1138 netdev->quota -= work_done;
1139
1140 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1141 netif_rx_complete(netdev);
1142 __raw_writel(htonl(3), mgp->irq_claim);
1143 return 0;
1144 }
1145 return 1;
1146 }
1147
1148 static irqreturn_t myri10ge_intr(int irq, void *arg, struct pt_regs *regs)
1149 {
1150 struct myri10ge_priv *mgp = arg;
1151 struct mcp_irq_data *stats = mgp->fw_stats;
1152 struct myri10ge_tx_buf *tx = &mgp->tx;
1153 u32 send_done_count;
1154 int i;
1155
1156 /* make sure it is our IRQ, and that the DMA has finished */
1157 if (unlikely(!stats->valid))
1158 return (IRQ_NONE);
1159
1160 /* low bit indicates receives are present, so schedule
1161 * napi poll handler */
1162 if (stats->valid & 1)
1163 netif_rx_schedule(mgp->dev);
1164
1165 if (!mgp->msi_enabled) {
1166 __raw_writel(0, mgp->irq_deassert);
1167 if (!myri10ge_deassert_wait)
1168 stats->valid = 0;
1169 mb();
1170 } else
1171 stats->valid = 0;
1172
1173 /* Wait for IRQ line to go low, if using INTx */
1174 i = 0;
1175 while (1) {
1176 i++;
1177 /* check for transmit completes and receives */
1178 send_done_count = ntohl(stats->send_done_count);
1179 if (send_done_count != tx->pkt_done)
1180 myri10ge_tx_done(mgp, (int)send_done_count);
1181 if (unlikely(i > myri10ge_max_irq_loops)) {
1182 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1183 mgp->dev->name);
1184 stats->valid = 0;
1185 schedule_work(&mgp->watchdog_work);
1186 }
1187 if (likely(stats->valid == 0))
1188 break;
1189 cpu_relax();
1190 barrier();
1191 }
1192
1193 myri10ge_check_statblock(mgp);
1194
1195 __raw_writel(htonl(3), mgp->irq_claim + 1);
1196 return (IRQ_HANDLED);
1197 }
1198
1199 static int
1200 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1201 {
1202 cmd->autoneg = AUTONEG_DISABLE;
1203 cmd->speed = SPEED_10000;
1204 cmd->duplex = DUPLEX_FULL;
1205 return 0;
1206 }
1207
1208 static void
1209 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1210 {
1211 struct myri10ge_priv *mgp = netdev_priv(netdev);
1212
1213 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1214 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1215 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1216 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1217 }
1218
1219 static int
1220 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1221 {
1222 struct myri10ge_priv *mgp = netdev_priv(netdev);
1223 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1224 return 0;
1225 }
1226
1227 static int
1228 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1229 {
1230 struct myri10ge_priv *mgp = netdev_priv(netdev);
1231
1232 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1233 __raw_writel(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1234 return 0;
1235 }
1236
1237 static void
1238 myri10ge_get_pauseparam(struct net_device *netdev,
1239 struct ethtool_pauseparam *pause)
1240 {
1241 struct myri10ge_priv *mgp = netdev_priv(netdev);
1242
1243 pause->autoneg = 0;
1244 pause->rx_pause = mgp->pause;
1245 pause->tx_pause = mgp->pause;
1246 }
1247
1248 static int
1249 myri10ge_set_pauseparam(struct net_device *netdev,
1250 struct ethtool_pauseparam *pause)
1251 {
1252 struct myri10ge_priv *mgp = netdev_priv(netdev);
1253
1254 if (pause->tx_pause != mgp->pause)
1255 return myri10ge_change_pause(mgp, pause->tx_pause);
1256 if (pause->rx_pause != mgp->pause)
1257 return myri10ge_change_pause(mgp, pause->tx_pause);
1258 if (pause->autoneg != 0)
1259 return -EINVAL;
1260 return 0;
1261 }
1262
1263 static void
1264 myri10ge_get_ringparam(struct net_device *netdev,
1265 struct ethtool_ringparam *ring)
1266 {
1267 struct myri10ge_priv *mgp = netdev_priv(netdev);
1268
1269 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1270 ring->rx_max_pending = mgp->rx_big.mask + 1;
1271 ring->rx_jumbo_max_pending = 0;
1272 ring->tx_max_pending = mgp->rx_small.mask + 1;
1273 ring->rx_mini_pending = ring->rx_mini_max_pending;
1274 ring->rx_pending = ring->rx_max_pending;
1275 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1276 ring->tx_pending = ring->tx_max_pending;
1277 }
1278
1279 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1280 {
1281 struct myri10ge_priv *mgp = netdev_priv(netdev);
1282 if (mgp->csum_flag)
1283 return 1;
1284 else
1285 return 0;
1286 }
1287
1288 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1289 {
1290 struct myri10ge_priv *mgp = netdev_priv(netdev);
1291 if (csum_enabled)
1292 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1293 else
1294 mgp->csum_flag = 0;
1295 return 0;
1296 }
1297
1298 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1299 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1300 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1301 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1302 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1303 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1304 "tx_heartbeat_errors", "tx_window_errors",
1305 /* device-specific stats */
1306 "tx_boundary", "WC", "irq", "MSI",
1307 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1308 "serial_number", "tx_pkt_start", "tx_pkt_done",
1309 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1310 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1311 "link_changes", "link_up", "dropped_link_overflow",
1312 "dropped_link_error_or_filtered", "dropped_runt",
1313 "dropped_overrun", "dropped_no_small_buffer",
1314 "dropped_no_big_buffer"
1315 };
1316
1317 #define MYRI10GE_NET_STATS_LEN 21
1318 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1319
1320 static void
1321 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1322 {
1323 switch (stringset) {
1324 case ETH_SS_STATS:
1325 memcpy(data, *myri10ge_gstrings_stats,
1326 sizeof(myri10ge_gstrings_stats));
1327 break;
1328 }
1329 }
1330
1331 static int myri10ge_get_stats_count(struct net_device *netdev)
1332 {
1333 return MYRI10GE_STATS_LEN;
1334 }
1335
1336 static void
1337 myri10ge_get_ethtool_stats(struct net_device *netdev,
1338 struct ethtool_stats *stats, u64 * data)
1339 {
1340 struct myri10ge_priv *mgp = netdev_priv(netdev);
1341 int i;
1342
1343 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1344 data[i] = ((unsigned long *)&mgp->stats)[i];
1345
1346 data[i++] = (unsigned int)mgp->tx.boundary;
1347 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1348 data[i++] = (unsigned int)mgp->pdev->irq;
1349 data[i++] = (unsigned int)mgp->msi_enabled;
1350 data[i++] = (unsigned int)mgp->read_dma;
1351 data[i++] = (unsigned int)mgp->write_dma;
1352 data[i++] = (unsigned int)mgp->read_write_dma;
1353 data[i++] = (unsigned int)mgp->serial_number;
1354 data[i++] = (unsigned int)mgp->tx.pkt_start;
1355 data[i++] = (unsigned int)mgp->tx.pkt_done;
1356 data[i++] = (unsigned int)mgp->tx.req;
1357 data[i++] = (unsigned int)mgp->tx.done;
1358 data[i++] = (unsigned int)mgp->rx_small.cnt;
1359 data[i++] = (unsigned int)mgp->rx_big.cnt;
1360 data[i++] = (unsigned int)mgp->wake_queue;
1361 data[i++] = (unsigned int)mgp->stop_queue;
1362 data[i++] = (unsigned int)mgp->watchdog_resets;
1363 data[i++] = (unsigned int)mgp->tx_linearized;
1364 data[i++] = (unsigned int)mgp->link_changes;
1365 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1366 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1367 data[i++] =
1368 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1369 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1370 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1371 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1372 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1373 }
1374
1375 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1376 {
1377 struct myri10ge_priv *mgp = netdev_priv(netdev);
1378 mgp->msg_enable = value;
1379 }
1380
1381 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1382 {
1383 struct myri10ge_priv *mgp = netdev_priv(netdev);
1384 return mgp->msg_enable;
1385 }
1386
1387 static struct ethtool_ops myri10ge_ethtool_ops = {
1388 .get_settings = myri10ge_get_settings,
1389 .get_drvinfo = myri10ge_get_drvinfo,
1390 .get_coalesce = myri10ge_get_coalesce,
1391 .set_coalesce = myri10ge_set_coalesce,
1392 .get_pauseparam = myri10ge_get_pauseparam,
1393 .set_pauseparam = myri10ge_set_pauseparam,
1394 .get_ringparam = myri10ge_get_ringparam,
1395 .get_rx_csum = myri10ge_get_rx_csum,
1396 .set_rx_csum = myri10ge_set_rx_csum,
1397 .get_tx_csum = ethtool_op_get_tx_csum,
1398 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1399 .get_sg = ethtool_op_get_sg,
1400 .set_sg = ethtool_op_set_sg,
1401 #ifdef NETIF_F_TSO
1402 .get_tso = ethtool_op_get_tso,
1403 .set_tso = ethtool_op_set_tso,
1404 #endif
1405 .get_strings = myri10ge_get_strings,
1406 .get_stats_count = myri10ge_get_stats_count,
1407 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1408 .set_msglevel = myri10ge_set_msglevel,
1409 .get_msglevel = myri10ge_get_msglevel
1410 };
1411
1412 static int myri10ge_allocate_rings(struct net_device *dev)
1413 {
1414 struct myri10ge_priv *mgp;
1415 struct myri10ge_cmd cmd;
1416 int tx_ring_size, rx_ring_size;
1417 int tx_ring_entries, rx_ring_entries;
1418 int i, status;
1419 size_t bytes;
1420
1421 mgp = netdev_priv(dev);
1422
1423 /* get ring sizes */
1424
1425 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1426 tx_ring_size = cmd.data0;
1427 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1428 rx_ring_size = cmd.data0;
1429
1430 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1431 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1432 mgp->tx.mask = tx_ring_entries - 1;
1433 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1434
1435 /* allocate the host shadow rings */
1436
1437 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1438 * sizeof(*mgp->tx.req_list);
1439 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1440 if (mgp->tx.req_bytes == NULL)
1441 goto abort_with_nothing;
1442
1443 /* ensure req_list entries are aligned to 8 bytes */
1444 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1445 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1446
1447 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1448 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1449 if (mgp->rx_small.shadow == NULL)
1450 goto abort_with_tx_req_bytes;
1451
1452 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1453 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1454 if (mgp->rx_big.shadow == NULL)
1455 goto abort_with_rx_small_shadow;
1456
1457 /* allocate the host info rings */
1458
1459 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1460 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1461 if (mgp->tx.info == NULL)
1462 goto abort_with_rx_big_shadow;
1463
1464 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1465 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1466 if (mgp->rx_small.info == NULL)
1467 goto abort_with_tx_info;
1468
1469 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1470 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1471 if (mgp->rx_big.info == NULL)
1472 goto abort_with_rx_small_info;
1473
1474 /* Fill the receive rings */
1475
1476 for (i = 0; i <= mgp->rx_small.mask; i++) {
1477 status = myri10ge_getbuf(&mgp->rx_small, mgp,
1478 mgp->small_bytes, i);
1479 if (status) {
1480 printk(KERN_ERR
1481 "myri10ge: %s: alloced only %d small bufs\n",
1482 dev->name, i);
1483 goto abort_with_rx_small_ring;
1484 }
1485 }
1486
1487 for (i = 0; i <= mgp->rx_big.mask; i++) {
1488 status =
1489 myri10ge_getbuf(&mgp->rx_big, mgp, dev->mtu + ETH_HLEN, i);
1490 if (status) {
1491 printk(KERN_ERR
1492 "myri10ge: %s: alloced only %d big bufs\n",
1493 dev->name, i);
1494 goto abort_with_rx_big_ring;
1495 }
1496 }
1497
1498 return 0;
1499
1500 abort_with_rx_big_ring:
1501 for (i = 0; i <= mgp->rx_big.mask; i++) {
1502 if (mgp->rx_big.info[i].skb != NULL)
1503 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1504 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1505 pci_unmap_single(mgp->pdev,
1506 pci_unmap_addr(&mgp->rx_big.info[i],
1507 bus),
1508 pci_unmap_len(&mgp->rx_big.info[i],
1509 len),
1510 PCI_DMA_FROMDEVICE);
1511 }
1512
1513 abort_with_rx_small_ring:
1514 for (i = 0; i <= mgp->rx_small.mask; i++) {
1515 if (mgp->rx_small.info[i].skb != NULL)
1516 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1517 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1518 pci_unmap_single(mgp->pdev,
1519 pci_unmap_addr(&mgp->rx_small.info[i],
1520 bus),
1521 pci_unmap_len(&mgp->rx_small.info[i],
1522 len),
1523 PCI_DMA_FROMDEVICE);
1524 }
1525 kfree(mgp->rx_big.info);
1526
1527 abort_with_rx_small_info:
1528 kfree(mgp->rx_small.info);
1529
1530 abort_with_tx_info:
1531 kfree(mgp->tx.info);
1532
1533 abort_with_rx_big_shadow:
1534 kfree(mgp->rx_big.shadow);
1535
1536 abort_with_rx_small_shadow:
1537 kfree(mgp->rx_small.shadow);
1538
1539 abort_with_tx_req_bytes:
1540 kfree(mgp->tx.req_bytes);
1541 mgp->tx.req_bytes = NULL;
1542 mgp->tx.req_list = NULL;
1543
1544 abort_with_nothing:
1545 return status;
1546 }
1547
1548 static void myri10ge_free_rings(struct net_device *dev)
1549 {
1550 struct myri10ge_priv *mgp;
1551 struct sk_buff *skb;
1552 struct myri10ge_tx_buf *tx;
1553 int i, len, idx;
1554
1555 mgp = netdev_priv(dev);
1556
1557 for (i = 0; i <= mgp->rx_big.mask; i++) {
1558 if (mgp->rx_big.info[i].skb != NULL)
1559 dev_kfree_skb_any(mgp->rx_big.info[i].skb);
1560 if (pci_unmap_len(&mgp->rx_big.info[i], len))
1561 pci_unmap_single(mgp->pdev,
1562 pci_unmap_addr(&mgp->rx_big.info[i],
1563 bus),
1564 pci_unmap_len(&mgp->rx_big.info[i],
1565 len),
1566 PCI_DMA_FROMDEVICE);
1567 }
1568
1569 for (i = 0; i <= mgp->rx_small.mask; i++) {
1570 if (mgp->rx_small.info[i].skb != NULL)
1571 dev_kfree_skb_any(mgp->rx_small.info[i].skb);
1572 if (pci_unmap_len(&mgp->rx_small.info[i], len))
1573 pci_unmap_single(mgp->pdev,
1574 pci_unmap_addr(&mgp->rx_small.info[i],
1575 bus),
1576 pci_unmap_len(&mgp->rx_small.info[i],
1577 len),
1578 PCI_DMA_FROMDEVICE);
1579 }
1580
1581 tx = &mgp->tx;
1582 while (tx->done != tx->req) {
1583 idx = tx->done & tx->mask;
1584 skb = tx->info[idx].skb;
1585
1586 /* Mark as free */
1587 tx->info[idx].skb = NULL;
1588 tx->done++;
1589 len = pci_unmap_len(&tx->info[idx], len);
1590 pci_unmap_len_set(&tx->info[idx], len, 0);
1591 if (skb) {
1592 mgp->stats.tx_dropped++;
1593 dev_kfree_skb_any(skb);
1594 if (len)
1595 pci_unmap_single(mgp->pdev,
1596 pci_unmap_addr(&tx->info[idx],
1597 bus), len,
1598 PCI_DMA_TODEVICE);
1599 } else {
1600 if (len)
1601 pci_unmap_page(mgp->pdev,
1602 pci_unmap_addr(&tx->info[idx],
1603 bus), len,
1604 PCI_DMA_TODEVICE);
1605 }
1606 }
1607 kfree(mgp->rx_big.info);
1608
1609 kfree(mgp->rx_small.info);
1610
1611 kfree(mgp->tx.info);
1612
1613 kfree(mgp->rx_big.shadow);
1614
1615 kfree(mgp->rx_small.shadow);
1616
1617 kfree(mgp->tx.req_bytes);
1618 mgp->tx.req_bytes = NULL;
1619 mgp->tx.req_list = NULL;
1620 }
1621
1622 static int myri10ge_open(struct net_device *dev)
1623 {
1624 struct myri10ge_priv *mgp;
1625 struct myri10ge_cmd cmd;
1626 int status, big_pow2;
1627
1628 mgp = netdev_priv(dev);
1629
1630 if (mgp->running != MYRI10GE_ETH_STOPPED)
1631 return -EBUSY;
1632
1633 mgp->running = MYRI10GE_ETH_STARTING;
1634 status = myri10ge_reset(mgp);
1635 if (status != 0) {
1636 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1637 mgp->running = MYRI10GE_ETH_STOPPED;
1638 return -ENXIO;
1639 }
1640
1641 /* decide what small buffer size to use. For good TCP rx
1642 * performance, it is important to not receive 1514 byte
1643 * frames into jumbo buffers, as it confuses the socket buffer
1644 * accounting code, leading to drops and erratic performance.
1645 */
1646
1647 if (dev->mtu <= ETH_DATA_LEN)
1648 mgp->small_bytes = 128; /* enough for a TCP header */
1649 else
1650 mgp->small_bytes = ETH_FRAME_LEN; /* enough for an ETH_DATA_LEN frame */
1651
1652 /* Override the small buffer size? */
1653 if (myri10ge_small_bytes > 0)
1654 mgp->small_bytes = myri10ge_small_bytes;
1655
1656 /* If the user sets an obscenely small MTU, adjust the small
1657 * bytes down to nearly nothing */
1658 if (mgp->small_bytes >= (dev->mtu + ETH_HLEN))
1659 mgp->small_bytes = 64;
1660
1661 /* get the lanai pointers to the send and receive rings */
1662
1663 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1664 mgp->tx.lanai =
1665 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1666
1667 status |=
1668 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1669 mgp->rx_small.lanai =
1670 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1671
1672 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1673 mgp->rx_big.lanai =
1674 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1675
1676 if (status != 0) {
1677 printk(KERN_ERR
1678 "myri10ge: %s: failed to get ring sizes or locations\n",
1679 dev->name);
1680 mgp->running = MYRI10GE_ETH_STOPPED;
1681 return -ENXIO;
1682 }
1683
1684 if (mgp->mtrr >= 0) {
1685 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1686 mgp->rx_small.wc_fifo =
1687 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1688 mgp->rx_big.wc_fifo =
1689 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1690 } else {
1691 mgp->tx.wc_fifo = NULL;
1692 mgp->rx_small.wc_fifo = NULL;
1693 mgp->rx_big.wc_fifo = NULL;
1694 }
1695
1696 status = myri10ge_allocate_rings(dev);
1697 if (status != 0)
1698 goto abort_with_nothing;
1699
1700 /* Firmware needs the big buff size as a power of 2. Lie and
1701 * tell him the buffer is larger, because we only use 1
1702 * buffer/pkt, and the mtu will prevent overruns.
1703 */
1704 big_pow2 = dev->mtu + ETH_HLEN + MXGEFW_PAD;
1705 while ((big_pow2 & (big_pow2 - 1)) != 0)
1706 big_pow2++;
1707
1708 /* now give firmware buffers sizes, and MTU */
1709 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1710 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1711 cmd.data0 = mgp->small_bytes;
1712 status |=
1713 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1714 cmd.data0 = big_pow2;
1715 status |=
1716 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1717 if (status) {
1718 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1719 dev->name);
1720 goto abort_with_rings;
1721 }
1722
1723 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1724 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1725 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA, &cmd, 0);
1726 if (status) {
1727 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1728 dev->name);
1729 goto abort_with_rings;
1730 }
1731
1732 mgp->link_state = -1;
1733 mgp->rdma_tags_available = 15;
1734
1735 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1736
1737 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1738 if (status) {
1739 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1740 dev->name);
1741 goto abort_with_rings;
1742 }
1743
1744 mgp->wake_queue = 0;
1745 mgp->stop_queue = 0;
1746 mgp->running = MYRI10GE_ETH_RUNNING;
1747 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1748 add_timer(&mgp->watchdog_timer);
1749 netif_wake_queue(dev);
1750 return 0;
1751
1752 abort_with_rings:
1753 myri10ge_free_rings(dev);
1754
1755 abort_with_nothing:
1756 mgp->running = MYRI10GE_ETH_STOPPED;
1757 return -ENOMEM;
1758 }
1759
1760 static int myri10ge_close(struct net_device *dev)
1761 {
1762 struct myri10ge_priv *mgp;
1763 struct myri10ge_cmd cmd;
1764 int status, old_down_cnt;
1765
1766 mgp = netdev_priv(dev);
1767
1768 if (mgp->running != MYRI10GE_ETH_RUNNING)
1769 return 0;
1770
1771 if (mgp->tx.req_bytes == NULL)
1772 return 0;
1773
1774 del_timer_sync(&mgp->watchdog_timer);
1775 mgp->running = MYRI10GE_ETH_STOPPING;
1776 netif_poll_disable(mgp->dev);
1777 netif_carrier_off(dev);
1778 netif_stop_queue(dev);
1779 old_down_cnt = mgp->down_cnt;
1780 mb();
1781 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1782 if (status)
1783 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1784 dev->name);
1785
1786 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1787 if (old_down_cnt == mgp->down_cnt)
1788 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1789
1790 netif_tx_disable(dev);
1791
1792 myri10ge_free_rings(dev);
1793
1794 mgp->running = MYRI10GE_ETH_STOPPED;
1795 return 0;
1796 }
1797
1798 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1799 * backwards one at a time and handle ring wraps */
1800
1801 static inline void
1802 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1803 struct mcp_kreq_ether_send *src, int cnt)
1804 {
1805 int idx, starting_slot;
1806 starting_slot = tx->req;
1807 while (cnt > 1) {
1808 cnt--;
1809 idx = (starting_slot + cnt) & tx->mask;
1810 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1811 mb();
1812 }
1813 }
1814
1815 /*
1816 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1817 * at most 32 bytes at a time, so as to avoid involving the software
1818 * pio handler in the nic. We re-write the first segment's flags
1819 * to mark them valid only after writing the entire chain.
1820 */
1821
1822 static inline void
1823 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1824 int cnt)
1825 {
1826 int idx, i;
1827 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1828 struct mcp_kreq_ether_send *srcp;
1829 u8 last_flags;
1830
1831 idx = tx->req & tx->mask;
1832
1833 last_flags = src->flags;
1834 src->flags = 0;
1835 mb();
1836 dst = dstp = &tx->lanai[idx];
1837 srcp = src;
1838
1839 if ((idx + cnt) < tx->mask) {
1840 for (i = 0; i < (cnt - 1); i += 2) {
1841 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1842 mb(); /* force write every 32 bytes */
1843 srcp += 2;
1844 dstp += 2;
1845 }
1846 } else {
1847 /* submit all but the first request, and ensure
1848 * that it is submitted below */
1849 myri10ge_submit_req_backwards(tx, src, cnt);
1850 i = 0;
1851 }
1852 if (i < cnt) {
1853 /* submit the first request */
1854 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1855 mb(); /* barrier before setting valid flag */
1856 }
1857
1858 /* re-write the last 32-bits with the valid flags */
1859 src->flags = last_flags;
1860 __raw_writel(*((u32 *) src + 3), (u32 __iomem *) dst + 3);
1861 tx->req += cnt;
1862 mb();
1863 }
1864
1865 static inline void
1866 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1867 struct mcp_kreq_ether_send *src, int cnt)
1868 {
1869 tx->req += cnt;
1870 mb();
1871 while (cnt >= 4) {
1872 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1873 mb();
1874 src += 4;
1875 cnt -= 4;
1876 }
1877 if (cnt > 0) {
1878 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1879 * needs to be so that we don't overrun it */
1880 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1881 src, 64);
1882 mb();
1883 }
1884 }
1885
1886 /*
1887 * Transmit a packet. We need to split the packet so that a single
1888 * segment does not cross myri10ge->tx.boundary, so this makes segment
1889 * counting tricky. So rather than try to count segments up front, we
1890 * just give up if there are too few segments to hold a reasonably
1891 * fragmented packet currently available. If we run
1892 * out of segments while preparing a packet for DMA, we just linearize
1893 * it and try again.
1894 */
1895
1896 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1897 {
1898 struct myri10ge_priv *mgp = netdev_priv(dev);
1899 struct mcp_kreq_ether_send *req;
1900 struct myri10ge_tx_buf *tx = &mgp->tx;
1901 struct skb_frag_struct *frag;
1902 dma_addr_t bus;
1903 u32 low, high_swapped;
1904 unsigned int len;
1905 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1906 u16 pseudo_hdr_offset, cksum_offset;
1907 int cum_len, seglen, boundary, rdma_count;
1908 u8 flags, odd_flag;
1909
1910 again:
1911 req = tx->req_list;
1912 avail = tx->mask - 1 - (tx->req - tx->done);
1913
1914 mss = 0;
1915 max_segments = MXGEFW_MAX_SEND_DESC;
1916
1917 #ifdef NETIF_F_TSO
1918 if (skb->len > (dev->mtu + ETH_HLEN)) {
1919 mss = skb_shinfo(skb)->gso_size;
1920 if (mss != 0)
1921 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1922 }
1923 #endif /*NETIF_F_TSO */
1924
1925 if ((unlikely(avail < max_segments))) {
1926 /* we are out of transmit resources */
1927 mgp->stop_queue++;
1928 netif_stop_queue(dev);
1929 return 1;
1930 }
1931
1932 /* Setup checksum offloading, if needed */
1933 cksum_offset = 0;
1934 pseudo_hdr_offset = 0;
1935 odd_flag = 0;
1936 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1937 if (likely(skb->ip_summed == CHECKSUM_HW)) {
1938 cksum_offset = (skb->h.raw - skb->data);
1939 pseudo_hdr_offset = (skb->h.raw + skb->csum) - skb->data;
1940 /* If the headers are excessively large, then we must
1941 * fall back to a software checksum */
1942 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
1943 if (skb_checksum_help(skb, 0))
1944 goto drop;
1945 cksum_offset = 0;
1946 pseudo_hdr_offset = 0;
1947 } else {
1948 pseudo_hdr_offset = htons(pseudo_hdr_offset);
1949 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
1950 flags |= MXGEFW_FLAGS_CKSUM;
1951 }
1952 }
1953
1954 cum_len = 0;
1955
1956 #ifdef NETIF_F_TSO
1957 if (mss) { /* TSO */
1958 /* this removes any CKSUM flag from before */
1959 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
1960
1961 /* negative cum_len signifies to the
1962 * send loop that we are still in the
1963 * header portion of the TSO packet.
1964 * TSO header must be at most 134 bytes long */
1965 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
1966
1967 /* for TSO, pseudo_hdr_offset holds mss.
1968 * The firmware figures out where to put
1969 * the checksum by parsing the header. */
1970 pseudo_hdr_offset = htons(mss);
1971 } else
1972 #endif /*NETIF_F_TSO */
1973 /* Mark small packets, and pad out tiny packets */
1974 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
1975 flags |= MXGEFW_FLAGS_SMALL;
1976
1977 /* pad frames to at least ETH_ZLEN bytes */
1978 if (unlikely(skb->len < ETH_ZLEN)) {
1979 if (skb_padto(skb, ETH_ZLEN)) {
1980 /* The packet is gone, so we must
1981 * return 0 */
1982 mgp->stats.tx_dropped += 1;
1983 return 0;
1984 }
1985 /* adjust the len to account for the zero pad
1986 * so that the nic can know how long it is */
1987 skb->len = ETH_ZLEN;
1988 }
1989 }
1990
1991 /* map the skb for DMA */
1992 len = skb->len - skb->data_len;
1993 idx = tx->req & tx->mask;
1994 tx->info[idx].skb = skb;
1995 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
1996 pci_unmap_addr_set(&tx->info[idx], bus, bus);
1997 pci_unmap_len_set(&tx->info[idx], len, len);
1998
1999 frag_cnt = skb_shinfo(skb)->nr_frags;
2000 frag_idx = 0;
2001 count = 0;
2002 rdma_count = 0;
2003
2004 /* "rdma_count" is the number of RDMAs belonging to the
2005 * current packet BEFORE the current send request. For
2006 * non-TSO packets, this is equal to "count".
2007 * For TSO packets, rdma_count needs to be reset
2008 * to 0 after a segment cut.
2009 *
2010 * The rdma_count field of the send request is
2011 * the number of RDMAs of the packet starting at
2012 * that request. For TSO send requests with one ore more cuts
2013 * in the middle, this is the number of RDMAs starting
2014 * after the last cut in the request. All previous
2015 * segments before the last cut implicitly have 1 RDMA.
2016 *
2017 * Since the number of RDMAs is not known beforehand,
2018 * it must be filled-in retroactively - after each
2019 * segmentation cut or at the end of the entire packet.
2020 */
2021
2022 while (1) {
2023 /* Break the SKB or Fragment up into pieces which
2024 * do not cross mgp->tx.boundary */
2025 low = MYRI10GE_LOWPART_TO_U32(bus);
2026 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2027 while (len) {
2028 u8 flags_next;
2029 int cum_len_next;
2030
2031 if (unlikely(count == max_segments))
2032 goto abort_linearize;
2033
2034 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2035 seglen = boundary - low;
2036 if (seglen > len)
2037 seglen = len;
2038 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2039 cum_len_next = cum_len + seglen;
2040 #ifdef NETIF_F_TSO
2041 if (mss) { /* TSO */
2042 (req - rdma_count)->rdma_count = rdma_count + 1;
2043
2044 if (likely(cum_len >= 0)) { /* payload */
2045 int next_is_first, chop;
2046
2047 chop = (cum_len_next > mss);
2048 cum_len_next = cum_len_next % mss;
2049 next_is_first = (cum_len_next == 0);
2050 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2051 flags_next |= next_is_first *
2052 MXGEFW_FLAGS_FIRST;
2053 rdma_count |= -(chop | next_is_first);
2054 rdma_count += chop & !next_is_first;
2055 } else if (likely(cum_len_next >= 0)) { /* header ends */
2056 int small;
2057
2058 rdma_count = -1;
2059 cum_len_next = 0;
2060 seglen = -cum_len;
2061 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2062 flags_next = MXGEFW_FLAGS_TSO_PLD |
2063 MXGEFW_FLAGS_FIRST |
2064 (small * MXGEFW_FLAGS_SMALL);
2065 }
2066 }
2067 #endif /* NETIF_F_TSO */
2068 req->addr_high = high_swapped;
2069 req->addr_low = htonl(low);
2070 req->pseudo_hdr_offset = pseudo_hdr_offset;
2071 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2072 req->rdma_count = 1;
2073 req->length = htons(seglen);
2074 req->cksum_offset = cksum_offset;
2075 req->flags = flags | ((cum_len & 1) * odd_flag);
2076
2077 low += seglen;
2078 len -= seglen;
2079 cum_len = cum_len_next;
2080 flags = flags_next;
2081 req++;
2082 count++;
2083 rdma_count++;
2084 if (unlikely(cksum_offset > seglen))
2085 cksum_offset -= seglen;
2086 else
2087 cksum_offset = 0;
2088 }
2089 if (frag_idx == frag_cnt)
2090 break;
2091
2092 /* map next fragment for DMA */
2093 idx = (count + tx->req) & tx->mask;
2094 frag = &skb_shinfo(skb)->frags[frag_idx];
2095 frag_idx++;
2096 len = frag->size;
2097 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2098 len, PCI_DMA_TODEVICE);
2099 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2100 pci_unmap_len_set(&tx->info[idx], len, len);
2101 }
2102
2103 (req - rdma_count)->rdma_count = rdma_count;
2104 #ifdef NETIF_F_TSO
2105 if (mss)
2106 do {
2107 req--;
2108 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2109 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2110 MXGEFW_FLAGS_FIRST)));
2111 #endif
2112 idx = ((count - 1) + tx->req) & tx->mask;
2113 tx->info[idx].last = 1;
2114 if (tx->wc_fifo == NULL)
2115 myri10ge_submit_req(tx, tx->req_list, count);
2116 else
2117 myri10ge_submit_req_wc(tx, tx->req_list, count);
2118 tx->pkt_start++;
2119 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2120 mgp->stop_queue++;
2121 netif_stop_queue(dev);
2122 }
2123 dev->trans_start = jiffies;
2124 return 0;
2125
2126 abort_linearize:
2127 /* Free any DMA resources we've alloced and clear out the skb
2128 * slot so as to not trip up assertions, and to avoid a
2129 * double-free if linearizing fails */
2130
2131 last_idx = (idx + 1) & tx->mask;
2132 idx = tx->req & tx->mask;
2133 tx->info[idx].skb = NULL;
2134 do {
2135 len = pci_unmap_len(&tx->info[idx], len);
2136 if (len) {
2137 if (tx->info[idx].skb != NULL)
2138 pci_unmap_single(mgp->pdev,
2139 pci_unmap_addr(&tx->info[idx],
2140 bus), len,
2141 PCI_DMA_TODEVICE);
2142 else
2143 pci_unmap_page(mgp->pdev,
2144 pci_unmap_addr(&tx->info[idx],
2145 bus), len,
2146 PCI_DMA_TODEVICE);
2147 pci_unmap_len_set(&tx->info[idx], len, 0);
2148 tx->info[idx].skb = NULL;
2149 }
2150 idx = (idx + 1) & tx->mask;
2151 } while (idx != last_idx);
2152 if (skb_is_gso(skb)) {
2153 printk(KERN_ERR
2154 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2155 mgp->dev->name);
2156 goto drop;
2157 }
2158
2159 if (skb_linearize(skb))
2160 goto drop;
2161
2162 mgp->tx_linearized++;
2163 goto again;
2164
2165 drop:
2166 dev_kfree_skb_any(skb);
2167 mgp->stats.tx_dropped += 1;
2168 return 0;
2169
2170 }
2171
2172 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2173 {
2174 struct myri10ge_priv *mgp = netdev_priv(dev);
2175 return &mgp->stats;
2176 }
2177
2178 static void myri10ge_set_multicast_list(struct net_device *dev)
2179 {
2180 /* can be called from atomic contexts,
2181 * pass 1 to force atomicity in myri10ge_send_cmd() */
2182 myri10ge_change_promisc(netdev_priv(dev), dev->flags & IFF_PROMISC, 1);
2183 }
2184
2185 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2186 {
2187 struct sockaddr *sa = addr;
2188 struct myri10ge_priv *mgp = netdev_priv(dev);
2189 int status;
2190
2191 if (!is_valid_ether_addr(sa->sa_data))
2192 return -EADDRNOTAVAIL;
2193
2194 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2195 if (status != 0) {
2196 printk(KERN_ERR
2197 "myri10ge: %s: changing mac address failed with %d\n",
2198 dev->name, status);
2199 return status;
2200 }
2201
2202 /* change the dev structure */
2203 memcpy(dev->dev_addr, sa->sa_data, 6);
2204 return 0;
2205 }
2206
2207 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2208 {
2209 struct myri10ge_priv *mgp = netdev_priv(dev);
2210 int error = 0;
2211
2212 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2213 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2214 dev->name, new_mtu);
2215 return -EINVAL;
2216 }
2217 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2218 dev->name, dev->mtu, new_mtu);
2219 if (mgp->running) {
2220 /* if we change the mtu on an active device, we must
2221 * reset the device so the firmware sees the change */
2222 myri10ge_close(dev);
2223 dev->mtu = new_mtu;
2224 myri10ge_open(dev);
2225 } else
2226 dev->mtu = new_mtu;
2227
2228 return error;
2229 }
2230
2231 /*
2232 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2233 * Only do it if the bridge is a root port since we don't want to disturb
2234 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2235 */
2236
2237 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2238 {
2239 struct pci_dev *bridge = mgp->pdev->bus->self;
2240 struct device *dev = &mgp->pdev->dev;
2241 unsigned cap;
2242 unsigned err_cap;
2243 u16 val;
2244 u8 ext_type;
2245 int ret;
2246
2247 if (!myri10ge_ecrc_enable || !bridge)
2248 return;
2249
2250 /* check that the bridge is a root port */
2251 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2252 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2253 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2254 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2255 if (myri10ge_ecrc_enable > 1) {
2256 struct pci_dev *old_bridge = bridge;
2257
2258 /* Walk the hierarchy up to the root port
2259 * where ECRC has to be enabled */
2260 do {
2261 bridge = bridge->bus->self;
2262 if (!bridge) {
2263 dev_err(dev,
2264 "Failed to find root port"
2265 " to force ECRC\n");
2266 return;
2267 }
2268 cap =
2269 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2270 pci_read_config_word(bridge,
2271 cap + PCI_CAP_FLAGS, &val);
2272 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2273 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2274
2275 dev_info(dev,
2276 "Forcing ECRC on non-root port %s"
2277 " (enabling on root port %s)\n",
2278 pci_name(old_bridge), pci_name(bridge));
2279 } else {
2280 dev_err(dev,
2281 "Not enabling ECRC on non-root port %s\n",
2282 pci_name(bridge));
2283 return;
2284 }
2285 }
2286
2287 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2288 if (!cap)
2289 return;
2290
2291 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2292 if (ret) {
2293 dev_err(dev, "failed reading ext-conf-space of %s\n",
2294 pci_name(bridge));
2295 dev_err(dev, "\t pci=nommconf in use? "
2296 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2297 return;
2298 }
2299 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2300 return;
2301
2302 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2303 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2304 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2305 mgp->tx.boundary = 4096;
2306 mgp->fw_name = myri10ge_fw_aligned;
2307 }
2308
2309 /*
2310 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2311 * when the PCI-E Completion packets are aligned on an 8-byte
2312 * boundary. Some PCI-E chip sets always align Completion packets; on
2313 * the ones that do not, the alignment can be enforced by enabling
2314 * ECRC generation (if supported).
2315 *
2316 * When PCI-E Completion packets are not aligned, it is actually more
2317 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2318 *
2319 * If the driver can neither enable ECRC nor verify that it has
2320 * already been enabled, then it must use a firmware image which works
2321 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2322 * should also ensure that it never gives the device a Read-DMA which is
2323 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2324 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2325 * firmware image, and set tx.boundary to 4KB.
2326 */
2327
2328 #define PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE 0x0132
2329
2330 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2331 {
2332 struct pci_dev *bridge = mgp->pdev->bus->self;
2333
2334 mgp->tx.boundary = 2048;
2335 mgp->fw_name = myri10ge_fw_unaligned;
2336
2337 if (myri10ge_force_firmware == 0) {
2338 myri10ge_enable_ecrc(mgp);
2339
2340 /* Check to see if the upstream bridge is known to
2341 * provide aligned completions */
2342 if (bridge
2343 /* ServerWorks HT2000/HT1000 */
2344 && bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2345 && bridge->device ==
2346 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE) {
2347 dev_info(&mgp->pdev->dev,
2348 "Assuming aligned completions (0x%x:0x%x)\n",
2349 bridge->vendor, bridge->device);
2350 mgp->tx.boundary = 4096;
2351 mgp->fw_name = myri10ge_fw_aligned;
2352 }
2353 } else {
2354 if (myri10ge_force_firmware == 1) {
2355 dev_info(&mgp->pdev->dev,
2356 "Assuming aligned completions (forced)\n");
2357 mgp->tx.boundary = 4096;
2358 mgp->fw_name = myri10ge_fw_aligned;
2359 } else {
2360 dev_info(&mgp->pdev->dev,
2361 "Assuming unaligned completions (forced)\n");
2362 mgp->tx.boundary = 2048;
2363 mgp->fw_name = myri10ge_fw_unaligned;
2364 }
2365 }
2366 if (myri10ge_fw_name != NULL) {
2367 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2368 myri10ge_fw_name);
2369 mgp->fw_name = myri10ge_fw_name;
2370 }
2371 }
2372
2373 static void myri10ge_save_state(struct myri10ge_priv *mgp)
2374 {
2375 struct pci_dev *pdev = mgp->pdev;
2376 int cap;
2377
2378 pci_save_state(pdev);
2379 /* now save PCIe and MSI state that Linux will not
2380 * save for us */
2381 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2382 pci_read_config_dword(pdev, cap + PCI_EXP_DEVCTL, &mgp->devctl);
2383 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2384 pci_read_config_word(pdev, cap + PCI_MSI_FLAGS, &mgp->msi_flags);
2385 }
2386
2387 static void myri10ge_restore_state(struct myri10ge_priv *mgp)
2388 {
2389 struct pci_dev *pdev = mgp->pdev;
2390 int cap;
2391
2392 /* restore PCIe and MSI state that linux will not */
2393 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2394 pci_write_config_dword(pdev, cap + PCI_CAP_ID_EXP, mgp->devctl);
2395 cap = pci_find_capability(pdev, PCI_CAP_ID_MSI);
2396 pci_write_config_word(pdev, cap + PCI_MSI_FLAGS, mgp->msi_flags);
2397
2398 pci_restore_state(pdev);
2399 }
2400
2401 #ifdef CONFIG_PM
2402
2403 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2404 {
2405 struct myri10ge_priv *mgp;
2406 struct net_device *netdev;
2407
2408 mgp = pci_get_drvdata(pdev);
2409 if (mgp == NULL)
2410 return -EINVAL;
2411 netdev = mgp->dev;
2412
2413 netif_device_detach(netdev);
2414 if (netif_running(netdev)) {
2415 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2416 rtnl_lock();
2417 myri10ge_close(netdev);
2418 rtnl_unlock();
2419 }
2420 myri10ge_dummy_rdma(mgp, 0);
2421 free_irq(pdev->irq, mgp);
2422 myri10ge_save_state(mgp);
2423 pci_disable_device(pdev);
2424 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2425 return 0;
2426 }
2427
2428 static int myri10ge_resume(struct pci_dev *pdev)
2429 {
2430 struct myri10ge_priv *mgp;
2431 struct net_device *netdev;
2432 int status;
2433 u16 vendor;
2434
2435 mgp = pci_get_drvdata(pdev);
2436 if (mgp == NULL)
2437 return -EINVAL;
2438 netdev = mgp->dev;
2439 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2440 msleep(5); /* give card time to respond */
2441 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2442 if (vendor == 0xffff) {
2443 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2444 mgp->dev->name);
2445 return -EIO;
2446 }
2447 myri10ge_restore_state(mgp);
2448
2449 status = pci_enable_device(pdev);
2450 if (status < 0) {
2451 dev_err(&pdev->dev, "failed to enable device\n");
2452 return -EIO;
2453 }
2454
2455 pci_set_master(pdev);
2456
2457 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2458 netdev->name, mgp);
2459 if (status != 0) {
2460 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2461 goto abort_with_enabled;
2462 }
2463
2464 myri10ge_reset(mgp);
2465 myri10ge_dummy_rdma(mgp, 1);
2466
2467 /* Save configuration space to be restored if the
2468 * nic resets due to a parity error */
2469 myri10ge_save_state(mgp);
2470
2471 if (netif_running(netdev)) {
2472 rtnl_lock();
2473 myri10ge_open(netdev);
2474 rtnl_unlock();
2475 }
2476 netif_device_attach(netdev);
2477
2478 return 0;
2479
2480 abort_with_enabled:
2481 pci_disable_device(pdev);
2482 return -EIO;
2483
2484 }
2485
2486 #endif /* CONFIG_PM */
2487
2488 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2489 {
2490 struct pci_dev *pdev = mgp->pdev;
2491 int vs = mgp->vendor_specific_offset;
2492 u32 reboot;
2493
2494 /*enter read32 mode */
2495 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2496
2497 /*read REBOOT_STATUS (0xfffffff0) */
2498 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2499 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2500 return reboot;
2501 }
2502
2503 /*
2504 * This watchdog is used to check whether the board has suffered
2505 * from a parity error and needs to be recovered.
2506 */
2507 static void myri10ge_watchdog(void *arg)
2508 {
2509 struct myri10ge_priv *mgp = arg;
2510 u32 reboot;
2511 int status;
2512 u16 cmd, vendor;
2513
2514 mgp->watchdog_resets++;
2515 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2516 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2517 /* Bus master DMA disabled? Check to see
2518 * if the card rebooted due to a parity error
2519 * For now, just report it */
2520 reboot = myri10ge_read_reboot(mgp);
2521 printk(KERN_ERR
2522 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2523 mgp->dev->name, reboot);
2524 /*
2525 * A rebooted nic will come back with config space as
2526 * it was after power was applied to PCIe bus.
2527 * Attempt to restore config space which was saved
2528 * when the driver was loaded, or the last time the
2529 * nic was resumed from power saving mode.
2530 */
2531 myri10ge_restore_state(mgp);
2532 } else {
2533 /* if we get back -1's from our slot, perhaps somebody
2534 * powered off our card. Don't try to reset it in
2535 * this case */
2536 if (cmd == 0xffff) {
2537 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2538 if (vendor == 0xffff) {
2539 printk(KERN_ERR
2540 "myri10ge: %s: device disappeared!\n",
2541 mgp->dev->name);
2542 return;
2543 }
2544 }
2545 /* Perhaps it is a software error. Try to reset */
2546
2547 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2548 mgp->dev->name);
2549 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2550 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2551 mgp->tx.pkt_start, mgp->tx.pkt_done,
2552 (int)ntohl(mgp->fw_stats->send_done_count));
2553 msleep(2000);
2554 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2555 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2556 mgp->tx.pkt_start, mgp->tx.pkt_done,
2557 (int)ntohl(mgp->fw_stats->send_done_count));
2558 }
2559 rtnl_lock();
2560 myri10ge_close(mgp->dev);
2561 status = myri10ge_load_firmware(mgp);
2562 if (status != 0)
2563 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2564 mgp->dev->name);
2565 else
2566 myri10ge_open(mgp->dev);
2567 rtnl_unlock();
2568 }
2569
2570 /*
2571 * We use our own timer routine rather than relying upon
2572 * netdev->tx_timeout because we have a very large hardware transmit
2573 * queue. Due to the large queue, the netdev->tx_timeout function
2574 * cannot detect a NIC with a parity error in a timely fashion if the
2575 * NIC is lightly loaded.
2576 */
2577 static void myri10ge_watchdog_timer(unsigned long arg)
2578 {
2579 struct myri10ge_priv *mgp;
2580
2581 mgp = (struct myri10ge_priv *)arg;
2582 if (mgp->tx.req != mgp->tx.done &&
2583 mgp->tx.done == mgp->watchdog_tx_done &&
2584 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2585 /* nic seems like it might be stuck.. */
2586 schedule_work(&mgp->watchdog_work);
2587 else
2588 /* rearm timer */
2589 mod_timer(&mgp->watchdog_timer,
2590 jiffies + myri10ge_watchdog_timeout * HZ);
2591
2592 mgp->watchdog_tx_done = mgp->tx.done;
2593 mgp->watchdog_tx_req = mgp->tx.req;
2594 }
2595
2596 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2597 {
2598 struct net_device *netdev;
2599 struct myri10ge_priv *mgp;
2600 struct device *dev = &pdev->dev;
2601 size_t bytes;
2602 int i;
2603 int status = -ENXIO;
2604 int cap;
2605 int dac_enabled;
2606 u16 val;
2607
2608 netdev = alloc_etherdev(sizeof(*mgp));
2609 if (netdev == NULL) {
2610 dev_err(dev, "Could not allocate ethernet device\n");
2611 return -ENOMEM;
2612 }
2613
2614 mgp = netdev_priv(netdev);
2615 memset(mgp, 0, sizeof(*mgp));
2616 mgp->dev = netdev;
2617 mgp->pdev = pdev;
2618 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2619 mgp->pause = myri10ge_flow_control;
2620 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2621 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2622 init_waitqueue_head(&mgp->down_wq);
2623
2624 if (pci_enable_device(pdev)) {
2625 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2626 status = -ENODEV;
2627 goto abort_with_netdev;
2628 }
2629 myri10ge_select_firmware(mgp);
2630
2631 /* Find the vendor-specific cap so we can check
2632 * the reboot register later on */
2633 mgp->vendor_specific_offset
2634 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2635
2636 /* Set our max read request to 4KB */
2637 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2638 if (cap < 64) {
2639 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2640 goto abort_with_netdev;
2641 }
2642 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2643 if (status != 0) {
2644 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2645 status);
2646 goto abort_with_netdev;
2647 }
2648 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2649 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2650 if (status != 0) {
2651 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2652 status);
2653 goto abort_with_netdev;
2654 }
2655
2656 pci_set_master(pdev);
2657 dac_enabled = 1;
2658 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2659 if (status != 0) {
2660 dac_enabled = 0;
2661 dev_err(&pdev->dev,
2662 "64-bit pci address mask was refused, trying 32-bit");
2663 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2664 }
2665 if (status != 0) {
2666 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2667 goto abort_with_netdev;
2668 }
2669 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2670 &mgp->cmd_bus, GFP_KERNEL);
2671 if (mgp->cmd == NULL)
2672 goto abort_with_netdev;
2673
2674 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2675 &mgp->fw_stats_bus, GFP_KERNEL);
2676 if (mgp->fw_stats == NULL)
2677 goto abort_with_cmd;
2678
2679 mgp->board_span = pci_resource_len(pdev, 0);
2680 mgp->iomem_base = pci_resource_start(pdev, 0);
2681 mgp->mtrr = -1;
2682 #ifdef CONFIG_MTRR
2683 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2684 MTRR_TYPE_WRCOMB, 1);
2685 #endif
2686 /* Hack. need to get rid of these magic numbers */
2687 mgp->sram_size =
2688 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2689 if (mgp->sram_size > mgp->board_span) {
2690 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2691 mgp->board_span);
2692 goto abort_with_wc;
2693 }
2694 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2695 if (mgp->sram == NULL) {
2696 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2697 mgp->board_span, mgp->iomem_base);
2698 status = -ENXIO;
2699 goto abort_with_wc;
2700 }
2701 memcpy_fromio(mgp->eeprom_strings,
2702 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2703 MYRI10GE_EEPROM_STRINGS_SIZE);
2704 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2705 status = myri10ge_read_mac_addr(mgp);
2706 if (status)
2707 goto abort_with_ioremap;
2708
2709 for (i = 0; i < ETH_ALEN; i++)
2710 netdev->dev_addr[i] = mgp->mac_addr[i];
2711
2712 /* allocate rx done ring */
2713 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2714 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2715 &mgp->rx_done.bus, GFP_KERNEL);
2716 if (mgp->rx_done.entry == NULL)
2717 goto abort_with_ioremap;
2718 memset(mgp->rx_done.entry, 0, bytes);
2719
2720 status = myri10ge_load_firmware(mgp);
2721 if (status != 0) {
2722 dev_err(&pdev->dev, "failed to load firmware\n");
2723 goto abort_with_rx_done;
2724 }
2725
2726 status = myri10ge_reset(mgp);
2727 if (status != 0) {
2728 dev_err(&pdev->dev, "failed reset\n");
2729 goto abort_with_firmware;
2730 }
2731
2732 if (myri10ge_msi) {
2733 status = pci_enable_msi(pdev);
2734 if (status != 0)
2735 dev_err(&pdev->dev,
2736 "Error %d setting up MSI; falling back to xPIC\n",
2737 status);
2738 else
2739 mgp->msi_enabled = 1;
2740 }
2741
2742 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
2743 netdev->name, mgp);
2744 if (status != 0) {
2745 dev_err(&pdev->dev, "failed to allocate IRQ\n");
2746 goto abort_with_firmware;
2747 }
2748
2749 pci_set_drvdata(pdev, mgp);
2750 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2751 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2752 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2753 myri10ge_initial_mtu = 68;
2754 netdev->mtu = myri10ge_initial_mtu;
2755 netdev->open = myri10ge_open;
2756 netdev->stop = myri10ge_close;
2757 netdev->hard_start_xmit = myri10ge_xmit;
2758 netdev->get_stats = myri10ge_get_stats;
2759 netdev->base_addr = mgp->iomem_base;
2760 netdev->irq = pdev->irq;
2761 netdev->change_mtu = myri10ge_change_mtu;
2762 netdev->set_multicast_list = myri10ge_set_multicast_list;
2763 netdev->set_mac_address = myri10ge_set_mac_address;
2764 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2765 if (dac_enabled)
2766 netdev->features |= NETIF_F_HIGHDMA;
2767 netdev->poll = myri10ge_poll;
2768 netdev->weight = myri10ge_napi_weight;
2769
2770 /* Save configuration space to be restored if the
2771 * nic resets due to a parity error */
2772 myri10ge_save_state(mgp);
2773
2774 /* Setup the watchdog timer */
2775 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2776 (unsigned long)mgp);
2777
2778 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2779 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog, mgp);
2780 status = register_netdev(netdev);
2781 if (status != 0) {
2782 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2783 goto abort_with_irq;
2784 }
2785 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2786 (mgp->msi_enabled ? "MSI" : "xPIC"),
2787 pdev->irq, mgp->tx.boundary, mgp->fw_name,
2788 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2789
2790 return 0;
2791
2792 abort_with_irq:
2793 free_irq(pdev->irq, mgp);
2794 if (mgp->msi_enabled)
2795 pci_disable_msi(pdev);
2796
2797 abort_with_firmware:
2798 myri10ge_dummy_rdma(mgp, 0);
2799
2800 abort_with_rx_done:
2801 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2802 dma_free_coherent(&pdev->dev, bytes,
2803 mgp->rx_done.entry, mgp->rx_done.bus);
2804
2805 abort_with_ioremap:
2806 iounmap(mgp->sram);
2807
2808 abort_with_wc:
2809 #ifdef CONFIG_MTRR
2810 if (mgp->mtrr >= 0)
2811 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2812 #endif
2813 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2814 mgp->fw_stats, mgp->fw_stats_bus);
2815
2816 abort_with_cmd:
2817 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2818 mgp->cmd, mgp->cmd_bus);
2819
2820 abort_with_netdev:
2821
2822 free_netdev(netdev);
2823 return status;
2824 }
2825
2826 /*
2827 * myri10ge_remove
2828 *
2829 * Does what is necessary to shutdown one Myrinet device. Called
2830 * once for each Myrinet card by the kernel when a module is
2831 * unloaded.
2832 */
2833 static void myri10ge_remove(struct pci_dev *pdev)
2834 {
2835 struct myri10ge_priv *mgp;
2836 struct net_device *netdev;
2837 size_t bytes;
2838
2839 mgp = pci_get_drvdata(pdev);
2840 if (mgp == NULL)
2841 return;
2842
2843 flush_scheduled_work();
2844 netdev = mgp->dev;
2845 unregister_netdev(netdev);
2846 free_irq(pdev->irq, mgp);
2847 if (mgp->msi_enabled)
2848 pci_disable_msi(pdev);
2849
2850 myri10ge_dummy_rdma(mgp, 0);
2851
2852 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2853 dma_free_coherent(&pdev->dev, bytes,
2854 mgp->rx_done.entry, mgp->rx_done.bus);
2855
2856 iounmap(mgp->sram);
2857
2858 #ifdef CONFIG_MTRR
2859 if (mgp->mtrr >= 0)
2860 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2861 #endif
2862 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2863 mgp->fw_stats, mgp->fw_stats_bus);
2864
2865 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2866 mgp->cmd, mgp->cmd_bus);
2867
2868 free_netdev(netdev);
2869 pci_set_drvdata(pdev, NULL);
2870 }
2871
2872 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
2873
2874 static struct pci_device_id myri10ge_pci_tbl[] = {
2875 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
2876 {0},
2877 };
2878
2879 static struct pci_driver myri10ge_driver = {
2880 .name = "myri10ge",
2881 .probe = myri10ge_probe,
2882 .remove = myri10ge_remove,
2883 .id_table = myri10ge_pci_tbl,
2884 #ifdef CONFIG_PM
2885 .suspend = myri10ge_suspend,
2886 .resume = myri10ge_resume,
2887 #endif
2888 };
2889
2890 static __init int myri10ge_init_module(void)
2891 {
2892 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
2893 MYRI10GE_VERSION_STR);
2894 return pci_register_driver(&myri10ge_driver);
2895 }
2896
2897 module_init(myri10ge_init_module);
2898
2899 static __exit void myri10ge_cleanup_module(void)
2900 {
2901 pci_unregister_driver(&myri10ge_driver);
2902 }
2903
2904 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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