projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge master.kernel.org:/pub/scm/linux/kernel/git/jejb/scsi-rc-fixes-2.6
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.3.0-1.226"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 #define MYRI10GE_ALLOC_ORDER 0
96 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
99 struct myri10ge_rx_buffer_state {
100 struct page *page;
101 int page_offset;
102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104 };
105
106 struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111 };
112
113 struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117 };
118
119 struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
127 int cnt;
128 int fill_cnt;
129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
131 int watchdog_needed;
132 };
133
134 struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146 };
147
148 struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153 };
154
155 struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
163 int big_bytes;
164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
179 __be32 link_state;
180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
182 __be32 __iomem *intr_coal_delay_ptr;
183 int mtrr;
184 int wc_enabled;
185 int wake_queue;
186 int stop_queue;
187 int down_cnt;
188 wait_queue_head_t down_wq;
189 struct work_struct watchdog_work;
190 struct timer_list watchdog_timer;
191 int watchdog_tx_done;
192 int watchdog_tx_req;
193 int watchdog_resets;
194 int tx_linearized;
195 int pause;
196 char *fw_name;
197 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
198 char fw_version[128];
199 int fw_ver_major;
200 int fw_ver_minor;
201 int fw_ver_tiny;
202 int adopted_rx_filter_bug;
203 u8 mac_addr[6]; /* eeprom mac address */
204 unsigned long serial_number;
205 int vendor_specific_offset;
206 int fw_multicast_support;
207 u32 read_dma;
208 u32 write_dma;
209 u32 read_write_dma;
210 u32 link_changes;
211 u32 msg_enable;
212 };
213
214 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
215 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
216
217 static char *myri10ge_fw_name = NULL;
218 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
219 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
220
221 static int myri10ge_ecrc_enable = 1;
222 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
223 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
224
225 static int myri10ge_max_intr_slots = 1024;
226 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
227 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
228
229 static int myri10ge_small_bytes = -1; /* -1 == auto */
230 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
231 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
232
233 static int myri10ge_msi = 1; /* enable msi by default */
234 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
235 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
236
237 static int myri10ge_intr_coal_delay = 75;
238 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
239 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
240
241 static int myri10ge_flow_control = 1;
242 module_param(myri10ge_flow_control, int, S_IRUGO);
243 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
244
245 static int myri10ge_deassert_wait = 1;
246 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
247 MODULE_PARM_DESC(myri10ge_deassert_wait,
248 "Wait when deasserting legacy interrupts\n");
249
250 static int myri10ge_force_firmware = 0;
251 module_param(myri10ge_force_firmware, int, S_IRUGO);
252 MODULE_PARM_DESC(myri10ge_force_firmware,
253 "Force firmware to assume aligned completions\n");
254
255 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
256 module_param(myri10ge_initial_mtu, int, S_IRUGO);
257 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
258
259 static int myri10ge_napi_weight = 64;
260 module_param(myri10ge_napi_weight, int, S_IRUGO);
261 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
262
263 static int myri10ge_watchdog_timeout = 1;
264 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
265 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
266
267 static int myri10ge_max_irq_loops = 1048576;
268 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
269 MODULE_PARM_DESC(myri10ge_max_irq_loops,
270 "Set stuck legacy IRQ detection threshold\n");
271
272 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
273
274 static int myri10ge_debug = -1; /* defaults above */
275 module_param(myri10ge_debug, int, 0);
276 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
277
278 static int myri10ge_fill_thresh = 256;
279 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
280 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
281
282 static int myri10ge_wcfifo = 0;
283 module_param(myri10ge_wcfifo, int, S_IRUGO);
284 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
285
286 #define MYRI10GE_FW_OFFSET 1024*1024
287 #define MYRI10GE_HIGHPART_TO_U32(X) \
288 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
289 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
290
291 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
292
293 static inline void put_be32(__be32 val, __be32 __iomem * p)
294 {
295 __raw_writel((__force __u32) val, (__force void __iomem *)p);
296 }
297
298 static int
299 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
300 struct myri10ge_cmd *data, int atomic)
301 {
302 struct mcp_cmd *buf;
303 char buf_bytes[sizeof(*buf) + 8];
304 struct mcp_cmd_response *response = mgp->cmd;
305 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
306 u32 dma_low, dma_high, result, value;
307 int sleep_total = 0;
308
309 /* ensure buf is aligned to 8 bytes */
310 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
311
312 buf->data0 = htonl(data->data0);
313 buf->data1 = htonl(data->data1);
314 buf->data2 = htonl(data->data2);
315 buf->cmd = htonl(cmd);
316 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
317 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
318
319 buf->response_addr.low = htonl(dma_low);
320 buf->response_addr.high = htonl(dma_high);
321 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
322 mb();
323 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
324
325 /* wait up to 15ms. Longest command is the DMA benchmark,
326 * which is capped at 5ms, but runs from a timeout handler
327 * that runs every 7.8ms. So a 15ms timeout leaves us with
328 * a 2.2ms margin
329 */
330 if (atomic) {
331 /* if atomic is set, do not sleep,
332 * and try to get the completion quickly
333 * (1ms will be enough for those commands) */
334 for (sleep_total = 0;
335 sleep_total < 1000
336 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
337 sleep_total += 10)
338 udelay(10);
339 } else {
340 /* use msleep for most command */
341 for (sleep_total = 0;
342 sleep_total < 15
343 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
344 sleep_total++)
345 msleep(1);
346 }
347
348 result = ntohl(response->result);
349 value = ntohl(response->data);
350 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
351 if (result == 0) {
352 data->data0 = value;
353 return 0;
354 } else if (result == MXGEFW_CMD_UNKNOWN) {
355 return -ENOSYS;
356 } else {
357 dev_err(&mgp->pdev->dev,
358 "command %d failed, result = %d\n",
359 cmd, result);
360 return -ENXIO;
361 }
362 }
363
364 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
365 cmd, result);
366 return -EAGAIN;
367 }
368
369 /*
370 * The eeprom strings on the lanaiX have the format
371 * SN=x\0
372 * MAC=x:x:x:x:x:x\0
373 * PT:ddd mmm xx xx:xx:xx xx\0
374 * PV:ddd mmm xx xx:xx:xx xx\0
375 */
376 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
377 {
378 char *ptr, *limit;
379 int i;
380
381 ptr = mgp->eeprom_strings;
382 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
383
384 while (*ptr != '\0' && ptr < limit) {
385 if (memcmp(ptr, "MAC=", 4) == 0) {
386 ptr += 4;
387 mgp->mac_addr_string = ptr;
388 for (i = 0; i < 6; i++) {
389 if ((ptr + 2) > limit)
390 goto abort;
391 mgp->mac_addr[i] =
392 simple_strtoul(ptr, &ptr, 16);
393 ptr += 1;
394 }
395 }
396 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
397 ptr += 3;
398 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
399 }
400 while (ptr < limit && *ptr++) ;
401 }
402
403 return 0;
404
405 abort:
406 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
407 return -ENXIO;
408 }
409
410 /*
411 * Enable or disable periodic RDMAs from the host to make certain
412 * chipsets resend dropped PCIe messages
413 */
414
415 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
416 {
417 char __iomem *submit;
418 __be32 buf[16];
419 u32 dma_low, dma_high;
420 int i;
421
422 /* clear confirmation addr */
423 mgp->cmd->data = 0;
424 mb();
425
426 /* send a rdma command to the PCIe engine, and wait for the
427 * response in the confirmation address. The firmware should
428 * write a -1 there to indicate it is alive and well
429 */
430 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
431 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
432
433 buf[0] = htonl(dma_high); /* confirm addr MSW */
434 buf[1] = htonl(dma_low); /* confirm addr LSW */
435 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
436 buf[3] = htonl(dma_high); /* dummy addr MSW */
437 buf[4] = htonl(dma_low); /* dummy addr LSW */
438 buf[5] = htonl(enable); /* enable? */
439
440 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
441
442 myri10ge_pio_copy(submit, &buf, sizeof(buf));
443 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
444 msleep(1);
445 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
446 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
447 (enable ? "enable" : "disable"));
448 }
449
450 static int
451 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
452 struct mcp_gen_header *hdr)
453 {
454 struct device *dev = &mgp->pdev->dev;
455
456 /* check firmware type */
457 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
458 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
459 return -EINVAL;
460 }
461
462 /* save firmware version for ethtool */
463 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
464
465 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
466 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
467
468 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
469 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
470 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
471 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
472 MXGEFW_VERSION_MINOR);
473 return -EINVAL;
474 }
475 return 0;
476 }
477
478 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
479 {
480 unsigned crc, reread_crc;
481 const struct firmware *fw;
482 struct device *dev = &mgp->pdev->dev;
483 struct mcp_gen_header *hdr;
484 size_t hdr_offset;
485 int status;
486 unsigned i;
487
488 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
489 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
490 mgp->fw_name);
491 status = -EINVAL;
492 goto abort_with_nothing;
493 }
494
495 /* check size */
496
497 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
498 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
499 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
500 status = -EINVAL;
501 goto abort_with_fw;
502 }
503
504 /* check id */
505 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
506 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
507 dev_err(dev, "Bad firmware file\n");
508 status = -EINVAL;
509 goto abort_with_fw;
510 }
511 hdr = (void *)(fw->data + hdr_offset);
512
513 status = myri10ge_validate_firmware(mgp, hdr);
514 if (status != 0)
515 goto abort_with_fw;
516
517 crc = crc32(~0, fw->data, fw->size);
518 for (i = 0; i < fw->size; i += 256) {
519 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
520 fw->data + i,
521 min(256U, (unsigned)(fw->size - i)));
522 mb();
523 readb(mgp->sram);
524 }
525 /* corruption checking is good for parity recovery and buggy chipset */
526 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
527 reread_crc = crc32(~0, fw->data, fw->size);
528 if (crc != reread_crc) {
529 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
530 (unsigned)fw->size, reread_crc, crc);
531 status = -EIO;
532 goto abort_with_fw;
533 }
534 *size = (u32) fw->size;
535
536 abort_with_fw:
537 release_firmware(fw);
538
539 abort_with_nothing:
540 return status;
541 }
542
543 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
544 {
545 struct mcp_gen_header *hdr;
546 struct device *dev = &mgp->pdev->dev;
547 const size_t bytes = sizeof(struct mcp_gen_header);
548 size_t hdr_offset;
549 int status;
550
551 /* find running firmware header */
552 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
553
554 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
555 dev_err(dev, "Running firmware has bad header offset (%d)\n",
556 (int)hdr_offset);
557 return -EIO;
558 }
559
560 /* copy header of running firmware from SRAM to host memory to
561 * validate firmware */
562 hdr = kmalloc(bytes, GFP_KERNEL);
563 if (hdr == NULL) {
564 dev_err(dev, "could not malloc firmware hdr\n");
565 return -ENOMEM;
566 }
567 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
568 status = myri10ge_validate_firmware(mgp, hdr);
569 kfree(hdr);
570
571 /* check to see if adopted firmware has bug where adopting
572 * it will cause broadcasts to be filtered unless the NIC
573 * is kept in ALLMULTI mode */
574 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
575 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
576 mgp->adopted_rx_filter_bug = 1;
577 dev_warn(dev, "Adopting fw %d.%d.%d: "
578 "working around rx filter bug\n",
579 mgp->fw_ver_major, mgp->fw_ver_minor,
580 mgp->fw_ver_tiny);
581 }
582 return status;
583 }
584
585 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
586 {
587 char __iomem *submit;
588 __be32 buf[16];
589 u32 dma_low, dma_high, size;
590 int status, i;
591
592 size = 0;
593 status = myri10ge_load_hotplug_firmware(mgp, &size);
594 if (status) {
595 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
596
597 /* Do not attempt to adopt firmware if there
598 * was a bad crc */
599 if (status == -EIO)
600 return status;
601
602 status = myri10ge_adopt_running_firmware(mgp);
603 if (status != 0) {
604 dev_err(&mgp->pdev->dev,
605 "failed to adopt running firmware\n");
606 return status;
607 }
608 dev_info(&mgp->pdev->dev,
609 "Successfully adopted running firmware\n");
610 if (mgp->tx.boundary == 4096) {
611 dev_warn(&mgp->pdev->dev,
612 "Using firmware currently running on NIC"
613 ". For optimal\n");
614 dev_warn(&mgp->pdev->dev,
615 "performance consider loading optimized "
616 "firmware\n");
617 dev_warn(&mgp->pdev->dev, "via hotplug\n");
618 }
619
620 mgp->fw_name = "adopted";
621 mgp->tx.boundary = 2048;
622 return status;
623 }
624
625 /* clear confirmation addr */
626 mgp->cmd->data = 0;
627 mb();
628
629 /* send a reload command to the bootstrap MCP, and wait for the
630 * response in the confirmation address. The firmware should
631 * write a -1 there to indicate it is alive and well
632 */
633 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
634 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
635
636 buf[0] = htonl(dma_high); /* confirm addr MSW */
637 buf[1] = htonl(dma_low); /* confirm addr LSW */
638 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
639
640 /* FIX: All newest firmware should un-protect the bottom of
641 * the sram before handoff. However, the very first interfaces
642 * do not. Therefore the handoff copy must skip the first 8 bytes
643 */
644 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
645 buf[4] = htonl(size - 8); /* length of code */
646 buf[5] = htonl(8); /* where to copy to */
647 buf[6] = htonl(0); /* where to jump to */
648
649 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
650
651 myri10ge_pio_copy(submit, &buf, sizeof(buf));
652 mb();
653 msleep(1);
654 mb();
655 i = 0;
656 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
657 msleep(1);
658 i++;
659 }
660 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
661 dev_err(&mgp->pdev->dev, "handoff failed\n");
662 return -ENXIO;
663 }
664 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
665 myri10ge_dummy_rdma(mgp, 1);
666
667 return 0;
668 }
669
670 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
671 {
672 struct myri10ge_cmd cmd;
673 int status;
674
675 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
676 | (addr[2] << 8) | addr[3]);
677
678 cmd.data1 = ((addr[4] << 8) | (addr[5]));
679
680 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
681 return status;
682 }
683
684 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
685 {
686 struct myri10ge_cmd cmd;
687 int status, ctl;
688
689 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
690 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
691
692 if (status) {
693 printk(KERN_ERR
694 "myri10ge: %s: Failed to set flow control mode\n",
695 mgp->dev->name);
696 return status;
697 }
698 mgp->pause = pause;
699 return 0;
700 }
701
702 static void
703 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
704 {
705 struct myri10ge_cmd cmd;
706 int status, ctl;
707
708 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
709 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
710 if (status)
711 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
712 mgp->dev->name);
713 }
714
715 static int myri10ge_reset(struct myri10ge_priv *mgp)
716 {
717 struct myri10ge_cmd cmd;
718 int status;
719 size_t bytes;
720 u32 len;
721 struct page *dmatest_page;
722 dma_addr_t dmatest_bus;
723
724 /* try to send a reset command to the card to see if it
725 * is alive */
726 memset(&cmd, 0, sizeof(cmd));
727 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
728 if (status != 0) {
729 dev_err(&mgp->pdev->dev, "failed reset\n");
730 return -ENXIO;
731 }
732 dmatest_page = alloc_page(GFP_KERNEL);
733 if (!dmatest_page)
734 return -ENOMEM;
735 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
736 DMA_BIDIRECTIONAL);
737
738 /* Now exchange information about interrupts */
739
740 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
741 memset(mgp->rx_done.entry, 0, bytes);
742 cmd.data0 = (u32) bytes;
743 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
744 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
745 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
746 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
747
748 status |=
749 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
750 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
751 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
752 &cmd, 0);
753 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
754
755 status |= myri10ge_send_cmd
756 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
757 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
758 if (status != 0) {
759 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
760 return status;
761 }
762 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
763
764 /* Run a small DMA test.
765 * The magic multipliers to the length tell the firmware
766 * to do DMA read, write, or read+write tests. The
767 * results are returned in cmd.data0. The upper 16
768 * bits or the return is the number of transfers completed.
769 * The lower 16 bits is the time in 0.5us ticks that the
770 * transfers took to complete.
771 */
772
773 len = mgp->tx.boundary;
774
775 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
776 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
777 cmd.data2 = len * 0x10000;
778 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
779 if (status == 0)
780 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
781 (cmd.data0 & 0xffff);
782 else
783 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
784 status);
785 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
786 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
787 cmd.data2 = len * 0x1;
788 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
789 if (status == 0)
790 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
791 (cmd.data0 & 0xffff);
792 else
793 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
794 status);
795
796 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
797 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
798 cmd.data2 = len * 0x10001;
799 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
800 if (status == 0)
801 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
802 (cmd.data0 & 0xffff);
803 else
804 dev_warn(&mgp->pdev->dev,
805 "DMA read/write benchmark failed: %d\n", status);
806
807 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
808 put_page(dmatest_page);
809
810 memset(mgp->rx_done.entry, 0, bytes);
811
812 /* reset mcp/driver shared state back to 0 */
813 mgp->tx.req = 0;
814 mgp->tx.done = 0;
815 mgp->tx.pkt_start = 0;
816 mgp->tx.pkt_done = 0;
817 mgp->rx_big.cnt = 0;
818 mgp->rx_small.cnt = 0;
819 mgp->rx_done.idx = 0;
820 mgp->rx_done.cnt = 0;
821 mgp->link_changes = 0;
822 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
823 myri10ge_change_promisc(mgp, 0, 0);
824 myri10ge_change_pause(mgp, mgp->pause);
825 if (mgp->adopted_rx_filter_bug)
826 (void)myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
827 return status;
828 }
829
830 static inline void
831 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
832 struct mcp_kreq_ether_recv *src)
833 {
834 __be32 low;
835
836 low = src->addr_low;
837 src->addr_low = htonl(DMA_32BIT_MASK);
838 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
839 mb();
840 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
841 mb();
842 src->addr_low = low;
843 put_be32(low, &dst->addr_low);
844 mb();
845 }
846
847 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
848 {
849 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
850
851 if ((skb->protocol == htons(ETH_P_8021Q)) &&
852 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
853 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
854 skb->csum = hw_csum;
855 skb->ip_summed = CHECKSUM_COMPLETE;
856 }
857 }
858
859 static inline void
860 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
861 struct skb_frag_struct *rx_frags, int len, int hlen)
862 {
863 struct skb_frag_struct *skb_frags;
864
865 skb->len = skb->data_len = len;
866 skb->truesize = len + sizeof(struct sk_buff);
867 /* attach the page(s) */
868
869 skb_frags = skb_shinfo(skb)->frags;
870 while (len > 0) {
871 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
872 len -= rx_frags->size;
873 skb_frags++;
874 rx_frags++;
875 skb_shinfo(skb)->nr_frags++;
876 }
877
878 /* pskb_may_pull is not available in irq context, but
879 * skb_pull() (for ether_pad and eth_type_trans()) requires
880 * the beginning of the packet in skb_headlen(), move it
881 * manually */
882 memcpy(skb->data, va, hlen);
883 skb_shinfo(skb)->frags[0].page_offset += hlen;
884 skb_shinfo(skb)->frags[0].size -= hlen;
885 skb->data_len -= hlen;
886 skb->tail += hlen;
887 skb_pull(skb, MXGEFW_PAD);
888 }
889
890 static void
891 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
892 int bytes, int watchdog)
893 {
894 struct page *page;
895 int idx;
896
897 if (unlikely(rx->watchdog_needed && !watchdog))
898 return;
899
900 /* try to refill entire ring */
901 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
902 idx = rx->fill_cnt & rx->mask;
903
904 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
905 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
906 /* we can use part of previous page */
907 get_page(rx->page);
908 #if MYRI10GE_ALLOC_SIZE > 4096
909 /* Firmware cannot cross 4K boundary.. */
910 if ((rx->page_offset >> 12) !=
911 ((rx->page_offset + bytes - 1) >> 12)) {
912 rx->page_offset =
913 (rx->page_offset + bytes) & ~4095;
914 }
915 #endif
916 } else {
917 /* we need a new page */
918 page =
919 alloc_pages(GFP_ATOMIC | __GFP_COMP,
920 MYRI10GE_ALLOC_ORDER);
921 if (unlikely(page == NULL)) {
922 if (rx->fill_cnt - rx->cnt < 16)
923 rx->watchdog_needed = 1;
924 return;
925 }
926 rx->page = page;
927 rx->page_offset = 0;
928 rx->bus = pci_map_page(mgp->pdev, page, 0,
929 MYRI10GE_ALLOC_SIZE,
930 PCI_DMA_FROMDEVICE);
931 }
932 rx->info[idx].page = rx->page;
933 rx->info[idx].page_offset = rx->page_offset;
934 /* note that this is the address of the start of the
935 * page */
936 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
937 rx->shadow[idx].addr_low =
938 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
939 rx->shadow[idx].addr_high =
940 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
941
942 /* start next packet on a cacheline boundary */
943 rx->page_offset += SKB_DATA_ALIGN(bytes);
944 rx->fill_cnt++;
945
946 /* copy 8 descriptors to the firmware at a time */
947 if ((idx & 7) == 7) {
948 if (rx->wc_fifo == NULL)
949 myri10ge_submit_8rx(&rx->lanai[idx - 7],
950 &rx->shadow[idx - 7]);
951 else {
952 mb();
953 myri10ge_pio_copy(rx->wc_fifo,
954 &rx->shadow[idx - 7], 64);
955 }
956 }
957 }
958 }
959
960 static inline void
961 myri10ge_unmap_rx_page(struct pci_dev *pdev,
962 struct myri10ge_rx_buffer_state *info, int bytes)
963 {
964 /* unmap the recvd page if we're the only or last user of it */
965 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
966 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
967 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
968 & ~(MYRI10GE_ALLOC_SIZE - 1)),
969 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
970 }
971 }
972
973 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
974 * page into an skb */
975
976 static inline int
977 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
978 int bytes, int len, __wsum csum)
979 {
980 struct sk_buff *skb;
981 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
982 int i, idx, hlen, remainder;
983 struct pci_dev *pdev = mgp->pdev;
984 struct net_device *dev = mgp->dev;
985 u8 *va;
986
987 len += MXGEFW_PAD;
988 idx = rx->cnt & rx->mask;
989 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
990 prefetch(va);
991 /* Fill skb_frag_struct(s) with data from our receive */
992 for (i = 0, remainder = len; remainder > 0; i++) {
993 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
994 rx_frags[i].page = rx->info[idx].page;
995 rx_frags[i].page_offset = rx->info[idx].page_offset;
996 if (remainder < MYRI10GE_ALLOC_SIZE)
997 rx_frags[i].size = remainder;
998 else
999 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1000 rx->cnt++;
1001 idx = rx->cnt & rx->mask;
1002 remainder -= MYRI10GE_ALLOC_SIZE;
1003 }
1004
1005 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1006
1007 /* allocate an skb to attach the page(s) to. */
1008
1009 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1010 if (unlikely(skb == NULL)) {
1011 mgp->stats.rx_dropped++;
1012 do {
1013 i--;
1014 put_page(rx_frags[i].page);
1015 } while (i != 0);
1016 return 0;
1017 }
1018
1019 /* Attach the pages to the skb, and trim off any padding */
1020 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1021 if (skb_shinfo(skb)->frags[0].size <= 0) {
1022 put_page(skb_shinfo(skb)->frags[0].page);
1023 skb_shinfo(skb)->nr_frags = 0;
1024 }
1025 skb->protocol = eth_type_trans(skb, dev);
1026 skb->dev = dev;
1027
1028 if (mgp->csum_flag) {
1029 if ((skb->protocol == htons(ETH_P_IP)) ||
1030 (skb->protocol == htons(ETH_P_IPV6))) {
1031 skb->csum = csum;
1032 skb->ip_summed = CHECKSUM_COMPLETE;
1033 } else
1034 myri10ge_vlan_ip_csum(skb, csum);
1035 }
1036 netif_receive_skb(skb);
1037 dev->last_rx = jiffies;
1038 return 1;
1039 }
1040
1041 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1042 {
1043 struct pci_dev *pdev = mgp->pdev;
1044 struct myri10ge_tx_buf *tx = &mgp->tx;
1045 struct sk_buff *skb;
1046 int idx, len;
1047 int limit = 0;
1048
1049 while (tx->pkt_done != mcp_index) {
1050 idx = tx->done & tx->mask;
1051 skb = tx->info[idx].skb;
1052
1053 /* Mark as free */
1054 tx->info[idx].skb = NULL;
1055 if (tx->info[idx].last) {
1056 tx->pkt_done++;
1057 tx->info[idx].last = 0;
1058 }
1059 tx->done++;
1060 len = pci_unmap_len(&tx->info[idx], len);
1061 pci_unmap_len_set(&tx->info[idx], len, 0);
1062 if (skb) {
1063 mgp->stats.tx_bytes += skb->len;
1064 mgp->stats.tx_packets++;
1065 dev_kfree_skb_irq(skb);
1066 if (len)
1067 pci_unmap_single(pdev,
1068 pci_unmap_addr(&tx->info[idx],
1069 bus), len,
1070 PCI_DMA_TODEVICE);
1071 } else {
1072 if (len)
1073 pci_unmap_page(pdev,
1074 pci_unmap_addr(&tx->info[idx],
1075 bus), len,
1076 PCI_DMA_TODEVICE);
1077 }
1078
1079 /* limit potential for livelock by only handling
1080 * 2 full tx rings per call */
1081 if (unlikely(++limit > 2 * tx->mask))
1082 break;
1083 }
1084 /* start the queue if we've stopped it */
1085 if (netif_queue_stopped(mgp->dev)
1086 && tx->req - tx->done < (tx->mask >> 1)) {
1087 mgp->wake_queue++;
1088 netif_wake_queue(mgp->dev);
1089 }
1090 }
1091
1092 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1093 {
1094 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1095 unsigned long rx_bytes = 0;
1096 unsigned long rx_packets = 0;
1097 unsigned long rx_ok;
1098
1099 int idx = rx_done->idx;
1100 int cnt = rx_done->cnt;
1101 u16 length;
1102 __wsum checksum;
1103
1104 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1105 length = ntohs(rx_done->entry[idx].length);
1106 rx_done->entry[idx].length = 0;
1107 checksum = csum_unfold(rx_done->entry[idx].checksum);
1108 if (length <= mgp->small_bytes)
1109 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1110 mgp->small_bytes,
1111 length, checksum);
1112 else
1113 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1114 mgp->big_bytes,
1115 length, checksum);
1116 rx_packets += rx_ok;
1117 rx_bytes += rx_ok * (unsigned long)length;
1118 cnt++;
1119 idx = cnt & (myri10ge_max_intr_slots - 1);
1120
1121 /* limit potential for livelock by only handling a
1122 * limited number of frames. */
1123 (*limit)--;
1124 }
1125 rx_done->idx = idx;
1126 rx_done->cnt = cnt;
1127 mgp->stats.rx_packets += rx_packets;
1128 mgp->stats.rx_bytes += rx_bytes;
1129
1130 /* restock receive rings if needed */
1131 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1132 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1133 mgp->small_bytes + MXGEFW_PAD, 0);
1134 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1135 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1136
1137 }
1138
1139 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1140 {
1141 struct mcp_irq_data *stats = mgp->fw_stats;
1142
1143 if (unlikely(stats->stats_updated)) {
1144 if (mgp->link_state != stats->link_up) {
1145 mgp->link_state = stats->link_up;
1146 if (mgp->link_state) {
1147 if (netif_msg_link(mgp))
1148 printk(KERN_INFO
1149 "myri10ge: %s: link up\n",
1150 mgp->dev->name);
1151 netif_carrier_on(mgp->dev);
1152 mgp->link_changes++;
1153 } else {
1154 if (netif_msg_link(mgp))
1155 printk(KERN_INFO
1156 "myri10ge: %s: link down\n",
1157 mgp->dev->name);
1158 netif_carrier_off(mgp->dev);
1159 mgp->link_changes++;
1160 }
1161 }
1162 if (mgp->rdma_tags_available !=
1163 ntohl(mgp->fw_stats->rdma_tags_available)) {
1164 mgp->rdma_tags_available =
1165 ntohl(mgp->fw_stats->rdma_tags_available);
1166 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1167 "%d tags left\n", mgp->dev->name,
1168 mgp->rdma_tags_available);
1169 }
1170 mgp->down_cnt += stats->link_down;
1171 if (stats->link_down)
1172 wake_up(&mgp->down_wq);
1173 }
1174 }
1175
1176 static int myri10ge_poll(struct net_device *netdev, int *budget)
1177 {
1178 struct myri10ge_priv *mgp = netdev_priv(netdev);
1179 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1180 int limit, orig_limit, work_done;
1181
1182 /* process as many rx events as NAPI will allow */
1183 limit = min(*budget, netdev->quota);
1184 orig_limit = limit;
1185 myri10ge_clean_rx_done(mgp, &limit);
1186 work_done = orig_limit - limit;
1187 *budget -= work_done;
1188 netdev->quota -= work_done;
1189
1190 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1191 netif_rx_complete(netdev);
1192 put_be32(htonl(3), mgp->irq_claim);
1193 return 0;
1194 }
1195 return 1;
1196 }
1197
1198 static irqreturn_t myri10ge_intr(int irq, void *arg)
1199 {
1200 struct myri10ge_priv *mgp = arg;
1201 struct mcp_irq_data *stats = mgp->fw_stats;
1202 struct myri10ge_tx_buf *tx = &mgp->tx;
1203 u32 send_done_count;
1204 int i;
1205
1206 /* make sure it is our IRQ, and that the DMA has finished */
1207 if (unlikely(!stats->valid))
1208 return (IRQ_NONE);
1209
1210 /* low bit indicates receives are present, so schedule
1211 * napi poll handler */
1212 if (stats->valid & 1)
1213 netif_rx_schedule(mgp->dev);
1214
1215 if (!mgp->msi_enabled) {
1216 put_be32(0, mgp->irq_deassert);
1217 if (!myri10ge_deassert_wait)
1218 stats->valid = 0;
1219 mb();
1220 } else
1221 stats->valid = 0;
1222
1223 /* Wait for IRQ line to go low, if using INTx */
1224 i = 0;
1225 while (1) {
1226 i++;
1227 /* check for transmit completes and receives */
1228 send_done_count = ntohl(stats->send_done_count);
1229 if (send_done_count != tx->pkt_done)
1230 myri10ge_tx_done(mgp, (int)send_done_count);
1231 if (unlikely(i > myri10ge_max_irq_loops)) {
1232 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1233 mgp->dev->name);
1234 stats->valid = 0;
1235 schedule_work(&mgp->watchdog_work);
1236 }
1237 if (likely(stats->valid == 0))
1238 break;
1239 cpu_relax();
1240 barrier();
1241 }
1242
1243 myri10ge_check_statblock(mgp);
1244
1245 put_be32(htonl(3), mgp->irq_claim + 1);
1246 return (IRQ_HANDLED);
1247 }
1248
1249 static int
1250 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1251 {
1252 cmd->autoneg = AUTONEG_DISABLE;
1253 cmd->speed = SPEED_10000;
1254 cmd->duplex = DUPLEX_FULL;
1255 return 0;
1256 }
1257
1258 static void
1259 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1260 {
1261 struct myri10ge_priv *mgp = netdev_priv(netdev);
1262
1263 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1264 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1265 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1266 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1267 }
1268
1269 static int
1270 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1271 {
1272 struct myri10ge_priv *mgp = netdev_priv(netdev);
1273 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1274 return 0;
1275 }
1276
1277 static int
1278 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1279 {
1280 struct myri10ge_priv *mgp = netdev_priv(netdev);
1281
1282 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1283 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1284 return 0;
1285 }
1286
1287 static void
1288 myri10ge_get_pauseparam(struct net_device *netdev,
1289 struct ethtool_pauseparam *pause)
1290 {
1291 struct myri10ge_priv *mgp = netdev_priv(netdev);
1292
1293 pause->autoneg = 0;
1294 pause->rx_pause = mgp->pause;
1295 pause->tx_pause = mgp->pause;
1296 }
1297
1298 static int
1299 myri10ge_set_pauseparam(struct net_device *netdev,
1300 struct ethtool_pauseparam *pause)
1301 {
1302 struct myri10ge_priv *mgp = netdev_priv(netdev);
1303
1304 if (pause->tx_pause != mgp->pause)
1305 return myri10ge_change_pause(mgp, pause->tx_pause);
1306 if (pause->rx_pause != mgp->pause)
1307 return myri10ge_change_pause(mgp, pause->tx_pause);
1308 if (pause->autoneg != 0)
1309 return -EINVAL;
1310 return 0;
1311 }
1312
1313 static void
1314 myri10ge_get_ringparam(struct net_device *netdev,
1315 struct ethtool_ringparam *ring)
1316 {
1317 struct myri10ge_priv *mgp = netdev_priv(netdev);
1318
1319 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1320 ring->rx_max_pending = mgp->rx_big.mask + 1;
1321 ring->rx_jumbo_max_pending = 0;
1322 ring->tx_max_pending = mgp->rx_small.mask + 1;
1323 ring->rx_mini_pending = ring->rx_mini_max_pending;
1324 ring->rx_pending = ring->rx_max_pending;
1325 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1326 ring->tx_pending = ring->tx_max_pending;
1327 }
1328
1329 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1330 {
1331 struct myri10ge_priv *mgp = netdev_priv(netdev);
1332 if (mgp->csum_flag)
1333 return 1;
1334 else
1335 return 0;
1336 }
1337
1338 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1339 {
1340 struct myri10ge_priv *mgp = netdev_priv(netdev);
1341 if (csum_enabled)
1342 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1343 else
1344 mgp->csum_flag = 0;
1345 return 0;
1346 }
1347
1348 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1349 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1350 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1351 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1352 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1353 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1354 "tx_heartbeat_errors", "tx_window_errors",
1355 /* device-specific stats */
1356 "tx_boundary", "WC", "irq", "MSI",
1357 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1358 "serial_number", "tx_pkt_start", "tx_pkt_done",
1359 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1360 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1361 "link_changes", "link_up", "dropped_link_overflow",
1362 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
1363 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1364 "dropped_no_big_buffer"
1365 };
1366
1367 #define MYRI10GE_NET_STATS_LEN 21
1368 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1369
1370 static void
1371 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1372 {
1373 switch (stringset) {
1374 case ETH_SS_STATS:
1375 memcpy(data, *myri10ge_gstrings_stats,
1376 sizeof(myri10ge_gstrings_stats));
1377 break;
1378 }
1379 }
1380
1381 static int myri10ge_get_stats_count(struct net_device *netdev)
1382 {
1383 return MYRI10GE_STATS_LEN;
1384 }
1385
1386 static void
1387 myri10ge_get_ethtool_stats(struct net_device *netdev,
1388 struct ethtool_stats *stats, u64 * data)
1389 {
1390 struct myri10ge_priv *mgp = netdev_priv(netdev);
1391 int i;
1392
1393 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1394 data[i] = ((unsigned long *)&mgp->stats)[i];
1395
1396 data[i++] = (unsigned int)mgp->tx.boundary;
1397 data[i++] = (unsigned int)mgp->wc_enabled;
1398 data[i++] = (unsigned int)mgp->pdev->irq;
1399 data[i++] = (unsigned int)mgp->msi_enabled;
1400 data[i++] = (unsigned int)mgp->read_dma;
1401 data[i++] = (unsigned int)mgp->write_dma;
1402 data[i++] = (unsigned int)mgp->read_write_dma;
1403 data[i++] = (unsigned int)mgp->serial_number;
1404 data[i++] = (unsigned int)mgp->tx.pkt_start;
1405 data[i++] = (unsigned int)mgp->tx.pkt_done;
1406 data[i++] = (unsigned int)mgp->tx.req;
1407 data[i++] = (unsigned int)mgp->tx.done;
1408 data[i++] = (unsigned int)mgp->rx_small.cnt;
1409 data[i++] = (unsigned int)mgp->rx_big.cnt;
1410 data[i++] = (unsigned int)mgp->wake_queue;
1411 data[i++] = (unsigned int)mgp->stop_queue;
1412 data[i++] = (unsigned int)mgp->watchdog_resets;
1413 data[i++] = (unsigned int)mgp->tx_linearized;
1414 data[i++] = (unsigned int)mgp->link_changes;
1415 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1416 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1417 data[i++] =
1418 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1419 data[i++] =
1420 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1421 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1422 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1423 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1424 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1425 }
1426
1427 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1428 {
1429 struct myri10ge_priv *mgp = netdev_priv(netdev);
1430 mgp->msg_enable = value;
1431 }
1432
1433 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1434 {
1435 struct myri10ge_priv *mgp = netdev_priv(netdev);
1436 return mgp->msg_enable;
1437 }
1438
1439 static const struct ethtool_ops myri10ge_ethtool_ops = {
1440 .get_settings = myri10ge_get_settings,
1441 .get_drvinfo = myri10ge_get_drvinfo,
1442 .get_coalesce = myri10ge_get_coalesce,
1443 .set_coalesce = myri10ge_set_coalesce,
1444 .get_pauseparam = myri10ge_get_pauseparam,
1445 .set_pauseparam = myri10ge_set_pauseparam,
1446 .get_ringparam = myri10ge_get_ringparam,
1447 .get_rx_csum = myri10ge_get_rx_csum,
1448 .set_rx_csum = myri10ge_set_rx_csum,
1449 .get_tx_csum = ethtool_op_get_tx_csum,
1450 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1451 .get_sg = ethtool_op_get_sg,
1452 .set_sg = ethtool_op_set_sg,
1453 .get_tso = ethtool_op_get_tso,
1454 .set_tso = ethtool_op_set_tso,
1455 .get_strings = myri10ge_get_strings,
1456 .get_stats_count = myri10ge_get_stats_count,
1457 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1458 .set_msglevel = myri10ge_set_msglevel,
1459 .get_msglevel = myri10ge_get_msglevel
1460 };
1461
1462 static int myri10ge_allocate_rings(struct net_device *dev)
1463 {
1464 struct myri10ge_priv *mgp;
1465 struct myri10ge_cmd cmd;
1466 int tx_ring_size, rx_ring_size;
1467 int tx_ring_entries, rx_ring_entries;
1468 int i, status;
1469 size_t bytes;
1470
1471 mgp = netdev_priv(dev);
1472
1473 /* get ring sizes */
1474
1475 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1476 tx_ring_size = cmd.data0;
1477 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1478 if (status != 0)
1479 return status;
1480 rx_ring_size = cmd.data0;
1481
1482 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1483 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1484 mgp->tx.mask = tx_ring_entries - 1;
1485 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1486
1487 status = -ENOMEM;
1488
1489 /* allocate the host shadow rings */
1490
1491 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1492 * sizeof(*mgp->tx.req_list);
1493 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1494 if (mgp->tx.req_bytes == NULL)
1495 goto abort_with_nothing;
1496
1497 /* ensure req_list entries are aligned to 8 bytes */
1498 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1499 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1500
1501 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1502 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1503 if (mgp->rx_small.shadow == NULL)
1504 goto abort_with_tx_req_bytes;
1505
1506 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1507 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1508 if (mgp->rx_big.shadow == NULL)
1509 goto abort_with_rx_small_shadow;
1510
1511 /* allocate the host info rings */
1512
1513 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1514 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1515 if (mgp->tx.info == NULL)
1516 goto abort_with_rx_big_shadow;
1517
1518 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1519 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1520 if (mgp->rx_small.info == NULL)
1521 goto abort_with_tx_info;
1522
1523 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1524 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1525 if (mgp->rx_big.info == NULL)
1526 goto abort_with_rx_small_info;
1527
1528 /* Fill the receive rings */
1529 mgp->rx_big.cnt = 0;
1530 mgp->rx_small.cnt = 0;
1531 mgp->rx_big.fill_cnt = 0;
1532 mgp->rx_small.fill_cnt = 0;
1533 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1534 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1535 mgp->rx_small.watchdog_needed = 0;
1536 mgp->rx_big.watchdog_needed = 0;
1537 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1538 mgp->small_bytes + MXGEFW_PAD, 0);
1539
1540 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1541 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1542 dev->name, mgp->rx_small.fill_cnt);
1543 goto abort_with_rx_small_ring;
1544 }
1545
1546 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1547 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1548 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1549 dev->name, mgp->rx_big.fill_cnt);
1550 goto abort_with_rx_big_ring;
1551 }
1552
1553 return 0;
1554
1555 abort_with_rx_big_ring:
1556 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1557 int idx = i & mgp->rx_big.mask;
1558 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1559 mgp->big_bytes);
1560 put_page(mgp->rx_big.info[idx].page);
1561 }
1562
1563 abort_with_rx_small_ring:
1564 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1565 int idx = i & mgp->rx_small.mask;
1566 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1567 mgp->small_bytes + MXGEFW_PAD);
1568 put_page(mgp->rx_small.info[idx].page);
1569 }
1570
1571 kfree(mgp->rx_big.info);
1572
1573 abort_with_rx_small_info:
1574 kfree(mgp->rx_small.info);
1575
1576 abort_with_tx_info:
1577 kfree(mgp->tx.info);
1578
1579 abort_with_rx_big_shadow:
1580 kfree(mgp->rx_big.shadow);
1581
1582 abort_with_rx_small_shadow:
1583 kfree(mgp->rx_small.shadow);
1584
1585 abort_with_tx_req_bytes:
1586 kfree(mgp->tx.req_bytes);
1587 mgp->tx.req_bytes = NULL;
1588 mgp->tx.req_list = NULL;
1589
1590 abort_with_nothing:
1591 return status;
1592 }
1593
1594 static void myri10ge_free_rings(struct net_device *dev)
1595 {
1596 struct myri10ge_priv *mgp;
1597 struct sk_buff *skb;
1598 struct myri10ge_tx_buf *tx;
1599 int i, len, idx;
1600
1601 mgp = netdev_priv(dev);
1602
1603 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1604 idx = i & mgp->rx_big.mask;
1605 if (i == mgp->rx_big.fill_cnt - 1)
1606 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1607 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1608 mgp->big_bytes);
1609 put_page(mgp->rx_big.info[idx].page);
1610 }
1611
1612 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1613 idx = i & mgp->rx_small.mask;
1614 if (i == mgp->rx_small.fill_cnt - 1)
1615 mgp->rx_small.info[idx].page_offset =
1616 MYRI10GE_ALLOC_SIZE;
1617 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1618 mgp->small_bytes + MXGEFW_PAD);
1619 put_page(mgp->rx_small.info[idx].page);
1620 }
1621 tx = &mgp->tx;
1622 while (tx->done != tx->req) {
1623 idx = tx->done & tx->mask;
1624 skb = tx->info[idx].skb;
1625
1626 /* Mark as free */
1627 tx->info[idx].skb = NULL;
1628 tx->done++;
1629 len = pci_unmap_len(&tx->info[idx], len);
1630 pci_unmap_len_set(&tx->info[idx], len, 0);
1631 if (skb) {
1632 mgp->stats.tx_dropped++;
1633 dev_kfree_skb_any(skb);
1634 if (len)
1635 pci_unmap_single(mgp->pdev,
1636 pci_unmap_addr(&tx->info[idx],
1637 bus), len,
1638 PCI_DMA_TODEVICE);
1639 } else {
1640 if (len)
1641 pci_unmap_page(mgp->pdev,
1642 pci_unmap_addr(&tx->info[idx],
1643 bus), len,
1644 PCI_DMA_TODEVICE);
1645 }
1646 }
1647 kfree(mgp->rx_big.info);
1648
1649 kfree(mgp->rx_small.info);
1650
1651 kfree(mgp->tx.info);
1652
1653 kfree(mgp->rx_big.shadow);
1654
1655 kfree(mgp->rx_small.shadow);
1656
1657 kfree(mgp->tx.req_bytes);
1658 mgp->tx.req_bytes = NULL;
1659 mgp->tx.req_list = NULL;
1660 }
1661
1662 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1663 {
1664 struct pci_dev *pdev = mgp->pdev;
1665 int status;
1666
1667 if (myri10ge_msi) {
1668 status = pci_enable_msi(pdev);
1669 if (status != 0)
1670 dev_err(&pdev->dev,
1671 "Error %d setting up MSI; falling back to xPIC\n",
1672 status);
1673 else
1674 mgp->msi_enabled = 1;
1675 } else {
1676 mgp->msi_enabled = 0;
1677 }
1678 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1679 mgp->dev->name, mgp);
1680 if (status != 0) {
1681 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1682 if (mgp->msi_enabled)
1683 pci_disable_msi(pdev);
1684 }
1685 return status;
1686 }
1687
1688 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1689 {
1690 struct pci_dev *pdev = mgp->pdev;
1691
1692 free_irq(pdev->irq, mgp);
1693 if (mgp->msi_enabled)
1694 pci_disable_msi(pdev);
1695 }
1696
1697 static int myri10ge_open(struct net_device *dev)
1698 {
1699 struct myri10ge_priv *mgp;
1700 struct myri10ge_cmd cmd;
1701 int status, big_pow2;
1702
1703 mgp = netdev_priv(dev);
1704
1705 if (mgp->running != MYRI10GE_ETH_STOPPED)
1706 return -EBUSY;
1707
1708 mgp->running = MYRI10GE_ETH_STARTING;
1709 status = myri10ge_reset(mgp);
1710 if (status != 0) {
1711 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1712 goto abort_with_nothing;
1713 }
1714
1715 status = myri10ge_request_irq(mgp);
1716 if (status != 0)
1717 goto abort_with_nothing;
1718
1719 /* decide what small buffer size to use. For good TCP rx
1720 * performance, it is important to not receive 1514 byte
1721 * frames into jumbo buffers, as it confuses the socket buffer
1722 * accounting code, leading to drops and erratic performance.
1723 */
1724
1725 if (dev->mtu <= ETH_DATA_LEN)
1726 /* enough for a TCP header */
1727 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1728 ? (128 - MXGEFW_PAD)
1729 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1730 else
1731 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1732 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1733
1734 /* Override the small buffer size? */
1735 if (myri10ge_small_bytes > 0)
1736 mgp->small_bytes = myri10ge_small_bytes;
1737
1738 /* get the lanai pointers to the send and receive rings */
1739
1740 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1741 mgp->tx.lanai =
1742 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1743
1744 status |=
1745 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1746 mgp->rx_small.lanai =
1747 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1748
1749 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1750 mgp->rx_big.lanai =
1751 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1752
1753 if (status != 0) {
1754 printk(KERN_ERR
1755 "myri10ge: %s: failed to get ring sizes or locations\n",
1756 dev->name);
1757 mgp->running = MYRI10GE_ETH_STOPPED;
1758 goto abort_with_irq;
1759 }
1760
1761 if (myri10ge_wcfifo && mgp->wc_enabled) {
1762 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1763 mgp->rx_small.wc_fifo =
1764 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1765 mgp->rx_big.wc_fifo =
1766 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1767 } else {
1768 mgp->tx.wc_fifo = NULL;
1769 mgp->rx_small.wc_fifo = NULL;
1770 mgp->rx_big.wc_fifo = NULL;
1771 }
1772
1773 /* Firmware needs the big buff size as a power of 2. Lie and
1774 * tell him the buffer is larger, because we only use 1
1775 * buffer/pkt, and the mtu will prevent overruns.
1776 */
1777 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1778 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1779 while ((big_pow2 & (big_pow2 - 1)) != 0)
1780 big_pow2++;
1781 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1782 } else {
1783 big_pow2 = MYRI10GE_ALLOC_SIZE;
1784 mgp->big_bytes = big_pow2;
1785 }
1786
1787 status = myri10ge_allocate_rings(dev);
1788 if (status != 0)
1789 goto abort_with_irq;
1790
1791 /* now give firmware buffers sizes, and MTU */
1792 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1793 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1794 cmd.data0 = mgp->small_bytes;
1795 status |=
1796 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1797 cmd.data0 = big_pow2;
1798 status |=
1799 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1800 if (status) {
1801 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1802 dev->name);
1803 goto abort_with_rings;
1804 }
1805
1806 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1807 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1808 cmd.data2 = sizeof(struct mcp_irq_data);
1809 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1810 if (status == -ENOSYS) {
1811 dma_addr_t bus = mgp->fw_stats_bus;
1812 bus += offsetof(struct mcp_irq_data, send_done_count);
1813 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1814 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1815 status = myri10ge_send_cmd(mgp,
1816 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1817 &cmd, 0);
1818 /* Firmware cannot support multicast without STATS_DMA_V2 */
1819 mgp->fw_multicast_support = 0;
1820 } else {
1821 mgp->fw_multicast_support = 1;
1822 }
1823 if (status) {
1824 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1825 dev->name);
1826 goto abort_with_rings;
1827 }
1828
1829 mgp->link_state = htonl(~0U);
1830 mgp->rdma_tags_available = 15;
1831
1832 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1833
1834 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1835 if (status) {
1836 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1837 dev->name);
1838 goto abort_with_rings;
1839 }
1840
1841 mgp->wake_queue = 0;
1842 mgp->stop_queue = 0;
1843 mgp->running = MYRI10GE_ETH_RUNNING;
1844 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1845 add_timer(&mgp->watchdog_timer);
1846 netif_wake_queue(dev);
1847 return 0;
1848
1849 abort_with_rings:
1850 myri10ge_free_rings(dev);
1851
1852 abort_with_irq:
1853 myri10ge_free_irq(mgp);
1854
1855 abort_with_nothing:
1856 mgp->running = MYRI10GE_ETH_STOPPED;
1857 return -ENOMEM;
1858 }
1859
1860 static int myri10ge_close(struct net_device *dev)
1861 {
1862 struct myri10ge_priv *mgp;
1863 struct myri10ge_cmd cmd;
1864 int status, old_down_cnt;
1865
1866 mgp = netdev_priv(dev);
1867
1868 if (mgp->running != MYRI10GE_ETH_RUNNING)
1869 return 0;
1870
1871 if (mgp->tx.req_bytes == NULL)
1872 return 0;
1873
1874 del_timer_sync(&mgp->watchdog_timer);
1875 mgp->running = MYRI10GE_ETH_STOPPING;
1876 netif_poll_disable(mgp->dev);
1877 netif_carrier_off(dev);
1878 netif_stop_queue(dev);
1879 old_down_cnt = mgp->down_cnt;
1880 mb();
1881 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1882 if (status)
1883 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1884 dev->name);
1885
1886 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1887 if (old_down_cnt == mgp->down_cnt)
1888 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1889
1890 netif_tx_disable(dev);
1891 myri10ge_free_irq(mgp);
1892 myri10ge_free_rings(dev);
1893
1894 mgp->running = MYRI10GE_ETH_STOPPED;
1895 return 0;
1896 }
1897
1898 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1899 * backwards one at a time and handle ring wraps */
1900
1901 static inline void
1902 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1903 struct mcp_kreq_ether_send *src, int cnt)
1904 {
1905 int idx, starting_slot;
1906 starting_slot = tx->req;
1907 while (cnt > 1) {
1908 cnt--;
1909 idx = (starting_slot + cnt) & tx->mask;
1910 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1911 mb();
1912 }
1913 }
1914
1915 /*
1916 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1917 * at most 32 bytes at a time, so as to avoid involving the software
1918 * pio handler in the nic. We re-write the first segment's flags
1919 * to mark them valid only after writing the entire chain.
1920 */
1921
1922 static inline void
1923 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1924 int cnt)
1925 {
1926 int idx, i;
1927 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1928 struct mcp_kreq_ether_send *srcp;
1929 u8 last_flags;
1930
1931 idx = tx->req & tx->mask;
1932
1933 last_flags = src->flags;
1934 src->flags = 0;
1935 mb();
1936 dst = dstp = &tx->lanai[idx];
1937 srcp = src;
1938
1939 if ((idx + cnt) < tx->mask) {
1940 for (i = 0; i < (cnt - 1); i += 2) {
1941 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1942 mb(); /* force write every 32 bytes */
1943 srcp += 2;
1944 dstp += 2;
1945 }
1946 } else {
1947 /* submit all but the first request, and ensure
1948 * that it is submitted below */
1949 myri10ge_submit_req_backwards(tx, src, cnt);
1950 i = 0;
1951 }
1952 if (i < cnt) {
1953 /* submit the first request */
1954 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1955 mb(); /* barrier before setting valid flag */
1956 }
1957
1958 /* re-write the last 32-bits with the valid flags */
1959 src->flags = last_flags;
1960 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1961 tx->req += cnt;
1962 mb();
1963 }
1964
1965 static inline void
1966 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1967 struct mcp_kreq_ether_send *src, int cnt)
1968 {
1969 tx->req += cnt;
1970 mb();
1971 while (cnt >= 4) {
1972 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1973 mb();
1974 src += 4;
1975 cnt -= 4;
1976 }
1977 if (cnt > 0) {
1978 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1979 * needs to be so that we don't overrun it */
1980 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1981 src, 64);
1982 mb();
1983 }
1984 }
1985
1986 /*
1987 * Transmit a packet. We need to split the packet so that a single
1988 * segment does not cross myri10ge->tx.boundary, so this makes segment
1989 * counting tricky. So rather than try to count segments up front, we
1990 * just give up if there are too few segments to hold a reasonably
1991 * fragmented packet currently available. If we run
1992 * out of segments while preparing a packet for DMA, we just linearize
1993 * it and try again.
1994 */
1995
1996 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1997 {
1998 struct myri10ge_priv *mgp = netdev_priv(dev);
1999 struct mcp_kreq_ether_send *req;
2000 struct myri10ge_tx_buf *tx = &mgp->tx;
2001 struct skb_frag_struct *frag;
2002 dma_addr_t bus;
2003 u32 low;
2004 __be32 high_swapped;
2005 unsigned int len;
2006 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2007 u16 pseudo_hdr_offset, cksum_offset;
2008 int cum_len, seglen, boundary, rdma_count;
2009 u8 flags, odd_flag;
2010
2011 again:
2012 req = tx->req_list;
2013 avail = tx->mask - 1 - (tx->req - tx->done);
2014
2015 mss = 0;
2016 max_segments = MXGEFW_MAX_SEND_DESC;
2017
2018 if (skb->len > (dev->mtu + ETH_HLEN)) {
2019 mss = skb_shinfo(skb)->gso_size;
2020 if (mss != 0)
2021 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2022 }
2023
2024 if ((unlikely(avail < max_segments))) {
2025 /* we are out of transmit resources */
2026 mgp->stop_queue++;
2027 netif_stop_queue(dev);
2028 return 1;
2029 }
2030
2031 /* Setup checksum offloading, if needed */
2032 cksum_offset = 0;
2033 pseudo_hdr_offset = 0;
2034 odd_flag = 0;
2035 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2036 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2037 cksum_offset = (skb->h.raw - skb->data);
2038 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2039 /* If the headers are excessively large, then we must
2040 * fall back to a software checksum */
2041 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2042 if (skb_checksum_help(skb))
2043 goto drop;
2044 cksum_offset = 0;
2045 pseudo_hdr_offset = 0;
2046 } else {
2047 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2048 flags |= MXGEFW_FLAGS_CKSUM;
2049 }
2050 }
2051
2052 cum_len = 0;
2053
2054 if (mss) { /* TSO */
2055 /* this removes any CKSUM flag from before */
2056 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2057
2058 /* negative cum_len signifies to the
2059 * send loop that we are still in the
2060 * header portion of the TSO packet.
2061 * TSO header must be at most 134 bytes long */
2062 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2063
2064 /* for TSO, pseudo_hdr_offset holds mss.
2065 * The firmware figures out where to put
2066 * the checksum by parsing the header. */
2067 pseudo_hdr_offset = mss;
2068 } else
2069 /* Mark small packets, and pad out tiny packets */
2070 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2071 flags |= MXGEFW_FLAGS_SMALL;
2072
2073 /* pad frames to at least ETH_ZLEN bytes */
2074 if (unlikely(skb->len < ETH_ZLEN)) {
2075 if (skb_padto(skb, ETH_ZLEN)) {
2076 /* The packet is gone, so we must
2077 * return 0 */
2078 mgp->stats.tx_dropped += 1;
2079 return 0;
2080 }
2081 /* adjust the len to account for the zero pad
2082 * so that the nic can know how long it is */
2083 skb->len = ETH_ZLEN;
2084 }
2085 }
2086
2087 /* map the skb for DMA */
2088 len = skb->len - skb->data_len;
2089 idx = tx->req & tx->mask;
2090 tx->info[idx].skb = skb;
2091 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2092 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2093 pci_unmap_len_set(&tx->info[idx], len, len);
2094
2095 frag_cnt = skb_shinfo(skb)->nr_frags;
2096 frag_idx = 0;
2097 count = 0;
2098 rdma_count = 0;
2099
2100 /* "rdma_count" is the number of RDMAs belonging to the
2101 * current packet BEFORE the current send request. For
2102 * non-TSO packets, this is equal to "count".
2103 * For TSO packets, rdma_count needs to be reset
2104 * to 0 after a segment cut.
2105 *
2106 * The rdma_count field of the send request is
2107 * the number of RDMAs of the packet starting at
2108 * that request. For TSO send requests with one ore more cuts
2109 * in the middle, this is the number of RDMAs starting
2110 * after the last cut in the request. All previous
2111 * segments before the last cut implicitly have 1 RDMA.
2112 *
2113 * Since the number of RDMAs is not known beforehand,
2114 * it must be filled-in retroactively - after each
2115 * segmentation cut or at the end of the entire packet.
2116 */
2117
2118 while (1) {
2119 /* Break the SKB or Fragment up into pieces which
2120 * do not cross mgp->tx.boundary */
2121 low = MYRI10GE_LOWPART_TO_U32(bus);
2122 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2123 while (len) {
2124 u8 flags_next;
2125 int cum_len_next;
2126
2127 if (unlikely(count == max_segments))
2128 goto abort_linearize;
2129
2130 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2131 seglen = boundary - low;
2132 if (seglen > len)
2133 seglen = len;
2134 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2135 cum_len_next = cum_len + seglen;
2136 if (mss) { /* TSO */
2137 (req - rdma_count)->rdma_count = rdma_count + 1;
2138
2139 if (likely(cum_len >= 0)) { /* payload */
2140 int next_is_first, chop;
2141
2142 chop = (cum_len_next > mss);
2143 cum_len_next = cum_len_next % mss;
2144 next_is_first = (cum_len_next == 0);
2145 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2146 flags_next |= next_is_first *
2147 MXGEFW_FLAGS_FIRST;
2148 rdma_count |= -(chop | next_is_first);
2149 rdma_count += chop & !next_is_first;
2150 } else if (likely(cum_len_next >= 0)) { /* header ends */
2151 int small;
2152
2153 rdma_count = -1;
2154 cum_len_next = 0;
2155 seglen = -cum_len;
2156 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2157 flags_next = MXGEFW_FLAGS_TSO_PLD |
2158 MXGEFW_FLAGS_FIRST |
2159 (small * MXGEFW_FLAGS_SMALL);
2160 }
2161 }
2162 req->addr_high = high_swapped;
2163 req->addr_low = htonl(low);
2164 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2165 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2166 req->rdma_count = 1;
2167 req->length = htons(seglen);
2168 req->cksum_offset = cksum_offset;
2169 req->flags = flags | ((cum_len & 1) * odd_flag);
2170
2171 low += seglen;
2172 len -= seglen;
2173 cum_len = cum_len_next;
2174 flags = flags_next;
2175 req++;
2176 count++;
2177 rdma_count++;
2178 if (unlikely(cksum_offset > seglen))
2179 cksum_offset -= seglen;
2180 else
2181 cksum_offset = 0;
2182 }
2183 if (frag_idx == frag_cnt)
2184 break;
2185
2186 /* map next fragment for DMA */
2187 idx = (count + tx->req) & tx->mask;
2188 frag = &skb_shinfo(skb)->frags[frag_idx];
2189 frag_idx++;
2190 len = frag->size;
2191 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2192 len, PCI_DMA_TODEVICE);
2193 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2194 pci_unmap_len_set(&tx->info[idx], len, len);
2195 }
2196
2197 (req - rdma_count)->rdma_count = rdma_count;
2198 if (mss)
2199 do {
2200 req--;
2201 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2202 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2203 MXGEFW_FLAGS_FIRST)));
2204 idx = ((count - 1) + tx->req) & tx->mask;
2205 tx->info[idx].last = 1;
2206 if (tx->wc_fifo == NULL)
2207 myri10ge_submit_req(tx, tx->req_list, count);
2208 else
2209 myri10ge_submit_req_wc(tx, tx->req_list, count);
2210 tx->pkt_start++;
2211 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2212 mgp->stop_queue++;
2213 netif_stop_queue(dev);
2214 }
2215 dev->trans_start = jiffies;
2216 return 0;
2217
2218 abort_linearize:
2219 /* Free any DMA resources we've alloced and clear out the skb
2220 * slot so as to not trip up assertions, and to avoid a
2221 * double-free if linearizing fails */
2222
2223 last_idx = (idx + 1) & tx->mask;
2224 idx = tx->req & tx->mask;
2225 tx->info[idx].skb = NULL;
2226 do {
2227 len = pci_unmap_len(&tx->info[idx], len);
2228 if (len) {
2229 if (tx->info[idx].skb != NULL)
2230 pci_unmap_single(mgp->pdev,
2231 pci_unmap_addr(&tx->info[idx],
2232 bus), len,
2233 PCI_DMA_TODEVICE);
2234 else
2235 pci_unmap_page(mgp->pdev,
2236 pci_unmap_addr(&tx->info[idx],
2237 bus), len,
2238 PCI_DMA_TODEVICE);
2239 pci_unmap_len_set(&tx->info[idx], len, 0);
2240 tx->info[idx].skb = NULL;
2241 }
2242 idx = (idx + 1) & tx->mask;
2243 } while (idx != last_idx);
2244 if (skb_is_gso(skb)) {
2245 printk(KERN_ERR
2246 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2247 mgp->dev->name);
2248 goto drop;
2249 }
2250
2251 if (skb_linearize(skb))
2252 goto drop;
2253
2254 mgp->tx_linearized++;
2255 goto again;
2256
2257 drop:
2258 dev_kfree_skb_any(skb);
2259 mgp->stats.tx_dropped += 1;
2260 return 0;
2261
2262 }
2263
2264 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2265 {
2266 struct myri10ge_priv *mgp = netdev_priv(dev);
2267 return &mgp->stats;
2268 }
2269
2270 static void myri10ge_set_multicast_list(struct net_device *dev)
2271 {
2272 struct myri10ge_cmd cmd;
2273 struct myri10ge_priv *mgp;
2274 struct dev_mc_list *mc_list;
2275 __be32 data[2] = { 0, 0 };
2276 int err;
2277
2278 mgp = netdev_priv(dev);
2279 /* can be called from atomic contexts,
2280 * pass 1 to force atomicity in myri10ge_send_cmd() */
2281 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2282
2283 /* This firmware is known to not support multicast */
2284 if (!mgp->fw_multicast_support || mgp->adopted_rx_filter_bug)
2285 return;
2286
2287 /* Disable multicast filtering */
2288
2289 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2290 if (err != 0) {
2291 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2292 " error status: %d\n", dev->name, err);
2293 goto abort;
2294 }
2295
2296 if (dev->flags & IFF_ALLMULTI) {
2297 /* request to disable multicast filtering, so quit here */
2298 return;
2299 }
2300
2301 /* Flush the filters */
2302
2303 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2304 &cmd, 1);
2305 if (err != 0) {
2306 printk(KERN_ERR
2307 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2308 ", error status: %d\n", dev->name, err);
2309 goto abort;
2310 }
2311
2312 /* Walk the multicast list, and add each address */
2313 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2314 memcpy(data, &mc_list->dmi_addr, 6);
2315 cmd.data0 = ntohl(data[0]);
2316 cmd.data1 = ntohl(data[1]);
2317 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2318 &cmd, 1);
2319
2320 if (err != 0) {
2321 printk(KERN_ERR "myri10ge: %s: Failed "
2322 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2323 "%d\t", dev->name, err);
2324 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2325 ((unsigned char *)&mc_list->dmi_addr)[0],
2326 ((unsigned char *)&mc_list->dmi_addr)[1],
2327 ((unsigned char *)&mc_list->dmi_addr)[2],
2328 ((unsigned char *)&mc_list->dmi_addr)[3],
2329 ((unsigned char *)&mc_list->dmi_addr)[4],
2330 ((unsigned char *)&mc_list->dmi_addr)[5]
2331 );
2332 goto abort;
2333 }
2334 }
2335 /* Enable multicast filtering */
2336 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2337 if (err != 0) {
2338 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2339 "error status: %d\n", dev->name, err);
2340 goto abort;
2341 }
2342
2343 return;
2344
2345 abort:
2346 return;
2347 }
2348
2349 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2350 {
2351 struct sockaddr *sa = addr;
2352 struct myri10ge_priv *mgp = netdev_priv(dev);
2353 int status;
2354
2355 if (!is_valid_ether_addr(sa->sa_data))
2356 return -EADDRNOTAVAIL;
2357
2358 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2359 if (status != 0) {
2360 printk(KERN_ERR
2361 "myri10ge: %s: changing mac address failed with %d\n",
2362 dev->name, status);
2363 return status;
2364 }
2365
2366 /* change the dev structure */
2367 memcpy(dev->dev_addr, sa->sa_data, 6);
2368 return 0;
2369 }
2370
2371 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2372 {
2373 struct myri10ge_priv *mgp = netdev_priv(dev);
2374 int error = 0;
2375
2376 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2377 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2378 dev->name, new_mtu);
2379 return -EINVAL;
2380 }
2381 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2382 dev->name, dev->mtu, new_mtu);
2383 if (mgp->running) {
2384 /* if we change the mtu on an active device, we must
2385 * reset the device so the firmware sees the change */
2386 myri10ge_close(dev);
2387 dev->mtu = new_mtu;
2388 myri10ge_open(dev);
2389 } else
2390 dev->mtu = new_mtu;
2391
2392 return error;
2393 }
2394
2395 /*
2396 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2397 * Only do it if the bridge is a root port since we don't want to disturb
2398 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2399 */
2400
2401 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2402 {
2403 struct pci_dev *bridge = mgp->pdev->bus->self;
2404 struct device *dev = &mgp->pdev->dev;
2405 unsigned cap;
2406 unsigned err_cap;
2407 u16 val;
2408 u8 ext_type;
2409 int ret;
2410
2411 if (!myri10ge_ecrc_enable || !bridge)
2412 return;
2413
2414 /* check that the bridge is a root port */
2415 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2416 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2417 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2418 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2419 if (myri10ge_ecrc_enable > 1) {
2420 struct pci_dev *old_bridge = bridge;
2421
2422 /* Walk the hierarchy up to the root port
2423 * where ECRC has to be enabled */
2424 do {
2425 bridge = bridge->bus->self;
2426 if (!bridge) {
2427 dev_err(dev,
2428 "Failed to find root port"
2429 " to force ECRC\n");
2430 return;
2431 }
2432 cap =
2433 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2434 pci_read_config_word(bridge,
2435 cap + PCI_CAP_FLAGS, &val);
2436 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2437 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2438
2439 dev_info(dev,
2440 "Forcing ECRC on non-root port %s"
2441 " (enabling on root port %s)\n",
2442 pci_name(old_bridge), pci_name(bridge));
2443 } else {
2444 dev_err(dev,
2445 "Not enabling ECRC on non-root port %s\n",
2446 pci_name(bridge));
2447 return;
2448 }
2449 }
2450
2451 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2452 if (!cap)
2453 return;
2454
2455 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2456 if (ret) {
2457 dev_err(dev, "failed reading ext-conf-space of %s\n",
2458 pci_name(bridge));
2459 dev_err(dev, "\t pci=nommconf in use? "
2460 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2461 return;
2462 }
2463 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2464 return;
2465
2466 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2467 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2468 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2469 mgp->tx.boundary = 4096;
2470 mgp->fw_name = myri10ge_fw_aligned;
2471 }
2472
2473 /*
2474 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2475 * when the PCI-E Completion packets are aligned on an 8-byte
2476 * boundary. Some PCI-E chip sets always align Completion packets; on
2477 * the ones that do not, the alignment can be enforced by enabling
2478 * ECRC generation (if supported).
2479 *
2480 * When PCI-E Completion packets are not aligned, it is actually more
2481 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2482 *
2483 * If the driver can neither enable ECRC nor verify that it has
2484 * already been enabled, then it must use a firmware image which works
2485 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2486 * should also ensure that it never gives the device a Read-DMA which is
2487 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2488 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2489 * firmware image, and set tx.boundary to 4KB.
2490 */
2491
2492 #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2493 #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2494 #define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST 0x140
2495 #define PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST 0x142
2496
2497 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2498 {
2499 struct pci_dev *bridge = mgp->pdev->bus->self;
2500
2501 mgp->tx.boundary = 2048;
2502 mgp->fw_name = myri10ge_fw_unaligned;
2503
2504 if (myri10ge_force_firmware == 0) {
2505 int link_width, exp_cap;
2506 u16 lnk;
2507
2508 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2509 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2510 link_width = (lnk >> 4) & 0x3f;
2511
2512 myri10ge_enable_ecrc(mgp);
2513
2514 /* Check to see if Link is less than 8 or if the
2515 * upstream bridge is known to provide aligned
2516 * completions */
2517 if (link_width < 8) {
2518 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2519 link_width);
2520 mgp->tx.boundary = 4096;
2521 mgp->fw_name = myri10ge_fw_aligned;
2522 } else if (bridge &&
2523 /* ServerWorks HT2000/HT1000 */
2524 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2525 && bridge->device ==
2526 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2527 /* ServerWorks HT2100 */
2528 || (bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2529 && bridge->device >=
2530 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_FIRST
2531 && bridge->device <=
2532 PCI_DEVICE_ID_SERVERWORKS_HT2100_PCIE_LAST)
2533 /* All Intel E5000 PCIE ports */
2534 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2535 && bridge->device >=
2536 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2537 && bridge->device <=
2538 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
2539 dev_info(&mgp->pdev->dev,
2540 "Assuming aligned completions (0x%x:0x%x)\n",
2541 bridge->vendor, bridge->device);
2542 mgp->tx.boundary = 4096;
2543 mgp->fw_name = myri10ge_fw_aligned;
2544 } else if (bridge &&
2545 bridge->vendor == PCI_VENDOR_ID_SGI &&
2546 bridge->device == 0x4002 /* TIOCE pcie-port */ ) {
2547 /* this pcie bridge does not support 4K rdma request */
2548 mgp->tx.boundary = 2048;
2549 mgp->fw_name = myri10ge_fw_aligned;
2550 }
2551 } else {
2552 if (myri10ge_force_firmware == 1) {
2553 dev_info(&mgp->pdev->dev,
2554 "Assuming aligned completions (forced)\n");
2555 mgp->tx.boundary = 4096;
2556 mgp->fw_name = myri10ge_fw_aligned;
2557 } else {
2558 dev_info(&mgp->pdev->dev,
2559 "Assuming unaligned completions (forced)\n");
2560 mgp->tx.boundary = 2048;
2561 mgp->fw_name = myri10ge_fw_unaligned;
2562 }
2563 }
2564 if (myri10ge_fw_name != NULL) {
2565 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2566 myri10ge_fw_name);
2567 mgp->fw_name = myri10ge_fw_name;
2568 }
2569 }
2570
2571 #ifdef CONFIG_PM
2572
2573 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2574 {
2575 struct myri10ge_priv *mgp;
2576 struct net_device *netdev;
2577
2578 mgp = pci_get_drvdata(pdev);
2579 if (mgp == NULL)
2580 return -EINVAL;
2581 netdev = mgp->dev;
2582
2583 netif_device_detach(netdev);
2584 if (netif_running(netdev)) {
2585 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2586 rtnl_lock();
2587 myri10ge_close(netdev);
2588 rtnl_unlock();
2589 }
2590 myri10ge_dummy_rdma(mgp, 0);
2591 pci_save_state(pdev);
2592 pci_disable_device(pdev);
2593
2594 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2595 }
2596
2597 static int myri10ge_resume(struct pci_dev *pdev)
2598 {
2599 struct myri10ge_priv *mgp;
2600 struct net_device *netdev;
2601 int status;
2602 u16 vendor;
2603
2604 mgp = pci_get_drvdata(pdev);
2605 if (mgp == NULL)
2606 return -EINVAL;
2607 netdev = mgp->dev;
2608 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2609 msleep(5); /* give card time to respond */
2610 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2611 if (vendor == 0xffff) {
2612 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2613 mgp->dev->name);
2614 return -EIO;
2615 }
2616
2617 status = pci_restore_state(pdev);
2618 if (status)
2619 return status;
2620
2621 status = pci_enable_device(pdev);
2622 if (status) {
2623 dev_err(&pdev->dev, "failed to enable device\n");
2624 return status;
2625 }
2626
2627 pci_set_master(pdev);
2628
2629 myri10ge_reset(mgp);
2630 myri10ge_dummy_rdma(mgp, 1);
2631
2632 /* Save configuration space to be restored if the
2633 * nic resets due to a parity error */
2634 pci_save_state(pdev);
2635
2636 if (netif_running(netdev)) {
2637 rtnl_lock();
2638 status = myri10ge_open(netdev);
2639 rtnl_unlock();
2640 if (status != 0)
2641 goto abort_with_enabled;
2642
2643 }
2644 netif_device_attach(netdev);
2645
2646 return 0;
2647
2648 abort_with_enabled:
2649 pci_disable_device(pdev);
2650 return -EIO;
2651
2652 }
2653
2654 #endif /* CONFIG_PM */
2655
2656 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2657 {
2658 struct pci_dev *pdev = mgp->pdev;
2659 int vs = mgp->vendor_specific_offset;
2660 u32 reboot;
2661
2662 /*enter read32 mode */
2663 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2664
2665 /*read REBOOT_STATUS (0xfffffff0) */
2666 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2667 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2668 return reboot;
2669 }
2670
2671 /*
2672 * This watchdog is used to check whether the board has suffered
2673 * from a parity error and needs to be recovered.
2674 */
2675 static void myri10ge_watchdog(struct work_struct *work)
2676 {
2677 struct myri10ge_priv *mgp =
2678 container_of(work, struct myri10ge_priv, watchdog_work);
2679 u32 reboot;
2680 int status;
2681 u16 cmd, vendor;
2682
2683 mgp->watchdog_resets++;
2684 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2685 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2686 /* Bus master DMA disabled? Check to see
2687 * if the card rebooted due to a parity error
2688 * For now, just report it */
2689 reboot = myri10ge_read_reboot(mgp);
2690 printk(KERN_ERR
2691 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2692 mgp->dev->name, reboot);
2693 /*
2694 * A rebooted nic will come back with config space as
2695 * it was after power was applied to PCIe bus.
2696 * Attempt to restore config space which was saved
2697 * when the driver was loaded, or the last time the
2698 * nic was resumed from power saving mode.
2699 */
2700 pci_restore_state(mgp->pdev);
2701
2702 /* save state again for accounting reasons */
2703 pci_save_state(mgp->pdev);
2704
2705 } else {
2706 /* if we get back -1's from our slot, perhaps somebody
2707 * powered off our card. Don't try to reset it in
2708 * this case */
2709 if (cmd == 0xffff) {
2710 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2711 if (vendor == 0xffff) {
2712 printk(KERN_ERR
2713 "myri10ge: %s: device disappeared!\n",
2714 mgp->dev->name);
2715 return;
2716 }
2717 }
2718 /* Perhaps it is a software error. Try to reset */
2719
2720 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2721 mgp->dev->name);
2722 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2723 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2724 mgp->tx.pkt_start, mgp->tx.pkt_done,
2725 (int)ntohl(mgp->fw_stats->send_done_count));
2726 msleep(2000);
2727 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2728 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2729 mgp->tx.pkt_start, mgp->tx.pkt_done,
2730 (int)ntohl(mgp->fw_stats->send_done_count));
2731 }
2732 rtnl_lock();
2733 myri10ge_close(mgp->dev);
2734 status = myri10ge_load_firmware(mgp);
2735 if (status != 0)
2736 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2737 mgp->dev->name);
2738 else
2739 myri10ge_open(mgp->dev);
2740 rtnl_unlock();
2741 }
2742
2743 /*
2744 * We use our own timer routine rather than relying upon
2745 * netdev->tx_timeout because we have a very large hardware transmit
2746 * queue. Due to the large queue, the netdev->tx_timeout function
2747 * cannot detect a NIC with a parity error in a timely fashion if the
2748 * NIC is lightly loaded.
2749 */
2750 static void myri10ge_watchdog_timer(unsigned long arg)
2751 {
2752 struct myri10ge_priv *mgp;
2753
2754 mgp = (struct myri10ge_priv *)arg;
2755
2756 if (mgp->rx_small.watchdog_needed) {
2757 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2758 mgp->small_bytes + MXGEFW_PAD, 1);
2759 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2760 myri10ge_fill_thresh)
2761 mgp->rx_small.watchdog_needed = 0;
2762 }
2763 if (mgp->rx_big.watchdog_needed) {
2764 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2765 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2766 myri10ge_fill_thresh)
2767 mgp->rx_big.watchdog_needed = 0;
2768 }
2769
2770 if (mgp->tx.req != mgp->tx.done &&
2771 mgp->tx.done == mgp->watchdog_tx_done &&
2772 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2773 /* nic seems like it might be stuck.. */
2774 schedule_work(&mgp->watchdog_work);
2775 else
2776 /* rearm timer */
2777 mod_timer(&mgp->watchdog_timer,
2778 jiffies + myri10ge_watchdog_timeout * HZ);
2779
2780 mgp->watchdog_tx_done = mgp->tx.done;
2781 mgp->watchdog_tx_req = mgp->tx.req;
2782 }
2783
2784 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2785 {
2786 struct net_device *netdev;
2787 struct myri10ge_priv *mgp;
2788 struct device *dev = &pdev->dev;
2789 size_t bytes;
2790 int i;
2791 int status = -ENXIO;
2792 int cap;
2793 int dac_enabled;
2794 u16 val;
2795
2796 netdev = alloc_etherdev(sizeof(*mgp));
2797 if (netdev == NULL) {
2798 dev_err(dev, "Could not allocate ethernet device\n");
2799 return -ENOMEM;
2800 }
2801
2802 mgp = netdev_priv(netdev);
2803 memset(mgp, 0, sizeof(*mgp));
2804 mgp->dev = netdev;
2805 mgp->pdev = pdev;
2806 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2807 mgp->pause = myri10ge_flow_control;
2808 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2809 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2810 init_waitqueue_head(&mgp->down_wq);
2811
2812 if (pci_enable_device(pdev)) {
2813 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2814 status = -ENODEV;
2815 goto abort_with_netdev;
2816 }
2817 myri10ge_select_firmware(mgp);
2818
2819 /* Find the vendor-specific cap so we can check
2820 * the reboot register later on */
2821 mgp->vendor_specific_offset
2822 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2823
2824 /* Set our max read request to 4KB */
2825 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2826 if (cap < 64) {
2827 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2828 goto abort_with_netdev;
2829 }
2830 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2831 if (status != 0) {
2832 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2833 status);
2834 goto abort_with_netdev;
2835 }
2836 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2837 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2838 if (status != 0) {
2839 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2840 status);
2841 goto abort_with_netdev;
2842 }
2843
2844 pci_set_master(pdev);
2845 dac_enabled = 1;
2846 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2847 if (status != 0) {
2848 dac_enabled = 0;
2849 dev_err(&pdev->dev,
2850 "64-bit pci address mask was refused, trying 32-bit");
2851 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2852 }
2853 if (status != 0) {
2854 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2855 goto abort_with_netdev;
2856 }
2857 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2858 &mgp->cmd_bus, GFP_KERNEL);
2859 if (mgp->cmd == NULL)
2860 goto abort_with_netdev;
2861
2862 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2863 &mgp->fw_stats_bus, GFP_KERNEL);
2864 if (mgp->fw_stats == NULL)
2865 goto abort_with_cmd;
2866
2867 mgp->board_span = pci_resource_len(pdev, 0);
2868 mgp->iomem_base = pci_resource_start(pdev, 0);
2869 mgp->mtrr = -1;
2870 mgp->wc_enabled = 0;
2871 #ifdef CONFIG_MTRR
2872 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2873 MTRR_TYPE_WRCOMB, 1);
2874 if (mgp->mtrr >= 0)
2875 mgp->wc_enabled = 1;
2876 #endif
2877 /* Hack. need to get rid of these magic numbers */
2878 mgp->sram_size =
2879 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2880 if (mgp->sram_size > mgp->board_span) {
2881 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2882 mgp->board_span);
2883 goto abort_with_wc;
2884 }
2885 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2886 if (mgp->sram == NULL) {
2887 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2888 mgp->board_span, mgp->iomem_base);
2889 status = -ENXIO;
2890 goto abort_with_wc;
2891 }
2892 memcpy_fromio(mgp->eeprom_strings,
2893 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2894 MYRI10GE_EEPROM_STRINGS_SIZE);
2895 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2896 status = myri10ge_read_mac_addr(mgp);
2897 if (status)
2898 goto abort_with_ioremap;
2899
2900 for (i = 0; i < ETH_ALEN; i++)
2901 netdev->dev_addr[i] = mgp->mac_addr[i];
2902
2903 /* allocate rx done ring */
2904 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2905 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2906 &mgp->rx_done.bus, GFP_KERNEL);
2907 if (mgp->rx_done.entry == NULL)
2908 goto abort_with_ioremap;
2909 memset(mgp->rx_done.entry, 0, bytes);
2910
2911 status = myri10ge_load_firmware(mgp);
2912 if (status != 0) {
2913 dev_err(&pdev->dev, "failed to load firmware\n");
2914 goto abort_with_rx_done;
2915 }
2916
2917 status = myri10ge_reset(mgp);
2918 if (status != 0) {
2919 dev_err(&pdev->dev, "failed reset\n");
2920 goto abort_with_firmware;
2921 }
2922
2923 pci_set_drvdata(pdev, mgp);
2924 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2925 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2926 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2927 myri10ge_initial_mtu = 68;
2928 netdev->mtu = myri10ge_initial_mtu;
2929 netdev->open = myri10ge_open;
2930 netdev->stop = myri10ge_close;
2931 netdev->hard_start_xmit = myri10ge_xmit;
2932 netdev->get_stats = myri10ge_get_stats;
2933 netdev->base_addr = mgp->iomem_base;
2934 netdev->change_mtu = myri10ge_change_mtu;
2935 netdev->set_multicast_list = myri10ge_set_multicast_list;
2936 netdev->set_mac_address = myri10ge_set_mac_address;
2937 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2938 if (dac_enabled)
2939 netdev->features |= NETIF_F_HIGHDMA;
2940 netdev->poll = myri10ge_poll;
2941 netdev->weight = myri10ge_napi_weight;
2942
2943 /* make sure we can get an irq, and that MSI can be
2944 * setup (if available). Also ensure netdev->irq
2945 * is set to correct value if MSI is enabled */
2946 status = myri10ge_request_irq(mgp);
2947 if (status != 0)
2948 goto abort_with_firmware;
2949 netdev->irq = pdev->irq;
2950 myri10ge_free_irq(mgp);
2951
2952 /* Save configuration space to be restored if the
2953 * nic resets due to a parity error */
2954 pci_save_state(pdev);
2955
2956 /* Setup the watchdog timer */
2957 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2958 (unsigned long)mgp);
2959
2960 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2961 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
2962 status = register_netdev(netdev);
2963 if (status != 0) {
2964 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2965 goto abort_with_state;
2966 }
2967 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2968 (mgp->msi_enabled ? "MSI" : "xPIC"),
2969 netdev->irq, mgp->tx.boundary, mgp->fw_name,
2970 (mgp->wc_enabled ? "Enabled" : "Disabled"));
2971
2972 return 0;
2973
2974 abort_with_state:
2975 pci_restore_state(pdev);
2976
2977 abort_with_firmware:
2978 myri10ge_dummy_rdma(mgp, 0);
2979
2980 abort_with_rx_done:
2981 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2982 dma_free_coherent(&pdev->dev, bytes,
2983 mgp->rx_done.entry, mgp->rx_done.bus);
2984
2985 abort_with_ioremap:
2986 iounmap(mgp->sram);
2987
2988 abort_with_wc:
2989 #ifdef CONFIG_MTRR
2990 if (mgp->mtrr >= 0)
2991 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2992 #endif
2993 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2994 mgp->fw_stats, mgp->fw_stats_bus);
2995
2996 abort_with_cmd:
2997 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2998 mgp->cmd, mgp->cmd_bus);
2999
3000 abort_with_netdev:
3001
3002 free_netdev(netdev);
3003 return status;
3004 }
3005
3006 /*
3007 * myri10ge_remove
3008 *
3009 * Does what is necessary to shutdown one Myrinet device. Called
3010 * once for each Myrinet card by the kernel when a module is
3011 * unloaded.
3012 */
3013 static void myri10ge_remove(struct pci_dev *pdev)
3014 {
3015 struct myri10ge_priv *mgp;
3016 struct net_device *netdev;
3017 size_t bytes;
3018
3019 mgp = pci_get_drvdata(pdev);
3020 if (mgp == NULL)
3021 return;
3022
3023 flush_scheduled_work();
3024 netdev = mgp->dev;
3025 unregister_netdev(netdev);
3026
3027 myri10ge_dummy_rdma(mgp, 0);
3028
3029 /* avoid a memory leak */
3030 pci_restore_state(pdev);
3031
3032 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
3033 dma_free_coherent(&pdev->dev, bytes,
3034 mgp->rx_done.entry, mgp->rx_done.bus);
3035
3036 iounmap(mgp->sram);
3037
3038 #ifdef CONFIG_MTRR
3039 if (mgp->mtrr >= 0)
3040 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3041 #endif
3042 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
3043 mgp->fw_stats, mgp->fw_stats_bus);
3044
3045 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3046 mgp->cmd, mgp->cmd_bus);
3047
3048 free_netdev(netdev);
3049 pci_set_drvdata(pdev, NULL);
3050 }
3051
3052 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3053
3054 static struct pci_device_id myri10ge_pci_tbl[] = {
3055 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3056 {0},
3057 };
3058
3059 static struct pci_driver myri10ge_driver = {
3060 .name = "myri10ge",
3061 .probe = myri10ge_probe,
3062 .remove = myri10ge_remove,
3063 .id_table = myri10ge_pci_tbl,
3064 #ifdef CONFIG_PM
3065 .suspend = myri10ge_suspend,
3066 .resume = myri10ge_resume,
3067 #endif
3068 };
3069
3070 static __init int myri10ge_init_module(void)
3071 {
3072 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3073 MYRI10GE_VERSION_STR);
3074 return pci_register_driver(&myri10ge_driver);
3075 }
3076
3077 module_init(myri10ge_init_module);
3078
3079 static __exit void myri10ge_cleanup_module(void)
3080 {
3081 pci_unregister_driver(&myri10ge_driver);
3082 }
3083
3084 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
This page took 0.095544 seconds and 6 git commands to generate.