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Merge branch 'master' of /home/trondmy/kernel/linux-2.6/
[deliverable/linux.git] / drivers / net / myri10ge / myri10ge.c
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005, 2006 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/ip.h>
52 #include <linux/inet.h>
53 #include <linux/in.h>
54 #include <linux/ethtool.h>
55 #include <linux/firmware.h>
56 #include <linux/delay.h>
57 #include <linux/version.h>
58 #include <linux/timer.h>
59 #include <linux/vmalloc.h>
60 #include <linux/crc32.h>
61 #include <linux/moduleparam.h>
62 #include <linux/io.h>
63 #include <net/checksum.h>
64 #include <asm/byteorder.h>
65 #include <asm/io.h>
66 #include <asm/processor.h>
67 #ifdef CONFIG_MTRR
68 #include <asm/mtrr.h>
69 #endif
70
71 #include "myri10ge_mcp.h"
72 #include "myri10ge_mcp_gen_header.h"
73
74 #define MYRI10GE_VERSION_STR "1.2.0"
75
76 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77 MODULE_AUTHOR("Maintainer: help@myri.com");
78 MODULE_VERSION(MYRI10GE_VERSION_STR);
79 MODULE_LICENSE("Dual BSD/GPL");
80
81 #define MYRI10GE_MAX_ETHER_MTU 9014
82
83 #define MYRI10GE_ETH_STOPPED 0
84 #define MYRI10GE_ETH_STOPPING 1
85 #define MYRI10GE_ETH_STARTING 2
86 #define MYRI10GE_ETH_RUNNING 3
87 #define MYRI10GE_ETH_OPEN_FAILED 4
88
89 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
90 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
91
92 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
93 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
94
95 #define MYRI10GE_ALLOC_ORDER 0
96 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
97 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
98
99 struct myri10ge_rx_buffer_state {
100 struct page *page;
101 int page_offset;
102 DECLARE_PCI_UNMAP_ADDR(bus)
103 DECLARE_PCI_UNMAP_LEN(len)
104 };
105
106 struct myri10ge_tx_buffer_state {
107 struct sk_buff *skb;
108 int last;
109 DECLARE_PCI_UNMAP_ADDR(bus)
110 DECLARE_PCI_UNMAP_LEN(len)
111 };
112
113 struct myri10ge_cmd {
114 u32 data0;
115 u32 data1;
116 u32 data2;
117 };
118
119 struct myri10ge_rx_buf {
120 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
121 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
122 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
123 struct myri10ge_rx_buffer_state *info;
124 struct page *page;
125 dma_addr_t bus;
126 int page_offset;
127 int cnt;
128 int fill_cnt;
129 int alloc_fail;
130 int mask; /* number of rx slots -1 */
131 int watchdog_needed;
132 };
133
134 struct myri10ge_tx_buf {
135 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
136 u8 __iomem *wc_fifo; /* w/c send fifo address */
137 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
138 char *req_bytes;
139 struct myri10ge_tx_buffer_state *info;
140 int mask; /* number of transmit slots -1 */
141 int boundary; /* boundary transmits cannot cross */
142 int req ____cacheline_aligned; /* transmit slots submitted */
143 int pkt_start; /* packets started */
144 int done ____cacheline_aligned; /* transmit slots completed */
145 int pkt_done; /* packets completed */
146 };
147
148 struct myri10ge_rx_done {
149 struct mcp_slot *entry;
150 dma_addr_t bus;
151 int cnt;
152 int idx;
153 };
154
155 struct myri10ge_priv {
156 int running; /* running? */
157 int csum_flag; /* rx_csums? */
158 struct myri10ge_tx_buf tx; /* transmit ring */
159 struct myri10ge_rx_buf rx_small;
160 struct myri10ge_rx_buf rx_big;
161 struct myri10ge_rx_done rx_done;
162 int small_bytes;
163 int big_bytes;
164 struct net_device *dev;
165 struct net_device_stats stats;
166 u8 __iomem *sram;
167 int sram_size;
168 unsigned long board_span;
169 unsigned long iomem_base;
170 __be32 __iomem *irq_claim;
171 __be32 __iomem *irq_deassert;
172 char *mac_addr_string;
173 struct mcp_cmd_response *cmd;
174 dma_addr_t cmd_bus;
175 struct mcp_irq_data *fw_stats;
176 dma_addr_t fw_stats_bus;
177 struct pci_dev *pdev;
178 int msi_enabled;
179 __be32 link_state;
180 unsigned int rdma_tags_available;
181 int intr_coal_delay;
182 __be32 __iomem *intr_coal_delay_ptr;
183 int mtrr;
184 int wake_queue;
185 int stop_queue;
186 int down_cnt;
187 wait_queue_head_t down_wq;
188 struct work_struct watchdog_work;
189 struct timer_list watchdog_timer;
190 int watchdog_tx_done;
191 int watchdog_tx_req;
192 int watchdog_resets;
193 int tx_linearized;
194 int pause;
195 char *fw_name;
196 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
197 char fw_version[128];
198 u8 mac_addr[6]; /* eeprom mac address */
199 unsigned long serial_number;
200 int vendor_specific_offset;
201 int fw_multicast_support;
202 u32 read_dma;
203 u32 write_dma;
204 u32 read_write_dma;
205 u32 link_changes;
206 u32 msg_enable;
207 };
208
209 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
210 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
211
212 static char *myri10ge_fw_name = NULL;
213 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
214 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name\n");
215
216 static int myri10ge_ecrc_enable = 1;
217 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
218 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E\n");
219
220 static int myri10ge_max_intr_slots = 1024;
221 module_param(myri10ge_max_intr_slots, int, S_IRUGO);
222 MODULE_PARM_DESC(myri10ge_max_intr_slots, "Interrupt queue slots\n");
223
224 static int myri10ge_small_bytes = -1; /* -1 == auto */
225 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
226 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets\n");
227
228 static int myri10ge_msi = 1; /* enable msi by default */
229 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
230 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts\n");
231
232 static int myri10ge_intr_coal_delay = 25;
233 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
234 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay\n");
235
236 static int myri10ge_flow_control = 1;
237 module_param(myri10ge_flow_control, int, S_IRUGO);
238 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter\n");
239
240 static int myri10ge_deassert_wait = 1;
241 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
242 MODULE_PARM_DESC(myri10ge_deassert_wait,
243 "Wait when deasserting legacy interrupts\n");
244
245 static int myri10ge_force_firmware = 0;
246 module_param(myri10ge_force_firmware, int, S_IRUGO);
247 MODULE_PARM_DESC(myri10ge_force_firmware,
248 "Force firmware to assume aligned completions\n");
249
250 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
251 module_param(myri10ge_initial_mtu, int, S_IRUGO);
252 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU\n");
253
254 static int myri10ge_napi_weight = 64;
255 module_param(myri10ge_napi_weight, int, S_IRUGO);
256 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight\n");
257
258 static int myri10ge_watchdog_timeout = 1;
259 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
260 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout\n");
261
262 static int myri10ge_max_irq_loops = 1048576;
263 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
264 MODULE_PARM_DESC(myri10ge_max_irq_loops,
265 "Set stuck legacy IRQ detection threshold\n");
266
267 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
268
269 static int myri10ge_debug = -1; /* defaults above */
270 module_param(myri10ge_debug, int, 0);
271 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
272
273 static int myri10ge_fill_thresh = 256;
274 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
275 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
276
277 static int myri10ge_wcfifo = 1;
278 module_param(myri10ge_wcfifo, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
280
281 #define MYRI10GE_FW_OFFSET 1024*1024
282 #define MYRI10GE_HIGHPART_TO_U32(X) \
283 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
284 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
285
286 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
287
288 static inline void put_be32(__be32 val, __be32 __iomem * p)
289 {
290 __raw_writel((__force __u32) val, (__force void __iomem *)p);
291 }
292
293 static int
294 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
295 struct myri10ge_cmd *data, int atomic)
296 {
297 struct mcp_cmd *buf;
298 char buf_bytes[sizeof(*buf) + 8];
299 struct mcp_cmd_response *response = mgp->cmd;
300 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
301 u32 dma_low, dma_high, result, value;
302 int sleep_total = 0;
303
304 /* ensure buf is aligned to 8 bytes */
305 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
306
307 buf->data0 = htonl(data->data0);
308 buf->data1 = htonl(data->data1);
309 buf->data2 = htonl(data->data2);
310 buf->cmd = htonl(cmd);
311 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
312 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
313
314 buf->response_addr.low = htonl(dma_low);
315 buf->response_addr.high = htonl(dma_high);
316 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
317 mb();
318 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
319
320 /* wait up to 15ms. Longest command is the DMA benchmark,
321 * which is capped at 5ms, but runs from a timeout handler
322 * that runs every 7.8ms. So a 15ms timeout leaves us with
323 * a 2.2ms margin
324 */
325 if (atomic) {
326 /* if atomic is set, do not sleep,
327 * and try to get the completion quickly
328 * (1ms will be enough for those commands) */
329 for (sleep_total = 0;
330 sleep_total < 1000
331 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
332 sleep_total += 10)
333 udelay(10);
334 } else {
335 /* use msleep for most command */
336 for (sleep_total = 0;
337 sleep_total < 15
338 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
339 sleep_total++)
340 msleep(1);
341 }
342
343 result = ntohl(response->result);
344 value = ntohl(response->data);
345 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
346 if (result == 0) {
347 data->data0 = value;
348 return 0;
349 } else if (result == MXGEFW_CMD_UNKNOWN) {
350 return -ENOSYS;
351 } else {
352 dev_err(&mgp->pdev->dev,
353 "command %d failed, result = %d\n",
354 cmd, result);
355 return -ENXIO;
356 }
357 }
358
359 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
360 cmd, result);
361 return -EAGAIN;
362 }
363
364 /*
365 * The eeprom strings on the lanaiX have the format
366 * SN=x\0
367 * MAC=x:x:x:x:x:x\0
368 * PT:ddd mmm xx xx:xx:xx xx\0
369 * PV:ddd mmm xx xx:xx:xx xx\0
370 */
371 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
372 {
373 char *ptr, *limit;
374 int i;
375
376 ptr = mgp->eeprom_strings;
377 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
378
379 while (*ptr != '\0' && ptr < limit) {
380 if (memcmp(ptr, "MAC=", 4) == 0) {
381 ptr += 4;
382 mgp->mac_addr_string = ptr;
383 for (i = 0; i < 6; i++) {
384 if ((ptr + 2) > limit)
385 goto abort;
386 mgp->mac_addr[i] =
387 simple_strtoul(ptr, &ptr, 16);
388 ptr += 1;
389 }
390 }
391 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
392 ptr += 3;
393 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
394 }
395 while (ptr < limit && *ptr++) ;
396 }
397
398 return 0;
399
400 abort:
401 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
402 return -ENXIO;
403 }
404
405 /*
406 * Enable or disable periodic RDMAs from the host to make certain
407 * chipsets resend dropped PCIe messages
408 */
409
410 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
411 {
412 char __iomem *submit;
413 __be32 buf[16];
414 u32 dma_low, dma_high;
415 int i;
416
417 /* clear confirmation addr */
418 mgp->cmd->data = 0;
419 mb();
420
421 /* send a rdma command to the PCIe engine, and wait for the
422 * response in the confirmation address. The firmware should
423 * write a -1 there to indicate it is alive and well
424 */
425 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
426 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
427
428 buf[0] = htonl(dma_high); /* confirm addr MSW */
429 buf[1] = htonl(dma_low); /* confirm addr LSW */
430 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
431 buf[3] = htonl(dma_high); /* dummy addr MSW */
432 buf[4] = htonl(dma_low); /* dummy addr LSW */
433 buf[5] = htonl(enable); /* enable? */
434
435 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
436
437 myri10ge_pio_copy(submit, &buf, sizeof(buf));
438 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
439 msleep(1);
440 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
441 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
442 (enable ? "enable" : "disable"));
443 }
444
445 static int
446 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
447 struct mcp_gen_header *hdr)
448 {
449 struct device *dev = &mgp->pdev->dev;
450 int major, minor;
451
452 /* check firmware type */
453 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
454 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
455 return -EINVAL;
456 }
457
458 /* save firmware version for ethtool */
459 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
460
461 sscanf(mgp->fw_version, "%d.%d", &major, &minor);
462
463 if (!(major == MXGEFW_VERSION_MAJOR && minor == MXGEFW_VERSION_MINOR)) {
464 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
465 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
466 MXGEFW_VERSION_MINOR);
467 return -EINVAL;
468 }
469 return 0;
470 }
471
472 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
473 {
474 unsigned crc, reread_crc;
475 const struct firmware *fw;
476 struct device *dev = &mgp->pdev->dev;
477 struct mcp_gen_header *hdr;
478 size_t hdr_offset;
479 int status;
480 unsigned i;
481
482 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
483 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
484 mgp->fw_name);
485 status = -EINVAL;
486 goto abort_with_nothing;
487 }
488
489 /* check size */
490
491 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
492 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
493 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
494 status = -EINVAL;
495 goto abort_with_fw;
496 }
497
498 /* check id */
499 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
500 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
501 dev_err(dev, "Bad firmware file\n");
502 status = -EINVAL;
503 goto abort_with_fw;
504 }
505 hdr = (void *)(fw->data + hdr_offset);
506
507 status = myri10ge_validate_firmware(mgp, hdr);
508 if (status != 0)
509 goto abort_with_fw;
510
511 crc = crc32(~0, fw->data, fw->size);
512 for (i = 0; i < fw->size; i += 256) {
513 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
514 fw->data + i,
515 min(256U, (unsigned)(fw->size - i)));
516 mb();
517 readb(mgp->sram);
518 }
519 /* corruption checking is good for parity recovery and buggy chipset */
520 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
521 reread_crc = crc32(~0, fw->data, fw->size);
522 if (crc != reread_crc) {
523 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
524 (unsigned)fw->size, reread_crc, crc);
525 status = -EIO;
526 goto abort_with_fw;
527 }
528 *size = (u32) fw->size;
529
530 abort_with_fw:
531 release_firmware(fw);
532
533 abort_with_nothing:
534 return status;
535 }
536
537 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
538 {
539 struct mcp_gen_header *hdr;
540 struct device *dev = &mgp->pdev->dev;
541 const size_t bytes = sizeof(struct mcp_gen_header);
542 size_t hdr_offset;
543 int status;
544
545 /* find running firmware header */
546 hdr_offset = ntohl(__raw_readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
547
548 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
549 dev_err(dev, "Running firmware has bad header offset (%d)\n",
550 (int)hdr_offset);
551 return -EIO;
552 }
553
554 /* copy header of running firmware from SRAM to host memory to
555 * validate firmware */
556 hdr = kmalloc(bytes, GFP_KERNEL);
557 if (hdr == NULL) {
558 dev_err(dev, "could not malloc firmware hdr\n");
559 return -ENOMEM;
560 }
561 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
562 status = myri10ge_validate_firmware(mgp, hdr);
563 kfree(hdr);
564 return status;
565 }
566
567 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
568 {
569 char __iomem *submit;
570 __be32 buf[16];
571 u32 dma_low, dma_high, size;
572 int status, i;
573
574 size = 0;
575 status = myri10ge_load_hotplug_firmware(mgp, &size);
576 if (status) {
577 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
578
579 /* Do not attempt to adopt firmware if there
580 * was a bad crc */
581 if (status == -EIO)
582 return status;
583
584 status = myri10ge_adopt_running_firmware(mgp);
585 if (status != 0) {
586 dev_err(&mgp->pdev->dev,
587 "failed to adopt running firmware\n");
588 return status;
589 }
590 dev_info(&mgp->pdev->dev,
591 "Successfully adopted running firmware\n");
592 if (mgp->tx.boundary == 4096) {
593 dev_warn(&mgp->pdev->dev,
594 "Using firmware currently running on NIC"
595 ". For optimal\n");
596 dev_warn(&mgp->pdev->dev,
597 "performance consider loading optimized "
598 "firmware\n");
599 dev_warn(&mgp->pdev->dev, "via hotplug\n");
600 }
601
602 mgp->fw_name = "adopted";
603 mgp->tx.boundary = 2048;
604 return status;
605 }
606
607 /* clear confirmation addr */
608 mgp->cmd->data = 0;
609 mb();
610
611 /* send a reload command to the bootstrap MCP, and wait for the
612 * response in the confirmation address. The firmware should
613 * write a -1 there to indicate it is alive and well
614 */
615 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
616 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
617
618 buf[0] = htonl(dma_high); /* confirm addr MSW */
619 buf[1] = htonl(dma_low); /* confirm addr LSW */
620 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
621
622 /* FIX: All newest firmware should un-protect the bottom of
623 * the sram before handoff. However, the very first interfaces
624 * do not. Therefore the handoff copy must skip the first 8 bytes
625 */
626 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
627 buf[4] = htonl(size - 8); /* length of code */
628 buf[5] = htonl(8); /* where to copy to */
629 buf[6] = htonl(0); /* where to jump to */
630
631 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
632
633 myri10ge_pio_copy(submit, &buf, sizeof(buf));
634 mb();
635 msleep(1);
636 mb();
637 i = 0;
638 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20) {
639 msleep(1);
640 i++;
641 }
642 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
643 dev_err(&mgp->pdev->dev, "handoff failed\n");
644 return -ENXIO;
645 }
646 dev_info(&mgp->pdev->dev, "handoff confirmed\n");
647 myri10ge_dummy_rdma(mgp, 1);
648
649 return 0;
650 }
651
652 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
653 {
654 struct myri10ge_cmd cmd;
655 int status;
656
657 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
658 | (addr[2] << 8) | addr[3]);
659
660 cmd.data1 = ((addr[4] << 8) | (addr[5]));
661
662 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
663 return status;
664 }
665
666 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
667 {
668 struct myri10ge_cmd cmd;
669 int status, ctl;
670
671 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
672 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
673
674 if (status) {
675 printk(KERN_ERR
676 "myri10ge: %s: Failed to set flow control mode\n",
677 mgp->dev->name);
678 return status;
679 }
680 mgp->pause = pause;
681 return 0;
682 }
683
684 static void
685 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
686 {
687 struct myri10ge_cmd cmd;
688 int status, ctl;
689
690 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
691 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
692 if (status)
693 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
694 mgp->dev->name);
695 }
696
697 static int myri10ge_reset(struct myri10ge_priv *mgp)
698 {
699 struct myri10ge_cmd cmd;
700 int status;
701 size_t bytes;
702 u32 len;
703
704 /* try to send a reset command to the card to see if it
705 * is alive */
706 memset(&cmd, 0, sizeof(cmd));
707 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
708 if (status != 0) {
709 dev_err(&mgp->pdev->dev, "failed reset\n");
710 return -ENXIO;
711 }
712
713 /* Now exchange information about interrupts */
714
715 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
716 memset(mgp->rx_done.entry, 0, bytes);
717 cmd.data0 = (u32) bytes;
718 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
719 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
720 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
721 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
722
723 status |=
724 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
725 mgp->irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
726 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
727 &cmd, 0);
728 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
729
730 status |= myri10ge_send_cmd
731 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
732 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
733 if (status != 0) {
734 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
735 return status;
736 }
737 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
738
739 /* Run a small DMA test.
740 * The magic multipliers to the length tell the firmware
741 * to do DMA read, write, or read+write tests. The
742 * results are returned in cmd.data0. The upper 16
743 * bits or the return is the number of transfers completed.
744 * The lower 16 bits is the time in 0.5us ticks that the
745 * transfers took to complete.
746 */
747
748 len = mgp->tx.boundary;
749
750 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
751 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
752 cmd.data2 = len * 0x10000;
753 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
754 if (status == 0)
755 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) /
756 (cmd.data0 & 0xffff);
757 else
758 dev_warn(&mgp->pdev->dev, "DMA read benchmark failed: %d\n",
759 status);
760 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
761 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
762 cmd.data2 = len * 0x1;
763 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
764 if (status == 0)
765 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) /
766 (cmd.data0 & 0xffff);
767 else
768 dev_warn(&mgp->pdev->dev, "DMA write benchmark failed: %d\n",
769 status);
770
771 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->rx_done.bus);
772 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->rx_done.bus);
773 cmd.data2 = len * 0x10001;
774 status = myri10ge_send_cmd(mgp, MXGEFW_DMA_TEST, &cmd, 0);
775 if (status == 0)
776 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
777 (cmd.data0 & 0xffff);
778 else
779 dev_warn(&mgp->pdev->dev,
780 "DMA read/write benchmark failed: %d\n", status);
781
782 memset(mgp->rx_done.entry, 0, bytes);
783
784 /* reset mcp/driver shared state back to 0 */
785 mgp->tx.req = 0;
786 mgp->tx.done = 0;
787 mgp->tx.pkt_start = 0;
788 mgp->tx.pkt_done = 0;
789 mgp->rx_big.cnt = 0;
790 mgp->rx_small.cnt = 0;
791 mgp->rx_done.idx = 0;
792 mgp->rx_done.cnt = 0;
793 mgp->link_changes = 0;
794 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
795 myri10ge_change_promisc(mgp, 0, 0);
796 myri10ge_change_pause(mgp, mgp->pause);
797 return status;
798 }
799
800 static inline void
801 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
802 struct mcp_kreq_ether_recv *src)
803 {
804 __be32 low;
805
806 low = src->addr_low;
807 src->addr_low = htonl(DMA_32BIT_MASK);
808 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
809 mb();
810 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
811 mb();
812 src->addr_low = low;
813 put_be32(low, &dst->addr_low);
814 mb();
815 }
816
817 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
818 {
819 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
820
821 if ((skb->protocol == htons(ETH_P_8021Q)) &&
822 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
823 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
824 skb->csum = hw_csum;
825 skb->ip_summed = CHECKSUM_COMPLETE;
826 }
827 }
828
829 static inline void
830 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
831 struct skb_frag_struct *rx_frags, int len, int hlen)
832 {
833 struct skb_frag_struct *skb_frags;
834
835 skb->len = skb->data_len = len;
836 skb->truesize = len + sizeof(struct sk_buff);
837 /* attach the page(s) */
838
839 skb_frags = skb_shinfo(skb)->frags;
840 while (len > 0) {
841 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
842 len -= rx_frags->size;
843 skb_frags++;
844 rx_frags++;
845 skb_shinfo(skb)->nr_frags++;
846 }
847
848 /* pskb_may_pull is not available in irq context, but
849 * skb_pull() (for ether_pad and eth_type_trans()) requires
850 * the beginning of the packet in skb_headlen(), move it
851 * manually */
852 memcpy(skb->data, va, hlen);
853 skb_shinfo(skb)->frags[0].page_offset += hlen;
854 skb_shinfo(skb)->frags[0].size -= hlen;
855 skb->data_len -= hlen;
856 skb->tail += hlen;
857 skb_pull(skb, MXGEFW_PAD);
858 }
859
860 static void
861 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
862 int bytes, int watchdog)
863 {
864 struct page *page;
865 int idx;
866
867 if (unlikely(rx->watchdog_needed && !watchdog))
868 return;
869
870 /* try to refill entire ring */
871 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
872 idx = rx->fill_cnt & rx->mask;
873
874 if ((bytes < MYRI10GE_ALLOC_SIZE / 2) &&
875 (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE)) {
876 /* we can use part of previous page */
877 get_page(rx->page);
878 } else {
879 /* we need a new page */
880 page =
881 alloc_pages(GFP_ATOMIC | __GFP_COMP,
882 MYRI10GE_ALLOC_ORDER);
883 if (unlikely(page == NULL)) {
884 if (rx->fill_cnt - rx->cnt < 16)
885 rx->watchdog_needed = 1;
886 return;
887 }
888 rx->page = page;
889 rx->page_offset = 0;
890 rx->bus = pci_map_page(mgp->pdev, page, 0,
891 MYRI10GE_ALLOC_SIZE,
892 PCI_DMA_FROMDEVICE);
893 }
894 rx->info[idx].page = rx->page;
895 rx->info[idx].page_offset = rx->page_offset;
896 /* note that this is the address of the start of the
897 * page */
898 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
899 rx->shadow[idx].addr_low =
900 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
901 rx->shadow[idx].addr_high =
902 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
903
904 /* start next packet on a cacheline boundary */
905 rx->page_offset += SKB_DATA_ALIGN(bytes);
906 rx->fill_cnt++;
907
908 /* copy 8 descriptors to the firmware at a time */
909 if ((idx & 7) == 7) {
910 if (rx->wc_fifo == NULL)
911 myri10ge_submit_8rx(&rx->lanai[idx - 7],
912 &rx->shadow[idx - 7]);
913 else {
914 mb();
915 myri10ge_pio_copy(rx->wc_fifo,
916 &rx->shadow[idx - 7], 64);
917 }
918 }
919 }
920 }
921
922 static inline void
923 myri10ge_unmap_rx_page(struct pci_dev *pdev,
924 struct myri10ge_rx_buffer_state *info, int bytes)
925 {
926 /* unmap the recvd page if we're the only or last user of it */
927 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
928 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
929 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
930 & ~(MYRI10GE_ALLOC_SIZE - 1)),
931 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
932 }
933 }
934
935 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
936 * page into an skb */
937
938 static inline int
939 myri10ge_rx_done(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
940 int bytes, int len, __wsum csum)
941 {
942 struct sk_buff *skb;
943 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
944 int i, idx, hlen, remainder;
945 struct pci_dev *pdev = mgp->pdev;
946 struct net_device *dev = mgp->dev;
947 u8 *va;
948
949 len += MXGEFW_PAD;
950 idx = rx->cnt & rx->mask;
951 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
952 prefetch(va);
953 /* Fill skb_frag_struct(s) with data from our receive */
954 for (i = 0, remainder = len; remainder > 0; i++) {
955 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
956 rx_frags[i].page = rx->info[idx].page;
957 rx_frags[i].page_offset = rx->info[idx].page_offset;
958 if (remainder < MYRI10GE_ALLOC_SIZE)
959 rx_frags[i].size = remainder;
960 else
961 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
962 rx->cnt++;
963 idx = rx->cnt & rx->mask;
964 remainder -= MYRI10GE_ALLOC_SIZE;
965 }
966
967 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
968
969 /* allocate an skb to attach the page(s) to. */
970
971 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
972 if (unlikely(skb == NULL)) {
973 mgp->stats.rx_dropped++;
974 do {
975 i--;
976 put_page(rx_frags[i].page);
977 } while (i != 0);
978 return 0;
979 }
980
981 /* Attach the pages to the skb, and trim off any padding */
982 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
983 if (skb_shinfo(skb)->frags[0].size <= 0) {
984 put_page(skb_shinfo(skb)->frags[0].page);
985 skb_shinfo(skb)->nr_frags = 0;
986 }
987 skb->protocol = eth_type_trans(skb, dev);
988 skb->dev = dev;
989
990 if (mgp->csum_flag) {
991 if ((skb->protocol == htons(ETH_P_IP)) ||
992 (skb->protocol == htons(ETH_P_IPV6))) {
993 skb->csum = csum;
994 skb->ip_summed = CHECKSUM_COMPLETE;
995 } else
996 myri10ge_vlan_ip_csum(skb, csum);
997 }
998 netif_receive_skb(skb);
999 dev->last_rx = jiffies;
1000 return 1;
1001 }
1002
1003 static inline void myri10ge_tx_done(struct myri10ge_priv *mgp, int mcp_index)
1004 {
1005 struct pci_dev *pdev = mgp->pdev;
1006 struct myri10ge_tx_buf *tx = &mgp->tx;
1007 struct sk_buff *skb;
1008 int idx, len;
1009 int limit = 0;
1010
1011 while (tx->pkt_done != mcp_index) {
1012 idx = tx->done & tx->mask;
1013 skb = tx->info[idx].skb;
1014
1015 /* Mark as free */
1016 tx->info[idx].skb = NULL;
1017 if (tx->info[idx].last) {
1018 tx->pkt_done++;
1019 tx->info[idx].last = 0;
1020 }
1021 tx->done++;
1022 len = pci_unmap_len(&tx->info[idx], len);
1023 pci_unmap_len_set(&tx->info[idx], len, 0);
1024 if (skb) {
1025 mgp->stats.tx_bytes += skb->len;
1026 mgp->stats.tx_packets++;
1027 dev_kfree_skb_irq(skb);
1028 if (len)
1029 pci_unmap_single(pdev,
1030 pci_unmap_addr(&tx->info[idx],
1031 bus), len,
1032 PCI_DMA_TODEVICE);
1033 } else {
1034 if (len)
1035 pci_unmap_page(pdev,
1036 pci_unmap_addr(&tx->info[idx],
1037 bus), len,
1038 PCI_DMA_TODEVICE);
1039 }
1040
1041 /* limit potential for livelock by only handling
1042 * 2 full tx rings per call */
1043 if (unlikely(++limit > 2 * tx->mask))
1044 break;
1045 }
1046 /* start the queue if we've stopped it */
1047 if (netif_queue_stopped(mgp->dev)
1048 && tx->req - tx->done < (tx->mask >> 1)) {
1049 mgp->wake_queue++;
1050 netif_wake_queue(mgp->dev);
1051 }
1052 }
1053
1054 static inline void myri10ge_clean_rx_done(struct myri10ge_priv *mgp, int *limit)
1055 {
1056 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1057 unsigned long rx_bytes = 0;
1058 unsigned long rx_packets = 0;
1059 unsigned long rx_ok;
1060
1061 int idx = rx_done->idx;
1062 int cnt = rx_done->cnt;
1063 u16 length;
1064 __wsum checksum;
1065
1066 while (rx_done->entry[idx].length != 0 && *limit != 0) {
1067 length = ntohs(rx_done->entry[idx].length);
1068 rx_done->entry[idx].length = 0;
1069 checksum = csum_unfold(rx_done->entry[idx].checksum);
1070 if (length <= mgp->small_bytes)
1071 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_small,
1072 mgp->small_bytes,
1073 length, checksum);
1074 else
1075 rx_ok = myri10ge_rx_done(mgp, &mgp->rx_big,
1076 mgp->big_bytes,
1077 length, checksum);
1078 rx_packets += rx_ok;
1079 rx_bytes += rx_ok * (unsigned long)length;
1080 cnt++;
1081 idx = cnt & (myri10ge_max_intr_slots - 1);
1082
1083 /* limit potential for livelock by only handling a
1084 * limited number of frames. */
1085 (*limit)--;
1086 }
1087 rx_done->idx = idx;
1088 rx_done->cnt = cnt;
1089 mgp->stats.rx_packets += rx_packets;
1090 mgp->stats.rx_bytes += rx_bytes;
1091
1092 /* restock receive rings if needed */
1093 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt < myri10ge_fill_thresh)
1094 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1095 mgp->small_bytes + MXGEFW_PAD, 0);
1096 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt < myri10ge_fill_thresh)
1097 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1098
1099 }
1100
1101 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1102 {
1103 struct mcp_irq_data *stats = mgp->fw_stats;
1104
1105 if (unlikely(stats->stats_updated)) {
1106 if (mgp->link_state != stats->link_up) {
1107 mgp->link_state = stats->link_up;
1108 if (mgp->link_state) {
1109 if (netif_msg_link(mgp))
1110 printk(KERN_INFO
1111 "myri10ge: %s: link up\n",
1112 mgp->dev->name);
1113 netif_carrier_on(mgp->dev);
1114 mgp->link_changes++;
1115 } else {
1116 if (netif_msg_link(mgp))
1117 printk(KERN_INFO
1118 "myri10ge: %s: link down\n",
1119 mgp->dev->name);
1120 netif_carrier_off(mgp->dev);
1121 mgp->link_changes++;
1122 }
1123 }
1124 if (mgp->rdma_tags_available !=
1125 ntohl(mgp->fw_stats->rdma_tags_available)) {
1126 mgp->rdma_tags_available =
1127 ntohl(mgp->fw_stats->rdma_tags_available);
1128 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1129 "%d tags left\n", mgp->dev->name,
1130 mgp->rdma_tags_available);
1131 }
1132 mgp->down_cnt += stats->link_down;
1133 if (stats->link_down)
1134 wake_up(&mgp->down_wq);
1135 }
1136 }
1137
1138 static int myri10ge_poll(struct net_device *netdev, int *budget)
1139 {
1140 struct myri10ge_priv *mgp = netdev_priv(netdev);
1141 struct myri10ge_rx_done *rx_done = &mgp->rx_done;
1142 int limit, orig_limit, work_done;
1143
1144 /* process as many rx events as NAPI will allow */
1145 limit = min(*budget, netdev->quota);
1146 orig_limit = limit;
1147 myri10ge_clean_rx_done(mgp, &limit);
1148 work_done = orig_limit - limit;
1149 *budget -= work_done;
1150 netdev->quota -= work_done;
1151
1152 if (rx_done->entry[rx_done->idx].length == 0 || !netif_running(netdev)) {
1153 netif_rx_complete(netdev);
1154 put_be32(htonl(3), mgp->irq_claim);
1155 return 0;
1156 }
1157 return 1;
1158 }
1159
1160 static irqreturn_t myri10ge_intr(int irq, void *arg)
1161 {
1162 struct myri10ge_priv *mgp = arg;
1163 struct mcp_irq_data *stats = mgp->fw_stats;
1164 struct myri10ge_tx_buf *tx = &mgp->tx;
1165 u32 send_done_count;
1166 int i;
1167
1168 /* make sure it is our IRQ, and that the DMA has finished */
1169 if (unlikely(!stats->valid))
1170 return (IRQ_NONE);
1171
1172 /* low bit indicates receives are present, so schedule
1173 * napi poll handler */
1174 if (stats->valid & 1)
1175 netif_rx_schedule(mgp->dev);
1176
1177 if (!mgp->msi_enabled) {
1178 put_be32(0, mgp->irq_deassert);
1179 if (!myri10ge_deassert_wait)
1180 stats->valid = 0;
1181 mb();
1182 } else
1183 stats->valid = 0;
1184
1185 /* Wait for IRQ line to go low, if using INTx */
1186 i = 0;
1187 while (1) {
1188 i++;
1189 /* check for transmit completes and receives */
1190 send_done_count = ntohl(stats->send_done_count);
1191 if (send_done_count != tx->pkt_done)
1192 myri10ge_tx_done(mgp, (int)send_done_count);
1193 if (unlikely(i > myri10ge_max_irq_loops)) {
1194 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1195 mgp->dev->name);
1196 stats->valid = 0;
1197 schedule_work(&mgp->watchdog_work);
1198 }
1199 if (likely(stats->valid == 0))
1200 break;
1201 cpu_relax();
1202 barrier();
1203 }
1204
1205 myri10ge_check_statblock(mgp);
1206
1207 put_be32(htonl(3), mgp->irq_claim + 1);
1208 return (IRQ_HANDLED);
1209 }
1210
1211 static int
1212 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1213 {
1214 cmd->autoneg = AUTONEG_DISABLE;
1215 cmd->speed = SPEED_10000;
1216 cmd->duplex = DUPLEX_FULL;
1217 return 0;
1218 }
1219
1220 static void
1221 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1222 {
1223 struct myri10ge_priv *mgp = netdev_priv(netdev);
1224
1225 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1226 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1227 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1228 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1229 }
1230
1231 static int
1232 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1233 {
1234 struct myri10ge_priv *mgp = netdev_priv(netdev);
1235 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1236 return 0;
1237 }
1238
1239 static int
1240 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1241 {
1242 struct myri10ge_priv *mgp = netdev_priv(netdev);
1243
1244 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1245 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1246 return 0;
1247 }
1248
1249 static void
1250 myri10ge_get_pauseparam(struct net_device *netdev,
1251 struct ethtool_pauseparam *pause)
1252 {
1253 struct myri10ge_priv *mgp = netdev_priv(netdev);
1254
1255 pause->autoneg = 0;
1256 pause->rx_pause = mgp->pause;
1257 pause->tx_pause = mgp->pause;
1258 }
1259
1260 static int
1261 myri10ge_set_pauseparam(struct net_device *netdev,
1262 struct ethtool_pauseparam *pause)
1263 {
1264 struct myri10ge_priv *mgp = netdev_priv(netdev);
1265
1266 if (pause->tx_pause != mgp->pause)
1267 return myri10ge_change_pause(mgp, pause->tx_pause);
1268 if (pause->rx_pause != mgp->pause)
1269 return myri10ge_change_pause(mgp, pause->tx_pause);
1270 if (pause->autoneg != 0)
1271 return -EINVAL;
1272 return 0;
1273 }
1274
1275 static void
1276 myri10ge_get_ringparam(struct net_device *netdev,
1277 struct ethtool_ringparam *ring)
1278 {
1279 struct myri10ge_priv *mgp = netdev_priv(netdev);
1280
1281 ring->rx_mini_max_pending = mgp->rx_small.mask + 1;
1282 ring->rx_max_pending = mgp->rx_big.mask + 1;
1283 ring->rx_jumbo_max_pending = 0;
1284 ring->tx_max_pending = mgp->rx_small.mask + 1;
1285 ring->rx_mini_pending = ring->rx_mini_max_pending;
1286 ring->rx_pending = ring->rx_max_pending;
1287 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1288 ring->tx_pending = ring->tx_max_pending;
1289 }
1290
1291 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1292 {
1293 struct myri10ge_priv *mgp = netdev_priv(netdev);
1294 if (mgp->csum_flag)
1295 return 1;
1296 else
1297 return 0;
1298 }
1299
1300 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1301 {
1302 struct myri10ge_priv *mgp = netdev_priv(netdev);
1303 if (csum_enabled)
1304 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1305 else
1306 mgp->csum_flag = 0;
1307 return 0;
1308 }
1309
1310 static const char myri10ge_gstrings_stats[][ETH_GSTRING_LEN] = {
1311 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1312 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1313 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1314 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1315 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1316 "tx_heartbeat_errors", "tx_window_errors",
1317 /* device-specific stats */
1318 "tx_boundary", "WC", "irq", "MSI",
1319 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1320 "serial_number", "tx_pkt_start", "tx_pkt_done",
1321 "tx_req", "tx_done", "rx_small_cnt", "rx_big_cnt",
1322 "wake_queue", "stop_queue", "watchdog_resets", "tx_linearized",
1323 "link_changes", "link_up", "dropped_link_overflow",
1324 "dropped_link_error_or_filtered", "dropped_multicast_filtered",
1325 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1326 "dropped_no_big_buffer"
1327 };
1328
1329 #define MYRI10GE_NET_STATS_LEN 21
1330 #define MYRI10GE_STATS_LEN sizeof(myri10ge_gstrings_stats) / ETH_GSTRING_LEN
1331
1332 static void
1333 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1334 {
1335 switch (stringset) {
1336 case ETH_SS_STATS:
1337 memcpy(data, *myri10ge_gstrings_stats,
1338 sizeof(myri10ge_gstrings_stats));
1339 break;
1340 }
1341 }
1342
1343 static int myri10ge_get_stats_count(struct net_device *netdev)
1344 {
1345 return MYRI10GE_STATS_LEN;
1346 }
1347
1348 static void
1349 myri10ge_get_ethtool_stats(struct net_device *netdev,
1350 struct ethtool_stats *stats, u64 * data)
1351 {
1352 struct myri10ge_priv *mgp = netdev_priv(netdev);
1353 int i;
1354
1355 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1356 data[i] = ((unsigned long *)&mgp->stats)[i];
1357
1358 data[i++] = (unsigned int)mgp->tx.boundary;
1359 data[i++] = (unsigned int)(mgp->mtrr >= 0);
1360 data[i++] = (unsigned int)mgp->pdev->irq;
1361 data[i++] = (unsigned int)mgp->msi_enabled;
1362 data[i++] = (unsigned int)mgp->read_dma;
1363 data[i++] = (unsigned int)mgp->write_dma;
1364 data[i++] = (unsigned int)mgp->read_write_dma;
1365 data[i++] = (unsigned int)mgp->serial_number;
1366 data[i++] = (unsigned int)mgp->tx.pkt_start;
1367 data[i++] = (unsigned int)mgp->tx.pkt_done;
1368 data[i++] = (unsigned int)mgp->tx.req;
1369 data[i++] = (unsigned int)mgp->tx.done;
1370 data[i++] = (unsigned int)mgp->rx_small.cnt;
1371 data[i++] = (unsigned int)mgp->rx_big.cnt;
1372 data[i++] = (unsigned int)mgp->wake_queue;
1373 data[i++] = (unsigned int)mgp->stop_queue;
1374 data[i++] = (unsigned int)mgp->watchdog_resets;
1375 data[i++] = (unsigned int)mgp->tx_linearized;
1376 data[i++] = (unsigned int)mgp->link_changes;
1377 data[i++] = (unsigned int)ntohl(mgp->fw_stats->link_up);
1378 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_link_overflow);
1379 data[i++] =
1380 (unsigned int)ntohl(mgp->fw_stats->dropped_link_error_or_filtered);
1381 data[i++] =
1382 (unsigned int)ntohl(mgp->fw_stats->dropped_multicast_filtered);
1383 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_runt);
1384 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_overrun);
1385 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_small_buffer);
1386 data[i++] = (unsigned int)ntohl(mgp->fw_stats->dropped_no_big_buffer);
1387 }
1388
1389 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1390 {
1391 struct myri10ge_priv *mgp = netdev_priv(netdev);
1392 mgp->msg_enable = value;
1393 }
1394
1395 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1396 {
1397 struct myri10ge_priv *mgp = netdev_priv(netdev);
1398 return mgp->msg_enable;
1399 }
1400
1401 static const struct ethtool_ops myri10ge_ethtool_ops = {
1402 .get_settings = myri10ge_get_settings,
1403 .get_drvinfo = myri10ge_get_drvinfo,
1404 .get_coalesce = myri10ge_get_coalesce,
1405 .set_coalesce = myri10ge_set_coalesce,
1406 .get_pauseparam = myri10ge_get_pauseparam,
1407 .set_pauseparam = myri10ge_set_pauseparam,
1408 .get_ringparam = myri10ge_get_ringparam,
1409 .get_rx_csum = myri10ge_get_rx_csum,
1410 .set_rx_csum = myri10ge_set_rx_csum,
1411 .get_tx_csum = ethtool_op_get_tx_csum,
1412 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1413 .get_sg = ethtool_op_get_sg,
1414 .set_sg = ethtool_op_set_sg,
1415 .get_tso = ethtool_op_get_tso,
1416 .set_tso = ethtool_op_set_tso,
1417 .get_strings = myri10ge_get_strings,
1418 .get_stats_count = myri10ge_get_stats_count,
1419 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1420 .set_msglevel = myri10ge_set_msglevel,
1421 .get_msglevel = myri10ge_get_msglevel
1422 };
1423
1424 static int myri10ge_allocate_rings(struct net_device *dev)
1425 {
1426 struct myri10ge_priv *mgp;
1427 struct myri10ge_cmd cmd;
1428 int tx_ring_size, rx_ring_size;
1429 int tx_ring_entries, rx_ring_entries;
1430 int i, status;
1431 size_t bytes;
1432
1433 mgp = netdev_priv(dev);
1434
1435 /* get ring sizes */
1436
1437 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1438 tx_ring_size = cmd.data0;
1439 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1440 rx_ring_size = cmd.data0;
1441
1442 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1443 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1444 mgp->tx.mask = tx_ring_entries - 1;
1445 mgp->rx_small.mask = mgp->rx_big.mask = rx_ring_entries - 1;
1446
1447 /* allocate the host shadow rings */
1448
1449 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1450 * sizeof(*mgp->tx.req_list);
1451 mgp->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1452 if (mgp->tx.req_bytes == NULL)
1453 goto abort_with_nothing;
1454
1455 /* ensure req_list entries are aligned to 8 bytes */
1456 mgp->tx.req_list = (struct mcp_kreq_ether_send *)
1457 ALIGN((unsigned long)mgp->tx.req_bytes, 8);
1458
1459 bytes = rx_ring_entries * sizeof(*mgp->rx_small.shadow);
1460 mgp->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1461 if (mgp->rx_small.shadow == NULL)
1462 goto abort_with_tx_req_bytes;
1463
1464 bytes = rx_ring_entries * sizeof(*mgp->rx_big.shadow);
1465 mgp->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1466 if (mgp->rx_big.shadow == NULL)
1467 goto abort_with_rx_small_shadow;
1468
1469 /* allocate the host info rings */
1470
1471 bytes = tx_ring_entries * sizeof(*mgp->tx.info);
1472 mgp->tx.info = kzalloc(bytes, GFP_KERNEL);
1473 if (mgp->tx.info == NULL)
1474 goto abort_with_rx_big_shadow;
1475
1476 bytes = rx_ring_entries * sizeof(*mgp->rx_small.info);
1477 mgp->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1478 if (mgp->rx_small.info == NULL)
1479 goto abort_with_tx_info;
1480
1481 bytes = rx_ring_entries * sizeof(*mgp->rx_big.info);
1482 mgp->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1483 if (mgp->rx_big.info == NULL)
1484 goto abort_with_rx_small_info;
1485
1486 /* Fill the receive rings */
1487 mgp->rx_big.cnt = 0;
1488 mgp->rx_small.cnt = 0;
1489 mgp->rx_big.fill_cnt = 0;
1490 mgp->rx_small.fill_cnt = 0;
1491 mgp->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1492 mgp->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1493 mgp->rx_small.watchdog_needed = 0;
1494 mgp->rx_big.watchdog_needed = 0;
1495 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
1496 mgp->small_bytes + MXGEFW_PAD, 0);
1497
1498 if (mgp->rx_small.fill_cnt < mgp->rx_small.mask + 1) {
1499 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1500 dev->name, mgp->rx_small.fill_cnt);
1501 goto abort_with_rx_small_ring;
1502 }
1503
1504 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 0);
1505 if (mgp->rx_big.fill_cnt < mgp->rx_big.mask + 1) {
1506 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1507 dev->name, mgp->rx_big.fill_cnt);
1508 goto abort_with_rx_big_ring;
1509 }
1510
1511 return 0;
1512
1513 abort_with_rx_big_ring:
1514 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1515 int idx = i & mgp->rx_big.mask;
1516 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1517 mgp->big_bytes);
1518 put_page(mgp->rx_big.info[idx].page);
1519 }
1520
1521 abort_with_rx_small_ring:
1522 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1523 int idx = i & mgp->rx_small.mask;
1524 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1525 mgp->small_bytes + MXGEFW_PAD);
1526 put_page(mgp->rx_small.info[idx].page);
1527 }
1528
1529 kfree(mgp->rx_big.info);
1530
1531 abort_with_rx_small_info:
1532 kfree(mgp->rx_small.info);
1533
1534 abort_with_tx_info:
1535 kfree(mgp->tx.info);
1536
1537 abort_with_rx_big_shadow:
1538 kfree(mgp->rx_big.shadow);
1539
1540 abort_with_rx_small_shadow:
1541 kfree(mgp->rx_small.shadow);
1542
1543 abort_with_tx_req_bytes:
1544 kfree(mgp->tx.req_bytes);
1545 mgp->tx.req_bytes = NULL;
1546 mgp->tx.req_list = NULL;
1547
1548 abort_with_nothing:
1549 return status;
1550 }
1551
1552 static void myri10ge_free_rings(struct net_device *dev)
1553 {
1554 struct myri10ge_priv *mgp;
1555 struct sk_buff *skb;
1556 struct myri10ge_tx_buf *tx;
1557 int i, len, idx;
1558
1559 mgp = netdev_priv(dev);
1560
1561 for (i = mgp->rx_big.cnt; i < mgp->rx_big.fill_cnt; i++) {
1562 idx = i & mgp->rx_big.mask;
1563 if (i == mgp->rx_big.fill_cnt - 1)
1564 mgp->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1565 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_big.info[idx],
1566 mgp->big_bytes);
1567 put_page(mgp->rx_big.info[idx].page);
1568 }
1569
1570 for (i = mgp->rx_small.cnt; i < mgp->rx_small.fill_cnt; i++) {
1571 idx = i & mgp->rx_small.mask;
1572 if (i == mgp->rx_small.fill_cnt - 1)
1573 mgp->rx_small.info[idx].page_offset =
1574 MYRI10GE_ALLOC_SIZE;
1575 myri10ge_unmap_rx_page(mgp->pdev, &mgp->rx_small.info[idx],
1576 mgp->small_bytes + MXGEFW_PAD);
1577 put_page(mgp->rx_small.info[idx].page);
1578 }
1579 tx = &mgp->tx;
1580 while (tx->done != tx->req) {
1581 idx = tx->done & tx->mask;
1582 skb = tx->info[idx].skb;
1583
1584 /* Mark as free */
1585 tx->info[idx].skb = NULL;
1586 tx->done++;
1587 len = pci_unmap_len(&tx->info[idx], len);
1588 pci_unmap_len_set(&tx->info[idx], len, 0);
1589 if (skb) {
1590 mgp->stats.tx_dropped++;
1591 dev_kfree_skb_any(skb);
1592 if (len)
1593 pci_unmap_single(mgp->pdev,
1594 pci_unmap_addr(&tx->info[idx],
1595 bus), len,
1596 PCI_DMA_TODEVICE);
1597 } else {
1598 if (len)
1599 pci_unmap_page(mgp->pdev,
1600 pci_unmap_addr(&tx->info[idx],
1601 bus), len,
1602 PCI_DMA_TODEVICE);
1603 }
1604 }
1605 kfree(mgp->rx_big.info);
1606
1607 kfree(mgp->rx_small.info);
1608
1609 kfree(mgp->tx.info);
1610
1611 kfree(mgp->rx_big.shadow);
1612
1613 kfree(mgp->rx_small.shadow);
1614
1615 kfree(mgp->tx.req_bytes);
1616 mgp->tx.req_bytes = NULL;
1617 mgp->tx.req_list = NULL;
1618 }
1619
1620 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1621 {
1622 struct pci_dev *pdev = mgp->pdev;
1623 int status;
1624
1625 if (myri10ge_msi) {
1626 status = pci_enable_msi(pdev);
1627 if (status != 0)
1628 dev_err(&pdev->dev,
1629 "Error %d setting up MSI; falling back to xPIC\n",
1630 status);
1631 else
1632 mgp->msi_enabled = 1;
1633 } else {
1634 mgp->msi_enabled = 0;
1635 }
1636 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1637 mgp->dev->name, mgp);
1638 if (status != 0) {
1639 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1640 if (mgp->msi_enabled)
1641 pci_disable_msi(pdev);
1642 }
1643 return status;
1644 }
1645
1646 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1647 {
1648 struct pci_dev *pdev = mgp->pdev;
1649
1650 free_irq(pdev->irq, mgp);
1651 if (mgp->msi_enabled)
1652 pci_disable_msi(pdev);
1653 }
1654
1655 static int myri10ge_open(struct net_device *dev)
1656 {
1657 struct myri10ge_priv *mgp;
1658 struct myri10ge_cmd cmd;
1659 int status, big_pow2;
1660
1661 mgp = netdev_priv(dev);
1662
1663 if (mgp->running != MYRI10GE_ETH_STOPPED)
1664 return -EBUSY;
1665
1666 mgp->running = MYRI10GE_ETH_STARTING;
1667 status = myri10ge_reset(mgp);
1668 if (status != 0) {
1669 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1670 goto abort_with_nothing;
1671 }
1672
1673 status = myri10ge_request_irq(mgp);
1674 if (status != 0)
1675 goto abort_with_nothing;
1676
1677 /* decide what small buffer size to use. For good TCP rx
1678 * performance, it is important to not receive 1514 byte
1679 * frames into jumbo buffers, as it confuses the socket buffer
1680 * accounting code, leading to drops and erratic performance.
1681 */
1682
1683 if (dev->mtu <= ETH_DATA_LEN)
1684 /* enough for a TCP header */
1685 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1686 ? (128 - MXGEFW_PAD)
1687 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1688 else
1689 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1690 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1691
1692 /* Override the small buffer size? */
1693 if (myri10ge_small_bytes > 0)
1694 mgp->small_bytes = myri10ge_small_bytes;
1695
1696 /* get the lanai pointers to the send and receive rings */
1697
1698 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1699 mgp->tx.lanai =
1700 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1701
1702 status |=
1703 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1704 mgp->rx_small.lanai =
1705 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1706
1707 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1708 mgp->rx_big.lanai =
1709 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1710
1711 if (status != 0) {
1712 printk(KERN_ERR
1713 "myri10ge: %s: failed to get ring sizes or locations\n",
1714 dev->name);
1715 mgp->running = MYRI10GE_ETH_STOPPED;
1716 goto abort_with_irq;
1717 }
1718
1719 if (myri10ge_wcfifo && mgp->mtrr >= 0) {
1720 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1721 mgp->rx_small.wc_fifo =
1722 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1723 mgp->rx_big.wc_fifo =
1724 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
1725 } else {
1726 mgp->tx.wc_fifo = NULL;
1727 mgp->rx_small.wc_fifo = NULL;
1728 mgp->rx_big.wc_fifo = NULL;
1729 }
1730
1731 /* Firmware needs the big buff size as a power of 2. Lie and
1732 * tell him the buffer is larger, because we only use 1
1733 * buffer/pkt, and the mtu will prevent overruns.
1734 */
1735 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1736 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
1737 while ((big_pow2 & (big_pow2 - 1)) != 0)
1738 big_pow2++;
1739 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
1740 } else {
1741 big_pow2 = MYRI10GE_ALLOC_SIZE;
1742 mgp->big_bytes = big_pow2;
1743 }
1744
1745 status = myri10ge_allocate_rings(dev);
1746 if (status != 0)
1747 goto abort_with_irq;
1748
1749 /* now give firmware buffers sizes, and MTU */
1750 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
1751 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
1752 cmd.data0 = mgp->small_bytes;
1753 status |=
1754 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
1755 cmd.data0 = big_pow2;
1756 status |=
1757 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
1758 if (status) {
1759 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
1760 dev->name);
1761 goto abort_with_rings;
1762 }
1763
1764 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->fw_stats_bus);
1765 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->fw_stats_bus);
1766 cmd.data2 = sizeof(struct mcp_irq_data);
1767 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
1768 if (status == -ENOSYS) {
1769 dma_addr_t bus = mgp->fw_stats_bus;
1770 bus += offsetof(struct mcp_irq_data, send_done_count);
1771 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
1772 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
1773 status = myri10ge_send_cmd(mgp,
1774 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
1775 &cmd, 0);
1776 /* Firmware cannot support multicast without STATS_DMA_V2 */
1777 mgp->fw_multicast_support = 0;
1778 } else {
1779 mgp->fw_multicast_support = 1;
1780 }
1781 if (status) {
1782 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
1783 dev->name);
1784 goto abort_with_rings;
1785 }
1786
1787 mgp->link_state = htonl(~0U);
1788 mgp->rdma_tags_available = 15;
1789
1790 netif_poll_enable(mgp->dev); /* must happen prior to any irq */
1791
1792 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
1793 if (status) {
1794 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
1795 dev->name);
1796 goto abort_with_rings;
1797 }
1798
1799 mgp->wake_queue = 0;
1800 mgp->stop_queue = 0;
1801 mgp->running = MYRI10GE_ETH_RUNNING;
1802 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
1803 add_timer(&mgp->watchdog_timer);
1804 netif_wake_queue(dev);
1805 return 0;
1806
1807 abort_with_rings:
1808 myri10ge_free_rings(dev);
1809
1810 abort_with_irq:
1811 myri10ge_free_irq(mgp);
1812
1813 abort_with_nothing:
1814 mgp->running = MYRI10GE_ETH_STOPPED;
1815 return -ENOMEM;
1816 }
1817
1818 static int myri10ge_close(struct net_device *dev)
1819 {
1820 struct myri10ge_priv *mgp;
1821 struct myri10ge_cmd cmd;
1822 int status, old_down_cnt;
1823
1824 mgp = netdev_priv(dev);
1825
1826 if (mgp->running != MYRI10GE_ETH_RUNNING)
1827 return 0;
1828
1829 if (mgp->tx.req_bytes == NULL)
1830 return 0;
1831
1832 del_timer_sync(&mgp->watchdog_timer);
1833 mgp->running = MYRI10GE_ETH_STOPPING;
1834 netif_poll_disable(mgp->dev);
1835 netif_carrier_off(dev);
1836 netif_stop_queue(dev);
1837 old_down_cnt = mgp->down_cnt;
1838 mb();
1839 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
1840 if (status)
1841 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
1842 dev->name);
1843
1844 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
1845 if (old_down_cnt == mgp->down_cnt)
1846 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
1847
1848 netif_tx_disable(dev);
1849 myri10ge_free_irq(mgp);
1850 myri10ge_free_rings(dev);
1851
1852 mgp->running = MYRI10GE_ETH_STOPPED;
1853 return 0;
1854 }
1855
1856 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1857 * backwards one at a time and handle ring wraps */
1858
1859 static inline void
1860 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
1861 struct mcp_kreq_ether_send *src, int cnt)
1862 {
1863 int idx, starting_slot;
1864 starting_slot = tx->req;
1865 while (cnt > 1) {
1866 cnt--;
1867 idx = (starting_slot + cnt) & tx->mask;
1868 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
1869 mb();
1870 }
1871 }
1872
1873 /*
1874 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
1875 * at most 32 bytes at a time, so as to avoid involving the software
1876 * pio handler in the nic. We re-write the first segment's flags
1877 * to mark them valid only after writing the entire chain.
1878 */
1879
1880 static inline void
1881 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
1882 int cnt)
1883 {
1884 int idx, i;
1885 struct mcp_kreq_ether_send __iomem *dstp, *dst;
1886 struct mcp_kreq_ether_send *srcp;
1887 u8 last_flags;
1888
1889 idx = tx->req & tx->mask;
1890
1891 last_flags = src->flags;
1892 src->flags = 0;
1893 mb();
1894 dst = dstp = &tx->lanai[idx];
1895 srcp = src;
1896
1897 if ((idx + cnt) < tx->mask) {
1898 for (i = 0; i < (cnt - 1); i += 2) {
1899 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
1900 mb(); /* force write every 32 bytes */
1901 srcp += 2;
1902 dstp += 2;
1903 }
1904 } else {
1905 /* submit all but the first request, and ensure
1906 * that it is submitted below */
1907 myri10ge_submit_req_backwards(tx, src, cnt);
1908 i = 0;
1909 }
1910 if (i < cnt) {
1911 /* submit the first request */
1912 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
1913 mb(); /* barrier before setting valid flag */
1914 }
1915
1916 /* re-write the last 32-bits with the valid flags */
1917 src->flags = last_flags;
1918 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
1919 tx->req += cnt;
1920 mb();
1921 }
1922
1923 static inline void
1924 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
1925 struct mcp_kreq_ether_send *src, int cnt)
1926 {
1927 tx->req += cnt;
1928 mb();
1929 while (cnt >= 4) {
1930 myri10ge_pio_copy(tx->wc_fifo, src, 64);
1931 mb();
1932 src += 4;
1933 cnt -= 4;
1934 }
1935 if (cnt > 0) {
1936 /* pad it to 64 bytes. The src is 64 bytes bigger than it
1937 * needs to be so that we don't overrun it */
1938 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
1939 src, 64);
1940 mb();
1941 }
1942 }
1943
1944 /*
1945 * Transmit a packet. We need to split the packet so that a single
1946 * segment does not cross myri10ge->tx.boundary, so this makes segment
1947 * counting tricky. So rather than try to count segments up front, we
1948 * just give up if there are too few segments to hold a reasonably
1949 * fragmented packet currently available. If we run
1950 * out of segments while preparing a packet for DMA, we just linearize
1951 * it and try again.
1952 */
1953
1954 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
1955 {
1956 struct myri10ge_priv *mgp = netdev_priv(dev);
1957 struct mcp_kreq_ether_send *req;
1958 struct myri10ge_tx_buf *tx = &mgp->tx;
1959 struct skb_frag_struct *frag;
1960 dma_addr_t bus;
1961 u32 low;
1962 __be32 high_swapped;
1963 unsigned int len;
1964 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
1965 u16 pseudo_hdr_offset, cksum_offset;
1966 int cum_len, seglen, boundary, rdma_count;
1967 u8 flags, odd_flag;
1968
1969 again:
1970 req = tx->req_list;
1971 avail = tx->mask - 1 - (tx->req - tx->done);
1972
1973 mss = 0;
1974 max_segments = MXGEFW_MAX_SEND_DESC;
1975
1976 if (skb->len > (dev->mtu + ETH_HLEN)) {
1977 mss = skb_shinfo(skb)->gso_size;
1978 if (mss != 0)
1979 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
1980 }
1981
1982 if ((unlikely(avail < max_segments))) {
1983 /* we are out of transmit resources */
1984 mgp->stop_queue++;
1985 netif_stop_queue(dev);
1986 return 1;
1987 }
1988
1989 /* Setup checksum offloading, if needed */
1990 cksum_offset = 0;
1991 pseudo_hdr_offset = 0;
1992 odd_flag = 0;
1993 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
1994 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
1995 cksum_offset = (skb->h.raw - skb->data);
1996 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
1997 /* If the headers are excessively large, then we must
1998 * fall back to a software checksum */
1999 if (unlikely(cksum_offset > 255 || pseudo_hdr_offset > 127)) {
2000 if (skb_checksum_help(skb))
2001 goto drop;
2002 cksum_offset = 0;
2003 pseudo_hdr_offset = 0;
2004 } else {
2005 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2006 flags |= MXGEFW_FLAGS_CKSUM;
2007 }
2008 }
2009
2010 cum_len = 0;
2011
2012 if (mss) { /* TSO */
2013 /* this removes any CKSUM flag from before */
2014 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2015
2016 /* negative cum_len signifies to the
2017 * send loop that we are still in the
2018 * header portion of the TSO packet.
2019 * TSO header must be at most 134 bytes long */
2020 cum_len = -((skb->h.raw - skb->data) + (skb->h.th->doff << 2));
2021
2022 /* for TSO, pseudo_hdr_offset holds mss.
2023 * The firmware figures out where to put
2024 * the checksum by parsing the header. */
2025 pseudo_hdr_offset = mss;
2026 } else
2027 /* Mark small packets, and pad out tiny packets */
2028 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2029 flags |= MXGEFW_FLAGS_SMALL;
2030
2031 /* pad frames to at least ETH_ZLEN bytes */
2032 if (unlikely(skb->len < ETH_ZLEN)) {
2033 if (skb_padto(skb, ETH_ZLEN)) {
2034 /* The packet is gone, so we must
2035 * return 0 */
2036 mgp->stats.tx_dropped += 1;
2037 return 0;
2038 }
2039 /* adjust the len to account for the zero pad
2040 * so that the nic can know how long it is */
2041 skb->len = ETH_ZLEN;
2042 }
2043 }
2044
2045 /* map the skb for DMA */
2046 len = skb->len - skb->data_len;
2047 idx = tx->req & tx->mask;
2048 tx->info[idx].skb = skb;
2049 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2050 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2051 pci_unmap_len_set(&tx->info[idx], len, len);
2052
2053 frag_cnt = skb_shinfo(skb)->nr_frags;
2054 frag_idx = 0;
2055 count = 0;
2056 rdma_count = 0;
2057
2058 /* "rdma_count" is the number of RDMAs belonging to the
2059 * current packet BEFORE the current send request. For
2060 * non-TSO packets, this is equal to "count".
2061 * For TSO packets, rdma_count needs to be reset
2062 * to 0 after a segment cut.
2063 *
2064 * The rdma_count field of the send request is
2065 * the number of RDMAs of the packet starting at
2066 * that request. For TSO send requests with one ore more cuts
2067 * in the middle, this is the number of RDMAs starting
2068 * after the last cut in the request. All previous
2069 * segments before the last cut implicitly have 1 RDMA.
2070 *
2071 * Since the number of RDMAs is not known beforehand,
2072 * it must be filled-in retroactively - after each
2073 * segmentation cut or at the end of the entire packet.
2074 */
2075
2076 while (1) {
2077 /* Break the SKB or Fragment up into pieces which
2078 * do not cross mgp->tx.boundary */
2079 low = MYRI10GE_LOWPART_TO_U32(bus);
2080 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2081 while (len) {
2082 u8 flags_next;
2083 int cum_len_next;
2084
2085 if (unlikely(count == max_segments))
2086 goto abort_linearize;
2087
2088 boundary = (low + tx->boundary) & ~(tx->boundary - 1);
2089 seglen = boundary - low;
2090 if (seglen > len)
2091 seglen = len;
2092 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2093 cum_len_next = cum_len + seglen;
2094 if (mss) { /* TSO */
2095 (req - rdma_count)->rdma_count = rdma_count + 1;
2096
2097 if (likely(cum_len >= 0)) { /* payload */
2098 int next_is_first, chop;
2099
2100 chop = (cum_len_next > mss);
2101 cum_len_next = cum_len_next % mss;
2102 next_is_first = (cum_len_next == 0);
2103 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2104 flags_next |= next_is_first *
2105 MXGEFW_FLAGS_FIRST;
2106 rdma_count |= -(chop | next_is_first);
2107 rdma_count += chop & !next_is_first;
2108 } else if (likely(cum_len_next >= 0)) { /* header ends */
2109 int small;
2110
2111 rdma_count = -1;
2112 cum_len_next = 0;
2113 seglen = -cum_len;
2114 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2115 flags_next = MXGEFW_FLAGS_TSO_PLD |
2116 MXGEFW_FLAGS_FIRST |
2117 (small * MXGEFW_FLAGS_SMALL);
2118 }
2119 }
2120 req->addr_high = high_swapped;
2121 req->addr_low = htonl(low);
2122 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2123 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2124 req->rdma_count = 1;
2125 req->length = htons(seglen);
2126 req->cksum_offset = cksum_offset;
2127 req->flags = flags | ((cum_len & 1) * odd_flag);
2128
2129 low += seglen;
2130 len -= seglen;
2131 cum_len = cum_len_next;
2132 flags = flags_next;
2133 req++;
2134 count++;
2135 rdma_count++;
2136 if (unlikely(cksum_offset > seglen))
2137 cksum_offset -= seglen;
2138 else
2139 cksum_offset = 0;
2140 }
2141 if (frag_idx == frag_cnt)
2142 break;
2143
2144 /* map next fragment for DMA */
2145 idx = (count + tx->req) & tx->mask;
2146 frag = &skb_shinfo(skb)->frags[frag_idx];
2147 frag_idx++;
2148 len = frag->size;
2149 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2150 len, PCI_DMA_TODEVICE);
2151 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2152 pci_unmap_len_set(&tx->info[idx], len, len);
2153 }
2154
2155 (req - rdma_count)->rdma_count = rdma_count;
2156 if (mss)
2157 do {
2158 req--;
2159 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2160 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2161 MXGEFW_FLAGS_FIRST)));
2162 idx = ((count - 1) + tx->req) & tx->mask;
2163 tx->info[idx].last = 1;
2164 if (tx->wc_fifo == NULL)
2165 myri10ge_submit_req(tx, tx->req_list, count);
2166 else
2167 myri10ge_submit_req_wc(tx, tx->req_list, count);
2168 tx->pkt_start++;
2169 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2170 mgp->stop_queue++;
2171 netif_stop_queue(dev);
2172 }
2173 dev->trans_start = jiffies;
2174 return 0;
2175
2176 abort_linearize:
2177 /* Free any DMA resources we've alloced and clear out the skb
2178 * slot so as to not trip up assertions, and to avoid a
2179 * double-free if linearizing fails */
2180
2181 last_idx = (idx + 1) & tx->mask;
2182 idx = tx->req & tx->mask;
2183 tx->info[idx].skb = NULL;
2184 do {
2185 len = pci_unmap_len(&tx->info[idx], len);
2186 if (len) {
2187 if (tx->info[idx].skb != NULL)
2188 pci_unmap_single(mgp->pdev,
2189 pci_unmap_addr(&tx->info[idx],
2190 bus), len,
2191 PCI_DMA_TODEVICE);
2192 else
2193 pci_unmap_page(mgp->pdev,
2194 pci_unmap_addr(&tx->info[idx],
2195 bus), len,
2196 PCI_DMA_TODEVICE);
2197 pci_unmap_len_set(&tx->info[idx], len, 0);
2198 tx->info[idx].skb = NULL;
2199 }
2200 idx = (idx + 1) & tx->mask;
2201 } while (idx != last_idx);
2202 if (skb_is_gso(skb)) {
2203 printk(KERN_ERR
2204 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2205 mgp->dev->name);
2206 goto drop;
2207 }
2208
2209 if (skb_linearize(skb))
2210 goto drop;
2211
2212 mgp->tx_linearized++;
2213 goto again;
2214
2215 drop:
2216 dev_kfree_skb_any(skb);
2217 mgp->stats.tx_dropped += 1;
2218 return 0;
2219
2220 }
2221
2222 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2223 {
2224 struct myri10ge_priv *mgp = netdev_priv(dev);
2225 return &mgp->stats;
2226 }
2227
2228 static void myri10ge_set_multicast_list(struct net_device *dev)
2229 {
2230 struct myri10ge_cmd cmd;
2231 struct myri10ge_priv *mgp;
2232 struct dev_mc_list *mc_list;
2233 __be32 data[2] = { 0, 0 };
2234 int err;
2235
2236 mgp = netdev_priv(dev);
2237 /* can be called from atomic contexts,
2238 * pass 1 to force atomicity in myri10ge_send_cmd() */
2239 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2240
2241 /* This firmware is known to not support multicast */
2242 if (!mgp->fw_multicast_support)
2243 return;
2244
2245 /* Disable multicast filtering */
2246
2247 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2248 if (err != 0) {
2249 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2250 " error status: %d\n", dev->name, err);
2251 goto abort;
2252 }
2253
2254 if (dev->flags & IFF_ALLMULTI) {
2255 /* request to disable multicast filtering, so quit here */
2256 return;
2257 }
2258
2259 /* Flush the filters */
2260
2261 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2262 &cmd, 1);
2263 if (err != 0) {
2264 printk(KERN_ERR
2265 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2266 ", error status: %d\n", dev->name, err);
2267 goto abort;
2268 }
2269
2270 /* Walk the multicast list, and add each address */
2271 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2272 memcpy(data, &mc_list->dmi_addr, 6);
2273 cmd.data0 = ntohl(data[0]);
2274 cmd.data1 = ntohl(data[1]);
2275 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2276 &cmd, 1);
2277
2278 if (err != 0) {
2279 printk(KERN_ERR "myri10ge: %s: Failed "
2280 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2281 "%d\t", dev->name, err);
2282 printk(KERN_ERR "MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
2283 ((unsigned char *)&mc_list->dmi_addr)[0],
2284 ((unsigned char *)&mc_list->dmi_addr)[1],
2285 ((unsigned char *)&mc_list->dmi_addr)[2],
2286 ((unsigned char *)&mc_list->dmi_addr)[3],
2287 ((unsigned char *)&mc_list->dmi_addr)[4],
2288 ((unsigned char *)&mc_list->dmi_addr)[5]
2289 );
2290 goto abort;
2291 }
2292 }
2293 /* Enable multicast filtering */
2294 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2295 if (err != 0) {
2296 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2297 "error status: %d\n", dev->name, err);
2298 goto abort;
2299 }
2300
2301 return;
2302
2303 abort:
2304 return;
2305 }
2306
2307 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2308 {
2309 struct sockaddr *sa = addr;
2310 struct myri10ge_priv *mgp = netdev_priv(dev);
2311 int status;
2312
2313 if (!is_valid_ether_addr(sa->sa_data))
2314 return -EADDRNOTAVAIL;
2315
2316 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2317 if (status != 0) {
2318 printk(KERN_ERR
2319 "myri10ge: %s: changing mac address failed with %d\n",
2320 dev->name, status);
2321 return status;
2322 }
2323
2324 /* change the dev structure */
2325 memcpy(dev->dev_addr, sa->sa_data, 6);
2326 return 0;
2327 }
2328
2329 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2330 {
2331 struct myri10ge_priv *mgp = netdev_priv(dev);
2332 int error = 0;
2333
2334 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2335 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2336 dev->name, new_mtu);
2337 return -EINVAL;
2338 }
2339 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2340 dev->name, dev->mtu, new_mtu);
2341 if (mgp->running) {
2342 /* if we change the mtu on an active device, we must
2343 * reset the device so the firmware sees the change */
2344 myri10ge_close(dev);
2345 dev->mtu = new_mtu;
2346 myri10ge_open(dev);
2347 } else
2348 dev->mtu = new_mtu;
2349
2350 return error;
2351 }
2352
2353 /*
2354 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2355 * Only do it if the bridge is a root port since we don't want to disturb
2356 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2357 */
2358
2359 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2360 {
2361 struct pci_dev *bridge = mgp->pdev->bus->self;
2362 struct device *dev = &mgp->pdev->dev;
2363 unsigned cap;
2364 unsigned err_cap;
2365 u16 val;
2366 u8 ext_type;
2367 int ret;
2368
2369 if (!myri10ge_ecrc_enable || !bridge)
2370 return;
2371
2372 /* check that the bridge is a root port */
2373 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2374 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2375 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2376 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2377 if (myri10ge_ecrc_enable > 1) {
2378 struct pci_dev *old_bridge = bridge;
2379
2380 /* Walk the hierarchy up to the root port
2381 * where ECRC has to be enabled */
2382 do {
2383 bridge = bridge->bus->self;
2384 if (!bridge) {
2385 dev_err(dev,
2386 "Failed to find root port"
2387 " to force ECRC\n");
2388 return;
2389 }
2390 cap =
2391 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2392 pci_read_config_word(bridge,
2393 cap + PCI_CAP_FLAGS, &val);
2394 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2395 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2396
2397 dev_info(dev,
2398 "Forcing ECRC on non-root port %s"
2399 " (enabling on root port %s)\n",
2400 pci_name(old_bridge), pci_name(bridge));
2401 } else {
2402 dev_err(dev,
2403 "Not enabling ECRC on non-root port %s\n",
2404 pci_name(bridge));
2405 return;
2406 }
2407 }
2408
2409 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2410 if (!cap)
2411 return;
2412
2413 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2414 if (ret) {
2415 dev_err(dev, "failed reading ext-conf-space of %s\n",
2416 pci_name(bridge));
2417 dev_err(dev, "\t pci=nommconf in use? "
2418 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2419 return;
2420 }
2421 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2422 return;
2423
2424 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2425 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2426 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2427 mgp->tx.boundary = 4096;
2428 mgp->fw_name = myri10ge_fw_aligned;
2429 }
2430
2431 /*
2432 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2433 * when the PCI-E Completion packets are aligned on an 8-byte
2434 * boundary. Some PCI-E chip sets always align Completion packets; on
2435 * the ones that do not, the alignment can be enforced by enabling
2436 * ECRC generation (if supported).
2437 *
2438 * When PCI-E Completion packets are not aligned, it is actually more
2439 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2440 *
2441 * If the driver can neither enable ECRC nor verify that it has
2442 * already been enabled, then it must use a firmware image which works
2443 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2444 * should also ensure that it never gives the device a Read-DMA which is
2445 * larger than 2KB by setting the tx.boundary to 2KB. If ECRC is
2446 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2447 * firmware image, and set tx.boundary to 4KB.
2448 */
2449
2450 #define PCI_DEVICE_ID_INTEL_E5000_PCIE23 0x25f7
2451 #define PCI_DEVICE_ID_INTEL_E5000_PCIE47 0x25fa
2452
2453 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2454 {
2455 struct pci_dev *bridge = mgp->pdev->bus->self;
2456
2457 mgp->tx.boundary = 2048;
2458 mgp->fw_name = myri10ge_fw_unaligned;
2459
2460 if (myri10ge_force_firmware == 0) {
2461 int link_width, exp_cap;
2462 u16 lnk;
2463
2464 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2465 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2466 link_width = (lnk >> 4) & 0x3f;
2467
2468 myri10ge_enable_ecrc(mgp);
2469
2470 /* Check to see if Link is less than 8 or if the
2471 * upstream bridge is known to provide aligned
2472 * completions */
2473 if (link_width < 8) {
2474 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2475 link_width);
2476 mgp->tx.boundary = 4096;
2477 mgp->fw_name = myri10ge_fw_aligned;
2478 } else if (bridge &&
2479 /* ServerWorks HT2000/HT1000 */
2480 ((bridge->vendor == PCI_VENDOR_ID_SERVERWORKS
2481 && bridge->device ==
2482 PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE)
2483 /* All Intel E5000 PCIE ports */
2484 || (bridge->vendor == PCI_VENDOR_ID_INTEL
2485 && bridge->device >=
2486 PCI_DEVICE_ID_INTEL_E5000_PCIE23
2487 && bridge->device <=
2488 PCI_DEVICE_ID_INTEL_E5000_PCIE47))) {
2489 dev_info(&mgp->pdev->dev,
2490 "Assuming aligned completions (0x%x:0x%x)\n",
2491 bridge->vendor, bridge->device);
2492 mgp->tx.boundary = 4096;
2493 mgp->fw_name = myri10ge_fw_aligned;
2494 }
2495 } else {
2496 if (myri10ge_force_firmware == 1) {
2497 dev_info(&mgp->pdev->dev,
2498 "Assuming aligned completions (forced)\n");
2499 mgp->tx.boundary = 4096;
2500 mgp->fw_name = myri10ge_fw_aligned;
2501 } else {
2502 dev_info(&mgp->pdev->dev,
2503 "Assuming unaligned completions (forced)\n");
2504 mgp->tx.boundary = 2048;
2505 mgp->fw_name = myri10ge_fw_unaligned;
2506 }
2507 }
2508 if (myri10ge_fw_name != NULL) {
2509 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2510 myri10ge_fw_name);
2511 mgp->fw_name = myri10ge_fw_name;
2512 }
2513 }
2514
2515 #ifdef CONFIG_PM
2516
2517 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2518 {
2519 struct myri10ge_priv *mgp;
2520 struct net_device *netdev;
2521
2522 mgp = pci_get_drvdata(pdev);
2523 if (mgp == NULL)
2524 return -EINVAL;
2525 netdev = mgp->dev;
2526
2527 netif_device_detach(netdev);
2528 if (netif_running(netdev)) {
2529 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2530 rtnl_lock();
2531 myri10ge_close(netdev);
2532 rtnl_unlock();
2533 }
2534 myri10ge_dummy_rdma(mgp, 0);
2535 pci_save_state(pdev);
2536 pci_disable_device(pdev);
2537
2538 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2539 }
2540
2541 static int myri10ge_resume(struct pci_dev *pdev)
2542 {
2543 struct myri10ge_priv *mgp;
2544 struct net_device *netdev;
2545 int status;
2546 u16 vendor;
2547
2548 mgp = pci_get_drvdata(pdev);
2549 if (mgp == NULL)
2550 return -EINVAL;
2551 netdev = mgp->dev;
2552 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2553 msleep(5); /* give card time to respond */
2554 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2555 if (vendor == 0xffff) {
2556 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2557 mgp->dev->name);
2558 return -EIO;
2559 }
2560
2561 status = pci_restore_state(pdev);
2562 if (status)
2563 return status;
2564
2565 status = pci_enable_device(pdev);
2566 if (status) {
2567 dev_err(&pdev->dev, "failed to enable device\n");
2568 return status;
2569 }
2570
2571 pci_set_master(pdev);
2572
2573 myri10ge_reset(mgp);
2574 myri10ge_dummy_rdma(mgp, 1);
2575
2576 /* Save configuration space to be restored if the
2577 * nic resets due to a parity error */
2578 pci_save_state(pdev);
2579
2580 if (netif_running(netdev)) {
2581 rtnl_lock();
2582 status = myri10ge_open(netdev);
2583 rtnl_unlock();
2584 if (status != 0)
2585 goto abort_with_enabled;
2586
2587 }
2588 netif_device_attach(netdev);
2589
2590 return 0;
2591
2592 abort_with_enabled:
2593 pci_disable_device(pdev);
2594 return -EIO;
2595
2596 }
2597
2598 #endif /* CONFIG_PM */
2599
2600 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2601 {
2602 struct pci_dev *pdev = mgp->pdev;
2603 int vs = mgp->vendor_specific_offset;
2604 u32 reboot;
2605
2606 /*enter read32 mode */
2607 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2608
2609 /*read REBOOT_STATUS (0xfffffff0) */
2610 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2611 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2612 return reboot;
2613 }
2614
2615 /*
2616 * This watchdog is used to check whether the board has suffered
2617 * from a parity error and needs to be recovered.
2618 */
2619 static void myri10ge_watchdog(struct work_struct *work)
2620 {
2621 struct myri10ge_priv *mgp =
2622 container_of(work, struct myri10ge_priv, watchdog_work);
2623 u32 reboot;
2624 int status;
2625 u16 cmd, vendor;
2626
2627 mgp->watchdog_resets++;
2628 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2629 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2630 /* Bus master DMA disabled? Check to see
2631 * if the card rebooted due to a parity error
2632 * For now, just report it */
2633 reboot = myri10ge_read_reboot(mgp);
2634 printk(KERN_ERR
2635 "myri10ge: %s: NIC rebooted (0x%x), resetting\n",
2636 mgp->dev->name, reboot);
2637 /*
2638 * A rebooted nic will come back with config space as
2639 * it was after power was applied to PCIe bus.
2640 * Attempt to restore config space which was saved
2641 * when the driver was loaded, or the last time the
2642 * nic was resumed from power saving mode.
2643 */
2644 pci_restore_state(mgp->pdev);
2645
2646 /* save state again for accounting reasons */
2647 pci_save_state(mgp->pdev);
2648
2649 } else {
2650 /* if we get back -1's from our slot, perhaps somebody
2651 * powered off our card. Don't try to reset it in
2652 * this case */
2653 if (cmd == 0xffff) {
2654 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2655 if (vendor == 0xffff) {
2656 printk(KERN_ERR
2657 "myri10ge: %s: device disappeared!\n",
2658 mgp->dev->name);
2659 return;
2660 }
2661 }
2662 /* Perhaps it is a software error. Try to reset */
2663
2664 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
2665 mgp->dev->name);
2666 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2667 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2668 mgp->tx.pkt_start, mgp->tx.pkt_done,
2669 (int)ntohl(mgp->fw_stats->send_done_count));
2670 msleep(2000);
2671 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
2672 mgp->dev->name, mgp->tx.req, mgp->tx.done,
2673 mgp->tx.pkt_start, mgp->tx.pkt_done,
2674 (int)ntohl(mgp->fw_stats->send_done_count));
2675 }
2676 rtnl_lock();
2677 myri10ge_close(mgp->dev);
2678 status = myri10ge_load_firmware(mgp);
2679 if (status != 0)
2680 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
2681 mgp->dev->name);
2682 else
2683 myri10ge_open(mgp->dev);
2684 rtnl_unlock();
2685 }
2686
2687 /*
2688 * We use our own timer routine rather than relying upon
2689 * netdev->tx_timeout because we have a very large hardware transmit
2690 * queue. Due to the large queue, the netdev->tx_timeout function
2691 * cannot detect a NIC with a parity error in a timely fashion if the
2692 * NIC is lightly loaded.
2693 */
2694 static void myri10ge_watchdog_timer(unsigned long arg)
2695 {
2696 struct myri10ge_priv *mgp;
2697
2698 mgp = (struct myri10ge_priv *)arg;
2699
2700 if (mgp->rx_small.watchdog_needed) {
2701 myri10ge_alloc_rx_pages(mgp, &mgp->rx_small,
2702 mgp->small_bytes + MXGEFW_PAD, 1);
2703 if (mgp->rx_small.fill_cnt - mgp->rx_small.cnt >=
2704 myri10ge_fill_thresh)
2705 mgp->rx_small.watchdog_needed = 0;
2706 }
2707 if (mgp->rx_big.watchdog_needed) {
2708 myri10ge_alloc_rx_pages(mgp, &mgp->rx_big, mgp->big_bytes, 1);
2709 if (mgp->rx_big.fill_cnt - mgp->rx_big.cnt >=
2710 myri10ge_fill_thresh)
2711 mgp->rx_big.watchdog_needed = 0;
2712 }
2713
2714 if (mgp->tx.req != mgp->tx.done &&
2715 mgp->tx.done == mgp->watchdog_tx_done &&
2716 mgp->watchdog_tx_req != mgp->watchdog_tx_done)
2717 /* nic seems like it might be stuck.. */
2718 schedule_work(&mgp->watchdog_work);
2719 else
2720 /* rearm timer */
2721 mod_timer(&mgp->watchdog_timer,
2722 jiffies + myri10ge_watchdog_timeout * HZ);
2723
2724 mgp->watchdog_tx_done = mgp->tx.done;
2725 mgp->watchdog_tx_req = mgp->tx.req;
2726 }
2727
2728 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2729 {
2730 struct net_device *netdev;
2731 struct myri10ge_priv *mgp;
2732 struct device *dev = &pdev->dev;
2733 size_t bytes;
2734 int i;
2735 int status = -ENXIO;
2736 int cap;
2737 int dac_enabled;
2738 u16 val;
2739
2740 netdev = alloc_etherdev(sizeof(*mgp));
2741 if (netdev == NULL) {
2742 dev_err(dev, "Could not allocate ethernet device\n");
2743 return -ENOMEM;
2744 }
2745
2746 mgp = netdev_priv(netdev);
2747 memset(mgp, 0, sizeof(*mgp));
2748 mgp->dev = netdev;
2749 mgp->pdev = pdev;
2750 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
2751 mgp->pause = myri10ge_flow_control;
2752 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
2753 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
2754 init_waitqueue_head(&mgp->down_wq);
2755
2756 if (pci_enable_device(pdev)) {
2757 dev_err(&pdev->dev, "pci_enable_device call failed\n");
2758 status = -ENODEV;
2759 goto abort_with_netdev;
2760 }
2761 myri10ge_select_firmware(mgp);
2762
2763 /* Find the vendor-specific cap so we can check
2764 * the reboot register later on */
2765 mgp->vendor_specific_offset
2766 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
2767
2768 /* Set our max read request to 4KB */
2769 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2770 if (cap < 64) {
2771 dev_err(&pdev->dev, "Bad PCI_CAP_ID_EXP location %d\n", cap);
2772 goto abort_with_netdev;
2773 }
2774 status = pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &val);
2775 if (status != 0) {
2776 dev_err(&pdev->dev, "Error %d reading PCI_EXP_DEVCTL\n",
2777 status);
2778 goto abort_with_netdev;
2779 }
2780 val = (val & ~PCI_EXP_DEVCTL_READRQ) | (5 << 12);
2781 status = pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, val);
2782 if (status != 0) {
2783 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
2784 status);
2785 goto abort_with_netdev;
2786 }
2787
2788 pci_set_master(pdev);
2789 dac_enabled = 1;
2790 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2791 if (status != 0) {
2792 dac_enabled = 0;
2793 dev_err(&pdev->dev,
2794 "64-bit pci address mask was refused, trying 32-bit");
2795 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2796 }
2797 if (status != 0) {
2798 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
2799 goto abort_with_netdev;
2800 }
2801 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
2802 &mgp->cmd_bus, GFP_KERNEL);
2803 if (mgp->cmd == NULL)
2804 goto abort_with_netdev;
2805
2806 mgp->fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2807 &mgp->fw_stats_bus, GFP_KERNEL);
2808 if (mgp->fw_stats == NULL)
2809 goto abort_with_cmd;
2810
2811 mgp->board_span = pci_resource_len(pdev, 0);
2812 mgp->iomem_base = pci_resource_start(pdev, 0);
2813 mgp->mtrr = -1;
2814 #ifdef CONFIG_MTRR
2815 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
2816 MTRR_TYPE_WRCOMB, 1);
2817 #endif
2818 /* Hack. need to get rid of these magic numbers */
2819 mgp->sram_size =
2820 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
2821 if (mgp->sram_size > mgp->board_span) {
2822 dev_err(&pdev->dev, "board span %ld bytes too small\n",
2823 mgp->board_span);
2824 goto abort_with_wc;
2825 }
2826 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
2827 if (mgp->sram == NULL) {
2828 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
2829 mgp->board_span, mgp->iomem_base);
2830 status = -ENXIO;
2831 goto abort_with_wc;
2832 }
2833 memcpy_fromio(mgp->eeprom_strings,
2834 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
2835 MYRI10GE_EEPROM_STRINGS_SIZE);
2836 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
2837 status = myri10ge_read_mac_addr(mgp);
2838 if (status)
2839 goto abort_with_ioremap;
2840
2841 for (i = 0; i < ETH_ALEN; i++)
2842 netdev->dev_addr[i] = mgp->mac_addr[i];
2843
2844 /* allocate rx done ring */
2845 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2846 mgp->rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
2847 &mgp->rx_done.bus, GFP_KERNEL);
2848 if (mgp->rx_done.entry == NULL)
2849 goto abort_with_ioremap;
2850 memset(mgp->rx_done.entry, 0, bytes);
2851
2852 status = myri10ge_load_firmware(mgp);
2853 if (status != 0) {
2854 dev_err(&pdev->dev, "failed to load firmware\n");
2855 goto abort_with_rx_done;
2856 }
2857
2858 status = myri10ge_reset(mgp);
2859 if (status != 0) {
2860 dev_err(&pdev->dev, "failed reset\n");
2861 goto abort_with_firmware;
2862 }
2863
2864 pci_set_drvdata(pdev, mgp);
2865 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
2866 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
2867 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
2868 myri10ge_initial_mtu = 68;
2869 netdev->mtu = myri10ge_initial_mtu;
2870 netdev->open = myri10ge_open;
2871 netdev->stop = myri10ge_close;
2872 netdev->hard_start_xmit = myri10ge_xmit;
2873 netdev->get_stats = myri10ge_get_stats;
2874 netdev->base_addr = mgp->iomem_base;
2875 netdev->change_mtu = myri10ge_change_mtu;
2876 netdev->set_multicast_list = myri10ge_set_multicast_list;
2877 netdev->set_mac_address = myri10ge_set_mac_address;
2878 netdev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
2879 if (dac_enabled)
2880 netdev->features |= NETIF_F_HIGHDMA;
2881 netdev->poll = myri10ge_poll;
2882 netdev->weight = myri10ge_napi_weight;
2883
2884 /* make sure we can get an irq, and that MSI can be
2885 * setup (if available). Also ensure netdev->irq
2886 * is set to correct value if MSI is enabled */
2887 status = myri10ge_request_irq(mgp);
2888 if (status != 0)
2889 goto abort_with_firmware;
2890 netdev->irq = pdev->irq;
2891 myri10ge_free_irq(mgp);
2892
2893 /* Save configuration space to be restored if the
2894 * nic resets due to a parity error */
2895 pci_save_state(pdev);
2896
2897 /* Setup the watchdog timer */
2898 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
2899 (unsigned long)mgp);
2900
2901 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
2902 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
2903 status = register_netdev(netdev);
2904 if (status != 0) {
2905 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2906 goto abort_with_state;
2907 }
2908 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2909 (mgp->msi_enabled ? "MSI" : "xPIC"),
2910 netdev->irq, mgp->tx.boundary, mgp->fw_name,
2911 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2912
2913 return 0;
2914
2915 abort_with_state:
2916 pci_restore_state(pdev);
2917
2918 abort_with_firmware:
2919 myri10ge_dummy_rdma(mgp, 0);
2920
2921 abort_with_rx_done:
2922 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2923 dma_free_coherent(&pdev->dev, bytes,
2924 mgp->rx_done.entry, mgp->rx_done.bus);
2925
2926 abort_with_ioremap:
2927 iounmap(mgp->sram);
2928
2929 abort_with_wc:
2930 #ifdef CONFIG_MTRR
2931 if (mgp->mtrr >= 0)
2932 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2933 #endif
2934 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2935 mgp->fw_stats, mgp->fw_stats_bus);
2936
2937 abort_with_cmd:
2938 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2939 mgp->cmd, mgp->cmd_bus);
2940
2941 abort_with_netdev:
2942
2943 free_netdev(netdev);
2944 return status;
2945 }
2946
2947 /*
2948 * myri10ge_remove
2949 *
2950 * Does what is necessary to shutdown one Myrinet device. Called
2951 * once for each Myrinet card by the kernel when a module is
2952 * unloaded.
2953 */
2954 static void myri10ge_remove(struct pci_dev *pdev)
2955 {
2956 struct myri10ge_priv *mgp;
2957 struct net_device *netdev;
2958 size_t bytes;
2959
2960 mgp = pci_get_drvdata(pdev);
2961 if (mgp == NULL)
2962 return;
2963
2964 flush_scheduled_work();
2965 netdev = mgp->dev;
2966 unregister_netdev(netdev);
2967
2968 myri10ge_dummy_rdma(mgp, 0);
2969
2970 /* avoid a memory leak */
2971 pci_restore_state(pdev);
2972
2973 bytes = myri10ge_max_intr_slots * sizeof(*mgp->rx_done.entry);
2974 dma_free_coherent(&pdev->dev, bytes,
2975 mgp->rx_done.entry, mgp->rx_done.bus);
2976
2977 iounmap(mgp->sram);
2978
2979 #ifdef CONFIG_MTRR
2980 if (mgp->mtrr >= 0)
2981 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
2982 #endif
2983 dma_free_coherent(&pdev->dev, sizeof(*mgp->fw_stats),
2984 mgp->fw_stats, mgp->fw_stats_bus);
2985
2986 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
2987 mgp->cmd, mgp->cmd_bus);
2988
2989 free_netdev(netdev);
2990 pci_set_drvdata(pdev, NULL);
2991 }
2992
2993 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
2994
2995 static struct pci_device_id myri10ge_pci_tbl[] = {
2996 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
2997 {0},
2998 };
2999
3000 static struct pci_driver myri10ge_driver = {
3001 .name = "myri10ge",
3002 .probe = myri10ge_probe,
3003 .remove = myri10ge_remove,
3004 .id_table = myri10ge_pci_tbl,
3005 #ifdef CONFIG_PM
3006 .suspend = myri10ge_suspend,
3007 .resume = myri10ge_resume,
3008 #endif
3009 };
3010
3011 static __init int myri10ge_init_module(void)
3012 {
3013 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3014 MYRI10GE_VERSION_STR);
3015 return pci_register_driver(&myri10ge_driver);
3016 }
3017
3018 module_init(myri10ge_init_module);
3019
3020 static __exit void myri10ge_cleanup_module(void)
3021 {
3022 pci_unregister_driver(&myri10ge_driver);
3023 }
3024
3025 module_exit(myri10ge_cleanup_module);
Linux kernel - Deliverables
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