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netdev: drivers should make ethtool_ops const
[deliverable/linux.git] / drivers / net / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/ioport.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/ip.h>
42 #include <linux/in.h>
43 #include <linux/tcp.h>
44 #include <linux/skbuff.h>
45 #include <linux/firmware.h>
46
47 #include <linux/ethtool.h>
48 #include <linux/mii.h>
49 #include <linux/timer.h>
50
51 #include <linux/vmalloc.h>
52
53 #include <asm/io.h>
54 #include <asm/byteorder.h>
55
56 #include "netxen_nic_hdr.h"
57 #include "netxen_nic_hw.h"
58
59 #define _NETXEN_NIC_LINUX_MAJOR 4
60 #define _NETXEN_NIC_LINUX_MINOR 0
61 #define _NETXEN_NIC_LINUX_SUBVERSION 41
62 #define NETXEN_NIC_LINUX_VERSIONID "4.0.41"
63
64 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
65 #define _major(v) (((v) >> 24) & 0xff)
66 #define _minor(v) (((v) >> 16) & 0xff)
67 #define _build(v) ((v) & 0xffff)
68
69 /* version in image has weird encoding:
70 * 7:0 - major
71 * 15:8 - minor
72 * 31:16 - build (little endian)
73 */
74 #define NETXEN_DECODE_VERSION(v) \
75 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
76
77 #define NETXEN_NUM_FLASH_SECTORS (64)
78 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
79 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
80 * NETXEN_FLASH_SECTOR_SIZE)
81
82 #define PHAN_VENDOR_ID 0x4040
83
84 #define RCV_DESC_RINGSIZE(rds_ring) \
85 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
86 #define RCV_BUFF_RINGSIZE(rds_ring) \
87 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
88 #define STATUS_DESC_RINGSIZE(sds_ring) \
89 (sizeof(struct status_desc) * (sds_ring)->num_desc)
90 #define TX_BUFF_RINGSIZE(tx_ring) \
91 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
92 #define TX_DESC_RINGSIZE(tx_ring) \
93 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
94
95 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
96
97 #define NETXEN_RCV_PRODUCER_OFFSET 0
98 #define NETXEN_RCV_PEG_DB_ID 2
99 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
100 #define FLASH_SUCCESS 0
101
102 #define ADDR_IN_WINDOW1(off) \
103 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
104
105 /*
106 * normalize a 64MB crb address to 32MB PCI window
107 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
108 */
109 #define NETXEN_CRB_NORMAL(reg) \
110 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
111
112 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
113 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
114
115 #define DB_NORMALIZE(adapter, off) \
116 (adapter->ahw.db_base + (off))
117
118 #define NX_P2_C0 0x24
119 #define NX_P2_C1 0x25
120 #define NX_P3_A0 0x30
121 #define NX_P3_A2 0x30
122 #define NX_P3_B0 0x40
123 #define NX_P3_B1 0x41
124 #define NX_P3_B2 0x42
125
126 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
127 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
128
129 #define FIRST_PAGE_GROUP_START 0
130 #define FIRST_PAGE_GROUP_END 0x100000
131
132 #define SECOND_PAGE_GROUP_START 0x6000000
133 #define SECOND_PAGE_GROUP_END 0x68BC000
134
135 #define THIRD_PAGE_GROUP_START 0x70E4000
136 #define THIRD_PAGE_GROUP_END 0x8000000
137
138 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
139 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
140 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
141
142 #define P2_MAX_MTU (8000)
143 #define P3_MAX_MTU (9600)
144 #define NX_ETHERMTU 1500
145 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
146
147 #define NX_P2_RX_BUF_MAX_LEN 1760
148 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
149 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
150 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
151 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
152
153 #define NX_RX_LRO_BUFFER_LENGTH (8060)
154
155 /*
156 * Maximum number of ring contexts
157 */
158 #define MAX_RING_CTX 1
159
160 /* Opcodes to be used with the commands */
161 #define TX_ETHER_PKT 0x01
162 #define TX_TCP_PKT 0x02
163 #define TX_UDP_PKT 0x03
164 #define TX_IP_PKT 0x04
165 #define TX_TCP_LSO 0x05
166 #define TX_TCP_LSO6 0x06
167 #define TX_IPSEC 0x07
168 #define TX_IPSEC_CMD 0x0a
169 #define TX_TCPV6_PKT 0x0b
170 #define TX_UDPV6_PKT 0x0c
171
172 /* The following opcodes are for internal consumption. */
173 #define NETXEN_CONTROL_OP 0x10
174 #define PEGNET_REQUEST 0x11
175
176 #define MAX_NUM_CARDS 4
177
178 #define MAX_BUFFERS_PER_CMD 32
179 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
180
181 /*
182 * Following are the states of the Phantom. Phantom will set them and
183 * Host will read to check if the fields are correct.
184 */
185 #define PHAN_INITIALIZE_START 0xff00
186 #define PHAN_INITIALIZE_FAILED 0xffff
187 #define PHAN_INITIALIZE_COMPLETE 0xff01
188
189 /* Host writes the following to notify that it has done the init-handshake */
190 #define PHAN_INITIALIZE_ACK 0xf00f
191
192 #define NUM_RCV_DESC_RINGS 3
193 #define NUM_STS_DESC_RINGS 4
194
195 #define RCV_RING_NORMAL 0
196 #define RCV_RING_JUMBO 1
197 #define RCV_RING_LRO 2
198
199 #define MIN_CMD_DESCRIPTORS 64
200 #define MIN_RCV_DESCRIPTORS 64
201 #define MIN_JUMBO_DESCRIPTORS 32
202
203 #define MAX_CMD_DESCRIPTORS 1024
204 #define MAX_RCV_DESCRIPTORS_1G 4096
205 #define MAX_RCV_DESCRIPTORS_10G 8192
206 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
207 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
208 #define MAX_LRO_RCV_DESCRIPTORS 8
209
210 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
211 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
212
213 #define NETXEN_CTX_SIGNATURE 0xdee0
214 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
215 #define NETXEN_CTX_RESET 0xbad0
216 #define NETXEN_CTX_D3_RESET 0xacc0
217 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
218
219 #define PHAN_PEG_RCV_INITIALIZED 0xff01
220 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
221
222 #define get_next_index(index, length) \
223 (((index) + 1) & ((length) - 1))
224
225 #define get_index_range(index,length,count) \
226 (((index) + (count)) & ((length) - 1))
227
228 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
229 #define MPORT_MULTI_FUNCTION_MODE 0x2222
230
231 /*
232 * NetXen host-peg signal message structure
233 *
234 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
235 * Bit 2 : priv_id => must be 1
236 * Bit 3-17 : count => for doorbell
237 * Bit 18-27 : ctx_id => Context id
238 * Bit 28-31 : opcode
239 */
240
241 typedef u32 netxen_ctx_msg;
242
243 #define netxen_set_msg_peg_id(config_word, val) \
244 ((config_word) &= ~3, (config_word) |= val & 3)
245 #define netxen_set_msg_privid(config_word) \
246 ((config_word) |= 1 << 2)
247 #define netxen_set_msg_count(config_word, val) \
248 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
249 #define netxen_set_msg_ctxid(config_word, val) \
250 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
251 #define netxen_set_msg_opcode(config_word, val) \
252 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
253
254 struct netxen_rcv_ring {
255 __le64 addr;
256 __le32 size;
257 __le32 rsrvd;
258 };
259
260 struct netxen_sts_ring {
261 __le64 addr;
262 __le32 size;
263 __le16 msi_index;
264 __le16 rsvd;
265 } ;
266
267 struct netxen_ring_ctx {
268
269 /* one command ring */
270 __le64 cmd_consumer_offset;
271 __le64 cmd_ring_addr;
272 __le32 cmd_ring_size;
273 __le32 rsrvd;
274
275 /* three receive rings */
276 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
277
278 __le64 sts_ring_addr;
279 __le32 sts_ring_size;
280
281 __le32 ctx_id;
282
283 __le64 rsrvd_2[3];
284 __le32 sts_ring_count;
285 __le32 rsrvd_3;
286 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
287
288 } __attribute__ ((aligned(64)));
289
290 /*
291 * Following data structures describe the descriptors that will be used.
292 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
293 * we are doing LSO (above the 1500 size packet) only.
294 */
295
296 /*
297 * The size of reference handle been changed to 16 bits to pass the MSS fields
298 * for the LSO packet
299 */
300
301 #define FLAGS_CHECKSUM_ENABLED 0x01
302 #define FLAGS_LSO_ENABLED 0x02
303 #define FLAGS_IPSEC_SA_ADD 0x04
304 #define FLAGS_IPSEC_SA_DELETE 0x08
305 #define FLAGS_VLAN_TAGGED 0x10
306 #define FLAGS_VLAN_OOB 0x40
307
308 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
309 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
310
311 #define netxen_set_cmd_desc_port(cmd_desc, var) \
312 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
313 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
314 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
315
316 #define netxen_set_tx_port(_desc, _port) \
317 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
318
319 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
320 (_desc)->flags_opcode = \
321 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
322
323 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
324 (_desc)->nfrags__length = \
325 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
326
327 struct cmd_desc_type0 {
328 u8 tcp_hdr_offset; /* For LSO only */
329 u8 ip_hdr_offset; /* For LSO only */
330 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
331 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
332
333 __le64 addr_buffer2;
334
335 __le16 reference_handle;
336 __le16 mss;
337 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
338 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
339 __le16 conn_id; /* IPSec offoad only */
340
341 __le64 addr_buffer3;
342 __le64 addr_buffer1;
343
344 __le16 buffer_length[4];
345
346 __le64 addr_buffer4;
347
348 __le16 vlan_TCI;
349 __le16 reserved;
350 __le32 reserved2;
351
352 } __attribute__ ((aligned(64)));
353
354 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
355 struct rcv_desc {
356 __le16 reference_handle;
357 __le16 reserved;
358 __le32 buffer_length; /* allocated buffer length (usually 2K) */
359 __le64 addr_buffer;
360 };
361
362 /* opcode field in status_desc */
363 #define NETXEN_NIC_SYN_OFFLOAD 0x03
364 #define NETXEN_NIC_RXPKT_DESC 0x04
365 #define NETXEN_OLD_RXPKT_DESC 0x3f
366 #define NETXEN_NIC_RESPONSE_DESC 0x05
367 #define NETXEN_NIC_LRO_DESC 0x12
368
369 /* for status field in status_desc */
370 #define STATUS_NEED_CKSUM (1)
371 #define STATUS_CKSUM_OK (2)
372
373 /* owner bits of status_desc */
374 #define STATUS_OWNER_HOST (0x1ULL << 56)
375 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
376
377 /* Status descriptor:
378 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
379 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
380 53-55 desc_cnt, 56-57 owner, 58-63 opcode
381 */
382 #define netxen_get_sts_port(sts_data) \
383 ((sts_data) & 0x0F)
384 #define netxen_get_sts_status(sts_data) \
385 (((sts_data) >> 4) & 0x0F)
386 #define netxen_get_sts_type(sts_data) \
387 (((sts_data) >> 8) & 0x0F)
388 #define netxen_get_sts_totallength(sts_data) \
389 (((sts_data) >> 12) & 0xFFFF)
390 #define netxen_get_sts_refhandle(sts_data) \
391 (((sts_data) >> 28) & 0xFFFF)
392 #define netxen_get_sts_prot(sts_data) \
393 (((sts_data) >> 44) & 0x0F)
394 #define netxen_get_sts_pkt_offset(sts_data) \
395 (((sts_data) >> 48) & 0x1F)
396 #define netxen_get_sts_desc_cnt(sts_data) \
397 (((sts_data) >> 53) & 0x7)
398 #define netxen_get_sts_opcode(sts_data) \
399 (((sts_data) >> 58) & 0x03F)
400
401 #define netxen_get_lro_sts_refhandle(sts_data) \
402 ((sts_data) & 0x0FFFF)
403 #define netxen_get_lro_sts_length(sts_data) \
404 (((sts_data) >> 16) & 0x0FFFF)
405 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
406 (((sts_data) >> 32) & 0x0FF)
407 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
408 (((sts_data) >> 40) & 0x0FF)
409 #define netxen_get_lro_sts_timestamp(sts_data) \
410 (((sts_data) >> 48) & 0x1)
411 #define netxen_get_lro_sts_type(sts_data) \
412 (((sts_data) >> 49) & 0x7)
413 #define netxen_get_lro_sts_push_flag(sts_data) \
414 (((sts_data) >> 52) & 0x1)
415 #define netxen_get_lro_sts_seq_number(sts_data) \
416 ((sts_data) & 0x0FFFFFFFF)
417
418
419 struct status_desc {
420 __le64 status_desc_data[2];
421 } __attribute__ ((aligned(16)));
422
423 /* The version of the main data structure */
424 #define NETXEN_BDINFO_VERSION 1
425
426 /* Magic number to let user know flash is programmed */
427 #define NETXEN_BDINFO_MAGIC 0x12345678
428
429 /* Max number of Gig ports on a Phantom board */
430 #define NETXEN_MAX_PORTS 4
431
432 #define NETXEN_BRDTYPE_P1_BD 0x0000
433 #define NETXEN_BRDTYPE_P1_SB 0x0001
434 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
435 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
436
437 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
438 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
439 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
440 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
441 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
442
443 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
444 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
445 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
446
447 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
448 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
449 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
450 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
451 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
452 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
453 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
454 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
455 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
456 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
457 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
458 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
459 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
460 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
461
462 /* Flash memory map */
463 #define NETXEN_CRBINIT_START 0 /* crbinit section */
464 #define NETXEN_BRDCFG_START 0x4000 /* board config */
465 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
466 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
467 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
468 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
469 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
470 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
471 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
472 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
473
474 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
475 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
476 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
477 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
478 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
479 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
480
481 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
482 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
483 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
484
485 #define NX_FW_MIN_SIZE (0x3fffff)
486 #define NX_P2_MN_ROMIMAGE 0
487 #define NX_P3_CT_ROMIMAGE 1
488 #define NX_P3_MN_ROMIMAGE 2
489 #define NX_FLASH_ROMIMAGE 3
490
491 extern char netxen_nic_driver_name[];
492
493 /* Number of status descriptors to handle per interrupt */
494 #define MAX_STATUS_HANDLE (64)
495
496 /*
497 * netxen_skb_frag{} is to contain mapping info for each SG list. This
498 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
499 */
500 struct netxen_skb_frag {
501 u64 dma;
502 u64 length;
503 };
504
505 struct netxen_recv_crb {
506 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
507 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
508 u32 sw_int_mask[NUM_STS_DESC_RINGS];
509 };
510
511 /* Following defines are for the state of the buffers */
512 #define NETXEN_BUFFER_FREE 0
513 #define NETXEN_BUFFER_BUSY 1
514
515 /*
516 * There will be one netxen_buffer per skb packet. These will be
517 * used to save the dma info for pci_unmap_page()
518 */
519 struct netxen_cmd_buffer {
520 struct sk_buff *skb;
521 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
522 u32 frag_count;
523 };
524
525 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
526 struct netxen_rx_buffer {
527 struct list_head list;
528 struct sk_buff *skb;
529 u64 dma;
530 u16 ref_handle;
531 u16 state;
532 };
533
534 /* Board types */
535 #define NETXEN_NIC_GBE 0x01
536 #define NETXEN_NIC_XGBE 0x02
537
538 /*
539 * One hardware_context{} per adapter
540 * contains interrupt info as well shared hardware info.
541 */
542 struct netxen_hardware_context {
543 void __iomem *pci_base0;
544 void __iomem *pci_base1;
545 void __iomem *pci_base2;
546 void __iomem *db_base;
547 unsigned long db_len;
548 unsigned long pci_len0;
549
550 int qdr_sn_window;
551 int ddr_mn_window;
552 unsigned long mn_win_crb;
553 unsigned long ms_win_crb;
554
555 u8 cut_through;
556 u8 revision_id;
557 u8 pci_func;
558 u8 linkup;
559 u16 port_type;
560 u16 board_type;
561 };
562
563 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
564 #define ETHERNET_FCS_SIZE 4
565
566 struct netxen_adapter_stats {
567 u64 xmitcalled;
568 u64 xmitfinished;
569 u64 rxdropped;
570 u64 txdropped;
571 u64 csummed;
572 u64 rx_pkts;
573 u64 lro_pkts;
574 u64 rxbytes;
575 u64 txbytes;
576 };
577
578 /*
579 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
580 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
581 */
582 struct nx_host_rds_ring {
583 u32 producer;
584 u32 crb_rcv_producer;
585 u32 num_desc;
586 u32 dma_size;
587 u32 skb_size;
588 u32 flags;
589 struct rcv_desc *desc_head;
590 struct netxen_rx_buffer *rx_buf_arr;
591 struct list_head free_list;
592 spinlock_t lock;
593 dma_addr_t phys_addr;
594 };
595
596 struct nx_host_sds_ring {
597 u32 consumer;
598 u32 crb_sts_consumer;
599 u32 crb_intr_mask;
600 u32 num_desc;
601
602 struct status_desc *desc_head;
603 struct netxen_adapter *adapter;
604 struct napi_struct napi;
605 struct list_head free_list[NUM_RCV_DESC_RINGS];
606
607 int irq;
608
609 dma_addr_t phys_addr;
610 char name[IFNAMSIZ+4];
611 };
612
613 struct nx_host_tx_ring {
614 u32 producer;
615 __le32 *hw_consumer;
616 u32 sw_consumer;
617 u32 crb_cmd_producer;
618 u32 crb_cmd_consumer;
619 u32 num_desc;
620
621 struct netdev_queue *txq;
622
623 struct netxen_cmd_buffer *cmd_buf_arr;
624 struct cmd_desc_type0 *desc_head;
625 dma_addr_t phys_addr;
626 };
627
628 /*
629 * Receive context. There is one such structure per instance of the
630 * receive processing. Any state information that is relevant to
631 * the receive, and is must be in this structure. The global data may be
632 * present elsewhere.
633 */
634 struct netxen_recv_context {
635 u32 state;
636 u16 context_id;
637 u16 virt_port;
638
639 struct nx_host_rds_ring *rds_rings;
640 struct nx_host_sds_ring *sds_rings;
641
642 struct netxen_ring_ctx *hwctx;
643 dma_addr_t phys_addr;
644 };
645
646 /* New HW context creation */
647
648 #define NX_OS_CRB_RETRY_COUNT 4000
649 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
650 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
651
652 #define NX_CDRP_CLEAR 0x00000000
653 #define NX_CDRP_CMD_BIT 0x80000000
654
655 /*
656 * All responses must have the NX_CDRP_CMD_BIT cleared
657 * in the crb NX_CDRP_CRB_OFFSET.
658 */
659 #define NX_CDRP_FORM_RSP(rsp) (rsp)
660 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
661
662 #define NX_CDRP_RSP_OK 0x00000001
663 #define NX_CDRP_RSP_FAIL 0x00000002
664 #define NX_CDRP_RSP_TIMEOUT 0x00000003
665
666 /*
667 * All commands must have the NX_CDRP_CMD_BIT set in
668 * the crb NX_CDRP_CRB_OFFSET.
669 */
670 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
671 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
672
673 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
674 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
675 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
676 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
677 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
678 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
679 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
680 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
681 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
682 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
683 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
684 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
685 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
686 #define NX_CDRP_CMD_SET_MTU 0x00000012
687 #define NX_CDRP_CMD_READ_PHY 0x00000013
688 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
689 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
690 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
691 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
692 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
693 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
694 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
695 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
696 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
697 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
698 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
699 #define NX_CDRP_CMD_MAX 0x0000001f
700
701 #define NX_RCODE_SUCCESS 0
702 #define NX_RCODE_NO_HOST_MEM 1
703 #define NX_RCODE_NO_HOST_RESOURCE 2
704 #define NX_RCODE_NO_CARD_CRB 3
705 #define NX_RCODE_NO_CARD_MEM 4
706 #define NX_RCODE_NO_CARD_RESOURCE 5
707 #define NX_RCODE_INVALID_ARGS 6
708 #define NX_RCODE_INVALID_ACTION 7
709 #define NX_RCODE_INVALID_STATE 8
710 #define NX_RCODE_NOT_SUPPORTED 9
711 #define NX_RCODE_NOT_PERMITTED 10
712 #define NX_RCODE_NOT_READY 11
713 #define NX_RCODE_DOES_NOT_EXIST 12
714 #define NX_RCODE_ALREADY_EXISTS 13
715 #define NX_RCODE_BAD_SIGNATURE 14
716 #define NX_RCODE_CMD_NOT_IMPL 15
717 #define NX_RCODE_CMD_INVALID 16
718 #define NX_RCODE_TIMEOUT 17
719 #define NX_RCODE_CMD_FAILED 18
720 #define NX_RCODE_MAX_EXCEEDED 19
721 #define NX_RCODE_MAX 20
722
723 #define NX_DESTROY_CTX_RESET 0
724 #define NX_DESTROY_CTX_D3_RESET 1
725 #define NX_DESTROY_CTX_MAX 2
726
727 /*
728 * Capabilities
729 */
730 #define NX_CAP_BIT(class, bit) (1 << bit)
731 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
732 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
733 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
734 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
735 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
736 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
737 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
738 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
739 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
740 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
741
742 /*
743 * Context state
744 */
745 #define NX_HOST_CTX_STATE_FREED 0
746 #define NX_HOST_CTX_STATE_ALLOCATED 1
747 #define NX_HOST_CTX_STATE_ACTIVE 2
748 #define NX_HOST_CTX_STATE_DISABLED 3
749 #define NX_HOST_CTX_STATE_QUIESCED 4
750 #define NX_HOST_CTX_STATE_MAX 5
751
752 /*
753 * Rx context
754 */
755
756 typedef struct {
757 __le64 host_phys_addr; /* Ring base addr */
758 __le32 ring_size; /* Ring entries */
759 __le16 msi_index;
760 __le16 rsvd; /* Padding */
761 } nx_hostrq_sds_ring_t;
762
763 typedef struct {
764 __le64 host_phys_addr; /* Ring base addr */
765 __le64 buff_size; /* Packet buffer size */
766 __le32 ring_size; /* Ring entries */
767 __le32 ring_kind; /* Class of ring */
768 } nx_hostrq_rds_ring_t;
769
770 typedef struct {
771 __le64 host_rsp_dma_addr; /* Response dma'd here */
772 __le32 capabilities[4]; /* Flag bit vector */
773 __le32 host_int_crb_mode; /* Interrupt crb usage */
774 __le32 host_rds_crb_mode; /* RDS crb usage */
775 /* These ring offsets are relative to data[0] below */
776 __le32 rds_ring_offset; /* Offset to RDS config */
777 __le32 sds_ring_offset; /* Offset to SDS config */
778 __le16 num_rds_rings; /* Count of RDS rings */
779 __le16 num_sds_rings; /* Count of SDS rings */
780 __le16 rsvd1; /* Padding */
781 __le16 rsvd2; /* Padding */
782 u8 reserved[128]; /* reserve space for future expansion*/
783 /* MUST BE 64-bit aligned.
784 The following is packed:
785 - N hostrq_rds_rings
786 - N hostrq_sds_rings */
787 char data[0];
788 } nx_hostrq_rx_ctx_t;
789
790 typedef struct {
791 __le32 host_producer_crb; /* Crb to use */
792 __le32 rsvd1; /* Padding */
793 } nx_cardrsp_rds_ring_t;
794
795 typedef struct {
796 __le32 host_consumer_crb; /* Crb to use */
797 __le32 interrupt_crb; /* Crb to use */
798 } nx_cardrsp_sds_ring_t;
799
800 typedef struct {
801 /* These ring offsets are relative to data[0] below */
802 __le32 rds_ring_offset; /* Offset to RDS config */
803 __le32 sds_ring_offset; /* Offset to SDS config */
804 __le32 host_ctx_state; /* Starting State */
805 __le32 num_fn_per_port; /* How many PCI fn share the port */
806 __le16 num_rds_rings; /* Count of RDS rings */
807 __le16 num_sds_rings; /* Count of SDS rings */
808 __le16 context_id; /* Handle for context */
809 u8 phys_port; /* Physical id of port */
810 u8 virt_port; /* Virtual/Logical id of port */
811 u8 reserved[128]; /* save space for future expansion */
812 /* MUST BE 64-bit aligned.
813 The following is packed:
814 - N cardrsp_rds_rings
815 - N cardrs_sds_rings */
816 char data[0];
817 } nx_cardrsp_rx_ctx_t;
818
819 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
820 (sizeof(HOSTRQ_RX) + \
821 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
822 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
823
824 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
825 (sizeof(CARDRSP_RX) + \
826 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
827 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
828
829 /*
830 * Tx context
831 */
832
833 typedef struct {
834 __le64 host_phys_addr; /* Ring base addr */
835 __le32 ring_size; /* Ring entries */
836 __le32 rsvd; /* Padding */
837 } nx_hostrq_cds_ring_t;
838
839 typedef struct {
840 __le64 host_rsp_dma_addr; /* Response dma'd here */
841 __le64 cmd_cons_dma_addr; /* */
842 __le64 dummy_dma_addr; /* */
843 __le32 capabilities[4]; /* Flag bit vector */
844 __le32 host_int_crb_mode; /* Interrupt crb usage */
845 __le32 rsvd1; /* Padding */
846 __le16 rsvd2; /* Padding */
847 __le16 interrupt_ctl;
848 __le16 msi_index;
849 __le16 rsvd3; /* Padding */
850 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
851 u8 reserved[128]; /* future expansion */
852 } nx_hostrq_tx_ctx_t;
853
854 typedef struct {
855 __le32 host_producer_crb; /* Crb to use */
856 __le32 interrupt_crb; /* Crb to use */
857 } nx_cardrsp_cds_ring_t;
858
859 typedef struct {
860 __le32 host_ctx_state; /* Starting state */
861 __le16 context_id; /* Handle for context */
862 u8 phys_port; /* Physical id of port */
863 u8 virt_port; /* Virtual/Logical id of port */
864 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
865 u8 reserved[128]; /* future expansion */
866 } nx_cardrsp_tx_ctx_t;
867
868 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
869 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
870
871 /* CRB */
872
873 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
874 #define NX_HOST_RDS_CRB_MODE_SHARED 1
875 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
876 #define NX_HOST_RDS_CRB_MODE_MAX 3
877
878 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
879 #define NX_HOST_INT_CRB_MODE_SHARED 1
880 #define NX_HOST_INT_CRB_MODE_NORX 2
881 #define NX_HOST_INT_CRB_MODE_NOTX 3
882 #define NX_HOST_INT_CRB_MODE_NORXTX 4
883
884
885 /* MAC */
886
887 #define MC_COUNT_P2 16
888 #define MC_COUNT_P3 38
889
890 #define NETXEN_MAC_NOOP 0
891 #define NETXEN_MAC_ADD 1
892 #define NETXEN_MAC_DEL 2
893
894 typedef struct nx_mac_list_s {
895 struct list_head list;
896 uint8_t mac_addr[ETH_ALEN+2];
897 } nx_mac_list_t;
898
899 /*
900 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
901 * adjusted based on configured MTU.
902 */
903 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
904 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
905 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
906 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
907
908 #define NETXEN_NIC_INTR_DEFAULT 0x04
909
910 typedef union {
911 struct {
912 uint16_t rx_packets;
913 uint16_t rx_time_us;
914 uint16_t tx_packets;
915 uint16_t tx_time_us;
916 } data;
917 uint64_t word;
918 } nx_nic_intr_coalesce_data_t;
919
920 typedef struct {
921 uint16_t stats_time_us;
922 uint16_t rate_sample_time;
923 uint16_t flags;
924 uint16_t rsvd_1;
925 uint32_t low_threshold;
926 uint32_t high_threshold;
927 nx_nic_intr_coalesce_data_t normal;
928 nx_nic_intr_coalesce_data_t low;
929 nx_nic_intr_coalesce_data_t high;
930 nx_nic_intr_coalesce_data_t irq;
931 } nx_nic_intr_coalesce_t;
932
933 #define NX_HOST_REQUEST 0x13
934 #define NX_NIC_REQUEST 0x14
935
936 #define NX_MAC_EVENT 0x1
937
938 #define NX_IP_UP 2
939 #define NX_IP_DOWN 3
940
941 /*
942 * Driver --> Firmware
943 */
944 #define NX_NIC_H2C_OPCODE_START 0
945 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
946 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
947 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
948 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
949 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
950 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
951 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
952 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
953 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
954 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
955 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
956 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
957 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
958 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
959 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
960 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
961 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
962 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
963 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
964 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
965 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
966 #define NX_NIC_C2C_OPCODE 22
967 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
968 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
969 #define NX_NIC_H2C_OPCODE_LAST 25
970
971 /*
972 * Firmware --> Driver
973 */
974
975 #define NX_NIC_C2H_OPCODE_START 128
976 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
977 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
978 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
979 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
980 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
981 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
982 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
983 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
984 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
985 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
986 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
987 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
988 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
989 #define NX_NIC_C2H_OPCODE_LAST 142
990
991 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
992 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
993 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
994
995 #define NX_NIC_LRO_REQUEST_FIRST 0
996 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
997 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
998 #define NX_NIC_LRO_REQUEST_TIMER 3
999 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1000 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1001 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1002 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1003 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1004 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1005 #define NX_TOE_LRO_REQUEST_TIMER 10
1006 #define NX_NIC_LRO_REQUEST_LAST 11
1007
1008 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1009 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1010 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1011 #define NX_FW_CAPABILITY_BDG (1 << 8)
1012 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1013 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1014
1015 /* module types */
1016 #define LINKEVENT_MODULE_NOT_PRESENT 1
1017 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1018 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1019 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1020 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1021 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1022 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1023 #define LINKEVENT_MODULE_TWINAX 8
1024
1025 #define LINKSPEED_10GBPS 10000
1026 #define LINKSPEED_1GBPS 1000
1027 #define LINKSPEED_100MBPS 100
1028 #define LINKSPEED_10MBPS 10
1029
1030 #define LINKSPEED_ENCODED_10MBPS 0
1031 #define LINKSPEED_ENCODED_100MBPS 1
1032 #define LINKSPEED_ENCODED_1GBPS 2
1033
1034 #define LINKEVENT_AUTONEG_DISABLED 0
1035 #define LINKEVENT_AUTONEG_ENABLED 1
1036
1037 #define LINKEVENT_HALF_DUPLEX 0
1038 #define LINKEVENT_FULL_DUPLEX 1
1039
1040 #define LINKEVENT_LINKSPEED_MBPS 0
1041 #define LINKEVENT_LINKSPEED_ENCODED 1
1042
1043 /* firmware response header:
1044 * 63:58 - message type
1045 * 57:56 - owner
1046 * 55:53 - desc count
1047 * 52:48 - reserved
1048 * 47:40 - completion id
1049 * 39:32 - opcode
1050 * 31:16 - error code
1051 * 15:00 - reserved
1052 */
1053 #define netxen_get_nic_msgtype(msg_hdr) \
1054 ((msg_hdr >> 58) & 0x3F)
1055 #define netxen_get_nic_msg_compid(msg_hdr) \
1056 ((msg_hdr >> 40) & 0xFF)
1057 #define netxen_get_nic_msg_opcode(msg_hdr) \
1058 ((msg_hdr >> 32) & 0xFF)
1059 #define netxen_get_nic_msg_errcode(msg_hdr) \
1060 ((msg_hdr >> 16) & 0xFFFF)
1061
1062 typedef struct {
1063 union {
1064 struct {
1065 u64 hdr;
1066 u64 body[7];
1067 };
1068 u64 words[8];
1069 };
1070 } nx_fw_msg_t;
1071
1072 typedef struct {
1073 __le64 qhdr;
1074 __le64 req_hdr;
1075 __le64 words[6];
1076 } nx_nic_req_t;
1077
1078 typedef struct {
1079 u8 op;
1080 u8 tag;
1081 u8 mac_addr[6];
1082 } nx_mac_req_t;
1083
1084 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1085
1086 #define NETXEN_NIC_MSI_ENABLED 0x02
1087 #define NETXEN_NIC_MSIX_ENABLED 0x04
1088 #define NETXEN_NIC_LRO_ENABLED 0x08
1089 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1090 #define NETXEN_IS_MSI_FAMILY(adapter) \
1091 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1092
1093 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1094 #define NETXEN_MSIX_TBL_SPACE 8192
1095 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1096
1097 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1098
1099 #define NETXEN_NETDEV_WEIGHT 128
1100 #define NETXEN_ADAPTER_UP_MAGIC 777
1101 #define NETXEN_NIC_PEG_TUNE 0
1102
1103 struct netxen_dummy_dma {
1104 void *addr;
1105 dma_addr_t phys_addr;
1106 };
1107
1108 struct netxen_adapter {
1109 struct netxen_hardware_context ahw;
1110
1111 struct net_device *netdev;
1112 struct pci_dev *pdev;
1113 struct list_head mac_list;
1114
1115 u32 curr_window;
1116 u32 crb_win;
1117 rwlock_t adapter_lock;
1118
1119 spinlock_t tx_clean_lock;
1120
1121 u16 num_txd;
1122 u16 num_rxd;
1123 u16 num_jumbo_rxd;
1124 u16 num_lro_rxd;
1125
1126 u8 max_rds_rings;
1127 u8 max_sds_rings;
1128 u8 driver_mismatch;
1129 u8 msix_supported;
1130 u8 rx_csum;
1131 u8 pci_using_dac;
1132 u8 portnum;
1133 u8 physical_port;
1134
1135 u8 mc_enabled;
1136 u8 max_mc_count;
1137 u8 rss_supported;
1138 u8 link_changed;
1139 u32 resv3;
1140
1141 u8 has_link_events;
1142 u8 fw_type;
1143 u16 tx_context_id;
1144 u16 mtu;
1145 u16 is_up;
1146
1147 u16 link_speed;
1148 u16 link_duplex;
1149 u16 link_autoneg;
1150 u16 module_type;
1151
1152 u32 capabilities;
1153 u32 flags;
1154 u32 irq;
1155 u32 temp;
1156
1157 u32 msi_tgt_status;
1158 u32 resv4;
1159
1160 struct netxen_adapter_stats stats;
1161
1162 struct netxen_recv_context recv_ctx;
1163 struct nx_host_tx_ring *tx_ring;
1164
1165 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1166 int (*set_mtu) (struct netxen_adapter *, int);
1167 int (*set_promisc) (struct netxen_adapter *, u32);
1168 void (*set_multi) (struct net_device *);
1169 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1170 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1171 int (*init_port) (struct netxen_adapter *, int);
1172 int (*stop_port) (struct netxen_adapter *);
1173
1174 u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1175 int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1176 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1177 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1178 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1179 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1180 unsigned long (*pci_set_window)(struct netxen_adapter *,
1181 unsigned long long);
1182
1183 struct netxen_legacy_intr_set legacy_intr;
1184
1185 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1186
1187 struct netxen_dummy_dma dummy_dma;
1188
1189 struct work_struct watchdog_task;
1190 struct timer_list watchdog_timer;
1191 struct work_struct tx_timeout_task;
1192
1193 struct net_device_stats net_stats;
1194
1195 nx_nic_intr_coalesce_t coal;
1196
1197 u32 resv5;
1198 u32 fw_version;
1199 const struct firmware *fw;
1200 };
1201
1202 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
1203 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
1204
1205 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1206 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1207
1208 /* Functions available from netxen_nic_hw.c */
1209 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1210 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1211
1212 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1213 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1214
1215 #define NXRD32(adapter, off) \
1216 (adapter->hw_read_wx(adapter, off))
1217 #define NXWR32(adapter, off, val) \
1218 (adapter->hw_write_wx(adapter, off, val))
1219
1220 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1221 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1222
1223 #define netxen_rom_lock(a) \
1224 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1225 #define netxen_rom_unlock(a) \
1226 netxen_pcie_sem_unlock((a), 2)
1227 #define netxen_phy_lock(a) \
1228 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1229 #define netxen_phy_unlock(a) \
1230 netxen_pcie_sem_unlock((a), 3)
1231 #define netxen_api_lock(a) \
1232 netxen_pcie_sem_lock((a), 5, 0)
1233 #define netxen_api_unlock(a) \
1234 netxen_pcie_sem_unlock((a), 5)
1235 #define netxen_sw_lock(a) \
1236 netxen_pcie_sem_lock((a), 6, 0)
1237 #define netxen_sw_unlock(a) \
1238 netxen_pcie_sem_unlock((a), 6)
1239 #define crb_win_lock(a) \
1240 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1241 #define crb_win_unlock(a) \
1242 netxen_pcie_sem_unlock((a), 7)
1243
1244 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1245 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1246 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1247
1248 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1249 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1250 ulong off, u32 data);
1251 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1252 u64 off, void *data, int size);
1253 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1254 u64 off, void *data, int size);
1255 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1256 u64 off, u32 data);
1257 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1258 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1259 u64 off, u32 data);
1260 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1261 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1262 unsigned long long addr);
1263 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1264 u32 wndw);
1265
1266 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1267 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1268 ulong off, u32 data);
1269 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1270 u64 off, void *data, int size);
1271 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1272 u64 off, void *data, int size);
1273 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1274 u64 off, u32 data);
1275 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1276 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1277 u64 off, u32 data);
1278 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1279 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1280 unsigned long long addr);
1281
1282 /* Functions from netxen_nic_init.c */
1283 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1284 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1285
1286 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1287 int netxen_load_firmware(struct netxen_adapter *adapter);
1288 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1289 void netxen_request_firmware(struct netxen_adapter *adapter);
1290 void netxen_release_firmware(struct netxen_adapter *adapter);
1291 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1292
1293 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1294 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1295 u8 *bytes, size_t size);
1296 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1297 u8 *bytes, size_t size);
1298 int netxen_flash_unlock(struct netxen_adapter *adapter);
1299 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1300 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1301 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1302 void netxen_halt_pegs(struct netxen_adapter *adapter);
1303
1304 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1305
1306 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1307 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1308
1309 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1310 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1311
1312 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1313 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1314
1315 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1316 int netxen_init_firmware(struct netxen_adapter *adapter);
1317 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1318 void netxen_watchdog_task(struct work_struct *work);
1319 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1320 struct nx_host_rds_ring *rds_ring);
1321 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1322 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1323 void netxen_p2_nic_set_multi(struct net_device *netdev);
1324 void netxen_p3_nic_set_multi(struct net_device *netdev);
1325 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1326 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode);
1327 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1328 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1329 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1330 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1331 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1332 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1333
1334 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1335 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1336 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1337 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1338 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1339
1340 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1341 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1342
1343 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1344 struct nx_host_tx_ring *tx_ring);
1345
1346 /* Functions from netxen_nic_main.c */
1347 int netxen_nic_reset_context(struct netxen_adapter *);
1348
1349 /*
1350 * NetXen Board information
1351 */
1352
1353 #define NETXEN_MAX_SHORT_NAME 32
1354 struct netxen_brdinfo {
1355 int brdtype; /* type of board */
1356 long ports; /* max no of physical ports */
1357 char short_name[NETXEN_MAX_SHORT_NAME];
1358 };
1359
1360 static const struct netxen_brdinfo netxen_boards[] = {
1361 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1362 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1363 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1364 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1365 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1366 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1367 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1368 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1369 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1370 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1371 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1372 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1373 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1374 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1375 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1376 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1377 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1378 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1379 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1380 };
1381
1382 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1383
1384 static inline void get_brd_name_by_type(u32 type, char *name)
1385 {
1386 int i, found = 0;
1387 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1388 if (netxen_boards[i].brdtype == type) {
1389 strcpy(name, netxen_boards[i].short_name);
1390 found = 1;
1391 break;
1392 }
1393
1394 }
1395 if (!found)
1396 name = "Unknown";
1397 }
1398
1399 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1400 {
1401 smp_mb();
1402 return find_diff_among(tx_ring->producer,
1403 tx_ring->sw_consumer, tx_ring->num_desc);
1404
1405 }
1406
1407 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1408 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1409 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1410 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1411 int *valp);
1412
1413 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1414
1415 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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