drivers/net/netxen/netxen_nic.h

   1 /*
   2  * Copyright (C) 2003 - 2009 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen Inc,
  26  * 18922 Forge Drive
  27  * Cupertino, CA 95014-0701
  28  *
  29  */
  30
  31 #ifndef _NETXEN_NIC_H_
  32 #define _NETXEN_NIC_H_
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ioport.h>
  38 #include <linux/pci.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/ip.h>
  42 #include <linux/in.h>
  43 #include <linux/tcp.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/firmware.h>
  46
  47 #include <linux/ethtool.h>
  48 #include <linux/mii.h>
  49 #include <linux/timer.h>
  50
  51 #include <linux/vmalloc.h>
  52
  53 #include <asm/io.h>
  54 #include <asm/byteorder.h>
  55
  56 #include "netxen_nic_hw.h"
  57
  58 #define _NETXEN_NIC_LINUX_MAJOR 4
  59 #define _NETXEN_NIC_LINUX_MINOR 0
  60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
  61 #define NETXEN_NIC_LINUX_VERSIONID  "4.0.30"
  62
  63 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
  64 #define _major(v)       (((v) >> 24) & 0xff)
  65 #define _minor(v)       (((v) >> 16) & 0xff)
  66 #define _build(v)       ((v) & 0xffff)
  67
  68 /* version in image has weird encoding:
  69  *  7:0  - major
  70  * 15:8  - minor
  71  * 31:16 - build (little endian)
  72  */
  73 #define NETXEN_DECODE_VERSION(v) \
  74         NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
  75
  76 #define NETXEN_NUM_FLASH_SECTORS (64)
  77 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  78 #define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  79                                         * NETXEN_FLASH_SECTOR_SIZE)
  80
  81 #define PHAN_VENDOR_ID 0x4040
  82
  83 #define RCV_DESC_RINGSIZE(rds_ring)     \
  84         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  85 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  86         (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  87 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  88         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  89 #define TX_BUFF_RINGSIZE(tx_ring)       \
  90         (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  91 #define TX_DESC_RINGSIZE(tx_ring)       \
  92         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  93
  94 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  95
  96 #define NETXEN_RCV_PRODUCER_OFFSET      0
  97 #define NETXEN_RCV_PEG_DB_ID            2
  98 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  99 #define FLASH_SUCCESS 0
 100
 101 #define ADDR_IN_WINDOW1(off)    \
 102         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
 103
 104 /*
 105  * normalize a 64MB crb address to 32MB PCI window
 106  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
 107  */
 108 #define NETXEN_CRB_NORMAL(reg)  \
 109         ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
 110
 111 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
 112         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 113
 114 #define DB_NORMALIZE(adapter, off) \
 115         (adapter->ahw.db_base + (off))
 116
 117 #define NX_P2_C0                0x24
 118 #define NX_P2_C1                0x25
 119 #define NX_P3_A0                0x30
 120 #define NX_P3_A2                0x30
 121 #define NX_P3_B0                0x40
 122 #define NX_P3_B1                0x41
 123 #define NX_P3_B2                0x42
 124
 125 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 126 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 127
 128 #define FIRST_PAGE_GROUP_START  0
 129 #define FIRST_PAGE_GROUP_END    0x100000
 130
 131 #define SECOND_PAGE_GROUP_START 0x6000000
 132 #define SECOND_PAGE_GROUP_END   0x68BC000
 133
 134 #define THIRD_PAGE_GROUP_START  0x70E4000
 135 #define THIRD_PAGE_GROUP_END    0x8000000
 136
 137 #define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 138 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 139 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 140
 141 #define P2_MAX_MTU                     (8000)
 142 #define P3_MAX_MTU                     (9600)
 143 #define NX_ETHERMTU                    1500
 144 #define NX_MAX_ETHERHDR                32 /* This contains some padding */
 145
 146 #define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 149 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 150
 151 #define MAX_RX_BUFFER_LENGTH            1760
 152 #define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 153 #define MAX_RX_LRO_BUFFER_LENGTH        (8062)
 154 #define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 155 #define RX_JUMBO_DMA_MAP_LEN    \
 156         (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 157 #define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 158
 159 /*
 160  * Maximum number of ring contexts
 161  */
 162 #define MAX_RING_CTX 1
 163
 164 /* Opcodes to be used with the commands */
 165 #define TX_ETHER_PKT    0x01
 166 #define TX_TCP_PKT      0x02
 167 #define TX_UDP_PKT      0x03
 168 #define TX_IP_PKT       0x04
 169 #define TX_TCP_LSO      0x05
 170 #define TX_TCP_LSO6     0x06
 171 #define TX_IPSEC        0x07
 172 #define TX_IPSEC_CMD    0x0a
 173 #define TX_TCPV6_PKT    0x0b
 174 #define TX_UDPV6_PKT    0x0c
 175
 176 /* The following opcodes are for internal consumption. */
 177 #define NETXEN_CONTROL_OP       0x10
 178 #define PEGNET_REQUEST          0x11
 179
 180 #define MAX_NUM_CARDS           4
 181
 182 #define MAX_BUFFERS_PER_CMD     32
 183 #define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + 4)
 184
 185 /*
 186  * Following are the states of the Phantom. Phantom will set them and
 187  * Host will read to check if the fields are correct.
 188  */
 189 #define PHAN_INITIALIZE_START           0xff00
 190 #define PHAN_INITIALIZE_FAILED          0xffff
 191 #define PHAN_INITIALIZE_COMPLETE        0xff01
 192
 193 /* Host writes the following to notify that it has done the init-handshake */
 194 #define PHAN_INITIALIZE_ACK     0xf00f
 195
 196 #define NUM_RCV_DESC_RINGS      3
 197 #define NUM_STS_DESC_RINGS      4
 198
 199 #define RCV_RING_NORMAL 0
 200 #define RCV_RING_JUMBO  1
 201 #define RCV_RING_LRO    2
 202
 203 #define MAX_CMD_DESCRIPTORS             4096
 204 #define MAX_RCV_DESCRIPTORS             16384
 205 #define MAX_CMD_DESCRIPTORS_HOST        1024
 206 #define MAX_RCV_DESCRIPTORS_1G          2048
 207 #define MAX_RCV_DESCRIPTORS_10G         4096
 208 #define MAX_JUMBO_RCV_DESCRIPTORS       1024
 209 #define MAX_LRO_RCV_DESCRIPTORS         8
 210 #define NETXEN_CTX_SIGNATURE    0xdee0
 211 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
 212 #define NETXEN_CTX_RESET        0xbad0
 213 #define NETXEN_CTX_D3_RESET     0xacc0
 214 #define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 215
 216 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 217 #define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 218
 219 #define get_next_index(index, length)   \
 220         (((index) + 1) & ((length) - 1))
 221
 222 #define get_index_range(index,length,count)     \
 223         (((index) + (count)) & ((length) - 1))
 224
 225 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
 226 #define MPORT_MULTI_FUNCTION_MODE 0x2222
 227
 228 #include "netxen_nic_phan_reg.h"
 229
 230 /*
 231  * NetXen host-peg signal message structure
 232  *
 233  *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 234  *      Bit 2           : priv_id => must be 1
 235  *      Bit 3-17        : count => for doorbell
 236  *      Bit 18-27       : ctx_id => Context id
 237  *      Bit 28-31       : opcode
 238  */
 239
 240 typedef u32 netxen_ctx_msg;
 241
 242 #define netxen_set_msg_peg_id(config_word, val) \
 243         ((config_word) &= ~3, (config_word) |= val & 3)
 244 #define netxen_set_msg_privid(config_word)      \
 245         ((config_word) |= 1 << 2)
 246 #define netxen_set_msg_count(config_word, val)  \
 247         ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 248 #define netxen_set_msg_ctxid(config_word, val)  \
 249         ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 250 #define netxen_set_msg_opcode(config_word, val) \
 251         ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 252
 253 struct netxen_rcv_ring {
 254         __le64 addr;
 255         __le32 size;
 256         __le32 rsrvd;
 257 };
 258
 259 struct netxen_sts_ring {
 260         __le64 addr;
 261         __le32 size;
 262         __le16 msi_index;
 263         __le16 rsvd;
 264 } ;
 265
 266 struct netxen_ring_ctx {
 267
 268         /* one command ring */
 269         __le64 cmd_consumer_offset;
 270         __le64 cmd_ring_addr;
 271         __le32 cmd_ring_size;
 272         __le32 rsrvd;
 273
 274         /* three receive rings */
 275         struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
 276
 277         __le64 sts_ring_addr;
 278         __le32 sts_ring_size;
 279
 280         __le32 ctx_id;
 281
 282         __le64 rsrvd_2[3];
 283         __le32 sts_ring_count;
 284         __le32 rsrvd_3;
 285         struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
 286
 287 } __attribute__ ((aligned(64)));
 288
 289 /*
 290  * Following data structures describe the descriptors that will be used.
 291  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 292  * we are doing LSO (above the 1500 size packet) only.
 293  */
 294
 295 /*
 296  * The size of reference handle been changed to 16 bits to pass the MSS fields
 297  * for the LSO packet
 298  */
 299
 300 #define FLAGS_CHECKSUM_ENABLED  0x01
 301 #define FLAGS_LSO_ENABLED       0x02
 302 #define FLAGS_IPSEC_SA_ADD      0x04
 303 #define FLAGS_IPSEC_SA_DELETE   0x08
 304 #define FLAGS_VLAN_TAGGED       0x10
 305
 306 #define netxen_set_cmd_desc_port(cmd_desc, var) \
 307         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 308 #define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 309         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 310
 311 #define netxen_set_tx_port(_desc, _port) \
 312         (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
 313
 314 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
 315         (_desc)->flags_opcode = \
 316         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
 317
 318 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
 319         (_desc)->num_of_buffers_total_length = \
 320         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
 321
 322 struct cmd_desc_type0 {
 323         u8 tcp_hdr_offset;      /* For LSO only */
 324         u8 ip_hdr_offset;       /* For LSO only */
 325         /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
 326         __le16 flags_opcode;
 327         /* Bit pattern: 0-7 total number of segments,
 328            8-31 Total size of the packet */
 329         __le32 num_of_buffers_total_length;
 330         union {
 331                 struct {
 332                         __le32 addr_low_part2;
 333                         __le32 addr_high_part2;
 334                 };
 335                 __le64 addr_buffer2;
 336         };
 337
 338         __le16 reference_handle;        /* changed to u16 to add mss */
 339         __le16 mss;             /* passed by NDIS_PACKET for LSO */
 340         /* Bit pattern 0-3 port, 0-3 ctx id */
 341         u8 port_ctxid;
 342         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 343         __le16 conn_id;         /* IPSec offoad only */
 344
 345         union {
 346                 struct {
 347                         __le32 addr_low_part3;
 348                         __le32 addr_high_part3;
 349                 };
 350                 __le64 addr_buffer3;
 351         };
 352         union {
 353                 struct {
 354                         __le32 addr_low_part1;
 355                         __le32 addr_high_part1;
 356                 };
 357                 __le64 addr_buffer1;
 358         };
 359
 360         __le16 buffer_length[4];
 361
 362         union {
 363                 struct {
 364                         __le32 addr_low_part4;
 365                         __le32 addr_high_part4;
 366                 };
 367                 __le64 addr_buffer4;
 368         };
 369
 370         __le64 unused;
 371
 372 } __attribute__ ((aligned(64)));
 373
 374 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 375 struct rcv_desc {
 376         __le16 reference_handle;
 377         __le16 reserved;
 378         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 379         __le64 addr_buffer;
 380 };
 381
 382 /* opcode field in status_desc */
 383 #define NETXEN_NIC_SYN_OFFLOAD  0x03
 384 #define NETXEN_NIC_RXPKT_DESC  0x04
 385 #define NETXEN_OLD_RXPKT_DESC  0x3f
 386 #define NETXEN_NIC_RESPONSE_DESC 0x05
 387
 388 /* for status field in status_desc */
 389 #define STATUS_NEED_CKSUM       (1)
 390 #define STATUS_CKSUM_OK         (2)
 391
 392 /* owner bits of status_desc */
 393 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 394 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 395
 396 /* Status descriptor:
 397    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 398    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 399    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 400  */
 401 #define netxen_get_sts_port(sts_data)   \
 402         ((sts_data) & 0x0F)
 403 #define netxen_get_sts_status(sts_data) \
 404         (((sts_data) >> 4) & 0x0F)
 405 #define netxen_get_sts_type(sts_data)   \
 406         (((sts_data) >> 8) & 0x0F)
 407 #define netxen_get_sts_totallength(sts_data)    \
 408         (((sts_data) >> 12) & 0xFFFF)
 409 #define netxen_get_sts_refhandle(sts_data)      \
 410         (((sts_data) >> 28) & 0xFFFF)
 411 #define netxen_get_sts_prot(sts_data)   \
 412         (((sts_data) >> 44) & 0x0F)
 413 #define netxen_get_sts_pkt_offset(sts_data)     \
 414         (((sts_data) >> 48) & 0x1F)
 415 #define netxen_get_sts_desc_cnt(sts_data)       \
 416         (((sts_data) >> 53) & 0x7)
 417 #define netxen_get_sts_opcode(sts_data) \
 418         (((sts_data) >> 58) & 0x03F)
 419
 420 struct status_desc {
 421         __le64 status_desc_data[2];
 422 } __attribute__ ((aligned(16)));
 423
 424 /* The version of the main data structure */
 425 #define NETXEN_BDINFO_VERSION 1
 426
 427 /* Magic number to let user know flash is programmed */
 428 #define NETXEN_BDINFO_MAGIC 0x12345678
 429
 430 /* Max number of Gig ports on a Phantom board */
 431 #define NETXEN_MAX_PORTS 4
 432
 433 #define NETXEN_BRDTYPE_P1_BD            0x0000
 434 #define NETXEN_BRDTYPE_P1_SB            0x0001
 435 #define NETXEN_BRDTYPE_P1_SMAX          0x0002
 436 #define NETXEN_BRDTYPE_P1_SOCK          0x0003
 437
 438 #define NETXEN_BRDTYPE_P2_SOCK_31       0x0008
 439 #define NETXEN_BRDTYPE_P2_SOCK_35       0x0009
 440 #define NETXEN_BRDTYPE_P2_SB35_4G       0x000a
 441 #define NETXEN_BRDTYPE_P2_SB31_10G      0x000b
 442 #define NETXEN_BRDTYPE_P2_SB31_2G       0x000c
 443
 444 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ         0x000d
 445 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ         0x000e
 446 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4          0x000f
 447
 448 #define NETXEN_BRDTYPE_P3_REF_QG        0x0021
 449 #define NETXEN_BRDTYPE_P3_HMEZ          0x0022
 450 #define NETXEN_BRDTYPE_P3_10G_CX4_LP    0x0023
 451 #define NETXEN_BRDTYPE_P3_4_GB          0x0024
 452 #define NETXEN_BRDTYPE_P3_IMEZ          0x0025
 453 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS  0x0026
 454 #define NETXEN_BRDTYPE_P3_10000_BASE_T  0x0027
 455 #define NETXEN_BRDTYPE_P3_XG_LOM        0x0028
 456 #define NETXEN_BRDTYPE_P3_4_GB_MM       0x0029
 457 #define NETXEN_BRDTYPE_P3_10G_SFP_CT    0x002a
 458 #define NETXEN_BRDTYPE_P3_10G_SFP_QT    0x002b
 459 #define NETXEN_BRDTYPE_P3_10G_CX4       0x0031
 460 #define NETXEN_BRDTYPE_P3_10G_XFP       0x0032
 461 #define NETXEN_BRDTYPE_P3_10G_TP        0x0080
 462
 463 struct netxen_board_info {
 464         u32 header_version;
 465
 466         u32 board_mfg;
 467         u32 board_type;
 468         u32 board_num;
 469         u32 chip_id;
 470         u32 chip_minor;
 471         u32 chip_major;
 472         u32 chip_pkg;
 473         u32 chip_lot;
 474
 475         u32 port_mask;          /* available niu ports */
 476         u32 peg_mask;           /* available pegs */
 477         u32 icache_ok;          /* can we run with icache? */
 478         u32 dcache_ok;          /* can we run with dcache? */
 479         u32 casper_ok;
 480
 481         u32 mac_addr_lo_0;
 482         u32 mac_addr_lo_1;
 483         u32 mac_addr_lo_2;
 484         u32 mac_addr_lo_3;
 485
 486         /* MN-related config */
 487         u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 488         u32 mn_sync_shift_cclk;
 489         u32 mn_sync_shift_mclk;
 490         u32 mn_wb_en;
 491         u32 mn_crystal_freq;    /* in MHz */
 492         u32 mn_speed;           /* in MHz */
 493         u32 mn_org;
 494         u32 mn_depth;
 495         u32 mn_ranks_0;         /* ranks per slot */
 496         u32 mn_ranks_1;         /* ranks per slot */
 497         u32 mn_rd_latency_0;
 498         u32 mn_rd_latency_1;
 499         u32 mn_rd_latency_2;
 500         u32 mn_rd_latency_3;
 501         u32 mn_rd_latency_4;
 502         u32 mn_rd_latency_5;
 503         u32 mn_rd_latency_6;
 504         u32 mn_rd_latency_7;
 505         u32 mn_rd_latency_8;
 506         u32 mn_dll_val[18];
 507         u32 mn_mode_reg;        /* MIU DDR Mode Register */
 508         u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 509         u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 510         u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 511         u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 512
 513         /* SN-related config */
 514         u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 515         u32 sn_pt_mode;         /* pass through mode */
 516         u32 sn_ecc_en;
 517         u32 sn_wb_en;
 518         u32 sn_crystal_freq;
 519         u32 sn_speed;
 520         u32 sn_org;
 521         u32 sn_depth;
 522         u32 sn_dll_tap;
 523         u32 sn_rd_latency;
 524
 525         u32 mac_addr_hi_0;
 526         u32 mac_addr_hi_1;
 527         u32 mac_addr_hi_2;
 528         u32 mac_addr_hi_3;
 529
 530         u32 magic;              /* indicates flash has been initialized */
 531
 532         u32 mn_rdimm;
 533         u32 mn_dll_override;
 534
 535 };
 536
 537 #define FLASH_NUM_PORTS         (4)
 538
 539 struct netxen_flash_mac_addr {
 540         u32 flash_addr[32];
 541 };
 542
 543 struct netxen_user_old_info {
 544         u8 flash_md5[16];
 545         u8 crbinit_md5[16];
 546         u8 brdcfg_md5[16];
 547         /* bootloader */
 548         u32 bootld_version;
 549         u32 bootld_size;
 550         u8 bootld_md5[16];
 551         /* image */
 552         u32 image_version;
 553         u32 image_size;
 554         u8 image_md5[16];
 555         /* primary image status */
 556         u32 primary_status;
 557         u32 secondary_present;
 558
 559         /* MAC address , 4 ports */
 560         struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 561 };
 562 #define FLASH_NUM_MAC_PER_PORT  32
 563 struct netxen_user_info {
 564         u8 flash_md5[16 * 64];
 565         /* bootloader */
 566         u32 bootld_version;
 567         u32 bootld_size;
 568         /* image */
 569         u32 image_version;
 570         u32 image_size;
 571         /* primary image status */
 572         u32 primary_status;
 573         u32 secondary_present;
 574
 575         /* MAC address , 4 ports, 32 address per port */
 576         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 577         u32 sub_sys_id;
 578         u8 serial_num[32];
 579
 580         /* Any user defined data */
 581 };
 582
 583 /*
 584  * Flash Layout - new format.
 585  */
 586 struct netxen_new_user_info {
 587         u8 flash_md5[16 * 64];
 588         /* bootloader */
 589         u32 bootld_version;
 590         u32 bootld_size;
 591         /* image */
 592         u32 image_version;
 593         u32 image_size;
 594         /* primary image status */
 595         u32 primary_status;
 596         u32 secondary_present;
 597
 598         /* MAC address , 4 ports, 32 address per port */
 599         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 600         u32 sub_sys_id;
 601         u8 serial_num[32];
 602
 603         /* Any user defined data */
 604 };
 605
 606 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 607 #define SECONDARY_IMAGE_ABSENT  0xffffffff
 608 #define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 609 #define PRIMARY_IMAGE_BAD       0xffffffff
 610
 611 /* Flash memory map */
 612 #define NETXEN_CRBINIT_START    0       /* crbinit section */
 613 #define NETXEN_BRDCFG_START     0x4000  /* board config */
 614 #define NETXEN_INITCODE_START   0x6000  /* pegtune code */
 615 #define NETXEN_BOOTLD_START     0x10000 /* bootld */
 616 #define NETXEN_IMAGE_START      0x43000 /* compressed image */
 617 #define NETXEN_SECONDARY_START  0x200000        /* backup images */
 618 #define NETXEN_PXE_START        0x3E0000        /* PXE boot rom */
 619 #define NETXEN_USER_START       0x3E8000        /* Firmare info */
 620 #define NETXEN_FIXED_START      0x3F0000        /* backup of crbinit */
 621
 622 #define NX_FW_VERSION_OFFSET    (NETXEN_USER_START+0x408)
 623 #define NX_FW_SIZE_OFFSET       (NETXEN_USER_START+0x40c)
 624 #define NX_BIOS_VERSION_OFFSET  (NETXEN_USER_START+0x83c)
 625 #define NX_FW_MAGIC_OFFSET      (NETXEN_BRDCFG_START+0x128)
 626 #define NX_FW_MIN_SIZE          (0x3fffff)
 627 #define NX_P2_MN_ROMIMAGE       0
 628 #define NX_P3_CT_ROMIMAGE       1
 629 #define NX_P3_MN_ROMIMAGE       2
 630 #define NX_FLASH_ROMIMAGE       3
 631
 632 #define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 633
 634 #define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 635 #define NETXEN_INIT_SECTOR              (0)
 636 #define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 637 #define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 638 #define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 639 #define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 640 #define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 641 #define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 642 #define NETXEN_NUM_CONFIG_SECTORS       (1)
 643 extern char netxen_nic_driver_name[];
 644
 645 /* Number of status descriptors to handle per interrupt */
 646 #define MAX_STATUS_HANDLE       (64)
 647
 648 /*
 649  * netxen_skb_frag{} is to contain mapping info for each SG list. This
 650  * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 651  */
 652 struct netxen_skb_frag {
 653         u64 dma;
 654         u64 length;
 655 };
 656
 657 #define _netxen_set_bits(config_word, start, bits, val) {\
 658         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 659         unsigned long long __tvalue = (val);    \
 660         (config_word) &= ~__tmask;      \
 661         (config_word) |= (((__tvalue) << (start)) & __tmask); \
 662 }
 663
 664 #define _netxen_clear_bits(config_word, start, bits) {\
 665         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 666         (config_word) &= ~__tmask; \
 667 }
 668
 669 /*    Following defines are for the state of the buffers    */
 670 #define NETXEN_BUFFER_FREE      0
 671 #define NETXEN_BUFFER_BUSY      1
 672
 673 /*
 674  * There will be one netxen_buffer per skb packet.    These will be
 675  * used to save the dma info for pci_unmap_page()
 676  */
 677 struct netxen_cmd_buffer {
 678         struct sk_buff *skb;
 679         struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 680         u32 frag_count;
 681 };
 682
 683 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 684 struct netxen_rx_buffer {
 685         struct list_head list;
 686         struct sk_buff *skb;
 687         u64 dma;
 688         u16 ref_handle;
 689         u16 state;
 690 };
 691
 692 /* Board types */
 693 #define NETXEN_NIC_GBE  0x01
 694 #define NETXEN_NIC_XGBE 0x02
 695
 696 /*
 697  * One hardware_context{} per adapter
 698  * contains interrupt info as well shared hardware info.
 699  */
 700 struct netxen_hardware_context {
 701         void __iomem *pci_base0;
 702         void __iomem *pci_base1;
 703         void __iomem *pci_base2;
 704         void __iomem *db_base;
 705         unsigned long db_len;
 706         unsigned long pci_len0;
 707
 708         int qdr_sn_window;
 709         int ddr_mn_window;
 710         unsigned long mn_win_crb;
 711         unsigned long ms_win_crb;
 712
 713         u8 cut_through;
 714         u8 revision_id;
 715         u8 pci_func;
 716         u8 linkup;
 717         u16 port_type;
 718         u16 board_type;
 719 };
 720
 721 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 722 #define ETHERNET_FCS_SIZE               4
 723
 724 struct netxen_adapter_stats {
 725         u64  xmitcalled;
 726         u64  xmitfinished;
 727         u64  rxdropped;
 728         u64  txdropped;
 729         u64  csummed;
 730         u64  no_rcv;
 731         u64  rxbytes;
 732         u64  txbytes;
 733 };
 734
 735 /*
 736  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 737  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 738  */
 739 struct nx_host_rds_ring {
 740         u32 producer;
 741         u32 crb_rcv_producer;
 742         u32 num_desc;
 743         u32 dma_size;
 744         u32 skb_size;
 745         u32 flags;
 746         struct rcv_desc *desc_head;
 747         struct netxen_rx_buffer *rx_buf_arr;
 748         struct list_head free_list;
 749         spinlock_t lock;
 750         dma_addr_t phys_addr;
 751 };
 752
 753 struct nx_host_sds_ring {
 754         u32 consumer;
 755         u32 crb_sts_consumer;
 756         u32 crb_intr_mask;
 757         u32 num_desc;
 758
 759         struct status_desc *desc_head;
 760         struct netxen_adapter *adapter;
 761         struct napi_struct napi;
 762         struct list_head free_list[NUM_RCV_DESC_RINGS];
 763
 764         int irq;
 765
 766         dma_addr_t phys_addr;
 767         char name[IFNAMSIZ+4];
 768 };
 769
 770 struct nx_host_tx_ring {
 771         u32 producer;
 772         __le32 *hw_consumer;
 773         u32 sw_consumer;
 774         u32 crb_cmd_producer;
 775         u32 crb_cmd_consumer;
 776         u32 num_desc;
 777
 778         struct netdev_queue *txq;
 779
 780         struct netxen_cmd_buffer *cmd_buf_arr;
 781         struct cmd_desc_type0 *desc_head;
 782         dma_addr_t phys_addr;
 783 };
 784
 785 /*
 786  * Receive context. There is one such structure per instance of the
 787  * receive processing. Any state information that is relevant to
 788  * the receive, and is must be in this structure. The global data may be
 789  * present elsewhere.
 790  */
 791 struct netxen_recv_context {
 792         u32 state;
 793         u16 context_id;
 794         u16 virt_port;
 795
 796         struct nx_host_rds_ring *rds_rings;
 797         struct nx_host_sds_ring *sds_rings;
 798
 799         struct netxen_ring_ctx *hwctx;
 800         dma_addr_t phys_addr;
 801 };
 802
 803 /* New HW context creation */
 804
 805 #define NX_OS_CRB_RETRY_COUNT   4000
 806 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 807         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 808
 809 #define NX_CDRP_CLEAR           0x00000000
 810 #define NX_CDRP_CMD_BIT         0x80000000
 811
 812 /*
 813  * All responses must have the NX_CDRP_CMD_BIT cleared
 814  * in the crb NX_CDRP_CRB_OFFSET.
 815  */
 816 #define NX_CDRP_FORM_RSP(rsp)   (rsp)
 817 #define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 818
 819 #define NX_CDRP_RSP_OK          0x00000001
 820 #define NX_CDRP_RSP_FAIL        0x00000002
 821 #define NX_CDRP_RSP_TIMEOUT     0x00000003
 822
 823 /*
 824  * All commands must have the NX_CDRP_CMD_BIT set in
 825  * the crb NX_CDRP_CRB_OFFSET.
 826  */
 827 #define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 828 #define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 829
 830 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 831 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 832 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 833 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 834 #define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 835 #define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 836 #define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 837 #define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 838 #define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 839 #define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 840 #define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 841 #define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 842 #define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 843 #define NX_CDRP_CMD_SET_MTU                 0x00000012
 844 #define NX_CDRP_CMD_MAX                     0x00000013
 845
 846 #define NX_RCODE_SUCCESS                0
 847 #define NX_RCODE_NO_HOST_MEM            1
 848 #define NX_RCODE_NO_HOST_RESOURCE       2
 849 #define NX_RCODE_NO_CARD_CRB            3
 850 #define NX_RCODE_NO_CARD_MEM            4
 851 #define NX_RCODE_NO_CARD_RESOURCE       5
 852 #define NX_RCODE_INVALID_ARGS           6
 853 #define NX_RCODE_INVALID_ACTION         7
 854 #define NX_RCODE_INVALID_STATE          8
 855 #define NX_RCODE_NOT_SUPPORTED          9
 856 #define NX_RCODE_NOT_PERMITTED          10
 857 #define NX_RCODE_NOT_READY              11
 858 #define NX_RCODE_DOES_NOT_EXIST         12
 859 #define NX_RCODE_ALREADY_EXISTS         13
 860 #define NX_RCODE_BAD_SIGNATURE          14
 861 #define NX_RCODE_CMD_NOT_IMPL           15
 862 #define NX_RCODE_CMD_INVALID            16
 863 #define NX_RCODE_TIMEOUT                17
 864 #define NX_RCODE_CMD_FAILED             18
 865 #define NX_RCODE_MAX_EXCEEDED           19
 866 #define NX_RCODE_MAX                    20
 867
 868 #define NX_DESTROY_CTX_RESET            0
 869 #define NX_DESTROY_CTX_D3_RESET         1
 870 #define NX_DESTROY_CTX_MAX              2
 871
 872 /*
 873  * Capabilities
 874  */
 875 #define NX_CAP_BIT(class, bit)          (1 << bit)
 876 #define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 877 #define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 878 #define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 879 #define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 880 #define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 881 #define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 882 #define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 883 #define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 884 #define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 885
 886 /*
 887  * Context state
 888  */
 889 #define NX_HOST_CTX_STATE_FREED         0
 890 #define NX_HOST_CTX_STATE_ALLOCATED     1
 891 #define NX_HOST_CTX_STATE_ACTIVE        2
 892 #define NX_HOST_CTX_STATE_DISABLED      3
 893 #define NX_HOST_CTX_STATE_QUIESCED      4
 894 #define NX_HOST_CTX_STATE_MAX           5
 895
 896 /*
 897  * Rx context
 898  */
 899
 900 typedef struct {
 901         __le64 host_phys_addr;  /* Ring base addr */
 902         __le32 ring_size;               /* Ring entries */
 903         __le16 msi_index;
 904         __le16 rsvd;            /* Padding */
 905 } nx_hostrq_sds_ring_t;
 906
 907 typedef struct {
 908         __le64 host_phys_addr;  /* Ring base addr */
 909         __le64 buff_size;               /* Packet buffer size */
 910         __le32 ring_size;               /* Ring entries */
 911         __le32 ring_kind;               /* Class of ring */
 912 } nx_hostrq_rds_ring_t;
 913
 914 typedef struct {
 915         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 916         __le32 capabilities[4]; /* Flag bit vector */
 917         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 918         __le32 host_rds_crb_mode;       /* RDS crb usage */
 919         /* These ring offsets are relative to data[0] below */
 920         __le32 rds_ring_offset; /* Offset to RDS config */
 921         __le32 sds_ring_offset; /* Offset to SDS config */
 922         __le16 num_rds_rings;   /* Count of RDS rings */
 923         __le16 num_sds_rings;   /* Count of SDS rings */
 924         __le16 rsvd1;           /* Padding */
 925         __le16 rsvd2;           /* Padding */
 926         u8  reserved[128];      /* reserve space for future expansion*/
 927         /* MUST BE 64-bit aligned.
 928            The following is packed:
 929            - N hostrq_rds_rings
 930            - N hostrq_sds_rings */
 931         char data[0];
 932 } nx_hostrq_rx_ctx_t;
 933
 934 typedef struct {
 935         __le32 host_producer_crb;       /* Crb to use */
 936         __le32 rsvd1;           /* Padding */
 937 } nx_cardrsp_rds_ring_t;
 938
 939 typedef struct {
 940         __le32 host_consumer_crb;       /* Crb to use */
 941         __le32 interrupt_crb;   /* Crb to use */
 942 } nx_cardrsp_sds_ring_t;
 943
 944 typedef struct {
 945         /* These ring offsets are relative to data[0] below */
 946         __le32 rds_ring_offset; /* Offset to RDS config */
 947         __le32 sds_ring_offset; /* Offset to SDS config */
 948         __le32 host_ctx_state;  /* Starting State */
 949         __le32 num_fn_per_port; /* How many PCI fn share the port */
 950         __le16 num_rds_rings;   /* Count of RDS rings */
 951         __le16 num_sds_rings;   /* Count of SDS rings */
 952         __le16 context_id;              /* Handle for context */
 953         u8  phys_port;          /* Physical id of port */
 954         u8  virt_port;          /* Virtual/Logical id of port */
 955         u8  reserved[128];      /* save space for future expansion */
 956         /*  MUST BE 64-bit aligned.
 957            The following is packed:
 958            - N cardrsp_rds_rings
 959            - N cardrs_sds_rings */
 960         char data[0];
 961 } nx_cardrsp_rx_ctx_t;
 962
 963 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 964         (sizeof(HOSTRQ_RX) +                                    \
 965         (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
 966         (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
 967
 968 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 969         (sizeof(CARDRSP_RX) +                                   \
 970         (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
 971         (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
 972
 973 /*
 974  * Tx context
 975  */
 976
 977 typedef struct {
 978         __le64 host_phys_addr;  /* Ring base addr */
 979         __le32 ring_size;               /* Ring entries */
 980         __le32 rsvd;            /* Padding */
 981 } nx_hostrq_cds_ring_t;
 982
 983 typedef struct {
 984         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 985         __le64 cmd_cons_dma_addr;       /*  */
 986         __le64 dummy_dma_addr;  /*  */
 987         __le32 capabilities[4]; /* Flag bit vector */
 988         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 989         __le32 rsvd1;           /* Padding */
 990         __le16 rsvd2;           /* Padding */
 991         __le16 interrupt_ctl;
 992         __le16 msi_index;
 993         __le16 rsvd3;           /* Padding */
 994         nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
 995         u8  reserved[128];      /* future expansion */
 996 } nx_hostrq_tx_ctx_t;
 997
 998 typedef struct {
 999         __le32 host_producer_crb;       /* Crb to use */
1000         __le32 interrupt_crb;   /* Crb to use */
1001 } nx_cardrsp_cds_ring_t;
1002
1003 typedef struct {
1004         __le32 host_ctx_state;  /* Starting state */
1005         __le16 context_id;              /* Handle for context */
1006         u8  phys_port;          /* Physical id of port */
1007         u8  virt_port;          /* Virtual/Logical id of port */
1008         nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1009         u8  reserved[128];      /* future expansion */
1010 } nx_cardrsp_tx_ctx_t;
1011
1012 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
1013 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
1014
1015 /* CRB */
1016
1017 #define NX_HOST_RDS_CRB_MODE_UNIQUE     0
1018 #define NX_HOST_RDS_CRB_MODE_SHARED     1
1019 #define NX_HOST_RDS_CRB_MODE_CUSTOM     2
1020 #define NX_HOST_RDS_CRB_MODE_MAX        3
1021
1022 #define NX_HOST_INT_CRB_MODE_UNIQUE     0
1023 #define NX_HOST_INT_CRB_MODE_SHARED     1
1024 #define NX_HOST_INT_CRB_MODE_NORX       2
1025 #define NX_HOST_INT_CRB_MODE_NOTX       3
1026 #define NX_HOST_INT_CRB_MODE_NORXTX     4
1027
1028
1029 /* MAC */
1030
1031 #define MC_COUNT_P2     16
1032 #define MC_COUNT_P3     38
1033
1034 #define NETXEN_MAC_NOOP 0
1035 #define NETXEN_MAC_ADD  1
1036 #define NETXEN_MAC_DEL  2
1037
1038 typedef struct nx_mac_list_s {
1039         struct list_head list;
1040         uint8_t mac_addr[ETH_ALEN+2];
1041 } nx_mac_list_t;
1042
1043 /*
1044  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1045  * adjusted based on configured MTU.
1046  */
1047 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1048 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1049 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1050 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1051
1052 #define NETXEN_NIC_INTR_DEFAULT                 0x04
1053
1054 typedef union {
1055         struct {
1056                 uint16_t        rx_packets;
1057                 uint16_t        rx_time_us;
1058                 uint16_t        tx_packets;
1059                 uint16_t        tx_time_us;
1060         } data;
1061         uint64_t                word;
1062 } nx_nic_intr_coalesce_data_t;
1063
1064 typedef struct {
1065         uint16_t                        stats_time_us;
1066         uint16_t                        rate_sample_time;
1067         uint16_t                        flags;
1068         uint16_t                        rsvd_1;
1069         uint32_t                        low_threshold;
1070         uint32_t                        high_threshold;
1071         nx_nic_intr_coalesce_data_t     normal;
1072         nx_nic_intr_coalesce_data_t     low;
1073         nx_nic_intr_coalesce_data_t     high;
1074         nx_nic_intr_coalesce_data_t     irq;
1075 } nx_nic_intr_coalesce_t;
1076
1077 #define NX_HOST_REQUEST         0x13
1078 #define NX_NIC_REQUEST          0x14
1079
1080 #define NX_MAC_EVENT            0x1
1081
1082 #define NX_IP_UP                2
1083 #define NX_IP_DOWN              3
1084
1085 /*
1086  * Driver --> Firmware
1087  */
1088 #define NX_NIC_H2C_OPCODE_START                         0
1089 #define NX_NIC_H2C_OPCODE_CONFIG_RSS                    1
1090 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL                2
1091 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE          3
1092 #define NX_NIC_H2C_OPCODE_CONFIG_LED                    4
1093 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS            5
1094 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC                 6
1095 #define NX_NIC_H2C_OPCODE_LRO_REQUEST                   7
1096 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS                8
1097 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST           9
1098 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST            10
1099 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU                 11
1100 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE     12
1101 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST      13
1102 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST       14
1103 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST        15
1104 #define NX_NIC_H2C_OPCODE_GET_NET_STATS                 16
1105 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
1106 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR                 18
1107 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK               19
1108 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE               20
1109 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT                 21
1110 #define NX_NIC_C2C_OPCODE                               22
1111 #define NX_NIC_H2C_OPCODE_LAST                          23
1112
1113 /*
1114  * Firmware --> Driver
1115  */
1116
1117 #define NX_NIC_C2H_OPCODE_START                         128
1118 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE           129
1119 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE       130
1120 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE           131
1121 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE   132
1122 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE        133
1123 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE           134
1124 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE      135
1125 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS                136
1126 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY        137
1127 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY         138
1128 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1129 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE        140
1130 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
1131 #define NX_NIC_C2H_OPCODE_LAST                          142
1132
1133 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1134 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1135 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1136
1137 #define NX_FW_CAPABILITY_LINK_NOTIFICATION      (1 << 5)
1138 #define NX_FW_CAPABILITY_SWITCHING              (1 << 6)
1139
1140 /* module types */
1141 #define LINKEVENT_MODULE_NOT_PRESENT                    1
1142 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
1143 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
1144 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
1145 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
1146 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
1147 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
1148 #define LINKEVENT_MODULE_TWINAX                         8
1149
1150 #define LINKSPEED_10GBPS        10000
1151 #define LINKSPEED_1GBPS         1000
1152 #define LINKSPEED_100MBPS       100
1153 #define LINKSPEED_10MBPS        10
1154
1155 #define LINKSPEED_ENCODED_10MBPS        0
1156 #define LINKSPEED_ENCODED_100MBPS       1
1157 #define LINKSPEED_ENCODED_1GBPS         2
1158
1159 #define LINKEVENT_AUTONEG_DISABLED      0
1160 #define LINKEVENT_AUTONEG_ENABLED       1
1161
1162 #define LINKEVENT_HALF_DUPLEX           0
1163 #define LINKEVENT_FULL_DUPLEX           1
1164
1165 #define LINKEVENT_LINKSPEED_MBPS        0
1166 #define LINKEVENT_LINKSPEED_ENCODED     1
1167
1168 /* firmware response header:
1169  *      63:58 - message type
1170  *      57:56 - owner
1171  *      55:53 - desc count
1172  *      52:48 - reserved
1173  *      47:40 - completion id
1174  *      39:32 - opcode
1175  *      31:16 - error code
1176  *      15:00 - reserved
1177  */
1178 #define netxen_get_nic_msgtype(msg_hdr) \
1179         ((msg_hdr >> 58) & 0x3F)
1180 #define netxen_get_nic_msg_compid(msg_hdr)      \
1181         ((msg_hdr >> 40) & 0xFF)
1182 #define netxen_get_nic_msg_opcode(msg_hdr)      \
1183         ((msg_hdr >> 32) & 0xFF)
1184 #define netxen_get_nic_msg_errcode(msg_hdr)     \
1185         ((msg_hdr >> 16) & 0xFFFF)
1186
1187 typedef struct {
1188         union {
1189                 struct {
1190                         u64 hdr;
1191                         u64 body[7];
1192                 };
1193                 u64 words[8];
1194         };
1195 } nx_fw_msg_t;
1196
1197 typedef struct {
1198         __le64 qhdr;
1199         __le64 req_hdr;
1200         __le64 words[6];
1201 } nx_nic_req_t;
1202
1203 typedef struct {
1204         u8 op;
1205         u8 tag;
1206         u8 mac_addr[6];
1207 } nx_mac_req_t;
1208
1209 #define MAX_PENDING_DESC_BLOCK_SIZE     64
1210
1211 #define NETXEN_NIC_MSI_ENABLED          0x02
1212 #define NETXEN_NIC_MSIX_ENABLED         0x04
1213 #define NETXEN_IS_MSI_FAMILY(adapter) \
1214         ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1215
1216 #define MSIX_ENTRIES_PER_ADAPTER        NUM_STS_DESC_RINGS
1217 #define NETXEN_MSIX_TBL_SPACE           8192
1218 #define NETXEN_PCI_REG_MSIX_TBL         0x44
1219
1220 #define NETXEN_DB_MAPSIZE_BYTES         0x1000
1221
1222 #define NETXEN_NETDEV_WEIGHT 128
1223 #define NETXEN_ADAPTER_UP_MAGIC 777
1224 #define NETXEN_NIC_PEG_TUNE 0
1225
1226 struct netxen_dummy_dma {
1227         void *addr;
1228         dma_addr_t phys_addr;
1229 };
1230
1231 struct netxen_adapter {
1232         struct netxen_hardware_context ahw;
1233
1234         struct net_device *netdev;
1235         struct pci_dev *pdev;
1236         struct list_head mac_list;
1237
1238         u32 curr_window;
1239         u32 crb_win;
1240         rwlock_t adapter_lock;
1241
1242         spinlock_t tx_clean_lock;
1243
1244         u16 num_txd;
1245         u16 num_rxd;
1246         u16 num_jumbo_rxd;
1247         u16 num_lro_rxd;
1248
1249         u8 max_rds_rings;
1250         u8 max_sds_rings;
1251         u8 driver_mismatch;
1252         u8 msix_supported;
1253         u8 rx_csum;
1254         u8 pci_using_dac;
1255         u8 portnum;
1256         u8 physical_port;
1257
1258         u8 mc_enabled;
1259         u8 max_mc_count;
1260         u8 rss_supported;
1261         u8 resv2;
1262         u32 resv3;
1263
1264         u8 has_link_events;
1265         u8 fw_type;
1266         u16 tx_context_id;
1267         u16 mtu;
1268         u16 is_up;
1269
1270         u16 link_speed;
1271         u16 link_duplex;
1272         u16 link_autoneg;
1273         u16 module_type;
1274
1275         u32 capabilities;
1276         u32 flags;
1277         u32 irq;
1278         u32 temp;
1279
1280         u32 msi_tgt_status;
1281         u32 resv4;
1282
1283         struct netxen_adapter_stats stats;
1284
1285         struct netxen_recv_context recv_ctx;
1286         struct nx_host_tx_ring *tx_ring;
1287
1288         int (*enable_phy_interrupts) (struct netxen_adapter *);
1289         int (*disable_phy_interrupts) (struct netxen_adapter *);
1290         int (*macaddr_set) (struct netxen_adapter *, u8 *);
1291         int (*set_mtu) (struct netxen_adapter *, int);
1292         int (*set_promisc) (struct netxen_adapter *, u32);
1293         void (*set_multi) (struct net_device *);
1294         int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1295         int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1296         int (*init_port) (struct netxen_adapter *, int);
1297         int (*stop_port) (struct netxen_adapter *);
1298
1299         u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1300         int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1301         int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1302         int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1303         int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1304         u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1305         unsigned long (*pci_set_window)(struct netxen_adapter *,
1306                         unsigned long long);
1307
1308         struct netxen_legacy_intr_set legacy_intr;
1309
1310         struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1311
1312         struct netxen_dummy_dma dummy_dma;
1313
1314         struct work_struct watchdog_task;
1315         struct timer_list watchdog_timer;
1316         struct work_struct  tx_timeout_task;
1317
1318         struct net_device_stats net_stats;
1319
1320         nx_nic_intr_coalesce_t coal;
1321
1322         u32 fw_major;
1323         u32 fw_version;
1324         const struct firmware *fw;
1325 };
1326
1327 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1328 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1329 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1330 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1331 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1332                             __u32 * readval);
1333 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1334                              long reg, __u32 val);
1335
1336 /* Functions available from netxen_nic_hw.c */
1337 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1338 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1339
1340 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1341 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1342
1343 #define NXRD32(adapter, off) \
1344         (adapter->hw_read_wx(adapter, off))
1345 #define NXWR32(adapter, off, val) \
1346         (adapter->hw_write_wx(adapter, off, val))
1347
1348 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1349 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1350 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1351
1352 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1353 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1354                 ulong off, u32 data);
1355 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1356                 u64 off, void *data, int size);
1357 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1358                 u64 off, void *data, int size);
1359 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1360                 u64 off, u32 data);
1361 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1362 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1363                 u64 off, u32 data);
1364 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1365 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1366                 unsigned long long addr);
1367 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1368                 u32 wndw);
1369
1370 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1371 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1372                 ulong off, u32 data);
1373 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1374                 u64 off, void *data, int size);
1375 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1376                 u64 off, void *data, int size);
1377 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1378                 u64 off, u32 data);
1379 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1380 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1381                 u64 off, u32 data);
1382 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1383 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1384                 unsigned long long addr);
1385
1386 /* Functions from netxen_nic_init.c */
1387 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1388 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1389
1390 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1391 int netxen_load_firmware(struct netxen_adapter *adapter);
1392 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1393 void netxen_request_firmware(struct netxen_adapter *adapter);
1394 void netxen_release_firmware(struct netxen_adapter *adapter);
1395 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1396
1397 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1398 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1399                                 u8 *bytes, size_t size);
1400 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1401                                 u8 *bytes, size_t size);
1402 int netxen_flash_unlock(struct netxen_adapter *adapter);
1403 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1404 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1405 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1406 void netxen_halt_pegs(struct netxen_adapter *adapter);
1407
1408 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1409
1410 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1411 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1412
1413 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1414 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1415
1416 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1417 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1418
1419 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1420 int netxen_init_firmware(struct netxen_adapter *adapter);
1421 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1422 void netxen_watchdog_task(struct work_struct *work);
1423 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1424                 struct nx_host_rds_ring *rds_ring);
1425 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1426 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1427 void netxen_p2_nic_set_multi(struct net_device *netdev);
1428 void netxen_p3_nic_set_multi(struct net_device *netdev);
1429 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1430 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1431 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1432 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1433 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1434 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1435 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1436
1437 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1438 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1439
1440 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1441 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1442
1443 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1444                 struct nx_host_tx_ring *tx_ring);
1445
1446 /*
1447  * NetXen Board information
1448  */
1449
1450 #define NETXEN_MAX_SHORT_NAME 32
1451 struct netxen_brdinfo {
1452         int brdtype;    /* type of board */
1453         long ports;             /* max no of physical ports */
1454         char short_name[NETXEN_MAX_SHORT_NAME];
1455 };
1456
1457 static const struct netxen_brdinfo netxen_boards[] = {
1458         {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1459         {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1460         {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1461         {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1462         {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1463         {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1464         {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1465         {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1466         {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1467         {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1468         {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1469         {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1470         {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1471         {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1472         {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1473         {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1474         {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1475         {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1476         {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1477 };
1478
1479 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1480
1481 static inline void get_brd_name_by_type(u32 type, char *name)
1482 {
1483         int i, found = 0;
1484         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1485                 if (netxen_boards[i].brdtype == type) {
1486                         strcpy(name, netxen_boards[i].short_name);
1487                         found = 1;
1488                         break;
1489                 }
1490
1491         }
1492         if (!found)
1493                 name = "Unknown";
1494 }
1495
1496 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1497 {
1498         smp_mb();
1499         return find_diff_among(tx_ring->producer,
1500                         tx_ring->sw_consumer, tx_ring->num_desc);
1501
1502 }
1503
1504 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1505 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1506 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1507 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1508                                 int *valp);
1509
1510 extern struct ethtool_ops netxen_nic_ethtool_ops;
1511
1512 #endif                          /* __NETXEN_NIC_H_ */