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[deliverable/linux.git] / drivers / net / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.
23 *
24 */
25
26 #ifndef _NETXEN_NIC_H_
27 #define _NETXEN_NIC_H_
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/ioport.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ip.h>
37 #include <linux/in.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/firmware.h>
41
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/timer.h>
45
46 #include <linux/vmalloc.h>
47
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50
51 #include "netxen_nic_hdr.h"
52 #include "netxen_nic_hw.h"
53
54 #define _NETXEN_NIC_LINUX_MAJOR 4
55 #define _NETXEN_NIC_LINUX_MINOR 0
56 #define _NETXEN_NIC_LINUX_SUBVERSION 62
57 #define NETXEN_NIC_LINUX_VERSIONID "4.0.62"
58
59 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60 #define _major(v) (((v) >> 24) & 0xff)
61 #define _minor(v) (((v) >> 16) & 0xff)
62 #define _build(v) ((v) & 0xffff)
63
64 /* version in image has weird encoding:
65 * 7:0 - major
66 * 15:8 - minor
67 * 31:16 - build (little endian)
68 */
69 #define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72 #define NETXEN_NUM_FLASH_SECTORS (64)
73 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
89
90 #define NETXEN_RCV_PRODUCER_OFFSET 0
91 #define NETXEN_RCV_PEG_DB_ID 2
92 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
93 #define FLASH_SUCCESS 0
94
95 #define ADDR_IN_WINDOW1(off) \
96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
97
98 /*
99 * normalize a 64MB crb address to 32MB PCI window
100 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
101 */
102 #define NETXEN_CRB_NORMAL(reg) \
103 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
104
105 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
106 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
107
108 #define DB_NORMALIZE(adapter, off) \
109 (adapter->ahw.db_base + (off))
110
111 #define NX_P2_C0 0x24
112 #define NX_P2_C1 0x25
113 #define NX_P3_A0 0x30
114 #define NX_P3_A2 0x30
115 #define NX_P3_B0 0x40
116 #define NX_P3_B1 0x41
117 #define NX_P3_B2 0x42
118 #define NX_P3P_A0 0x50
119
120 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
121 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
122 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
123
124 #define FIRST_PAGE_GROUP_START 0
125 #define FIRST_PAGE_GROUP_END 0x100000
126
127 #define SECOND_PAGE_GROUP_START 0x6000000
128 #define SECOND_PAGE_GROUP_END 0x68BC000
129
130 #define THIRD_PAGE_GROUP_START 0x70E4000
131 #define THIRD_PAGE_GROUP_END 0x8000000
132
133 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
134 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
135 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
136
137 #define P2_MAX_MTU (8000)
138 #define P3_MAX_MTU (9600)
139 #define NX_ETHERMTU 1500
140 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
141
142 #define NX_P2_RX_BUF_MAX_LEN 1760
143 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
144 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
145 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
146 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
147 #define NX_LRO_BUFFER_EXTRA 2048
148
149 #define NX_RX_LRO_BUFFER_LENGTH (8060)
150
151 /*
152 * Maximum number of ring contexts
153 */
154 #define MAX_RING_CTX 1
155
156 /* Opcodes to be used with the commands */
157 #define TX_ETHER_PKT 0x01
158 #define TX_TCP_PKT 0x02
159 #define TX_UDP_PKT 0x03
160 #define TX_IP_PKT 0x04
161 #define TX_TCP_LSO 0x05
162 #define TX_TCP_LSO6 0x06
163 #define TX_IPSEC 0x07
164 #define TX_IPSEC_CMD 0x0a
165 #define TX_TCPV6_PKT 0x0b
166 #define TX_UDPV6_PKT 0x0c
167
168 /* The following opcodes are for internal consumption. */
169 #define NETXEN_CONTROL_OP 0x10
170 #define PEGNET_REQUEST 0x11
171
172 #define MAX_NUM_CARDS 4
173
174 #define MAX_BUFFERS_PER_CMD 32
175 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
176 #define NX_MAX_TX_TIMEOUTS 2
177
178 /*
179 * Following are the states of the Phantom. Phantom will set them and
180 * Host will read to check if the fields are correct.
181 */
182 #define PHAN_INITIALIZE_START 0xff00
183 #define PHAN_INITIALIZE_FAILED 0xffff
184 #define PHAN_INITIALIZE_COMPLETE 0xff01
185
186 /* Host writes the following to notify that it has done the init-handshake */
187 #define PHAN_INITIALIZE_ACK 0xf00f
188
189 #define NUM_RCV_DESC_RINGS 3
190 #define NUM_STS_DESC_RINGS 4
191
192 #define RCV_RING_NORMAL 0
193 #define RCV_RING_JUMBO 1
194 #define RCV_RING_LRO 2
195
196 #define MIN_CMD_DESCRIPTORS 64
197 #define MIN_RCV_DESCRIPTORS 64
198 #define MIN_JUMBO_DESCRIPTORS 32
199
200 #define MAX_CMD_DESCRIPTORS 1024
201 #define MAX_RCV_DESCRIPTORS_1G 4096
202 #define MAX_RCV_DESCRIPTORS_10G 8192
203 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
204 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
205 #define MAX_LRO_RCV_DESCRIPTORS 8
206
207 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
208 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
209
210 #define NETXEN_CTX_SIGNATURE 0xdee0
211 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
212 #define NETXEN_CTX_RESET 0xbad0
213 #define NETXEN_CTX_D3_RESET 0xacc0
214 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
215
216 #define PHAN_PEG_RCV_INITIALIZED 0xff01
217 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
218
219 #define get_next_index(index, length) \
220 (((index) + 1) & ((length) - 1))
221
222 #define get_index_range(index,length,count) \
223 (((index) + (count)) & ((length) - 1))
224
225 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
226 #define MPORT_MULTI_FUNCTION_MODE 0x2222
227
228 #define NX_MAX_PCI_FUNC 8
229
230 /*
231 * NetXen host-peg signal message structure
232 *
233 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
234 * Bit 2 : priv_id => must be 1
235 * Bit 3-17 : count => for doorbell
236 * Bit 18-27 : ctx_id => Context id
237 * Bit 28-31 : opcode
238 */
239
240 typedef u32 netxen_ctx_msg;
241
242 #define netxen_set_msg_peg_id(config_word, val) \
243 ((config_word) &= ~3, (config_word) |= val & 3)
244 #define netxen_set_msg_privid(config_word) \
245 ((config_word) |= 1 << 2)
246 #define netxen_set_msg_count(config_word, val) \
247 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
248 #define netxen_set_msg_ctxid(config_word, val) \
249 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
250 #define netxen_set_msg_opcode(config_word, val) \
251 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
252
253 struct netxen_rcv_ring {
254 __le64 addr;
255 __le32 size;
256 __le32 rsrvd;
257 };
258
259 struct netxen_sts_ring {
260 __le64 addr;
261 __le32 size;
262 __le16 msi_index;
263 __le16 rsvd;
264 } ;
265
266 struct netxen_ring_ctx {
267
268 /* one command ring */
269 __le64 cmd_consumer_offset;
270 __le64 cmd_ring_addr;
271 __le32 cmd_ring_size;
272 __le32 rsrvd;
273
274 /* three receive rings */
275 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
276
277 __le64 sts_ring_addr;
278 __le32 sts_ring_size;
279
280 __le32 ctx_id;
281
282 __le64 rsrvd_2[3];
283 __le32 sts_ring_count;
284 __le32 rsrvd_3;
285 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
286
287 } __attribute__ ((aligned(64)));
288
289 /*
290 * Following data structures describe the descriptors that will be used.
291 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
292 * we are doing LSO (above the 1500 size packet) only.
293 */
294
295 /*
296 * The size of reference handle been changed to 16 bits to pass the MSS fields
297 * for the LSO packet
298 */
299
300 #define FLAGS_CHECKSUM_ENABLED 0x01
301 #define FLAGS_LSO_ENABLED 0x02
302 #define FLAGS_IPSEC_SA_ADD 0x04
303 #define FLAGS_IPSEC_SA_DELETE 0x08
304 #define FLAGS_VLAN_TAGGED 0x10
305 #define FLAGS_VLAN_OOB 0x40
306
307 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
308 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
309
310 #define netxen_set_cmd_desc_port(cmd_desc, var) \
311 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
312 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
313 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
314
315 #define netxen_set_tx_port(_desc, _port) \
316 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
317
318 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
319 (_desc)->flags_opcode = \
320 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
321
322 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
323 (_desc)->nfrags__length = \
324 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
325
326 struct cmd_desc_type0 {
327 u8 tcp_hdr_offset; /* For LSO only */
328 u8 ip_hdr_offset; /* For LSO only */
329 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
330 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
331
332 __le64 addr_buffer2;
333
334 __le16 reference_handle;
335 __le16 mss;
336 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
337 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
338 __le16 conn_id; /* IPSec offoad only */
339
340 __le64 addr_buffer3;
341 __le64 addr_buffer1;
342
343 __le16 buffer_length[4];
344
345 __le64 addr_buffer4;
346
347 __le32 reserved2;
348 __le16 reserved;
349 __le16 vlan_TCI;
350
351 } __attribute__ ((aligned(64)));
352
353 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
354 struct rcv_desc {
355 __le16 reference_handle;
356 __le16 reserved;
357 __le32 buffer_length; /* allocated buffer length (usually 2K) */
358 __le64 addr_buffer;
359 };
360
361 /* opcode field in status_desc */
362 #define NETXEN_NIC_SYN_OFFLOAD 0x03
363 #define NETXEN_NIC_RXPKT_DESC 0x04
364 #define NETXEN_OLD_RXPKT_DESC 0x3f
365 #define NETXEN_NIC_RESPONSE_DESC 0x05
366 #define NETXEN_NIC_LRO_DESC 0x12
367
368 /* for status field in status_desc */
369 #define STATUS_NEED_CKSUM (1)
370 #define STATUS_CKSUM_OK (2)
371
372 /* owner bits of status_desc */
373 #define STATUS_OWNER_HOST (0x1ULL << 56)
374 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
375
376 /* Status descriptor:
377 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
378 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
379 53-55 desc_cnt, 56-57 owner, 58-63 opcode
380 */
381 #define netxen_get_sts_port(sts_data) \
382 ((sts_data) & 0x0F)
383 #define netxen_get_sts_status(sts_data) \
384 (((sts_data) >> 4) & 0x0F)
385 #define netxen_get_sts_type(sts_data) \
386 (((sts_data) >> 8) & 0x0F)
387 #define netxen_get_sts_totallength(sts_data) \
388 (((sts_data) >> 12) & 0xFFFF)
389 #define netxen_get_sts_refhandle(sts_data) \
390 (((sts_data) >> 28) & 0xFFFF)
391 #define netxen_get_sts_prot(sts_data) \
392 (((sts_data) >> 44) & 0x0F)
393 #define netxen_get_sts_pkt_offset(sts_data) \
394 (((sts_data) >> 48) & 0x1F)
395 #define netxen_get_sts_desc_cnt(sts_data) \
396 (((sts_data) >> 53) & 0x7)
397 #define netxen_get_sts_opcode(sts_data) \
398 (((sts_data) >> 58) & 0x03F)
399
400 #define netxen_get_lro_sts_refhandle(sts_data) \
401 ((sts_data) & 0x0FFFF)
402 #define netxen_get_lro_sts_length(sts_data) \
403 (((sts_data) >> 16) & 0x0FFFF)
404 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
405 (((sts_data) >> 32) & 0x0FF)
406 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
407 (((sts_data) >> 40) & 0x0FF)
408 #define netxen_get_lro_sts_timestamp(sts_data) \
409 (((sts_data) >> 48) & 0x1)
410 #define netxen_get_lro_sts_type(sts_data) \
411 (((sts_data) >> 49) & 0x7)
412 #define netxen_get_lro_sts_push_flag(sts_data) \
413 (((sts_data) >> 52) & 0x1)
414 #define netxen_get_lro_sts_seq_number(sts_data) \
415 ((sts_data) & 0x0FFFFFFFF)
416
417
418 struct status_desc {
419 __le64 status_desc_data[2];
420 } __attribute__ ((aligned(16)));
421
422 /* UNIFIED ROMIMAGE *************************/
423 #define NX_UNI_FW_MIN_SIZE 0x3eb000
424 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
425 #define NX_UNI_DIR_SECT_BOOTLD 0x6
426 #define NX_UNI_DIR_SECT_FW 0x7
427
428 /*Offsets */
429 #define NX_UNI_CHIP_REV_OFF 10
430 #define NX_UNI_FLAGS_OFF 11
431 #define NX_UNI_BIOS_VERSION_OFF 12
432 #define NX_UNI_BOOTLD_IDX_OFF 27
433 #define NX_UNI_FIRMWARE_IDX_OFF 29
434
435 struct uni_table_desc{
436 uint32_t findex;
437 uint32_t num_entries;
438 uint32_t entry_size;
439 uint32_t reserved[5];
440 };
441
442 struct uni_data_desc{
443 uint32_t findex;
444 uint32_t size;
445 uint32_t reserved[5];
446 };
447
448 /* UNIFIED ROMIMAGE *************************/
449
450 /* The version of the main data structure */
451 #define NETXEN_BDINFO_VERSION 1
452
453 /* Magic number to let user know flash is programmed */
454 #define NETXEN_BDINFO_MAGIC 0x12345678
455
456 /* Max number of Gig ports on a Phantom board */
457 #define NETXEN_MAX_PORTS 4
458
459 #define NETXEN_BRDTYPE_P1_BD 0x0000
460 #define NETXEN_BRDTYPE_P1_SB 0x0001
461 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
462 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
463
464 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
465 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
466 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
467 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
468 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
469
470 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
471 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
472 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
473
474 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
475 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
476 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
477 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
478 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
479 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
480 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
481 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
482 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
483 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
484 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
485 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
486 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
487 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
488
489 /* Flash memory map */
490 #define NETXEN_CRBINIT_START 0 /* crbinit section */
491 #define NETXEN_BRDCFG_START 0x4000 /* board config */
492 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
493 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
494 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
495 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
496 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
497 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
498 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
499 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
500
501 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
502 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
503 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
504 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
505 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
506 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
507
508 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
509 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
510 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
511
512 #define NX_FW_MIN_SIZE (0x3fffff)
513 #define NX_P2_MN_ROMIMAGE 0
514 #define NX_P3_CT_ROMIMAGE 1
515 #define NX_P3_MN_ROMIMAGE 2
516 #define NX_UNIFIED_ROMIMAGE 3
517 #define NX_FLASH_ROMIMAGE 4
518 #define NX_UNKNOWN_ROMIMAGE 0xff
519
520 extern char netxen_nic_driver_name[];
521
522 /* Number of status descriptors to handle per interrupt */
523 #define MAX_STATUS_HANDLE (64)
524
525 /*
526 * netxen_skb_frag{} is to contain mapping info for each SG list. This
527 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
528 */
529 struct netxen_skb_frag {
530 u64 dma;
531 u64 length;
532 };
533
534 struct netxen_recv_crb {
535 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
536 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
537 u32 sw_int_mask[NUM_STS_DESC_RINGS];
538 };
539
540 /* Following defines are for the state of the buffers */
541 #define NETXEN_BUFFER_FREE 0
542 #define NETXEN_BUFFER_BUSY 1
543
544 /*
545 * There will be one netxen_buffer per skb packet. These will be
546 * used to save the dma info for pci_unmap_page()
547 */
548 struct netxen_cmd_buffer {
549 struct sk_buff *skb;
550 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
551 u32 frag_count;
552 };
553
554 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
555 struct netxen_rx_buffer {
556 struct list_head list;
557 struct sk_buff *skb;
558 u64 dma;
559 u16 ref_handle;
560 u16 state;
561 };
562
563 /* Board types */
564 #define NETXEN_NIC_GBE 0x01
565 #define NETXEN_NIC_XGBE 0x02
566
567 /*
568 * One hardware_context{} per adapter
569 * contains interrupt info as well shared hardware info.
570 */
571 struct netxen_hardware_context {
572 void __iomem *pci_base0;
573 void __iomem *pci_base1;
574 void __iomem *pci_base2;
575 void __iomem *db_base;
576 void __iomem *ocm_win_crb;
577
578 unsigned long db_len;
579 unsigned long pci_len0;
580
581 u32 ocm_win;
582 u32 crb_win;
583
584 rwlock_t crb_lock;
585 spinlock_t mem_lock;
586
587 u8 cut_through;
588 u8 revision_id;
589 u8 pci_func;
590 u8 linkup;
591 u16 port_type;
592 u16 board_type;
593 };
594
595 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
596 #define ETHERNET_FCS_SIZE 4
597
598 struct netxen_adapter_stats {
599 u64 xmitcalled;
600 u64 xmitfinished;
601 u64 rxdropped;
602 u64 txdropped;
603 u64 csummed;
604 u64 rx_pkts;
605 u64 lro_pkts;
606 u64 rxbytes;
607 u64 txbytes;
608 };
609
610 /*
611 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
612 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
613 */
614 struct nx_host_rds_ring {
615 u32 producer;
616 u32 num_desc;
617 u32 dma_size;
618 u32 skb_size;
619 u32 flags;
620 void __iomem *crb_rcv_producer;
621 struct rcv_desc *desc_head;
622 struct netxen_rx_buffer *rx_buf_arr;
623 struct list_head free_list;
624 spinlock_t lock;
625 dma_addr_t phys_addr;
626 };
627
628 struct nx_host_sds_ring {
629 u32 consumer;
630 u32 num_desc;
631 void __iomem *crb_sts_consumer;
632 void __iomem *crb_intr_mask;
633
634 struct status_desc *desc_head;
635 struct netxen_adapter *adapter;
636 struct napi_struct napi;
637 struct list_head free_list[NUM_RCV_DESC_RINGS];
638
639 int irq;
640
641 dma_addr_t phys_addr;
642 char name[IFNAMSIZ+4];
643 };
644
645 struct nx_host_tx_ring {
646 u32 producer;
647 __le32 *hw_consumer;
648 u32 sw_consumer;
649 void __iomem *crb_cmd_producer;
650 void __iomem *crb_cmd_consumer;
651 u32 num_desc;
652
653 struct netdev_queue *txq;
654
655 struct netxen_cmd_buffer *cmd_buf_arr;
656 struct cmd_desc_type0 *desc_head;
657 dma_addr_t phys_addr;
658 };
659
660 /*
661 * Receive context. There is one such structure per instance of the
662 * receive processing. Any state information that is relevant to
663 * the receive, and is must be in this structure. The global data may be
664 * present elsewhere.
665 */
666 struct netxen_recv_context {
667 u32 state;
668 u16 context_id;
669 u16 virt_port;
670
671 struct nx_host_rds_ring *rds_rings;
672 struct nx_host_sds_ring *sds_rings;
673
674 struct netxen_ring_ctx *hwctx;
675 dma_addr_t phys_addr;
676 };
677
678 /* New HW context creation */
679
680 #define NX_OS_CRB_RETRY_COUNT 4000
681 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
682 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
683
684 #define NX_CDRP_CLEAR 0x00000000
685 #define NX_CDRP_CMD_BIT 0x80000000
686
687 /*
688 * All responses must have the NX_CDRP_CMD_BIT cleared
689 * in the crb NX_CDRP_CRB_OFFSET.
690 */
691 #define NX_CDRP_FORM_RSP(rsp) (rsp)
692 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
693
694 #define NX_CDRP_RSP_OK 0x00000001
695 #define NX_CDRP_RSP_FAIL 0x00000002
696 #define NX_CDRP_RSP_TIMEOUT 0x00000003
697
698 /*
699 * All commands must have the NX_CDRP_CMD_BIT set in
700 * the crb NX_CDRP_CRB_OFFSET.
701 */
702 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
703 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
704
705 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
706 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
707 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
708 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
709 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
710 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
711 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
712 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
713 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
714 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
715 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
716 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
717 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
718 #define NX_CDRP_CMD_SET_MTU 0x00000012
719 #define NX_CDRP_CMD_READ_PHY 0x00000013
720 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
721 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
722 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
723 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
724 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
725 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
726 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
727 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
728 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
729 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
730 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
731 #define NX_CDRP_CMD_MAX 0x0000001f
732
733 #define NX_RCODE_SUCCESS 0
734 #define NX_RCODE_NO_HOST_MEM 1
735 #define NX_RCODE_NO_HOST_RESOURCE 2
736 #define NX_RCODE_NO_CARD_CRB 3
737 #define NX_RCODE_NO_CARD_MEM 4
738 #define NX_RCODE_NO_CARD_RESOURCE 5
739 #define NX_RCODE_INVALID_ARGS 6
740 #define NX_RCODE_INVALID_ACTION 7
741 #define NX_RCODE_INVALID_STATE 8
742 #define NX_RCODE_NOT_SUPPORTED 9
743 #define NX_RCODE_NOT_PERMITTED 10
744 #define NX_RCODE_NOT_READY 11
745 #define NX_RCODE_DOES_NOT_EXIST 12
746 #define NX_RCODE_ALREADY_EXISTS 13
747 #define NX_RCODE_BAD_SIGNATURE 14
748 #define NX_RCODE_CMD_NOT_IMPL 15
749 #define NX_RCODE_CMD_INVALID 16
750 #define NX_RCODE_TIMEOUT 17
751 #define NX_RCODE_CMD_FAILED 18
752 #define NX_RCODE_MAX_EXCEEDED 19
753 #define NX_RCODE_MAX 20
754
755 #define NX_DESTROY_CTX_RESET 0
756 #define NX_DESTROY_CTX_D3_RESET 1
757 #define NX_DESTROY_CTX_MAX 2
758
759 /*
760 * Capabilities
761 */
762 #define NX_CAP_BIT(class, bit) (1 << bit)
763 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
764 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
765 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
766 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
767 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
768 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
769 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
770 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
771 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
772 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
773
774 /*
775 * Context state
776 */
777 #define NX_HOST_CTX_STATE_FREED 0
778 #define NX_HOST_CTX_STATE_ALLOCATED 1
779 #define NX_HOST_CTX_STATE_ACTIVE 2
780 #define NX_HOST_CTX_STATE_DISABLED 3
781 #define NX_HOST_CTX_STATE_QUIESCED 4
782 #define NX_HOST_CTX_STATE_MAX 5
783
784 /*
785 * Rx context
786 */
787
788 typedef struct {
789 __le64 host_phys_addr; /* Ring base addr */
790 __le32 ring_size; /* Ring entries */
791 __le16 msi_index;
792 __le16 rsvd; /* Padding */
793 } nx_hostrq_sds_ring_t;
794
795 typedef struct {
796 __le64 host_phys_addr; /* Ring base addr */
797 __le64 buff_size; /* Packet buffer size */
798 __le32 ring_size; /* Ring entries */
799 __le32 ring_kind; /* Class of ring */
800 } nx_hostrq_rds_ring_t;
801
802 typedef struct {
803 __le64 host_rsp_dma_addr; /* Response dma'd here */
804 __le32 capabilities[4]; /* Flag bit vector */
805 __le32 host_int_crb_mode; /* Interrupt crb usage */
806 __le32 host_rds_crb_mode; /* RDS crb usage */
807 /* These ring offsets are relative to data[0] below */
808 __le32 rds_ring_offset; /* Offset to RDS config */
809 __le32 sds_ring_offset; /* Offset to SDS config */
810 __le16 num_rds_rings; /* Count of RDS rings */
811 __le16 num_sds_rings; /* Count of SDS rings */
812 __le16 rsvd1; /* Padding */
813 __le16 rsvd2; /* Padding */
814 u8 reserved[128]; /* reserve space for future expansion*/
815 /* MUST BE 64-bit aligned.
816 The following is packed:
817 - N hostrq_rds_rings
818 - N hostrq_sds_rings */
819 char data[0];
820 } nx_hostrq_rx_ctx_t;
821
822 typedef struct {
823 __le32 host_producer_crb; /* Crb to use */
824 __le32 rsvd1; /* Padding */
825 } nx_cardrsp_rds_ring_t;
826
827 typedef struct {
828 __le32 host_consumer_crb; /* Crb to use */
829 __le32 interrupt_crb; /* Crb to use */
830 } nx_cardrsp_sds_ring_t;
831
832 typedef struct {
833 /* These ring offsets are relative to data[0] below */
834 __le32 rds_ring_offset; /* Offset to RDS config */
835 __le32 sds_ring_offset; /* Offset to SDS config */
836 __le32 host_ctx_state; /* Starting State */
837 __le32 num_fn_per_port; /* How many PCI fn share the port */
838 __le16 num_rds_rings; /* Count of RDS rings */
839 __le16 num_sds_rings; /* Count of SDS rings */
840 __le16 context_id; /* Handle for context */
841 u8 phys_port; /* Physical id of port */
842 u8 virt_port; /* Virtual/Logical id of port */
843 u8 reserved[128]; /* save space for future expansion */
844 /* MUST BE 64-bit aligned.
845 The following is packed:
846 - N cardrsp_rds_rings
847 - N cardrs_sds_rings */
848 char data[0];
849 } nx_cardrsp_rx_ctx_t;
850
851 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
852 (sizeof(HOSTRQ_RX) + \
853 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
854 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
855
856 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
857 (sizeof(CARDRSP_RX) + \
858 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
859 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
860
861 /*
862 * Tx context
863 */
864
865 typedef struct {
866 __le64 host_phys_addr; /* Ring base addr */
867 __le32 ring_size; /* Ring entries */
868 __le32 rsvd; /* Padding */
869 } nx_hostrq_cds_ring_t;
870
871 typedef struct {
872 __le64 host_rsp_dma_addr; /* Response dma'd here */
873 __le64 cmd_cons_dma_addr; /* */
874 __le64 dummy_dma_addr; /* */
875 __le32 capabilities[4]; /* Flag bit vector */
876 __le32 host_int_crb_mode; /* Interrupt crb usage */
877 __le32 rsvd1; /* Padding */
878 __le16 rsvd2; /* Padding */
879 __le16 interrupt_ctl;
880 __le16 msi_index;
881 __le16 rsvd3; /* Padding */
882 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
883 u8 reserved[128]; /* future expansion */
884 } nx_hostrq_tx_ctx_t;
885
886 typedef struct {
887 __le32 host_producer_crb; /* Crb to use */
888 __le32 interrupt_crb; /* Crb to use */
889 } nx_cardrsp_cds_ring_t;
890
891 typedef struct {
892 __le32 host_ctx_state; /* Starting state */
893 __le16 context_id; /* Handle for context */
894 u8 phys_port; /* Physical id of port */
895 u8 virt_port; /* Virtual/Logical id of port */
896 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
897 u8 reserved[128]; /* future expansion */
898 } nx_cardrsp_tx_ctx_t;
899
900 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
901 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
902
903 /* CRB */
904
905 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
906 #define NX_HOST_RDS_CRB_MODE_SHARED 1
907 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
908 #define NX_HOST_RDS_CRB_MODE_MAX 3
909
910 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
911 #define NX_HOST_INT_CRB_MODE_SHARED 1
912 #define NX_HOST_INT_CRB_MODE_NORX 2
913 #define NX_HOST_INT_CRB_MODE_NOTX 3
914 #define NX_HOST_INT_CRB_MODE_NORXTX 4
915
916
917 /* MAC */
918
919 #define MC_COUNT_P2 16
920 #define MC_COUNT_P3 38
921
922 #define NETXEN_MAC_NOOP 0
923 #define NETXEN_MAC_ADD 1
924 #define NETXEN_MAC_DEL 2
925
926 typedef struct nx_mac_list_s {
927 struct list_head list;
928 uint8_t mac_addr[ETH_ALEN+2];
929 } nx_mac_list_t;
930
931 /*
932 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
933 * adjusted based on configured MTU.
934 */
935 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
936 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
937 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
938 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
939
940 #define NETXEN_NIC_INTR_DEFAULT 0x04
941
942 typedef union {
943 struct {
944 uint16_t rx_packets;
945 uint16_t rx_time_us;
946 uint16_t tx_packets;
947 uint16_t tx_time_us;
948 } data;
949 uint64_t word;
950 } nx_nic_intr_coalesce_data_t;
951
952 typedef struct {
953 uint16_t stats_time_us;
954 uint16_t rate_sample_time;
955 uint16_t flags;
956 uint16_t rsvd_1;
957 uint32_t low_threshold;
958 uint32_t high_threshold;
959 nx_nic_intr_coalesce_data_t normal;
960 nx_nic_intr_coalesce_data_t low;
961 nx_nic_intr_coalesce_data_t high;
962 nx_nic_intr_coalesce_data_t irq;
963 } nx_nic_intr_coalesce_t;
964
965 #define NX_HOST_REQUEST 0x13
966 #define NX_NIC_REQUEST 0x14
967
968 #define NX_MAC_EVENT 0x1
969
970 #define NX_IP_UP 2
971 #define NX_IP_DOWN 3
972
973 /*
974 * Driver --> Firmware
975 */
976 #define NX_NIC_H2C_OPCODE_START 0
977 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
978 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
979 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
980 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
981 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
982 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
983 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
984 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
985 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
986 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
987 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
988 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
989 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
990 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
991 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
992 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
993 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
994 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
995 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
996 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
997 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
998 #define NX_NIC_C2C_OPCODE 22
999 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1000 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1001 #define NX_NIC_H2C_OPCODE_LAST 25
1002
1003 /*
1004 * Firmware --> Driver
1005 */
1006
1007 #define NX_NIC_C2H_OPCODE_START 128
1008 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1009 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1010 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1011 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1012 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1013 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1014 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1015 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1016 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1017 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1018 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1019 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1020 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1021 #define NX_NIC_C2H_OPCODE_LAST 142
1022
1023 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1024 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1025 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1026
1027 #define NX_NIC_LRO_REQUEST_FIRST 0
1028 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1029 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1030 #define NX_NIC_LRO_REQUEST_TIMER 3
1031 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1032 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1033 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1034 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1035 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1036 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1037 #define NX_TOE_LRO_REQUEST_TIMER 10
1038 #define NX_NIC_LRO_REQUEST_LAST 11
1039
1040 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1041 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1042 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1043 #define NX_FW_CAPABILITY_BDG (1 << 8)
1044 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1045 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1046
1047 /* module types */
1048 #define LINKEVENT_MODULE_NOT_PRESENT 1
1049 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1050 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1051 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1052 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1053 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1054 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1055 #define LINKEVENT_MODULE_TWINAX 8
1056
1057 #define LINKSPEED_10GBPS 10000
1058 #define LINKSPEED_1GBPS 1000
1059 #define LINKSPEED_100MBPS 100
1060 #define LINKSPEED_10MBPS 10
1061
1062 #define LINKSPEED_ENCODED_10MBPS 0
1063 #define LINKSPEED_ENCODED_100MBPS 1
1064 #define LINKSPEED_ENCODED_1GBPS 2
1065
1066 #define LINKEVENT_AUTONEG_DISABLED 0
1067 #define LINKEVENT_AUTONEG_ENABLED 1
1068
1069 #define LINKEVENT_HALF_DUPLEX 0
1070 #define LINKEVENT_FULL_DUPLEX 1
1071
1072 #define LINKEVENT_LINKSPEED_MBPS 0
1073 #define LINKEVENT_LINKSPEED_ENCODED 1
1074
1075 #define AUTO_FW_RESET_ENABLED 0xEF10AF12
1076 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1077
1078 /* firmware response header:
1079 * 63:58 - message type
1080 * 57:56 - owner
1081 * 55:53 - desc count
1082 * 52:48 - reserved
1083 * 47:40 - completion id
1084 * 39:32 - opcode
1085 * 31:16 - error code
1086 * 15:00 - reserved
1087 */
1088 #define netxen_get_nic_msgtype(msg_hdr) \
1089 ((msg_hdr >> 58) & 0x3F)
1090 #define netxen_get_nic_msg_compid(msg_hdr) \
1091 ((msg_hdr >> 40) & 0xFF)
1092 #define netxen_get_nic_msg_opcode(msg_hdr) \
1093 ((msg_hdr >> 32) & 0xFF)
1094 #define netxen_get_nic_msg_errcode(msg_hdr) \
1095 ((msg_hdr >> 16) & 0xFFFF)
1096
1097 typedef struct {
1098 union {
1099 struct {
1100 u64 hdr;
1101 u64 body[7];
1102 };
1103 u64 words[8];
1104 };
1105 } nx_fw_msg_t;
1106
1107 typedef struct {
1108 __le64 qhdr;
1109 __le64 req_hdr;
1110 __le64 words[6];
1111 } nx_nic_req_t;
1112
1113 typedef struct {
1114 u8 op;
1115 u8 tag;
1116 u8 mac_addr[6];
1117 } nx_mac_req_t;
1118
1119 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1120
1121 #define NETXEN_NIC_MSI_ENABLED 0x02
1122 #define NETXEN_NIC_MSIX_ENABLED 0x04
1123 #define NETXEN_NIC_LRO_ENABLED 0x08
1124 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1125 #define NETXEN_NIC_DIAG_ENABLED 0x20
1126 #define NETXEN_IS_MSI_FAMILY(adapter) \
1127 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1128
1129 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1130 #define NETXEN_MSIX_TBL_SPACE 8192
1131 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1132
1133 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1134
1135 #define NETXEN_NETDEV_WEIGHT 128
1136 #define NETXEN_ADAPTER_UP_MAGIC 777
1137 #define NETXEN_NIC_PEG_TUNE 0
1138
1139 #define __NX_FW_ATTACHED 0
1140 #define __NX_DEV_UP 1
1141 #define __NX_RESETTING 2
1142
1143 struct netxen_dummy_dma {
1144 void *addr;
1145 dma_addr_t phys_addr;
1146 };
1147
1148 struct netxen_adapter {
1149 struct netxen_hardware_context ahw;
1150
1151 struct net_device *netdev;
1152 struct pci_dev *pdev;
1153 struct list_head mac_list;
1154
1155 spinlock_t tx_clean_lock;
1156
1157 u16 num_txd;
1158 u16 num_rxd;
1159 u16 num_jumbo_rxd;
1160 u16 num_lro_rxd;
1161
1162 u8 max_rds_rings;
1163 u8 max_sds_rings;
1164 u8 driver_mismatch;
1165 u8 msix_supported;
1166 u8 rx_csum;
1167 u8 pci_using_dac;
1168 u8 portnum;
1169 u8 physical_port;
1170
1171 u8 mc_enabled;
1172 u8 max_mc_count;
1173 u8 rss_supported;
1174 u8 link_changed;
1175 u8 fw_wait_cnt;
1176 u8 fw_fail_cnt;
1177 u8 tx_timeo_cnt;
1178 u8 need_fw_reset;
1179
1180 u8 has_link_events;
1181 u8 fw_type;
1182 u16 tx_context_id;
1183 u16 mtu;
1184 u16 is_up;
1185
1186 u16 link_speed;
1187 u16 link_duplex;
1188 u16 link_autoneg;
1189 u16 module_type;
1190
1191 u32 capabilities;
1192 u32 flags;
1193 u32 irq;
1194 u32 temp;
1195
1196 u32 int_vec_bit;
1197 u32 heartbit;
1198
1199 struct netxen_adapter_stats stats;
1200
1201 struct netxen_recv_context recv_ctx;
1202 struct nx_host_tx_ring *tx_ring;
1203
1204 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1205 int (*set_mtu) (struct netxen_adapter *, int);
1206 int (*set_promisc) (struct netxen_adapter *, u32);
1207 void (*set_multi) (struct net_device *);
1208 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1209 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1210 int (*init_port) (struct netxen_adapter *, int);
1211 int (*stop_port) (struct netxen_adapter *);
1212
1213 u32 (*crb_read)(struct netxen_adapter *, ulong);
1214 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1215
1216 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1217 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1218
1219 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1220
1221 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1222 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1223
1224 void __iomem *tgt_mask_reg;
1225 void __iomem *pci_int_reg;
1226 void __iomem *tgt_status_reg;
1227 void __iomem *crb_int_state_reg;
1228 void __iomem *isr_int_vec;
1229
1230 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1231
1232 struct netxen_dummy_dma dummy_dma;
1233
1234 struct delayed_work fw_work;
1235
1236 struct work_struct tx_timeout_task;
1237
1238 nx_nic_intr_coalesce_t coal;
1239
1240 unsigned long state;
1241 __le32 file_prd_off; /*File fw product offset*/
1242 u32 fw_version;
1243 const struct firmware *fw;
1244 };
1245
1246 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
1247 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
1248
1249 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1250 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1251
1252 /* Functions available from netxen_nic_hw.c */
1253 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1254 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1255
1256 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1257 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1258
1259 #define NXRD32(adapter, off) \
1260 (adapter->crb_read(adapter, off))
1261 #define NXWR32(adapter, off, val) \
1262 (adapter->crb_write(adapter, off, val))
1263 #define NXRDIO(adapter, addr) \
1264 (adapter->io_read(adapter, addr))
1265 #define NXWRIO(adapter, addr, val) \
1266 (adapter->io_write(adapter, addr, val))
1267
1268 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1269 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1270
1271 #define netxen_rom_lock(a) \
1272 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1273 #define netxen_rom_unlock(a) \
1274 netxen_pcie_sem_unlock((a), 2)
1275 #define netxen_phy_lock(a) \
1276 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1277 #define netxen_phy_unlock(a) \
1278 netxen_pcie_sem_unlock((a), 3)
1279 #define netxen_api_lock(a) \
1280 netxen_pcie_sem_lock((a), 5, 0)
1281 #define netxen_api_unlock(a) \
1282 netxen_pcie_sem_unlock((a), 5)
1283 #define netxen_sw_lock(a) \
1284 netxen_pcie_sem_lock((a), 6, 0)
1285 #define netxen_sw_unlock(a) \
1286 netxen_pcie_sem_unlock((a), 6)
1287 #define crb_win_lock(a) \
1288 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1289 #define crb_win_unlock(a) \
1290 netxen_pcie_sem_unlock((a), 7)
1291
1292 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1293 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1294
1295 /* Functions from netxen_nic_init.c */
1296 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1297 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1298
1299 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1300 int netxen_load_firmware(struct netxen_adapter *adapter);
1301 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1302 void netxen_request_firmware(struct netxen_adapter *adapter);
1303 void netxen_release_firmware(struct netxen_adapter *adapter);
1304 int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1305
1306 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1307 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1308 u8 *bytes, size_t size);
1309 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1310 u8 *bytes, size_t size);
1311 int netxen_flash_unlock(struct netxen_adapter *adapter);
1312 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1313 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1314 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1315 void netxen_halt_pegs(struct netxen_adapter *adapter);
1316
1317 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1318
1319 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1320 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1321
1322 void netxen_setup_hwops(struct netxen_adapter *adapter);
1323 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1324
1325 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1326 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1327
1328 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1329 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1330
1331 int netxen_init_firmware(struct netxen_adapter *adapter);
1332 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1333 void netxen_watchdog_task(struct work_struct *work);
1334 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1335 struct nx_host_rds_ring *rds_ring);
1336 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1337 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1338 void netxen_p2_nic_set_multi(struct net_device *netdev);
1339 void netxen_p3_nic_set_multi(struct net_device *netdev);
1340 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1341 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode);
1342 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1343 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1344 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1345 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1346 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1347 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1348
1349 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1350 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1351 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1352 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1353 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1354
1355 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1356 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1357
1358 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1359 struct nx_host_tx_ring *tx_ring);
1360
1361 /* Functions from netxen_nic_main.c */
1362 int netxen_nic_reset_context(struct netxen_adapter *);
1363
1364 /*
1365 * NetXen Board information
1366 */
1367
1368 #define NETXEN_MAX_SHORT_NAME 32
1369 struct netxen_brdinfo {
1370 int brdtype; /* type of board */
1371 long ports; /* max no of physical ports */
1372 char short_name[NETXEN_MAX_SHORT_NAME];
1373 };
1374
1375 static const struct netxen_brdinfo netxen_boards[] = {
1376 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1377 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1378 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1379 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1380 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1381 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1382 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1383 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1384 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1385 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1386 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1387 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1388 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1389 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1390 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1391 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1392 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1393 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1394 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1395 };
1396
1397 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1398
1399 static inline void get_brd_name_by_type(u32 type, char *name)
1400 {
1401 int i, found = 0;
1402 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1403 if (netxen_boards[i].brdtype == type) {
1404 strcpy(name, netxen_boards[i].short_name);
1405 found = 1;
1406 break;
1407 }
1408
1409 }
1410 if (!found)
1411 name = "Unknown";
1412 }
1413
1414 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1415 {
1416 smp_mb();
1417 return find_diff_among(tx_ring->producer,
1418 tx_ring->sw_consumer, tx_ring->num_desc);
1419
1420 }
1421
1422 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1423 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1424 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1425 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1426 int *valp);
1427
1428 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1429
1430 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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