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netxen: update version 4.0.74
[deliverable/linux.git] / drivers / net / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26 #ifndef _NETXEN_NIC_H_
27 #define _NETXEN_NIC_H_
28
29 #include <linux/module.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/ioport.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/ip.h>
37 #include <linux/in.h>
38 #include <linux/tcp.h>
39 #include <linux/skbuff.h>
40 #include <linux/firmware.h>
41
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/timer.h>
45
46 #include <linux/vmalloc.h>
47
48 #include <asm/io.h>
49 #include <asm/byteorder.h>
50
51 #include "netxen_nic_hdr.h"
52 #include "netxen_nic_hw.h"
53
54 #define _NETXEN_NIC_LINUX_MAJOR 4
55 #define _NETXEN_NIC_LINUX_MINOR 0
56 #define _NETXEN_NIC_LINUX_SUBVERSION 74
57 #define NETXEN_NIC_LINUX_VERSIONID "4.0.74"
58
59 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
60 #define _major(v) (((v) >> 24) & 0xff)
61 #define _minor(v) (((v) >> 16) & 0xff)
62 #define _build(v) ((v) & 0xffff)
63
64 /* version in image has weird encoding:
65 * 7:0 - major
66 * 15:8 - minor
67 * 31:16 - build (little endian)
68 */
69 #define NETXEN_DECODE_VERSION(v) \
70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
71
72 #define NETXEN_NUM_FLASH_SECTORS (64)
73 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
74 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
75 * NETXEN_FLASH_SECTOR_SIZE)
76
77 #define RCV_DESC_RINGSIZE(rds_ring) \
78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
79 #define RCV_BUFF_RINGSIZE(rds_ring) \
80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
81 #define STATUS_DESC_RINGSIZE(sds_ring) \
82 (sizeof(struct status_desc) * (sds_ring)->num_desc)
83 #define TX_BUFF_RINGSIZE(tx_ring) \
84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
85 #define TX_DESC_RINGSIZE(tx_ring) \
86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
87
88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
89
90 #define NETXEN_RCV_PRODUCER_OFFSET 0
91 #define NETXEN_RCV_PEG_DB_ID 2
92 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
93 #define FLASH_SUCCESS 0
94
95 #define ADDR_IN_WINDOW1(off) \
96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
97
98 #define ADDR_IN_RANGE(addr, low, high) \
99 (((addr) < (high)) && ((addr) >= (low)))
100
101 /*
102 * normalize a 64MB crb address to 32MB PCI window
103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
104 */
105 #define NETXEN_CRB_NORMAL(reg) \
106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
107
108 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
110
111 #define DB_NORMALIZE(adapter, off) \
112 (adapter->ahw.db_base + (off))
113
114 #define NX_P2_C0 0x24
115 #define NX_P2_C1 0x25
116 #define NX_P3_A0 0x30
117 #define NX_P3_A2 0x30
118 #define NX_P3_B0 0x40
119 #define NX_P3_B1 0x41
120 #define NX_P3_B2 0x42
121 #define NX_P3P_A0 0x50
122
123 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
124 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
125 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0)
126
127 #define FIRST_PAGE_GROUP_START 0
128 #define FIRST_PAGE_GROUP_END 0x100000
129
130 #define SECOND_PAGE_GROUP_START 0x6000000
131 #define SECOND_PAGE_GROUP_END 0x68BC000
132
133 #define THIRD_PAGE_GROUP_START 0x70E4000
134 #define THIRD_PAGE_GROUP_END 0x8000000
135
136 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
137 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
138 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
139
140 #define P2_MAX_MTU (8000)
141 #define P3_MAX_MTU (9600)
142 #define NX_ETHERMTU 1500
143 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
144
145 #define NX_P2_RX_BUF_MAX_LEN 1760
146 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
149 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
150 #define NX_LRO_BUFFER_EXTRA 2048
151
152 #define NX_RX_LRO_BUFFER_LENGTH (8060)
153
154 /*
155 * Maximum number of ring contexts
156 */
157 #define MAX_RING_CTX 1
158
159 /* Opcodes to be used with the commands */
160 #define TX_ETHER_PKT 0x01
161 #define TX_TCP_PKT 0x02
162 #define TX_UDP_PKT 0x03
163 #define TX_IP_PKT 0x04
164 #define TX_TCP_LSO 0x05
165 #define TX_TCP_LSO6 0x06
166 #define TX_IPSEC 0x07
167 #define TX_IPSEC_CMD 0x0a
168 #define TX_TCPV6_PKT 0x0b
169 #define TX_UDPV6_PKT 0x0c
170
171 /* The following opcodes are for internal consumption. */
172 #define NETXEN_CONTROL_OP 0x10
173 #define PEGNET_REQUEST 0x11
174
175 #define MAX_NUM_CARDS 4
176
177 #define MAX_BUFFERS_PER_CMD 32
178 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4)
179 #define NX_MAX_TX_TIMEOUTS 2
180
181 /*
182 * Following are the states of the Phantom. Phantom will set them and
183 * Host will read to check if the fields are correct.
184 */
185 #define PHAN_INITIALIZE_START 0xff00
186 #define PHAN_INITIALIZE_FAILED 0xffff
187 #define PHAN_INITIALIZE_COMPLETE 0xff01
188
189 /* Host writes the following to notify that it has done the init-handshake */
190 #define PHAN_INITIALIZE_ACK 0xf00f
191
192 #define NUM_RCV_DESC_RINGS 3
193 #define NUM_STS_DESC_RINGS 4
194
195 #define RCV_RING_NORMAL 0
196 #define RCV_RING_JUMBO 1
197 #define RCV_RING_LRO 2
198
199 #define MIN_CMD_DESCRIPTORS 64
200 #define MIN_RCV_DESCRIPTORS 64
201 #define MIN_JUMBO_DESCRIPTORS 32
202
203 #define MAX_CMD_DESCRIPTORS 1024
204 #define MAX_RCV_DESCRIPTORS_1G 4096
205 #define MAX_RCV_DESCRIPTORS_10G 8192
206 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
207 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
208 #define MAX_LRO_RCV_DESCRIPTORS 8
209
210 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
211 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
212
213 #define NETXEN_CTX_SIGNATURE 0xdee0
214 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
215 #define NETXEN_CTX_RESET 0xbad0
216 #define NETXEN_CTX_D3_RESET 0xacc0
217 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
218
219 #define PHAN_PEG_RCV_INITIALIZED 0xff01
220 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
221
222 #define get_next_index(index, length) \
223 (((index) + 1) & ((length) - 1))
224
225 #define get_index_range(index,length,count) \
226 (((index) + (count)) & ((length) - 1))
227
228 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
229 #define MPORT_MULTI_FUNCTION_MODE 0x2222
230
231 #define NX_MAX_PCI_FUNC 8
232
233 /*
234 * NetXen host-peg signal message structure
235 *
236 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
237 * Bit 2 : priv_id => must be 1
238 * Bit 3-17 : count => for doorbell
239 * Bit 18-27 : ctx_id => Context id
240 * Bit 28-31 : opcode
241 */
242
243 typedef u32 netxen_ctx_msg;
244
245 #define netxen_set_msg_peg_id(config_word, val) \
246 ((config_word) &= ~3, (config_word) |= val & 3)
247 #define netxen_set_msg_privid(config_word) \
248 ((config_word) |= 1 << 2)
249 #define netxen_set_msg_count(config_word, val) \
250 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
251 #define netxen_set_msg_ctxid(config_word, val) \
252 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
253 #define netxen_set_msg_opcode(config_word, val) \
254 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
255
256 struct netxen_rcv_ring {
257 __le64 addr;
258 __le32 size;
259 __le32 rsrvd;
260 };
261
262 struct netxen_sts_ring {
263 __le64 addr;
264 __le32 size;
265 __le16 msi_index;
266 __le16 rsvd;
267 } ;
268
269 struct netxen_ring_ctx {
270
271 /* one command ring */
272 __le64 cmd_consumer_offset;
273 __le64 cmd_ring_addr;
274 __le32 cmd_ring_size;
275 __le32 rsrvd;
276
277 /* three receive rings */
278 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
279
280 __le64 sts_ring_addr;
281 __le32 sts_ring_size;
282
283 __le32 ctx_id;
284
285 __le64 rsrvd_2[3];
286 __le32 sts_ring_count;
287 __le32 rsrvd_3;
288 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
289
290 } __attribute__ ((aligned(64)));
291
292 /*
293 * Following data structures describe the descriptors that will be used.
294 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
295 * we are doing LSO (above the 1500 size packet) only.
296 */
297
298 /*
299 * The size of reference handle been changed to 16 bits to pass the MSS fields
300 * for the LSO packet
301 */
302
303 #define FLAGS_CHECKSUM_ENABLED 0x01
304 #define FLAGS_LSO_ENABLED 0x02
305 #define FLAGS_IPSEC_SA_ADD 0x04
306 #define FLAGS_IPSEC_SA_DELETE 0x08
307 #define FLAGS_VLAN_TAGGED 0x10
308 #define FLAGS_VLAN_OOB 0x40
309
310 #define netxen_set_tx_vlan_tci(cmd_desc, v) \
311 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
312
313 #define netxen_set_cmd_desc_port(cmd_desc, var) \
314 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
315 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
316 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
317
318 #define netxen_set_tx_port(_desc, _port) \
319 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
320
321 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
322 (_desc)->flags_opcode = \
323 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
324
325 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
326 (_desc)->nfrags__length = \
327 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
328
329 struct cmd_desc_type0 {
330 u8 tcp_hdr_offset; /* For LSO only */
331 u8 ip_hdr_offset; /* For LSO only */
332 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
333 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
334
335 __le64 addr_buffer2;
336
337 __le16 reference_handle;
338 __le16 mss;
339 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
340 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
341 __le16 conn_id; /* IPSec offoad only */
342
343 __le64 addr_buffer3;
344 __le64 addr_buffer1;
345
346 __le16 buffer_length[4];
347
348 __le64 addr_buffer4;
349
350 __le32 reserved2;
351 __le16 reserved;
352 __le16 vlan_TCI;
353
354 } __attribute__ ((aligned(64)));
355
356 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
357 struct rcv_desc {
358 __le16 reference_handle;
359 __le16 reserved;
360 __le32 buffer_length; /* allocated buffer length (usually 2K) */
361 __le64 addr_buffer;
362 };
363
364 /* opcode field in status_desc */
365 #define NETXEN_NIC_SYN_OFFLOAD 0x03
366 #define NETXEN_NIC_RXPKT_DESC 0x04
367 #define NETXEN_OLD_RXPKT_DESC 0x3f
368 #define NETXEN_NIC_RESPONSE_DESC 0x05
369 #define NETXEN_NIC_LRO_DESC 0x12
370
371 /* for status field in status_desc */
372 #define STATUS_NEED_CKSUM (1)
373 #define STATUS_CKSUM_OK (2)
374
375 /* owner bits of status_desc */
376 #define STATUS_OWNER_HOST (0x1ULL << 56)
377 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
378
379 /* Status descriptor:
380 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
381 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
382 53-55 desc_cnt, 56-57 owner, 58-63 opcode
383 */
384 #define netxen_get_sts_port(sts_data) \
385 ((sts_data) & 0x0F)
386 #define netxen_get_sts_status(sts_data) \
387 (((sts_data) >> 4) & 0x0F)
388 #define netxen_get_sts_type(sts_data) \
389 (((sts_data) >> 8) & 0x0F)
390 #define netxen_get_sts_totallength(sts_data) \
391 (((sts_data) >> 12) & 0xFFFF)
392 #define netxen_get_sts_refhandle(sts_data) \
393 (((sts_data) >> 28) & 0xFFFF)
394 #define netxen_get_sts_prot(sts_data) \
395 (((sts_data) >> 44) & 0x0F)
396 #define netxen_get_sts_pkt_offset(sts_data) \
397 (((sts_data) >> 48) & 0x1F)
398 #define netxen_get_sts_desc_cnt(sts_data) \
399 (((sts_data) >> 53) & 0x7)
400 #define netxen_get_sts_opcode(sts_data) \
401 (((sts_data) >> 58) & 0x03F)
402
403 #define netxen_get_lro_sts_refhandle(sts_data) \
404 ((sts_data) & 0x0FFFF)
405 #define netxen_get_lro_sts_length(sts_data) \
406 (((sts_data) >> 16) & 0x0FFFF)
407 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \
408 (((sts_data) >> 32) & 0x0FF)
409 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \
410 (((sts_data) >> 40) & 0x0FF)
411 #define netxen_get_lro_sts_timestamp(sts_data) \
412 (((sts_data) >> 48) & 0x1)
413 #define netxen_get_lro_sts_type(sts_data) \
414 (((sts_data) >> 49) & 0x7)
415 #define netxen_get_lro_sts_push_flag(sts_data) \
416 (((sts_data) >> 52) & 0x1)
417 #define netxen_get_lro_sts_seq_number(sts_data) \
418 ((sts_data) & 0x0FFFFFFFF)
419
420
421 struct status_desc {
422 __le64 status_desc_data[2];
423 } __attribute__ ((aligned(16)));
424
425 /* UNIFIED ROMIMAGE *************************/
426 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0
427 #define NX_UNI_DIR_SECT_BOOTLD 0x6
428 #define NX_UNI_DIR_SECT_FW 0x7
429
430 /*Offsets */
431 #define NX_UNI_CHIP_REV_OFF 10
432 #define NX_UNI_FLAGS_OFF 11
433 #define NX_UNI_BIOS_VERSION_OFF 12
434 #define NX_UNI_BOOTLD_IDX_OFF 27
435 #define NX_UNI_FIRMWARE_IDX_OFF 29
436
437 struct uni_table_desc{
438 uint32_t findex;
439 uint32_t num_entries;
440 uint32_t entry_size;
441 uint32_t reserved[5];
442 };
443
444 struct uni_data_desc{
445 uint32_t findex;
446 uint32_t size;
447 uint32_t reserved[5];
448 };
449
450 /* UNIFIED ROMIMAGE *************************/
451
452 /* The version of the main data structure */
453 #define NETXEN_BDINFO_VERSION 1
454
455 /* Magic number to let user know flash is programmed */
456 #define NETXEN_BDINFO_MAGIC 0x12345678
457
458 /* Max number of Gig ports on a Phantom board */
459 #define NETXEN_MAX_PORTS 4
460
461 #define NETXEN_BRDTYPE_P1_BD 0x0000
462 #define NETXEN_BRDTYPE_P1_SB 0x0001
463 #define NETXEN_BRDTYPE_P1_SMAX 0x0002
464 #define NETXEN_BRDTYPE_P1_SOCK 0x0003
465
466 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008
467 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009
468 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a
469 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b
470 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c
471
472 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d
473 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e
474 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f
475
476 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021
477 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022
478 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023
479 #define NETXEN_BRDTYPE_P3_4_GB 0x0024
480 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025
481 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026
482 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027
483 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028
484 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029
485 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a
486 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b
487 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031
488 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032
489 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080
490
491 /* Flash memory map */
492 #define NETXEN_CRBINIT_START 0 /* crbinit section */
493 #define NETXEN_BRDCFG_START 0x4000 /* board config */
494 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */
495 #define NETXEN_BOOTLD_START 0x10000 /* bootld */
496 #define NETXEN_IMAGE_START 0x43000 /* compressed image */
497 #define NETXEN_SECONDARY_START 0x200000 /* backup images */
498 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */
499 #define NETXEN_USER_START 0x3E8000 /* Firmare info */
500 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */
501 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */
502
503 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START)
504 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
505 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
506 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418)
507 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c)
508 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
509
510 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START)
511 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8)
512 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
513
514 #define NX_FW_MIN_SIZE (0x3fffff)
515 #define NX_P2_MN_ROMIMAGE 0
516 #define NX_P3_CT_ROMIMAGE 1
517 #define NX_P3_MN_ROMIMAGE 2
518 #define NX_UNIFIED_ROMIMAGE 3
519 #define NX_FLASH_ROMIMAGE 4
520 #define NX_UNKNOWN_ROMIMAGE 0xff
521
522 #define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin"
523 #define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin"
524 #define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin"
525 #define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
526 #define NX_FLASH_ROMIMAGE_NAME "flash"
527
528 extern char netxen_nic_driver_name[];
529
530 /* Number of status descriptors to handle per interrupt */
531 #define MAX_STATUS_HANDLE (64)
532
533 /*
534 * netxen_skb_frag{} is to contain mapping info for each SG list. This
535 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
536 */
537 struct netxen_skb_frag {
538 u64 dma;
539 u64 length;
540 };
541
542 struct netxen_recv_crb {
543 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS];
544 u32 crb_sts_consumer[NUM_STS_DESC_RINGS];
545 u32 sw_int_mask[NUM_STS_DESC_RINGS];
546 };
547
548 /* Following defines are for the state of the buffers */
549 #define NETXEN_BUFFER_FREE 0
550 #define NETXEN_BUFFER_BUSY 1
551
552 /*
553 * There will be one netxen_buffer per skb packet. These will be
554 * used to save the dma info for pci_unmap_page()
555 */
556 struct netxen_cmd_buffer {
557 struct sk_buff *skb;
558 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
559 u32 frag_count;
560 };
561
562 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
563 struct netxen_rx_buffer {
564 struct list_head list;
565 struct sk_buff *skb;
566 u64 dma;
567 u16 ref_handle;
568 u16 state;
569 };
570
571 /* Board types */
572 #define NETXEN_NIC_GBE 0x01
573 #define NETXEN_NIC_XGBE 0x02
574
575 /*
576 * One hardware_context{} per adapter
577 * contains interrupt info as well shared hardware info.
578 */
579 struct netxen_hardware_context {
580 void __iomem *pci_base0;
581 void __iomem *pci_base1;
582 void __iomem *pci_base2;
583 void __iomem *db_base;
584 void __iomem *ocm_win_crb;
585
586 unsigned long db_len;
587 unsigned long pci_len0;
588
589 u32 ocm_win;
590 u32 crb_win;
591
592 rwlock_t crb_lock;
593 spinlock_t mem_lock;
594
595 u8 cut_through;
596 u8 revision_id;
597 u8 pci_func;
598 u8 linkup;
599 u16 port_type;
600 u16 board_type;
601 };
602
603 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
604 #define ETHERNET_FCS_SIZE 4
605
606 struct netxen_adapter_stats {
607 u64 xmitcalled;
608 u64 xmitfinished;
609 u64 rxdropped;
610 u64 txdropped;
611 u64 csummed;
612 u64 rx_pkts;
613 u64 lro_pkts;
614 u64 rxbytes;
615 u64 txbytes;
616 };
617
618 /*
619 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
620 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
621 */
622 struct nx_host_rds_ring {
623 u32 producer;
624 u32 num_desc;
625 u32 dma_size;
626 u32 skb_size;
627 u32 flags;
628 void __iomem *crb_rcv_producer;
629 struct rcv_desc *desc_head;
630 struct netxen_rx_buffer *rx_buf_arr;
631 struct list_head free_list;
632 spinlock_t lock;
633 dma_addr_t phys_addr;
634 };
635
636 struct nx_host_sds_ring {
637 u32 consumer;
638 u32 num_desc;
639 void __iomem *crb_sts_consumer;
640 void __iomem *crb_intr_mask;
641
642 struct status_desc *desc_head;
643 struct netxen_adapter *adapter;
644 struct napi_struct napi;
645 struct list_head free_list[NUM_RCV_DESC_RINGS];
646
647 int irq;
648
649 dma_addr_t phys_addr;
650 char name[IFNAMSIZ+4];
651 };
652
653 struct nx_host_tx_ring {
654 u32 producer;
655 __le32 *hw_consumer;
656 u32 sw_consumer;
657 void __iomem *crb_cmd_producer;
658 void __iomem *crb_cmd_consumer;
659 u32 num_desc;
660
661 struct netdev_queue *txq;
662
663 struct netxen_cmd_buffer *cmd_buf_arr;
664 struct cmd_desc_type0 *desc_head;
665 dma_addr_t phys_addr;
666 };
667
668 /*
669 * Receive context. There is one such structure per instance of the
670 * receive processing. Any state information that is relevant to
671 * the receive, and is must be in this structure. The global data may be
672 * present elsewhere.
673 */
674 struct netxen_recv_context {
675 u32 state;
676 u16 context_id;
677 u16 virt_port;
678
679 struct nx_host_rds_ring *rds_rings;
680 struct nx_host_sds_ring *sds_rings;
681
682 struct netxen_ring_ctx *hwctx;
683 dma_addr_t phys_addr;
684 };
685
686 /* New HW context creation */
687
688 #define NX_OS_CRB_RETRY_COUNT 4000
689 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
690 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
691
692 #define NX_CDRP_CLEAR 0x00000000
693 #define NX_CDRP_CMD_BIT 0x80000000
694
695 /*
696 * All responses must have the NX_CDRP_CMD_BIT cleared
697 * in the crb NX_CDRP_CRB_OFFSET.
698 */
699 #define NX_CDRP_FORM_RSP(rsp) (rsp)
700 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
701
702 #define NX_CDRP_RSP_OK 0x00000001
703 #define NX_CDRP_RSP_FAIL 0x00000002
704 #define NX_CDRP_RSP_TIMEOUT 0x00000003
705
706 /*
707 * All commands must have the NX_CDRP_CMD_BIT set in
708 * the crb NX_CDRP_CRB_OFFSET.
709 */
710 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
711 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
712
713 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
714 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
715 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
716 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
717 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
718 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
719 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
720 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
721 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
722 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
723 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
724 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
725 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
726 #define NX_CDRP_CMD_SET_MTU 0x00000012
727 #define NX_CDRP_CMD_READ_PHY 0x00000013
728 #define NX_CDRP_CMD_WRITE_PHY 0x00000014
729 #define NX_CDRP_CMD_READ_HW_REG 0x00000015
730 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016
731 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017
732 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018
733 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019
734 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a
735 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b
736 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c
737 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d
738 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e
739 #define NX_CDRP_CMD_MAX 0x0000001f
740
741 #define NX_RCODE_SUCCESS 0
742 #define NX_RCODE_NO_HOST_MEM 1
743 #define NX_RCODE_NO_HOST_RESOURCE 2
744 #define NX_RCODE_NO_CARD_CRB 3
745 #define NX_RCODE_NO_CARD_MEM 4
746 #define NX_RCODE_NO_CARD_RESOURCE 5
747 #define NX_RCODE_INVALID_ARGS 6
748 #define NX_RCODE_INVALID_ACTION 7
749 #define NX_RCODE_INVALID_STATE 8
750 #define NX_RCODE_NOT_SUPPORTED 9
751 #define NX_RCODE_NOT_PERMITTED 10
752 #define NX_RCODE_NOT_READY 11
753 #define NX_RCODE_DOES_NOT_EXIST 12
754 #define NX_RCODE_ALREADY_EXISTS 13
755 #define NX_RCODE_BAD_SIGNATURE 14
756 #define NX_RCODE_CMD_NOT_IMPL 15
757 #define NX_RCODE_CMD_INVALID 16
758 #define NX_RCODE_TIMEOUT 17
759 #define NX_RCODE_CMD_FAILED 18
760 #define NX_RCODE_MAX_EXCEEDED 19
761 #define NX_RCODE_MAX 20
762
763 #define NX_DESTROY_CTX_RESET 0
764 #define NX_DESTROY_CTX_D3_RESET 1
765 #define NX_DESTROY_CTX_MAX 2
766
767 /*
768 * Capabilities
769 */
770 #define NX_CAP_BIT(class, bit) (1 << bit)
771 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
772 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
773 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
774 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
775 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
776 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
777 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
778 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
779 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
780 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10)
781
782 /*
783 * Context state
784 */
785 #define NX_HOST_CTX_STATE_FREED 0
786 #define NX_HOST_CTX_STATE_ALLOCATED 1
787 #define NX_HOST_CTX_STATE_ACTIVE 2
788 #define NX_HOST_CTX_STATE_DISABLED 3
789 #define NX_HOST_CTX_STATE_QUIESCED 4
790 #define NX_HOST_CTX_STATE_MAX 5
791
792 /*
793 * Rx context
794 */
795
796 typedef struct {
797 __le64 host_phys_addr; /* Ring base addr */
798 __le32 ring_size; /* Ring entries */
799 __le16 msi_index;
800 __le16 rsvd; /* Padding */
801 } nx_hostrq_sds_ring_t;
802
803 typedef struct {
804 __le64 host_phys_addr; /* Ring base addr */
805 __le64 buff_size; /* Packet buffer size */
806 __le32 ring_size; /* Ring entries */
807 __le32 ring_kind; /* Class of ring */
808 } nx_hostrq_rds_ring_t;
809
810 typedef struct {
811 __le64 host_rsp_dma_addr; /* Response dma'd here */
812 __le32 capabilities[4]; /* Flag bit vector */
813 __le32 host_int_crb_mode; /* Interrupt crb usage */
814 __le32 host_rds_crb_mode; /* RDS crb usage */
815 /* These ring offsets are relative to data[0] below */
816 __le32 rds_ring_offset; /* Offset to RDS config */
817 __le32 sds_ring_offset; /* Offset to SDS config */
818 __le16 num_rds_rings; /* Count of RDS rings */
819 __le16 num_sds_rings; /* Count of SDS rings */
820 __le16 rsvd1; /* Padding */
821 __le16 rsvd2; /* Padding */
822 u8 reserved[128]; /* reserve space for future expansion*/
823 /* MUST BE 64-bit aligned.
824 The following is packed:
825 - N hostrq_rds_rings
826 - N hostrq_sds_rings */
827 char data[0];
828 } nx_hostrq_rx_ctx_t;
829
830 typedef struct {
831 __le32 host_producer_crb; /* Crb to use */
832 __le32 rsvd1; /* Padding */
833 } nx_cardrsp_rds_ring_t;
834
835 typedef struct {
836 __le32 host_consumer_crb; /* Crb to use */
837 __le32 interrupt_crb; /* Crb to use */
838 } nx_cardrsp_sds_ring_t;
839
840 typedef struct {
841 /* These ring offsets are relative to data[0] below */
842 __le32 rds_ring_offset; /* Offset to RDS config */
843 __le32 sds_ring_offset; /* Offset to SDS config */
844 __le32 host_ctx_state; /* Starting State */
845 __le32 num_fn_per_port; /* How many PCI fn share the port */
846 __le16 num_rds_rings; /* Count of RDS rings */
847 __le16 num_sds_rings; /* Count of SDS rings */
848 __le16 context_id; /* Handle for context */
849 u8 phys_port; /* Physical id of port */
850 u8 virt_port; /* Virtual/Logical id of port */
851 u8 reserved[128]; /* save space for future expansion */
852 /* MUST BE 64-bit aligned.
853 The following is packed:
854 - N cardrsp_rds_rings
855 - N cardrs_sds_rings */
856 char data[0];
857 } nx_cardrsp_rx_ctx_t;
858
859 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
860 (sizeof(HOSTRQ_RX) + \
861 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
862 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
863
864 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
865 (sizeof(CARDRSP_RX) + \
866 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
867 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
868
869 /*
870 * Tx context
871 */
872
873 typedef struct {
874 __le64 host_phys_addr; /* Ring base addr */
875 __le32 ring_size; /* Ring entries */
876 __le32 rsvd; /* Padding */
877 } nx_hostrq_cds_ring_t;
878
879 typedef struct {
880 __le64 host_rsp_dma_addr; /* Response dma'd here */
881 __le64 cmd_cons_dma_addr; /* */
882 __le64 dummy_dma_addr; /* */
883 __le32 capabilities[4]; /* Flag bit vector */
884 __le32 host_int_crb_mode; /* Interrupt crb usage */
885 __le32 rsvd1; /* Padding */
886 __le16 rsvd2; /* Padding */
887 __le16 interrupt_ctl;
888 __le16 msi_index;
889 __le16 rsvd3; /* Padding */
890 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
891 u8 reserved[128]; /* future expansion */
892 } nx_hostrq_tx_ctx_t;
893
894 typedef struct {
895 __le32 host_producer_crb; /* Crb to use */
896 __le32 interrupt_crb; /* Crb to use */
897 } nx_cardrsp_cds_ring_t;
898
899 typedef struct {
900 __le32 host_ctx_state; /* Starting state */
901 __le16 context_id; /* Handle for context */
902 u8 phys_port; /* Physical id of port */
903 u8 virt_port; /* Virtual/Logical id of port */
904 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
905 u8 reserved[128]; /* future expansion */
906 } nx_cardrsp_tx_ctx_t;
907
908 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
909 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
910
911 /* CRB */
912
913 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
914 #define NX_HOST_RDS_CRB_MODE_SHARED 1
915 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
916 #define NX_HOST_RDS_CRB_MODE_MAX 3
917
918 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
919 #define NX_HOST_INT_CRB_MODE_SHARED 1
920 #define NX_HOST_INT_CRB_MODE_NORX 2
921 #define NX_HOST_INT_CRB_MODE_NOTX 3
922 #define NX_HOST_INT_CRB_MODE_NORXTX 4
923
924
925 /* MAC */
926
927 #define MC_COUNT_P2 16
928 #define MC_COUNT_P3 38
929
930 #define NETXEN_MAC_NOOP 0
931 #define NETXEN_MAC_ADD 1
932 #define NETXEN_MAC_DEL 2
933
934 typedef struct nx_mac_list_s {
935 struct list_head list;
936 uint8_t mac_addr[ETH_ALEN+2];
937 } nx_mac_list_t;
938
939 /*
940 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
941 * adjusted based on configured MTU.
942 */
943 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
944 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
945 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
946 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
947
948 #define NETXEN_NIC_INTR_DEFAULT 0x04
949
950 typedef union {
951 struct {
952 uint16_t rx_packets;
953 uint16_t rx_time_us;
954 uint16_t tx_packets;
955 uint16_t tx_time_us;
956 } data;
957 uint64_t word;
958 } nx_nic_intr_coalesce_data_t;
959
960 typedef struct {
961 uint16_t stats_time_us;
962 uint16_t rate_sample_time;
963 uint16_t flags;
964 uint16_t rsvd_1;
965 uint32_t low_threshold;
966 uint32_t high_threshold;
967 nx_nic_intr_coalesce_data_t normal;
968 nx_nic_intr_coalesce_data_t low;
969 nx_nic_intr_coalesce_data_t high;
970 nx_nic_intr_coalesce_data_t irq;
971 } nx_nic_intr_coalesce_t;
972
973 #define NX_HOST_REQUEST 0x13
974 #define NX_NIC_REQUEST 0x14
975
976 #define NX_MAC_EVENT 0x1
977
978 #define NX_IP_UP 2
979 #define NX_IP_DOWN 3
980
981 /*
982 * Driver --> Firmware
983 */
984 #define NX_NIC_H2C_OPCODE_START 0
985 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1
986 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2
987 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3
988 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4
989 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5
990 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6
991 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7
992 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8
993 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9
994 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10
995 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11
996 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12
997 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13
998 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14
999 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15
1000 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16
1001 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17
1002 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18
1003 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19
1004 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20
1005 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21
1006 #define NX_NIC_C2C_OPCODE 22
1007 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23
1008 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24
1009 #define NX_NIC_H2C_OPCODE_LAST 25
1010
1011 /*
1012 * Firmware --> Driver
1013 */
1014
1015 #define NX_NIC_C2H_OPCODE_START 128
1016 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129
1017 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130
1018 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131
1019 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132
1020 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133
1021 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134
1022 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135
1023 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136
1024 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137
1025 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138
1026 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1027 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140
1028 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
1029 #define NX_NIC_C2H_OPCODE_LAST 142
1030
1031 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1032 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1033 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1034
1035 #define NX_NIC_LRO_REQUEST_FIRST 0
1036 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1
1037 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2
1038 #define NX_NIC_LRO_REQUEST_TIMER 3
1039 #define NX_NIC_LRO_REQUEST_CLEANUP 4
1040 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5
1041 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6
1042 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7
1043 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8
1044 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9
1045 #define NX_TOE_LRO_REQUEST_TIMER 10
1046 #define NX_NIC_LRO_REQUEST_LAST 11
1047
1048 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5)
1049 #define NX_FW_CAPABILITY_SWITCHING (1 << 6)
1050 #define NX_FW_CAPABILITY_PEXQ (1 << 7)
1051 #define NX_FW_CAPABILITY_BDG (1 << 8)
1052 #define NX_FW_CAPABILITY_FVLANTX (1 << 9)
1053 #define NX_FW_CAPABILITY_HW_LRO (1 << 10)
1054
1055 /* module types */
1056 #define LINKEVENT_MODULE_NOT_PRESENT 1
1057 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
1058 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
1059 #define LINKEVENT_MODULE_OPTICAL_LRM 4
1060 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
1061 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
1062 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
1063 #define LINKEVENT_MODULE_TWINAX 8
1064
1065 #define LINKSPEED_10GBPS 10000
1066 #define LINKSPEED_1GBPS 1000
1067 #define LINKSPEED_100MBPS 100
1068 #define LINKSPEED_10MBPS 10
1069
1070 #define LINKSPEED_ENCODED_10MBPS 0
1071 #define LINKSPEED_ENCODED_100MBPS 1
1072 #define LINKSPEED_ENCODED_1GBPS 2
1073
1074 #define LINKEVENT_AUTONEG_DISABLED 0
1075 #define LINKEVENT_AUTONEG_ENABLED 1
1076
1077 #define LINKEVENT_HALF_DUPLEX 0
1078 #define LINKEVENT_FULL_DUPLEX 1
1079
1080 #define LINKEVENT_LINKSPEED_MBPS 0
1081 #define LINKEVENT_LINKSPEED_ENCODED 1
1082
1083 #define AUTO_FW_RESET_ENABLED 0xEF10AF12
1084 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12
1085
1086 /* firmware response header:
1087 * 63:58 - message type
1088 * 57:56 - owner
1089 * 55:53 - desc count
1090 * 52:48 - reserved
1091 * 47:40 - completion id
1092 * 39:32 - opcode
1093 * 31:16 - error code
1094 * 15:00 - reserved
1095 */
1096 #define netxen_get_nic_msgtype(msg_hdr) \
1097 ((msg_hdr >> 58) & 0x3F)
1098 #define netxen_get_nic_msg_compid(msg_hdr) \
1099 ((msg_hdr >> 40) & 0xFF)
1100 #define netxen_get_nic_msg_opcode(msg_hdr) \
1101 ((msg_hdr >> 32) & 0xFF)
1102 #define netxen_get_nic_msg_errcode(msg_hdr) \
1103 ((msg_hdr >> 16) & 0xFFFF)
1104
1105 typedef struct {
1106 union {
1107 struct {
1108 u64 hdr;
1109 u64 body[7];
1110 };
1111 u64 words[8];
1112 };
1113 } nx_fw_msg_t;
1114
1115 typedef struct {
1116 __le64 qhdr;
1117 __le64 req_hdr;
1118 __le64 words[6];
1119 } nx_nic_req_t;
1120
1121 typedef struct {
1122 u8 op;
1123 u8 tag;
1124 u8 mac_addr[6];
1125 } nx_mac_req_t;
1126
1127 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1128
1129 #define NETXEN_NIC_MSI_ENABLED 0x02
1130 #define NETXEN_NIC_MSIX_ENABLED 0x04
1131 #define NETXEN_NIC_LRO_ENABLED 0x08
1132 #define NETXEN_NIC_BRIDGE_ENABLED 0X10
1133 #define NETXEN_NIC_DIAG_ENABLED 0x20
1134 #define NETXEN_IS_MSI_FAMILY(adapter) \
1135 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1136
1137 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1138 #define NETXEN_MSIX_TBL_SPACE 8192
1139 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1140
1141 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1142
1143 #define NETXEN_NETDEV_WEIGHT 128
1144 #define NETXEN_ADAPTER_UP_MAGIC 777
1145 #define NETXEN_NIC_PEG_TUNE 0
1146
1147 #define __NX_FW_ATTACHED 0
1148 #define __NX_DEV_UP 1
1149 #define __NX_RESETTING 2
1150
1151 struct netxen_dummy_dma {
1152 void *addr;
1153 dma_addr_t phys_addr;
1154 };
1155
1156 struct netxen_adapter {
1157 struct netxen_hardware_context ahw;
1158
1159 struct net_device *netdev;
1160 struct pci_dev *pdev;
1161 struct list_head mac_list;
1162
1163 spinlock_t tx_clean_lock;
1164
1165 u16 num_txd;
1166 u16 num_rxd;
1167 u16 num_jumbo_rxd;
1168 u16 num_lro_rxd;
1169
1170 u8 max_rds_rings;
1171 u8 max_sds_rings;
1172 u8 driver_mismatch;
1173 u8 msix_supported;
1174 u8 rx_csum;
1175 u8 pci_using_dac;
1176 u8 portnum;
1177 u8 physical_port;
1178
1179 u8 mc_enabled;
1180 u8 max_mc_count;
1181 u8 rss_supported;
1182 u8 link_changed;
1183 u8 fw_wait_cnt;
1184 u8 fw_fail_cnt;
1185 u8 tx_timeo_cnt;
1186 u8 need_fw_reset;
1187
1188 u8 has_link_events;
1189 u8 fw_type;
1190 u16 tx_context_id;
1191 u16 mtu;
1192 u16 is_up;
1193
1194 u16 link_speed;
1195 u16 link_duplex;
1196 u16 link_autoneg;
1197 u16 module_type;
1198
1199 u32 capabilities;
1200 u32 flags;
1201 u32 irq;
1202 u32 temp;
1203
1204 u32 int_vec_bit;
1205 u32 heartbit;
1206
1207 u8 mac_addr[ETH_ALEN];
1208
1209 struct netxen_adapter_stats stats;
1210
1211 struct netxen_recv_context recv_ctx;
1212 struct nx_host_tx_ring *tx_ring;
1213
1214 int (*macaddr_set) (struct netxen_adapter *, u8 *);
1215 int (*set_mtu) (struct netxen_adapter *, int);
1216 int (*set_promisc) (struct netxen_adapter *, u32);
1217 void (*set_multi) (struct net_device *);
1218 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *);
1219 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val);
1220 int (*init_port) (struct netxen_adapter *, int);
1221 int (*stop_port) (struct netxen_adapter *);
1222
1223 u32 (*crb_read)(struct netxen_adapter *, ulong);
1224 int (*crb_write)(struct netxen_adapter *, ulong, u32);
1225
1226 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *);
1227 int (*pci_mem_write)(struct netxen_adapter *, u64, u64);
1228
1229 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *);
1230
1231 u32 (*io_read)(struct netxen_adapter *, void __iomem *);
1232 void (*io_write)(struct netxen_adapter *, void __iomem *, u32);
1233
1234 void __iomem *tgt_mask_reg;
1235 void __iomem *pci_int_reg;
1236 void __iomem *tgt_status_reg;
1237 void __iomem *crb_int_state_reg;
1238 void __iomem *isr_int_vec;
1239
1240 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1241
1242 struct netxen_dummy_dma dummy_dma;
1243
1244 struct delayed_work fw_work;
1245
1246 struct work_struct tx_timeout_task;
1247
1248 nx_nic_intr_coalesce_t coal;
1249
1250 unsigned long state;
1251 __le32 file_prd_off; /*File fw product offset*/
1252 u32 fw_version;
1253 const struct firmware *fw;
1254 };
1255
1256 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port);
1257 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter);
1258
1259 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val);
1260 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val);
1261
1262 /* Functions available from netxen_nic_hw.c */
1263 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1264 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1265
1266 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1267 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1268
1269 #define NXRD32(adapter, off) \
1270 (adapter->crb_read(adapter, off))
1271 #define NXWR32(adapter, off, val) \
1272 (adapter->crb_write(adapter, off, val))
1273 #define NXRDIO(adapter, addr) \
1274 (adapter->io_read(adapter, addr))
1275 #define NXWRIO(adapter, addr, val) \
1276 (adapter->io_write(adapter, addr, val))
1277
1278 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32);
1279 void netxen_pcie_sem_unlock(struct netxen_adapter *, int);
1280
1281 #define netxen_rom_lock(a) \
1282 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID)
1283 #define netxen_rom_unlock(a) \
1284 netxen_pcie_sem_unlock((a), 2)
1285 #define netxen_phy_lock(a) \
1286 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID)
1287 #define netxen_phy_unlock(a) \
1288 netxen_pcie_sem_unlock((a), 3)
1289 #define netxen_api_lock(a) \
1290 netxen_pcie_sem_lock((a), 5, 0)
1291 #define netxen_api_unlock(a) \
1292 netxen_pcie_sem_unlock((a), 5)
1293 #define netxen_sw_lock(a) \
1294 netxen_pcie_sem_lock((a), 6, 0)
1295 #define netxen_sw_unlock(a) \
1296 netxen_pcie_sem_unlock((a), 6)
1297 #define crb_win_lock(a) \
1298 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID)
1299 #define crb_win_unlock(a) \
1300 netxen_pcie_sem_unlock((a), 7)
1301
1302 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1303 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1304
1305 /* Functions from netxen_nic_init.c */
1306 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1307 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1308
1309 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1310 int netxen_load_firmware(struct netxen_adapter *adapter);
1311 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1312 void netxen_request_firmware(struct netxen_adapter *adapter);
1313 void netxen_release_firmware(struct netxen_adapter *adapter);
1314 int netxen_pinit_from_rom(struct netxen_adapter *adapter);
1315
1316 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1317 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1318 u8 *bytes, size_t size);
1319 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1320 u8 *bytes, size_t size);
1321 int netxen_flash_unlock(struct netxen_adapter *adapter);
1322 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1323 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1324 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1325 void netxen_halt_pegs(struct netxen_adapter *adapter);
1326
1327 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1328
1329 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1330 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1331
1332 void netxen_setup_hwops(struct netxen_adapter *adapter);
1333 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32);
1334
1335 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1336 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1337
1338 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1339 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1340
1341 int netxen_init_firmware(struct netxen_adapter *adapter);
1342 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1343 void netxen_watchdog_task(struct work_struct *work);
1344 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1345 struct nx_host_rds_ring *rds_ring);
1346 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1347 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1348 void netxen_p2_nic_set_multi(struct net_device *netdev);
1349 void netxen_p3_nic_set_multi(struct net_device *netdev);
1350 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1351 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode);
1352 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1353 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1354 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1355 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1356 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1357 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1358 void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *);
1359 void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64);
1360
1361 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1362 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1363 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable);
1364 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable);
1365 int netxen_send_lro_cleanup(struct netxen_adapter *adapter);
1366
1367 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1368 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1369
1370 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1371 struct nx_host_tx_ring *tx_ring);
1372
1373 /* Functions from netxen_nic_main.c */
1374 int netxen_nic_reset_context(struct netxen_adapter *);
1375
1376 /*
1377 * NetXen Board information
1378 */
1379
1380 #define NETXEN_MAX_SHORT_NAME 32
1381 struct netxen_brdinfo {
1382 int brdtype; /* type of board */
1383 long ports; /* max no of physical ports */
1384 char short_name[NETXEN_MAX_SHORT_NAME];
1385 };
1386
1387 static const struct netxen_brdinfo netxen_boards[] = {
1388 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1389 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1390 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1391 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1392 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1393 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1394 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1395 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1396 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1397 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1398 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1399 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1400 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1401 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1402 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1403 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1404 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1405 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1406 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1407 };
1408
1409 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1410
1411 static inline void get_brd_name_by_type(u32 type, char *name)
1412 {
1413 int i, found = 0;
1414 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1415 if (netxen_boards[i].brdtype == type) {
1416 strcpy(name, netxen_boards[i].short_name);
1417 found = 1;
1418 break;
1419 }
1420
1421 }
1422 if (!found)
1423 name = "Unknown";
1424 }
1425
1426 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1427 {
1428 smp_mb();
1429 return find_diff_among(tx_ring->producer,
1430 tx_ring->sw_consumer, tx_ring->num_desc);
1431
1432 }
1433
1434 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1435 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac);
1436 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1437 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1438 int *valp);
1439
1440 extern const struct ethtool_ops netxen_nic_ethtool_ops;
1441
1442 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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