drivers/net/netxen/netxen_nic.h

   1 /*
   2  * Copyright (C) 2003 - 2009 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen Inc,
  26  * 18922 Forge Drive
  27  * Cupertino, CA 95014-0701
  28  *
  29  */
  30
  31 #ifndef _NETXEN_NIC_H_
  32 #define _NETXEN_NIC_H_
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ioport.h>
  38 #include <linux/pci.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/ip.h>
  42 #include <linux/in.h>
  43 #include <linux/tcp.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/firmware.h>
  46
  47 #include <linux/ethtool.h>
  48 #include <linux/mii.h>
  49 #include <linux/timer.h>
  50
  51 #include <linux/vmalloc.h>
  52
  53 #include <asm/io.h>
  54 #include <asm/byteorder.h>
  55
  56 #include "netxen_nic_hw.h"
  57
  58 #define _NETXEN_NIC_LINUX_MAJOR 4
  59 #define _NETXEN_NIC_LINUX_MINOR 0
  60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
  61 #define NETXEN_NIC_LINUX_VERSIONID  "4.0.30"
  62
  63 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
  64 #define _major(v)       (((v) >> 24) & 0xff)
  65 #define _minor(v)       (((v) >> 16) & 0xff)
  66 #define _build(v)       ((v) & 0xffff)
  67
  68 /* version in image has weird encoding:
  69  *  7:0  - major
  70  * 15:8  - minor
  71  * 31:16 - build (little endian)
  72  */
  73 #define NETXEN_DECODE_VERSION(v) \
  74         NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
  75
  76 #define NETXEN_NUM_FLASH_SECTORS (64)
  77 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  78 #define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  79                                         * NETXEN_FLASH_SECTOR_SIZE)
  80
  81 #define PHAN_VENDOR_ID 0x4040
  82
  83 #define RCV_DESC_RINGSIZE(rds_ring)     \
  84         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  85 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  86         (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  87 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  88         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  89 #define TX_BUFF_RINGSIZE(tx_ring)       \
  90         (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  91 #define TX_DESC_RINGSIZE(tx_ring)       \
  92         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  93
  94 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  95
  96 #define NETXEN_RCV_PRODUCER_OFFSET      0
  97 #define NETXEN_RCV_PEG_DB_ID            2
  98 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  99 #define FLASH_SUCCESS 0
 100
 101 #define ADDR_IN_WINDOW1(off)    \
 102         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
 103
 104 /*
 105  * normalize a 64MB crb address to 32MB PCI window
 106  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
 107  */
 108 #define NETXEN_CRB_NORMAL(reg)  \
 109         ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
 110
 111 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
 112         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 113
 114 #define DB_NORMALIZE(adapter, off) \
 115         (adapter->ahw.db_base + (off))
 116
 117 #define NX_P2_C0                0x24
 118 #define NX_P2_C1                0x25
 119 #define NX_P3_A0                0x30
 120 #define NX_P3_A2                0x30
 121 #define NX_P3_B0                0x40
 122 #define NX_P3_B1                0x41
 123 #define NX_P3_B2                0x42
 124
 125 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 126 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 127
 128 #define FIRST_PAGE_GROUP_START  0
 129 #define FIRST_PAGE_GROUP_END    0x100000
 130
 131 #define SECOND_PAGE_GROUP_START 0x6000000
 132 #define SECOND_PAGE_GROUP_END   0x68BC000
 133
 134 #define THIRD_PAGE_GROUP_START  0x70E4000
 135 #define THIRD_PAGE_GROUP_END    0x8000000
 136
 137 #define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 138 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 139 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 140
 141 #define P2_MAX_MTU                     (8000)
 142 #define P3_MAX_MTU                     (9600)
 143 #define NX_ETHERMTU                    1500
 144 #define NX_MAX_ETHERHDR                32 /* This contains some padding */
 145
 146 #define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 149 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 150
 151 #define MAX_RX_BUFFER_LENGTH            1760
 152 #define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 153 #define MAX_RX_LRO_BUFFER_LENGTH        (8062)
 154 #define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 155 #define RX_JUMBO_DMA_MAP_LEN    \
 156         (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 157 #define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 158
 159 /*
 160  * Maximum number of ring contexts
 161  */
 162 #define MAX_RING_CTX 1
 163
 164 /* Opcodes to be used with the commands */
 165 #define TX_ETHER_PKT    0x01
 166 #define TX_TCP_PKT      0x02
 167 #define TX_UDP_PKT      0x03
 168 #define TX_IP_PKT       0x04
 169 #define TX_TCP_LSO      0x05
 170 #define TX_TCP_LSO6     0x06
 171 #define TX_IPSEC        0x07
 172 #define TX_IPSEC_CMD    0x0a
 173 #define TX_TCPV6_PKT    0x0b
 174 #define TX_UDPV6_PKT    0x0c
 175
 176 /* The following opcodes are for internal consumption. */
 177 #define NETXEN_CONTROL_OP       0x10
 178 #define PEGNET_REQUEST          0x11
 179
 180 #define MAX_NUM_CARDS           4
 181
 182 #define MAX_BUFFERS_PER_CMD     32
 183 #define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + 4)
 184
 185 /*
 186  * Following are the states of the Phantom. Phantom will set them and
 187  * Host will read to check if the fields are correct.
 188  */
 189 #define PHAN_INITIALIZE_START           0xff00
 190 #define PHAN_INITIALIZE_FAILED          0xffff
 191 #define PHAN_INITIALIZE_COMPLETE        0xff01
 192
 193 /* Host writes the following to notify that it has done the init-handshake */
 194 #define PHAN_INITIALIZE_ACK     0xf00f
 195
 196 #define NUM_RCV_DESC_RINGS      3
 197 #define NUM_STS_DESC_RINGS      4
 198
 199 #define RCV_RING_NORMAL 0
 200 #define RCV_RING_JUMBO  1
 201 #define RCV_RING_LRO    2
 202
 203 #define MAX_CMD_DESCRIPTORS             4096
 204 #define MAX_RCV_DESCRIPTORS             16384
 205 #define MAX_CMD_DESCRIPTORS_HOST        1024
 206 #define MAX_RCV_DESCRIPTORS_1G          2048
 207 #define MAX_RCV_DESCRIPTORS_10G         4096
 208 #define MAX_JUMBO_RCV_DESCRIPTORS       1024
 209 #define MAX_LRO_RCV_DESCRIPTORS         8
 210 #define NETXEN_CTX_SIGNATURE    0xdee0
 211 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
 212 #define NETXEN_CTX_RESET        0xbad0
 213 #define NETXEN_CTX_D3_RESET     0xacc0
 214 #define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 215
 216 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 217 #define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 218
 219 #define get_next_index(index, length)   \
 220         (((index) + 1) & ((length) - 1))
 221
 222 #define get_index_range(index,length,count)     \
 223         (((index) + (count)) & ((length) - 1))
 224
 225 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
 226 #define MPORT_MULTI_FUNCTION_MODE 0x2222
 227
 228 #include "netxen_nic_phan_reg.h"
 229
 230 /*
 231  * NetXen host-peg signal message structure
 232  *
 233  *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 234  *      Bit 2           : priv_id => must be 1
 235  *      Bit 3-17        : count => for doorbell
 236  *      Bit 18-27       : ctx_id => Context id
 237  *      Bit 28-31       : opcode
 238  */
 239
 240 typedef u32 netxen_ctx_msg;
 241
 242 #define netxen_set_msg_peg_id(config_word, val) \
 243         ((config_word) &= ~3, (config_word) |= val & 3)
 244 #define netxen_set_msg_privid(config_word)      \
 245         ((config_word) |= 1 << 2)
 246 #define netxen_set_msg_count(config_word, val)  \
 247         ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 248 #define netxen_set_msg_ctxid(config_word, val)  \
 249         ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 250 #define netxen_set_msg_opcode(config_word, val) \
 251         ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 252
 253 struct netxen_rcv_ring {
 254         __le64 addr;
 255         __le32 size;
 256         __le32 rsrvd;
 257 };
 258
 259 struct netxen_sts_ring {
 260         __le64 addr;
 261         __le32 size;
 262         __le16 msi_index;
 263         __le16 rsvd;
 264 } ;
 265
 266 struct netxen_ring_ctx {
 267
 268         /* one command ring */
 269         __le64 cmd_consumer_offset;
 270         __le64 cmd_ring_addr;
 271         __le32 cmd_ring_size;
 272         __le32 rsrvd;
 273
 274         /* three receive rings */
 275         struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
 276
 277         __le64 sts_ring_addr;
 278         __le32 sts_ring_size;
 279
 280         __le32 ctx_id;
 281
 282         __le64 rsrvd_2[3];
 283         __le32 sts_ring_count;
 284         __le32 rsrvd_3;
 285         struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
 286
 287 } __attribute__ ((aligned(64)));
 288
 289 /*
 290  * Following data structures describe the descriptors that will be used.
 291  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 292  * we are doing LSO (above the 1500 size packet) only.
 293  */
 294
 295 /*
 296  * The size of reference handle been changed to 16 bits to pass the MSS fields
 297  * for the LSO packet
 298  */
 299
 300 #define FLAGS_CHECKSUM_ENABLED  0x01
 301 #define FLAGS_LSO_ENABLED       0x02
 302 #define FLAGS_IPSEC_SA_ADD      0x04
 303 #define FLAGS_IPSEC_SA_DELETE   0x08
 304 #define FLAGS_VLAN_TAGGED       0x10
 305
 306 #define netxen_set_cmd_desc_port(cmd_desc, var) \
 307         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 308 #define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 309         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 310
 311 #define netxen_set_tx_port(_desc, _port) \
 312         (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
 313
 314 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
 315         (_desc)->flags_opcode = \
 316         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
 317
 318 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
 319         (_desc)->num_of_buffers_total_length = \
 320         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
 321
 322 struct cmd_desc_type0 {
 323         u8 tcp_hdr_offset;      /* For LSO only */
 324         u8 ip_hdr_offset;       /* For LSO only */
 325         /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
 326         __le16 flags_opcode;
 327         /* Bit pattern: 0-7 total number of segments,
 328            8-31 Total size of the packet */
 329         __le32 num_of_buffers_total_length;
 330         union {
 331                 struct {
 332                         __le32 addr_low_part2;
 333                         __le32 addr_high_part2;
 334                 };
 335                 __le64 addr_buffer2;
 336         };
 337
 338         __le16 reference_handle;        /* changed to u16 to add mss */
 339         __le16 mss;             /* passed by NDIS_PACKET for LSO */
 340         /* Bit pattern 0-3 port, 0-3 ctx id */
 341         u8 port_ctxid;
 342         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 343         __le16 conn_id;         /* IPSec offoad only */
 344
 345         union {
 346                 struct {
 347                         __le32 addr_low_part3;
 348                         __le32 addr_high_part3;
 349                 };
 350                 __le64 addr_buffer3;
 351         };
 352         union {
 353                 struct {
 354                         __le32 addr_low_part1;
 355                         __le32 addr_high_part1;
 356                 };
 357                 __le64 addr_buffer1;
 358         };
 359
 360         __le16 buffer_length[4];
 361
 362         union {
 363                 struct {
 364                         __le32 addr_low_part4;
 365                         __le32 addr_high_part4;
 366                 };
 367                 __le64 addr_buffer4;
 368         };
 369
 370         __le64 unused;
 371
 372 } __attribute__ ((aligned(64)));
 373
 374 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 375 struct rcv_desc {
 376         __le16 reference_handle;
 377         __le16 reserved;
 378         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 379         __le64 addr_buffer;
 380 };
 381
 382 /* opcode field in status_desc */
 383 #define NETXEN_NIC_RXPKT_DESC  0x04
 384 #define NETXEN_OLD_RXPKT_DESC  0x3f
 385 #define NETXEN_NIC_RESPONSE_DESC 0x05
 386
 387 /* for status field in status_desc */
 388 #define STATUS_NEED_CKSUM       (1)
 389 #define STATUS_CKSUM_OK         (2)
 390
 391 /* owner bits of status_desc */
 392 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 393 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 394
 395 /* Status descriptor:
 396    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 397    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 398    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 399  */
 400 #define netxen_get_sts_port(sts_data)   \
 401         ((sts_data) & 0x0F)
 402 #define netxen_get_sts_status(sts_data) \
 403         (((sts_data) >> 4) & 0x0F)
 404 #define netxen_get_sts_type(sts_data)   \
 405         (((sts_data) >> 8) & 0x0F)
 406 #define netxen_get_sts_totallength(sts_data)    \
 407         (((sts_data) >> 12) & 0xFFFF)
 408 #define netxen_get_sts_refhandle(sts_data)      \
 409         (((sts_data) >> 28) & 0xFFFF)
 410 #define netxen_get_sts_prot(sts_data)   \
 411         (((sts_data) >> 44) & 0x0F)
 412 #define netxen_get_sts_pkt_offset(sts_data)     \
 413         (((sts_data) >> 48) & 0x1F)
 414 #define netxen_get_sts_desc_cnt(sts_data)       \
 415         (((sts_data) >> 53) & 0x7)
 416 #define netxen_get_sts_opcode(sts_data) \
 417         (((sts_data) >> 58) & 0x03F)
 418
 419 struct status_desc {
 420         __le64 status_desc_data[2];
 421 } __attribute__ ((aligned(16)));
 422
 423 /* The version of the main data structure */
 424 #define NETXEN_BDINFO_VERSION 1
 425
 426 /* Magic number to let user know flash is programmed */
 427 #define NETXEN_BDINFO_MAGIC 0x12345678
 428
 429 /* Max number of Gig ports on a Phantom board */
 430 #define NETXEN_MAX_PORTS 4
 431
 432 #define NETXEN_BRDTYPE_P1_BD            0x0000
 433 #define NETXEN_BRDTYPE_P1_SB            0x0001
 434 #define NETXEN_BRDTYPE_P1_SMAX          0x0002
 435 #define NETXEN_BRDTYPE_P1_SOCK          0x0003
 436
 437 #define NETXEN_BRDTYPE_P2_SOCK_31       0x0008
 438 #define NETXEN_BRDTYPE_P2_SOCK_35       0x0009
 439 #define NETXEN_BRDTYPE_P2_SB35_4G       0x000a
 440 #define NETXEN_BRDTYPE_P2_SB31_10G      0x000b
 441 #define NETXEN_BRDTYPE_P2_SB31_2G       0x000c
 442
 443 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ         0x000d
 444 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ         0x000e
 445 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4          0x000f
 446
 447 #define NETXEN_BRDTYPE_P3_REF_QG        0x0021
 448 #define NETXEN_BRDTYPE_P3_HMEZ          0x0022
 449 #define NETXEN_BRDTYPE_P3_10G_CX4_LP    0x0023
 450 #define NETXEN_BRDTYPE_P3_4_GB          0x0024
 451 #define NETXEN_BRDTYPE_P3_IMEZ          0x0025
 452 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS  0x0026
 453 #define NETXEN_BRDTYPE_P3_10000_BASE_T  0x0027
 454 #define NETXEN_BRDTYPE_P3_XG_LOM        0x0028
 455 #define NETXEN_BRDTYPE_P3_4_GB_MM       0x0029
 456 #define NETXEN_BRDTYPE_P3_10G_SFP_CT    0x002a
 457 #define NETXEN_BRDTYPE_P3_10G_SFP_QT    0x002b
 458 #define NETXEN_BRDTYPE_P3_10G_CX4       0x0031
 459 #define NETXEN_BRDTYPE_P3_10G_XFP       0x0032
 460 #define NETXEN_BRDTYPE_P3_10G_TP        0x0080
 461
 462 struct netxen_board_info {
 463         u32 header_version;
 464
 465         u32 board_mfg;
 466         u32 board_type;
 467         u32 board_num;
 468         u32 chip_id;
 469         u32 chip_minor;
 470         u32 chip_major;
 471         u32 chip_pkg;
 472         u32 chip_lot;
 473
 474         u32 port_mask;          /* available niu ports */
 475         u32 peg_mask;           /* available pegs */
 476         u32 icache_ok;          /* can we run with icache? */
 477         u32 dcache_ok;          /* can we run with dcache? */
 478         u32 casper_ok;
 479
 480         u32 mac_addr_lo_0;
 481         u32 mac_addr_lo_1;
 482         u32 mac_addr_lo_2;
 483         u32 mac_addr_lo_3;
 484
 485         /* MN-related config */
 486         u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 487         u32 mn_sync_shift_cclk;
 488         u32 mn_sync_shift_mclk;
 489         u32 mn_wb_en;
 490         u32 mn_crystal_freq;    /* in MHz */
 491         u32 mn_speed;           /* in MHz */
 492         u32 mn_org;
 493         u32 mn_depth;
 494         u32 mn_ranks_0;         /* ranks per slot */
 495         u32 mn_ranks_1;         /* ranks per slot */
 496         u32 mn_rd_latency_0;
 497         u32 mn_rd_latency_1;
 498         u32 mn_rd_latency_2;
 499         u32 mn_rd_latency_3;
 500         u32 mn_rd_latency_4;
 501         u32 mn_rd_latency_5;
 502         u32 mn_rd_latency_6;
 503         u32 mn_rd_latency_7;
 504         u32 mn_rd_latency_8;
 505         u32 mn_dll_val[18];
 506         u32 mn_mode_reg;        /* MIU DDR Mode Register */
 507         u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 508         u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 509         u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 510         u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 511
 512         /* SN-related config */
 513         u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 514         u32 sn_pt_mode;         /* pass through mode */
 515         u32 sn_ecc_en;
 516         u32 sn_wb_en;
 517         u32 sn_crystal_freq;
 518         u32 sn_speed;
 519         u32 sn_org;
 520         u32 sn_depth;
 521         u32 sn_dll_tap;
 522         u32 sn_rd_latency;
 523
 524         u32 mac_addr_hi_0;
 525         u32 mac_addr_hi_1;
 526         u32 mac_addr_hi_2;
 527         u32 mac_addr_hi_3;
 528
 529         u32 magic;              /* indicates flash has been initialized */
 530
 531         u32 mn_rdimm;
 532         u32 mn_dll_override;
 533
 534 };
 535
 536 #define FLASH_NUM_PORTS         (4)
 537
 538 struct netxen_flash_mac_addr {
 539         u32 flash_addr[32];
 540 };
 541
 542 struct netxen_user_old_info {
 543         u8 flash_md5[16];
 544         u8 crbinit_md5[16];
 545         u8 brdcfg_md5[16];
 546         /* bootloader */
 547         u32 bootld_version;
 548         u32 bootld_size;
 549         u8 bootld_md5[16];
 550         /* image */
 551         u32 image_version;
 552         u32 image_size;
 553         u8 image_md5[16];
 554         /* primary image status */
 555         u32 primary_status;
 556         u32 secondary_present;
 557
 558         /* MAC address , 4 ports */
 559         struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 560 };
 561 #define FLASH_NUM_MAC_PER_PORT  32
 562 struct netxen_user_info {
 563         u8 flash_md5[16 * 64];
 564         /* bootloader */
 565         u32 bootld_version;
 566         u32 bootld_size;
 567         /* image */
 568         u32 image_version;
 569         u32 image_size;
 570         /* primary image status */
 571         u32 primary_status;
 572         u32 secondary_present;
 573
 574         /* MAC address , 4 ports, 32 address per port */
 575         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 576         u32 sub_sys_id;
 577         u8 serial_num[32];
 578
 579         /* Any user defined data */
 580 };
 581
 582 /*
 583  * Flash Layout - new format.
 584  */
 585 struct netxen_new_user_info {
 586         u8 flash_md5[16 * 64];
 587         /* bootloader */
 588         u32 bootld_version;
 589         u32 bootld_size;
 590         /* image */
 591         u32 image_version;
 592         u32 image_size;
 593         /* primary image status */
 594         u32 primary_status;
 595         u32 secondary_present;
 596
 597         /* MAC address , 4 ports, 32 address per port */
 598         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 599         u32 sub_sys_id;
 600         u8 serial_num[32];
 601
 602         /* Any user defined data */
 603 };
 604
 605 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 606 #define SECONDARY_IMAGE_ABSENT  0xffffffff
 607 #define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 608 #define PRIMARY_IMAGE_BAD       0xffffffff
 609
 610 /* Flash memory map */
 611 #define NETXEN_CRBINIT_START    0       /* crbinit section */
 612 #define NETXEN_BRDCFG_START     0x4000  /* board config */
 613 #define NETXEN_INITCODE_START   0x6000  /* pegtune code */
 614 #define NETXEN_BOOTLD_START     0x10000 /* bootld */
 615 #define NETXEN_IMAGE_START      0x43000 /* compressed image */
 616 #define NETXEN_SECONDARY_START  0x200000        /* backup images */
 617 #define NETXEN_PXE_START        0x3E0000        /* PXE boot rom */
 618 #define NETXEN_USER_START       0x3E8000        /* Firmare info */
 619 #define NETXEN_FIXED_START      0x3F0000        /* backup of crbinit */
 620
 621 #define NX_FW_VERSION_OFFSET    (NETXEN_USER_START+0x408)
 622 #define NX_FW_SIZE_OFFSET       (NETXEN_USER_START+0x40c)
 623 #define NX_BIOS_VERSION_OFFSET  (NETXEN_USER_START+0x83c)
 624 #define NX_FW_MAGIC_OFFSET      (NETXEN_BRDCFG_START+0x128)
 625 #define NX_FW_MIN_SIZE          (0x3fffff)
 626 #define NX_P2_MN_ROMIMAGE       0
 627 #define NX_P3_CT_ROMIMAGE       1
 628 #define NX_P3_MN_ROMIMAGE       2
 629 #define NX_FLASH_ROMIMAGE       3
 630
 631 #define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 632
 633 #define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 634 #define NETXEN_INIT_SECTOR              (0)
 635 #define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 636 #define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 637 #define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 638 #define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 639 #define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 640 #define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 641 #define NETXEN_NUM_CONFIG_SECTORS       (1)
 642 extern char netxen_nic_driver_name[];
 643
 644 /* Number of status descriptors to handle per interrupt */
 645 #define MAX_STATUS_HANDLE       (64)
 646
 647 /*
 648  * netxen_skb_frag{} is to contain mapping info for each SG list. This
 649  * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 650  */
 651 struct netxen_skb_frag {
 652         u64 dma;
 653         u64 length;
 654 };
 655
 656 #define _netxen_set_bits(config_word, start, bits, val) {\
 657         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 658         unsigned long long __tvalue = (val);    \
 659         (config_word) &= ~__tmask;      \
 660         (config_word) |= (((__tvalue) << (start)) & __tmask); \
 661 }
 662
 663 #define _netxen_clear_bits(config_word, start, bits) {\
 664         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 665         (config_word) &= ~__tmask; \
 666 }
 667
 668 /*    Following defines are for the state of the buffers    */
 669 #define NETXEN_BUFFER_FREE      0
 670 #define NETXEN_BUFFER_BUSY      1
 671
 672 /*
 673  * There will be one netxen_buffer per skb packet.    These will be
 674  * used to save the dma info for pci_unmap_page()
 675  */
 676 struct netxen_cmd_buffer {
 677         struct sk_buff *skb;
 678         struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 679         u32 frag_count;
 680 };
 681
 682 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 683 struct netxen_rx_buffer {
 684         struct list_head list;
 685         struct sk_buff *skb;
 686         u64 dma;
 687         u16 ref_handle;
 688         u16 state;
 689 };
 690
 691 /* Board types */
 692 #define NETXEN_NIC_GBE  0x01
 693 #define NETXEN_NIC_XGBE 0x02
 694
 695 /*
 696  * One hardware_context{} per adapter
 697  * contains interrupt info as well shared hardware info.
 698  */
 699 struct netxen_hardware_context {
 700         void __iomem *pci_base0;
 701         void __iomem *pci_base1;
 702         void __iomem *pci_base2;
 703         void __iomem *db_base;
 704         unsigned long db_len;
 705         unsigned long pci_len0;
 706
 707         int qdr_sn_window;
 708         int ddr_mn_window;
 709         unsigned long mn_win_crb;
 710         unsigned long ms_win_crb;
 711
 712         u8 cut_through;
 713         u8 revision_id;
 714         u8 pci_func;
 715         u8 linkup;
 716         u16 port_type;
 717         u16 board_type;
 718 };
 719
 720 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 721 #define ETHERNET_FCS_SIZE               4
 722
 723 struct netxen_adapter_stats {
 724         u64  xmitcalled;
 725         u64  xmitfinished;
 726         u64  rxdropped;
 727         u64  txdropped;
 728         u64  csummed;
 729         u64  no_rcv;
 730         u64  rxbytes;
 731         u64  txbytes;
 732 };
 733
 734 /*
 735  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 736  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 737  */
 738 struct nx_host_rds_ring {
 739         u32 producer;
 740         u32 crb_rcv_producer;
 741         u32 num_desc;
 742         u32 dma_size;
 743         u32 skb_size;
 744         u32 flags;
 745         struct rcv_desc *desc_head;
 746         struct netxen_rx_buffer *rx_buf_arr;
 747         struct list_head free_list;
 748         spinlock_t lock;
 749         dma_addr_t phys_addr;
 750 };
 751
 752 struct nx_host_sds_ring {
 753         u32 consumer;
 754         u32 crb_sts_consumer;
 755         u32 crb_intr_mask;
 756         u32 num_desc;
 757
 758         struct status_desc *desc_head;
 759         struct netxen_adapter *adapter;
 760         struct napi_struct napi;
 761         struct list_head free_list[NUM_RCV_DESC_RINGS];
 762
 763         int irq;
 764
 765         dma_addr_t phys_addr;
 766         char name[IFNAMSIZ+4];
 767 };
 768
 769 struct nx_host_tx_ring {
 770         u32 producer;
 771         __le32 *hw_consumer;
 772         u32 sw_consumer;
 773         u32 crb_cmd_producer;
 774         u32 crb_cmd_consumer;
 775         u32 num_desc;
 776
 777         struct netxen_cmd_buffer *cmd_buf_arr;
 778         struct cmd_desc_type0 *desc_head;
 779         dma_addr_t phys_addr;
 780 };
 781
 782 /*
 783  * Receive context. There is one such structure per instance of the
 784  * receive processing. Any state information that is relevant to
 785  * the receive, and is must be in this structure. The global data may be
 786  * present elsewhere.
 787  */
 788 struct netxen_recv_context {
 789         u32 state;
 790         u16 context_id;
 791         u16 virt_port;
 792
 793         struct nx_host_rds_ring *rds_rings;
 794         struct nx_host_sds_ring *sds_rings;
 795
 796         struct netxen_ring_ctx *hwctx;
 797         dma_addr_t phys_addr;
 798 };
 799
 800 /* New HW context creation */
 801
 802 #define NX_OS_CRB_RETRY_COUNT   4000
 803 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 804         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 805
 806 #define NX_CDRP_CLEAR           0x00000000
 807 #define NX_CDRP_CMD_BIT         0x80000000
 808
 809 /*
 810  * All responses must have the NX_CDRP_CMD_BIT cleared
 811  * in the crb NX_CDRP_CRB_OFFSET.
 812  */
 813 #define NX_CDRP_FORM_RSP(rsp)   (rsp)
 814 #define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 815
 816 #define NX_CDRP_RSP_OK          0x00000001
 817 #define NX_CDRP_RSP_FAIL        0x00000002
 818 #define NX_CDRP_RSP_TIMEOUT     0x00000003
 819
 820 /*
 821  * All commands must have the NX_CDRP_CMD_BIT set in
 822  * the crb NX_CDRP_CRB_OFFSET.
 823  */
 824 #define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 825 #define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 826
 827 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 828 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 829 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 830 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 831 #define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 832 #define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 833 #define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 834 #define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 835 #define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 836 #define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 837 #define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 838 #define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 839 #define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 840 #define NX_CDRP_CMD_SET_MTU                 0x00000012
 841 #define NX_CDRP_CMD_MAX                     0x00000013
 842
 843 #define NX_RCODE_SUCCESS                0
 844 #define NX_RCODE_NO_HOST_MEM            1
 845 #define NX_RCODE_NO_HOST_RESOURCE       2
 846 #define NX_RCODE_NO_CARD_CRB            3
 847 #define NX_RCODE_NO_CARD_MEM            4
 848 #define NX_RCODE_NO_CARD_RESOURCE       5
 849 #define NX_RCODE_INVALID_ARGS           6
 850 #define NX_RCODE_INVALID_ACTION         7
 851 #define NX_RCODE_INVALID_STATE          8
 852 #define NX_RCODE_NOT_SUPPORTED          9
 853 #define NX_RCODE_NOT_PERMITTED          10
 854 #define NX_RCODE_NOT_READY              11
 855 #define NX_RCODE_DOES_NOT_EXIST         12
 856 #define NX_RCODE_ALREADY_EXISTS         13
 857 #define NX_RCODE_BAD_SIGNATURE          14
 858 #define NX_RCODE_CMD_NOT_IMPL           15
 859 #define NX_RCODE_CMD_INVALID            16
 860 #define NX_RCODE_TIMEOUT                17
 861 #define NX_RCODE_CMD_FAILED             18
 862 #define NX_RCODE_MAX_EXCEEDED           19
 863 #define NX_RCODE_MAX                    20
 864
 865 #define NX_DESTROY_CTX_RESET            0
 866 #define NX_DESTROY_CTX_D3_RESET         1
 867 #define NX_DESTROY_CTX_MAX              2
 868
 869 /*
 870  * Capabilities
 871  */
 872 #define NX_CAP_BIT(class, bit)          (1 << bit)
 873 #define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 874 #define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 875 #define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 876 #define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 877 #define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 878 #define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 879 #define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 880 #define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 881 #define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 882
 883 /*
 884  * Context state
 885  */
 886 #define NX_HOST_CTX_STATE_FREED         0
 887 #define NX_HOST_CTX_STATE_ALLOCATED     1
 888 #define NX_HOST_CTX_STATE_ACTIVE        2
 889 #define NX_HOST_CTX_STATE_DISABLED      3
 890 #define NX_HOST_CTX_STATE_QUIESCED      4
 891 #define NX_HOST_CTX_STATE_MAX           5
 892
 893 /*
 894  * Rx context
 895  */
 896
 897 typedef struct {
 898         __le64 host_phys_addr;  /* Ring base addr */
 899         __le32 ring_size;               /* Ring entries */
 900         __le16 msi_index;
 901         __le16 rsvd;            /* Padding */
 902 } nx_hostrq_sds_ring_t;
 903
 904 typedef struct {
 905         __le64 host_phys_addr;  /* Ring base addr */
 906         __le64 buff_size;               /* Packet buffer size */
 907         __le32 ring_size;               /* Ring entries */
 908         __le32 ring_kind;               /* Class of ring */
 909 } nx_hostrq_rds_ring_t;
 910
 911 typedef struct {
 912         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 913         __le32 capabilities[4]; /* Flag bit vector */
 914         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 915         __le32 host_rds_crb_mode;       /* RDS crb usage */
 916         /* These ring offsets are relative to data[0] below */
 917         __le32 rds_ring_offset; /* Offset to RDS config */
 918         __le32 sds_ring_offset; /* Offset to SDS config */
 919         __le16 num_rds_rings;   /* Count of RDS rings */
 920         __le16 num_sds_rings;   /* Count of SDS rings */
 921         __le16 rsvd1;           /* Padding */
 922         __le16 rsvd2;           /* Padding */
 923         u8  reserved[128];      /* reserve space for future expansion*/
 924         /* MUST BE 64-bit aligned.
 925            The following is packed:
 926            - N hostrq_rds_rings
 927            - N hostrq_sds_rings */
 928         char data[0];
 929 } nx_hostrq_rx_ctx_t;
 930
 931 typedef struct {
 932         __le32 host_producer_crb;       /* Crb to use */
 933         __le32 rsvd1;           /* Padding */
 934 } nx_cardrsp_rds_ring_t;
 935
 936 typedef struct {
 937         __le32 host_consumer_crb;       /* Crb to use */
 938         __le32 interrupt_crb;   /* Crb to use */
 939 } nx_cardrsp_sds_ring_t;
 940
 941 typedef struct {
 942         /* These ring offsets are relative to data[0] below */
 943         __le32 rds_ring_offset; /* Offset to RDS config */
 944         __le32 sds_ring_offset; /* Offset to SDS config */
 945         __le32 host_ctx_state;  /* Starting State */
 946         __le32 num_fn_per_port; /* How many PCI fn share the port */
 947         __le16 num_rds_rings;   /* Count of RDS rings */
 948         __le16 num_sds_rings;   /* Count of SDS rings */
 949         __le16 context_id;              /* Handle for context */
 950         u8  phys_port;          /* Physical id of port */
 951         u8  virt_port;          /* Virtual/Logical id of port */
 952         u8  reserved[128];      /* save space for future expansion */
 953         /*  MUST BE 64-bit aligned.
 954            The following is packed:
 955            - N cardrsp_rds_rings
 956            - N cardrs_sds_rings */
 957         char data[0];
 958 } nx_cardrsp_rx_ctx_t;
 959
 960 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 961         (sizeof(HOSTRQ_RX) +                                    \
 962         (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
 963         (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
 964
 965 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 966         (sizeof(CARDRSP_RX) +                                   \
 967         (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
 968         (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
 969
 970 /*
 971  * Tx context
 972  */
 973
 974 typedef struct {
 975         __le64 host_phys_addr;  /* Ring base addr */
 976         __le32 ring_size;               /* Ring entries */
 977         __le32 rsvd;            /* Padding */
 978 } nx_hostrq_cds_ring_t;
 979
 980 typedef struct {
 981         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 982         __le64 cmd_cons_dma_addr;       /*  */
 983         __le64 dummy_dma_addr;  /*  */
 984         __le32 capabilities[4]; /* Flag bit vector */
 985         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 986         __le32 rsvd1;           /* Padding */
 987         __le16 rsvd2;           /* Padding */
 988         __le16 interrupt_ctl;
 989         __le16 msi_index;
 990         __le16 rsvd3;           /* Padding */
 991         nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
 992         u8  reserved[128];      /* future expansion */
 993 } nx_hostrq_tx_ctx_t;
 994
 995 typedef struct {
 996         __le32 host_producer_crb;       /* Crb to use */
 997         __le32 interrupt_crb;   /* Crb to use */
 998 } nx_cardrsp_cds_ring_t;
 999
1000 typedef struct {
1001         __le32 host_ctx_state;  /* Starting state */
1002         __le16 context_id;              /* Handle for context */
1003         u8  phys_port;          /* Physical id of port */
1004         u8  virt_port;          /* Virtual/Logical id of port */
1005         nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1006         u8  reserved[128];      /* future expansion */
1007 } nx_cardrsp_tx_ctx_t;
1008
1009 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
1010 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
1011
1012 /* CRB */
1013
1014 #define NX_HOST_RDS_CRB_MODE_UNIQUE     0
1015 #define NX_HOST_RDS_CRB_MODE_SHARED     1
1016 #define NX_HOST_RDS_CRB_MODE_CUSTOM     2
1017 #define NX_HOST_RDS_CRB_MODE_MAX        3
1018
1019 #define NX_HOST_INT_CRB_MODE_UNIQUE     0
1020 #define NX_HOST_INT_CRB_MODE_SHARED     1
1021 #define NX_HOST_INT_CRB_MODE_NORX       2
1022 #define NX_HOST_INT_CRB_MODE_NOTX       3
1023 #define NX_HOST_INT_CRB_MODE_NORXTX     4
1024
1025
1026 /* MAC */
1027
1028 #define MC_COUNT_P2     16
1029 #define MC_COUNT_P3     38
1030
1031 #define NETXEN_MAC_NOOP 0
1032 #define NETXEN_MAC_ADD  1
1033 #define NETXEN_MAC_DEL  2
1034
1035 typedef struct nx_mac_list_s {
1036         struct list_head list;
1037         uint8_t mac_addr[ETH_ALEN+2];
1038 } nx_mac_list_t;
1039
1040 /*
1041  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1042  * adjusted based on configured MTU.
1043  */
1044 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1045 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1046 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1047 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1048
1049 #define NETXEN_NIC_INTR_DEFAULT                 0x04
1050
1051 typedef union {
1052         struct {
1053                 uint16_t        rx_packets;
1054                 uint16_t        rx_time_us;
1055                 uint16_t        tx_packets;
1056                 uint16_t        tx_time_us;
1057         } data;
1058         uint64_t                word;
1059 } nx_nic_intr_coalesce_data_t;
1060
1061 typedef struct {
1062         uint16_t                        stats_time_us;
1063         uint16_t                        rate_sample_time;
1064         uint16_t                        flags;
1065         uint16_t                        rsvd_1;
1066         uint32_t                        low_threshold;
1067         uint32_t                        high_threshold;
1068         nx_nic_intr_coalesce_data_t     normal;
1069         nx_nic_intr_coalesce_data_t     low;
1070         nx_nic_intr_coalesce_data_t     high;
1071         nx_nic_intr_coalesce_data_t     irq;
1072 } nx_nic_intr_coalesce_t;
1073
1074 #define NX_HOST_REQUEST         0x13
1075 #define NX_NIC_REQUEST          0x14
1076
1077 #define NX_MAC_EVENT            0x1
1078
1079 /*
1080  * Driver --> Firmware
1081  */
1082 #define NX_NIC_H2C_OPCODE_START                         0
1083 #define NX_NIC_H2C_OPCODE_CONFIG_RSS                    1
1084 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL                2
1085 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE          3
1086 #define NX_NIC_H2C_OPCODE_CONFIG_LED                    4
1087 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS            5
1088 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC                 6
1089 #define NX_NIC_H2C_OPCODE_LRO_REQUEST                   7
1090 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS                8
1091 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST           9
1092 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST            10
1093 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU                 11
1094 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE     12
1095 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST      13
1096 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST       14
1097 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST        15
1098 #define NX_NIC_H2C_OPCODE_GET_NET_STATS                 16
1099 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
1100 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR                 18
1101 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK               19
1102 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE               20
1103 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT                 21
1104 #define NX_NIC_C2C_OPCODE                               22
1105 #define NX_NIC_H2C_OPCODE_LAST                          23
1106
1107 /*
1108  * Firmware --> Driver
1109  */
1110
1111 #define NX_NIC_C2H_OPCODE_START                         128
1112 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE           129
1113 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE       130
1114 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE           131
1115 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE   132
1116 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE        133
1117 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE           134
1118 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE      135
1119 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS                136
1120 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY        137
1121 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY         138
1122 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1123 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE        140
1124 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
1125 #define NX_NIC_C2H_OPCODE_LAST                          142
1126
1127 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1128 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1129 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1130
1131 #define NX_FW_CAPABILITY_LINK_NOTIFICATION      (1 << 5)
1132 #define NX_FW_CAPABILITY_SWITCHING              (1 << 6)
1133
1134 /* module types */
1135 #define LINKEVENT_MODULE_NOT_PRESENT                    1
1136 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
1137 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
1138 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
1139 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
1140 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
1141 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
1142 #define LINKEVENT_MODULE_TWINAX                         8
1143
1144 #define LINKSPEED_10GBPS        10000
1145 #define LINKSPEED_1GBPS         1000
1146 #define LINKSPEED_100MBPS       100
1147 #define LINKSPEED_10MBPS        10
1148
1149 #define LINKSPEED_ENCODED_10MBPS        0
1150 #define LINKSPEED_ENCODED_100MBPS       1
1151 #define LINKSPEED_ENCODED_1GBPS         2
1152
1153 #define LINKEVENT_AUTONEG_DISABLED      0
1154 #define LINKEVENT_AUTONEG_ENABLED       1
1155
1156 #define LINKEVENT_HALF_DUPLEX           0
1157 #define LINKEVENT_FULL_DUPLEX           1
1158
1159 #define LINKEVENT_LINKSPEED_MBPS        0
1160 #define LINKEVENT_LINKSPEED_ENCODED     1
1161
1162 /* firmware response header:
1163  *      63:58 - message type
1164  *      57:56 - owner
1165  *      55:53 - desc count
1166  *      52:48 - reserved
1167  *      47:40 - completion id
1168  *      39:32 - opcode
1169  *      31:16 - error code
1170  *      15:00 - reserved
1171  */
1172 #define netxen_get_nic_msgtype(msg_hdr) \
1173         ((msg_hdr >> 58) & 0x3F)
1174 #define netxen_get_nic_msg_compid(msg_hdr)      \
1175         ((msg_hdr >> 40) & 0xFF)
1176 #define netxen_get_nic_msg_opcode(msg_hdr)      \
1177         ((msg_hdr >> 32) & 0xFF)
1178 #define netxen_get_nic_msg_errcode(msg_hdr)     \
1179         ((msg_hdr >> 16) & 0xFFFF)
1180
1181 typedef struct {
1182         union {
1183                 struct {
1184                         u64 hdr;
1185                         u64 body[7];
1186                 };
1187                 u64 words[8];
1188         };
1189 } nx_fw_msg_t;
1190
1191 typedef struct {
1192         __le64 qhdr;
1193         __le64 req_hdr;
1194         __le64 words[6];
1195 } nx_nic_req_t;
1196
1197 typedef struct {
1198         u8 op;
1199         u8 tag;
1200         u8 mac_addr[6];
1201 } nx_mac_req_t;
1202
1203 #define MAX_PENDING_DESC_BLOCK_SIZE     64
1204
1205 #define NETXEN_NIC_MSI_ENABLED          0x02
1206 #define NETXEN_NIC_MSIX_ENABLED         0x04
1207 #define NETXEN_IS_MSI_FAMILY(adapter) \
1208         ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1209
1210 #define MSIX_ENTRIES_PER_ADAPTER        NUM_STS_DESC_RINGS
1211 #define NETXEN_MSIX_TBL_SPACE           8192
1212 #define NETXEN_PCI_REG_MSIX_TBL         0x44
1213
1214 #define NETXEN_DB_MAPSIZE_BYTES         0x1000
1215
1216 #define NETXEN_NETDEV_WEIGHT 128
1217 #define NETXEN_ADAPTER_UP_MAGIC 777
1218 #define NETXEN_NIC_PEG_TUNE 0
1219
1220 struct netxen_dummy_dma {
1221         void *addr;
1222         dma_addr_t phys_addr;
1223 };
1224
1225 struct netxen_adapter {
1226         struct netxen_hardware_context ahw;
1227
1228         struct net_device *netdev;
1229         struct pci_dev *pdev;
1230         struct list_head mac_list;
1231
1232         u32 curr_window;
1233         u32 crb_win;
1234         rwlock_t adapter_lock;
1235
1236         spinlock_t tx_clean_lock;
1237
1238         u16 num_txd;
1239         u16 num_rxd;
1240         u16 num_jumbo_rxd;
1241         u16 num_lro_rxd;
1242
1243         u8 max_rds_rings;
1244         u8 max_sds_rings;
1245         u8 driver_mismatch;
1246         u8 msix_supported;
1247         u8 rx_csum;
1248         u8 pci_using_dac;
1249         u8 portnum;
1250         u8 physical_port;
1251
1252         u8 mc_enabled;
1253         u8 max_mc_count;
1254         u8 rss_supported;
1255         u8 resv2;
1256         u32 resv3;
1257
1258         u8 has_link_events;
1259         u8 fw_type;
1260         u16 tx_context_id;
1261         u16 mtu;
1262         u16 is_up;
1263
1264         u16 link_speed;
1265         u16 link_duplex;
1266         u16 link_autoneg;
1267         u16 module_type;
1268
1269         u32 capabilities;
1270         u32 flags;
1271         u32 irq;
1272         u32 temp;
1273
1274         u32 msi_tgt_status;
1275         u32 resv4;
1276
1277         struct netxen_adapter_stats stats;
1278
1279         struct netxen_recv_context recv_ctx;
1280         struct nx_host_tx_ring *tx_ring;
1281
1282         int (*enable_phy_interrupts) (struct netxen_adapter *);
1283         int (*disable_phy_interrupts) (struct netxen_adapter *);
1284         int (*macaddr_set) (struct netxen_adapter *, u8 *);
1285         int (*set_mtu) (struct netxen_adapter *, int);
1286         int (*set_promisc) (struct netxen_adapter *, u32);
1287         void (*set_multi) (struct net_device *);
1288         int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1289         int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1290         int (*init_port) (struct netxen_adapter *, int);
1291         int (*stop_port) (struct netxen_adapter *);
1292
1293         u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1294         int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1295         int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1296         int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1297         int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1298         u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1299         unsigned long (*pci_set_window)(struct netxen_adapter *,
1300                         unsigned long long);
1301
1302         struct netxen_legacy_intr_set legacy_intr;
1303
1304         struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1305
1306         struct netxen_dummy_dma dummy_dma;
1307
1308         struct work_struct watchdog_task;
1309         struct timer_list watchdog_timer;
1310         struct work_struct  tx_timeout_task;
1311
1312         struct net_device_stats net_stats;
1313
1314         nx_nic_intr_coalesce_t coal;
1315
1316         u32 fw_major;
1317         u32 fw_version;
1318         const struct firmware *fw;
1319 };
1320
1321 /*
1322  * NetXen dma watchdog control structure
1323  *
1324  *      Bit 0           : enabled => R/O: 1 watchdog active, 0 inactive
1325  *      Bit 1           : disable_request => 1 req disable dma watchdog
1326  *      Bit 2           : enable_request =>  1 req enable dma watchdog
1327  *      Bit 3-31        : unused
1328  */
1329
1330 #define netxen_set_dma_watchdog_disable_req(config_word) \
1331         _netxen_set_bits(config_word, 1, 1, 1)
1332 #define netxen_set_dma_watchdog_enable_req(config_word) \
1333         _netxen_set_bits(config_word, 2, 1, 1)
1334 #define netxen_get_dma_watchdog_enabled(config_word) \
1335         ((config_word) & 0x1)
1336 #define netxen_get_dma_watchdog_disabled(config_word) \
1337         (((config_word) >> 1) & 0x1)
1338
1339 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1340 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1341 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1342 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1343 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1344                             __u32 * readval);
1345 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1346                              long reg, __u32 val);
1347
1348 /* Functions available from netxen_nic_hw.c */
1349 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1350 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1351
1352 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1353 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1354
1355 #define NXRD32(adapter, off) \
1356         (adapter->hw_read_wx(adapter, off))
1357 #define NXWR32(adapter, off, val) \
1358         (adapter->hw_write_wx(adapter, off, val))
1359
1360 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1361 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1362 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1363
1364 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1365 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1366                 ulong off, u32 data);
1367 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1368                 u64 off, void *data, int size);
1369 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1370                 u64 off, void *data, int size);
1371 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1372                 u64 off, u32 data);
1373 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1374 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1375                 u64 off, u32 data);
1376 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1377 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1378                 unsigned long long addr);
1379 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1380                 u32 wndw);
1381
1382 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1383 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1384                 ulong off, u32 data);
1385 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1386                 u64 off, void *data, int size);
1387 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1388                 u64 off, void *data, int size);
1389 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1390                 u64 off, u32 data);
1391 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1392 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1393                 u64 off, u32 data);
1394 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1395 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1396                 unsigned long long addr);
1397
1398 /* Functions from netxen_nic_init.c */
1399 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1400 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1401 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1402 int netxen_load_firmware(struct netxen_adapter *adapter);
1403 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1404 void netxen_request_firmware(struct netxen_adapter *adapter);
1405 void netxen_release_firmware(struct netxen_adapter *adapter);
1406 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1407
1408 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1409 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1410                                 u8 *bytes, size_t size);
1411 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1412                                 u8 *bytes, size_t size);
1413 int netxen_flash_unlock(struct netxen_adapter *adapter);
1414 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1415 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1416 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1417 void netxen_halt_pegs(struct netxen_adapter *adapter);
1418
1419 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1420
1421 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1422 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1423
1424 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1425 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1426
1427 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1428 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1429
1430 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1431 int netxen_init_firmware(struct netxen_adapter *adapter);
1432 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1433 void netxen_watchdog_task(struct work_struct *work);
1434 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1435                 struct nx_host_rds_ring *rds_ring);
1436 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1437 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1438 void netxen_p2_nic_set_multi(struct net_device *netdev);
1439 void netxen_p3_nic_set_multi(struct net_device *netdev);
1440 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1441 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1442 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1443 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1444 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1445 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1446
1447 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1448 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1449
1450 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1451 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1452
1453 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1454                 struct nx_host_tx_ring *tx_ring);
1455
1456 /*
1457  * NetXen Board information
1458  */
1459
1460 #define NETXEN_MAX_SHORT_NAME 32
1461 struct netxen_brdinfo {
1462         int brdtype;    /* type of board */
1463         long ports;             /* max no of physical ports */
1464         char short_name[NETXEN_MAX_SHORT_NAME];
1465 };
1466
1467 static const struct netxen_brdinfo netxen_boards[] = {
1468         {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1469         {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1470         {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1471         {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1472         {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1473         {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1474         {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1475         {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1476         {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1477         {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1478         {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1479         {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1480         {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1481         {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1482         {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1483         {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1484         {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1485         {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1486         {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1487 };
1488
1489 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1490
1491 static inline void get_brd_name_by_type(u32 type, char *name)
1492 {
1493         int i, found = 0;
1494         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1495                 if (netxen_boards[i].brdtype == type) {
1496                         strcpy(name, netxen_boards[i].short_name);
1497                         found = 1;
1498                         break;
1499                 }
1500
1501         }
1502         if (!found)
1503                 name = "Unknown";
1504 }
1505
1506 static inline int
1507 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1508 {
1509         u32 ctrl;
1510
1511         /* check if already inactive */
1512         ctrl = adapter->hw_read_wx(adapter,
1513                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1514
1515         if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1516                 return 1;
1517
1518         /* Send the disable request */
1519         netxen_set_dma_watchdog_disable_req(ctrl);
1520         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1521
1522         return 0;
1523 }
1524
1525 static inline int
1526 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1527 {
1528         u32 ctrl;
1529
1530         ctrl = adapter->hw_read_wx(adapter,
1531                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1532
1533         return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1534 }
1535
1536 static inline int
1537 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1538 {
1539         u32 ctrl;
1540
1541         ctrl = adapter->hw_read_wx(adapter,
1542                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1543
1544         if (netxen_get_dma_watchdog_enabled(ctrl))
1545                 return 1;
1546
1547         /* send the wakeup request */
1548         netxen_set_dma_watchdog_enable_req(ctrl);
1549
1550         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1551
1552         return 0;
1553 }
1554
1555
1556 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1557 {
1558         smp_mb();
1559         return find_diff_among(tx_ring->producer,
1560                         tx_ring->sw_consumer, tx_ring->num_desc);
1561
1562 }
1563
1564 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1565 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1566 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1567 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1568                                 int *valp);
1569
1570 extern struct ethtool_ops netxen_nic_ethtool_ops;
1571
1572 #endif                          /* __NETXEN_NIC_H_ */