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hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / netxen / netxen_nic.h
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #ifndef _NETXEN_NIC_H_
32 #define _NETXEN_NIC_H_
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/compiler.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
42 #include <linux/pci.h>
43 #include <linux/netdevice.h>
44 #include <linux/etherdevice.h>
45 #include <linux/ip.h>
46 #include <linux/in.h>
47 #include <linux/tcp.h>
48 #include <linux/skbuff.h>
49
50 #include <linux/ethtool.h>
51 #include <linux/mii.h>
52 #include <linux/interrupt.h>
53 #include <linux/timer.h>
54
55 #include <linux/mm.h>
56 #include <linux/mman.h>
57 #include <linux/vmalloc.h>
58
59 #include <asm/system.h>
60 #include <asm/io.h>
61 #include <asm/byteorder.h>
62 #include <asm/uaccess.h>
63 #include <asm/pgtable.h>
64
65 #include "netxen_nic_hw.h"
66
67 #define _NETXEN_NIC_LINUX_MAJOR 4
68 #define _NETXEN_NIC_LINUX_MINOR 0
69 #define _NETXEN_NIC_LINUX_SUBVERSION 30
70 #define NETXEN_NIC_LINUX_VERSIONID "4.0.30"
71
72 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 16) + ((b) << 8) + (c))
73
74 #define NETXEN_NUM_FLASH_SECTORS (64)
75 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
76 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \
77 * NETXEN_FLASH_SECTOR_SIZE)
78
79 #define PHAN_VENDOR_ID 0x4040
80
81 #define RCV_DESC_RINGSIZE(rds_ring) \
82 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
83 #define RCV_BUFF_RINGSIZE(rds_ring) \
84 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
85 #define STATUS_DESC_RINGSIZE(sds_ring) \
86 (sizeof(struct status_desc) * (sds_ring)->num_desc)
87 #define TX_BUFF_RINGSIZE(adapter) \
88 (sizeof(struct netxen_cmd_buffer) * adapter->num_txd)
89 #define TX_DESC_RINGSIZE(adapter) \
90 (sizeof(struct cmd_desc_type0) * adapter->num_txd)
91
92 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
93
94 #define NETXEN_RCV_PRODUCER_OFFSET 0
95 #define NETXEN_RCV_PEG_DB_ID 2
96 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
97 #define FLASH_SUCCESS 0
98
99 #define ADDR_IN_WINDOW1(off) \
100 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
101
102 /*
103 * normalize a 64MB crb address to 32MB PCI window
104 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
105 */
106 #define NETXEN_CRB_NORMAL(reg) \
107 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
108
109 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
110 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
111
112 #define DB_NORMALIZE(adapter, off) \
113 (adapter->ahw.db_base + (off))
114
115 #define NX_P2_C0 0x24
116 #define NX_P2_C1 0x25
117 #define NX_P3_A0 0x30
118 #define NX_P3_A2 0x30
119 #define NX_P3_B0 0x40
120 #define NX_P3_B1 0x41
121
122 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1)
123 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0)
124
125 #define FIRST_PAGE_GROUP_START 0
126 #define FIRST_PAGE_GROUP_END 0x100000
127
128 #define SECOND_PAGE_GROUP_START 0x6000000
129 #define SECOND_PAGE_GROUP_END 0x68BC000
130
131 #define THIRD_PAGE_GROUP_START 0x70E4000
132 #define THIRD_PAGE_GROUP_END 0x8000000
133
134 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
135 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
136 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
137
138 #define P2_MAX_MTU (8000)
139 #define P3_MAX_MTU (9600)
140 #define NX_ETHERMTU 1500
141 #define NX_MAX_ETHERHDR 32 /* This contains some padding */
142
143 #define NX_RX_NORMAL_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU)
144 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU)
145 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU)
146 #define NX_CT_DEFAULT_RX_BUF_LEN 2048
147
148 #define MAX_RX_BUFFER_LENGTH 1760
149 #define MAX_RX_JUMBO_BUFFER_LENGTH 8062
150 #define MAX_RX_LRO_BUFFER_LENGTH (8062)
151 #define RX_DMA_MAP_LEN (MAX_RX_BUFFER_LENGTH - 2)
152 #define RX_JUMBO_DMA_MAP_LEN \
153 (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
154 #define RX_LRO_DMA_MAP_LEN (MAX_RX_LRO_BUFFER_LENGTH - 2)
155
156 /*
157 * Maximum number of ring contexts
158 */
159 #define MAX_RING_CTX 1
160
161 /* Opcodes to be used with the commands */
162 #define TX_ETHER_PKT 0x01
163 #define TX_TCP_PKT 0x02
164 #define TX_UDP_PKT 0x03
165 #define TX_IP_PKT 0x04
166 #define TX_TCP_LSO 0x05
167 #define TX_TCP_LSO6 0x06
168 #define TX_IPSEC 0x07
169 #define TX_IPSEC_CMD 0x0a
170 #define TX_TCPV6_PKT 0x0b
171 #define TX_UDPV6_PKT 0x0c
172
173 /* The following opcodes are for internal consumption. */
174 #define NETXEN_CONTROL_OP 0x10
175 #define PEGNET_REQUEST 0x11
176
177 #define MAX_NUM_CARDS 4
178
179 #define MAX_BUFFERS_PER_CMD 32
180
181 /*
182 * Following are the states of the Phantom. Phantom will set them and
183 * Host will read to check if the fields are correct.
184 */
185 #define PHAN_INITIALIZE_START 0xff00
186 #define PHAN_INITIALIZE_FAILED 0xffff
187 #define PHAN_INITIALIZE_COMPLETE 0xff01
188
189 /* Host writes the following to notify that it has done the init-handshake */
190 #define PHAN_INITIALIZE_ACK 0xf00f
191
192 #define NUM_RCV_DESC_RINGS 3
193 #define NUM_STS_DESC_RINGS 4
194
195 #define RCV_RING_NORMAL 0
196 #define RCV_RING_JUMBO 1
197 #define RCV_RING_LRO 2
198
199 #define MAX_CMD_DESCRIPTORS 4096
200 #define MAX_RCV_DESCRIPTORS 16384
201 #define MAX_CMD_DESCRIPTORS_HOST 1024
202 #define MAX_RCV_DESCRIPTORS_1G 2048
203 #define MAX_RCV_DESCRIPTORS_10G 4096
204 #define MAX_JUMBO_RCV_DESCRIPTORS 1024
205 #define MAX_LRO_RCV_DESCRIPTORS 8
206 #define MAX_RCVSTATUS_DESCRIPTORS MAX_RCV_DESCRIPTORS
207 #define MAX_JUMBO_RCV_DESC MAX_JUMBO_RCV_DESCRIPTORS
208 #define MAX_RCV_DESC MAX_RCV_DESCRIPTORS
209 #define MAX_RCVSTATUS_DESC MAX_RCV_DESCRIPTORS
210 #define MAX_EPG_DESCRIPTORS (MAX_CMD_DESCRIPTORS * 8)
211 #define NUM_RCV_DESC (MAX_RCV_DESC + MAX_JUMBO_RCV_DESCRIPTORS + \
212 MAX_LRO_RCV_DESCRIPTORS)
213 #define MIN_TX_COUNT 4096
214 #define MIN_RX_COUNT 4096
215 #define NETXEN_CTX_SIGNATURE 0xdee0
216 #define NETXEN_RCV_PRODUCER(ringid) (ringid)
217 #define MAX_FRAME_SIZE 0x10000 /* 64K MAX size for LSO */
218
219 #define PHAN_PEG_RCV_INITIALIZED 0xff01
220 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00
221
222 #define get_next_index(index, length) \
223 (((index) + 1) & ((length) - 1))
224
225 #define get_index_range(index,length,count) \
226 (((index) + (count)) & ((length) - 1))
227
228 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
229 #define MPORT_MULTI_FUNCTION_MODE 0x2222
230
231 #include "netxen_nic_phan_reg.h"
232
233 /*
234 * NetXen host-peg signal message structure
235 *
236 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx
237 * Bit 2 : priv_id => must be 1
238 * Bit 3-17 : count => for doorbell
239 * Bit 18-27 : ctx_id => Context id
240 * Bit 28-31 : opcode
241 */
242
243 typedef u32 netxen_ctx_msg;
244
245 #define netxen_set_msg_peg_id(config_word, val) \
246 ((config_word) &= ~3, (config_word) |= val & 3)
247 #define netxen_set_msg_privid(config_word) \
248 ((config_word) |= 1 << 2)
249 #define netxen_set_msg_count(config_word, val) \
250 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
251 #define netxen_set_msg_ctxid(config_word, val) \
252 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
253 #define netxen_set_msg_opcode(config_word, val) \
254 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
255
256 struct netxen_rcv_context {
257 __le64 rcv_ring_addr;
258 __le32 rcv_ring_size;
259 __le32 rsrvd;
260 };
261
262 struct netxen_ring_ctx {
263
264 /* one command ring */
265 __le64 cmd_consumer_offset;
266 __le64 cmd_ring_addr;
267 __le32 cmd_ring_size;
268 __le32 rsrvd;
269
270 /* three receive rings */
271 struct netxen_rcv_context rcv_ctx[3];
272
273 /* one status ring */
274 __le64 sts_ring_addr;
275 __le32 sts_ring_size;
276
277 __le32 ctx_id;
278 } __attribute__ ((aligned(64)));
279
280 /*
281 * Following data structures describe the descriptors that will be used.
282 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
283 * we are doing LSO (above the 1500 size packet) only.
284 */
285
286 /*
287 * The size of reference handle been changed to 16 bits to pass the MSS fields
288 * for the LSO packet
289 */
290
291 #define FLAGS_CHECKSUM_ENABLED 0x01
292 #define FLAGS_LSO_ENABLED 0x02
293 #define FLAGS_IPSEC_SA_ADD 0x04
294 #define FLAGS_IPSEC_SA_DELETE 0x08
295 #define FLAGS_VLAN_TAGGED 0x10
296
297 #define netxen_set_cmd_desc_port(cmd_desc, var) \
298 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
299 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \
300 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
301
302 #define netxen_set_tx_port(_desc, _port) \
303 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
304
305 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
306 (_desc)->flags_opcode = \
307 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
308
309 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
310 (_desc)->num_of_buffers_total_length = \
311 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
312
313 struct cmd_desc_type0 {
314 u8 tcp_hdr_offset; /* For LSO only */
315 u8 ip_hdr_offset; /* For LSO only */
316 /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
317 __le16 flags_opcode;
318 /* Bit pattern: 0-7 total number of segments,
319 8-31 Total size of the packet */
320 __le32 num_of_buffers_total_length;
321 union {
322 struct {
323 __le32 addr_low_part2;
324 __le32 addr_high_part2;
325 };
326 __le64 addr_buffer2;
327 };
328
329 __le16 reference_handle; /* changed to u16 to add mss */
330 __le16 mss; /* passed by NDIS_PACKET for LSO */
331 /* Bit pattern 0-3 port, 0-3 ctx id */
332 u8 port_ctxid;
333 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
334 __le16 conn_id; /* IPSec offoad only */
335
336 union {
337 struct {
338 __le32 addr_low_part3;
339 __le32 addr_high_part3;
340 };
341 __le64 addr_buffer3;
342 };
343 union {
344 struct {
345 __le32 addr_low_part1;
346 __le32 addr_high_part1;
347 };
348 __le64 addr_buffer1;
349 };
350
351 __le16 buffer_length[4];
352
353 union {
354 struct {
355 __le32 addr_low_part4;
356 __le32 addr_high_part4;
357 };
358 __le64 addr_buffer4;
359 };
360
361 __le64 unused;
362
363 } __attribute__ ((aligned(64)));
364
365 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
366 struct rcv_desc {
367 __le16 reference_handle;
368 __le16 reserved;
369 __le32 buffer_length; /* allocated buffer length (usually 2K) */
370 __le64 addr_buffer;
371 };
372
373 /* opcode field in status_desc */
374 #define NETXEN_NIC_RXPKT_DESC 0x04
375 #define NETXEN_OLD_RXPKT_DESC 0x3f
376
377 /* for status field in status_desc */
378 #define STATUS_NEED_CKSUM (1)
379 #define STATUS_CKSUM_OK (2)
380
381 /* owner bits of status_desc */
382 #define STATUS_OWNER_HOST (0x1ULL << 56)
383 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
384
385 /* Note: sizeof(status_desc) should always be a mutliple of 2 */
386
387 #define netxen_get_sts_desc_lro_cnt(status_desc) \
388 ((status_desc)->lro & 0x7F)
389 #define netxen_get_sts_desc_lro_last_frag(status_desc) \
390 (((status_desc)->lro & 0x80) >> 7)
391
392 #define netxen_get_sts_port(sts_data) \
393 ((sts_data) & 0x0F)
394 #define netxen_get_sts_status(sts_data) \
395 (((sts_data) >> 4) & 0x0F)
396 #define netxen_get_sts_type(sts_data) \
397 (((sts_data) >> 8) & 0x0F)
398 #define netxen_get_sts_totallength(sts_data) \
399 (((sts_data) >> 12) & 0xFFFF)
400 #define netxen_get_sts_refhandle(sts_data) \
401 (((sts_data) >> 28) & 0xFFFF)
402 #define netxen_get_sts_prot(sts_data) \
403 (((sts_data) >> 44) & 0x0F)
404 #define netxen_get_sts_pkt_offset(sts_data) \
405 (((sts_data) >> 48) & 0x1F)
406 #define netxen_get_sts_opcode(sts_data) \
407 (((sts_data) >> 58) & 0x03F)
408
409 struct status_desc {
410 /* Bit pattern: 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
411 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
412 53-55 desc_cnt, 56-57 owner, 58-63 opcode
413 */
414 __le64 status_desc_data;
415 union {
416 struct {
417 __le32 hash_value;
418 u8 hash_type;
419 u8 msg_type;
420 u8 unused;
421 union {
422 /* Bit pattern: 0-6 lro_count indicates frag
423 * sequence, 7 last_frag indicates last frag
424 */
425 u8 lro;
426
427 /* chained buffers */
428 u8 nr_frags;
429 };
430 };
431 struct {
432 __le16 frag_handles[4];
433 };
434 };
435 } __attribute__ ((aligned(16)));
436
437 enum {
438 NETXEN_RCV_PEG_0 = 0,
439 NETXEN_RCV_PEG_1
440 };
441 /* The version of the main data structure */
442 #define NETXEN_BDINFO_VERSION 1
443
444 /* Magic number to let user know flash is programmed */
445 #define NETXEN_BDINFO_MAGIC 0x12345678
446
447 /* Max number of Gig ports on a Phantom board */
448 #define NETXEN_MAX_PORTS 4
449
450 typedef enum {
451 NETXEN_BRDTYPE_P1_BD = 0x0000,
452 NETXEN_BRDTYPE_P1_SB = 0x0001,
453 NETXEN_BRDTYPE_P1_SMAX = 0x0002,
454 NETXEN_BRDTYPE_P1_SOCK = 0x0003,
455
456 NETXEN_BRDTYPE_P2_SOCK_31 = 0x0008,
457 NETXEN_BRDTYPE_P2_SOCK_35 = 0x0009,
458 NETXEN_BRDTYPE_P2_SB35_4G = 0x000a,
459 NETXEN_BRDTYPE_P2_SB31_10G = 0x000b,
460 NETXEN_BRDTYPE_P2_SB31_2G = 0x000c,
461
462 NETXEN_BRDTYPE_P2_SB31_10G_IMEZ = 0x000d,
463 NETXEN_BRDTYPE_P2_SB31_10G_HMEZ = 0x000e,
464 NETXEN_BRDTYPE_P2_SB31_10G_CX4 = 0x000f,
465
466 NETXEN_BRDTYPE_P3_REF_QG = 0x0021,
467 NETXEN_BRDTYPE_P3_HMEZ = 0x0022,
468 NETXEN_BRDTYPE_P3_10G_CX4_LP = 0x0023,
469 NETXEN_BRDTYPE_P3_4_GB = 0x0024,
470 NETXEN_BRDTYPE_P3_IMEZ = 0x0025,
471 NETXEN_BRDTYPE_P3_10G_SFP_PLUS = 0x0026,
472 NETXEN_BRDTYPE_P3_10000_BASE_T = 0x0027,
473 NETXEN_BRDTYPE_P3_XG_LOM = 0x0028,
474 NETXEN_BRDTYPE_P3_4_GB_MM = 0x0029,
475 NETXEN_BRDTYPE_P3_10G_SFP_CT = 0x002a,
476 NETXEN_BRDTYPE_P3_10G_SFP_QT = 0x002b,
477 NETXEN_BRDTYPE_P3_10G_CX4 = 0x0031,
478 NETXEN_BRDTYPE_P3_10G_XFP = 0x0032,
479 NETXEN_BRDTYPE_P3_10G_TP = 0x0080
480
481 } netxen_brdtype_t;
482
483 typedef enum {
484 NETXEN_BRDMFG_INVENTEC = 1
485 } netxen_brdmfg;
486
487 typedef enum {
488 MEM_ORG_128Mbx4 = 0x0, /* DDR1 only */
489 MEM_ORG_128Mbx8 = 0x1, /* DDR1 only */
490 MEM_ORG_128Mbx16 = 0x2, /* DDR1 only */
491 MEM_ORG_256Mbx4 = 0x3,
492 MEM_ORG_256Mbx8 = 0x4,
493 MEM_ORG_256Mbx16 = 0x5,
494 MEM_ORG_512Mbx4 = 0x6,
495 MEM_ORG_512Mbx8 = 0x7,
496 MEM_ORG_512Mbx16 = 0x8,
497 MEM_ORG_1Gbx4 = 0x9,
498 MEM_ORG_1Gbx8 = 0xa,
499 MEM_ORG_1Gbx16 = 0xb,
500 MEM_ORG_2Gbx4 = 0xc,
501 MEM_ORG_2Gbx8 = 0xd,
502 MEM_ORG_2Gbx16 = 0xe,
503 MEM_ORG_128Mbx32 = 0x10002, /* GDDR only */
504 MEM_ORG_256Mbx32 = 0x10005 /* GDDR only */
505 } netxen_mn_mem_org_t;
506
507 typedef enum {
508 MEM_ORG_512Kx36 = 0x0,
509 MEM_ORG_1Mx36 = 0x1,
510 MEM_ORG_2Mx36 = 0x2
511 } netxen_sn_mem_org_t;
512
513 typedef enum {
514 MEM_DEPTH_4MB = 0x1,
515 MEM_DEPTH_8MB = 0x2,
516 MEM_DEPTH_16MB = 0x3,
517 MEM_DEPTH_32MB = 0x4,
518 MEM_DEPTH_64MB = 0x5,
519 MEM_DEPTH_128MB = 0x6,
520 MEM_DEPTH_256MB = 0x7,
521 MEM_DEPTH_512MB = 0x8,
522 MEM_DEPTH_1GB = 0x9,
523 MEM_DEPTH_2GB = 0xa,
524 MEM_DEPTH_4GB = 0xb,
525 MEM_DEPTH_8GB = 0xc,
526 MEM_DEPTH_16GB = 0xd,
527 MEM_DEPTH_32GB = 0xe
528 } netxen_mem_depth_t;
529
530 struct netxen_board_info {
531 u32 header_version;
532
533 u32 board_mfg;
534 u32 board_type;
535 u32 board_num;
536 u32 chip_id;
537 u32 chip_minor;
538 u32 chip_major;
539 u32 chip_pkg;
540 u32 chip_lot;
541
542 u32 port_mask; /* available niu ports */
543 u32 peg_mask; /* available pegs */
544 u32 icache_ok; /* can we run with icache? */
545 u32 dcache_ok; /* can we run with dcache? */
546 u32 casper_ok;
547
548 u32 mac_addr_lo_0;
549 u32 mac_addr_lo_1;
550 u32 mac_addr_lo_2;
551 u32 mac_addr_lo_3;
552
553 /* MN-related config */
554 u32 mn_sync_mode; /* enable/ sync shift cclk/ sync shift mclk */
555 u32 mn_sync_shift_cclk;
556 u32 mn_sync_shift_mclk;
557 u32 mn_wb_en;
558 u32 mn_crystal_freq; /* in MHz */
559 u32 mn_speed; /* in MHz */
560 u32 mn_org;
561 u32 mn_depth;
562 u32 mn_ranks_0; /* ranks per slot */
563 u32 mn_ranks_1; /* ranks per slot */
564 u32 mn_rd_latency_0;
565 u32 mn_rd_latency_1;
566 u32 mn_rd_latency_2;
567 u32 mn_rd_latency_3;
568 u32 mn_rd_latency_4;
569 u32 mn_rd_latency_5;
570 u32 mn_rd_latency_6;
571 u32 mn_rd_latency_7;
572 u32 mn_rd_latency_8;
573 u32 mn_dll_val[18];
574 u32 mn_mode_reg; /* MIU DDR Mode Register */
575 u32 mn_ext_mode_reg; /* MIU DDR Extended Mode Register */
576 u32 mn_timing_0; /* MIU Memory Control Timing Rgister */
577 u32 mn_timing_1; /* MIU Extended Memory Ctrl Timing Register */
578 u32 mn_timing_2; /* MIU Extended Memory Ctrl Timing2 Register */
579
580 /* SN-related config */
581 u32 sn_sync_mode; /* enable/ sync shift cclk / sync shift mclk */
582 u32 sn_pt_mode; /* pass through mode */
583 u32 sn_ecc_en;
584 u32 sn_wb_en;
585 u32 sn_crystal_freq;
586 u32 sn_speed;
587 u32 sn_org;
588 u32 sn_depth;
589 u32 sn_dll_tap;
590 u32 sn_rd_latency;
591
592 u32 mac_addr_hi_0;
593 u32 mac_addr_hi_1;
594 u32 mac_addr_hi_2;
595 u32 mac_addr_hi_3;
596
597 u32 magic; /* indicates flash has been initialized */
598
599 u32 mn_rdimm;
600 u32 mn_dll_override;
601
602 };
603
604 #define FLASH_NUM_PORTS (4)
605
606 struct netxen_flash_mac_addr {
607 u32 flash_addr[32];
608 };
609
610 struct netxen_user_old_info {
611 u8 flash_md5[16];
612 u8 crbinit_md5[16];
613 u8 brdcfg_md5[16];
614 /* bootloader */
615 u32 bootld_version;
616 u32 bootld_size;
617 u8 bootld_md5[16];
618 /* image */
619 u32 image_version;
620 u32 image_size;
621 u8 image_md5[16];
622 /* primary image status */
623 u32 primary_status;
624 u32 secondary_present;
625
626 /* MAC address , 4 ports */
627 struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
628 };
629 #define FLASH_NUM_MAC_PER_PORT 32
630 struct netxen_user_info {
631 u8 flash_md5[16 * 64];
632 /* bootloader */
633 u32 bootld_version;
634 u32 bootld_size;
635 /* image */
636 u32 image_version;
637 u32 image_size;
638 /* primary image status */
639 u32 primary_status;
640 u32 secondary_present;
641
642 /* MAC address , 4 ports, 32 address per port */
643 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
644 u32 sub_sys_id;
645 u8 serial_num[32];
646
647 /* Any user defined data */
648 };
649
650 /*
651 * Flash Layout - new format.
652 */
653 struct netxen_new_user_info {
654 u8 flash_md5[16 * 64];
655 /* bootloader */
656 u32 bootld_version;
657 u32 bootld_size;
658 /* image */
659 u32 image_version;
660 u32 image_size;
661 /* primary image status */
662 u32 primary_status;
663 u32 secondary_present;
664
665 /* MAC address , 4 ports, 32 address per port */
666 u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
667 u32 sub_sys_id;
668 u8 serial_num[32];
669
670 /* Any user defined data */
671 };
672
673 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
674 #define SECONDARY_IMAGE_ABSENT 0xffffffff
675 #define PRIMARY_IMAGE_GOOD 0x5a5a5a5a
676 #define PRIMARY_IMAGE_BAD 0xffffffff
677
678 /* Flash memory map */
679 typedef enum {
680 NETXEN_CRBINIT_START = 0, /* Crbinit section */
681 NETXEN_BRDCFG_START = 0x4000, /* board config */
682 NETXEN_INITCODE_START = 0x6000, /* pegtune code */
683 NETXEN_BOOTLD_START = 0x10000, /* bootld */
684 NETXEN_IMAGE_START = 0x43000, /* compressed image */
685 NETXEN_SECONDARY_START = 0x200000, /* backup images */
686 NETXEN_PXE_START = 0x3E0000, /* user defined region */
687 NETXEN_USER_START = 0x3E8000, /* User defined region for new boards */
688 NETXEN_FIXED_START = 0x3F0000 /* backup of crbinit */
689 } netxen_flash_map_t;
690
691 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408)
692 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c)
693 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c)
694 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128)
695 #define NX_FW_MIN_SIZE (0x3fffff)
696 #define NX_P2_MN_ROMIMAGE 0
697 #define NX_P3_CT_ROMIMAGE 1
698 #define NX_P3_MN_ROMIMAGE 2
699
700 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* for backward compatibility */
701
702 #define NETXEN_FLASH_START (NETXEN_CRBINIT_START)
703 #define NETXEN_INIT_SECTOR (0)
704 #define NETXEN_PRIMARY_START (NETXEN_BOOTLD_START)
705 #define NETXEN_FLASH_CRBINIT_SIZE (0x4000)
706 #define NETXEN_FLASH_BRDCFG_SIZE (sizeof(struct netxen_board_info))
707 #define NETXEN_FLASH_USER_SIZE (sizeof(struct netxen_user_info)/sizeof(u32))
708 #define NETXEN_FLASH_SECONDARY_SIZE (NETXEN_USER_START-NETXEN_SECONDARY_START)
709 #define NETXEN_NUM_PRIMARY_SECTORS (0x20)
710 #define NETXEN_NUM_CONFIG_SECTORS (1)
711 #define PFX "NetXen: "
712 extern char netxen_nic_driver_name[];
713
714 /* Note: Make sure to not call this before adapter->port is valid */
715 #if !defined(NETXEN_DEBUG)
716 #define DPRINTK(klevel, fmt, args...) do { \
717 } while (0)
718 #else
719 #define DPRINTK(klevel, fmt, args...) do { \
720 printk(KERN_##klevel PFX "%s: %s: " fmt, __func__,\
721 (adapter != NULL && adapter->netdev != NULL) ? \
722 adapter->netdev->name : NULL, \
723 ## args); } while(0)
724 #endif
725
726 /* Number of status descriptors to handle per interrupt */
727 #define MAX_STATUS_HANDLE (64)
728
729 /*
730 * netxen_skb_frag{} is to contain mapping info for each SG list. This
731 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
732 */
733 struct netxen_skb_frag {
734 u64 dma;
735 ulong length;
736 };
737
738 #define _netxen_set_bits(config_word, start, bits, val) {\
739 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
740 unsigned long long __tvalue = (val); \
741 (config_word) &= ~__tmask; \
742 (config_word) |= (((__tvalue) << (start)) & __tmask); \
743 }
744
745 #define _netxen_clear_bits(config_word, start, bits) {\
746 unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start)); \
747 (config_word) &= ~__tmask; \
748 }
749
750 /* Following defines are for the state of the buffers */
751 #define NETXEN_BUFFER_FREE 0
752 #define NETXEN_BUFFER_BUSY 1
753
754 /*
755 * There will be one netxen_buffer per skb packet. These will be
756 * used to save the dma info for pci_unmap_page()
757 */
758 struct netxen_cmd_buffer {
759 struct sk_buff *skb;
760 struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
761 u32 frag_count;
762 };
763
764 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
765 struct netxen_rx_buffer {
766 struct list_head list;
767 struct sk_buff *skb;
768 u64 dma;
769 u16 ref_handle;
770 u16 state;
771 };
772
773 /* Board types */
774 #define NETXEN_NIC_GBE 0x01
775 #define NETXEN_NIC_XGBE 0x02
776
777 /*
778 * One hardware_context{} per adapter
779 * contains interrupt info as well shared hardware info.
780 */
781 struct netxen_hardware_context {
782 void __iomem *pci_base0;
783 void __iomem *pci_base1;
784 void __iomem *pci_base2;
785 void __iomem *db_base;
786 unsigned long db_len;
787 unsigned long pci_len0;
788
789 int qdr_sn_window;
790 int ddr_mn_window;
791 unsigned long mn_win_crb;
792 unsigned long ms_win_crb;
793
794 u8 cut_through;
795 u8 revision_id;
796 u16 port_type;
797 int board_type;
798 u32 linkup;
799 /* Address of cmd ring in Phantom */
800 struct cmd_desc_type0 *cmd_desc_head;
801 dma_addr_t cmd_desc_phys_addr;
802 struct netxen_adapter *adapter;
803 int pci_func;
804 };
805
806 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
807 #define ETHERNET_FCS_SIZE 4
808
809 struct netxen_adapter_stats {
810 u64 rcvdbadskb;
811 u64 xmitcalled;
812 u64 xmitedframes;
813 u64 xmitfinished;
814 u64 badskblen;
815 u64 nocmddescriptor;
816 u64 polled;
817 u64 rxdropped;
818 u64 txdropped;
819 u64 csummed;
820 u64 no_rcv;
821 u64 rxbytes;
822 u64 txbytes;
823 u64 ints;
824 };
825
826 /*
827 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
828 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
829 */
830 struct nx_host_rds_ring {
831 u32 producer;
832 u32 crb_rcv_producer;
833 u32 num_desc;
834 u32 dma_size;
835 u32 skb_size;
836 u32 flags;
837 struct rcv_desc *desc_head;
838 struct netxen_rx_buffer *rx_buf_arr;
839 struct list_head free_list;
840 spinlock_t lock;
841 dma_addr_t phys_addr;
842 };
843
844 struct nx_host_sds_ring {
845 u32 consumer;
846 u32 crb_sts_consumer;
847 u32 crb_intr_mask;
848 u32 num_desc;
849
850 struct status_desc *desc_head;
851 struct netxen_adapter *adapter;
852 struct napi_struct napi;
853 struct list_head free_list[NUM_RCV_DESC_RINGS];
854
855 u16 clean_tx;
856 u16 post_rxd;
857 int irq;
858
859 dma_addr_t phys_addr;
860 char name[IFNAMSIZ+4];
861 };
862
863 /*
864 * Receive context. There is one such structure per instance of the
865 * receive processing. Any state information that is relevant to
866 * the receive, and is must be in this structure. The global data may be
867 * present elsewhere.
868 */
869 struct netxen_recv_context {
870 u32 state;
871 u16 context_id;
872 u16 virt_port;
873
874 struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
875 struct nx_host_sds_ring sds_rings[NUM_STS_DESC_RINGS];
876 };
877
878 /* New HW context creation */
879
880 #define NX_OS_CRB_RETRY_COUNT 4000
881 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
882 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
883
884 #define NX_CDRP_CLEAR 0x00000000
885 #define NX_CDRP_CMD_BIT 0x80000000
886
887 /*
888 * All responses must have the NX_CDRP_CMD_BIT cleared
889 * in the crb NX_CDRP_CRB_OFFSET.
890 */
891 #define NX_CDRP_FORM_RSP(rsp) (rsp)
892 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0)
893
894 #define NX_CDRP_RSP_OK 0x00000001
895 #define NX_CDRP_RSP_FAIL 0x00000002
896 #define NX_CDRP_RSP_TIMEOUT 0x00000003
897
898 /*
899 * All commands must have the NX_CDRP_CMD_BIT set in
900 * the crb NX_CDRP_CRB_OFFSET.
901 */
902 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd))
903 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0)
904
905 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
906 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
907 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
908 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
909 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
910 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
911 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007
912 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008
913 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009
914 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
915 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e
916 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f
917 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010
918 #define NX_CDRP_CMD_SET_MTU 0x00000012
919 #define NX_CDRP_CMD_MAX 0x00000013
920
921 #define NX_RCODE_SUCCESS 0
922 #define NX_RCODE_NO_HOST_MEM 1
923 #define NX_RCODE_NO_HOST_RESOURCE 2
924 #define NX_RCODE_NO_CARD_CRB 3
925 #define NX_RCODE_NO_CARD_MEM 4
926 #define NX_RCODE_NO_CARD_RESOURCE 5
927 #define NX_RCODE_INVALID_ARGS 6
928 #define NX_RCODE_INVALID_ACTION 7
929 #define NX_RCODE_INVALID_STATE 8
930 #define NX_RCODE_NOT_SUPPORTED 9
931 #define NX_RCODE_NOT_PERMITTED 10
932 #define NX_RCODE_NOT_READY 11
933 #define NX_RCODE_DOES_NOT_EXIST 12
934 #define NX_RCODE_ALREADY_EXISTS 13
935 #define NX_RCODE_BAD_SIGNATURE 14
936 #define NX_RCODE_CMD_NOT_IMPL 15
937 #define NX_RCODE_CMD_INVALID 16
938 #define NX_RCODE_TIMEOUT 17
939 #define NX_RCODE_CMD_FAILED 18
940 #define NX_RCODE_MAX_EXCEEDED 19
941 #define NX_RCODE_MAX 20
942
943 #define NX_DESTROY_CTX_RESET 0
944 #define NX_DESTROY_CTX_D3_RESET 1
945 #define NX_DESTROY_CTX_MAX 2
946
947 /*
948 * Capabilities
949 */
950 #define NX_CAP_BIT(class, bit) (1 << bit)
951 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0)
952 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1)
953 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2)
954 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3)
955 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4)
956 #define NX_CAP0_LRO NX_CAP_BIT(0, 5)
957 #define NX_CAP0_LSO NX_CAP_BIT(0, 6)
958 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7)
959 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8)
960
961 /*
962 * Context state
963 */
964 #define NX_HOST_CTX_STATE_FREED 0
965 #define NX_HOST_CTX_STATE_ALLOCATED 1
966 #define NX_HOST_CTX_STATE_ACTIVE 2
967 #define NX_HOST_CTX_STATE_DISABLED 3
968 #define NX_HOST_CTX_STATE_QUIESCED 4
969 #define NX_HOST_CTX_STATE_MAX 5
970
971 /*
972 * Rx context
973 */
974
975 typedef struct {
976 __le64 host_phys_addr; /* Ring base addr */
977 __le32 ring_size; /* Ring entries */
978 __le16 msi_index;
979 __le16 rsvd; /* Padding */
980 } nx_hostrq_sds_ring_t;
981
982 typedef struct {
983 __le64 host_phys_addr; /* Ring base addr */
984 __le64 buff_size; /* Packet buffer size */
985 __le32 ring_size; /* Ring entries */
986 __le32 ring_kind; /* Class of ring */
987 } nx_hostrq_rds_ring_t;
988
989 typedef struct {
990 __le64 host_rsp_dma_addr; /* Response dma'd here */
991 __le32 capabilities[4]; /* Flag bit vector */
992 __le32 host_int_crb_mode; /* Interrupt crb usage */
993 __le32 host_rds_crb_mode; /* RDS crb usage */
994 /* These ring offsets are relative to data[0] below */
995 __le32 rds_ring_offset; /* Offset to RDS config */
996 __le32 sds_ring_offset; /* Offset to SDS config */
997 __le16 num_rds_rings; /* Count of RDS rings */
998 __le16 num_sds_rings; /* Count of SDS rings */
999 __le16 rsvd1; /* Padding */
1000 __le16 rsvd2; /* Padding */
1001 u8 reserved[128]; /* reserve space for future expansion*/
1002 /* MUST BE 64-bit aligned.
1003 The following is packed:
1004 - N hostrq_rds_rings
1005 - N hostrq_sds_rings */
1006 char data[0];
1007 } nx_hostrq_rx_ctx_t;
1008
1009 typedef struct {
1010 __le32 host_producer_crb; /* Crb to use */
1011 __le32 rsvd1; /* Padding */
1012 } nx_cardrsp_rds_ring_t;
1013
1014 typedef struct {
1015 __le32 host_consumer_crb; /* Crb to use */
1016 __le32 interrupt_crb; /* Crb to use */
1017 } nx_cardrsp_sds_ring_t;
1018
1019 typedef struct {
1020 /* These ring offsets are relative to data[0] below */
1021 __le32 rds_ring_offset; /* Offset to RDS config */
1022 __le32 sds_ring_offset; /* Offset to SDS config */
1023 __le32 host_ctx_state; /* Starting State */
1024 __le32 num_fn_per_port; /* How many PCI fn share the port */
1025 __le16 num_rds_rings; /* Count of RDS rings */
1026 __le16 num_sds_rings; /* Count of SDS rings */
1027 __le16 context_id; /* Handle for context */
1028 u8 phys_port; /* Physical id of port */
1029 u8 virt_port; /* Virtual/Logical id of port */
1030 u8 reserved[128]; /* save space for future expansion */
1031 /* MUST BE 64-bit aligned.
1032 The following is packed:
1033 - N cardrsp_rds_rings
1034 - N cardrs_sds_rings */
1035 char data[0];
1036 } nx_cardrsp_rx_ctx_t;
1037
1038 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
1039 (sizeof(HOSTRQ_RX) + \
1040 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \
1041 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
1042
1043 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
1044 (sizeof(CARDRSP_RX) + \
1045 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \
1046 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
1047
1048 /*
1049 * Tx context
1050 */
1051
1052 typedef struct {
1053 __le64 host_phys_addr; /* Ring base addr */
1054 __le32 ring_size; /* Ring entries */
1055 __le32 rsvd; /* Padding */
1056 } nx_hostrq_cds_ring_t;
1057
1058 typedef struct {
1059 __le64 host_rsp_dma_addr; /* Response dma'd here */
1060 __le64 cmd_cons_dma_addr; /* */
1061 __le64 dummy_dma_addr; /* */
1062 __le32 capabilities[4]; /* Flag bit vector */
1063 __le32 host_int_crb_mode; /* Interrupt crb usage */
1064 __le32 rsvd1; /* Padding */
1065 __le16 rsvd2; /* Padding */
1066 __le16 interrupt_ctl;
1067 __le16 msi_index;
1068 __le16 rsvd3; /* Padding */
1069 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */
1070 u8 reserved[128]; /* future expansion */
1071 } nx_hostrq_tx_ctx_t;
1072
1073 typedef struct {
1074 __le32 host_producer_crb; /* Crb to use */
1075 __le32 interrupt_crb; /* Crb to use */
1076 } nx_cardrsp_cds_ring_t;
1077
1078 typedef struct {
1079 __le32 host_ctx_state; /* Starting state */
1080 __le16 context_id; /* Handle for context */
1081 u8 phys_port; /* Physical id of port */
1082 u8 virt_port; /* Virtual/Logical id of port */
1083 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
1084 u8 reserved[128]; /* future expansion */
1085 } nx_cardrsp_tx_ctx_t;
1086
1087 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
1088 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
1089
1090 /* CRB */
1091
1092 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0
1093 #define NX_HOST_RDS_CRB_MODE_SHARED 1
1094 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2
1095 #define NX_HOST_RDS_CRB_MODE_MAX 3
1096
1097 #define NX_HOST_INT_CRB_MODE_UNIQUE 0
1098 #define NX_HOST_INT_CRB_MODE_SHARED 1
1099 #define NX_HOST_INT_CRB_MODE_NORX 2
1100 #define NX_HOST_INT_CRB_MODE_NOTX 3
1101 #define NX_HOST_INT_CRB_MODE_NORXTX 4
1102
1103
1104 /* MAC */
1105
1106 #define MC_COUNT_P2 16
1107 #define MC_COUNT_P3 38
1108
1109 #define NETXEN_MAC_NOOP 0
1110 #define NETXEN_MAC_ADD 1
1111 #define NETXEN_MAC_DEL 2
1112
1113 typedef struct nx_mac_list_s {
1114 struct nx_mac_list_s *next;
1115 uint8_t mac_addr[MAX_ADDR_LEN];
1116 } nx_mac_list_t;
1117
1118 /*
1119 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1120 * adjusted based on configured MTU.
1121 */
1122 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1123 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1124 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1125 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1126
1127 #define NETXEN_NIC_INTR_DEFAULT 0x04
1128
1129 typedef union {
1130 struct {
1131 uint16_t rx_packets;
1132 uint16_t rx_time_us;
1133 uint16_t tx_packets;
1134 uint16_t tx_time_us;
1135 } data;
1136 uint64_t word;
1137 } nx_nic_intr_coalesce_data_t;
1138
1139 typedef struct {
1140 uint16_t stats_time_us;
1141 uint16_t rate_sample_time;
1142 uint16_t flags;
1143 uint16_t rsvd_1;
1144 uint32_t low_threshold;
1145 uint32_t high_threshold;
1146 nx_nic_intr_coalesce_data_t normal;
1147 nx_nic_intr_coalesce_data_t low;
1148 nx_nic_intr_coalesce_data_t high;
1149 nx_nic_intr_coalesce_data_t irq;
1150 } nx_nic_intr_coalesce_t;
1151
1152 #define NX_HOST_REQUEST 0x13
1153 #define NX_NIC_REQUEST 0x14
1154
1155 #define NX_MAC_EVENT 0x1
1156
1157 enum {
1158 NX_NIC_H2C_OPCODE_START = 0,
1159 NX_NIC_H2C_OPCODE_CONFIG_RSS,
1160 NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL,
1161 NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE,
1162 NX_NIC_H2C_OPCODE_CONFIG_LED,
1163 NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS,
1164 NX_NIC_H2C_OPCODE_CONFIG_L2_MAC,
1165 NX_NIC_H2C_OPCODE_LRO_REQUEST,
1166 NX_NIC_H2C_OPCODE_GET_SNMP_STATS,
1167 NX_NIC_H2C_OPCODE_PROXY_START_REQUEST,
1168 NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST,
1169 NX_NIC_H2C_OPCODE_PROXY_SET_MTU,
1170 NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE,
1171 NX_H2P_OPCODE_GET_FINGER_PRINT_REQUEST,
1172 NX_H2P_OPCODE_INSTALL_LICENSE_REQUEST,
1173 NX_H2P_OPCODE_GET_LICENSE_CAPABILITY_REQUEST,
1174 NX_NIC_H2C_OPCODE_GET_NET_STATS,
1175 NX_NIC_H2C_OPCODE_LAST
1176 };
1177
1178 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
1179 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
1180 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
1181
1182 typedef struct {
1183 __le64 qhdr;
1184 __le64 req_hdr;
1185 __le64 words[6];
1186 } nx_nic_req_t;
1187
1188 typedef struct {
1189 u8 op;
1190 u8 tag;
1191 u8 mac_addr[6];
1192 } nx_mac_req_t;
1193
1194 #define MAX_PENDING_DESC_BLOCK_SIZE 64
1195
1196 #define NETXEN_NIC_MSI_ENABLED 0x02
1197 #define NETXEN_NIC_MSIX_ENABLED 0x04
1198 #define NETXEN_IS_MSI_FAMILY(adapter) \
1199 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1200
1201 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
1202 #define NETXEN_MSIX_TBL_SPACE 8192
1203 #define NETXEN_PCI_REG_MSIX_TBL 0x44
1204
1205 #define NETXEN_DB_MAPSIZE_BYTES 0x1000
1206
1207 #define NETXEN_NETDEV_WEIGHT 128
1208 #define NETXEN_ADAPTER_UP_MAGIC 777
1209 #define NETXEN_NIC_PEG_TUNE 0
1210
1211 struct netxen_dummy_dma {
1212 void *addr;
1213 dma_addr_t phys_addr;
1214 };
1215
1216 struct netxen_adapter {
1217 struct netxen_hardware_context ahw;
1218
1219 struct net_device *netdev;
1220 struct pci_dev *pdev;
1221 int pci_using_dac;
1222 struct net_device_stats net_stats;
1223 int mtu;
1224 int portnum;
1225 u8 physical_port;
1226 u16 tx_context_id;
1227
1228 uint8_t mc_enabled;
1229 uint8_t max_mc_count;
1230 nx_mac_list_t *mac_list;
1231
1232 struct netxen_legacy_intr_set legacy_intr;
1233
1234 struct work_struct watchdog_task;
1235 struct timer_list watchdog_timer;
1236 struct work_struct tx_timeout_task;
1237
1238 u32 curr_window;
1239 u32 crb_win;
1240 rwlock_t adapter_lock;
1241
1242 u32 cmd_producer;
1243 __le32 *cmd_consumer;
1244 u32 last_cmd_consumer;
1245 u32 crb_addr_cmd_producer;
1246 u32 crb_addr_cmd_consumer;
1247 spinlock_t tx_clean_lock;
1248
1249 u32 num_txd;
1250 u32 num_rxd;
1251 u32 num_jumbo_rxd;
1252 u32 num_lro_rxd;
1253
1254 int max_rds_rings;
1255 int max_sds_rings;
1256
1257 u32 flags;
1258 u32 irq;
1259 int driver_mismatch;
1260 u32 temp;
1261
1262 u32 fw_major;
1263 u32 fw_version;
1264
1265 int msix_supported;
1266 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1267
1268 struct netxen_adapter_stats stats;
1269
1270 u16 link_speed;
1271 u16 link_duplex;
1272 u16 state;
1273 u16 link_autoneg;
1274 int rx_csum;
1275
1276 struct netxen_cmd_buffer *cmd_buf_arr; /* Command buffers for xmit */
1277
1278 /*
1279 * Receive instances. These can be either one per port,
1280 * or one per peg, etc.
1281 */
1282 struct netxen_recv_context recv_ctx;
1283
1284 int is_up;
1285 struct netxen_dummy_dma dummy_dma;
1286 nx_nic_intr_coalesce_t coal;
1287
1288 /* Context interface shared between card and host */
1289 struct netxen_ring_ctx *ctx_desc;
1290 dma_addr_t ctx_desc_phys_addr;
1291 int intr_scheme;
1292 int msi_mode;
1293 int (*enable_phy_interrupts) (struct netxen_adapter *);
1294 int (*disable_phy_interrupts) (struct netxen_adapter *);
1295 int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1296 int (*set_mtu) (struct netxen_adapter *, int);
1297 int (*set_promisc) (struct netxen_adapter *, u32);
1298 int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1299 int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1300 int (*init_port) (struct netxen_adapter *, int);
1301 int (*stop_port) (struct netxen_adapter *);
1302
1303 int (*hw_read_wx)(struct netxen_adapter *, ulong, void *, int);
1304 int (*hw_write_wx)(struct netxen_adapter *, ulong, void *, int);
1305 int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1306 int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1307 int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1308 u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1309 void (*pci_write_normalize)(struct netxen_adapter *, u64, u32);
1310 u32 (*pci_read_normalize)(struct netxen_adapter *, u64);
1311 unsigned long (*pci_set_window)(struct netxen_adapter *,
1312 unsigned long long);
1313 }; /* netxen_adapter structure */
1314
1315 /*
1316 * NetXen dma watchdog control structure
1317 *
1318 * Bit 0 : enabled => R/O: 1 watchdog active, 0 inactive
1319 * Bit 1 : disable_request => 1 req disable dma watchdog
1320 * Bit 2 : enable_request => 1 req enable dma watchdog
1321 * Bit 3-31 : unused
1322 */
1323
1324 #define netxen_set_dma_watchdog_disable_req(config_word) \
1325 _netxen_set_bits(config_word, 1, 1, 1)
1326 #define netxen_set_dma_watchdog_enable_req(config_word) \
1327 _netxen_set_bits(config_word, 2, 1, 1)
1328 #define netxen_get_dma_watchdog_enabled(config_word) \
1329 ((config_word) & 0x1)
1330 #define netxen_get_dma_watchdog_disabled(config_word) \
1331 (((config_word) >> 1) & 0x1)
1332
1333 /* Max number of xmit producer threads that can run simultaneously */
1334 #define MAX_XMIT_PRODUCERS 16
1335
1336 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
1337 ((adapter)->ahw.pci_base0 + (off))
1338 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
1339 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
1340 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
1341 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
1342
1343 static inline void __iomem *pci_base_offset(struct netxen_adapter *adapter,
1344 unsigned long off)
1345 {
1346 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1347 return (adapter->ahw.pci_base0 + off);
1348 } else if ((off < SECOND_PAGE_GROUP_END) &&
1349 (off >= SECOND_PAGE_GROUP_START)) {
1350 return (adapter->ahw.pci_base1 + off - SECOND_PAGE_GROUP_START);
1351 } else if ((off < THIRD_PAGE_GROUP_END) &&
1352 (off >= THIRD_PAGE_GROUP_START)) {
1353 return (adapter->ahw.pci_base2 + off - THIRD_PAGE_GROUP_START);
1354 }
1355 return NULL;
1356 }
1357
1358 static inline void __iomem *pci_base(struct netxen_adapter *adapter,
1359 unsigned long off)
1360 {
1361 if ((off < FIRST_PAGE_GROUP_END) && (off >= FIRST_PAGE_GROUP_START)) {
1362 return adapter->ahw.pci_base0;
1363 } else if ((off < SECOND_PAGE_GROUP_END) &&
1364 (off >= SECOND_PAGE_GROUP_START)) {
1365 return adapter->ahw.pci_base1;
1366 } else if ((off < THIRD_PAGE_GROUP_END) &&
1367 (off >= THIRD_PAGE_GROUP_START)) {
1368 return adapter->ahw.pci_base2;
1369 }
1370 return NULL;
1371 }
1372
1373 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1374 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1375 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1376 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1377 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1378 __u32 * readval);
1379 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1380 long reg, __u32 val);
1381
1382 /* Functions available from netxen_nic_hw.c */
1383 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1384 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1385 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val);
1386 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off);
1387 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value);
1388 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value);
1389 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value);
1390 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value);
1391
1392 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1393 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1394 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1395
1396 int netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1397 ulong off, void *data, int len);
1398 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1399 ulong off, void *data, int len);
1400 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1401 u64 off, void *data, int size);
1402 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1403 u64 off, void *data, int size);
1404 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1405 u64 off, u32 data);
1406 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1407 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1408 u64 off, u32 data);
1409 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1410 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1411 unsigned long long addr);
1412 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1413 u32 wndw);
1414
1415 int netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1416 ulong off, void *data, int len);
1417 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1418 ulong off, void *data, int len);
1419 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1420 u64 off, void *data, int size);
1421 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1422 u64 off, void *data, int size);
1423 void netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
1424 unsigned long off, int data);
1425 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1426 u64 off, u32 data);
1427 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1428 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1429 u64 off, u32 data);
1430 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1431 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1432 unsigned long long addr);
1433
1434 /* Functions from netxen_nic_init.c */
1435 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1436 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1437 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1438 int netxen_receive_peg_ready(struct netxen_adapter *adapter);
1439 int netxen_load_firmware(struct netxen_adapter *adapter);
1440 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1441
1442 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1443 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1444 u8 *bytes, size_t size);
1445 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1446 u8 *bytes, size_t size);
1447 int netxen_flash_unlock(struct netxen_adapter *adapter);
1448 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1449 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1450 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1451 void netxen_halt_pegs(struct netxen_adapter *adapter);
1452
1453 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1454
1455 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1456 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1457
1458 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1459 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1460
1461 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1462 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1463
1464 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1465 int netxen_init_firmware(struct netxen_adapter *adapter);
1466 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1467 void netxen_watchdog_task(struct work_struct *work);
1468 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1469 struct nx_host_rds_ring *rds_ring);
1470 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1471 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1472 void netxen_p2_nic_set_multi(struct net_device *netdev);
1473 void netxen_p3_nic_set_multi(struct net_device *netdev);
1474 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1475 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1476 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1477 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1478
1479 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1480 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1481
1482 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1483 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1484
1485 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1486 uint32_t crb_producer);
1487
1488 /*
1489 * NetXen Board information
1490 */
1491
1492 #define NETXEN_MAX_SHORT_NAME 32
1493 struct netxen_brdinfo {
1494 netxen_brdtype_t brdtype; /* type of board */
1495 long ports; /* max no of physical ports */
1496 char short_name[NETXEN_MAX_SHORT_NAME];
1497 };
1498
1499 static const struct netxen_brdinfo netxen_boards[] = {
1500 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1501 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1502 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1503 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1504 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1505 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1506 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "},
1507 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"},
1508 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"},
1509 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"},
1510 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"},
1511 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1512 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1513 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"},
1514 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1515 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1516 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1517 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1518 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1519 };
1520
1521 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1522
1523 static inline void get_brd_name_by_type(u32 type, char *name)
1524 {
1525 int i, found = 0;
1526 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1527 if (netxen_boards[i].brdtype == type) {
1528 strcpy(name, netxen_boards[i].short_name);
1529 found = 1;
1530 break;
1531 }
1532
1533 }
1534 if (!found)
1535 name = "Unknown";
1536 }
1537
1538 static inline int
1539 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1540 {
1541 u32 ctrl;
1542
1543 /* check if already inactive */
1544 if (adapter->hw_read_wx(adapter,
1545 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1546 printk(KERN_ERR "failed to read dma watchdog status\n");
1547
1548 if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1549 return 1;
1550
1551 /* Send the disable request */
1552 netxen_set_dma_watchdog_disable_req(ctrl);
1553 netxen_crb_writelit_adapter(adapter,
1554 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1555
1556 return 0;
1557 }
1558
1559 static inline int
1560 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1561 {
1562 u32 ctrl;
1563
1564 if (adapter->hw_read_wx(adapter,
1565 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1566 printk(KERN_ERR "failed to read dma watchdog status\n");
1567
1568 return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1569 }
1570
1571 static inline int
1572 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1573 {
1574 u32 ctrl;
1575
1576 if (adapter->hw_read_wx(adapter,
1577 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), &ctrl, 4))
1578 printk(KERN_ERR "failed to read dma watchdog status\n");
1579
1580 if (netxen_get_dma_watchdog_enabled(ctrl))
1581 return 1;
1582
1583 /* send the wakeup request */
1584 netxen_set_dma_watchdog_enable_req(ctrl);
1585
1586 netxen_crb_writelit_adapter(adapter,
1587 NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1588
1589 return 0;
1590 }
1591
1592
1593 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1594 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1595 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1596 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1597 int *valp);
1598
1599 extern struct ethtool_ops netxen_nic_ethtool_ops;
1600
1601 #endif /* __NETXEN_NIC_H_ */
Linux kernel - Deliverables
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