drivers/net/netxen/netxen_nic.h

   1 /*
   2  * Copyright (C) 2003 - 2009 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen Inc,
  26  * 18922 Forge Drive
  27  * Cupertino, CA 95014-0701
  28  *
  29  */
  30
  31 #ifndef _NETXEN_NIC_H_
  32 #define _NETXEN_NIC_H_
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ioport.h>
  38 #include <linux/pci.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/ip.h>
  42 #include <linux/in.h>
  43 #include <linux/tcp.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/firmware.h>
  46
  47 #include <linux/ethtool.h>
  48 #include <linux/mii.h>
  49 #include <linux/timer.h>
  50
  51 #include <linux/vmalloc.h>
  52
  53 #include <asm/io.h>
  54 #include <asm/byteorder.h>
  55
  56 #include "netxen_nic_hw.h"
  57
  58 #define _NETXEN_NIC_LINUX_MAJOR 4
  59 #define _NETXEN_NIC_LINUX_MINOR 0
  60 #define _NETXEN_NIC_LINUX_SUBVERSION 30
  61 #define NETXEN_NIC_LINUX_VERSIONID  "4.0.30"
  62
  63 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 24) + ((b) << 16) + (c))
  64 #define _major(v)       (((v) >> 24) & 0xff)
  65 #define _minor(v)       (((v) >> 16) & 0xff)
  66 #define _build(v)       ((v) & 0xffff)
  67
  68 /* version in image has weird encoding:
  69  *  7:0  - major
  70  * 15:8  - minor
  71  * 31:16 - build (little endian)
  72  */
  73 #define NETXEN_DECODE_VERSION(v) \
  74         NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
  75
  76 #define NETXEN_NUM_FLASH_SECTORS (64)
  77 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  78 #define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  79                                         * NETXEN_FLASH_SECTOR_SIZE)
  80
  81 #define PHAN_VENDOR_ID 0x4040
  82
  83 #define RCV_DESC_RINGSIZE(rds_ring)     \
  84         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  85 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  86         (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  87 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  88         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  89 #define TX_BUFF_RINGSIZE(tx_ring)       \
  90         (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  91 #define TX_DESC_RINGSIZE(tx_ring)       \
  92         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  93
  94 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  95
  96 #define NETXEN_RCV_PRODUCER_OFFSET      0
  97 #define NETXEN_RCV_PEG_DB_ID            2
  98 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  99 #define FLASH_SUCCESS 0
 100
 101 #define ADDR_IN_WINDOW1(off)    \
 102         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
 103
 104 /*
 105  * normalize a 64MB crb address to 32MB PCI window
 106  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
 107  */
 108 #define NETXEN_CRB_NORMAL(reg)  \
 109         ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
 110
 111 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
 112         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 113
 114 #define DB_NORMALIZE(adapter, off) \
 115         (adapter->ahw.db_base + (off))
 116
 117 #define NX_P2_C0                0x24
 118 #define NX_P2_C1                0x25
 119 #define NX_P3_A0                0x30
 120 #define NX_P3_A2                0x30
 121 #define NX_P3_B0                0x40
 122 #define NX_P3_B1                0x41
 123 #define NX_P3_B2                0x42
 124
 125 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 126 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 127
 128 #define FIRST_PAGE_GROUP_START  0
 129 #define FIRST_PAGE_GROUP_END    0x100000
 130
 131 #define SECOND_PAGE_GROUP_START 0x6000000
 132 #define SECOND_PAGE_GROUP_END   0x68BC000
 133
 134 #define THIRD_PAGE_GROUP_START  0x70E4000
 135 #define THIRD_PAGE_GROUP_END    0x8000000
 136
 137 #define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 138 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 139 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 140
 141 #define P2_MAX_MTU                     (8000)
 142 #define P3_MAX_MTU                     (9600)
 143 #define NX_ETHERMTU                    1500
 144 #define NX_MAX_ETHERHDR                32 /* This contains some padding */
 145
 146 #define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 149 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 150
 151 #define MAX_RX_BUFFER_LENGTH            1760
 152 #define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 153 #define MAX_RX_LRO_BUFFER_LENGTH        (8062)
 154 #define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 155 #define RX_JUMBO_DMA_MAP_LEN    \
 156         (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 157 #define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 158
 159 /*
 160  * Maximum number of ring contexts
 161  */
 162 #define MAX_RING_CTX 1
 163
 164 /* Opcodes to be used with the commands */
 165 #define TX_ETHER_PKT    0x01
 166 #define TX_TCP_PKT      0x02
 167 #define TX_UDP_PKT      0x03
 168 #define TX_IP_PKT       0x04
 169 #define TX_TCP_LSO      0x05
 170 #define TX_TCP_LSO6     0x06
 171 #define TX_IPSEC        0x07
 172 #define TX_IPSEC_CMD    0x0a
 173 #define TX_TCPV6_PKT    0x0b
 174 #define TX_UDPV6_PKT    0x0c
 175
 176 /* The following opcodes are for internal consumption. */
 177 #define NETXEN_CONTROL_OP       0x10
 178 #define PEGNET_REQUEST          0x11
 179
 180 #define MAX_NUM_CARDS           4
 181
 182 #define MAX_BUFFERS_PER_CMD     32
 183 #define TX_STOP_THRESH          ((MAX_SKB_FRAGS >> 2) + 4)
 184
 185 /*
 186  * Following are the states of the Phantom. Phantom will set them and
 187  * Host will read to check if the fields are correct.
 188  */
 189 #define PHAN_INITIALIZE_START           0xff00
 190 #define PHAN_INITIALIZE_FAILED          0xffff
 191 #define PHAN_INITIALIZE_COMPLETE        0xff01
 192
 193 /* Host writes the following to notify that it has done the init-handshake */
 194 #define PHAN_INITIALIZE_ACK     0xf00f
 195
 196 #define NUM_RCV_DESC_RINGS      3
 197 #define NUM_STS_DESC_RINGS      4
 198
 199 #define RCV_RING_NORMAL 0
 200 #define RCV_RING_JUMBO  1
 201 #define RCV_RING_LRO    2
 202
 203 #define MIN_CMD_DESCRIPTORS             64
 204 #define MIN_RCV_DESCRIPTORS             64
 205 #define MIN_JUMBO_DESCRIPTORS           32
 206
 207 #define MAX_CMD_DESCRIPTORS             1024
 208 #define MAX_RCV_DESCRIPTORS_1G          4096
 209 #define MAX_RCV_DESCRIPTORS_10G         8192
 210 #define MAX_JUMBO_RCV_DESCRIPTORS_1G    512
 211 #define MAX_JUMBO_RCV_DESCRIPTORS_10G   1024
 212 #define MAX_LRO_RCV_DESCRIPTORS         8
 213
 214 #define DEFAULT_RCV_DESCRIPTORS_1G      2048
 215 #define DEFAULT_RCV_DESCRIPTORS_10G     4096
 216
 217 #define NETXEN_CTX_SIGNATURE    0xdee0
 218 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0
 219 #define NETXEN_CTX_RESET        0xbad0
 220 #define NETXEN_CTX_D3_RESET     0xacc0
 221 #define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 222
 223 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 224 #define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 225
 226 #define get_next_index(index, length)   \
 227         (((index) + 1) & ((length) - 1))
 228
 229 #define get_index_range(index,length,count)     \
 230         (((index) + (count)) & ((length) - 1))
 231
 232 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
 233 #define MPORT_MULTI_FUNCTION_MODE 0x2222
 234
 235 #include "netxen_nic_phan_reg.h"
 236
 237 /*
 238  * NetXen host-peg signal message structure
 239  *
 240  *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 241  *      Bit 2           : priv_id => must be 1
 242  *      Bit 3-17        : count => for doorbell
 243  *      Bit 18-27       : ctx_id => Context id
 244  *      Bit 28-31       : opcode
 245  */
 246
 247 typedef u32 netxen_ctx_msg;
 248
 249 #define netxen_set_msg_peg_id(config_word, val) \
 250         ((config_word) &= ~3, (config_word) |= val & 3)
 251 #define netxen_set_msg_privid(config_word)      \
 252         ((config_word) |= 1 << 2)
 253 #define netxen_set_msg_count(config_word, val)  \
 254         ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 255 #define netxen_set_msg_ctxid(config_word, val)  \
 256         ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 257 #define netxen_set_msg_opcode(config_word, val) \
 258         ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 259
 260 struct netxen_rcv_ring {
 261         __le64 addr;
 262         __le32 size;
 263         __le32 rsrvd;
 264 };
 265
 266 struct netxen_sts_ring {
 267         __le64 addr;
 268         __le32 size;
 269         __le16 msi_index;
 270         __le16 rsvd;
 271 } ;
 272
 273 struct netxen_ring_ctx {
 274
 275         /* one command ring */
 276         __le64 cmd_consumer_offset;
 277         __le64 cmd_ring_addr;
 278         __le32 cmd_ring_size;
 279         __le32 rsrvd;
 280
 281         /* three receive rings */
 282         struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS];
 283
 284         __le64 sts_ring_addr;
 285         __le32 sts_ring_size;
 286
 287         __le32 ctx_id;
 288
 289         __le64 rsrvd_2[3];
 290         __le32 sts_ring_count;
 291         __le32 rsrvd_3;
 292         struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS];
 293
 294 } __attribute__ ((aligned(64)));
 295
 296 /*
 297  * Following data structures describe the descriptors that will be used.
 298  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 299  * we are doing LSO (above the 1500 size packet) only.
 300  */
 301
 302 /*
 303  * The size of reference handle been changed to 16 bits to pass the MSS fields
 304  * for the LSO packet
 305  */
 306
 307 #define FLAGS_CHECKSUM_ENABLED  0x01
 308 #define FLAGS_LSO_ENABLED       0x02
 309 #define FLAGS_IPSEC_SA_ADD      0x04
 310 #define FLAGS_IPSEC_SA_DELETE   0x08
 311 #define FLAGS_VLAN_TAGGED       0x10
 312
 313 #define netxen_set_cmd_desc_port(cmd_desc, var) \
 314         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 315 #define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 316         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 317
 318 #define netxen_set_tx_port(_desc, _port) \
 319         (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
 320
 321 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
 322         (_desc)->flags_opcode = \
 323         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
 324
 325 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
 326         (_desc)->nfrags__length = \
 327         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
 328
 329 struct cmd_desc_type0 {
 330         u8 tcp_hdr_offset;      /* For LSO only */
 331         u8 ip_hdr_offset;       /* For LSO only */
 332         __le16 flags_opcode;    /* 15:13 unused, 12:7 opcode, 6:0 flags */
 333         __le32 nfrags__length;  /* 31:8 total len, 7:0 frag count */
 334
 335         __le64 addr_buffer2;
 336
 337         __le16 reference_handle;
 338         __le16 mss;
 339         u8 port_ctxid;          /* 7:4 ctxid 3:0 port */
 340         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 341         __le16 conn_id;         /* IPSec offoad only */
 342
 343         __le64 addr_buffer3;
 344         __le64 addr_buffer1;
 345
 346         __le16 buffer_length[4];
 347
 348         __le64 addr_buffer4;
 349
 350         __le64 unused;
 351
 352 } __attribute__ ((aligned(64)));
 353
 354 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 355 struct rcv_desc {
 356         __le16 reference_handle;
 357         __le16 reserved;
 358         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 359         __le64 addr_buffer;
 360 };
 361
 362 /* opcode field in status_desc */
 363 #define NETXEN_NIC_SYN_OFFLOAD  0x03
 364 #define NETXEN_NIC_RXPKT_DESC  0x04
 365 #define NETXEN_OLD_RXPKT_DESC  0x3f
 366 #define NETXEN_NIC_RESPONSE_DESC 0x05
 367
 368 /* for status field in status_desc */
 369 #define STATUS_NEED_CKSUM       (1)
 370 #define STATUS_CKSUM_OK         (2)
 371
 372 /* owner bits of status_desc */
 373 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 374 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 375
 376 /* Status descriptor:
 377    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 378    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 379    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 380  */
 381 #define netxen_get_sts_port(sts_data)   \
 382         ((sts_data) & 0x0F)
 383 #define netxen_get_sts_status(sts_data) \
 384         (((sts_data) >> 4) & 0x0F)
 385 #define netxen_get_sts_type(sts_data)   \
 386         (((sts_data) >> 8) & 0x0F)
 387 #define netxen_get_sts_totallength(sts_data)    \
 388         (((sts_data) >> 12) & 0xFFFF)
 389 #define netxen_get_sts_refhandle(sts_data)      \
 390         (((sts_data) >> 28) & 0xFFFF)
 391 #define netxen_get_sts_prot(sts_data)   \
 392         (((sts_data) >> 44) & 0x0F)
 393 #define netxen_get_sts_pkt_offset(sts_data)     \
 394         (((sts_data) >> 48) & 0x1F)
 395 #define netxen_get_sts_desc_cnt(sts_data)       \
 396         (((sts_data) >> 53) & 0x7)
 397 #define netxen_get_sts_opcode(sts_data) \
 398         (((sts_data) >> 58) & 0x03F)
 399
 400 struct status_desc {
 401         __le64 status_desc_data[2];
 402 } __attribute__ ((aligned(16)));
 403
 404 /* The version of the main data structure */
 405 #define NETXEN_BDINFO_VERSION 1
 406
 407 /* Magic number to let user know flash is programmed */
 408 #define NETXEN_BDINFO_MAGIC 0x12345678
 409
 410 /* Max number of Gig ports on a Phantom board */
 411 #define NETXEN_MAX_PORTS 4
 412
 413 #define NETXEN_BRDTYPE_P1_BD            0x0000
 414 #define NETXEN_BRDTYPE_P1_SB            0x0001
 415 #define NETXEN_BRDTYPE_P1_SMAX          0x0002
 416 #define NETXEN_BRDTYPE_P1_SOCK          0x0003
 417
 418 #define NETXEN_BRDTYPE_P2_SOCK_31       0x0008
 419 #define NETXEN_BRDTYPE_P2_SOCK_35       0x0009
 420 #define NETXEN_BRDTYPE_P2_SB35_4G       0x000a
 421 #define NETXEN_BRDTYPE_P2_SB31_10G      0x000b
 422 #define NETXEN_BRDTYPE_P2_SB31_2G       0x000c
 423
 424 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ         0x000d
 425 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ         0x000e
 426 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4          0x000f
 427
 428 #define NETXEN_BRDTYPE_P3_REF_QG        0x0021
 429 #define NETXEN_BRDTYPE_P3_HMEZ          0x0022
 430 #define NETXEN_BRDTYPE_P3_10G_CX4_LP    0x0023
 431 #define NETXEN_BRDTYPE_P3_4_GB          0x0024
 432 #define NETXEN_BRDTYPE_P3_IMEZ          0x0025
 433 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS  0x0026
 434 #define NETXEN_BRDTYPE_P3_10000_BASE_T  0x0027
 435 #define NETXEN_BRDTYPE_P3_XG_LOM        0x0028
 436 #define NETXEN_BRDTYPE_P3_4_GB_MM       0x0029
 437 #define NETXEN_BRDTYPE_P3_10G_SFP_CT    0x002a
 438 #define NETXEN_BRDTYPE_P3_10G_SFP_QT    0x002b
 439 #define NETXEN_BRDTYPE_P3_10G_CX4       0x0031
 440 #define NETXEN_BRDTYPE_P3_10G_XFP       0x0032
 441 #define NETXEN_BRDTYPE_P3_10G_TP        0x0080
 442
 443 struct netxen_board_info {
 444         u32 header_version;
 445
 446         u32 board_mfg;
 447         u32 board_type;
 448         u32 board_num;
 449         u32 chip_id;
 450         u32 chip_minor;
 451         u32 chip_major;
 452         u32 chip_pkg;
 453         u32 chip_lot;
 454
 455         u32 port_mask;          /* available niu ports */
 456         u32 peg_mask;           /* available pegs */
 457         u32 icache_ok;          /* can we run with icache? */
 458         u32 dcache_ok;          /* can we run with dcache? */
 459         u32 casper_ok;
 460
 461         u32 mac_addr_lo_0;
 462         u32 mac_addr_lo_1;
 463         u32 mac_addr_lo_2;
 464         u32 mac_addr_lo_3;
 465
 466         /* MN-related config */
 467         u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 468         u32 mn_sync_shift_cclk;
 469         u32 mn_sync_shift_mclk;
 470         u32 mn_wb_en;
 471         u32 mn_crystal_freq;    /* in MHz */
 472         u32 mn_speed;           /* in MHz */
 473         u32 mn_org;
 474         u32 mn_depth;
 475         u32 mn_ranks_0;         /* ranks per slot */
 476         u32 mn_ranks_1;         /* ranks per slot */
 477         u32 mn_rd_latency_0;
 478         u32 mn_rd_latency_1;
 479         u32 mn_rd_latency_2;
 480         u32 mn_rd_latency_3;
 481         u32 mn_rd_latency_4;
 482         u32 mn_rd_latency_5;
 483         u32 mn_rd_latency_6;
 484         u32 mn_rd_latency_7;
 485         u32 mn_rd_latency_8;
 486         u32 mn_dll_val[18];
 487         u32 mn_mode_reg;        /* MIU DDR Mode Register */
 488         u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 489         u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 490         u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 491         u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 492
 493         /* SN-related config */
 494         u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 495         u32 sn_pt_mode;         /* pass through mode */
 496         u32 sn_ecc_en;
 497         u32 sn_wb_en;
 498         u32 sn_crystal_freq;
 499         u32 sn_speed;
 500         u32 sn_org;
 501         u32 sn_depth;
 502         u32 sn_dll_tap;
 503         u32 sn_rd_latency;
 504
 505         u32 mac_addr_hi_0;
 506         u32 mac_addr_hi_1;
 507         u32 mac_addr_hi_2;
 508         u32 mac_addr_hi_3;
 509
 510         u32 magic;              /* indicates flash has been initialized */
 511
 512         u32 mn_rdimm;
 513         u32 mn_dll_override;
 514
 515 };
 516
 517 #define FLASH_NUM_PORTS         (4)
 518
 519 struct netxen_flash_mac_addr {
 520         u32 flash_addr[32];
 521 };
 522
 523 struct netxen_user_old_info {
 524         u8 flash_md5[16];
 525         u8 crbinit_md5[16];
 526         u8 brdcfg_md5[16];
 527         /* bootloader */
 528         u32 bootld_version;
 529         u32 bootld_size;
 530         u8 bootld_md5[16];
 531         /* image */
 532         u32 image_version;
 533         u32 image_size;
 534         u8 image_md5[16];
 535         /* primary image status */
 536         u32 primary_status;
 537         u32 secondary_present;
 538
 539         /* MAC address , 4 ports */
 540         struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 541 };
 542 #define FLASH_NUM_MAC_PER_PORT  32
 543 struct netxen_user_info {
 544         u8 flash_md5[16 * 64];
 545         /* bootloader */
 546         u32 bootld_version;
 547         u32 bootld_size;
 548         /* image */
 549         u32 image_version;
 550         u32 image_size;
 551         /* primary image status */
 552         u32 primary_status;
 553         u32 secondary_present;
 554
 555         /* MAC address , 4 ports, 32 address per port */
 556         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 557         u32 sub_sys_id;
 558         u8 serial_num[32];
 559
 560         /* Any user defined data */
 561 };
 562
 563 /*
 564  * Flash Layout - new format.
 565  */
 566 struct netxen_new_user_info {
 567         u8 flash_md5[16 * 64];
 568         /* bootloader */
 569         u32 bootld_version;
 570         u32 bootld_size;
 571         /* image */
 572         u32 image_version;
 573         u32 image_size;
 574         /* primary image status */
 575         u32 primary_status;
 576         u32 secondary_present;
 577
 578         /* MAC address , 4 ports, 32 address per port */
 579         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 580         u32 sub_sys_id;
 581         u8 serial_num[32];
 582
 583         /* Any user defined data */
 584 };
 585
 586 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 587 #define SECONDARY_IMAGE_ABSENT  0xffffffff
 588 #define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 589 #define PRIMARY_IMAGE_BAD       0xffffffff
 590
 591 /* Flash memory map */
 592 #define NETXEN_CRBINIT_START    0       /* crbinit section */
 593 #define NETXEN_BRDCFG_START     0x4000  /* board config */
 594 #define NETXEN_INITCODE_START   0x6000  /* pegtune code */
 595 #define NETXEN_BOOTLD_START     0x10000 /* bootld */
 596 #define NETXEN_IMAGE_START      0x43000 /* compressed image */
 597 #define NETXEN_SECONDARY_START  0x200000        /* backup images */
 598 #define NETXEN_PXE_START        0x3E0000        /* PXE boot rom */
 599 #define NETXEN_USER_START       0x3E8000        /* Firmare info */
 600 #define NETXEN_FIXED_START      0x3F0000        /* backup of crbinit */
 601
 602 #define NX_FW_VERSION_OFFSET    (NETXEN_USER_START+0x408)
 603 #define NX_FW_SIZE_OFFSET       (NETXEN_USER_START+0x40c)
 604 #define NX_BIOS_VERSION_OFFSET  (NETXEN_USER_START+0x83c)
 605 #define NX_FW_MAGIC_OFFSET      (NETXEN_BRDCFG_START+0x128)
 606 #define NX_FW_MIN_SIZE          (0x3fffff)
 607 #define NX_P2_MN_ROMIMAGE       0
 608 #define NX_P3_CT_ROMIMAGE       1
 609 #define NX_P3_MN_ROMIMAGE       2
 610 #define NX_FLASH_ROMIMAGE       3
 611
 612 #define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 613
 614 #define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 615 #define NETXEN_INIT_SECTOR              (0)
 616 #define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 617 #define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 618 #define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 619 #define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 620 #define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 621 #define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 622 #define NETXEN_NUM_CONFIG_SECTORS       (1)
 623 extern char netxen_nic_driver_name[];
 624
 625 /* Number of status descriptors to handle per interrupt */
 626 #define MAX_STATUS_HANDLE       (64)
 627
 628 /*
 629  * netxen_skb_frag{} is to contain mapping info for each SG list. This
 630  * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 631  */
 632 struct netxen_skb_frag {
 633         u64 dma;
 634         u64 length;
 635 };
 636
 637 #define _netxen_set_bits(config_word, start, bits, val) {\
 638         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 639         unsigned long long __tvalue = (val);    \
 640         (config_word) &= ~__tmask;      \
 641         (config_word) |= (((__tvalue) << (start)) & __tmask); \
 642 }
 643
 644 #define _netxen_clear_bits(config_word, start, bits) {\
 645         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 646         (config_word) &= ~__tmask; \
 647 }
 648
 649 /*    Following defines are for the state of the buffers    */
 650 #define NETXEN_BUFFER_FREE      0
 651 #define NETXEN_BUFFER_BUSY      1
 652
 653 /*
 654  * There will be one netxen_buffer per skb packet.    These will be
 655  * used to save the dma info for pci_unmap_page()
 656  */
 657 struct netxen_cmd_buffer {
 658         struct sk_buff *skb;
 659         struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 660         u32 frag_count;
 661 };
 662
 663 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 664 struct netxen_rx_buffer {
 665         struct list_head list;
 666         struct sk_buff *skb;
 667         u64 dma;
 668         u16 ref_handle;
 669         u16 state;
 670 };
 671
 672 /* Board types */
 673 #define NETXEN_NIC_GBE  0x01
 674 #define NETXEN_NIC_XGBE 0x02
 675
 676 /*
 677  * One hardware_context{} per adapter
 678  * contains interrupt info as well shared hardware info.
 679  */
 680 struct netxen_hardware_context {
 681         void __iomem *pci_base0;
 682         void __iomem *pci_base1;
 683         void __iomem *pci_base2;
 684         void __iomem *db_base;
 685         unsigned long db_len;
 686         unsigned long pci_len0;
 687
 688         int qdr_sn_window;
 689         int ddr_mn_window;
 690         unsigned long mn_win_crb;
 691         unsigned long ms_win_crb;
 692
 693         u8 cut_through;
 694         u8 revision_id;
 695         u8 pci_func;
 696         u8 linkup;
 697         u16 port_type;
 698         u16 board_type;
 699 };
 700
 701 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 702 #define ETHERNET_FCS_SIZE               4
 703
 704 struct netxen_adapter_stats {
 705         u64  xmitcalled;
 706         u64  xmitfinished;
 707         u64  rxdropped;
 708         u64  txdropped;
 709         u64  csummed;
 710         u64  no_rcv;
 711         u64  rxbytes;
 712         u64  txbytes;
 713 };
 714
 715 /*
 716  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 717  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 718  */
 719 struct nx_host_rds_ring {
 720         u32 producer;
 721         u32 crb_rcv_producer;
 722         u32 num_desc;
 723         u32 dma_size;
 724         u32 skb_size;
 725         u32 flags;
 726         struct rcv_desc *desc_head;
 727         struct netxen_rx_buffer *rx_buf_arr;
 728         struct list_head free_list;
 729         spinlock_t lock;
 730         dma_addr_t phys_addr;
 731 };
 732
 733 struct nx_host_sds_ring {
 734         u32 consumer;
 735         u32 crb_sts_consumer;
 736         u32 crb_intr_mask;
 737         u32 num_desc;
 738
 739         struct status_desc *desc_head;
 740         struct netxen_adapter *adapter;
 741         struct napi_struct napi;
 742         struct list_head free_list[NUM_RCV_DESC_RINGS];
 743
 744         int irq;
 745
 746         dma_addr_t phys_addr;
 747         char name[IFNAMSIZ+4];
 748 };
 749
 750 struct nx_host_tx_ring {
 751         u32 producer;
 752         __le32 *hw_consumer;
 753         u32 sw_consumer;
 754         u32 crb_cmd_producer;
 755         u32 crb_cmd_consumer;
 756         u32 num_desc;
 757
 758         struct netdev_queue *txq;
 759
 760         struct netxen_cmd_buffer *cmd_buf_arr;
 761         struct cmd_desc_type0 *desc_head;
 762         dma_addr_t phys_addr;
 763 };
 764
 765 /*
 766  * Receive context. There is one such structure per instance of the
 767  * receive processing. Any state information that is relevant to
 768  * the receive, and is must be in this structure. The global data may be
 769  * present elsewhere.
 770  */
 771 struct netxen_recv_context {
 772         u32 state;
 773         u16 context_id;
 774         u16 virt_port;
 775
 776         struct nx_host_rds_ring *rds_rings;
 777         struct nx_host_sds_ring *sds_rings;
 778
 779         struct netxen_ring_ctx *hwctx;
 780         dma_addr_t phys_addr;
 781 };
 782
 783 /* New HW context creation */
 784
 785 #define NX_OS_CRB_RETRY_COUNT   4000
 786 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 787         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 788
 789 #define NX_CDRP_CLEAR           0x00000000
 790 #define NX_CDRP_CMD_BIT         0x80000000
 791
 792 /*
 793  * All responses must have the NX_CDRP_CMD_BIT cleared
 794  * in the crb NX_CDRP_CRB_OFFSET.
 795  */
 796 #define NX_CDRP_FORM_RSP(rsp)   (rsp)
 797 #define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 798
 799 #define NX_CDRP_RSP_OK          0x00000001
 800 #define NX_CDRP_RSP_FAIL        0x00000002
 801 #define NX_CDRP_RSP_TIMEOUT     0x00000003
 802
 803 /*
 804  * All commands must have the NX_CDRP_CMD_BIT set in
 805  * the crb NX_CDRP_CRB_OFFSET.
 806  */
 807 #define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 808 #define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 809
 810 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 811 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 812 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 813 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 814 #define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 815 #define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 816 #define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 817 #define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 818 #define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 819 #define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 820 #define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 821 #define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 822 #define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 823 #define NX_CDRP_CMD_SET_MTU                 0x00000012
 824 #define NX_CDRP_CMD_MAX                     0x00000013
 825
 826 #define NX_RCODE_SUCCESS                0
 827 #define NX_RCODE_NO_HOST_MEM            1
 828 #define NX_RCODE_NO_HOST_RESOURCE       2
 829 #define NX_RCODE_NO_CARD_CRB            3
 830 #define NX_RCODE_NO_CARD_MEM            4
 831 #define NX_RCODE_NO_CARD_RESOURCE       5
 832 #define NX_RCODE_INVALID_ARGS           6
 833 #define NX_RCODE_INVALID_ACTION         7
 834 #define NX_RCODE_INVALID_STATE          8
 835 #define NX_RCODE_NOT_SUPPORTED          9
 836 #define NX_RCODE_NOT_PERMITTED          10
 837 #define NX_RCODE_NOT_READY              11
 838 #define NX_RCODE_DOES_NOT_EXIST         12
 839 #define NX_RCODE_ALREADY_EXISTS         13
 840 #define NX_RCODE_BAD_SIGNATURE          14
 841 #define NX_RCODE_CMD_NOT_IMPL           15
 842 #define NX_RCODE_CMD_INVALID            16
 843 #define NX_RCODE_TIMEOUT                17
 844 #define NX_RCODE_CMD_FAILED             18
 845 #define NX_RCODE_MAX_EXCEEDED           19
 846 #define NX_RCODE_MAX                    20
 847
 848 #define NX_DESTROY_CTX_RESET            0
 849 #define NX_DESTROY_CTX_D3_RESET         1
 850 #define NX_DESTROY_CTX_MAX              2
 851
 852 /*
 853  * Capabilities
 854  */
 855 #define NX_CAP_BIT(class, bit)          (1 << bit)
 856 #define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 857 #define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 858 #define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 859 #define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 860 #define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 861 #define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 862 #define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 863 #define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 864 #define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 865
 866 /*
 867  * Context state
 868  */
 869 #define NX_HOST_CTX_STATE_FREED         0
 870 #define NX_HOST_CTX_STATE_ALLOCATED     1
 871 #define NX_HOST_CTX_STATE_ACTIVE        2
 872 #define NX_HOST_CTX_STATE_DISABLED      3
 873 #define NX_HOST_CTX_STATE_QUIESCED      4
 874 #define NX_HOST_CTX_STATE_MAX           5
 875
 876 /*
 877  * Rx context
 878  */
 879
 880 typedef struct {
 881         __le64 host_phys_addr;  /* Ring base addr */
 882         __le32 ring_size;               /* Ring entries */
 883         __le16 msi_index;
 884         __le16 rsvd;            /* Padding */
 885 } nx_hostrq_sds_ring_t;
 886
 887 typedef struct {
 888         __le64 host_phys_addr;  /* Ring base addr */
 889         __le64 buff_size;               /* Packet buffer size */
 890         __le32 ring_size;               /* Ring entries */
 891         __le32 ring_kind;               /* Class of ring */
 892 } nx_hostrq_rds_ring_t;
 893
 894 typedef struct {
 895         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 896         __le32 capabilities[4]; /* Flag bit vector */
 897         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 898         __le32 host_rds_crb_mode;       /* RDS crb usage */
 899         /* These ring offsets are relative to data[0] below */
 900         __le32 rds_ring_offset; /* Offset to RDS config */
 901         __le32 sds_ring_offset; /* Offset to SDS config */
 902         __le16 num_rds_rings;   /* Count of RDS rings */
 903         __le16 num_sds_rings;   /* Count of SDS rings */
 904         __le16 rsvd1;           /* Padding */
 905         __le16 rsvd2;           /* Padding */
 906         u8  reserved[128];      /* reserve space for future expansion*/
 907         /* MUST BE 64-bit aligned.
 908            The following is packed:
 909            - N hostrq_rds_rings
 910            - N hostrq_sds_rings */
 911         char data[0];
 912 } nx_hostrq_rx_ctx_t;
 913
 914 typedef struct {
 915         __le32 host_producer_crb;       /* Crb to use */
 916         __le32 rsvd1;           /* Padding */
 917 } nx_cardrsp_rds_ring_t;
 918
 919 typedef struct {
 920         __le32 host_consumer_crb;       /* Crb to use */
 921         __le32 interrupt_crb;   /* Crb to use */
 922 } nx_cardrsp_sds_ring_t;
 923
 924 typedef struct {
 925         /* These ring offsets are relative to data[0] below */
 926         __le32 rds_ring_offset; /* Offset to RDS config */
 927         __le32 sds_ring_offset; /* Offset to SDS config */
 928         __le32 host_ctx_state;  /* Starting State */
 929         __le32 num_fn_per_port; /* How many PCI fn share the port */
 930         __le16 num_rds_rings;   /* Count of RDS rings */
 931         __le16 num_sds_rings;   /* Count of SDS rings */
 932         __le16 context_id;              /* Handle for context */
 933         u8  phys_port;          /* Physical id of port */
 934         u8  virt_port;          /* Virtual/Logical id of port */
 935         u8  reserved[128];      /* save space for future expansion */
 936         /*  MUST BE 64-bit aligned.
 937            The following is packed:
 938            - N cardrsp_rds_rings
 939            - N cardrs_sds_rings */
 940         char data[0];
 941 } nx_cardrsp_rx_ctx_t;
 942
 943 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 944         (sizeof(HOSTRQ_RX) +                                    \
 945         (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
 946         (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
 947
 948 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 949         (sizeof(CARDRSP_RX) +                                   \
 950         (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
 951         (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
 952
 953 /*
 954  * Tx context
 955  */
 956
 957 typedef struct {
 958         __le64 host_phys_addr;  /* Ring base addr */
 959         __le32 ring_size;               /* Ring entries */
 960         __le32 rsvd;            /* Padding */
 961 } nx_hostrq_cds_ring_t;
 962
 963 typedef struct {
 964         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 965         __le64 cmd_cons_dma_addr;       /*  */
 966         __le64 dummy_dma_addr;  /*  */
 967         __le32 capabilities[4]; /* Flag bit vector */
 968         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 969         __le32 rsvd1;           /* Padding */
 970         __le16 rsvd2;           /* Padding */
 971         __le16 interrupt_ctl;
 972         __le16 msi_index;
 973         __le16 rsvd3;           /* Padding */
 974         nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
 975         u8  reserved[128];      /* future expansion */
 976 } nx_hostrq_tx_ctx_t;
 977
 978 typedef struct {
 979         __le32 host_producer_crb;       /* Crb to use */
 980         __le32 interrupt_crb;   /* Crb to use */
 981 } nx_cardrsp_cds_ring_t;
 982
 983 typedef struct {
 984         __le32 host_ctx_state;  /* Starting state */
 985         __le16 context_id;              /* Handle for context */
 986         u8  phys_port;          /* Physical id of port */
 987         u8  virt_port;          /* Virtual/Logical id of port */
 988         nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
 989         u8  reserved[128];      /* future expansion */
 990 } nx_cardrsp_tx_ctx_t;
 991
 992 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
 993 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
 994
 995 /* CRB */
 996
 997 #define NX_HOST_RDS_CRB_MODE_UNIQUE     0
 998 #define NX_HOST_RDS_CRB_MODE_SHARED     1
 999 #define NX_HOST_RDS_CRB_MODE_CUSTOM     2
1000 #define NX_HOST_RDS_CRB_MODE_MAX        3
1001
1002 #define NX_HOST_INT_CRB_MODE_UNIQUE     0
1003 #define NX_HOST_INT_CRB_MODE_SHARED     1
1004 #define NX_HOST_INT_CRB_MODE_NORX       2
1005 #define NX_HOST_INT_CRB_MODE_NOTX       3
1006 #define NX_HOST_INT_CRB_MODE_NORXTX     4
1007
1008
1009 /* MAC */
1010
1011 #define MC_COUNT_P2     16
1012 #define MC_COUNT_P3     38
1013
1014 #define NETXEN_MAC_NOOP 0
1015 #define NETXEN_MAC_ADD  1
1016 #define NETXEN_MAC_DEL  2
1017
1018 typedef struct nx_mac_list_s {
1019         struct list_head list;
1020         uint8_t mac_addr[ETH_ALEN+2];
1021 } nx_mac_list_t;
1022
1023 /*
1024  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1025  * adjusted based on configured MTU.
1026  */
1027 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1028 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1029 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1030 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1031
1032 #define NETXEN_NIC_INTR_DEFAULT                 0x04
1033
1034 typedef union {
1035         struct {
1036                 uint16_t        rx_packets;
1037                 uint16_t        rx_time_us;
1038                 uint16_t        tx_packets;
1039                 uint16_t        tx_time_us;
1040         } data;
1041         uint64_t                word;
1042 } nx_nic_intr_coalesce_data_t;
1043
1044 typedef struct {
1045         uint16_t                        stats_time_us;
1046         uint16_t                        rate_sample_time;
1047         uint16_t                        flags;
1048         uint16_t                        rsvd_1;
1049         uint32_t                        low_threshold;
1050         uint32_t                        high_threshold;
1051         nx_nic_intr_coalesce_data_t     normal;
1052         nx_nic_intr_coalesce_data_t     low;
1053         nx_nic_intr_coalesce_data_t     high;
1054         nx_nic_intr_coalesce_data_t     irq;
1055 } nx_nic_intr_coalesce_t;
1056
1057 #define NX_HOST_REQUEST         0x13
1058 #define NX_NIC_REQUEST          0x14
1059
1060 #define NX_MAC_EVENT            0x1
1061
1062 #define NX_IP_UP                2
1063 #define NX_IP_DOWN              3
1064
1065 /*
1066  * Driver --> Firmware
1067  */
1068 #define NX_NIC_H2C_OPCODE_START                         0
1069 #define NX_NIC_H2C_OPCODE_CONFIG_RSS                    1
1070 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL                2
1071 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE          3
1072 #define NX_NIC_H2C_OPCODE_CONFIG_LED                    4
1073 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS            5
1074 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC                 6
1075 #define NX_NIC_H2C_OPCODE_LRO_REQUEST                   7
1076 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS                8
1077 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST           9
1078 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST            10
1079 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU                 11
1080 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE     12
1081 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST      13
1082 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST       14
1083 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST        15
1084 #define NX_NIC_H2C_OPCODE_GET_NET_STATS                 16
1085 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
1086 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR                 18
1087 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK               19
1088 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE               20
1089 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT                 21
1090 #define NX_NIC_C2C_OPCODE                               22
1091 #define NX_NIC_H2C_OPCODE_LAST                          23
1092
1093 /*
1094  * Firmware --> Driver
1095  */
1096
1097 #define NX_NIC_C2H_OPCODE_START                         128
1098 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE           129
1099 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE       130
1100 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE           131
1101 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE   132
1102 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE        133
1103 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE           134
1104 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE      135
1105 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS                136
1106 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY        137
1107 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY         138
1108 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1109 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE        140
1110 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
1111 #define NX_NIC_C2H_OPCODE_LAST                          142
1112
1113 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1114 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1115 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1116
1117 #define NX_FW_CAPABILITY_LINK_NOTIFICATION      (1 << 5)
1118 #define NX_FW_CAPABILITY_SWITCHING              (1 << 6)
1119
1120 /* module types */
1121 #define LINKEVENT_MODULE_NOT_PRESENT                    1
1122 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
1123 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
1124 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
1125 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
1126 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
1127 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
1128 #define LINKEVENT_MODULE_TWINAX                         8
1129
1130 #define LINKSPEED_10GBPS        10000
1131 #define LINKSPEED_1GBPS         1000
1132 #define LINKSPEED_100MBPS       100
1133 #define LINKSPEED_10MBPS        10
1134
1135 #define LINKSPEED_ENCODED_10MBPS        0
1136 #define LINKSPEED_ENCODED_100MBPS       1
1137 #define LINKSPEED_ENCODED_1GBPS         2
1138
1139 #define LINKEVENT_AUTONEG_DISABLED      0
1140 #define LINKEVENT_AUTONEG_ENABLED       1
1141
1142 #define LINKEVENT_HALF_DUPLEX           0
1143 #define LINKEVENT_FULL_DUPLEX           1
1144
1145 #define LINKEVENT_LINKSPEED_MBPS        0
1146 #define LINKEVENT_LINKSPEED_ENCODED     1
1147
1148 /* firmware response header:
1149  *      63:58 - message type
1150  *      57:56 - owner
1151  *      55:53 - desc count
1152  *      52:48 - reserved
1153  *      47:40 - completion id
1154  *      39:32 - opcode
1155  *      31:16 - error code
1156  *      15:00 - reserved
1157  */
1158 #define netxen_get_nic_msgtype(msg_hdr) \
1159         ((msg_hdr >> 58) & 0x3F)
1160 #define netxen_get_nic_msg_compid(msg_hdr)      \
1161         ((msg_hdr >> 40) & 0xFF)
1162 #define netxen_get_nic_msg_opcode(msg_hdr)      \
1163         ((msg_hdr >> 32) & 0xFF)
1164 #define netxen_get_nic_msg_errcode(msg_hdr)     \
1165         ((msg_hdr >> 16) & 0xFFFF)
1166
1167 typedef struct {
1168         union {
1169                 struct {
1170                         u64 hdr;
1171                         u64 body[7];
1172                 };
1173                 u64 words[8];
1174         };
1175 } nx_fw_msg_t;
1176
1177 typedef struct {
1178         __le64 qhdr;
1179         __le64 req_hdr;
1180         __le64 words[6];
1181 } nx_nic_req_t;
1182
1183 typedef struct {
1184         u8 op;
1185         u8 tag;
1186         u8 mac_addr[6];
1187 } nx_mac_req_t;
1188
1189 #define MAX_PENDING_DESC_BLOCK_SIZE     64
1190
1191 #define NETXEN_NIC_MSI_ENABLED          0x02
1192 #define NETXEN_NIC_MSIX_ENABLED         0x04
1193 #define NETXEN_IS_MSI_FAMILY(adapter) \
1194         ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1195
1196 #define MSIX_ENTRIES_PER_ADAPTER        NUM_STS_DESC_RINGS
1197 #define NETXEN_MSIX_TBL_SPACE           8192
1198 #define NETXEN_PCI_REG_MSIX_TBL         0x44
1199
1200 #define NETXEN_DB_MAPSIZE_BYTES         0x1000
1201
1202 #define NETXEN_NETDEV_WEIGHT 128
1203 #define NETXEN_ADAPTER_UP_MAGIC 777
1204 #define NETXEN_NIC_PEG_TUNE 0
1205
1206 struct netxen_dummy_dma {
1207         void *addr;
1208         dma_addr_t phys_addr;
1209 };
1210
1211 struct netxen_adapter {
1212         struct netxen_hardware_context ahw;
1213
1214         struct net_device *netdev;
1215         struct pci_dev *pdev;
1216         struct list_head mac_list;
1217
1218         u32 curr_window;
1219         u32 crb_win;
1220         rwlock_t adapter_lock;
1221
1222         spinlock_t tx_clean_lock;
1223
1224         u16 num_txd;
1225         u16 num_rxd;
1226         u16 num_jumbo_rxd;
1227         u16 num_lro_rxd;
1228
1229         u8 max_rds_rings;
1230         u8 max_sds_rings;
1231         u8 driver_mismatch;
1232         u8 msix_supported;
1233         u8 rx_csum;
1234         u8 pci_using_dac;
1235         u8 portnum;
1236         u8 physical_port;
1237
1238         u8 mc_enabled;
1239         u8 max_mc_count;
1240         u8 rss_supported;
1241         u8 resv2;
1242         u32 resv3;
1243
1244         u8 has_link_events;
1245         u8 fw_type;
1246         u16 tx_context_id;
1247         u16 mtu;
1248         u16 is_up;
1249
1250         u16 link_speed;
1251         u16 link_duplex;
1252         u16 link_autoneg;
1253         u16 module_type;
1254
1255         u32 capabilities;
1256         u32 flags;
1257         u32 irq;
1258         u32 temp;
1259
1260         u32 msi_tgt_status;
1261         u32 resv4;
1262
1263         struct netxen_adapter_stats stats;
1264
1265         struct netxen_recv_context recv_ctx;
1266         struct nx_host_tx_ring *tx_ring;
1267
1268         int (*enable_phy_interrupts) (struct netxen_adapter *);
1269         int (*disable_phy_interrupts) (struct netxen_adapter *);
1270         int (*macaddr_set) (struct netxen_adapter *, u8 *);
1271         int (*set_mtu) (struct netxen_adapter *, int);
1272         int (*set_promisc) (struct netxen_adapter *, u32);
1273         void (*set_multi) (struct net_device *);
1274         int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1275         int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1276         int (*init_port) (struct netxen_adapter *, int);
1277         int (*stop_port) (struct netxen_adapter *);
1278
1279         u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1280         int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1281         int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1282         int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1283         int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1284         u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1285         unsigned long (*pci_set_window)(struct netxen_adapter *,
1286                         unsigned long long);
1287
1288         struct netxen_legacy_intr_set legacy_intr;
1289
1290         struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1291
1292         struct netxen_dummy_dma dummy_dma;
1293
1294         struct work_struct watchdog_task;
1295         struct timer_list watchdog_timer;
1296         struct work_struct  tx_timeout_task;
1297
1298         struct net_device_stats net_stats;
1299
1300         nx_nic_intr_coalesce_t coal;
1301
1302         u32 fw_major;
1303         u32 fw_version;
1304         const struct firmware *fw;
1305 };
1306
1307 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1308 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1309 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1310 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1311 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1312                             __u32 * readval);
1313 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1314                              long reg, __u32 val);
1315
1316 /* Functions available from netxen_nic_hw.c */
1317 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1318 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1319
1320 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1321 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr);
1322
1323 #define NXRD32(adapter, off) \
1324         (adapter->hw_read_wx(adapter, off))
1325 #define NXWR32(adapter, off, val) \
1326         (adapter->hw_write_wx(adapter, off, val))
1327
1328 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1329 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1330 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1331
1332 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1333 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1334                 ulong off, u32 data);
1335 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1336                 u64 off, void *data, int size);
1337 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1338                 u64 off, void *data, int size);
1339 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1340                 u64 off, u32 data);
1341 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1342 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1343                 u64 off, u32 data);
1344 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1345 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1346                 unsigned long long addr);
1347 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1348                 u32 wndw);
1349
1350 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1351 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1352                 ulong off, u32 data);
1353 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1354                 u64 off, void *data, int size);
1355 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1356                 u64 off, void *data, int size);
1357 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1358                 u64 off, u32 data);
1359 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1360 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1361                 u64 off, u32 data);
1362 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1363 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1364                 unsigned long long addr);
1365
1366 /* Functions from netxen_nic_init.c */
1367 int netxen_init_dummy_dma(struct netxen_adapter *adapter);
1368 void netxen_free_dummy_dma(struct netxen_adapter *adapter);
1369
1370 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1371 int netxen_load_firmware(struct netxen_adapter *adapter);
1372 int netxen_need_fw_reset(struct netxen_adapter *adapter);
1373 void netxen_request_firmware(struct netxen_adapter *adapter);
1374 void netxen_release_firmware(struct netxen_adapter *adapter);
1375 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1376
1377 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1378 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1379                                 u8 *bytes, size_t size);
1380 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1381                                 u8 *bytes, size_t size);
1382 int netxen_flash_unlock(struct netxen_adapter *adapter);
1383 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1384 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1385 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1386 void netxen_halt_pegs(struct netxen_adapter *adapter);
1387
1388 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1389
1390 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1391 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1392
1393 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1394 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1395
1396 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1397 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1398
1399 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1400 int netxen_init_firmware(struct netxen_adapter *adapter);
1401 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1402 void netxen_watchdog_task(struct work_struct *work);
1403 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1404                 struct nx_host_rds_ring *rds_ring);
1405 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1406 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1407 void netxen_p2_nic_set_multi(struct net_device *netdev);
1408 void netxen_p3_nic_set_multi(struct net_device *netdev);
1409 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1410 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1411 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1412 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1413 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd);
1414 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1415 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1416
1417 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1418 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1419
1420 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1421 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1422
1423 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1424                 struct nx_host_tx_ring *tx_ring);
1425
1426 /*
1427  * NetXen Board information
1428  */
1429
1430 #define NETXEN_MAX_SHORT_NAME 32
1431 struct netxen_brdinfo {
1432         int brdtype;    /* type of board */
1433         long ports;             /* max no of physical ports */
1434         char short_name[NETXEN_MAX_SHORT_NAME];
1435 };
1436
1437 static const struct netxen_brdinfo netxen_boards[] = {
1438         {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1439         {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1440         {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1441         {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1442         {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1443         {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1444         {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1445         {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1446         {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1447         {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1448         {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1449         {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1450         {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1451         {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1452         {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1453         {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1454         {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1455         {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1456         {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1457 };
1458
1459 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1460
1461 static inline void get_brd_name_by_type(u32 type, char *name)
1462 {
1463         int i, found = 0;
1464         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1465                 if (netxen_boards[i].brdtype == type) {
1466                         strcpy(name, netxen_boards[i].short_name);
1467                         found = 1;
1468                         break;
1469                 }
1470
1471         }
1472         if (!found)
1473                 name = "Unknown";
1474 }
1475
1476 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring)
1477 {
1478         smp_mb();
1479         return find_diff_among(tx_ring->producer,
1480                         tx_ring->sw_consumer, tx_ring->num_desc);
1481
1482 }
1483
1484 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1485 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1486 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1487 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1488                                 int *valp);
1489
1490 extern struct ethtool_ops netxen_nic_ethtool_ops;
1491
1492 #endif                          /* __NETXEN_NIC_H_ */