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hwmon: (max6650) Add support for alarms
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33 #include "netxen_nic_phan_reg.h"
34
35 #include <linux/firmware.h>
36 #include <net/ip.h>
37
38 #define MASK(n) ((1ULL<<(n))-1)
39 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
40 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
41 #define MS_WIN(addr) (addr & 0x0ffc0000)
42
43 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
44
45 #define CRB_BLK(off) ((off >> 20) & 0x3f)
46 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
47 #define CRB_WINDOW_2M (0x130060)
48 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
49 #define CRB_INDIRECT_2M (0x1e0000UL)
50
51 #define CRB_WIN_LOCK_TIMEOUT 100000000
52 static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
53 {{{0, 0, 0, 0} } }, /* 0: PCI */
54 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
55 {1, 0x0110000, 0x0120000, 0x130000},
56 {1, 0x0120000, 0x0122000, 0x124000},
57 {1, 0x0130000, 0x0132000, 0x126000},
58 {1, 0x0140000, 0x0142000, 0x128000},
59 {1, 0x0150000, 0x0152000, 0x12a000},
60 {1, 0x0160000, 0x0170000, 0x110000},
61 {1, 0x0170000, 0x0172000, 0x12e000},
62 {0, 0x0000000, 0x0000000, 0x000000},
63 {0, 0x0000000, 0x0000000, 0x000000},
64 {0, 0x0000000, 0x0000000, 0x000000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {1, 0x01e0000, 0x01e0800, 0x122000},
69 {0, 0x0000000, 0x0000000, 0x000000} } },
70 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
71 {{{0, 0, 0, 0} } }, /* 3: */
72 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
73 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
74 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
75 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
76 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
77 {0, 0x0000000, 0x0000000, 0x000000},
78 {0, 0x0000000, 0x0000000, 0x000000},
79 {0, 0x0000000, 0x0000000, 0x000000},
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {1, 0x08f0000, 0x08f2000, 0x172000} } },
92 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {0, 0x0000000, 0x0000000, 0x000000},
95 {0, 0x0000000, 0x0000000, 0x000000},
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x09f0000, 0x09f2000, 0x176000} } },
108 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {0, 0x0000000, 0x0000000, 0x000000},
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
124 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
140 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
141 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
142 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
143 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
144 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
145 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
146 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
147 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
148 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
149 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
150 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
151 {{{0, 0, 0, 0} } }, /* 23: */
152 {{{0, 0, 0, 0} } }, /* 24: */
153 {{{0, 0, 0, 0} } }, /* 25: */
154 {{{0, 0, 0, 0} } }, /* 26: */
155 {{{0, 0, 0, 0} } }, /* 27: */
156 {{{0, 0, 0, 0} } }, /* 28: */
157 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
158 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
159 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
160 {{{0} } }, /* 32: PCI */
161 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
162 {1, 0x2110000, 0x2120000, 0x130000},
163 {1, 0x2120000, 0x2122000, 0x124000},
164 {1, 0x2130000, 0x2132000, 0x126000},
165 {1, 0x2140000, 0x2142000, 0x128000},
166 {1, 0x2150000, 0x2152000, 0x12a000},
167 {1, 0x2160000, 0x2170000, 0x110000},
168 {1, 0x2170000, 0x2172000, 0x12e000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000} } },
177 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
178 {{{0} } }, /* 35: */
179 {{{0} } }, /* 36: */
180 {{{0} } }, /* 37: */
181 {{{0} } }, /* 38: */
182 {{{0} } }, /* 39: */
183 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
184 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
185 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
186 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
187 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
188 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
189 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
190 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
191 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
192 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
193 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
194 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
195 {{{0} } }, /* 52: */
196 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
197 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
198 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
199 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
200 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
201 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
202 {{{0} } }, /* 59: I2C0 */
203 {{{0} } }, /* 60: I2C1 */
204 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
205 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
206 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
207 };
208
209 /*
210 * top 12 bits of crb internal address (hub, agent)
211 */
212 static unsigned crb_hub_agt[64] =
213 {
214 0,
215 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
216 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
217 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
218 0,
219 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
220 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
221 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
223 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
224 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
226 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
227 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
228 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
229 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
230 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
231 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
233 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
241 0,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
243 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
246 0,
247 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
248 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
249 0,
250 0,
251 0,
252 0,
253 0,
254 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
255 0,
256 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
257 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
258 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
263 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
264 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
265 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
266 0,
267 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
268 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
269 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
270 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
271 0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
273 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
275 0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
277 0,
278 };
279
280 /* PCI Windowing for DDR regions. */
281
282 #define ADDR_IN_RANGE(addr, low, high) \
283 (((addr) <= (high)) && ((addr) >= (low)))
284
285 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
286
287 #define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
288 #define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
289 #define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
290 #define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
291
292 #define NETXEN_NIC_WINDOW_MARGIN 0x100000
293
294 int netxen_nic_set_mac(struct net_device *netdev, void *p)
295 {
296 struct netxen_adapter *adapter = netdev_priv(netdev);
297 struct sockaddr *addr = p;
298
299 if (netif_running(netdev))
300 return -EBUSY;
301
302 if (!is_valid_ether_addr(addr->sa_data))
303 return -EADDRNOTAVAIL;
304
305 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
306
307 /* For P3, MAC addr is not set in NIU */
308 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
309 if (adapter->macaddr_set)
310 adapter->macaddr_set(adapter, addr->sa_data);
311
312 return 0;
313 }
314
315 #define NETXEN_UNICAST_ADDR(port, index) \
316 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
317 #define NETXEN_MCAST_ADDR(port, index) \
318 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
319 #define MAC_HI(addr) \
320 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
321 #define MAC_LO(addr) \
322 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
323
324 static int
325 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
326 {
327 u32 val = 0;
328 u16 port = adapter->physical_port;
329 u8 *addr = adapter->netdev->dev_addr;
330
331 if (adapter->mc_enabled)
332 return 0;
333
334 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
335 val |= (1UL << (28+port));
336 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
337
338 /* add broadcast addr to filter */
339 val = 0xffffff;
340 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
341 netxen_crb_writelit_adapter(adapter,
342 NETXEN_UNICAST_ADDR(port, 0)+4, val);
343
344 /* add station addr to filter */
345 val = MAC_HI(addr);
346 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
347 val = MAC_LO(addr);
348 netxen_crb_writelit_adapter(adapter,
349 NETXEN_UNICAST_ADDR(port, 1)+4, val);
350
351 adapter->mc_enabled = 1;
352 return 0;
353 }
354
355 static int
356 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
357 {
358 u32 val = 0;
359 u16 port = adapter->physical_port;
360 u8 *addr = adapter->netdev->dev_addr;
361
362 if (!adapter->mc_enabled)
363 return 0;
364
365 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
366 val &= ~(1UL << (28+port));
367 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
368
369 val = MAC_HI(addr);
370 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
371 val = MAC_LO(addr);
372 netxen_crb_writelit_adapter(adapter,
373 NETXEN_UNICAST_ADDR(port, 0)+4, val);
374
375 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
376 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
377
378 adapter->mc_enabled = 0;
379 return 0;
380 }
381
382 static int
383 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
384 int index, u8 *addr)
385 {
386 u32 hi = 0, lo = 0;
387 u16 port = adapter->physical_port;
388
389 lo = MAC_LO(addr);
390 hi = MAC_HI(addr);
391
392 netxen_crb_writelit_adapter(adapter,
393 NETXEN_MCAST_ADDR(port, index), hi);
394 netxen_crb_writelit_adapter(adapter,
395 NETXEN_MCAST_ADDR(port, index)+4, lo);
396
397 return 0;
398 }
399
400 void netxen_p2_nic_set_multi(struct net_device *netdev)
401 {
402 struct netxen_adapter *adapter = netdev_priv(netdev);
403 struct dev_mc_list *mc_ptr;
404 u8 null_addr[6];
405 int index = 0;
406
407 memset(null_addr, 0, 6);
408
409 if (netdev->flags & IFF_PROMISC) {
410
411 adapter->set_promisc(adapter,
412 NETXEN_NIU_PROMISC_MODE);
413
414 /* Full promiscuous mode */
415 netxen_nic_disable_mcast_filter(adapter);
416
417 return;
418 }
419
420 if (netdev->mc_count == 0) {
421 adapter->set_promisc(adapter,
422 NETXEN_NIU_NON_PROMISC_MODE);
423 netxen_nic_disable_mcast_filter(adapter);
424 return;
425 }
426
427 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
428 if (netdev->flags & IFF_ALLMULTI ||
429 netdev->mc_count > adapter->max_mc_count) {
430 netxen_nic_disable_mcast_filter(adapter);
431 return;
432 }
433
434 netxen_nic_enable_mcast_filter(adapter);
435
436 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
437 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
438
439 if (index != netdev->mc_count)
440 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
441 netxen_nic_driver_name, netdev->name);
442
443 /* Clear out remaining addresses */
444 for (; index < adapter->max_mc_count; index++)
445 netxen_nic_set_mcast_addr(adapter, index, null_addr);
446 }
447
448 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
449 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
450 {
451 nx_mac_list_t *cur, *prev;
452
453 /* if in del_list, move it to adapter->mac_list */
454 for (cur = *del_list, prev = NULL; cur;) {
455 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
456 if (prev == NULL)
457 *del_list = cur->next;
458 else
459 prev->next = cur->next;
460 cur->next = adapter->mac_list;
461 adapter->mac_list = cur;
462 return 0;
463 }
464 prev = cur;
465 cur = cur->next;
466 }
467
468 /* make sure to add each mac address only once */
469 for (cur = adapter->mac_list; cur; cur = cur->next) {
470 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
471 return 0;
472 }
473 /* not in del_list, create new entry and add to add_list */
474 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
475 if (cur == NULL) {
476 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
477 "not work properly from now.\n", __func__);
478 return -1;
479 }
480
481 memcpy(cur->mac_addr, addr, ETH_ALEN);
482 cur->next = *add_list;
483 *add_list = cur;
484 return 0;
485 }
486
487 static int
488 netxen_send_cmd_descs(struct netxen_adapter *adapter,
489 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
490 {
491 uint32_t i, producer;
492 struct netxen_cmd_buffer *pbuf;
493 struct cmd_desc_type0 *cmd_desc;
494
495 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
496 printk(KERN_WARNING "%s: Too many command descriptors in a "
497 "request\n", __func__);
498 return -EINVAL;
499 }
500
501 i = 0;
502
503 netif_tx_lock_bh(adapter->netdev);
504
505 producer = adapter->cmd_producer;
506 do {
507 cmd_desc = &cmd_desc_arr[i];
508
509 pbuf = &adapter->cmd_buf_arr[producer];
510 pbuf->skb = NULL;
511 pbuf->frag_count = 0;
512
513 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
514 memcpy(&adapter->ahw.cmd_desc_head[producer],
515 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
516
517 producer = get_next_index(producer,
518 adapter->num_txd);
519 i++;
520
521 } while (i != nr_elements);
522
523 adapter->cmd_producer = producer;
524
525 /* write producer index to start the xmit */
526
527 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
528
529 netif_tx_unlock_bh(adapter->netdev);
530
531 return 0;
532 }
533
534 static int nx_p3_sre_macaddr_change(struct net_device *dev,
535 u8 *addr, unsigned op)
536 {
537 struct netxen_adapter *adapter = netdev_priv(dev);
538 nx_nic_req_t req;
539 nx_mac_req_t *mac_req;
540 u64 word;
541 int rv;
542
543 memset(&req, 0, sizeof(nx_nic_req_t));
544 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
545
546 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
547 req.req_hdr = cpu_to_le64(word);
548
549 mac_req = (nx_mac_req_t *)&req.words[0];
550 mac_req->op = op;
551 memcpy(mac_req->mac_addr, addr, 6);
552
553 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
554 if (rv != 0) {
555 printk(KERN_ERR "ERROR. Could not send mac update\n");
556 return rv;
557 }
558
559 return 0;
560 }
561
562 void netxen_p3_nic_set_multi(struct net_device *netdev)
563 {
564 struct netxen_adapter *adapter = netdev_priv(netdev);
565 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
566 struct dev_mc_list *mc_ptr;
567 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
568 u32 mode = VPORT_MISS_MODE_DROP;
569
570 del_list = adapter->mac_list;
571 adapter->mac_list = NULL;
572
573 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
574 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
575
576 if (netdev->flags & IFF_PROMISC) {
577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
578 goto send_fw_cmd;
579 }
580
581 if ((netdev->flags & IFF_ALLMULTI) ||
582 (netdev->mc_count > adapter->max_mc_count)) {
583 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
584 goto send_fw_cmd;
585 }
586
587 if (netdev->mc_count > 0) {
588 for (mc_ptr = netdev->mc_list; mc_ptr;
589 mc_ptr = mc_ptr->next) {
590 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
591 &add_list, &del_list);
592 }
593 }
594
595 send_fw_cmd:
596 adapter->set_promisc(adapter, mode);
597 for (cur = del_list; cur;) {
598 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
599 next = cur->next;
600 kfree(cur);
601 cur = next;
602 }
603 for (cur = add_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
605 next = cur->next;
606 cur->next = adapter->mac_list;
607 adapter->mac_list = cur;
608 cur = next;
609 }
610 }
611
612 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
613 {
614 nx_nic_req_t req;
615 u64 word;
616
617 memset(&req, 0, sizeof(nx_nic_req_t));
618
619 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
620
621 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
622 ((u64)adapter->portnum << 16);
623 req.req_hdr = cpu_to_le64(word);
624
625 req.words[0] = cpu_to_le64(mode);
626
627 return netxen_send_cmd_descs(adapter,
628 (struct cmd_desc_type0 *)&req, 1);
629 }
630
631 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
632 {
633 nx_mac_list_t *cur, *next;
634
635 cur = adapter->mac_list;
636
637 while (cur) {
638 next = cur->next;
639 kfree(cur);
640 cur = next;
641 }
642 }
643
644 #define NETXEN_CONFIG_INTR_COALESCE 3
645
646 /*
647 * Send the interrupt coalescing parameter set by ethtool to the card.
648 */
649 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
650 {
651 nx_nic_req_t req;
652 u64 word;
653 int rv;
654
655 memset(&req, 0, sizeof(nx_nic_req_t));
656
657 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
658
659 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
660 req.req_hdr = cpu_to_le64(word);
661
662 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
663
664 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
665 if (rv != 0) {
666 printk(KERN_ERR "ERROR. Could not send "
667 "interrupt coalescing parameters\n");
668 }
669
670 return rv;
671 }
672
673 #define RSS_HASHTYPE_IP_TCP 0x3
674
675 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
676 {
677 nx_nic_req_t req;
678 u64 word;
679 int i, rv;
680
681 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
682 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
683 0x255b0ec26d5a56daULL };
684
685
686 memset(&req, 0, sizeof(nx_nic_req_t));
687 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
688
689 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
690 req.req_hdr = cpu_to_le64(word);
691
692 /*
693 * RSS request:
694 * bits 3-0: hash_method
695 * 5-4: hash_type_ipv4
696 * 7-6: hash_type_ipv6
697 * 8: enable
698 * 9: use indirection table
699 * 47-10: reserved
700 * 63-48: indirection table mask
701 */
702 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
703 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
704 ((u64)(enable & 0x1) << 8) |
705 ((0x7ULL) << 48);
706 req.words[0] = cpu_to_le64(word);
707 for (i = 0; i < 5; i++)
708 req.words[i+1] = cpu_to_le64(key[i]);
709
710
711 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
712 if (rv != 0) {
713 printk(KERN_ERR "%s: could not configure RSS\n",
714 adapter->netdev->name);
715 }
716
717 return rv;
718 }
719
720 /*
721 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
722 * @returns 0 on success, negative on failure
723 */
724
725 #define MTU_FUDGE_FACTOR 100
726
727 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
728 {
729 struct netxen_adapter *adapter = netdev_priv(netdev);
730 int max_mtu;
731 int rc = 0;
732
733 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
734 max_mtu = P3_MAX_MTU;
735 else
736 max_mtu = P2_MAX_MTU;
737
738 if (mtu > max_mtu) {
739 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
740 netdev->name, max_mtu);
741 return -EINVAL;
742 }
743
744 if (adapter->set_mtu)
745 rc = adapter->set_mtu(adapter, mtu);
746
747 if (!rc)
748 netdev->mtu = mtu;
749
750 return rc;
751 }
752
753 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
754 int size, __le32 * buf)
755 {
756 int i, v, addr;
757 __le32 *ptr32;
758
759 addr = base;
760 ptr32 = buf;
761 for (i = 0; i < size / sizeof(u32); i++) {
762 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
763 return -1;
764 *ptr32 = cpu_to_le32(v);
765 ptr32++;
766 addr += sizeof(u32);
767 }
768 if ((char *)buf + size > (char *)ptr32) {
769 __le32 local;
770 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
771 return -1;
772 local = cpu_to_le32(v);
773 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
774 }
775
776 return 0;
777 }
778
779 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
780 {
781 __le32 *pmac = (__le32 *) mac;
782 u32 offset;
783
784 offset = NETXEN_USER_START +
785 offsetof(struct netxen_new_user_info, mac_addr) +
786 adapter->portnum * sizeof(u64);
787
788 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
789 return -1;
790
791 if (*mac == cpu_to_le64(~0ULL)) {
792
793 offset = NETXEN_USER_START_OLD +
794 offsetof(struct netxen_user_old_info, mac_addr) +
795 adapter->portnum * sizeof(u64);
796
797 if (netxen_get_flash_block(adapter,
798 offset, sizeof(u64), pmac) == -1)
799 return -1;
800
801 if (*mac == cpu_to_le64(~0ULL))
802 return -1;
803 }
804 return 0;
805 }
806
807 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
808 {
809 uint32_t crbaddr, mac_hi, mac_lo;
810 int pci_func = adapter->ahw.pci_func;
811
812 crbaddr = CRB_MAC_BLOCK_START +
813 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
814
815 adapter->hw_read_wx(adapter, crbaddr, &mac_lo, 4);
816 adapter->hw_read_wx(adapter, crbaddr+4, &mac_hi, 4);
817
818 if (pci_func & 1)
819 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
820 else
821 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
822
823 return 0;
824 }
825
826 #define CRB_WIN_LOCK_TIMEOUT 100000000
827
828 static int crb_win_lock(struct netxen_adapter *adapter)
829 {
830 int done = 0, timeout = 0;
831
832 while (!done) {
833 /* acquire semaphore3 from PCI HW block */
834 adapter->hw_read_wx(adapter,
835 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
836 if (done == 1)
837 break;
838 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
839 return -1;
840 timeout++;
841 udelay(1);
842 }
843 netxen_crb_writelit_adapter(adapter,
844 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
845 return 0;
846 }
847
848 static void crb_win_unlock(struct netxen_adapter *adapter)
849 {
850 int val;
851
852 adapter->hw_read_wx(adapter,
853 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
854 }
855
856 /*
857 * Changes the CRB window to the specified window.
858 */
859 void
860 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
861 {
862 void __iomem *offset;
863 u32 tmp;
864 int count = 0;
865 uint8_t func = adapter->ahw.pci_func;
866
867 if (adapter->curr_window == wndw)
868 return;
869 /*
870 * Move the CRB window.
871 * We need to write to the "direct access" region of PCI
872 * to avoid a race condition where the window register has
873 * not been successfully written across CRB before the target
874 * register address is received by PCI. The direct region bypasses
875 * the CRB bus.
876 */
877 offset = PCI_OFFSET_SECOND_RANGE(adapter,
878 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
879
880 if (wndw & 0x1)
881 wndw = NETXEN_WINDOW_ONE;
882
883 writel(wndw, offset);
884
885 /* MUST make sure window is set before we forge on... */
886 while ((tmp = readl(offset)) != wndw) {
887 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
888 "registered properly: 0x%08x.\n",
889 netxen_nic_driver_name, __func__, tmp);
890 mdelay(1);
891 if (count >= 10)
892 break;
893 count++;
894 }
895
896 if (wndw == NETXEN_WINDOW_ONE)
897 adapter->curr_window = 1;
898 else
899 adapter->curr_window = 0;
900 }
901
902 /*
903 * Return -1 if off is not valid,
904 * 1 if window access is needed. 'off' is set to offset from
905 * CRB space in 128M pci map
906 * 0 if no window access is needed. 'off' is set to 2M addr
907 * In: 'off' is offset from base in 128M pci map
908 */
909 static int
910 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
911 ulong *off, int len)
912 {
913 unsigned long end = *off + len;
914 crb_128M_2M_sub_block_map_t *m;
915
916
917 if (*off >= NETXEN_CRB_MAX)
918 return -1;
919
920 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
921 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
922 (ulong)adapter->ahw.pci_base0;
923 return 0;
924 }
925
926 if (*off < NETXEN_PCI_CRBSPACE)
927 return -1;
928
929 *off -= NETXEN_PCI_CRBSPACE;
930 end = *off + len;
931
932 /*
933 * Try direct map
934 */
935 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
936
937 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
938 *off = *off + m->start_2M - m->start_128M +
939 (ulong)adapter->ahw.pci_base0;
940 return 0;
941 }
942
943 /*
944 * Not in direct map, use crb window
945 */
946 return 1;
947 }
948
949 /*
950 * In: 'off' is offset from CRB space in 128M pci map
951 * Out: 'off' is 2M pci map addr
952 * side effect: lock crb window
953 */
954 static void
955 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
956 {
957 u32 win_read;
958
959 adapter->crb_win = CRB_HI(*off);
960 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
961 /*
962 * Read back value to make sure write has gone through before trying
963 * to use it.
964 */
965 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
966 if (win_read != adapter->crb_win) {
967 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
968 "Read crbwin (0x%x), off=0x%lx\n",
969 __func__, adapter->crb_win, win_read, *off);
970 }
971 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
972 (ulong)adapter->ahw.pci_base0;
973 }
974
975 static int
976 netxen_do_load_firmware(struct netxen_adapter *adapter, const char *fwname,
977 const struct firmware *fw)
978 {
979 u64 *ptr64;
980 u32 i, flashaddr, size;
981 struct pci_dev *pdev = adapter->pdev;
982
983 if (fw)
984 dev_info(&pdev->dev, "loading firmware from file %s\n", fwname);
985 else
986 dev_info(&pdev->dev, "loading firmware from flash\n");
987
988 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
989 adapter->pci_write_normalize(adapter,
990 NETXEN_ROMUSB_GLB_CAS_RST, 1);
991
992 if (fw) {
993 __le64 data;
994
995 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 8;
996
997 ptr64 = (u64 *)&fw->data[NETXEN_BOOTLD_START];
998 flashaddr = NETXEN_BOOTLD_START;
999
1000 for (i = 0; i < size; i++) {
1001 data = cpu_to_le64(ptr64[i]);
1002 adapter->pci_mem_write(adapter, flashaddr, &data, 8);
1003 flashaddr += 8;
1004 }
1005
1006 size = *(u32 *)&fw->data[NX_FW_SIZE_OFFSET];
1007 size = (__force u32)cpu_to_le32(size) / 8;
1008
1009 ptr64 = (u64 *)&fw->data[NETXEN_IMAGE_START];
1010 flashaddr = NETXEN_IMAGE_START;
1011
1012 for (i = 0; i < size; i++) {
1013 data = cpu_to_le64(ptr64[i]);
1014
1015 if (adapter->pci_mem_write(adapter,
1016 flashaddr, &data, 8))
1017 return -EIO;
1018
1019 flashaddr += 8;
1020 }
1021 } else {
1022 u32 data;
1023
1024 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START) / 4;
1025 flashaddr = NETXEN_BOOTLD_START;
1026
1027 for (i = 0; i < size; i++) {
1028 if (netxen_rom_fast_read(adapter,
1029 flashaddr, (int *)&data) != 0)
1030 return -EIO;
1031
1032 if (adapter->pci_mem_write(adapter,
1033 flashaddr, &data, 4))
1034 return -EIO;
1035
1036 flashaddr += 4;
1037 }
1038 }
1039 msleep(1);
1040
1041 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1042 adapter->pci_write_normalize(adapter,
1043 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
1044 else {
1045 adapter->pci_write_normalize(adapter,
1046 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
1047 adapter->pci_write_normalize(adapter,
1048 NETXEN_ROMUSB_GLB_CAS_RST, 0);
1049 }
1050
1051 return 0;
1052 }
1053
1054 static int
1055 netxen_validate_firmware(struct netxen_adapter *adapter, const char *fwname,
1056 const struct firmware *fw)
1057 {
1058 __le32 val;
1059 u32 major, minor, build, ver, min_ver, bios;
1060 struct pci_dev *pdev = adapter->pdev;
1061
1062 if (fw->size < NX_FW_MIN_SIZE)
1063 return -EINVAL;
1064
1065 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_MAGIC_OFFSET]);
1066 if ((__force u32)val != NETXEN_BDINFO_MAGIC)
1067 return -EINVAL;
1068
1069 val = cpu_to_le32(*(u32 *)&fw->data[NX_FW_VERSION_OFFSET]);
1070 major = (__force u32)val & 0xff;
1071 minor = ((__force u32)val >> 8) & 0xff;
1072 build = (__force u32)val >> 16;
1073
1074 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
1075 min_ver = NETXEN_VERSION_CODE(4, 0, 216);
1076 else
1077 min_ver = NETXEN_VERSION_CODE(3, 4, 216);
1078
1079 ver = NETXEN_VERSION_CODE(major, minor, build);
1080
1081 if ((major > _NETXEN_NIC_LINUX_MAJOR) || (ver < min_ver)) {
1082 dev_err(&pdev->dev,
1083 "%s: firmware version %d.%d.%d unsupported\n",
1084 fwname, major, minor, build);
1085 return -EINVAL;
1086 }
1087
1088 val = cpu_to_le32(*(u32 *)&fw->data[NX_BIOS_VERSION_OFFSET]);
1089 netxen_rom_fast_read(adapter, NX_BIOS_VERSION_OFFSET, (int *)&bios);
1090 if ((__force u32)val != bios) {
1091 dev_err(&pdev->dev, "%s: firmware bios is incompatible\n",
1092 fwname);
1093 return -EINVAL;
1094 }
1095
1096 /* check if flashed firmware is newer */
1097 if (netxen_rom_fast_read(adapter,
1098 NX_FW_VERSION_OFFSET, (int *)&val))
1099 return -EIO;
1100 major = (__force u32)val & 0xff;
1101 minor = ((__force u32)val >> 8) & 0xff;
1102 build = (__force u32)val >> 16;
1103 if (NETXEN_VERSION_CODE(major, minor, build) > ver)
1104 return -EINVAL;
1105
1106 netxen_nic_reg_write(adapter, NETXEN_CAM_RAM(0x1fc),
1107 NETXEN_BDINFO_MAGIC);
1108 return 0;
1109 }
1110
1111 static char *fw_name[] = { "nxromimg.bin", "nx3fwct.bin", "nx3fwmn.bin" };
1112
1113 int netxen_load_firmware(struct netxen_adapter *adapter)
1114 {
1115 u32 capability, flashed_ver;
1116 const struct firmware *fw;
1117 int fw_type;
1118 struct pci_dev *pdev = adapter->pdev;
1119 int rc = 0;
1120
1121 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1122 fw_type = NX_P2_MN_ROMIMAGE;
1123 goto request_fw;
1124 } else {
1125 fw_type = NX_P3_CT_ROMIMAGE;
1126 goto request_fw;
1127 }
1128
1129 request_mn:
1130 capability = 0;
1131
1132 netxen_rom_fast_read(adapter,
1133 NX_FW_VERSION_OFFSET, (int *)&flashed_ver);
1134 if (flashed_ver >= NETXEN_VERSION_CODE(4, 0, 220)) {
1135 adapter->hw_read_wx(adapter,
1136 NX_PEG_TUNE_CAPABILITY, &capability, 4);
1137 if (capability & NX_PEG_TUNE_MN_PRESENT) {
1138 fw_type = NX_P3_MN_ROMIMAGE;
1139 goto request_fw;
1140 }
1141 }
1142
1143 request_fw:
1144 rc = request_firmware(&fw, fw_name[fw_type], &pdev->dev);
1145 if (rc != 0) {
1146 if (fw_type == NX_P3_CT_ROMIMAGE) {
1147 msleep(1);
1148 goto request_mn;
1149 }
1150
1151 fw = NULL;
1152 goto load_fw;
1153 }
1154
1155 rc = netxen_validate_firmware(adapter, fw_name[fw_type], fw);
1156 if (rc != 0) {
1157 release_firmware(fw);
1158
1159 if (fw_type == NX_P3_CT_ROMIMAGE) {
1160 msleep(1);
1161 goto request_mn;
1162 }
1163
1164 fw = NULL;
1165 }
1166
1167 load_fw:
1168 rc = netxen_do_load_firmware(adapter, fw_name[fw_type], fw);
1169
1170 if (fw)
1171 release_firmware(fw);
1172 return rc;
1173 }
1174
1175 int
1176 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1177 ulong off, void *data, int len)
1178 {
1179 void __iomem *addr;
1180
1181 BUG_ON(len != 4);
1182
1183 if (ADDR_IN_WINDOW1(off)) {
1184 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1185 } else { /* Window 0 */
1186 addr = pci_base_offset(adapter, off);
1187 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1188 }
1189
1190 if (!addr) {
1191 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1192 return 1;
1193 }
1194
1195 writel(*(u32 *) data, addr);
1196
1197 if (!ADDR_IN_WINDOW1(off))
1198 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1199
1200 return 0;
1201 }
1202
1203 int
1204 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
1205 ulong off, void *data, int len)
1206 {
1207 void __iomem *addr;
1208
1209 BUG_ON(len != 4);
1210
1211 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1212 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1213 } else { /* Window 0 */
1214 addr = pci_base_offset(adapter, off);
1215 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1216 }
1217
1218 if (!addr) {
1219 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1220 return 1;
1221 }
1222
1223 *(u32 *)data = readl(addr);
1224
1225 if (!ADDR_IN_WINDOW1(off))
1226 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1227
1228 return 0;
1229 }
1230
1231 int
1232 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1233 ulong off, void *data, int len)
1234 {
1235 unsigned long flags = 0;
1236 int rv;
1237
1238 BUG_ON(len != 4);
1239
1240 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1241
1242 if (rv == -1) {
1243 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1244 __func__, off);
1245 dump_stack();
1246 return -1;
1247 }
1248
1249 if (rv == 1) {
1250 write_lock_irqsave(&adapter->adapter_lock, flags);
1251 crb_win_lock(adapter);
1252 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1253 writel(*(uint32_t *)data, (void __iomem *)off);
1254 crb_win_unlock(adapter);
1255 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1256 } else
1257 writel(*(uint32_t *)data, (void __iomem *)off);
1258
1259
1260 return 0;
1261 }
1262
1263 int
1264 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1265 ulong off, void *data, int len)
1266 {
1267 unsigned long flags = 0;
1268 int rv;
1269
1270 BUG_ON(len != 4);
1271
1272 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1273
1274 if (rv == -1) {
1275 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1276 __func__, off);
1277 dump_stack();
1278 return -1;
1279 }
1280
1281 if (rv == 1) {
1282 write_lock_irqsave(&adapter->adapter_lock, flags);
1283 crb_win_lock(adapter);
1284 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1285 *(uint32_t *)data = readl((void __iomem *)off);
1286 crb_win_unlock(adapter);
1287 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1288 } else
1289 *(uint32_t *)data = readl((void __iomem *)off);
1290
1291 return 0;
1292 }
1293
1294 void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
1295 {
1296 adapter->hw_write_wx(adapter, off, &val, 4);
1297 }
1298
1299 int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
1300 {
1301 int val;
1302 adapter->hw_read_wx(adapter, off, &val, 4);
1303 return val;
1304 }
1305
1306 /* Change the window to 0, write and change back to window 1. */
1307 void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1308 {
1309 adapter->hw_write_wx(adapter, index, &value, 4);
1310 }
1311
1312 /* Change the window to 0, read and change back to window 1. */
1313 void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
1314 {
1315 adapter->hw_read_wx(adapter, index, value, 4);
1316 }
1317
1318 void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1319 {
1320 adapter->hw_write_wx(adapter, index, &value, 4);
1321 }
1322
1323 void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1324 {
1325 adapter->hw_read_wx(adapter, index, value, 4);
1326 }
1327
1328 /*
1329 * check memory access boundary.
1330 * used by test agent. support ddr access only for now
1331 */
1332 static unsigned long
1333 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1334 unsigned long long addr, int size)
1335 {
1336 if (!ADDR_IN_RANGE(addr,
1337 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1338 !ADDR_IN_RANGE(addr+size-1,
1339 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1340 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1341 return 0;
1342 }
1343
1344 return 1;
1345 }
1346
1347 static int netxen_pci_set_window_warning_count;
1348
1349 unsigned long
1350 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1351 unsigned long long addr)
1352 {
1353 void __iomem *offset;
1354 int window;
1355 unsigned long long qdr_max;
1356 uint8_t func = adapter->ahw.pci_func;
1357
1358 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1359 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1360 } else {
1361 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1362 }
1363
1364 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1365 /* DDR network side */
1366 addr -= NETXEN_ADDR_DDR_NET;
1367 window = (addr >> 25) & 0x3ff;
1368 if (adapter->ahw.ddr_mn_window != window) {
1369 adapter->ahw.ddr_mn_window = window;
1370 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1371 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1372 writel(window, offset);
1373 /* MUST make sure window is set before we forge on... */
1374 readl(offset);
1375 }
1376 addr -= (window * NETXEN_WINDOW_ONE);
1377 addr += NETXEN_PCI_DDR_NET;
1378 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1379 addr -= NETXEN_ADDR_OCM0;
1380 addr += NETXEN_PCI_OCM0;
1381 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1382 addr -= NETXEN_ADDR_OCM1;
1383 addr += NETXEN_PCI_OCM1;
1384 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1385 /* QDR network side */
1386 addr -= NETXEN_ADDR_QDR_NET;
1387 window = (addr >> 22) & 0x3f;
1388 if (adapter->ahw.qdr_sn_window != window) {
1389 adapter->ahw.qdr_sn_window = window;
1390 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1391 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1392 writel((window << 22), offset);
1393 /* MUST make sure window is set before we forge on... */
1394 readl(offset);
1395 }
1396 addr -= (window * 0x400000);
1397 addr += NETXEN_PCI_QDR_NET;
1398 } else {
1399 /*
1400 * peg gdb frequently accesses memory that doesn't exist,
1401 * this limits the chit chat so debugging isn't slowed down.
1402 */
1403 if ((netxen_pci_set_window_warning_count++ < 8)
1404 || (netxen_pci_set_window_warning_count % 64 == 0))
1405 printk("%s: Warning:netxen_nic_pci_set_window()"
1406 " Unknown address range!\n",
1407 netxen_nic_driver_name);
1408 addr = -1UL;
1409 }
1410 return addr;
1411 }
1412
1413 /*
1414 * Note : only 32-bit writes!
1415 */
1416 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1417 u64 off, u32 data)
1418 {
1419 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1420 return 0;
1421 }
1422
1423 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1424 {
1425 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1426 }
1427
1428 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1429 u64 off, u32 data)
1430 {
1431 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1432 }
1433
1434 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1435 {
1436 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1437 }
1438
1439 unsigned long
1440 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1441 unsigned long long addr)
1442 {
1443 int window;
1444 u32 win_read;
1445
1446 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1447 /* DDR network side */
1448 window = MN_WIN(addr);
1449 adapter->ahw.ddr_mn_window = window;
1450 adapter->hw_write_wx(adapter,
1451 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1452 &window, 4);
1453 adapter->hw_read_wx(adapter,
1454 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1455 &win_read, 4);
1456 if ((win_read << 17) != window) {
1457 printk(KERN_INFO "Written MNwin (0x%x) != "
1458 "Read MNwin (0x%x)\n", window, win_read);
1459 }
1460 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1461 } else if (ADDR_IN_RANGE(addr,
1462 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1463 if ((addr & 0x00ff800) == 0xff800) {
1464 printk("%s: QM access not handled.\n", __func__);
1465 addr = -1UL;
1466 }
1467
1468 window = OCM_WIN(addr);
1469 adapter->ahw.ddr_mn_window = window;
1470 adapter->hw_write_wx(adapter,
1471 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1472 &window, 4);
1473 adapter->hw_read_wx(adapter,
1474 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1475 &win_read, 4);
1476 if ((win_read >> 7) != window) {
1477 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1478 "Read OCMwin (0x%x)\n",
1479 __func__, window, win_read);
1480 }
1481 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1482
1483 } else if (ADDR_IN_RANGE(addr,
1484 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1485 /* QDR network side */
1486 window = MS_WIN(addr);
1487 adapter->ahw.qdr_sn_window = window;
1488 adapter->hw_write_wx(adapter,
1489 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1490 &window, 4);
1491 adapter->hw_read_wx(adapter,
1492 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1493 &win_read, 4);
1494 if (win_read != window) {
1495 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1496 "Read MSwin (0x%x)\n",
1497 __func__, window, win_read);
1498 }
1499 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1500
1501 } else {
1502 /*
1503 * peg gdb frequently accesses memory that doesn't exist,
1504 * this limits the chit chat so debugging isn't slowed down.
1505 */
1506 if ((netxen_pci_set_window_warning_count++ < 8)
1507 || (netxen_pci_set_window_warning_count%64 == 0)) {
1508 printk("%s: Warning:%s Unknown address range!\n",
1509 __func__, netxen_nic_driver_name);
1510 }
1511 addr = -1UL;
1512 }
1513 return addr;
1514 }
1515
1516 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1517 unsigned long long addr)
1518 {
1519 int window;
1520 unsigned long long qdr_max;
1521
1522 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1523 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1524 else
1525 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1526
1527 if (ADDR_IN_RANGE(addr,
1528 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1529 /* DDR network side */
1530 BUG(); /* MN access can not come here */
1531 } else if (ADDR_IN_RANGE(addr,
1532 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1533 return 1;
1534 } else if (ADDR_IN_RANGE(addr,
1535 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1536 return 1;
1537 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1538 /* QDR network side */
1539 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1540 if (adapter->ahw.qdr_sn_window == window)
1541 return 1;
1542 }
1543
1544 return 0;
1545 }
1546
1547 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1548 u64 off, void *data, int size)
1549 {
1550 unsigned long flags;
1551 void __iomem *addr, *mem_ptr = NULL;
1552 int ret = 0;
1553 u64 start;
1554 unsigned long mem_base;
1555 unsigned long mem_page;
1556
1557 write_lock_irqsave(&adapter->adapter_lock, flags);
1558
1559 /*
1560 * If attempting to access unknown address or straddle hw windows,
1561 * do not access.
1562 */
1563 start = adapter->pci_set_window(adapter, off);
1564 if ((start == -1UL) ||
1565 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1566 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1567 printk(KERN_ERR "%s out of bound pci memory access. "
1568 "offset is 0x%llx\n", netxen_nic_driver_name,
1569 (unsigned long long)off);
1570 return -1;
1571 }
1572
1573 addr = pci_base_offset(adapter, start);
1574 if (!addr) {
1575 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1576 mem_base = pci_resource_start(adapter->pdev, 0);
1577 mem_page = start & PAGE_MASK;
1578 /* Map two pages whenever user tries to access addresses in two
1579 consecutive pages.
1580 */
1581 if (mem_page != ((start + size - 1) & PAGE_MASK))
1582 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1583 else
1584 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1585 if (mem_ptr == NULL) {
1586 *(uint8_t *)data = 0;
1587 return -1;
1588 }
1589 addr = mem_ptr;
1590 addr += start & (PAGE_SIZE - 1);
1591 write_lock_irqsave(&adapter->adapter_lock, flags);
1592 }
1593
1594 switch (size) {
1595 case 1:
1596 *(uint8_t *)data = readb(addr);
1597 break;
1598 case 2:
1599 *(uint16_t *)data = readw(addr);
1600 break;
1601 case 4:
1602 *(uint32_t *)data = readl(addr);
1603 break;
1604 case 8:
1605 *(uint64_t *)data = readq(addr);
1606 break;
1607 default:
1608 ret = -1;
1609 break;
1610 }
1611 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1612
1613 if (mem_ptr)
1614 iounmap(mem_ptr);
1615 return ret;
1616 }
1617
1618 static int
1619 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1620 void *data, int size)
1621 {
1622 unsigned long flags;
1623 void __iomem *addr, *mem_ptr = NULL;
1624 int ret = 0;
1625 u64 start;
1626 unsigned long mem_base;
1627 unsigned long mem_page;
1628
1629 write_lock_irqsave(&adapter->adapter_lock, flags);
1630
1631 /*
1632 * If attempting to access unknown address or straddle hw windows,
1633 * do not access.
1634 */
1635 start = adapter->pci_set_window(adapter, off);
1636 if ((start == -1UL) ||
1637 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1638 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1639 printk(KERN_ERR "%s out of bound pci memory access. "
1640 "offset is 0x%llx\n", netxen_nic_driver_name,
1641 (unsigned long long)off);
1642 return -1;
1643 }
1644
1645 addr = pci_base_offset(adapter, start);
1646 if (!addr) {
1647 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1648 mem_base = pci_resource_start(adapter->pdev, 0);
1649 mem_page = start & PAGE_MASK;
1650 /* Map two pages whenever user tries to access addresses in two
1651 * consecutive pages.
1652 */
1653 if (mem_page != ((start + size - 1) & PAGE_MASK))
1654 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1655 else
1656 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1657 if (mem_ptr == NULL)
1658 return -1;
1659 addr = mem_ptr;
1660 addr += start & (PAGE_SIZE - 1);
1661 write_lock_irqsave(&adapter->adapter_lock, flags);
1662 }
1663
1664 switch (size) {
1665 case 1:
1666 writeb(*(uint8_t *)data, addr);
1667 break;
1668 case 2:
1669 writew(*(uint16_t *)data, addr);
1670 break;
1671 case 4:
1672 writel(*(uint32_t *)data, addr);
1673 break;
1674 case 8:
1675 writeq(*(uint64_t *)data, addr);
1676 break;
1677 default:
1678 ret = -1;
1679 break;
1680 }
1681 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1682 if (mem_ptr)
1683 iounmap(mem_ptr);
1684 return ret;
1685 }
1686
1687 #define MAX_CTL_CHECK 1000
1688
1689 int
1690 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1691 u64 off, void *data, int size)
1692 {
1693 unsigned long flags;
1694 int i, j, ret = 0, loop, sz[2], off0;
1695 uint32_t temp;
1696 uint64_t off8, tmpw, word[2] = {0, 0};
1697 void __iomem *mem_crb;
1698
1699 /*
1700 * If not MN, go check for MS or invalid.
1701 */
1702 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1703 return netxen_nic_pci_mem_write_direct(adapter,
1704 off, data, size);
1705
1706 off8 = off & 0xfffffff8;
1707 off0 = off & 0x7;
1708 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1709 sz[1] = size - sz[0];
1710 loop = ((off0 + size - 1) >> 3) + 1;
1711 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1712
1713 if ((size != 8) || (off0 != 0)) {
1714 for (i = 0; i < loop; i++) {
1715 if (adapter->pci_mem_read(adapter,
1716 off8 + (i << 3), &word[i], 8))
1717 return -1;
1718 }
1719 }
1720
1721 switch (size) {
1722 case 1:
1723 tmpw = *((uint8_t *)data);
1724 break;
1725 case 2:
1726 tmpw = *((uint16_t *)data);
1727 break;
1728 case 4:
1729 tmpw = *((uint32_t *)data);
1730 break;
1731 case 8:
1732 default:
1733 tmpw = *((uint64_t *)data);
1734 break;
1735 }
1736 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1737 word[0] |= tmpw << (off0 * 8);
1738
1739 if (loop == 2) {
1740 word[1] &= ~(~0ULL << (sz[1] * 8));
1741 word[1] |= tmpw >> (sz[0] * 8);
1742 }
1743
1744 write_lock_irqsave(&adapter->adapter_lock, flags);
1745 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1746
1747 for (i = 0; i < loop; i++) {
1748 writel((uint32_t)(off8 + (i << 3)),
1749 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1750 writel(0,
1751 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1752 writel(word[i] & 0xffffffff,
1753 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1754 writel((word[i] >> 32) & 0xffffffff,
1755 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1756 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1757 (mem_crb+MIU_TEST_AGT_CTRL));
1758 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1759 (mem_crb+MIU_TEST_AGT_CTRL));
1760
1761 for (j = 0; j < MAX_CTL_CHECK; j++) {
1762 temp = readl(
1763 (mem_crb+MIU_TEST_AGT_CTRL));
1764 if ((temp & MIU_TA_CTL_BUSY) == 0)
1765 break;
1766 }
1767
1768 if (j >= MAX_CTL_CHECK) {
1769 if (printk_ratelimit())
1770 dev_err(&adapter->pdev->dev,
1771 "failed to write through agent\n");
1772 ret = -1;
1773 break;
1774 }
1775 }
1776
1777 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1778 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1779 return ret;
1780 }
1781
1782 int
1783 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1784 u64 off, void *data, int size)
1785 {
1786 unsigned long flags;
1787 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1788 uint32_t temp;
1789 uint64_t off8, val, word[2] = {0, 0};
1790 void __iomem *mem_crb;
1791
1792
1793 /*
1794 * If not MN, go check for MS or invalid.
1795 */
1796 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1797 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1798
1799 off8 = off & 0xfffffff8;
1800 off0[0] = off & 0x7;
1801 off0[1] = 0;
1802 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1803 sz[1] = size - sz[0];
1804 loop = ((off0[0] + size - 1) >> 3) + 1;
1805 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1806
1807 write_lock_irqsave(&adapter->adapter_lock, flags);
1808 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1809
1810 for (i = 0; i < loop; i++) {
1811 writel((uint32_t)(off8 + (i << 3)),
1812 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1813 writel(0,
1814 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1815 writel(MIU_TA_CTL_ENABLE,
1816 (mem_crb+MIU_TEST_AGT_CTRL));
1817 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1818 (mem_crb+MIU_TEST_AGT_CTRL));
1819
1820 for (j = 0; j < MAX_CTL_CHECK; j++) {
1821 temp = readl(
1822 (mem_crb+MIU_TEST_AGT_CTRL));
1823 if ((temp & MIU_TA_CTL_BUSY) == 0)
1824 break;
1825 }
1826
1827 if (j >= MAX_CTL_CHECK) {
1828 if (printk_ratelimit())
1829 dev_err(&adapter->pdev->dev,
1830 "failed to read through agent\n");
1831 break;
1832 }
1833
1834 start = off0[i] >> 2;
1835 end = (off0[i] + sz[i] - 1) >> 2;
1836 for (k = start; k <= end; k++) {
1837 word[i] |= ((uint64_t) readl(
1838 (mem_crb +
1839 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1840 }
1841 }
1842
1843 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1844 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1845
1846 if (j >= MAX_CTL_CHECK)
1847 return -1;
1848
1849 if (sz[0] == 8) {
1850 val = word[0];
1851 } else {
1852 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1853 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1854 }
1855
1856 switch (size) {
1857 case 1:
1858 *(uint8_t *)data = val;
1859 break;
1860 case 2:
1861 *(uint16_t *)data = val;
1862 break;
1863 case 4:
1864 *(uint32_t *)data = val;
1865 break;
1866 case 8:
1867 *(uint64_t *)data = val;
1868 break;
1869 }
1870 return 0;
1871 }
1872
1873 int
1874 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1875 u64 off, void *data, int size)
1876 {
1877 int i, j, ret = 0, loop, sz[2], off0;
1878 uint32_t temp;
1879 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1880
1881 /*
1882 * If not MN, go check for MS or invalid.
1883 */
1884 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1885 mem_crb = NETXEN_CRB_QDR_NET;
1886 else {
1887 mem_crb = NETXEN_CRB_DDR_NET;
1888 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1889 return netxen_nic_pci_mem_write_direct(adapter,
1890 off, data, size);
1891 }
1892
1893 off8 = off & 0xfffffff8;
1894 off0 = off & 0x7;
1895 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1896 sz[1] = size - sz[0];
1897 loop = ((off0 + size - 1) >> 3) + 1;
1898
1899 if ((size != 8) || (off0 != 0)) {
1900 for (i = 0; i < loop; i++) {
1901 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1902 &word[i], 8))
1903 return -1;
1904 }
1905 }
1906
1907 switch (size) {
1908 case 1:
1909 tmpw = *((uint8_t *)data);
1910 break;
1911 case 2:
1912 tmpw = *((uint16_t *)data);
1913 break;
1914 case 4:
1915 tmpw = *((uint32_t *)data);
1916 break;
1917 case 8:
1918 default:
1919 tmpw = *((uint64_t *)data);
1920 break;
1921 }
1922
1923 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1924 word[0] |= tmpw << (off0 * 8);
1925
1926 if (loop == 2) {
1927 word[1] &= ~(~0ULL << (sz[1] * 8));
1928 word[1] |= tmpw >> (sz[0] * 8);
1929 }
1930
1931 /*
1932 * don't lock here - write_wx gets the lock if each time
1933 * write_lock_irqsave(&adapter->adapter_lock, flags);
1934 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1935 */
1936
1937 for (i = 0; i < loop; i++) {
1938 temp = off8 + (i << 3);
1939 adapter->hw_write_wx(adapter,
1940 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1941 temp = 0;
1942 adapter->hw_write_wx(adapter,
1943 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1944 temp = word[i] & 0xffffffff;
1945 adapter->hw_write_wx(adapter,
1946 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1947 temp = (word[i] >> 32) & 0xffffffff;
1948 adapter->hw_write_wx(adapter,
1949 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1950 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1951 adapter->hw_write_wx(adapter,
1952 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1953 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1954 adapter->hw_write_wx(adapter,
1955 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1956
1957 for (j = 0; j < MAX_CTL_CHECK; j++) {
1958 adapter->hw_read_wx(adapter,
1959 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1960 if ((temp & MIU_TA_CTL_BUSY) == 0)
1961 break;
1962 }
1963
1964 if (j >= MAX_CTL_CHECK) {
1965 if (printk_ratelimit())
1966 dev_err(&adapter->pdev->dev,
1967 "failed to write through agent\n");
1968 ret = -1;
1969 break;
1970 }
1971 }
1972
1973 /*
1974 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1975 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1976 */
1977 return ret;
1978 }
1979
1980 int
1981 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1982 u64 off, void *data, int size)
1983 {
1984 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1985 uint32_t temp;
1986 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1987
1988 /*
1989 * If not MN, go check for MS or invalid.
1990 */
1991
1992 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1993 mem_crb = NETXEN_CRB_QDR_NET;
1994 else {
1995 mem_crb = NETXEN_CRB_DDR_NET;
1996 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1997 return netxen_nic_pci_mem_read_direct(adapter,
1998 off, data, size);
1999 }
2000
2001 off8 = off & 0xfffffff8;
2002 off0[0] = off & 0x7;
2003 off0[1] = 0;
2004 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
2005 sz[1] = size - sz[0];
2006 loop = ((off0[0] + size - 1) >> 3) + 1;
2007
2008 /*
2009 * don't lock here - write_wx gets the lock if each time
2010 * write_lock_irqsave(&adapter->adapter_lock, flags);
2011 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
2012 */
2013
2014 for (i = 0; i < loop; i++) {
2015 temp = off8 + (i << 3);
2016 adapter->hw_write_wx(adapter,
2017 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
2018 temp = 0;
2019 adapter->hw_write_wx(adapter,
2020 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
2021 temp = MIU_TA_CTL_ENABLE;
2022 adapter->hw_write_wx(adapter,
2023 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2024 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
2025 adapter->hw_write_wx(adapter,
2026 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2027
2028 for (j = 0; j < MAX_CTL_CHECK; j++) {
2029 adapter->hw_read_wx(adapter,
2030 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
2031 if ((temp & MIU_TA_CTL_BUSY) == 0)
2032 break;
2033 }
2034
2035 if (j >= MAX_CTL_CHECK) {
2036 if (printk_ratelimit())
2037 dev_err(&adapter->pdev->dev,
2038 "failed to read through agent\n");
2039 break;
2040 }
2041
2042 start = off0[i] >> 2;
2043 end = (off0[i] + sz[i] - 1) >> 2;
2044 for (k = start; k <= end; k++) {
2045 adapter->hw_read_wx(adapter,
2046 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
2047 word[i] |= ((uint64_t)temp << (32 * k));
2048 }
2049 }
2050
2051 /*
2052 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
2053 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
2054 */
2055
2056 if (j >= MAX_CTL_CHECK)
2057 return -1;
2058
2059 if (sz[0] == 8) {
2060 val = word[0];
2061 } else {
2062 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
2063 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
2064 }
2065
2066 switch (size) {
2067 case 1:
2068 *(uint8_t *)data = val;
2069 break;
2070 case 2:
2071 *(uint16_t *)data = val;
2072 break;
2073 case 4:
2074 *(uint32_t *)data = val;
2075 break;
2076 case 8:
2077 *(uint64_t *)data = val;
2078 break;
2079 }
2080 return 0;
2081 }
2082
2083 /*
2084 * Note : only 32-bit writes!
2085 */
2086 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
2087 u64 off, u32 data)
2088 {
2089 adapter->hw_write_wx(adapter, off, &data, 4);
2090
2091 return 0;
2092 }
2093
2094 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
2095 {
2096 u32 temp;
2097 adapter->hw_read_wx(adapter, off, &temp, 4);
2098 return temp;
2099 }
2100
2101 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
2102 u64 off, u32 data)
2103 {
2104 adapter->hw_write_wx(adapter, off, &data, 4);
2105 }
2106
2107 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
2108 {
2109 u32 temp;
2110 adapter->hw_read_wx(adapter, off, &temp, 4);
2111 return temp;
2112 }
2113
2114 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
2115 {
2116 int offset, board_type, magic, header_version;
2117 struct pci_dev *pdev = adapter->pdev;
2118
2119 offset = NETXEN_BRDCFG_START +
2120 offsetof(struct netxen_board_info, magic);
2121 if (netxen_rom_fast_read(adapter, offset, &magic))
2122 return -EIO;
2123
2124 offset = NETXEN_BRDCFG_START +
2125 offsetof(struct netxen_board_info, header_version);
2126 if (netxen_rom_fast_read(adapter, offset, &header_version))
2127 return -EIO;
2128
2129 if (magic != NETXEN_BDINFO_MAGIC ||
2130 header_version != NETXEN_BDINFO_VERSION) {
2131 dev_err(&pdev->dev,
2132 "invalid board config, magic=%08x, version=%08x\n",
2133 magic, header_version);
2134 return -EIO;
2135 }
2136
2137 offset = NETXEN_BRDCFG_START +
2138 offsetof(struct netxen_board_info, board_type);
2139 if (netxen_rom_fast_read(adapter, offset, &board_type))
2140 return -EIO;
2141
2142 adapter->ahw.board_type = board_type;
2143
2144 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
2145 u32 gpio = netxen_nic_reg_read(adapter,
2146 NETXEN_ROMUSB_GLB_PAD_GPIO_I);
2147 if ((gpio & 0x8000) == 0)
2148 board_type = NETXEN_BRDTYPE_P3_10G_TP;
2149 }
2150
2151 switch ((netxen_brdtype_t)board_type) {
2152 case NETXEN_BRDTYPE_P2_SB35_4G:
2153 adapter->ahw.port_type = NETXEN_NIC_GBE;
2154 break;
2155 case NETXEN_BRDTYPE_P2_SB31_10G:
2156 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2157 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2158 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
2159 case NETXEN_BRDTYPE_P3_HMEZ:
2160 case NETXEN_BRDTYPE_P3_XG_LOM:
2161 case NETXEN_BRDTYPE_P3_10G_CX4:
2162 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2163 case NETXEN_BRDTYPE_P3_IMEZ:
2164 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
2165 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2166 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
2167 case NETXEN_BRDTYPE_P3_10G_XFP:
2168 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2169 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2170 break;
2171 case NETXEN_BRDTYPE_P1_BD:
2172 case NETXEN_BRDTYPE_P1_SB:
2173 case NETXEN_BRDTYPE_P1_SMAX:
2174 case NETXEN_BRDTYPE_P1_SOCK:
2175 case NETXEN_BRDTYPE_P3_REF_QG:
2176 case NETXEN_BRDTYPE_P3_4_GB:
2177 case NETXEN_BRDTYPE_P3_4_GB_MM:
2178 adapter->ahw.port_type = NETXEN_NIC_GBE;
2179 break;
2180 case NETXEN_BRDTYPE_P3_10G_TP:
2181 adapter->ahw.port_type = (adapter->portnum < 2) ?
2182 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
2183 break;
2184 default:
2185 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
2186 adapter->ahw.port_type = NETXEN_NIC_XGBE;
2187 break;
2188 }
2189
2190 return 0;
2191 }
2192
2193 /* NIU access sections */
2194
2195 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
2196 {
2197 new_mtu += MTU_FUDGE_FACTOR;
2198 netxen_nic_write_w0(adapter,
2199 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2200 new_mtu);
2201 return 0;
2202 }
2203
2204 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
2205 {
2206 new_mtu += MTU_FUDGE_FACTOR;
2207 if (adapter->physical_port == 0)
2208 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
2209 new_mtu);
2210 else
2211 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2212 new_mtu);
2213 return 0;
2214 }
2215
2216 void
2217 netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2218 unsigned long off, int data)
2219 {
2220 adapter->hw_write_wx(adapter, off, &data, 4);
2221 }
2222
2223 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
2224 {
2225 __u32 status;
2226 __u32 autoneg;
2227 __u32 port_mode;
2228
2229 if (!netif_carrier_ok(adapter->netdev)) {
2230 adapter->link_speed = 0;
2231 adapter->link_duplex = -1;
2232 adapter->link_autoneg = AUTONEG_ENABLE;
2233 return;
2234 }
2235
2236 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
2237 adapter->hw_read_wx(adapter,
2238 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2239 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2240 adapter->link_speed = SPEED_1000;
2241 adapter->link_duplex = DUPLEX_FULL;
2242 adapter->link_autoneg = AUTONEG_DISABLE;
2243 return;
2244 }
2245
2246 if (adapter->phy_read
2247 && adapter->phy_read(adapter,
2248 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2249 &status) == 0) {
2250 if (netxen_get_phy_link(status)) {
2251 switch (netxen_get_phy_speed(status)) {
2252 case 0:
2253 adapter->link_speed = SPEED_10;
2254 break;
2255 case 1:
2256 adapter->link_speed = SPEED_100;
2257 break;
2258 case 2:
2259 adapter->link_speed = SPEED_1000;
2260 break;
2261 default:
2262 adapter->link_speed = 0;
2263 break;
2264 }
2265 switch (netxen_get_phy_duplex(status)) {
2266 case 0:
2267 adapter->link_duplex = DUPLEX_HALF;
2268 break;
2269 case 1:
2270 adapter->link_duplex = DUPLEX_FULL;
2271 break;
2272 default:
2273 adapter->link_duplex = -1;
2274 break;
2275 }
2276 if (adapter->phy_read
2277 && adapter->phy_read(adapter,
2278 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2279 &autoneg) != 0)
2280 adapter->link_autoneg = autoneg;
2281 } else
2282 goto link_down;
2283 } else {
2284 link_down:
2285 adapter->link_speed = 0;
2286 adapter->link_duplex = -1;
2287 }
2288 }
2289 }
2290
2291 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2292 {
2293 u32 fw_major, fw_minor, fw_build;
2294 char brd_name[NETXEN_MAX_SHORT_NAME];
2295 char serial_num[32];
2296 int i, addr, val;
2297 int *ptr32;
2298 struct pci_dev *pdev = adapter->pdev;
2299
2300 adapter->driver_mismatch = 0;
2301
2302 ptr32 = (int *)&serial_num;
2303 addr = NETXEN_USER_START +
2304 offsetof(struct netxen_new_user_info, serial_num);
2305 for (i = 0; i < 8; i++) {
2306 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2307 dev_err(&pdev->dev, "error reading board info\n");
2308 adapter->driver_mismatch = 1;
2309 return;
2310 }
2311 ptr32[i] = cpu_to_le32(val);
2312 addr += sizeof(u32);
2313 }
2314
2315 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2316 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2317 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
2318
2319 adapter->fw_major = fw_major;
2320 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2321
2322 if (adapter->portnum == 0) {
2323 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2324
2325 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2326 brd_name, serial_num, adapter->ahw.revision_id);
2327 }
2328
2329 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2330 adapter->driver_mismatch = 1;
2331 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2332 fw_major, fw_minor, fw_build);
2333 return;
2334 }
2335
2336 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2337 fw_major, fw_minor, fw_build);
2338
2339 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2340 adapter->hw_read_wx(adapter,
2341 NETXEN_MIU_MN_CONTROL, &i, 4);
2342 adapter->ahw.cut_through = (i & 0x4) ? 1 : 0;
2343 dev_info(&pdev->dev, "firmware running in %s mode\n",
2344 adapter->ahw.cut_through ? "cut-through" : "legacy");
2345 }
2346 }
2347
2348 int
2349 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2350 {
2351 u32 wol_cfg;
2352
2353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2354 return 0;
2355
2356 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG_NV);
2357 if (wol_cfg & (1UL << adapter->portnum)) {
2358 wol_cfg = netxen_nic_reg_read(adapter, NETXEN_WOL_CONFIG);
2359 if (wol_cfg & (1 << adapter->portnum))
2360 return 1;
2361 }
2362
2363 return 0;
2364 }
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