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net: convert multiple drivers to use netdev_for_each_mc_addr, part5 V2
[deliverable/linux.git] / drivers / net / netxen / netxen_nic_hw.c
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
19 * MA 02111-1307, USA.
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called "COPYING".
23 *
24 */
25
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
28
29 #include <net/ip.h>
30
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define OCM_WIN_P3P(addr) (addr & 0xffc0000)
35 #define MS_WIN(addr) (addr & 0x0ffc0000)
36
37 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
38
39 #define CRB_BLK(off) ((off >> 20) & 0x3f)
40 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
41 #define CRB_WINDOW_2M (0x130060)
42 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
43 #define CRB_INDIRECT_2M (0x1e0000UL)
44
45 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
46 void __iomem *addr, u32 data);
47 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
48 void __iomem *addr);
49
50 #ifndef readq
51 static inline u64 readq(void __iomem *addr)
52 {
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54 }
55 #endif
56
57 #ifndef writeq
58 static inline void writeq(u64 val, void __iomem *addr)
59 {
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62 }
63 #endif
64
65 #define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
67
68 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74
75 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
76 unsigned long off)
77 {
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
86
87 return NULL;
88 }
89
90 static crb_128M_2M_block_map_t
91 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
92 {{{0, 0, 0, 0} } }, /* 0: PCI */
93 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
94 {1, 0x0110000, 0x0120000, 0x130000},
95 {1, 0x0120000, 0x0122000, 0x124000},
96 {1, 0x0130000, 0x0132000, 0x126000},
97 {1, 0x0140000, 0x0142000, 0x128000},
98 {1, 0x0150000, 0x0152000, 0x12a000},
99 {1, 0x0160000, 0x0170000, 0x110000},
100 {1, 0x0170000, 0x0172000, 0x12e000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {1, 0x01e0000, 0x01e0800, 0x122000},
108 {0, 0x0000000, 0x0000000, 0x000000} } },
109 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
110 {{{0, 0, 0, 0} } }, /* 3: */
111 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
112 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
113 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
114 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
115 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {1, 0x08f0000, 0x08f2000, 0x172000} } },
131 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {1, 0x09f0000, 0x09f2000, 0x176000} } },
147 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
163 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
179 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
180 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
181 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
182 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
183 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
184 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
185 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
186 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
187 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
188 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
189 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
190 {{{0, 0, 0, 0} } }, /* 23: */
191 {{{0, 0, 0, 0} } }, /* 24: */
192 {{{0, 0, 0, 0} } }, /* 25: */
193 {{{0, 0, 0, 0} } }, /* 26: */
194 {{{0, 0, 0, 0} } }, /* 27: */
195 {{{0, 0, 0, 0} } }, /* 28: */
196 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
197 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
198 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
199 {{{0} } }, /* 32: PCI */
200 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
201 {1, 0x2110000, 0x2120000, 0x130000},
202 {1, 0x2120000, 0x2122000, 0x124000},
203 {1, 0x2130000, 0x2132000, 0x126000},
204 {1, 0x2140000, 0x2142000, 0x128000},
205 {1, 0x2150000, 0x2152000, 0x12a000},
206 {1, 0x2160000, 0x2170000, 0x110000},
207 {1, 0x2170000, 0x2172000, 0x12e000},
208 {0, 0x0000000, 0x0000000, 0x000000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000} } },
216 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
217 {{{0} } }, /* 35: */
218 {{{0} } }, /* 36: */
219 {{{0} } }, /* 37: */
220 {{{0} } }, /* 38: */
221 {{{0} } }, /* 39: */
222 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
223 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
224 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
225 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
226 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
227 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
228 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
229 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
230 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
231 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
232 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
233 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
234 {{{0} } }, /* 52: */
235 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
236 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
237 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
238 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
239 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
240 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
241 {{{0} } }, /* 59: I2C0 */
242 {{{0} } }, /* 60: I2C1 */
243 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
244 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
245 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
246 };
247
248 /*
249 * top 12 bits of crb internal address (hub, agent)
250 */
251 static unsigned crb_hub_agt[64] =
252 {
253 0,
254 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
255 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
257 0,
258 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
259 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
260 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
261 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
265 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
266 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
267 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
268 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
269 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
270 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
280 0,
281 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
282 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
283 0,
284 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
285 0,
286 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
287 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
288 0,
289 0,
290 0,
291 0,
292 0,
293 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
294 0,
295 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
302 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
303 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
304 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
305 0,
306 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
309 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
310 0,
311 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
312 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
314 0,
315 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
316 0,
317 };
318
319 /* PCI Windowing for DDR regions. */
320
321 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
322
323 #define NETXEN_PCIE_SEM_TIMEOUT 10000
324
325 int
326 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
327 {
328 int done = 0, timeout = 0;
329
330 while (!done) {
331 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
332 if (done == 1)
333 break;
334 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
335 return -EIO;
336 msleep(1);
337 }
338
339 if (id_reg)
340 NXWR32(adapter, id_reg, adapter->portnum);
341
342 return 0;
343 }
344
345 void
346 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
347 {
348 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
349 }
350
351 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
352 {
353 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
354 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
355 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
356 }
357
358 return 0;
359 }
360
361 /* Disable an XG interface */
362 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
363 {
364 __u32 mac_cfg;
365 u32 port = adapter->physical_port;
366
367 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
368 return 0;
369
370 if (port > NETXEN_NIU_MAX_XG_PORTS)
371 return -EINVAL;
372
373 mac_cfg = 0;
374 if (NXWR32(adapter,
375 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
376 return -EIO;
377 return 0;
378 }
379
380 #define NETXEN_UNICAST_ADDR(port, index) \
381 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
382 #define NETXEN_MCAST_ADDR(port, index) \
383 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
384 #define MAC_HI(addr) \
385 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
386 #define MAC_LO(addr) \
387 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
388
389 int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
390 {
391 u32 mac_cfg;
392 u32 cnt = 0;
393 __u32 reg = 0x0200;
394 u32 port = adapter->physical_port;
395 u16 board_type = adapter->ahw.board_type;
396
397 if (port > NETXEN_NIU_MAX_XG_PORTS)
398 return -EINVAL;
399
400 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
401 mac_cfg &= ~0x4;
402 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
403
404 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
405 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
406 reg = (0x20 << port);
407
408 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
409
410 mdelay(10);
411
412 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
413 mdelay(10);
414
415 if (cnt < 20) {
416
417 reg = NXRD32(adapter,
418 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
419
420 if (mode == NETXEN_NIU_PROMISC_MODE)
421 reg = (reg | 0x2000UL);
422 else
423 reg = (reg & ~0x2000UL);
424
425 if (mode == NETXEN_NIU_ALLMULTI_MODE)
426 reg = (reg | 0x1000UL);
427 else
428 reg = (reg & ~0x1000UL);
429
430 NXWR32(adapter,
431 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
432 }
433
434 mac_cfg |= 0x4;
435 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
436
437 return 0;
438 }
439
440 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
441 {
442 u32 mac_hi, mac_lo;
443 u32 reg_hi, reg_lo;
444
445 u8 phy = adapter->physical_port;
446
447 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
448 return -EINVAL;
449
450 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
451 mac_hi = addr[2] | ((u32)addr[3] << 8) |
452 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
453
454 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
455 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
456
457 /* write twice to flush */
458 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
459 return -EIO;
460 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
461 return -EIO;
462
463 return 0;
464 }
465
466 static int
467 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
468 {
469 u32 val = 0;
470 u16 port = adapter->physical_port;
471 u8 *addr = adapter->mac_addr;
472
473 if (adapter->mc_enabled)
474 return 0;
475
476 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
477 val |= (1UL << (28+port));
478 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
479
480 /* add broadcast addr to filter */
481 val = 0xffffff;
482 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
483 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
484
485 /* add station addr to filter */
486 val = MAC_HI(addr);
487 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
488 val = MAC_LO(addr);
489 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
490
491 adapter->mc_enabled = 1;
492 return 0;
493 }
494
495 static int
496 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
497 {
498 u32 val = 0;
499 u16 port = adapter->physical_port;
500 u8 *addr = adapter->mac_addr;
501
502 if (!adapter->mc_enabled)
503 return 0;
504
505 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
506 val &= ~(1UL << (28+port));
507 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
508
509 val = MAC_HI(addr);
510 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
511 val = MAC_LO(addr);
512 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
513
514 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
515 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
516
517 adapter->mc_enabled = 0;
518 return 0;
519 }
520
521 static int
522 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
523 int index, u8 *addr)
524 {
525 u32 hi = 0, lo = 0;
526 u16 port = adapter->physical_port;
527
528 lo = MAC_LO(addr);
529 hi = MAC_HI(addr);
530
531 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
532 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
533
534 return 0;
535 }
536
537 void netxen_p2_nic_set_multi(struct net_device *netdev)
538 {
539 struct netxen_adapter *adapter = netdev_priv(netdev);
540 struct dev_mc_list *mc_ptr;
541 u8 null_addr[6];
542 int i;
543
544 memset(null_addr, 0, 6);
545
546 if (netdev->flags & IFF_PROMISC) {
547
548 adapter->set_promisc(adapter,
549 NETXEN_NIU_PROMISC_MODE);
550
551 /* Full promiscuous mode */
552 netxen_nic_disable_mcast_filter(adapter);
553
554 return;
555 }
556
557 if (netdev_mc_empty(netdev)) {
558 adapter->set_promisc(adapter,
559 NETXEN_NIU_NON_PROMISC_MODE);
560 netxen_nic_disable_mcast_filter(adapter);
561 return;
562 }
563
564 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
565 if (netdev->flags & IFF_ALLMULTI ||
566 netdev_mc_count(netdev) > adapter->max_mc_count) {
567 netxen_nic_disable_mcast_filter(adapter);
568 return;
569 }
570
571 netxen_nic_enable_mcast_filter(adapter);
572
573 i = 0;
574 netdev_for_each_mc_addr(mc_ptr, netdev)
575 netxen_nic_set_mcast_addr(adapter, i++, mc_ptr->dmi_addr);
576
577 /* Clear out remaining addresses */
578 while (i < adapter->max_mc_count)
579 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
580 }
581
582 static int
583 netxen_send_cmd_descs(struct netxen_adapter *adapter,
584 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
585 {
586 u32 i, producer, consumer;
587 struct netxen_cmd_buffer *pbuf;
588 struct cmd_desc_type0 *cmd_desc;
589 struct nx_host_tx_ring *tx_ring;
590
591 i = 0;
592
593 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
594 return -EIO;
595
596 tx_ring = adapter->tx_ring;
597 __netif_tx_lock_bh(tx_ring->txq);
598
599 producer = tx_ring->producer;
600 consumer = tx_ring->sw_consumer;
601
602 if (nr_desc >= netxen_tx_avail(tx_ring)) {
603 netif_tx_stop_queue(tx_ring->txq);
604 __netif_tx_unlock_bh(tx_ring->txq);
605 return -EBUSY;
606 }
607
608 do {
609 cmd_desc = &cmd_desc_arr[i];
610
611 pbuf = &tx_ring->cmd_buf_arr[producer];
612 pbuf->skb = NULL;
613 pbuf->frag_count = 0;
614
615 memcpy(&tx_ring->desc_head[producer],
616 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
617
618 producer = get_next_index(producer, tx_ring->num_desc);
619 i++;
620
621 } while (i != nr_desc);
622
623 tx_ring->producer = producer;
624
625 netxen_nic_update_cmd_producer(adapter, tx_ring);
626
627 __netif_tx_unlock_bh(tx_ring->txq);
628
629 return 0;
630 }
631
632 static int
633 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
634 {
635 nx_nic_req_t req;
636 nx_mac_req_t *mac_req;
637 u64 word;
638
639 memset(&req, 0, sizeof(nx_nic_req_t));
640 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
641
642 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
643 req.req_hdr = cpu_to_le64(word);
644
645 mac_req = (nx_mac_req_t *)&req.words[0];
646 mac_req->op = op;
647 memcpy(mac_req->mac_addr, addr, 6);
648
649 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
650 }
651
652 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
653 u8 *addr, struct list_head *del_list)
654 {
655 struct list_head *head;
656 nx_mac_list_t *cur;
657
658 /* look up if already exists */
659 list_for_each(head, del_list) {
660 cur = list_entry(head, nx_mac_list_t, list);
661
662 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
663 list_move_tail(head, &adapter->mac_list);
664 return 0;
665 }
666 }
667
668 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
669 if (cur == NULL) {
670 printk(KERN_ERR "%s: failed to add mac address filter\n",
671 adapter->netdev->name);
672 return -ENOMEM;
673 }
674 memcpy(cur->mac_addr, addr, ETH_ALEN);
675 list_add_tail(&cur->list, &adapter->mac_list);
676 return nx_p3_sre_macaddr_change(adapter,
677 cur->mac_addr, NETXEN_MAC_ADD);
678 }
679
680 void netxen_p3_nic_set_multi(struct net_device *netdev)
681 {
682 struct netxen_adapter *adapter = netdev_priv(netdev);
683 struct dev_mc_list *mc_ptr;
684 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
685 u32 mode = VPORT_MISS_MODE_DROP;
686 LIST_HEAD(del_list);
687 struct list_head *head;
688 nx_mac_list_t *cur;
689
690 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
691 return;
692
693 list_splice_tail_init(&adapter->mac_list, &del_list);
694
695 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
696 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
697
698 if (netdev->flags & IFF_PROMISC) {
699 mode = VPORT_MISS_MODE_ACCEPT_ALL;
700 goto send_fw_cmd;
701 }
702
703 if ((netdev->flags & IFF_ALLMULTI) ||
704 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
705 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
706 goto send_fw_cmd;
707 }
708
709 if (!netdev_mc_empty(netdev)) {
710 netdev_for_each_mc_addr(mc_ptr, netdev)
711 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
712 }
713
714 send_fw_cmd:
715 adapter->set_promisc(adapter, mode);
716 head = &del_list;
717 while (!list_empty(head)) {
718 cur = list_entry(head->next, nx_mac_list_t, list);
719
720 nx_p3_sre_macaddr_change(adapter,
721 cur->mac_addr, NETXEN_MAC_DEL);
722 list_del(&cur->list);
723 kfree(cur);
724 }
725 }
726
727 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
728 {
729 nx_nic_req_t req;
730 u64 word;
731
732 memset(&req, 0, sizeof(nx_nic_req_t));
733
734 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
735
736 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
737 ((u64)adapter->portnum << 16);
738 req.req_hdr = cpu_to_le64(word);
739
740 req.words[0] = cpu_to_le64(mode);
741
742 return netxen_send_cmd_descs(adapter,
743 (struct cmd_desc_type0 *)&req, 1);
744 }
745
746 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
747 {
748 nx_mac_list_t *cur;
749 struct list_head *head = &adapter->mac_list;
750
751 while (!list_empty(head)) {
752 cur = list_entry(head->next, nx_mac_list_t, list);
753 nx_p3_sre_macaddr_change(adapter,
754 cur->mac_addr, NETXEN_MAC_DEL);
755 list_del(&cur->list);
756 kfree(cur);
757 }
758 }
759
760 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
761 {
762 /* assuming caller has already copied new addr to netdev */
763 netxen_p3_nic_set_multi(adapter->netdev);
764 return 0;
765 }
766
767 #define NETXEN_CONFIG_INTR_COALESCE 3
768
769 /*
770 * Send the interrupt coalescing parameter set by ethtool to the card.
771 */
772 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
773 {
774 nx_nic_req_t req;
775 u64 word[6];
776 int rv, i;
777
778 memset(&req, 0, sizeof(nx_nic_req_t));
779 memset(word, 0, sizeof(word));
780
781 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
782
783 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
784 req.req_hdr = cpu_to_le64(word[0]);
785
786 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
787 for (i = 0; i < 6; i++)
788 req.words[i] = cpu_to_le64(word[i]);
789
790 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
791 if (rv != 0) {
792 printk(KERN_ERR "ERROR. Could not send "
793 "interrupt coalescing parameters\n");
794 }
795
796 return rv;
797 }
798
799 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
800 {
801 nx_nic_req_t req;
802 u64 word;
803 int rv = 0;
804
805 if ((adapter->flags & NETXEN_NIC_LRO_ENABLED) == enable)
806 return 0;
807
808 memset(&req, 0, sizeof(nx_nic_req_t));
809
810 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
811
812 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
813 req.req_hdr = cpu_to_le64(word);
814
815 req.words[0] = cpu_to_le64(enable);
816
817 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
818 if (rv != 0) {
819 printk(KERN_ERR "ERROR. Could not send "
820 "configure hw lro request\n");
821 }
822
823 adapter->flags ^= NETXEN_NIC_LRO_ENABLED;
824
825 return rv;
826 }
827
828 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
829 {
830 nx_nic_req_t req;
831 u64 word;
832 int rv = 0;
833
834 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
835 return rv;
836
837 memset(&req, 0, sizeof(nx_nic_req_t));
838
839 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
840
841 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
842 ((u64)adapter->portnum << 16);
843 req.req_hdr = cpu_to_le64(word);
844
845 req.words[0] = cpu_to_le64(enable);
846
847 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
848 if (rv != 0) {
849 printk(KERN_ERR "ERROR. Could not send "
850 "configure bridge mode request\n");
851 }
852
853 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
854
855 return rv;
856 }
857
858
859 #define RSS_HASHTYPE_IP_TCP 0x3
860
861 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
862 {
863 nx_nic_req_t req;
864 u64 word;
865 int i, rv;
866
867 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
868 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
869 0x255b0ec26d5a56daULL };
870
871
872 memset(&req, 0, sizeof(nx_nic_req_t));
873 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
874
875 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
876 req.req_hdr = cpu_to_le64(word);
877
878 /*
879 * RSS request:
880 * bits 3-0: hash_method
881 * 5-4: hash_type_ipv4
882 * 7-6: hash_type_ipv6
883 * 8: enable
884 * 9: use indirection table
885 * 47-10: reserved
886 * 63-48: indirection table mask
887 */
888 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
889 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
890 ((u64)(enable & 0x1) << 8) |
891 ((0x7ULL) << 48);
892 req.words[0] = cpu_to_le64(word);
893 for (i = 0; i < 5; i++)
894 req.words[i+1] = cpu_to_le64(key[i]);
895
896
897 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
898 if (rv != 0) {
899 printk(KERN_ERR "%s: could not configure RSS\n",
900 adapter->netdev->name);
901 }
902
903 return rv;
904 }
905
906 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
907 {
908 nx_nic_req_t req;
909 u64 word;
910 int rv;
911
912 memset(&req, 0, sizeof(nx_nic_req_t));
913 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
914
915 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
916 req.req_hdr = cpu_to_le64(word);
917
918 req.words[0] = cpu_to_le64(cmd);
919 req.words[1] = cpu_to_le64(ip);
920
921 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
922 if (rv != 0) {
923 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
924 adapter->netdev->name,
925 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
926 }
927 return rv;
928 }
929
930 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
931 {
932 nx_nic_req_t req;
933 u64 word;
934 int rv;
935
936 memset(&req, 0, sizeof(nx_nic_req_t));
937 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
938
939 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
940 req.req_hdr = cpu_to_le64(word);
941 req.words[0] = cpu_to_le64(enable | (enable << 8));
942
943 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
944 if (rv != 0) {
945 printk(KERN_ERR "%s: could not configure link notification\n",
946 adapter->netdev->name);
947 }
948
949 return rv;
950 }
951
952 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
953 {
954 nx_nic_req_t req;
955 u64 word;
956 int rv;
957
958 memset(&req, 0, sizeof(nx_nic_req_t));
959 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
960
961 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
962 ((u64)adapter->portnum << 16) |
963 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
964
965 req.req_hdr = cpu_to_le64(word);
966
967 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
968 if (rv != 0) {
969 printk(KERN_ERR "%s: could not cleanup lro flows\n",
970 adapter->netdev->name);
971 }
972 return rv;
973 }
974
975 /*
976 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
977 * @returns 0 on success, negative on failure
978 */
979
980 #define MTU_FUDGE_FACTOR 100
981
982 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
983 {
984 struct netxen_adapter *adapter = netdev_priv(netdev);
985 int max_mtu;
986 int rc = 0;
987
988 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
989 max_mtu = P3_MAX_MTU;
990 else
991 max_mtu = P2_MAX_MTU;
992
993 if (mtu > max_mtu) {
994 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
995 netdev->name, max_mtu);
996 return -EINVAL;
997 }
998
999 if (adapter->set_mtu)
1000 rc = adapter->set_mtu(adapter, mtu);
1001
1002 if (!rc)
1003 netdev->mtu = mtu;
1004
1005 return rc;
1006 }
1007
1008 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
1009 int size, __le32 * buf)
1010 {
1011 int i, v, addr;
1012 __le32 *ptr32;
1013
1014 addr = base;
1015 ptr32 = buf;
1016 for (i = 0; i < size / sizeof(u32); i++) {
1017 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1018 return -1;
1019 *ptr32 = cpu_to_le32(v);
1020 ptr32++;
1021 addr += sizeof(u32);
1022 }
1023 if ((char *)buf + size > (char *)ptr32) {
1024 __le32 local;
1025 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
1026 return -1;
1027 local = cpu_to_le32(v);
1028 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1029 }
1030
1031 return 0;
1032 }
1033
1034 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1035 {
1036 __le32 *pmac = (__le32 *) mac;
1037 u32 offset;
1038
1039 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1040
1041 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1042 return -1;
1043
1044 if (*mac == cpu_to_le64(~0ULL)) {
1045
1046 offset = NX_OLD_MAC_ADDR_OFFSET +
1047 (adapter->portnum * sizeof(u64));
1048
1049 if (netxen_get_flash_block(adapter,
1050 offset, sizeof(u64), pmac) == -1)
1051 return -1;
1052
1053 if (*mac == cpu_to_le64(~0ULL))
1054 return -1;
1055 }
1056 return 0;
1057 }
1058
1059 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1060 {
1061 uint32_t crbaddr, mac_hi, mac_lo;
1062 int pci_func = adapter->ahw.pci_func;
1063
1064 crbaddr = CRB_MAC_BLOCK_START +
1065 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1066
1067 mac_lo = NXRD32(adapter, crbaddr);
1068 mac_hi = NXRD32(adapter, crbaddr+4);
1069
1070 if (pci_func & 1)
1071 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1072 else
1073 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1074
1075 return 0;
1076 }
1077
1078 /*
1079 * Changes the CRB window to the specified window.
1080 */
1081 static void
1082 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1083 u32 window)
1084 {
1085 void __iomem *offset;
1086 int count = 10;
1087 u8 func = adapter->ahw.pci_func;
1088
1089 if (adapter->ahw.crb_win == window)
1090 return;
1091
1092 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1093 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1094
1095 writel(window, offset);
1096 do {
1097 if (window == readl(offset))
1098 break;
1099
1100 if (printk_ratelimit())
1101 dev_warn(&adapter->pdev->dev,
1102 "failed to set CRB window to %d\n",
1103 (window == NETXEN_WINDOW_ONE));
1104 udelay(1);
1105
1106 } while (--count > 0);
1107
1108 if (count > 0)
1109 adapter->ahw.crb_win = window;
1110 }
1111
1112 /*
1113 * Returns < 0 if off is not valid,
1114 * 1 if window access is needed. 'off' is set to offset from
1115 * CRB space in 128M pci map
1116 * 0 if no window access is needed. 'off' is set to 2M addr
1117 * In: 'off' is offset from base in 128M pci map
1118 */
1119 static int
1120 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1121 ulong off, void __iomem **addr)
1122 {
1123 crb_128M_2M_sub_block_map_t *m;
1124
1125
1126 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1127 return -EINVAL;
1128
1129 off -= NETXEN_PCI_CRBSPACE;
1130
1131 /*
1132 * Try direct map
1133 */
1134 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1135
1136 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1137 *addr = adapter->ahw.pci_base0 + m->start_2M +
1138 (off - m->start_128M);
1139 return 0;
1140 }
1141
1142 /*
1143 * Not in direct map, use crb window
1144 */
1145 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1146 (off & MASK(16));
1147 return 1;
1148 }
1149
1150 /*
1151 * In: 'off' is offset from CRB space in 128M pci map
1152 * Out: 'off' is 2M pci map addr
1153 * side effect: lock crb window
1154 */
1155 static void
1156 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1157 {
1158 u32 window;
1159 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1160
1161 off -= NETXEN_PCI_CRBSPACE;
1162
1163 window = CRB_HI(off);
1164
1165 if (adapter->ahw.crb_win == window)
1166 return;
1167
1168 writel(window, addr);
1169 if (readl(addr) != window) {
1170 if (printk_ratelimit())
1171 dev_warn(&adapter->pdev->dev,
1172 "failed to set CRB window to %d off 0x%lx\n",
1173 window, off);
1174 }
1175 adapter->ahw.crb_win = window;
1176 }
1177
1178 static void __iomem *
1179 netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1180 ulong win_off, void __iomem **mem_ptr)
1181 {
1182 ulong off = win_off;
1183 void __iomem *addr;
1184 resource_size_t mem_base;
1185
1186 if (ADDR_IN_WINDOW1(win_off))
1187 off = NETXEN_CRB_NORMAL(win_off);
1188
1189 addr = pci_base_offset(adapter, off);
1190 if (addr)
1191 return addr;
1192
1193 if (adapter->ahw.pci_len0 == 0)
1194 off -= NETXEN_PCI_CRBSPACE;
1195
1196 mem_base = pci_resource_start(adapter->pdev, 0);
1197 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1198 if (*mem_ptr)
1199 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1200
1201 return addr;
1202 }
1203
1204 static int
1205 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1206 {
1207 unsigned long flags;
1208 void __iomem *addr, *mem_ptr = NULL;
1209
1210 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1211 if (!addr)
1212 return -EIO;
1213
1214 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1215 netxen_nic_io_write_128M(adapter, addr, data);
1216 } else { /* Window 0 */
1217 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1218 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1219 writel(data, addr);
1220 netxen_nic_pci_set_crbwindow_128M(adapter,
1221 NETXEN_WINDOW_ONE);
1222 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1223 }
1224
1225 if (mem_ptr)
1226 iounmap(mem_ptr);
1227
1228 return 0;
1229 }
1230
1231 static u32
1232 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1233 {
1234 unsigned long flags;
1235 void __iomem *addr, *mem_ptr = NULL;
1236 u32 data;
1237
1238 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1239 if (!addr)
1240 return -EIO;
1241
1242 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1243 data = netxen_nic_io_read_128M(adapter, addr);
1244 } else { /* Window 0 */
1245 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1246 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1247 data = readl(addr);
1248 netxen_nic_pci_set_crbwindow_128M(adapter,
1249 NETXEN_WINDOW_ONE);
1250 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1251 }
1252
1253 if (mem_ptr)
1254 iounmap(mem_ptr);
1255
1256 return data;
1257 }
1258
1259 static int
1260 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1261 {
1262 unsigned long flags;
1263 int rv;
1264 void __iomem *addr = NULL;
1265
1266 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1267
1268 if (rv == 0) {
1269 writel(data, addr);
1270 return 0;
1271 }
1272
1273 if (rv > 0) {
1274 /* indirect access */
1275 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1276 crb_win_lock(adapter);
1277 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1278 writel(data, addr);
1279 crb_win_unlock(adapter);
1280 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1281 return 0;
1282 }
1283
1284 dev_err(&adapter->pdev->dev,
1285 "%s: invalid offset: 0x%016lx\n", __func__, off);
1286 dump_stack();
1287 return -EIO;
1288 }
1289
1290 static u32
1291 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1292 {
1293 unsigned long flags;
1294 int rv;
1295 u32 data;
1296 void __iomem *addr = NULL;
1297
1298 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1299
1300 if (rv == 0)
1301 return readl(addr);
1302
1303 if (rv > 0) {
1304 /* indirect access */
1305 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1306 crb_win_lock(adapter);
1307 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1308 data = readl(addr);
1309 crb_win_unlock(adapter);
1310 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1311 return data;
1312 }
1313
1314 dev_err(&adapter->pdev->dev,
1315 "%s: invalid offset: 0x%016lx\n", __func__, off);
1316 dump_stack();
1317 return -1;
1318 }
1319
1320 /* window 1 registers only */
1321 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1322 void __iomem *addr, u32 data)
1323 {
1324 read_lock(&adapter->ahw.crb_lock);
1325 writel(data, addr);
1326 read_unlock(&adapter->ahw.crb_lock);
1327 }
1328
1329 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1330 void __iomem *addr)
1331 {
1332 u32 val;
1333
1334 read_lock(&adapter->ahw.crb_lock);
1335 val = readl(addr);
1336 read_unlock(&adapter->ahw.crb_lock);
1337
1338 return val;
1339 }
1340
1341 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1342 void __iomem *addr, u32 data)
1343 {
1344 writel(data, addr);
1345 }
1346
1347 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1348 void __iomem *addr)
1349 {
1350 return readl(addr);
1351 }
1352
1353 void __iomem *
1354 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1355 {
1356 void __iomem *addr = NULL;
1357
1358 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1359 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1360 (offset > NETXEN_CRB_PCIX_HOST))
1361 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1362 else
1363 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1364 } else {
1365 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1366 offset, &addr));
1367 }
1368
1369 return addr;
1370 }
1371
1372 static int
1373 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1374 u64 addr, u32 *start)
1375 {
1376 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1377 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1378 return 0;
1379 } else if (ADDR_IN_RANGE(addr,
1380 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1381 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1382 return 0;
1383 }
1384
1385 return -EIO;
1386 }
1387
1388 static int
1389 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1390 u64 addr, u32 *start)
1391 {
1392 u32 window;
1393 struct pci_dev *pdev = adapter->pdev;
1394
1395 if ((addr & 0x00ff800) == 0xff800) {
1396 if (printk_ratelimit())
1397 dev_warn(&pdev->dev, "QM access not handled\n");
1398 return -EIO;
1399 }
1400
1401 if (NX_IS_REVISION_P3P(adapter->ahw.revision_id))
1402 window = OCM_WIN_P3P(addr);
1403 else
1404 window = OCM_WIN(addr);
1405
1406 writel(window, adapter->ahw.ocm_win_crb);
1407 /* read back to flush */
1408 readl(adapter->ahw.ocm_win_crb);
1409
1410 adapter->ahw.ocm_win = window;
1411 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1412 return 0;
1413 }
1414
1415 static int
1416 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1417 u64 *data, int op)
1418 {
1419 void __iomem *addr, *mem_ptr = NULL;
1420 resource_size_t mem_base;
1421 int ret = -EIO;
1422 u32 start;
1423
1424 spin_lock(&adapter->ahw.mem_lock);
1425
1426 ret = adapter->pci_set_window(adapter, off, &start);
1427 if (ret != 0)
1428 goto unlock;
1429
1430 addr = pci_base_offset(adapter, start);
1431 if (addr)
1432 goto noremap;
1433
1434 mem_base = pci_resource_start(adapter->pdev, 0) + (start & PAGE_MASK);
1435
1436 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1437 if (mem_ptr == NULL) {
1438 ret = -EIO;
1439 goto unlock;
1440 }
1441
1442 addr = mem_ptr + (start & (PAGE_SIZE - 1));
1443
1444 noremap:
1445 if (op == 0) /* read */
1446 *data = readq(addr);
1447 else /* write */
1448 writeq(*data, addr);
1449
1450 unlock:
1451 spin_unlock(&adapter->ahw.mem_lock);
1452
1453 if (mem_ptr)
1454 iounmap(mem_ptr);
1455 return ret;
1456 }
1457
1458 #define MAX_CTL_CHECK 1000
1459
1460 static int
1461 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1462 u64 off, u64 data)
1463 {
1464 int j, ret;
1465 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1466 void __iomem *mem_crb;
1467
1468 /* Only 64-bit aligned access */
1469 if (off & 7)
1470 return -EIO;
1471
1472 /* P2 has different SIU and MIU test agent base addr */
1473 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1474 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1475 mem_crb = pci_base_offset(adapter,
1476 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1477 addr_hi = SIU_TEST_AGT_ADDR_HI;
1478 data_lo = SIU_TEST_AGT_WRDATA_LO;
1479 data_hi = SIU_TEST_AGT_WRDATA_HI;
1480 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1481 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1482 goto correct;
1483 }
1484
1485 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1486 mem_crb = pci_base_offset(adapter,
1487 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1488 addr_hi = MIU_TEST_AGT_ADDR_HI;
1489 data_lo = MIU_TEST_AGT_WRDATA_LO;
1490 data_hi = MIU_TEST_AGT_WRDATA_HI;
1491 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1492 off_hi = 0;
1493 goto correct;
1494 }
1495
1496 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1497 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1498 if (adapter->ahw.pci_len0 != 0) {
1499 return netxen_nic_pci_mem_access_direct(adapter,
1500 off, &data, 1);
1501 }
1502 }
1503
1504 return -EIO;
1505
1506 correct:
1507 spin_lock(&adapter->ahw.mem_lock);
1508 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1509
1510 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1511 writel(off_hi, (mem_crb + addr_hi));
1512 writel(data & 0xffffffff, (mem_crb + data_lo));
1513 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1514 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1515 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1516 (mem_crb + TEST_AGT_CTRL));
1517
1518 for (j = 0; j < MAX_CTL_CHECK; j++) {
1519 temp = readl((mem_crb + TEST_AGT_CTRL));
1520 if ((temp & TA_CTL_BUSY) == 0)
1521 break;
1522 }
1523
1524 if (j >= MAX_CTL_CHECK) {
1525 if (printk_ratelimit())
1526 dev_err(&adapter->pdev->dev,
1527 "failed to write through agent\n");
1528 ret = -EIO;
1529 } else
1530 ret = 0;
1531
1532 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1533 spin_unlock(&adapter->ahw.mem_lock);
1534 return ret;
1535 }
1536
1537 static int
1538 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1539 u64 off, u64 *data)
1540 {
1541 int j, ret;
1542 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1543 u64 val;
1544 void __iomem *mem_crb;
1545
1546 /* Only 64-bit aligned access */
1547 if (off & 7)
1548 return -EIO;
1549
1550 /* P2 has different SIU and MIU test agent base addr */
1551 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1552 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1553 mem_crb = pci_base_offset(adapter,
1554 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1555 addr_hi = SIU_TEST_AGT_ADDR_HI;
1556 data_lo = SIU_TEST_AGT_RDDATA_LO;
1557 data_hi = SIU_TEST_AGT_RDDATA_HI;
1558 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1559 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1560 goto correct;
1561 }
1562
1563 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1564 mem_crb = pci_base_offset(adapter,
1565 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1566 addr_hi = MIU_TEST_AGT_ADDR_HI;
1567 data_lo = MIU_TEST_AGT_RDDATA_LO;
1568 data_hi = MIU_TEST_AGT_RDDATA_HI;
1569 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1570 off_hi = 0;
1571 goto correct;
1572 }
1573
1574 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1575 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1576 if (adapter->ahw.pci_len0 != 0) {
1577 return netxen_nic_pci_mem_access_direct(adapter,
1578 off, data, 0);
1579 }
1580 }
1581
1582 return -EIO;
1583
1584 correct:
1585 spin_lock(&adapter->ahw.mem_lock);
1586 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1587
1588 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1589 writel(off_hi, (mem_crb + addr_hi));
1590 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1591 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1592
1593 for (j = 0; j < MAX_CTL_CHECK; j++) {
1594 temp = readl(mem_crb + TEST_AGT_CTRL);
1595 if ((temp & TA_CTL_BUSY) == 0)
1596 break;
1597 }
1598
1599 if (j >= MAX_CTL_CHECK) {
1600 if (printk_ratelimit())
1601 dev_err(&adapter->pdev->dev,
1602 "failed to read through agent\n");
1603 ret = -EIO;
1604 } else {
1605
1606 temp = readl(mem_crb + data_hi);
1607 val = ((u64)temp << 32);
1608 val |= readl(mem_crb + data_lo);
1609 *data = val;
1610 ret = 0;
1611 }
1612
1613 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1614 spin_unlock(&adapter->ahw.mem_lock);
1615
1616 return ret;
1617 }
1618
1619 static int
1620 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1621 u64 off, u64 data)
1622 {
1623 int i, j, ret;
1624 u32 temp, off8;
1625 u64 stride;
1626 void __iomem *mem_crb;
1627
1628 /* Only 64-bit aligned access */
1629 if (off & 7)
1630 return -EIO;
1631
1632 /* P3 onward, test agent base for MIU and SIU is same */
1633 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1634 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1635 mem_crb = netxen_get_ioaddr(adapter,
1636 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1637 goto correct;
1638 }
1639
1640 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1641 mem_crb = netxen_get_ioaddr(adapter,
1642 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1643 goto correct;
1644 }
1645
1646 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1647 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1648
1649 return -EIO;
1650
1651 correct:
1652 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1653
1654 off8 = off & ~(stride-1);
1655
1656 spin_lock(&adapter->ahw.mem_lock);
1657
1658 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1659 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1660
1661 i = 0;
1662 if (stride == 16) {
1663 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1664 writel((TA_CTL_START | TA_CTL_ENABLE),
1665 (mem_crb + TEST_AGT_CTRL));
1666
1667 for (j = 0; j < MAX_CTL_CHECK; j++) {
1668 temp = readl(mem_crb + TEST_AGT_CTRL);
1669 if ((temp & TA_CTL_BUSY) == 0)
1670 break;
1671 }
1672
1673 if (j >= MAX_CTL_CHECK) {
1674 ret = -EIO;
1675 goto done;
1676 }
1677
1678 i = (off & 0xf) ? 0 : 2;
1679 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i)),
1680 mem_crb + MIU_TEST_AGT_WRDATA(i));
1681 writel(readl(mem_crb + MIU_TEST_AGT_RDDATA(i+1)),
1682 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1683 i = (off & 0xf) ? 2 : 0;
1684 }
1685
1686 writel(data & 0xffffffff,
1687 mem_crb + MIU_TEST_AGT_WRDATA(i));
1688 writel((data >> 32) & 0xffffffff,
1689 mem_crb + MIU_TEST_AGT_WRDATA(i+1));
1690
1691 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1692 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1693 (mem_crb + TEST_AGT_CTRL));
1694
1695 for (j = 0; j < MAX_CTL_CHECK; j++) {
1696 temp = readl(mem_crb + TEST_AGT_CTRL);
1697 if ((temp & TA_CTL_BUSY) == 0)
1698 break;
1699 }
1700
1701 if (j >= MAX_CTL_CHECK) {
1702 if (printk_ratelimit())
1703 dev_err(&adapter->pdev->dev,
1704 "failed to write through agent\n");
1705 ret = -EIO;
1706 } else
1707 ret = 0;
1708
1709 done:
1710 spin_unlock(&adapter->ahw.mem_lock);
1711
1712 return ret;
1713 }
1714
1715 static int
1716 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1717 u64 off, u64 *data)
1718 {
1719 int j, ret;
1720 u32 temp, off8;
1721 u64 val, stride;
1722 void __iomem *mem_crb;
1723
1724 /* Only 64-bit aligned access */
1725 if (off & 7)
1726 return -EIO;
1727
1728 /* P3 onward, test agent base for MIU and SIU is same */
1729 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1730 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1731 mem_crb = netxen_get_ioaddr(adapter,
1732 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1733 goto correct;
1734 }
1735
1736 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1737 mem_crb = netxen_get_ioaddr(adapter,
1738 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1739 goto correct;
1740 }
1741
1742 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1743 return netxen_nic_pci_mem_access_direct(adapter,
1744 off, data, 0);
1745 }
1746
1747 return -EIO;
1748
1749 correct:
1750 stride = NX_IS_REVISION_P3P(adapter->ahw.revision_id) ? 16 : 8;
1751
1752 off8 = off & ~(stride-1);
1753
1754 spin_lock(&adapter->ahw.mem_lock);
1755
1756 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1757 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1758 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1759 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1760
1761 for (j = 0; j < MAX_CTL_CHECK; j++) {
1762 temp = readl(mem_crb + TEST_AGT_CTRL);
1763 if ((temp & TA_CTL_BUSY) == 0)
1764 break;
1765 }
1766
1767 if (j >= MAX_CTL_CHECK) {
1768 if (printk_ratelimit())
1769 dev_err(&adapter->pdev->dev,
1770 "failed to read through agent\n");
1771 ret = -EIO;
1772 } else {
1773 off8 = MIU_TEST_AGT_RDDATA_LO;
1774 if ((stride == 16) && (off & 0xf))
1775 off8 = MIU_TEST_AGT_RDDATA_UPPER_LO;
1776
1777 temp = readl(mem_crb + off8 + 4);
1778 val = (u64)temp << 32;
1779 val |= readl(mem_crb + off8);
1780 *data = val;
1781 ret = 0;
1782 }
1783
1784 spin_unlock(&adapter->ahw.mem_lock);
1785
1786 return ret;
1787 }
1788
1789 void
1790 netxen_setup_hwops(struct netxen_adapter *adapter)
1791 {
1792 adapter->init_port = netxen_niu_xg_init_port;
1793 adapter->stop_port = netxen_niu_disable_xg_port;
1794
1795 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1796 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1797 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1798 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1799 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1800 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1801 adapter->io_read = netxen_nic_io_read_128M,
1802 adapter->io_write = netxen_nic_io_write_128M,
1803
1804 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1805 adapter->set_multi = netxen_p2_nic_set_multi;
1806 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1807 adapter->set_promisc = netxen_p2_nic_set_promisc;
1808
1809 } else {
1810 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1811 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1812 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1813 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1814 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1815 adapter->io_read = netxen_nic_io_read_2M,
1816 adapter->io_write = netxen_nic_io_write_2M,
1817
1818 adapter->set_mtu = nx_fw_cmd_set_mtu;
1819 adapter->set_promisc = netxen_p3_nic_set_promisc;
1820 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1821 adapter->set_multi = netxen_p3_nic_set_multi;
1822
1823 adapter->phy_read = nx_fw_cmd_query_phy;
1824 adapter->phy_write = nx_fw_cmd_set_phy;
1825 }
1826 }
1827
1828 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1829 {
1830 int offset, board_type, magic;
1831 struct pci_dev *pdev = adapter->pdev;
1832
1833 offset = NX_FW_MAGIC_OFFSET;
1834 if (netxen_rom_fast_read(adapter, offset, &magic))
1835 return -EIO;
1836
1837 if (magic != NETXEN_BDINFO_MAGIC) {
1838 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1839 magic);
1840 return -EIO;
1841 }
1842
1843 offset = NX_BRDTYPE_OFFSET;
1844 if (netxen_rom_fast_read(adapter, offset, &board_type))
1845 return -EIO;
1846
1847 adapter->ahw.board_type = board_type;
1848
1849 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1850 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1851 if ((gpio & 0x8000) == 0)
1852 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1853 }
1854
1855 switch (board_type) {
1856 case NETXEN_BRDTYPE_P2_SB35_4G:
1857 adapter->ahw.port_type = NETXEN_NIC_GBE;
1858 break;
1859 case NETXEN_BRDTYPE_P2_SB31_10G:
1860 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1861 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1862 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1863 case NETXEN_BRDTYPE_P3_HMEZ:
1864 case NETXEN_BRDTYPE_P3_XG_LOM:
1865 case NETXEN_BRDTYPE_P3_10G_CX4:
1866 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1867 case NETXEN_BRDTYPE_P3_IMEZ:
1868 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1869 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1870 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1871 case NETXEN_BRDTYPE_P3_10G_XFP:
1872 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1873 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1874 break;
1875 case NETXEN_BRDTYPE_P1_BD:
1876 case NETXEN_BRDTYPE_P1_SB:
1877 case NETXEN_BRDTYPE_P1_SMAX:
1878 case NETXEN_BRDTYPE_P1_SOCK:
1879 case NETXEN_BRDTYPE_P3_REF_QG:
1880 case NETXEN_BRDTYPE_P3_4_GB:
1881 case NETXEN_BRDTYPE_P3_4_GB_MM:
1882 adapter->ahw.port_type = NETXEN_NIC_GBE;
1883 break;
1884 case NETXEN_BRDTYPE_P3_10G_TP:
1885 adapter->ahw.port_type = (adapter->portnum < 2) ?
1886 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1887 break;
1888 default:
1889 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1890 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1891 break;
1892 }
1893
1894 return 0;
1895 }
1896
1897 /* NIU access sections */
1898
1899 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1900 {
1901 new_mtu += MTU_FUDGE_FACTOR;
1902 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1903 new_mtu);
1904 return 0;
1905 }
1906
1907 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1908 {
1909 new_mtu += MTU_FUDGE_FACTOR;
1910 if (adapter->physical_port == 0)
1911 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1912 else
1913 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1914 return 0;
1915 }
1916
1917 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1918 {
1919 __u32 status;
1920 __u32 autoneg;
1921 __u32 port_mode;
1922
1923 if (!netif_carrier_ok(adapter->netdev)) {
1924 adapter->link_speed = 0;
1925 adapter->link_duplex = -1;
1926 adapter->link_autoneg = AUTONEG_ENABLE;
1927 return;
1928 }
1929
1930 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1931 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1932 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1933 adapter->link_speed = SPEED_1000;
1934 adapter->link_duplex = DUPLEX_FULL;
1935 adapter->link_autoneg = AUTONEG_DISABLE;
1936 return;
1937 }
1938
1939 if (adapter->phy_read &&
1940 adapter->phy_read(adapter,
1941 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1942 &status) == 0) {
1943 if (netxen_get_phy_link(status)) {
1944 switch (netxen_get_phy_speed(status)) {
1945 case 0:
1946 adapter->link_speed = SPEED_10;
1947 break;
1948 case 1:
1949 adapter->link_speed = SPEED_100;
1950 break;
1951 case 2:
1952 adapter->link_speed = SPEED_1000;
1953 break;
1954 default:
1955 adapter->link_speed = 0;
1956 break;
1957 }
1958 switch (netxen_get_phy_duplex(status)) {
1959 case 0:
1960 adapter->link_duplex = DUPLEX_HALF;
1961 break;
1962 case 1:
1963 adapter->link_duplex = DUPLEX_FULL;
1964 break;
1965 default:
1966 adapter->link_duplex = -1;
1967 break;
1968 }
1969 if (adapter->phy_read &&
1970 adapter->phy_read(adapter,
1971 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1972 &autoneg) != 0)
1973 adapter->link_autoneg = autoneg;
1974 } else
1975 goto link_down;
1976 } else {
1977 link_down:
1978 adapter->link_speed = 0;
1979 adapter->link_duplex = -1;
1980 }
1981 }
1982 }
1983
1984 int
1985 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1986 {
1987 u32 wol_cfg;
1988
1989 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1990 return 0;
1991
1992 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1993 if (wol_cfg & (1UL << adapter->portnum)) {
1994 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1995 if (wol_cfg & (1 << adapter->portnum))
1996 return 1;
1997 }
1998
1999 return 0;
2000 }
Linux kernel - Deliverables
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