1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
31 #include <linux/of_device.h>
35 #define DRV_MODULE_NAME "niu"
36 #define DRV_MODULE_VERSION "1.1"
37 #define DRV_MODULE_RELDATE "Apr 22, 2010"
39 static char version
[] __devinitdata
=
40 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION
);
48 static u64
readq(void __iomem
*reg
)
50 return ((u64
) readl(reg
)) | (((u64
) readl(reg
+ 4UL)) << 32);
53 static void writeq(u64 val
, void __iomem
*reg
)
55 writel(val
& 0xffffffff, reg
);
56 writel(val
>> 32, reg
+ 0x4UL
);
60 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl
) = {
61 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
65 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
67 #define NIU_TX_TIMEOUT (5 * HZ)
69 #define nr64(reg) readq(np->regs + (reg))
70 #define nw64(reg, val) writeq((val), np->regs + (reg))
72 #define nr64_mac(reg) readq(np->mac_regs + (reg))
73 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
75 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
76 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
78 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
79 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
81 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
82 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
84 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
87 static int debug
= -1;
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "NIU debug level");
91 #define niu_lock_parent(np, flags) \
92 spin_lock_irqsave(&np->parent->lock, flags)
93 #define niu_unlock_parent(np, flags) \
94 spin_unlock_irqrestore(&np->parent->lock, flags)
96 static int serdes_init_10g_serdes(struct niu
*np
);
98 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
99 u64 bits
, int limit
, int delay
)
101 while (--limit
>= 0) {
102 u64 val
= nr64_mac(reg
);
113 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
114 u64 bits
, int limit
, int delay
,
115 const char *reg_name
)
120 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
122 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
123 (unsigned long long)bits
, reg_name
,
124 (unsigned long long)nr64_mac(reg
));
128 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
129 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
130 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
133 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
134 u64 bits
, int limit
, int delay
)
136 while (--limit
>= 0) {
137 u64 val
= nr64_ipp(reg
);
148 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
149 u64 bits
, int limit
, int delay
,
150 const char *reg_name
)
159 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
161 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
162 (unsigned long long)bits
, reg_name
,
163 (unsigned long long)nr64_ipp(reg
));
167 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
168 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
169 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
172 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
173 u64 bits
, int limit
, int delay
)
175 while (--limit
>= 0) {
187 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
188 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
189 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
192 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
193 u64 bits
, int limit
, int delay
,
194 const char *reg_name
)
199 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
201 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
202 (unsigned long long)bits
, reg_name
,
203 (unsigned long long)nr64(reg
));
207 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
208 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
209 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
212 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
214 u64 val
= (u64
) lp
->timer
;
217 val
|= LDG_IMGMT_ARM
;
219 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
222 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
224 unsigned long mask_reg
, bits
;
227 if (ldn
< 0 || ldn
> LDN_MAX
)
231 mask_reg
= LD_IM0(ldn
);
234 mask_reg
= LD_IM1(ldn
- 64);
238 val
= nr64(mask_reg
);
248 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
250 struct niu_parent
*parent
= np
->parent
;
253 for (i
= 0; i
<= LDN_MAX
; i
++) {
256 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
259 err
= niu_ldn_irq_enable(np
, i
, on
);
266 static int niu_enable_interrupts(struct niu
*np
, int on
)
270 for (i
= 0; i
< np
->num_ldg
; i
++) {
271 struct niu_ldg
*lp
= &np
->ldg
[i
];
274 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
278 for (i
= 0; i
< np
->num_ldg
; i
++)
279 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
284 static u32
phy_encode(u32 type
, int port
)
286 return type
<< (port
* 2);
289 static u32
phy_decode(u32 val
, int port
)
291 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
294 static int mdio_wait(struct niu
*np
)
299 while (--limit
> 0) {
300 val
= nr64(MIF_FRAME_OUTPUT
);
301 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
302 return val
& MIF_FRAME_OUTPUT_DATA
;
310 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
314 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
319 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
320 return mdio_wait(np
);
323 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
327 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
332 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
340 static int mii_read(struct niu
*np
, int port
, int reg
)
342 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
343 return mdio_wait(np
);
346 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
350 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
358 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
362 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
363 ESR2_TI_PLL_TX_CFG_L(channel
),
366 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
367 ESR2_TI_PLL_TX_CFG_H(channel
),
372 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
376 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
377 ESR2_TI_PLL_RX_CFG_L(channel
),
380 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
381 ESR2_TI_PLL_RX_CFG_H(channel
),
386 /* Mode is always 10G fiber. */
387 static int serdes_init_niu_10g_fiber(struct niu
*np
)
389 struct niu_link_config
*lp
= &np
->link_config
;
393 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
394 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
395 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
396 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
398 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
399 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
401 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
402 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
404 tx_cfg
|= PLL_TX_CFG_ENTEST
;
405 rx_cfg
|= PLL_RX_CFG_ENTEST
;
408 /* Initialize all 4 lanes of the SERDES. */
409 for (i
= 0; i
< 4; i
++) {
410 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
415 for (i
= 0; i
< 4; i
++) {
416 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
424 static int serdes_init_niu_1g_serdes(struct niu
*np
)
426 struct niu_link_config
*lp
= &np
->link_config
;
427 u16 pll_cfg
, pll_sts
;
429 u64
uninitialized_var(sig
), mask
, val
;
434 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
|
435 PLL_TX_CFG_RATE_HALF
);
436 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
437 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
438 PLL_RX_CFG_RATE_HALF
);
441 rx_cfg
|= PLL_RX_CFG_EQ_LP_ADAPTIVE
;
443 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
444 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
446 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
447 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
449 tx_cfg
|= PLL_TX_CFG_ENTEST
;
450 rx_cfg
|= PLL_RX_CFG_ENTEST
;
453 /* Initialize PLL for 1G */
454 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_8X
);
456 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
457 ESR2_TI_PLL_CFG_L
, pll_cfg
);
459 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
464 pll_sts
= PLL_CFG_ENPLL
;
466 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
467 ESR2_TI_PLL_STS_L
, pll_sts
);
469 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
476 /* Initialize all 4 lanes of the SERDES. */
477 for (i
= 0; i
< 4; i
++) {
478 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
483 for (i
= 0; i
< 4; i
++) {
484 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
491 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
496 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
504 while (max_retry
--) {
505 sig
= nr64(ESR_INT_SIGNALS
);
506 if ((sig
& mask
) == val
)
512 if ((sig
& mask
) != val
) {
513 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
514 np
->port
, (int)(sig
& mask
), (int)val
);
521 static int serdes_init_niu_10g_serdes(struct niu
*np
)
523 struct niu_link_config
*lp
= &np
->link_config
;
524 u32 tx_cfg
, rx_cfg
, pll_cfg
, pll_sts
;
526 u64
uninitialized_var(sig
), mask
, val
;
530 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
531 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
532 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
533 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
535 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
536 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
538 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
539 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
541 tx_cfg
|= PLL_TX_CFG_ENTEST
;
542 rx_cfg
|= PLL_RX_CFG_ENTEST
;
545 /* Initialize PLL for 10G */
546 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_10X
);
548 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
549 ESR2_TI_PLL_CFG_L
, pll_cfg
& 0xffff);
551 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
556 pll_sts
= PLL_CFG_ENPLL
;
558 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
559 ESR2_TI_PLL_STS_L
, pll_sts
& 0xffff);
561 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
568 /* Initialize all 4 lanes of the SERDES. */
569 for (i
= 0; i
< 4; i
++) {
570 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
575 for (i
= 0; i
< 4; i
++) {
576 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
581 /* check if serdes is ready */
585 mask
= ESR_INT_SIGNALS_P0_BITS
;
586 val
= (ESR_INT_SRDY0_P0
|
596 mask
= ESR_INT_SIGNALS_P1_BITS
;
597 val
= (ESR_INT_SRDY0_P1
|
610 while (max_retry
--) {
611 sig
= nr64(ESR_INT_SIGNALS
);
612 if ((sig
& mask
) == val
)
618 if ((sig
& mask
) != val
) {
619 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
620 np
->port
, (int)(sig
& mask
), (int)val
);
622 /* 10G failed, try initializing at 1G */
623 err
= serdes_init_niu_1g_serdes(np
);
625 np
->flags
&= ~NIU_FLAGS_10G
;
626 np
->mac_xcvr
= MAC_XCVR_PCS
;
628 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
636 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
640 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
642 *val
= (err
& 0xffff);
643 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
644 ESR_RXTX_CTRL_H(chan
));
646 *val
|= ((err
& 0xffff) << 16);
652 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
656 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
657 ESR_GLUE_CTRL0_L(chan
));
659 *val
= (err
& 0xffff);
660 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
661 ESR_GLUE_CTRL0_H(chan
));
663 *val
|= ((err
& 0xffff) << 16);
670 static int esr_read_reset(struct niu
*np
, u32
*val
)
674 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
675 ESR_RXTX_RESET_CTRL_L
);
677 *val
= (err
& 0xffff);
678 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
679 ESR_RXTX_RESET_CTRL_H
);
681 *val
|= ((err
& 0xffff) << 16);
688 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
692 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
693 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
695 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
696 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
700 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
704 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
705 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
707 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
708 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
712 static int esr_reset(struct niu
*np
)
714 u32
uninitialized_var(reset
);
717 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
718 ESR_RXTX_RESET_CTRL_L
, 0x0000);
721 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
722 ESR_RXTX_RESET_CTRL_H
, 0xffff);
727 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
728 ESR_RXTX_RESET_CTRL_L
, 0xffff);
733 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
734 ESR_RXTX_RESET_CTRL_H
, 0x0000);
739 err
= esr_read_reset(np
, &reset
);
743 netdev_err(np
->dev
, "Port %u ESR_RESET did not clear [%08x]\n",
751 static int serdes_init_10g(struct niu
*np
)
753 struct niu_link_config
*lp
= &np
->link_config
;
754 unsigned long ctrl_reg
, test_cfg_reg
, i
;
755 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
760 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
761 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
764 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
765 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
771 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
772 ENET_SERDES_CTRL_SDET_1
|
773 ENET_SERDES_CTRL_SDET_2
|
774 ENET_SERDES_CTRL_SDET_3
|
775 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
776 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
777 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
778 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
779 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
780 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
781 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
785 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
786 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
787 ENET_SERDES_TEST_MD_0_SHIFT
) |
788 (ENET_TEST_MD_PAD_LOOPBACK
<<
789 ENET_SERDES_TEST_MD_1_SHIFT
) |
790 (ENET_TEST_MD_PAD_LOOPBACK
<<
791 ENET_SERDES_TEST_MD_2_SHIFT
) |
792 (ENET_TEST_MD_PAD_LOOPBACK
<<
793 ENET_SERDES_TEST_MD_3_SHIFT
));
796 nw64(ctrl_reg
, ctrl_val
);
797 nw64(test_cfg_reg
, test_cfg_val
);
799 /* Initialize all 4 lanes of the SERDES. */
800 for (i
= 0; i
< 4; i
++) {
801 u32 rxtx_ctrl
, glue0
;
803 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
806 err
= esr_read_glue0(np
, i
, &glue0
);
810 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
811 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
812 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
814 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
815 ESR_GLUE_CTRL0_THCNT
|
816 ESR_GLUE_CTRL0_BLTIME
);
817 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
818 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
819 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
820 (BLTIME_300_CYCLES
<<
821 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
823 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
826 err
= esr_write_glue0(np
, i
, glue0
);
835 sig
= nr64(ESR_INT_SIGNALS
);
838 mask
= ESR_INT_SIGNALS_P0_BITS
;
839 val
= (ESR_INT_SRDY0_P0
|
849 mask
= ESR_INT_SIGNALS_P1_BITS
;
850 val
= (ESR_INT_SRDY0_P1
|
863 if ((sig
& mask
) != val
) {
864 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
865 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
868 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
869 np
->port
, (int)(sig
& mask
), (int)val
);
872 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
873 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
877 static int serdes_init_1g(struct niu
*np
)
881 val
= nr64(ENET_SERDES_1_PLL_CFG
);
882 val
&= ~ENET_SERDES_PLL_FBDIV2
;
885 val
|= ENET_SERDES_PLL_HRATE0
;
888 val
|= ENET_SERDES_PLL_HRATE1
;
891 val
|= ENET_SERDES_PLL_HRATE2
;
894 val
|= ENET_SERDES_PLL_HRATE3
;
899 nw64(ENET_SERDES_1_PLL_CFG
, val
);
904 static int serdes_init_1g_serdes(struct niu
*np
)
906 struct niu_link_config
*lp
= &np
->link_config
;
907 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
908 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
910 u64 reset_val
, val_rd
;
912 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
913 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
914 ENET_SERDES_PLL_FBDIV0
;
917 reset_val
= ENET_SERDES_RESET_0
;
918 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
919 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
920 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
923 reset_val
= ENET_SERDES_RESET_1
;
924 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
925 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
926 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
932 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
933 ENET_SERDES_CTRL_SDET_1
|
934 ENET_SERDES_CTRL_SDET_2
|
935 ENET_SERDES_CTRL_SDET_3
|
936 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
937 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
938 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
939 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
940 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
941 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
942 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
946 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
947 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
948 ENET_SERDES_TEST_MD_0_SHIFT
) |
949 (ENET_TEST_MD_PAD_LOOPBACK
<<
950 ENET_SERDES_TEST_MD_1_SHIFT
) |
951 (ENET_TEST_MD_PAD_LOOPBACK
<<
952 ENET_SERDES_TEST_MD_2_SHIFT
) |
953 (ENET_TEST_MD_PAD_LOOPBACK
<<
954 ENET_SERDES_TEST_MD_3_SHIFT
));
957 nw64(ENET_SERDES_RESET
, reset_val
);
959 val_rd
= nr64(ENET_SERDES_RESET
);
960 val_rd
&= ~reset_val
;
962 nw64(ctrl_reg
, ctrl_val
);
963 nw64(test_cfg_reg
, test_cfg_val
);
964 nw64(ENET_SERDES_RESET
, val_rd
);
967 /* Initialize all 4 lanes of the SERDES. */
968 for (i
= 0; i
< 4; i
++) {
969 u32 rxtx_ctrl
, glue0
;
971 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
974 err
= esr_read_glue0(np
, i
, &glue0
);
978 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
979 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
980 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
982 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
983 ESR_GLUE_CTRL0_THCNT
|
984 ESR_GLUE_CTRL0_BLTIME
);
985 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
986 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
987 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
988 (BLTIME_300_CYCLES
<<
989 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
991 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
994 err
= esr_write_glue0(np
, i
, glue0
);
1000 sig
= nr64(ESR_INT_SIGNALS
);
1003 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
1008 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
1016 if ((sig
& mask
) != val
) {
1017 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
1018 np
->port
, (int)(sig
& mask
), (int)val
);
1025 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
1027 struct niu_link_config
*lp
= &np
->link_config
;
1031 unsigned long flags
;
1035 current_speed
= SPEED_INVALID
;
1036 current_duplex
= DUPLEX_INVALID
;
1038 spin_lock_irqsave(&np
->lock
, flags
);
1040 val
= nr64_pcs(PCS_MII_STAT
);
1042 if (val
& PCS_MII_STAT_LINK_STATUS
) {
1044 current_speed
= SPEED_1000
;
1045 current_duplex
= DUPLEX_FULL
;
1048 lp
->active_speed
= current_speed
;
1049 lp
->active_duplex
= current_duplex
;
1050 spin_unlock_irqrestore(&np
->lock
, flags
);
1052 *link_up_p
= link_up
;
1056 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
1058 unsigned long flags
;
1059 struct niu_link_config
*lp
= &np
->link_config
;
1066 if (!(np
->flags
& NIU_FLAGS_10G
))
1067 return link_status_1g_serdes(np
, link_up_p
);
1069 current_speed
= SPEED_INVALID
;
1070 current_duplex
= DUPLEX_INVALID
;
1071 spin_lock_irqsave(&np
->lock
, flags
);
1073 val
= nr64_xpcs(XPCS_STATUS(0));
1074 val2
= nr64_mac(XMAC_INTER2
);
1075 if (val2
& 0x01000000)
1078 if ((val
& 0x1000ULL
) && link_ok
) {
1080 current_speed
= SPEED_10000
;
1081 current_duplex
= DUPLEX_FULL
;
1083 lp
->active_speed
= current_speed
;
1084 lp
->active_duplex
= current_duplex
;
1085 spin_unlock_irqrestore(&np
->lock
, flags
);
1086 *link_up_p
= link_up
;
1090 static int link_status_mii(struct niu
*np
, int *link_up_p
)
1092 struct niu_link_config
*lp
= &np
->link_config
;
1094 int bmsr
, advert
, ctrl1000
, stat1000
, lpa
, bmcr
, estatus
;
1095 int supported
, advertising
, active_speed
, active_duplex
;
1097 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1098 if (unlikely(err
< 0))
1102 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1103 if (unlikely(err
< 0))
1107 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1108 if (unlikely(err
< 0))
1112 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1113 if (unlikely(err
< 0))
1117 if (likely(bmsr
& BMSR_ESTATEN
)) {
1118 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1119 if (unlikely(err
< 0))
1123 err
= mii_read(np
, np
->phy_addr
, MII_CTRL1000
);
1124 if (unlikely(err
< 0))
1128 err
= mii_read(np
, np
->phy_addr
, MII_STAT1000
);
1129 if (unlikely(err
< 0))
1133 estatus
= ctrl1000
= stat1000
= 0;
1136 if (bmsr
& BMSR_ANEGCAPABLE
)
1137 supported
|= SUPPORTED_Autoneg
;
1138 if (bmsr
& BMSR_10HALF
)
1139 supported
|= SUPPORTED_10baseT_Half
;
1140 if (bmsr
& BMSR_10FULL
)
1141 supported
|= SUPPORTED_10baseT_Full
;
1142 if (bmsr
& BMSR_100HALF
)
1143 supported
|= SUPPORTED_100baseT_Half
;
1144 if (bmsr
& BMSR_100FULL
)
1145 supported
|= SUPPORTED_100baseT_Full
;
1146 if (estatus
& ESTATUS_1000_THALF
)
1147 supported
|= SUPPORTED_1000baseT_Half
;
1148 if (estatus
& ESTATUS_1000_TFULL
)
1149 supported
|= SUPPORTED_1000baseT_Full
;
1150 lp
->supported
= supported
;
1153 if (advert
& ADVERTISE_10HALF
)
1154 advertising
|= ADVERTISED_10baseT_Half
;
1155 if (advert
& ADVERTISE_10FULL
)
1156 advertising
|= ADVERTISED_10baseT_Full
;
1157 if (advert
& ADVERTISE_100HALF
)
1158 advertising
|= ADVERTISED_100baseT_Half
;
1159 if (advert
& ADVERTISE_100FULL
)
1160 advertising
|= ADVERTISED_100baseT_Full
;
1161 if (ctrl1000
& ADVERTISE_1000HALF
)
1162 advertising
|= ADVERTISED_1000baseT_Half
;
1163 if (ctrl1000
& ADVERTISE_1000FULL
)
1164 advertising
|= ADVERTISED_1000baseT_Full
;
1166 if (bmcr
& BMCR_ANENABLE
) {
1169 lp
->active_autoneg
= 1;
1170 advertising
|= ADVERTISED_Autoneg
;
1173 neg1000
= (ctrl1000
<< 2) & stat1000
;
1175 if (neg1000
& (LPA_1000FULL
| LPA_1000HALF
))
1176 active_speed
= SPEED_1000
;
1177 else if (neg
& LPA_100
)
1178 active_speed
= SPEED_100
;
1179 else if (neg
& (LPA_10HALF
| LPA_10FULL
))
1180 active_speed
= SPEED_10
;
1182 active_speed
= SPEED_INVALID
;
1184 if ((neg1000
& LPA_1000FULL
) || (neg
& LPA_DUPLEX
))
1185 active_duplex
= DUPLEX_FULL
;
1186 else if (active_speed
!= SPEED_INVALID
)
1187 active_duplex
= DUPLEX_HALF
;
1189 active_duplex
= DUPLEX_INVALID
;
1191 lp
->active_autoneg
= 0;
1193 if ((bmcr
& BMCR_SPEED1000
) && !(bmcr
& BMCR_SPEED100
))
1194 active_speed
= SPEED_1000
;
1195 else if (bmcr
& BMCR_SPEED100
)
1196 active_speed
= SPEED_100
;
1198 active_speed
= SPEED_10
;
1200 if (bmcr
& BMCR_FULLDPLX
)
1201 active_duplex
= DUPLEX_FULL
;
1203 active_duplex
= DUPLEX_HALF
;
1206 lp
->active_advertising
= advertising
;
1207 lp
->active_speed
= active_speed
;
1208 lp
->active_duplex
= active_duplex
;
1209 *link_up_p
= !!(bmsr
& BMSR_LSTATUS
);
1214 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
1216 struct niu_link_config
*lp
= &np
->link_config
;
1217 u16 current_speed
, bmsr
;
1218 unsigned long flags
;
1223 current_speed
= SPEED_INVALID
;
1224 current_duplex
= DUPLEX_INVALID
;
1226 spin_lock_irqsave(&np
->lock
, flags
);
1230 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1235 if (bmsr
& BMSR_LSTATUS
) {
1236 u16 adv
, lpa
, common
, estat
;
1238 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1243 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1250 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1255 current_speed
= SPEED_1000
;
1256 current_duplex
= DUPLEX_FULL
;
1259 lp
->active_speed
= current_speed
;
1260 lp
->active_duplex
= current_duplex
;
1264 spin_unlock_irqrestore(&np
->lock
, flags
);
1266 *link_up_p
= link_up
;
1270 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1272 struct niu_link_config
*lp
= &np
->link_config
;
1273 unsigned long flags
;
1276 spin_lock_irqsave(&np
->lock
, flags
);
1278 err
= link_status_mii(np
, link_up_p
);
1279 lp
->supported
|= SUPPORTED_TP
;
1280 lp
->active_advertising
|= ADVERTISED_TP
;
1282 spin_unlock_irqrestore(&np
->lock
, flags
);
1286 static int bcm8704_reset(struct niu
*np
)
1290 err
= mdio_read(np
, np
->phy_addr
,
1291 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1292 if (err
< 0 || err
== 0xffff)
1295 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1301 while (--limit
>= 0) {
1302 err
= mdio_read(np
, np
->phy_addr
,
1303 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1306 if (!(err
& BMCR_RESET
))
1310 netdev_err(np
->dev
, "Port %u PHY will not reset (bmcr=%04x)\n",
1311 np
->port
, (err
& 0xffff));
1317 /* When written, certain PHY registers need to be read back twice
1318 * in order for the bits to settle properly.
1320 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
1322 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1325 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1331 static int bcm8706_init_user_dev3(struct niu
*np
)
1336 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1337 BCM8704_USER_OPT_DIGITAL_CTRL
);
1340 err
&= ~USER_ODIG_CTRL_GPIOS
;
1341 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1342 err
|= USER_ODIG_CTRL_RESV2
;
1343 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1344 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1353 static int bcm8704_init_user_dev3(struct niu
*np
)
1357 err
= mdio_write(np
, np
->phy_addr
,
1358 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1359 (USER_CONTROL_OPTXRST_LVL
|
1360 USER_CONTROL_OPBIASFLT_LVL
|
1361 USER_CONTROL_OBTMPFLT_LVL
|
1362 USER_CONTROL_OPPRFLT_LVL
|
1363 USER_CONTROL_OPTXFLT_LVL
|
1364 USER_CONTROL_OPRXLOS_LVL
|
1365 USER_CONTROL_OPRXFLT_LVL
|
1366 USER_CONTROL_OPTXON_LVL
|
1367 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1371 err
= mdio_write(np
, np
->phy_addr
,
1372 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1373 (USER_PMD_TX_CTL_XFP_CLKEN
|
1374 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1375 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1376 USER_PMD_TX_CTL_TSCK_LPWREN
));
1380 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1383 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1387 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1388 BCM8704_USER_OPT_DIGITAL_CTRL
);
1391 err
&= ~USER_ODIG_CTRL_GPIOS
;
1392 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1393 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1394 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1403 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1407 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1408 MRVL88X2011_LED_8_TO_11_CTL
);
1412 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1413 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1415 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1416 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1419 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1423 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1424 MRVL88X2011_LED_BLINK_CTL
);
1426 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1429 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1430 MRVL88X2011_LED_BLINK_CTL
, err
);
1436 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1440 /* Set LED functions */
1441 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1446 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1450 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1451 MRVL88X2011_GENERAL_CTL
);
1455 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1457 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1458 MRVL88X2011_GENERAL_CTL
, err
);
1462 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1463 MRVL88X2011_PMA_PMD_CTL_1
);
1467 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1468 err
|= MRVL88X2011_LOOPBACK
;
1470 err
&= ~MRVL88X2011_LOOPBACK
;
1472 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1473 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1478 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1479 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1483 static int xcvr_diag_bcm870x(struct niu
*np
)
1485 u16 analog_stat0
, tx_alarm_status
;
1489 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1493 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np
->port
, err
);
1495 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1498 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np
->port
, err
);
1500 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1504 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np
->port
, err
);
1507 /* XXX dig this out it might not be so useful XXX */
1508 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1509 BCM8704_USER_ANALOG_STATUS0
);
1512 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1513 BCM8704_USER_ANALOG_STATUS0
);
1518 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1519 BCM8704_USER_TX_ALARM_STATUS
);
1522 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1523 BCM8704_USER_TX_ALARM_STATUS
);
1526 tx_alarm_status
= err
;
1528 if (analog_stat0
!= 0x03fc) {
1529 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1530 pr_info("Port %u cable not connected or bad cable\n",
1532 } else if (analog_stat0
== 0x639c) {
1533 pr_info("Port %u optical module is bad or missing\n",
1541 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1543 struct niu_link_config
*lp
= &np
->link_config
;
1546 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1551 err
&= ~BMCR_LOOPBACK
;
1553 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1554 err
|= BMCR_LOOPBACK
;
1556 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1564 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1569 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1570 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1573 val
= nr64_mac(XMAC_CONFIG
);
1574 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1575 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1576 nw64_mac(XMAC_CONFIG
, val
);
1578 val
= nr64(MIF_CONFIG
);
1579 val
|= MIF_CONFIG_INDIRECT_MODE
;
1580 nw64(MIF_CONFIG
, val
);
1582 err
= bcm8704_reset(np
);
1586 err
= xcvr_10g_set_lb_bcm870x(np
);
1590 err
= bcm8706_init_user_dev3(np
);
1594 err
= xcvr_diag_bcm870x(np
);
1601 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1605 err
= bcm8704_reset(np
);
1609 err
= bcm8704_init_user_dev3(np
);
1613 err
= xcvr_10g_set_lb_bcm870x(np
);
1617 err
= xcvr_diag_bcm870x(np
);
1624 static int xcvr_init_10g(struct niu
*np
)
1629 val
= nr64_mac(XMAC_CONFIG
);
1630 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1631 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1632 nw64_mac(XMAC_CONFIG
, val
);
1634 /* XXX shared resource, lock parent XXX */
1635 val
= nr64(MIF_CONFIG
);
1636 val
|= MIF_CONFIG_INDIRECT_MODE
;
1637 nw64(MIF_CONFIG
, val
);
1639 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1640 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1642 /* handle different phy types */
1643 switch (phy_id
& NIU_PHY_ID_MASK
) {
1644 case NIU_PHY_ID_MRVL88X2011
:
1645 err
= xcvr_init_10g_mrvl88x2011(np
);
1648 default: /* bcom 8704 */
1649 err
= xcvr_init_10g_bcm8704(np
);
1656 static int mii_reset(struct niu
*np
)
1660 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1665 while (--limit
>= 0) {
1667 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1670 if (!(err
& BMCR_RESET
))
1674 netdev_err(np
->dev
, "Port %u MII would not reset, bmcr[%04x]\n",
1682 static int xcvr_init_1g_rgmii(struct niu
*np
)
1686 u16 bmcr
, bmsr
, estat
;
1688 val
= nr64(MIF_CONFIG
);
1689 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1690 nw64(MIF_CONFIG
, val
);
1692 err
= mii_reset(np
);
1696 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1702 if (bmsr
& BMSR_ESTATEN
) {
1703 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1710 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1714 if (bmsr
& BMSR_ESTATEN
) {
1717 if (estat
& ESTATUS_1000_TFULL
)
1718 ctrl1000
|= ADVERTISE_1000FULL
;
1719 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1724 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1726 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1730 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1733 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1735 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1742 static int mii_init_common(struct niu
*np
)
1744 struct niu_link_config
*lp
= &np
->link_config
;
1745 u16 bmcr
, bmsr
, adv
, estat
;
1748 err
= mii_reset(np
);
1752 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1758 if (bmsr
& BMSR_ESTATEN
) {
1759 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1766 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1770 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1771 bmcr
|= BMCR_LOOPBACK
;
1772 if (lp
->active_speed
== SPEED_1000
)
1773 bmcr
|= BMCR_SPEED1000
;
1774 if (lp
->active_duplex
== DUPLEX_FULL
)
1775 bmcr
|= BMCR_FULLDPLX
;
1778 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1781 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1782 BCM5464R_AUX_CTL_WRITE_1
);
1783 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1791 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1792 if ((bmsr
& BMSR_10HALF
) &&
1793 (lp
->advertising
& ADVERTISED_10baseT_Half
))
1794 adv
|= ADVERTISE_10HALF
;
1795 if ((bmsr
& BMSR_10FULL
) &&
1796 (lp
->advertising
& ADVERTISED_10baseT_Full
))
1797 adv
|= ADVERTISE_10FULL
;
1798 if ((bmsr
& BMSR_100HALF
) &&
1799 (lp
->advertising
& ADVERTISED_100baseT_Half
))
1800 adv
|= ADVERTISE_100HALF
;
1801 if ((bmsr
& BMSR_100FULL
) &&
1802 (lp
->advertising
& ADVERTISED_100baseT_Full
))
1803 adv
|= ADVERTISE_100FULL
;
1804 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1808 if (likely(bmsr
& BMSR_ESTATEN
)) {
1810 if ((estat
& ESTATUS_1000_THALF
) &&
1811 (lp
->advertising
& ADVERTISED_1000baseT_Half
))
1812 ctrl1000
|= ADVERTISE_1000HALF
;
1813 if ((estat
& ESTATUS_1000_TFULL
) &&
1814 (lp
->advertising
& ADVERTISED_1000baseT_Full
))
1815 ctrl1000
|= ADVERTISE_1000FULL
;
1816 err
= mii_write(np
, np
->phy_addr
,
1817 MII_CTRL1000
, ctrl1000
);
1822 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1827 if (lp
->duplex
== DUPLEX_FULL
) {
1828 bmcr
|= BMCR_FULLDPLX
;
1830 } else if (lp
->duplex
== DUPLEX_HALF
)
1835 if (lp
->speed
== SPEED_1000
) {
1836 /* if X-full requested while not supported, or
1837 X-half requested while not supported... */
1838 if ((fulldpx
&& !(estat
& ESTATUS_1000_TFULL
)) ||
1839 (!fulldpx
&& !(estat
& ESTATUS_1000_THALF
)))
1841 bmcr
|= BMCR_SPEED1000
;
1842 } else if (lp
->speed
== SPEED_100
) {
1843 if ((fulldpx
&& !(bmsr
& BMSR_100FULL
)) ||
1844 (!fulldpx
&& !(bmsr
& BMSR_100HALF
)))
1846 bmcr
|= BMCR_SPEED100
;
1847 } else if (lp
->speed
== SPEED_10
) {
1848 if ((fulldpx
&& !(bmsr
& BMSR_10FULL
)) ||
1849 (!fulldpx
&& !(bmsr
& BMSR_10HALF
)))
1855 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1860 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1865 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1870 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1871 np
->port
, bmcr
, bmsr
);
1877 static int xcvr_init_1g(struct niu
*np
)
1881 /* XXX shared resource, lock parent XXX */
1882 val
= nr64(MIF_CONFIG
);
1883 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1884 nw64(MIF_CONFIG
, val
);
1886 return mii_init_common(np
);
1889 static int niu_xcvr_init(struct niu
*np
)
1891 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1896 err
= ops
->xcvr_init(np
);
1901 static int niu_serdes_init(struct niu
*np
)
1903 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1907 if (ops
->serdes_init
)
1908 err
= ops
->serdes_init(np
);
1913 static void niu_init_xif(struct niu
*);
1914 static void niu_handle_led(struct niu
*, int status
);
1916 static int niu_link_status_common(struct niu
*np
, int link_up
)
1918 struct niu_link_config
*lp
= &np
->link_config
;
1919 struct net_device
*dev
= np
->dev
;
1920 unsigned long flags
;
1922 if (!netif_carrier_ok(dev
) && link_up
) {
1923 netif_info(np
, link
, dev
, "Link is up at %s, %s duplex\n",
1924 lp
->active_speed
== SPEED_10000
? "10Gb/sec" :
1925 lp
->active_speed
== SPEED_1000
? "1Gb/sec" :
1926 lp
->active_speed
== SPEED_100
? "100Mbit/sec" :
1928 lp
->active_duplex
== DUPLEX_FULL
? "full" : "half");
1930 spin_lock_irqsave(&np
->lock
, flags
);
1932 niu_handle_led(np
, 1);
1933 spin_unlock_irqrestore(&np
->lock
, flags
);
1935 netif_carrier_on(dev
);
1936 } else if (netif_carrier_ok(dev
) && !link_up
) {
1937 netif_warn(np
, link
, dev
, "Link is down\n");
1938 spin_lock_irqsave(&np
->lock
, flags
);
1939 niu_handle_led(np
, 0);
1940 spin_unlock_irqrestore(&np
->lock
, flags
);
1941 netif_carrier_off(dev
);
1947 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1949 int err
, link_up
, pma_status
, pcs_status
;
1953 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1954 MRVL88X2011_10G_PMD_STATUS_2
);
1958 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1959 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1960 MRVL88X2011_PMA_PMD_STATUS_1
);
1964 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1966 /* Check PMC Register : 3.0001.2 == 1: read twice */
1967 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1968 MRVL88X2011_PMA_PMD_STATUS_1
);
1972 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1973 MRVL88X2011_PMA_PMD_STATUS_1
);
1977 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1979 /* Check XGXS Register : 4.0018.[0-3,12] */
1980 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
1981 MRVL88X2011_10G_XGXS_LANE_STAT
);
1985 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
1986 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
1987 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
1989 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
1991 np
->link_config
.active_speed
= SPEED_10000
;
1992 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1995 mrvl88x2011_act_led(np
, (link_up
?
1996 MRVL88X2011_LED_CTL_PCS_ACT
:
1997 MRVL88X2011_LED_CTL_OFF
));
1999 *link_up_p
= link_up
;
2003 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
2008 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2009 BCM8704_PMD_RCV_SIGDET
);
2010 if (err
< 0 || err
== 0xffff)
2012 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2017 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2018 BCM8704_PCS_10G_R_STATUS
);
2022 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2027 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2028 BCM8704_PHYXS_XGXS_LANE_STAT
);
2031 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2032 PHYXS_XGXS_LANE_STAT_MAGIC
|
2033 PHYXS_XGXS_LANE_STAT_PATTEST
|
2034 PHYXS_XGXS_LANE_STAT_LANE3
|
2035 PHYXS_XGXS_LANE_STAT_LANE2
|
2036 PHYXS_XGXS_LANE_STAT_LANE1
|
2037 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2039 np
->link_config
.active_speed
= SPEED_INVALID
;
2040 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
2045 np
->link_config
.active_speed
= SPEED_10000
;
2046 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2050 *link_up_p
= link_up
;
2054 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
2060 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2061 BCM8704_PMD_RCV_SIGDET
);
2064 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2069 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2070 BCM8704_PCS_10G_R_STATUS
);
2073 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2078 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2079 BCM8704_PHYXS_XGXS_LANE_STAT
);
2083 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2084 PHYXS_XGXS_LANE_STAT_MAGIC
|
2085 PHYXS_XGXS_LANE_STAT_LANE3
|
2086 PHYXS_XGXS_LANE_STAT_LANE2
|
2087 PHYXS_XGXS_LANE_STAT_LANE1
|
2088 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2094 np
->link_config
.active_speed
= SPEED_10000
;
2095 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2099 *link_up_p
= link_up
;
2103 static int link_status_10g(struct niu
*np
, int *link_up_p
)
2105 unsigned long flags
;
2108 spin_lock_irqsave(&np
->lock
, flags
);
2110 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2113 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
2114 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
2116 /* handle different phy types */
2117 switch (phy_id
& NIU_PHY_ID_MASK
) {
2118 case NIU_PHY_ID_MRVL88X2011
:
2119 err
= link_status_10g_mrvl(np
, link_up_p
);
2122 default: /* bcom 8704 */
2123 err
= link_status_10g_bcom(np
, link_up_p
);
2128 spin_unlock_irqrestore(&np
->lock
, flags
);
2133 static int niu_10g_phy_present(struct niu
*np
)
2137 sig
= nr64(ESR_INT_SIGNALS
);
2140 mask
= ESR_INT_SIGNALS_P0_BITS
;
2141 val
= (ESR_INT_SRDY0_P0
|
2144 ESR_INT_XDP_P0_CH3
|
2145 ESR_INT_XDP_P0_CH2
|
2146 ESR_INT_XDP_P0_CH1
|
2147 ESR_INT_XDP_P0_CH0
);
2151 mask
= ESR_INT_SIGNALS_P1_BITS
;
2152 val
= (ESR_INT_SRDY0_P1
|
2155 ESR_INT_XDP_P1_CH3
|
2156 ESR_INT_XDP_P1_CH2
|
2157 ESR_INT_XDP_P1_CH1
|
2158 ESR_INT_XDP_P1_CH0
);
2165 if ((sig
& mask
) != val
)
2170 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
2172 unsigned long flags
;
2175 int phy_present_prev
;
2177 spin_lock_irqsave(&np
->lock
, flags
);
2179 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2180 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
2182 phy_present
= niu_10g_phy_present(np
);
2183 if (phy_present
!= phy_present_prev
) {
2186 /* A NEM was just plugged in */
2187 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2188 if (np
->phy_ops
->xcvr_init
)
2189 err
= np
->phy_ops
->xcvr_init(np
);
2191 err
= mdio_read(np
, np
->phy_addr
,
2192 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
2193 if (err
== 0xffff) {
2194 /* No mdio, back-to-back XAUI */
2198 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2201 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2203 netif_warn(np
, link
, np
->dev
,
2204 "Hotplug PHY Removed\n");
2208 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) {
2209 err
= link_status_10g_bcm8706(np
, link_up_p
);
2210 if (err
== 0xffff) {
2211 /* No mdio, back-to-back XAUI: it is C10NEM */
2213 np
->link_config
.active_speed
= SPEED_10000
;
2214 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2219 spin_unlock_irqrestore(&np
->lock
, flags
);
2224 static int niu_link_status(struct niu
*np
, int *link_up_p
)
2226 const struct niu_phy_ops
*ops
= np
->phy_ops
;
2230 if (ops
->link_status
)
2231 err
= ops
->link_status(np
, link_up_p
);
2236 static void niu_timer(unsigned long __opaque
)
2238 struct niu
*np
= (struct niu
*) __opaque
;
2242 err
= niu_link_status(np
, &link_up
);
2244 niu_link_status_common(np
, link_up
);
2246 if (netif_carrier_ok(np
->dev
))
2250 np
->timer
.expires
= jiffies
+ off
;
2252 add_timer(&np
->timer
);
2255 static const struct niu_phy_ops phy_ops_10g_serdes
= {
2256 .serdes_init
= serdes_init_10g_serdes
,
2257 .link_status
= link_status_10g_serdes
,
2260 static const struct niu_phy_ops phy_ops_10g_serdes_niu
= {
2261 .serdes_init
= serdes_init_niu_10g_serdes
,
2262 .link_status
= link_status_10g_serdes
,
2265 static const struct niu_phy_ops phy_ops_1g_serdes_niu
= {
2266 .serdes_init
= serdes_init_niu_1g_serdes
,
2267 .link_status
= link_status_1g_serdes
,
2270 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
2271 .xcvr_init
= xcvr_init_1g_rgmii
,
2272 .link_status
= link_status_1g_rgmii
,
2275 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
2276 .serdes_init
= serdes_init_niu_10g_fiber
,
2277 .xcvr_init
= xcvr_init_10g
,
2278 .link_status
= link_status_10g
,
2281 static const struct niu_phy_ops phy_ops_10g_fiber
= {
2282 .serdes_init
= serdes_init_10g
,
2283 .xcvr_init
= xcvr_init_10g
,
2284 .link_status
= link_status_10g
,
2287 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
2288 .serdes_init
= serdes_init_10g
,
2289 .xcvr_init
= xcvr_init_10g_bcm8706
,
2290 .link_status
= link_status_10g_hotplug
,
2293 static const struct niu_phy_ops phy_ops_niu_10g_hotplug
= {
2294 .serdes_init
= serdes_init_niu_10g_fiber
,
2295 .xcvr_init
= xcvr_init_10g_bcm8706
,
2296 .link_status
= link_status_10g_hotplug
,
2299 static const struct niu_phy_ops phy_ops_10g_copper
= {
2300 .serdes_init
= serdes_init_10g
,
2301 .link_status
= link_status_10g
, /* XXX */
2304 static const struct niu_phy_ops phy_ops_1g_fiber
= {
2305 .serdes_init
= serdes_init_1g
,
2306 .xcvr_init
= xcvr_init_1g
,
2307 .link_status
= link_status_1g
,
2310 static const struct niu_phy_ops phy_ops_1g_copper
= {
2311 .xcvr_init
= xcvr_init_1g
,
2312 .link_status
= link_status_1g
,
2315 struct niu_phy_template
{
2316 const struct niu_phy_ops
*ops
;
2320 static const struct niu_phy_template phy_template_niu_10g_fiber
= {
2321 .ops
= &phy_ops_10g_fiber_niu
,
2322 .phy_addr_base
= 16,
2325 static const struct niu_phy_template phy_template_niu_10g_serdes
= {
2326 .ops
= &phy_ops_10g_serdes_niu
,
2330 static const struct niu_phy_template phy_template_niu_1g_serdes
= {
2331 .ops
= &phy_ops_1g_serdes_niu
,
2335 static const struct niu_phy_template phy_template_10g_fiber
= {
2336 .ops
= &phy_ops_10g_fiber
,
2340 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2341 .ops
= &phy_ops_10g_fiber_hotplug
,
2345 static const struct niu_phy_template phy_template_niu_10g_hotplug
= {
2346 .ops
= &phy_ops_niu_10g_hotplug
,
2350 static const struct niu_phy_template phy_template_10g_copper
= {
2351 .ops
= &phy_ops_10g_copper
,
2352 .phy_addr_base
= 10,
2355 static const struct niu_phy_template phy_template_1g_fiber
= {
2356 .ops
= &phy_ops_1g_fiber
,
2360 static const struct niu_phy_template phy_template_1g_copper
= {
2361 .ops
= &phy_ops_1g_copper
,
2365 static const struct niu_phy_template phy_template_1g_rgmii
= {
2366 .ops
= &phy_ops_1g_rgmii
,
2370 static const struct niu_phy_template phy_template_10g_serdes
= {
2371 .ops
= &phy_ops_10g_serdes
,
2375 static int niu_atca_port_num
[4] = {
2379 static int serdes_init_10g_serdes(struct niu
*np
)
2381 struct niu_link_config
*lp
= &np
->link_config
;
2382 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2383 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2388 reset_val
= ENET_SERDES_RESET_0
;
2389 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2390 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2391 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2394 reset_val
= ENET_SERDES_RESET_1
;
2395 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2396 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2397 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2403 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2404 ENET_SERDES_CTRL_SDET_1
|
2405 ENET_SERDES_CTRL_SDET_2
|
2406 ENET_SERDES_CTRL_SDET_3
|
2407 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2408 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2409 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2410 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2411 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2412 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2413 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2417 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2418 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2419 ENET_SERDES_TEST_MD_0_SHIFT
) |
2420 (ENET_TEST_MD_PAD_LOOPBACK
<<
2421 ENET_SERDES_TEST_MD_1_SHIFT
) |
2422 (ENET_TEST_MD_PAD_LOOPBACK
<<
2423 ENET_SERDES_TEST_MD_2_SHIFT
) |
2424 (ENET_TEST_MD_PAD_LOOPBACK
<<
2425 ENET_SERDES_TEST_MD_3_SHIFT
));
2429 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2430 nw64(ctrl_reg
, ctrl_val
);
2431 nw64(test_cfg_reg
, test_cfg_val
);
2433 /* Initialize all 4 lanes of the SERDES. */
2434 for (i
= 0; i
< 4; i
++) {
2435 u32 rxtx_ctrl
, glue0
;
2438 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2441 err
= esr_read_glue0(np
, i
, &glue0
);
2445 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2446 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2447 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2449 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2450 ESR_GLUE_CTRL0_THCNT
|
2451 ESR_GLUE_CTRL0_BLTIME
);
2452 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2453 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2454 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2455 (BLTIME_300_CYCLES
<<
2456 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2458 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2461 err
= esr_write_glue0(np
, i
, glue0
);
2467 sig
= nr64(ESR_INT_SIGNALS
);
2470 mask
= ESR_INT_SIGNALS_P0_BITS
;
2471 val
= (ESR_INT_SRDY0_P0
|
2474 ESR_INT_XDP_P0_CH3
|
2475 ESR_INT_XDP_P0_CH2
|
2476 ESR_INT_XDP_P0_CH1
|
2477 ESR_INT_XDP_P0_CH0
);
2481 mask
= ESR_INT_SIGNALS_P1_BITS
;
2482 val
= (ESR_INT_SRDY0_P1
|
2485 ESR_INT_XDP_P1_CH3
|
2486 ESR_INT_XDP_P1_CH2
|
2487 ESR_INT_XDP_P1_CH1
|
2488 ESR_INT_XDP_P1_CH0
);
2495 if ((sig
& mask
) != val
) {
2497 err
= serdes_init_1g_serdes(np
);
2499 np
->flags
&= ~NIU_FLAGS_10G
;
2500 np
->mac_xcvr
= MAC_XCVR_PCS
;
2502 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
2511 static int niu_determine_phy_disposition(struct niu
*np
)
2513 struct niu_parent
*parent
= np
->parent
;
2514 u8 plat_type
= parent
->plat_type
;
2515 const struct niu_phy_template
*tp
;
2516 u32 phy_addr_off
= 0;
2518 if (plat_type
== PLAT_TYPE_NIU
) {
2522 NIU_FLAGS_XCVR_SERDES
)) {
2523 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2525 tp
= &phy_template_niu_10g_serdes
;
2527 case NIU_FLAGS_XCVR_SERDES
:
2529 tp
= &phy_template_niu_1g_serdes
;
2531 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2534 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2535 tp
= &phy_template_niu_10g_hotplug
;
2541 tp
= &phy_template_niu_10g_fiber
;
2542 phy_addr_off
+= np
->port
;
2550 NIU_FLAGS_XCVR_SERDES
)) {
2553 tp
= &phy_template_1g_copper
;
2554 if (plat_type
== PLAT_TYPE_VF_P0
)
2556 else if (plat_type
== PLAT_TYPE_VF_P1
)
2559 phy_addr_off
+= (np
->port
^ 0x3);
2564 tp
= &phy_template_10g_copper
;
2567 case NIU_FLAGS_FIBER
:
2569 tp
= &phy_template_1g_fiber
;
2572 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2574 tp
= &phy_template_10g_fiber
;
2575 if (plat_type
== PLAT_TYPE_VF_P0
||
2576 plat_type
== PLAT_TYPE_VF_P1
)
2578 phy_addr_off
+= np
->port
;
2579 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2580 tp
= &phy_template_10g_fiber_hotplug
;
2588 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2589 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2590 case NIU_FLAGS_XCVR_SERDES
:
2594 tp
= &phy_template_10g_serdes
;
2598 tp
= &phy_template_1g_rgmii
;
2604 phy_addr_off
= niu_atca_port_num
[np
->port
];
2612 np
->phy_ops
= tp
->ops
;
2613 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2618 static int niu_init_link(struct niu
*np
)
2620 struct niu_parent
*parent
= np
->parent
;
2623 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2624 err
= niu_xcvr_init(np
);
2629 err
= niu_serdes_init(np
);
2630 if (err
&& !(np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2633 err
= niu_xcvr_init(np
);
2634 if (!err
|| (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2635 niu_link_status(np
, &ignore
);
2639 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2641 u16 reg0
= addr
[4] << 8 | addr
[5];
2642 u16 reg1
= addr
[2] << 8 | addr
[3];
2643 u16 reg2
= addr
[0] << 8 | addr
[1];
2645 if (np
->flags
& NIU_FLAGS_XMAC
) {
2646 nw64_mac(XMAC_ADDR0
, reg0
);
2647 nw64_mac(XMAC_ADDR1
, reg1
);
2648 nw64_mac(XMAC_ADDR2
, reg2
);
2650 nw64_mac(BMAC_ADDR0
, reg0
);
2651 nw64_mac(BMAC_ADDR1
, reg1
);
2652 nw64_mac(BMAC_ADDR2
, reg2
);
2656 static int niu_num_alt_addr(struct niu
*np
)
2658 if (np
->flags
& NIU_FLAGS_XMAC
)
2659 return XMAC_NUM_ALT_ADDR
;
2661 return BMAC_NUM_ALT_ADDR
;
2664 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2666 u16 reg0
= addr
[4] << 8 | addr
[5];
2667 u16 reg1
= addr
[2] << 8 | addr
[3];
2668 u16 reg2
= addr
[0] << 8 | addr
[1];
2670 if (index
>= niu_num_alt_addr(np
))
2673 if (np
->flags
& NIU_FLAGS_XMAC
) {
2674 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2675 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2676 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2678 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2679 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2680 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2686 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2691 if (index
>= niu_num_alt_addr(np
))
2694 if (np
->flags
& NIU_FLAGS_XMAC
) {
2695 reg
= XMAC_ADDR_CMPEN
;
2698 reg
= BMAC_ADDR_CMPEN
;
2699 mask
= 1 << (index
+ 1);
2702 val
= nr64_mac(reg
);
2712 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2713 int num
, int mac_pref
)
2715 u64 val
= nr64_mac(reg
);
2716 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2719 val
|= HOST_INFO_MPR
;
2723 static int __set_rdc_table_num(struct niu
*np
,
2724 int xmac_index
, int bmac_index
,
2725 int rdc_table_num
, int mac_pref
)
2729 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2731 if (np
->flags
& NIU_FLAGS_XMAC
)
2732 reg
= XMAC_HOST_INFO(xmac_index
);
2734 reg
= BMAC_HOST_INFO(bmac_index
);
2735 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2739 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2742 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2745 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2748 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2751 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2752 int table_num
, int mac_pref
)
2754 if (idx
>= niu_num_alt_addr(np
))
2756 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2759 static u64
vlan_entry_set_parity(u64 reg_val
)
2764 port01_mask
= 0x00ff;
2765 port23_mask
= 0xff00;
2767 if (hweight64(reg_val
& port01_mask
) & 1)
2768 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2770 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2772 if (hweight64(reg_val
& port23_mask
) & 1)
2773 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2775 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2780 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2781 int port
, int vpr
, int rdc_table
)
2783 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2785 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2786 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2787 ENET_VLAN_TBL_SHIFT(port
));
2789 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2790 ENET_VLAN_TBL_SHIFT(port
));
2791 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2793 reg_val
= vlan_entry_set_parity(reg_val
);
2795 nw64(ENET_VLAN_TBL(index
), reg_val
);
2798 static void vlan_tbl_clear(struct niu
*np
)
2802 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2803 nw64(ENET_VLAN_TBL(i
), 0);
2806 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2810 while (--limit
> 0) {
2811 if (nr64(TCAM_CTL
) & bit
)
2821 static int tcam_flush(struct niu
*np
, int index
)
2823 nw64(TCAM_KEY_0
, 0x00);
2824 nw64(TCAM_KEY_MASK_0
, 0xff);
2825 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2827 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2831 static int tcam_read(struct niu
*np
, int index
,
2832 u64
*key
, u64
*mask
)
2836 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2837 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2839 key
[0] = nr64(TCAM_KEY_0
);
2840 key
[1] = nr64(TCAM_KEY_1
);
2841 key
[2] = nr64(TCAM_KEY_2
);
2842 key
[3] = nr64(TCAM_KEY_3
);
2843 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2844 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2845 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2846 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2852 static int tcam_write(struct niu
*np
, int index
,
2853 u64
*key
, u64
*mask
)
2855 nw64(TCAM_KEY_0
, key
[0]);
2856 nw64(TCAM_KEY_1
, key
[1]);
2857 nw64(TCAM_KEY_2
, key
[2]);
2858 nw64(TCAM_KEY_3
, key
[3]);
2859 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2860 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2861 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2862 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2863 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2865 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2869 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2873 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2874 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2876 *data
= nr64(TCAM_KEY_1
);
2882 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2884 nw64(TCAM_KEY_1
, assoc_data
);
2885 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2887 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2890 static void tcam_enable(struct niu
*np
, int on
)
2892 u64 val
= nr64(FFLP_CFG_1
);
2895 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2897 val
|= FFLP_CFG_1_TCAM_DIS
;
2898 nw64(FFLP_CFG_1
, val
);
2901 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2903 u64 val
= nr64(FFLP_CFG_1
);
2905 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2907 FFLP_CFG_1_CAMRATIO
);
2908 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2909 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2910 nw64(FFLP_CFG_1
, val
);
2912 val
= nr64(FFLP_CFG_1
);
2913 val
|= FFLP_CFG_1_FFLPINITDONE
;
2914 nw64(FFLP_CFG_1
, val
);
2917 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2923 if (class < CLASS_CODE_ETHERTYPE1
||
2924 class > CLASS_CODE_ETHERTYPE2
)
2927 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2939 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2945 if (class < CLASS_CODE_ETHERTYPE1
||
2946 class > CLASS_CODE_ETHERTYPE2
||
2947 (ether_type
& ~(u64
)0xffff) != 0)
2950 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2952 val
&= ~L2_CLS_ETYPE
;
2953 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2960 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2966 if (class < CLASS_CODE_USER_PROG1
||
2967 class > CLASS_CODE_USER_PROG4
)
2970 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2973 val
|= L3_CLS_VALID
;
2975 val
&= ~L3_CLS_VALID
;
2981 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2982 int ipv6
, u64 protocol_id
,
2983 u64 tos_mask
, u64 tos_val
)
2988 if (class < CLASS_CODE_USER_PROG1
||
2989 class > CLASS_CODE_USER_PROG4
||
2990 (protocol_id
& ~(u64
)0xff) != 0 ||
2991 (tos_mask
& ~(u64
)0xff) != 0 ||
2992 (tos_val
& ~(u64
)0xff) != 0)
2995 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2997 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
2998 L3_CLS_TOSMASK
| L3_CLS_TOS
);
3000 val
|= L3_CLS_IPVER
;
3001 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
3002 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
3003 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
3009 static int tcam_early_init(struct niu
*np
)
3015 tcam_set_lat_and_ratio(np
,
3016 DEFAULT_TCAM_LATENCY
,
3017 DEFAULT_TCAM_ACCESS_RATIO
);
3018 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
3019 err
= tcam_user_eth_class_enable(np
, i
, 0);
3023 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
3024 err
= tcam_user_ip_class_enable(np
, i
, 0);
3032 static int tcam_flush_all(struct niu
*np
)
3036 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
3037 int err
= tcam_flush(np
, i
);
3044 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
3046 return (u64
)index
| (num_entries
== 1 ? HASH_TBL_ADDR_AUTOINC
: 0);
3050 static int hash_read(struct niu
*np
, unsigned long partition
,
3051 unsigned long index
, unsigned long num_entries
,
3054 u64 val
= hash_addr_regval(index
, num_entries
);
3057 if (partition
>= FCRAM_NUM_PARTITIONS
||
3058 index
+ num_entries
> FCRAM_SIZE
)
3061 nw64(HASH_TBL_ADDR(partition
), val
);
3062 for (i
= 0; i
< num_entries
; i
++)
3063 data
[i
] = nr64(HASH_TBL_DATA(partition
));
3069 static int hash_write(struct niu
*np
, unsigned long partition
,
3070 unsigned long index
, unsigned long num_entries
,
3073 u64 val
= hash_addr_regval(index
, num_entries
);
3076 if (partition
>= FCRAM_NUM_PARTITIONS
||
3077 index
+ (num_entries
* 8) > FCRAM_SIZE
)
3080 nw64(HASH_TBL_ADDR(partition
), val
);
3081 for (i
= 0; i
< num_entries
; i
++)
3082 nw64(HASH_TBL_DATA(partition
), data
[i
]);
3087 static void fflp_reset(struct niu
*np
)
3091 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
3093 nw64(FFLP_CFG_1
, 0);
3095 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
3096 nw64(FFLP_CFG_1
, val
);
3099 static void fflp_set_timings(struct niu
*np
)
3101 u64 val
= nr64(FFLP_CFG_1
);
3103 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
3104 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
3105 nw64(FFLP_CFG_1
, val
);
3107 val
= nr64(FFLP_CFG_1
);
3108 val
|= FFLP_CFG_1_FFLPINITDONE
;
3109 nw64(FFLP_CFG_1
, val
);
3111 val
= nr64(FCRAM_REF_TMR
);
3112 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
3113 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
3114 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
3115 nw64(FCRAM_REF_TMR
, val
);
3118 static int fflp_set_partition(struct niu
*np
, u64 partition
,
3119 u64 mask
, u64 base
, int enable
)
3124 if (partition
>= FCRAM_NUM_PARTITIONS
||
3125 (mask
& ~(u64
)0x1f) != 0 ||
3126 (base
& ~(u64
)0x1f) != 0)
3129 reg
= FLW_PRT_SEL(partition
);
3132 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
3133 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
3134 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
3136 val
|= FLW_PRT_SEL_EXT
;
3142 static int fflp_disable_all_partitions(struct niu
*np
)
3146 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
3147 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
3154 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
3156 u64 val
= nr64(FFLP_CFG_1
);
3159 val
|= FFLP_CFG_1_LLCSNAP
;
3161 val
&= ~FFLP_CFG_1_LLCSNAP
;
3162 nw64(FFLP_CFG_1
, val
);
3165 static void fflp_errors_enable(struct niu
*np
, int on
)
3167 u64 val
= nr64(FFLP_CFG_1
);
3170 val
&= ~FFLP_CFG_1_ERRORDIS
;
3172 val
|= FFLP_CFG_1_ERRORDIS
;
3173 nw64(FFLP_CFG_1
, val
);
3176 static int fflp_hash_clear(struct niu
*np
)
3178 struct fcram_hash_ipv4 ent
;
3181 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3182 memset(&ent
, 0, sizeof(ent
));
3183 ent
.header
= HASH_HEADER_EXT
;
3185 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
3186 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
3193 static int fflp_early_init(struct niu
*np
)
3195 struct niu_parent
*parent
;
3196 unsigned long flags
;
3199 niu_lock_parent(np
, flags
);
3201 parent
= np
->parent
;
3203 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
3204 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3206 fflp_set_timings(np
);
3207 err
= fflp_disable_all_partitions(np
);
3209 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3210 "fflp_disable_all_partitions failed, err=%d\n",
3216 err
= tcam_early_init(np
);
3218 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3219 "tcam_early_init failed, err=%d\n", err
);
3222 fflp_llcsnap_enable(np
, 1);
3223 fflp_errors_enable(np
, 0);
3227 err
= tcam_flush_all(np
);
3229 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3230 "tcam_flush_all failed, err=%d\n", err
);
3233 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3234 err
= fflp_hash_clear(np
);
3236 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3237 "fflp_hash_clear failed, err=%d\n",
3245 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
3248 niu_unlock_parent(np
, flags
);
3252 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3254 if (class_code
< CLASS_CODE_USER_PROG1
||
3255 class_code
> CLASS_CODE_SCTP_IPV6
)
3258 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3262 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3264 if (class_code
< CLASS_CODE_USER_PROG1
||
3265 class_code
> CLASS_CODE_SCTP_IPV6
)
3268 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3272 /* Entries for the ports are interleaved in the TCAM */
3273 static u16
tcam_get_index(struct niu
*np
, u16 idx
)
3275 /* One entry reserved for IP fragment rule */
3276 if (idx
>= (np
->clas
.tcam_sz
- 1))
3278 return np
->clas
.tcam_top
+ ((idx
+1) * np
->parent
->num_ports
);
3281 static u16
tcam_get_size(struct niu
*np
)
3283 /* One entry reserved for IP fragment rule */
3284 return np
->clas
.tcam_sz
- 1;
3287 static u16
tcam_get_valid_entry_cnt(struct niu
*np
)
3289 /* One entry reserved for IP fragment rule */
3290 return np
->clas
.tcam_valid_entries
- 1;
3293 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
3294 u32 offset
, u32 size
)
3296 int i
= skb_shinfo(skb
)->nr_frags
;
3297 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3300 frag
->page_offset
= offset
;
3304 skb
->data_len
+= size
;
3305 skb
->truesize
+= size
;
3307 skb_shinfo(skb
)->nr_frags
= i
+ 1;
3310 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
3313 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
3315 return a
& (MAX_RBR_RING_SIZE
- 1);
3318 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
3319 struct page
***link
)
3321 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
3322 struct page
*p
, **pp
;
3325 pp
= &rp
->rxhash
[h
];
3326 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
3327 if (p
->index
== addr
) {
3338 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
3340 unsigned int h
= niu_hash_rxaddr(rp
, base
);
3343 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
3344 rp
->rxhash
[h
] = page
;
3347 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
3348 gfp_t mask
, int start_index
)
3354 page
= alloc_page(mask
);
3358 addr
= np
->ops
->map_page(np
->device
, page
, 0,
3359 PAGE_SIZE
, DMA_FROM_DEVICE
);
3361 niu_hash_page(rp
, page
, addr
);
3362 if (rp
->rbr_blocks_per_page
> 1)
3363 atomic_add(rp
->rbr_blocks_per_page
- 1,
3364 &compound_head(page
)->_count
);
3366 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
3367 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
3369 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
3370 addr
+= rp
->rbr_block_size
;
3376 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3378 int index
= rp
->rbr_index
;
3381 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3382 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3384 if (unlikely(err
)) {
3389 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3390 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3391 if (rp
->rbr_index
== rp
->rbr_table_size
)
3394 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3395 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3396 rp
->rbr_pending
= 0;
3401 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3403 unsigned int index
= rp
->rcr_index
;
3408 struct page
*page
, **link
;
3414 val
= le64_to_cpup(&rp
->rcr
[index
]);
3415 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3416 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3417 page
= niu_find_rxpage(rp
, addr
, &link
);
3419 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3420 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3421 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3422 *link
= (struct page
*) page
->mapping
;
3423 np
->ops
->unmap_page(np
->device
, page
->index
,
3424 PAGE_SIZE
, DMA_FROM_DEVICE
);
3426 page
->mapping
= NULL
;
3428 rp
->rbr_refill_pending
++;
3431 index
= NEXT_RCR(rp
, index
);
3432 if (!(val
& RCR_ENTRY_MULTI
))
3436 rp
->rcr_index
= index
;
3441 static int niu_process_rx_pkt(struct napi_struct
*napi
, struct niu
*np
,
3442 struct rx_ring_info
*rp
)
3444 unsigned int index
= rp
->rcr_index
;
3445 struct rx_pkt_hdr1
*rh
;
3446 struct sk_buff
*skb
;
3449 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3451 return niu_rx_pkt_ignore(np
, rp
);
3455 struct page
*page
, **link
;
3456 u32 rcr_size
, append_size
;
3461 val
= le64_to_cpup(&rp
->rcr
[index
]);
3463 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3464 RCR_ENTRY_L2_LEN_SHIFT
;
3467 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3468 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3469 page
= niu_find_rxpage(rp
, addr
, &link
);
3471 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3472 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3474 off
= addr
& ~PAGE_MASK
;
3475 append_size
= rcr_size
;
3479 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3480 if ((ptype
== RCR_PKT_TYPE_TCP
||
3481 ptype
== RCR_PKT_TYPE_UDP
) &&
3482 !(val
& (RCR_ENTRY_NOPORT
|
3484 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3486 skb_checksum_none_assert(skb
);
3487 } else if (!(val
& RCR_ENTRY_MULTI
))
3488 append_size
= len
- skb
->len
;
3490 niu_rx_skb_append(skb
, page
, off
, append_size
);
3491 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3492 *link
= (struct page
*) page
->mapping
;
3493 np
->ops
->unmap_page(np
->device
, page
->index
,
3494 PAGE_SIZE
, DMA_FROM_DEVICE
);
3496 page
->mapping
= NULL
;
3497 rp
->rbr_refill_pending
++;
3501 index
= NEXT_RCR(rp
, index
);
3502 if (!(val
& RCR_ENTRY_MULTI
))
3506 rp
->rcr_index
= index
;
3509 len
= min_t(int, len
, sizeof(*rh
) + VLAN_ETH_HLEN
);
3510 __pskb_pull_tail(skb
, len
);
3512 rh
= (struct rx_pkt_hdr1
*) skb
->data
;
3513 if (np
->dev
->features
& NETIF_F_RXHASH
)
3514 skb
->rxhash
= ((u32
)rh
->hashval2_0
<< 24 |
3515 (u32
)rh
->hashval2_1
<< 16 |
3516 (u32
)rh
->hashval1_1
<< 8 |
3517 (u32
)rh
->hashval1_2
<< 0);
3518 skb_pull(skb
, sizeof(*rh
));
3521 rp
->rx_bytes
+= skb
->len
;
3523 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3524 skb_record_rx_queue(skb
, rp
->rx_channel
);
3525 napi_gro_receive(napi
, skb
);
3530 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3532 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3533 int err
, index
= rp
->rbr_index
;
3536 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3537 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3541 index
+= blocks_per_page
;
3544 rp
->rbr_index
= index
;
3548 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3552 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3555 page
= rp
->rxhash
[i
];
3557 struct page
*next
= (struct page
*) page
->mapping
;
3558 u64 base
= page
->index
;
3560 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3563 page
->mapping
= NULL
;
3571 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3572 rp
->rbr
[i
] = cpu_to_le32(0);
3576 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3578 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3579 struct sk_buff
*skb
= tb
->skb
;
3580 struct tx_pkt_hdr
*tp
;
3584 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3585 tx_flags
= le64_to_cpup(&tp
->flags
);
3588 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3589 ((tx_flags
& TXHDR_PAD
) / 2));
3591 len
= skb_headlen(skb
);
3592 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3593 len
, DMA_TO_DEVICE
);
3595 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3600 idx
= NEXT_TX(rp
, idx
);
3601 len
-= MAX_TX_DESC_LEN
;
3604 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3605 tb
= &rp
->tx_buffs
[idx
];
3606 BUG_ON(tb
->skb
!= NULL
);
3607 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3608 skb_shinfo(skb
)->frags
[i
].size
,
3610 idx
= NEXT_TX(rp
, idx
);
3618 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3620 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3622 struct netdev_queue
*txq
;
3627 index
= (rp
- np
->tx_rings
);
3628 txq
= netdev_get_tx_queue(np
->dev
, index
);
3631 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3634 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3635 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3636 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3638 rp
->last_pkt_cnt
= tmp
;
3642 netif_printk(np
, tx_done
, KERN_DEBUG
, np
->dev
,
3643 "%s() pkt_cnt[%u] cons[%d]\n", __func__
, pkt_cnt
, cons
);
3646 cons
= release_tx_packet(np
, rp
, cons
);
3652 if (unlikely(netif_tx_queue_stopped(txq
) &&
3653 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3654 __netif_tx_lock(txq
, smp_processor_id());
3655 if (netif_tx_queue_stopped(txq
) &&
3656 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3657 netif_tx_wake_queue(txq
);
3658 __netif_tx_unlock(txq
);
3662 static inline void niu_sync_rx_discard_stats(struct niu
*np
,
3663 struct rx_ring_info
*rp
,
3666 /* This elaborate scheme is needed for reading the RX discard
3667 * counters, as they are only 16-bit and can overflow quickly,
3668 * and because the overflow indication bit is not usable as
3669 * the counter value does not wrap, but remains at max value
3672 * In theory and in practice counters can be lost in between
3673 * reading nr64() and clearing the counter nw64(). For this
3674 * reason, the number of counter clearings nw64() is
3675 * limited/reduced though the limit parameter.
3677 int rx_channel
= rp
->rx_channel
;
3680 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3681 * following discard events: IPP (Input Port Process),
3682 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3683 * Block Ring) prefetch buffer is empty.
3685 misc
= nr64(RXMISC(rx_channel
));
3686 if (unlikely((misc
& RXMISC_COUNT
) > limit
)) {
3687 nw64(RXMISC(rx_channel
), 0);
3688 rp
->rx_errors
+= misc
& RXMISC_COUNT
;
3690 if (unlikely(misc
& RXMISC_OFLOW
))
3691 dev_err(np
->device
, "rx-%d: Counter overflow RXMISC discard\n",
3694 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3695 "rx-%d: MISC drop=%u over=%u\n",
3696 rx_channel
, misc
, misc
-limit
);
3699 /* WRED (Weighted Random Early Discard) by hardware */
3700 wred
= nr64(RED_DIS_CNT(rx_channel
));
3701 if (unlikely((wred
& RED_DIS_CNT_COUNT
) > limit
)) {
3702 nw64(RED_DIS_CNT(rx_channel
), 0);
3703 rp
->rx_dropped
+= wred
& RED_DIS_CNT_COUNT
;
3705 if (unlikely(wred
& RED_DIS_CNT_OFLOW
))
3706 dev_err(np
->device
, "rx-%d: Counter overflow WRED discard\n", rx_channel
);
3708 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3709 "rx-%d: WRED drop=%u over=%u\n",
3710 rx_channel
, wred
, wred
-limit
);
3714 static int niu_rx_work(struct napi_struct
*napi
, struct niu
*np
,
3715 struct rx_ring_info
*rp
, int budget
)
3717 int qlen
, rcr_done
= 0, work_done
= 0;
3718 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3722 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3723 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3725 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3726 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3728 mbox
->rx_dma_ctl_stat
= 0;
3729 mbox
->rcrstat_a
= 0;
3731 netif_printk(np
, rx_status
, KERN_DEBUG
, np
->dev
,
3732 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3733 __func__
, rp
->rx_channel
, (unsigned long long)stat
, qlen
);
3735 rcr_done
= work_done
= 0;
3736 qlen
= min(qlen
, budget
);
3737 while (work_done
< qlen
) {
3738 rcr_done
+= niu_process_rx_pkt(napi
, np
, rp
);
3742 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3745 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3746 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3747 rp
->rbr_refill_pending
= 0;
3750 stat
= (RX_DMA_CTL_STAT_MEX
|
3751 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3752 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3754 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3756 /* Only sync discards stats when qlen indicate potential for drops */
3758 niu_sync_rx_discard_stats(np
, rp
, 0x7FFF);
3763 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3766 u32 tx_vec
= (v0
>> 32);
3767 u32 rx_vec
= (v0
& 0xffffffff);
3768 int i
, work_done
= 0;
3770 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
3771 "%s() v0[%016llx]\n", __func__
, (unsigned long long)v0
);
3773 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3774 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3775 if (tx_vec
& (1 << rp
->tx_channel
))
3776 niu_tx_work(np
, rp
);
3777 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3780 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3781 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3783 if (rx_vec
& (1 << rp
->rx_channel
)) {
3786 this_work_done
= niu_rx_work(&lp
->napi
, np
, rp
,
3789 budget
-= this_work_done
;
3790 work_done
+= this_work_done
;
3792 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3798 static int niu_poll(struct napi_struct
*napi
, int budget
)
3800 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3801 struct niu
*np
= lp
->np
;
3804 work_done
= niu_poll_core(np
, lp
, budget
);
3806 if (work_done
< budget
) {
3807 napi_complete(napi
);
3808 niu_ldg_rearm(np
, lp
, 1);
3813 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3816 netdev_err(np
->dev
, "RX channel %u errors ( ", rp
->rx_channel
);
3818 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3819 pr_cont("RBR_TMOUT ");
3820 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3821 pr_cont("RSP_CNT ");
3822 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3823 pr_cont("BYTE_EN_BUS ");
3824 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3825 pr_cont("RSP_DAT ");
3826 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3827 pr_cont("RCR_ACK ");
3828 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3829 pr_cont("RCR_SHA_PAR ");
3830 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3831 pr_cont("RBR_PRE_PAR ");
3832 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3834 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3835 pr_cont("RCRINCON ");
3836 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3837 pr_cont("RCRFULL ");
3838 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3839 pr_cont("RBRFULL ");
3840 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3841 pr_cont("RBRLOGPAGE ");
3842 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3843 pr_cont("CFIGLOGPAGE ");
3844 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3845 pr_cont("DC_FIDO ");
3850 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3852 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3856 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3857 RX_DMA_CTL_STAT_PORT_FATAL
))
3861 netdev_err(np
->dev
, "RX channel %u error, stat[%llx]\n",
3863 (unsigned long long) stat
);
3865 niu_log_rxchan_errors(np
, rp
, stat
);
3868 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3869 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3874 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3877 netdev_err(np
->dev
, "TX channel %u errors ( ", rp
->tx_channel
);
3879 if (cs
& TX_CS_MBOX_ERR
)
3881 if (cs
& TX_CS_PKT_SIZE_ERR
)
3882 pr_cont("PKT_SIZE ");
3883 if (cs
& TX_CS_TX_RING_OFLOW
)
3884 pr_cont("TX_RING_OFLOW ");
3885 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3886 pr_cont("PREF_BUF_PAR ");
3887 if (cs
& TX_CS_NACK_PREF
)
3888 pr_cont("NACK_PREF ");
3889 if (cs
& TX_CS_NACK_PKT_RD
)
3890 pr_cont("NACK_PKT_RD ");
3891 if (cs
& TX_CS_CONF_PART_ERR
)
3892 pr_cont("CONF_PART ");
3893 if (cs
& TX_CS_PKT_PRT_ERR
)
3894 pr_cont("PKT_PTR ");
3899 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3903 cs
= nr64(TX_CS(rp
->tx_channel
));
3904 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3905 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3907 netdev_err(np
->dev
, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3909 (unsigned long long)cs
,
3910 (unsigned long long)logh
,
3911 (unsigned long long)logl
);
3913 niu_log_txchan_errors(np
, rp
, cs
);
3918 static int niu_mif_interrupt(struct niu
*np
)
3920 u64 mif_status
= nr64(MIF_STATUS
);
3923 if (np
->flags
& NIU_FLAGS_XMAC
) {
3924 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3926 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3930 netdev_err(np
->dev
, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3931 (unsigned long long)mif_status
, phy_mdint
);
3936 static void niu_xmac_interrupt(struct niu
*np
)
3938 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3941 val
= nr64_mac(XTXMAC_STATUS
);
3942 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3943 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3944 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3945 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3946 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3947 mp
->tx_fifo_errors
++;
3948 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3949 mp
->tx_overflow_errors
++;
3950 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3951 mp
->tx_max_pkt_size_errors
++;
3952 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3953 mp
->tx_underflow_errors
++;
3955 val
= nr64_mac(XRXMAC_STATUS
);
3956 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3957 mp
->rx_local_faults
++;
3958 if (val
& XRXMAC_STATUS_RFLT_DET
)
3959 mp
->rx_remote_faults
++;
3960 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3961 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3962 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3963 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3964 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3965 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3966 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3967 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3968 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3969 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3970 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3971 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3972 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3973 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3974 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3975 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3976 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3977 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3978 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3979 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3980 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3981 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3982 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3983 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3984 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3985 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3986 if (val
& XRXMAC_STATUS_RXOCTET_CNT_EXP
)
3987 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3988 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3989 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3990 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3991 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3992 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3993 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3994 if (val
& XRXMAC_STATUS_RXUFLOW
)
3995 mp
->rx_underflows
++;
3996 if (val
& XRXMAC_STATUS_RXOFLOW
)
3999 val
= nr64_mac(XMAC_FC_STAT
);
4000 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
4001 mp
->pause_off_state
++;
4002 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
4003 mp
->pause_on_state
++;
4004 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
4005 mp
->pause_received
++;
4008 static void niu_bmac_interrupt(struct niu
*np
)
4010 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
4013 val
= nr64_mac(BTXMAC_STATUS
);
4014 if (val
& BTXMAC_STATUS_UNDERRUN
)
4015 mp
->tx_underflow_errors
++;
4016 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
4017 mp
->tx_max_pkt_size_errors
++;
4018 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
4019 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
4020 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
4021 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
4023 val
= nr64_mac(BRXMAC_STATUS
);
4024 if (val
& BRXMAC_STATUS_OVERFLOW
)
4026 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
4027 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
4028 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
4029 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4030 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
4031 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4032 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
4033 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
4035 val
= nr64_mac(BMAC_CTRL_STATUS
);
4036 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
4037 mp
->pause_off_state
++;
4038 if (val
& BMAC_CTRL_STATUS_PAUSE
)
4039 mp
->pause_on_state
++;
4040 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
4041 mp
->pause_received
++;
4044 static int niu_mac_interrupt(struct niu
*np
)
4046 if (np
->flags
& NIU_FLAGS_XMAC
)
4047 niu_xmac_interrupt(np
);
4049 niu_bmac_interrupt(np
);
4054 static void niu_log_device_error(struct niu
*np
, u64 stat
)
4056 netdev_err(np
->dev
, "Core device errors ( ");
4058 if (stat
& SYS_ERR_MASK_META2
)
4060 if (stat
& SYS_ERR_MASK_META1
)
4062 if (stat
& SYS_ERR_MASK_PEU
)
4064 if (stat
& SYS_ERR_MASK_TXC
)
4066 if (stat
& SYS_ERR_MASK_RDMC
)
4068 if (stat
& SYS_ERR_MASK_TDMC
)
4070 if (stat
& SYS_ERR_MASK_ZCP
)
4072 if (stat
& SYS_ERR_MASK_FFLP
)
4074 if (stat
& SYS_ERR_MASK_IPP
)
4076 if (stat
& SYS_ERR_MASK_MAC
)
4078 if (stat
& SYS_ERR_MASK_SMX
)
4084 static int niu_device_error(struct niu
*np
)
4086 u64 stat
= nr64(SYS_ERR_STAT
);
4088 netdev_err(np
->dev
, "Core device error, stat[%llx]\n",
4089 (unsigned long long)stat
);
4091 niu_log_device_error(np
, stat
);
4096 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
4097 u64 v0
, u64 v1
, u64 v2
)
4106 if (v1
& 0x00000000ffffffffULL
) {
4107 u32 rx_vec
= (v1
& 0xffffffff);
4109 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4110 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4112 if (rx_vec
& (1 << rp
->rx_channel
)) {
4113 int r
= niu_rx_error(np
, rp
);
4118 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
4119 RX_DMA_CTL_STAT_MEX
);
4124 if (v1
& 0x7fffffff00000000ULL
) {
4125 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
4127 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4128 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4130 if (tx_vec
& (1 << rp
->tx_channel
)) {
4131 int r
= niu_tx_error(np
, rp
);
4137 if ((v0
| v1
) & 0x8000000000000000ULL
) {
4138 int r
= niu_mif_interrupt(np
);
4144 int r
= niu_mac_interrupt(np
);
4149 int r
= niu_device_error(np
);
4156 niu_enable_interrupts(np
, 0);
4161 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
4164 struct rxdma_mailbox
*mbox
= rp
->mbox
;
4165 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
4167 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
4168 RX_DMA_CTL_STAT_RCRTO
);
4169 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
4171 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4172 "%s() stat[%llx]\n", __func__
, (unsigned long long)stat
);
4175 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
4178 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
4180 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4181 "%s() cs[%llx]\n", __func__
, (unsigned long long)rp
->tx_cs
);
4184 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
4186 struct niu_parent
*parent
= np
->parent
;
4190 tx_vec
= (v0
>> 32);
4191 rx_vec
= (v0
& 0xffffffff);
4193 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4194 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4195 int ldn
= LDN_RXDMA(rp
->rx_channel
);
4197 if (parent
->ldg_map
[ldn
] != ldg
)
4200 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4201 if (rx_vec
& (1 << rp
->rx_channel
))
4202 niu_rxchan_intr(np
, rp
, ldn
);
4205 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4206 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4207 int ldn
= LDN_TXDMA(rp
->tx_channel
);
4209 if (parent
->ldg_map
[ldn
] != ldg
)
4212 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4213 if (tx_vec
& (1 << rp
->tx_channel
))
4214 niu_txchan_intr(np
, rp
, ldn
);
4218 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
4219 u64 v0
, u64 v1
, u64 v2
)
4221 if (likely(napi_schedule_prep(&lp
->napi
))) {
4225 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
4226 __napi_schedule(&lp
->napi
);
4230 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
4232 struct niu_ldg
*lp
= dev_id
;
4233 struct niu
*np
= lp
->np
;
4234 int ldg
= lp
->ldg_num
;
4235 unsigned long flags
;
4238 if (netif_msg_intr(np
))
4239 printk(KERN_DEBUG KBUILD_MODNAME
": " "%s() ldg[%p](%d)",
4242 spin_lock_irqsave(&np
->lock
, flags
);
4244 v0
= nr64(LDSV0(ldg
));
4245 v1
= nr64(LDSV1(ldg
));
4246 v2
= nr64(LDSV2(ldg
));
4248 if (netif_msg_intr(np
))
4249 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4250 (unsigned long long) v0
,
4251 (unsigned long long) v1
,
4252 (unsigned long long) v2
);
4254 if (unlikely(!v0
&& !v1
&& !v2
)) {
4255 spin_unlock_irqrestore(&np
->lock
, flags
);
4259 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
4260 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
4264 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
4265 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
4267 niu_ldg_rearm(np
, lp
, 1);
4269 spin_unlock_irqrestore(&np
->lock
, flags
);
4274 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
4277 np
->ops
->free_coherent(np
->device
,
4278 sizeof(struct rxdma_mailbox
),
4279 rp
->mbox
, rp
->mbox_dma
);
4283 np
->ops
->free_coherent(np
->device
,
4284 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4285 rp
->rcr
, rp
->rcr_dma
);
4287 rp
->rcr_table_size
= 0;
4291 niu_rbr_free(np
, rp
);
4293 np
->ops
->free_coherent(np
->device
,
4294 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4295 rp
->rbr
, rp
->rbr_dma
);
4297 rp
->rbr_table_size
= 0;
4304 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
4307 np
->ops
->free_coherent(np
->device
,
4308 sizeof(struct txdma_mailbox
),
4309 rp
->mbox
, rp
->mbox_dma
);
4315 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
4316 if (rp
->tx_buffs
[i
].skb
)
4317 (void) release_tx_packet(np
, rp
, i
);
4320 np
->ops
->free_coherent(np
->device
,
4321 MAX_TX_RING_SIZE
* sizeof(__le64
),
4322 rp
->descr
, rp
->descr_dma
);
4331 static void niu_free_channels(struct niu
*np
)
4336 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4337 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4339 niu_free_rx_ring_info(np
, rp
);
4341 kfree(np
->rx_rings
);
4342 np
->rx_rings
= NULL
;
4343 np
->num_rx_rings
= 0;
4347 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4348 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4350 niu_free_tx_ring_info(np
, rp
);
4352 kfree(np
->tx_rings
);
4353 np
->tx_rings
= NULL
;
4354 np
->num_tx_rings
= 0;
4358 static int niu_alloc_rx_ring_info(struct niu
*np
,
4359 struct rx_ring_info
*rp
)
4361 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
4363 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
4368 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4369 sizeof(struct rxdma_mailbox
),
4370 &rp
->mbox_dma
, GFP_KERNEL
);
4373 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4374 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4379 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
4380 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4381 &rp
->rcr_dma
, GFP_KERNEL
);
4384 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
4385 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4389 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
4392 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
4393 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4394 &rp
->rbr_dma
, GFP_KERNEL
);
4397 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
4398 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4402 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
4404 rp
->rbr_pending
= 0;
4409 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
4411 int mtu
= np
->dev
->mtu
;
4413 /* These values are recommended by the HW designers for fair
4414 * utilization of DRR amongst the rings.
4416 rp
->max_burst
= mtu
+ 32;
4417 if (rp
->max_burst
> 4096)
4418 rp
->max_burst
= 4096;
4421 static int niu_alloc_tx_ring_info(struct niu
*np
,
4422 struct tx_ring_info
*rp
)
4424 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
4426 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4427 sizeof(struct txdma_mailbox
),
4428 &rp
->mbox_dma
, GFP_KERNEL
);
4431 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4432 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4437 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4438 MAX_TX_RING_SIZE
* sizeof(__le64
),
4439 &rp
->descr_dma
, GFP_KERNEL
);
4442 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4443 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4448 rp
->pending
= MAX_TX_RING_SIZE
;
4453 /* XXX make these configurable... XXX */
4454 rp
->mark_freq
= rp
->pending
/ 4;
4456 niu_set_max_burst(np
, rp
);
4461 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4465 bss
= min(PAGE_SHIFT
, 15);
4467 rp
->rbr_block_size
= 1 << bss
;
4468 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4470 rp
->rbr_sizes
[0] = 256;
4471 rp
->rbr_sizes
[1] = 1024;
4472 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4473 switch (PAGE_SIZE
) {
4475 rp
->rbr_sizes
[2] = 4096;
4479 rp
->rbr_sizes
[2] = 8192;
4483 rp
->rbr_sizes
[2] = 2048;
4485 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4488 static int niu_alloc_channels(struct niu
*np
)
4490 struct niu_parent
*parent
= np
->parent
;
4491 int first_rx_channel
, first_tx_channel
;
4495 first_rx_channel
= first_tx_channel
= 0;
4496 for (i
= 0; i
< port
; i
++) {
4497 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4498 first_tx_channel
+= parent
->txchan_per_port
[i
];
4501 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4502 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4504 np
->dev
->real_num_tx_queues
= np
->num_tx_rings
;
4506 np
->rx_rings
= kcalloc(np
->num_rx_rings
, sizeof(struct rx_ring_info
),
4512 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4513 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4516 rp
->rx_channel
= first_rx_channel
+ i
;
4518 err
= niu_alloc_rx_ring_info(np
, rp
);
4522 niu_size_rbr(np
, rp
);
4524 /* XXX better defaults, configurable, etc... XXX */
4525 rp
->nonsyn_window
= 64;
4526 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4527 rp
->syn_window
= 64;
4528 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4529 rp
->rcr_pkt_threshold
= 16;
4530 rp
->rcr_timeout
= 8;
4531 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4532 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4533 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4535 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4540 np
->tx_rings
= kcalloc(np
->num_tx_rings
, sizeof(struct tx_ring_info
),
4546 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4547 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4550 rp
->tx_channel
= first_tx_channel
+ i
;
4552 err
= niu_alloc_tx_ring_info(np
, rp
);
4560 niu_free_channels(np
);
4564 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4568 while (--limit
> 0) {
4569 u64 val
= nr64(TX_CS(channel
));
4570 if (val
& TX_CS_SNG_STATE
)
4576 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4578 u64 val
= nr64(TX_CS(channel
));
4580 val
|= TX_CS_STOP_N_GO
;
4581 nw64(TX_CS(channel
), val
);
4583 return niu_tx_cs_sng_poll(np
, channel
);
4586 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4590 while (--limit
> 0) {
4591 u64 val
= nr64(TX_CS(channel
));
4592 if (!(val
& TX_CS_RST
))
4598 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4600 u64 val
= nr64(TX_CS(channel
));
4604 nw64(TX_CS(channel
), val
);
4606 err
= niu_tx_cs_reset_poll(np
, channel
);
4608 nw64(TX_RING_KICK(channel
), 0);
4613 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4617 nw64(TX_LOG_MASK1(channel
), 0);
4618 nw64(TX_LOG_VAL1(channel
), 0);
4619 nw64(TX_LOG_MASK2(channel
), 0);
4620 nw64(TX_LOG_VAL2(channel
), 0);
4621 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4622 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4623 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4625 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4626 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4627 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4629 /* XXX TXDMA 32bit mode? XXX */
4634 static void niu_txc_enable_port(struct niu
*np
, int on
)
4636 unsigned long flags
;
4639 niu_lock_parent(np
, flags
);
4640 val
= nr64(TXC_CONTROL
);
4641 mask
= (u64
)1 << np
->port
;
4643 val
|= TXC_CONTROL_ENABLE
| mask
;
4646 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4647 val
&= ~TXC_CONTROL_ENABLE
;
4649 nw64(TXC_CONTROL
, val
);
4650 niu_unlock_parent(np
, flags
);
4653 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4655 unsigned long flags
;
4658 niu_lock_parent(np
, flags
);
4659 val
= nr64(TXC_INT_MASK
);
4660 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4661 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4662 niu_unlock_parent(np
, flags
);
4665 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4672 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4673 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4675 nw64(TXC_PORT_DMA(np
->port
), val
);
4678 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4680 int err
, channel
= rp
->tx_channel
;
4683 err
= niu_tx_channel_stop(np
, channel
);
4687 err
= niu_tx_channel_reset(np
, channel
);
4691 err
= niu_tx_channel_lpage_init(np
, channel
);
4695 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4696 nw64(TX_ENT_MSK(channel
), 0);
4698 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4699 TX_RNG_CFIG_STADDR
)) {
4700 netdev_err(np
->dev
, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4701 channel
, (unsigned long long)rp
->descr_dma
);
4705 /* The length field in TX_RNG_CFIG is measured in 64-byte
4706 * blocks. rp->pending is the number of TX descriptors in
4707 * our ring, 8 bytes each, thus we divide by 8 bytes more
4708 * to get the proper value the chip wants.
4710 ring_len
= (rp
->pending
/ 8);
4712 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4714 nw64(TX_RNG_CFIG(channel
), val
);
4716 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4717 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4718 netdev_err(np
->dev
, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4719 channel
, (unsigned long long)rp
->mbox_dma
);
4722 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4723 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4725 nw64(TX_CS(channel
), 0);
4727 rp
->last_pkt_cnt
= 0;
4732 static void niu_init_rdc_groups(struct niu
*np
)
4734 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4735 int i
, first_table_num
= tp
->first_table_num
;
4737 for (i
= 0; i
< tp
->num_tables
; i
++) {
4738 struct rdc_table
*tbl
= &tp
->tables
[i
];
4739 int this_table
= first_table_num
+ i
;
4742 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4743 nw64(RDC_TBL(this_table
, slot
),
4744 tbl
->rxdma_channel
[slot
]);
4747 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4750 static void niu_init_drr_weight(struct niu
*np
)
4752 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4757 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4762 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4765 nw64(PT_DRR_WT(np
->port
), val
);
4768 static int niu_init_hostinfo(struct niu
*np
)
4770 struct niu_parent
*parent
= np
->parent
;
4771 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4772 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4773 int first_rdc_table
= tp
->first_table_num
;
4775 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4779 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4783 for (i
= 0; i
< num_alt
; i
++) {
4784 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4792 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4794 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4795 RXDMA_CFIG1_RST
, 1000, 10,
4799 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4803 nw64(RX_LOG_MASK1(channel
), 0);
4804 nw64(RX_LOG_VAL1(channel
), 0);
4805 nw64(RX_LOG_MASK2(channel
), 0);
4806 nw64(RX_LOG_VAL2(channel
), 0);
4807 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4808 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4809 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4811 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4812 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4813 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4818 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4822 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4823 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4824 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4825 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4826 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4829 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4834 switch (rp
->rbr_block_size
) {
4836 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4839 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4842 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4845 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4850 val
|= RBR_CFIG_B_VLD2
;
4851 switch (rp
->rbr_sizes
[2]) {
4853 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4856 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4859 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4862 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4868 val
|= RBR_CFIG_B_VLD1
;
4869 switch (rp
->rbr_sizes
[1]) {
4871 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4874 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4877 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4880 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4886 val
|= RBR_CFIG_B_VLD0
;
4887 switch (rp
->rbr_sizes
[0]) {
4889 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4892 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4895 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4898 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4909 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4911 u64 val
= nr64(RXDMA_CFIG1(channel
));
4915 val
|= RXDMA_CFIG1_EN
;
4917 val
&= ~RXDMA_CFIG1_EN
;
4918 nw64(RXDMA_CFIG1(channel
), val
);
4921 while (--limit
> 0) {
4922 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4931 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4933 int err
, channel
= rp
->rx_channel
;
4936 err
= niu_rx_channel_reset(np
, channel
);
4940 err
= niu_rx_channel_lpage_init(np
, channel
);
4944 niu_rx_channel_wred_init(np
, rp
);
4946 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4947 nw64(RX_DMA_CTL_STAT(channel
),
4948 (RX_DMA_CTL_STAT_MEX
|
4949 RX_DMA_CTL_STAT_RCRTHRES
|
4950 RX_DMA_CTL_STAT_RCRTO
|
4951 RX_DMA_CTL_STAT_RBR_EMPTY
));
4952 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4953 nw64(RXDMA_CFIG2(channel
),
4954 ((rp
->mbox_dma
& RXDMA_CFIG2_MBADDR_L
) |
4955 RXDMA_CFIG2_FULL_HDR
));
4956 nw64(RBR_CFIG_A(channel
),
4957 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4958 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4959 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4962 nw64(RBR_CFIG_B(channel
), val
);
4963 nw64(RCRCFIG_A(channel
),
4964 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4965 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4966 nw64(RCRCFIG_B(channel
),
4967 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4969 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4971 err
= niu_enable_rx_channel(np
, channel
, 1);
4975 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4977 val
= nr64(RX_DMA_CTL_STAT(channel
));
4978 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4979 nw64(RX_DMA_CTL_STAT(channel
), val
);
4984 static int niu_init_rx_channels(struct niu
*np
)
4986 unsigned long flags
;
4987 u64 seed
= jiffies_64
;
4990 niu_lock_parent(np
, flags
);
4991 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4992 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4993 niu_unlock_parent(np
, flags
);
4995 /* XXX RXDMA 32bit mode? XXX */
4997 niu_init_rdc_groups(np
);
4998 niu_init_drr_weight(np
);
5000 err
= niu_init_hostinfo(np
);
5004 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5005 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5007 err
= niu_init_one_rx_channel(np
, rp
);
5015 static int niu_set_ip_frag_rule(struct niu
*np
)
5017 struct niu_parent
*parent
= np
->parent
;
5018 struct niu_classifier
*cp
= &np
->clas
;
5019 struct niu_tcam_entry
*tp
;
5022 index
= cp
->tcam_top
;
5023 tp
= &parent
->tcam
[index
];
5025 /* Note that the noport bit is the same in both ipv4 and
5026 * ipv6 format TCAM entries.
5028 memset(tp
, 0, sizeof(*tp
));
5029 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
5030 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
5031 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
5032 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
5033 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
5036 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
5040 cp
->tcam_valid_entries
++;
5045 static int niu_init_classifier_hw(struct niu
*np
)
5047 struct niu_parent
*parent
= np
->parent
;
5048 struct niu_classifier
*cp
= &np
->clas
;
5051 nw64(H1POLY
, cp
->h1_init
);
5052 nw64(H2POLY
, cp
->h2_init
);
5054 err
= niu_init_hostinfo(np
);
5058 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
5059 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
5061 vlan_tbl_write(np
, i
, np
->port
,
5062 vp
->vlan_pref
, vp
->rdc_num
);
5065 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
5066 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
5068 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
5069 ap
->rdc_num
, ap
->mac_pref
);
5074 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
5075 int index
= i
- CLASS_CODE_USER_PROG1
;
5077 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
5080 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
5085 err
= niu_set_ip_frag_rule(np
);
5094 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
5096 nw64(ZCP_RAM_DATA0
, data
[0]);
5097 nw64(ZCP_RAM_DATA1
, data
[1]);
5098 nw64(ZCP_RAM_DATA2
, data
[2]);
5099 nw64(ZCP_RAM_DATA3
, data
[3]);
5100 nw64(ZCP_RAM_DATA4
, data
[4]);
5101 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
5103 (ZCP_RAM_ACC_WRITE
|
5104 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5105 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5107 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5111 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
5115 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5118 netdev_err(np
->dev
, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5119 (unsigned long long)nr64(ZCP_RAM_ACC
));
5125 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5126 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5128 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5131 netdev_err(np
->dev
, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5132 (unsigned long long)nr64(ZCP_RAM_ACC
));
5136 data
[0] = nr64(ZCP_RAM_DATA0
);
5137 data
[1] = nr64(ZCP_RAM_DATA1
);
5138 data
[2] = nr64(ZCP_RAM_DATA2
);
5139 data
[3] = nr64(ZCP_RAM_DATA3
);
5140 data
[4] = nr64(ZCP_RAM_DATA4
);
5145 static void niu_zcp_cfifo_reset(struct niu
*np
)
5147 u64 val
= nr64(RESET_CFIFO
);
5149 val
|= RESET_CFIFO_RST(np
->port
);
5150 nw64(RESET_CFIFO
, val
);
5153 val
&= ~RESET_CFIFO_RST(np
->port
);
5154 nw64(RESET_CFIFO
, val
);
5157 static int niu_init_zcp(struct niu
*np
)
5159 u64 data
[5], rbuf
[5];
5162 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5163 if (np
->port
== 0 || np
->port
== 1)
5164 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
5166 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
5168 max
= NIU_CFIFO_ENTRIES
;
5176 for (i
= 0; i
< max
; i
++) {
5177 err
= niu_zcp_write(np
, i
, data
);
5180 err
= niu_zcp_read(np
, i
, rbuf
);
5185 niu_zcp_cfifo_reset(np
);
5186 nw64(CFIFO_ECC(np
->port
), 0);
5187 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
5188 (void) nr64(ZCP_INT_STAT
);
5189 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
5194 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
5196 u64 val
= nr64_ipp(IPP_CFIG
);
5198 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
5199 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
5200 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
5201 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
5202 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
5203 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
5204 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
5205 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
5208 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
5210 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
5211 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
5212 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
5213 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
5214 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
5215 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
5218 static int niu_ipp_reset(struct niu
*np
)
5220 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
5221 1000, 100, "IPP_CFIG");
5224 static int niu_init_ipp(struct niu
*np
)
5226 u64 data
[5], rbuf
[5], val
;
5229 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5230 if (np
->port
== 0 || np
->port
== 1)
5231 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
5233 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
5235 max
= NIU_DFIFO_ENTRIES
;
5243 for (i
= 0; i
< max
; i
++) {
5244 niu_ipp_write(np
, i
, data
);
5245 niu_ipp_read(np
, i
, rbuf
);
5248 (void) nr64_ipp(IPP_INT_STAT
);
5249 (void) nr64_ipp(IPP_INT_STAT
);
5251 err
= niu_ipp_reset(np
);
5255 (void) nr64_ipp(IPP_PKT_DIS
);
5256 (void) nr64_ipp(IPP_BAD_CS_CNT
);
5257 (void) nr64_ipp(IPP_ECC
);
5259 (void) nr64_ipp(IPP_INT_STAT
);
5261 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
5263 val
= nr64_ipp(IPP_CFIG
);
5264 val
&= ~IPP_CFIG_IP_MAX_PKT
;
5265 val
|= (IPP_CFIG_IPP_ENABLE
|
5266 IPP_CFIG_DFIFO_ECC_EN
|
5267 IPP_CFIG_DROP_BAD_CRC
|
5269 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
5270 nw64_ipp(IPP_CFIG
, val
);
5275 static void niu_handle_led(struct niu
*np
, int status
)
5278 val
= nr64_mac(XMAC_CONFIG
);
5280 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
5281 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
5283 val
|= XMAC_CONFIG_LED_POLARITY
;
5284 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
5286 val
|= XMAC_CONFIG_FORCE_LED_ON
;
5287 val
&= ~XMAC_CONFIG_LED_POLARITY
;
5291 nw64_mac(XMAC_CONFIG
, val
);
5294 static void niu_init_xif_xmac(struct niu
*np
)
5296 struct niu_link_config
*lp
= &np
->link_config
;
5299 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
5300 val
= nr64(MIF_CONFIG
);
5301 val
|= MIF_CONFIG_ATCA_GE
;
5302 nw64(MIF_CONFIG
, val
);
5305 val
= nr64_mac(XMAC_CONFIG
);
5306 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5308 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
5310 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
5311 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5312 val
|= XMAC_CONFIG_LOOPBACK
;
5314 val
&= ~XMAC_CONFIG_LOOPBACK
;
5317 if (np
->flags
& NIU_FLAGS_10G
) {
5318 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
5320 val
|= XMAC_CONFIG_LFS_DISABLE
;
5321 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
5322 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
5323 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
5325 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
5328 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5330 if (lp
->active_speed
== SPEED_100
)
5331 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
5333 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
5335 nw64_mac(XMAC_CONFIG
, val
);
5337 val
= nr64_mac(XMAC_CONFIG
);
5338 val
&= ~XMAC_CONFIG_MODE_MASK
;
5339 if (np
->flags
& NIU_FLAGS_10G
) {
5340 val
|= XMAC_CONFIG_MODE_XGMII
;
5342 if (lp
->active_speed
== SPEED_1000
)
5343 val
|= XMAC_CONFIG_MODE_GMII
;
5345 val
|= XMAC_CONFIG_MODE_MII
;
5348 nw64_mac(XMAC_CONFIG
, val
);
5351 static void niu_init_xif_bmac(struct niu
*np
)
5353 struct niu_link_config
*lp
= &np
->link_config
;
5356 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
5358 if (lp
->loopback_mode
== LOOPBACK_MAC
)
5359 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
5361 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
5363 if (lp
->active_speed
== SPEED_1000
)
5364 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
5366 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
5368 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
5369 BMAC_XIF_CONFIG_LED_POLARITY
);
5371 if (!(np
->flags
& NIU_FLAGS_10G
) &&
5372 !(np
->flags
& NIU_FLAGS_FIBER
) &&
5373 lp
->active_speed
== SPEED_100
)
5374 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5376 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5378 nw64_mac(BMAC_XIF_CONFIG
, val
);
5381 static void niu_init_xif(struct niu
*np
)
5383 if (np
->flags
& NIU_FLAGS_XMAC
)
5384 niu_init_xif_xmac(np
);
5386 niu_init_xif_bmac(np
);
5389 static void niu_pcs_mii_reset(struct niu
*np
)
5392 u64 val
= nr64_pcs(PCS_MII_CTL
);
5393 val
|= PCS_MII_CTL_RST
;
5394 nw64_pcs(PCS_MII_CTL
, val
);
5395 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
5397 val
= nr64_pcs(PCS_MII_CTL
);
5401 static void niu_xpcs_reset(struct niu
*np
)
5404 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
5405 val
|= XPCS_CONTROL1_RESET
;
5406 nw64_xpcs(XPCS_CONTROL1
, val
);
5407 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
5409 val
= nr64_xpcs(XPCS_CONTROL1
);
5413 static int niu_init_pcs(struct niu
*np
)
5415 struct niu_link_config
*lp
= &np
->link_config
;
5418 switch (np
->flags
& (NIU_FLAGS_10G
|
5420 NIU_FLAGS_XCVR_SERDES
)) {
5421 case NIU_FLAGS_FIBER
:
5423 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5424 nw64_pcs(PCS_DPATH_MODE
, 0);
5425 niu_pcs_mii_reset(np
);
5429 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
5430 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
5432 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5435 /* 10G copper or fiber */
5436 val
= nr64_mac(XMAC_CONFIG
);
5437 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5438 nw64_mac(XMAC_CONFIG
, val
);
5442 val
= nr64_xpcs(XPCS_CONTROL1
);
5443 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5444 val
|= XPCS_CONTROL1_LOOPBACK
;
5446 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5447 nw64_xpcs(XPCS_CONTROL1
, val
);
5449 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5450 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5451 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5455 case NIU_FLAGS_XCVR_SERDES
:
5457 niu_pcs_mii_reset(np
);
5458 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5459 nw64_pcs(PCS_DPATH_MODE
, 0);
5464 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5465 /* 1G RGMII FIBER */
5466 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5467 niu_pcs_mii_reset(np
);
5477 static int niu_reset_tx_xmac(struct niu
*np
)
5479 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5480 (XTXMAC_SW_RST_REG_RS
|
5481 XTXMAC_SW_RST_SOFT_RST
),
5482 1000, 100, "XTXMAC_SW_RST");
5485 static int niu_reset_tx_bmac(struct niu
*np
)
5489 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5491 while (--limit
>= 0) {
5492 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5497 dev_err(np
->device
, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5499 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5506 static int niu_reset_tx_mac(struct niu
*np
)
5508 if (np
->flags
& NIU_FLAGS_XMAC
)
5509 return niu_reset_tx_xmac(np
);
5511 return niu_reset_tx_bmac(np
);
5514 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5518 val
= nr64_mac(XMAC_MIN
);
5519 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5520 XMAC_MIN_RX_MIN_PKT_SIZE
);
5521 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5522 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5523 nw64_mac(XMAC_MIN
, val
);
5525 nw64_mac(XMAC_MAX
, max
);
5527 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5529 val
= nr64_mac(XMAC_IPG
);
5530 if (np
->flags
& NIU_FLAGS_10G
) {
5531 val
&= ~XMAC_IPG_IPG_XGMII
;
5532 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5534 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5535 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5537 nw64_mac(XMAC_IPG
, val
);
5539 val
= nr64_mac(XMAC_CONFIG
);
5540 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5541 XMAC_CONFIG_STRETCH_MODE
|
5542 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5543 XMAC_CONFIG_TX_ENABLE
);
5544 nw64_mac(XMAC_CONFIG
, val
);
5546 nw64_mac(TXMAC_FRM_CNT
, 0);
5547 nw64_mac(TXMAC_BYTE_CNT
, 0);
5550 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5554 nw64_mac(BMAC_MIN_FRAME
, min
);
5555 nw64_mac(BMAC_MAX_FRAME
, max
);
5557 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5558 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5559 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5561 val
= nr64_mac(BTXMAC_CONFIG
);
5562 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5563 BTXMAC_CONFIG_ENABLE
);
5564 nw64_mac(BTXMAC_CONFIG
, val
);
5567 static void niu_init_tx_mac(struct niu
*np
)
5572 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5577 /* The XMAC_MIN register only accepts values for TX min which
5578 * have the low 3 bits cleared.
5582 if (np
->flags
& NIU_FLAGS_XMAC
)
5583 niu_init_tx_xmac(np
, min
, max
);
5585 niu_init_tx_bmac(np
, min
, max
);
5588 static int niu_reset_rx_xmac(struct niu
*np
)
5592 nw64_mac(XRXMAC_SW_RST
,
5593 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5595 while (--limit
>= 0) {
5596 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5597 XRXMAC_SW_RST_SOFT_RST
)))
5602 dev_err(np
->device
, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5604 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5611 static int niu_reset_rx_bmac(struct niu
*np
)
5615 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5617 while (--limit
>= 0) {
5618 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5623 dev_err(np
->device
, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5625 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5632 static int niu_reset_rx_mac(struct niu
*np
)
5634 if (np
->flags
& NIU_FLAGS_XMAC
)
5635 return niu_reset_rx_xmac(np
);
5637 return niu_reset_rx_bmac(np
);
5640 static void niu_init_rx_xmac(struct niu
*np
)
5642 struct niu_parent
*parent
= np
->parent
;
5643 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5644 int first_rdc_table
= tp
->first_table_num
;
5648 nw64_mac(XMAC_ADD_FILT0
, 0);
5649 nw64_mac(XMAC_ADD_FILT1
, 0);
5650 nw64_mac(XMAC_ADD_FILT2
, 0);
5651 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5652 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5653 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5654 nw64_mac(XMAC_HASH_TBL(i
), 0);
5655 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5656 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5657 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5659 val
= nr64_mac(XMAC_CONFIG
);
5660 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5661 XMAC_CONFIG_PROMISCUOUS
|
5662 XMAC_CONFIG_PROMISC_GROUP
|
5663 XMAC_CONFIG_ERR_CHK_DIS
|
5664 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5665 XMAC_CONFIG_RESERVED_MULTICAST
|
5666 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5667 XMAC_CONFIG_ADDR_FILTER_EN
|
5668 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5669 XMAC_CONFIG_STRIP_CRC
|
5670 XMAC_CONFIG_PASS_FLOW_CTRL
|
5671 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5672 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5673 nw64_mac(XMAC_CONFIG
, val
);
5675 nw64_mac(RXMAC_BT_CNT
, 0);
5676 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5677 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5678 nw64_mac(RXMAC_FRAG_CNT
, 0);
5679 nw64_mac(RXMAC_HIST_CNT1
, 0);
5680 nw64_mac(RXMAC_HIST_CNT2
, 0);
5681 nw64_mac(RXMAC_HIST_CNT3
, 0);
5682 nw64_mac(RXMAC_HIST_CNT4
, 0);
5683 nw64_mac(RXMAC_HIST_CNT5
, 0);
5684 nw64_mac(RXMAC_HIST_CNT6
, 0);
5685 nw64_mac(RXMAC_HIST_CNT7
, 0);
5686 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5687 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5688 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5689 nw64_mac(LINK_FAULT_CNT
, 0);
5692 static void niu_init_rx_bmac(struct niu
*np
)
5694 struct niu_parent
*parent
= np
->parent
;
5695 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5696 int first_rdc_table
= tp
->first_table_num
;
5700 nw64_mac(BMAC_ADD_FILT0
, 0);
5701 nw64_mac(BMAC_ADD_FILT1
, 0);
5702 nw64_mac(BMAC_ADD_FILT2
, 0);
5703 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5704 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5705 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5706 nw64_mac(BMAC_HASH_TBL(i
), 0);
5707 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5708 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5709 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5711 val
= nr64_mac(BRXMAC_CONFIG
);
5712 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5713 BRXMAC_CONFIG_STRIP_PAD
|
5714 BRXMAC_CONFIG_STRIP_FCS
|
5715 BRXMAC_CONFIG_PROMISC
|
5716 BRXMAC_CONFIG_PROMISC_GRP
|
5717 BRXMAC_CONFIG_ADDR_FILT_EN
|
5718 BRXMAC_CONFIG_DISCARD_DIS
);
5719 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5720 nw64_mac(BRXMAC_CONFIG
, val
);
5722 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5723 val
|= BMAC_ADDR_CMPEN_EN0
;
5724 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5727 static void niu_init_rx_mac(struct niu
*np
)
5729 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5731 if (np
->flags
& NIU_FLAGS_XMAC
)
5732 niu_init_rx_xmac(np
);
5734 niu_init_rx_bmac(np
);
5737 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5739 u64 val
= nr64_mac(XMAC_CONFIG
);
5742 val
|= XMAC_CONFIG_TX_ENABLE
;
5744 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5745 nw64_mac(XMAC_CONFIG
, val
);
5748 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5750 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5753 val
|= BTXMAC_CONFIG_ENABLE
;
5755 val
&= ~BTXMAC_CONFIG_ENABLE
;
5756 nw64_mac(BTXMAC_CONFIG
, val
);
5759 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5761 if (np
->flags
& NIU_FLAGS_XMAC
)
5762 niu_enable_tx_xmac(np
, on
);
5764 niu_enable_tx_bmac(np
, on
);
5767 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5769 u64 val
= nr64_mac(XMAC_CONFIG
);
5771 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5772 XMAC_CONFIG_PROMISCUOUS
);
5774 if (np
->flags
& NIU_FLAGS_MCAST
)
5775 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5776 if (np
->flags
& NIU_FLAGS_PROMISC
)
5777 val
|= XMAC_CONFIG_PROMISCUOUS
;
5780 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5782 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5783 nw64_mac(XMAC_CONFIG
, val
);
5786 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5788 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5790 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5791 BRXMAC_CONFIG_PROMISC
);
5793 if (np
->flags
& NIU_FLAGS_MCAST
)
5794 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5795 if (np
->flags
& NIU_FLAGS_PROMISC
)
5796 val
|= BRXMAC_CONFIG_PROMISC
;
5799 val
|= BRXMAC_CONFIG_ENABLE
;
5801 val
&= ~BRXMAC_CONFIG_ENABLE
;
5802 nw64_mac(BRXMAC_CONFIG
, val
);
5805 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5807 if (np
->flags
& NIU_FLAGS_XMAC
)
5808 niu_enable_rx_xmac(np
, on
);
5810 niu_enable_rx_bmac(np
, on
);
5813 static int niu_init_mac(struct niu
*np
)
5818 err
= niu_init_pcs(np
);
5822 err
= niu_reset_tx_mac(np
);
5825 niu_init_tx_mac(np
);
5826 err
= niu_reset_rx_mac(np
);
5829 niu_init_rx_mac(np
);
5831 /* This looks hookey but the RX MAC reset we just did will
5832 * undo some of the state we setup in niu_init_tx_mac() so we
5833 * have to call it again. In particular, the RX MAC reset will
5834 * set the XMAC_MAX register back to it's default value.
5836 niu_init_tx_mac(np
);
5837 niu_enable_tx_mac(np
, 1);
5839 niu_enable_rx_mac(np
, 1);
5844 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5846 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5849 static void niu_stop_tx_channels(struct niu
*np
)
5853 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5854 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5856 niu_stop_one_tx_channel(np
, rp
);
5860 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5862 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5865 static void niu_reset_tx_channels(struct niu
*np
)
5869 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5870 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5872 niu_reset_one_tx_channel(np
, rp
);
5876 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5878 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5881 static void niu_stop_rx_channels(struct niu
*np
)
5885 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5886 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5888 niu_stop_one_rx_channel(np
, rp
);
5892 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5894 int channel
= rp
->rx_channel
;
5896 (void) niu_rx_channel_reset(np
, channel
);
5897 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5898 nw64(RX_DMA_CTL_STAT(channel
), 0);
5899 (void) niu_enable_rx_channel(np
, channel
, 0);
5902 static void niu_reset_rx_channels(struct niu
*np
)
5906 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5907 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5909 niu_reset_one_rx_channel(np
, rp
);
5913 static void niu_disable_ipp(struct niu
*np
)
5918 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5919 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5921 while (--limit
>= 0 && (rd
!= wr
)) {
5922 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5923 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5926 (rd
!= 0 && wr
!= 1)) {
5927 netdev_err(np
->dev
, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5928 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR
),
5929 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR
));
5932 val
= nr64_ipp(IPP_CFIG
);
5933 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5934 IPP_CFIG_DFIFO_ECC_EN
|
5935 IPP_CFIG_DROP_BAD_CRC
|
5937 nw64_ipp(IPP_CFIG
, val
);
5939 (void) niu_ipp_reset(np
);
5942 static int niu_init_hw(struct niu
*np
)
5946 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TXC\n");
5947 niu_txc_enable_port(np
, 1);
5948 niu_txc_port_dma_enable(np
, 1);
5949 niu_txc_set_imask(np
, 0);
5951 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TX channels\n");
5952 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5953 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5955 err
= niu_init_one_tx_channel(np
, rp
);
5960 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize RX channels\n");
5961 err
= niu_init_rx_channels(np
);
5963 goto out_uninit_tx_channels
;
5965 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize classifier\n");
5966 err
= niu_init_classifier_hw(np
);
5968 goto out_uninit_rx_channels
;
5970 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize ZCP\n");
5971 err
= niu_init_zcp(np
);
5973 goto out_uninit_rx_channels
;
5975 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize IPP\n");
5976 err
= niu_init_ipp(np
);
5978 goto out_uninit_rx_channels
;
5980 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize MAC\n");
5981 err
= niu_init_mac(np
);
5983 goto out_uninit_ipp
;
5988 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit IPP\n");
5989 niu_disable_ipp(np
);
5991 out_uninit_rx_channels
:
5992 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit RX channels\n");
5993 niu_stop_rx_channels(np
);
5994 niu_reset_rx_channels(np
);
5996 out_uninit_tx_channels
:
5997 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit TX channels\n");
5998 niu_stop_tx_channels(np
);
5999 niu_reset_tx_channels(np
);
6004 static void niu_stop_hw(struct niu
*np
)
6006 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable interrupts\n");
6007 niu_enable_interrupts(np
, 0);
6009 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable RX MAC\n");
6010 niu_enable_rx_mac(np
, 0);
6012 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable IPP\n");
6013 niu_disable_ipp(np
);
6015 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop TX channels\n");
6016 niu_stop_tx_channels(np
);
6018 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop RX channels\n");
6019 niu_stop_rx_channels(np
);
6021 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset TX channels\n");
6022 niu_reset_tx_channels(np
);
6024 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset RX channels\n");
6025 niu_reset_rx_channels(np
);
6028 static void niu_set_irq_name(struct niu
*np
)
6030 int port
= np
->port
;
6033 sprintf(np
->irq_name
[0], "%s:MAC", np
->dev
->name
);
6036 sprintf(np
->irq_name
[1], "%s:MIF", np
->dev
->name
);
6037 sprintf(np
->irq_name
[2], "%s:SYSERR", np
->dev
->name
);
6041 for (i
= 0; i
< np
->num_ldg
- j
; i
++) {
6042 if (i
< np
->num_rx_rings
)
6043 sprintf(np
->irq_name
[i
+j
], "%s-rx-%d",
6045 else if (i
< np
->num_tx_rings
+ np
->num_rx_rings
)
6046 sprintf(np
->irq_name
[i
+j
], "%s-tx-%d", np
->dev
->name
,
6047 i
- np
->num_rx_rings
);
6051 static int niu_request_irq(struct niu
*np
)
6055 niu_set_irq_name(np
);
6058 for (i
= 0; i
< np
->num_ldg
; i
++) {
6059 struct niu_ldg
*lp
= &np
->ldg
[i
];
6061 err
= request_irq(lp
->irq
, niu_interrupt
,
6062 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
6063 np
->irq_name
[i
], lp
);
6072 for (j
= 0; j
< i
; j
++) {
6073 struct niu_ldg
*lp
= &np
->ldg
[j
];
6075 free_irq(lp
->irq
, lp
);
6080 static void niu_free_irq(struct niu
*np
)
6084 for (i
= 0; i
< np
->num_ldg
; i
++) {
6085 struct niu_ldg
*lp
= &np
->ldg
[i
];
6087 free_irq(lp
->irq
, lp
);
6091 static void niu_enable_napi(struct niu
*np
)
6095 for (i
= 0; i
< np
->num_ldg
; i
++)
6096 napi_enable(&np
->ldg
[i
].napi
);
6099 static void niu_disable_napi(struct niu
*np
)
6103 for (i
= 0; i
< np
->num_ldg
; i
++)
6104 napi_disable(&np
->ldg
[i
].napi
);
6107 static int niu_open(struct net_device
*dev
)
6109 struct niu
*np
= netdev_priv(dev
);
6112 netif_carrier_off(dev
);
6114 err
= niu_alloc_channels(np
);
6118 err
= niu_enable_interrupts(np
, 0);
6120 goto out_free_channels
;
6122 err
= niu_request_irq(np
);
6124 goto out_free_channels
;
6126 niu_enable_napi(np
);
6128 spin_lock_irq(&np
->lock
);
6130 err
= niu_init_hw(np
);
6132 init_timer(&np
->timer
);
6133 np
->timer
.expires
= jiffies
+ HZ
;
6134 np
->timer
.data
= (unsigned long) np
;
6135 np
->timer
.function
= niu_timer
;
6137 err
= niu_enable_interrupts(np
, 1);
6142 spin_unlock_irq(&np
->lock
);
6145 niu_disable_napi(np
);
6149 netif_tx_start_all_queues(dev
);
6151 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6152 netif_carrier_on(dev
);
6154 add_timer(&np
->timer
);
6162 niu_free_channels(np
);
6168 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
6170 cancel_work_sync(&np
->reset_task
);
6172 niu_disable_napi(np
);
6173 netif_tx_stop_all_queues(dev
);
6175 del_timer_sync(&np
->timer
);
6177 spin_lock_irq(&np
->lock
);
6181 spin_unlock_irq(&np
->lock
);
6184 static int niu_close(struct net_device
*dev
)
6186 struct niu
*np
= netdev_priv(dev
);
6188 niu_full_shutdown(np
, dev
);
6192 niu_free_channels(np
);
6194 niu_handle_led(np
, 0);
6199 static void niu_sync_xmac_stats(struct niu
*np
)
6201 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
6203 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
6204 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
6206 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
6207 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
6208 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
6209 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
6210 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
6211 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
6212 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
6213 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
6214 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
6215 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
6216 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
6217 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
6218 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
6219 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
6220 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
6221 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
6224 static void niu_sync_bmac_stats(struct niu
*np
)
6226 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
6228 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
6229 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
6231 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
6232 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6233 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6234 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
6237 static void niu_sync_mac_stats(struct niu
*np
)
6239 if (np
->flags
& NIU_FLAGS_XMAC
)
6240 niu_sync_xmac_stats(np
);
6242 niu_sync_bmac_stats(np
);
6245 static void niu_get_rx_stats(struct niu
*np
)
6247 unsigned long pkts
, dropped
, errors
, bytes
;
6250 pkts
= dropped
= errors
= bytes
= 0;
6251 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6252 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6254 niu_sync_rx_discard_stats(np
, rp
, 0);
6256 pkts
+= rp
->rx_packets
;
6257 bytes
+= rp
->rx_bytes
;
6258 dropped
+= rp
->rx_dropped
;
6259 errors
+= rp
->rx_errors
;
6261 np
->dev
->stats
.rx_packets
= pkts
;
6262 np
->dev
->stats
.rx_bytes
= bytes
;
6263 np
->dev
->stats
.rx_dropped
= dropped
;
6264 np
->dev
->stats
.rx_errors
= errors
;
6267 static void niu_get_tx_stats(struct niu
*np
)
6269 unsigned long pkts
, errors
, bytes
;
6272 pkts
= errors
= bytes
= 0;
6273 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6274 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6276 pkts
+= rp
->tx_packets
;
6277 bytes
+= rp
->tx_bytes
;
6278 errors
+= rp
->tx_errors
;
6280 np
->dev
->stats
.tx_packets
= pkts
;
6281 np
->dev
->stats
.tx_bytes
= bytes
;
6282 np
->dev
->stats
.tx_errors
= errors
;
6285 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
6287 struct niu
*np
= netdev_priv(dev
);
6289 niu_get_rx_stats(np
);
6290 niu_get_tx_stats(np
);
6295 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
6299 for (i
= 0; i
< 16; i
++)
6300 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
6303 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
6307 for (i
= 0; i
< 16; i
++)
6308 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
6311 static void niu_load_hash(struct niu
*np
, u16
*hash
)
6313 if (np
->flags
& NIU_FLAGS_XMAC
)
6314 niu_load_hash_xmac(np
, hash
);
6316 niu_load_hash_bmac(np
, hash
);
6319 static void niu_set_rx_mode(struct net_device
*dev
)
6321 struct niu
*np
= netdev_priv(dev
);
6322 int i
, alt_cnt
, err
;
6323 struct netdev_hw_addr
*ha
;
6324 unsigned long flags
;
6325 u16 hash
[16] = { 0, };
6327 spin_lock_irqsave(&np
->lock
, flags
);
6328 niu_enable_rx_mac(np
, 0);
6330 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
6331 if (dev
->flags
& IFF_PROMISC
)
6332 np
->flags
|= NIU_FLAGS_PROMISC
;
6333 if ((dev
->flags
& IFF_ALLMULTI
) || (!netdev_mc_empty(dev
)))
6334 np
->flags
|= NIU_FLAGS_MCAST
;
6336 alt_cnt
= netdev_uc_count(dev
);
6337 if (alt_cnt
> niu_num_alt_addr(np
)) {
6339 np
->flags
|= NIU_FLAGS_PROMISC
;
6345 netdev_for_each_uc_addr(ha
, dev
) {
6346 err
= niu_set_alt_mac(np
, index
, ha
->addr
);
6348 netdev_warn(dev
, "Error %d adding alt mac %d\n",
6350 err
= niu_enable_alt_mac(np
, index
, 1);
6352 netdev_warn(dev
, "Error %d enabling alt mac %d\n",
6359 if (np
->flags
& NIU_FLAGS_XMAC
)
6363 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
6364 err
= niu_enable_alt_mac(np
, i
, 0);
6366 netdev_warn(dev
, "Error %d disabling alt mac %d\n",
6370 if (dev
->flags
& IFF_ALLMULTI
) {
6371 for (i
= 0; i
< 16; i
++)
6373 } else if (!netdev_mc_empty(dev
)) {
6374 netdev_for_each_mc_addr(ha
, dev
) {
6375 u32 crc
= ether_crc_le(ETH_ALEN
, ha
->addr
);
6378 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
6382 if (np
->flags
& NIU_FLAGS_MCAST
)
6383 niu_load_hash(np
, hash
);
6385 niu_enable_rx_mac(np
, 1);
6386 spin_unlock_irqrestore(&np
->lock
, flags
);
6389 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
6391 struct niu
*np
= netdev_priv(dev
);
6392 struct sockaddr
*addr
= p
;
6393 unsigned long flags
;
6395 if (!is_valid_ether_addr(addr
->sa_data
))
6398 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
6400 if (!netif_running(dev
))
6403 spin_lock_irqsave(&np
->lock
, flags
);
6404 niu_enable_rx_mac(np
, 0);
6405 niu_set_primary_mac(np
, dev
->dev_addr
);
6406 niu_enable_rx_mac(np
, 1);
6407 spin_unlock_irqrestore(&np
->lock
, flags
);
6412 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6417 static void niu_netif_stop(struct niu
*np
)
6419 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6421 niu_disable_napi(np
);
6423 netif_tx_disable(np
->dev
);
6426 static void niu_netif_start(struct niu
*np
)
6428 /* NOTE: unconditional netif_wake_queue is only appropriate
6429 * so long as all callers are assured to have free tx slots
6430 * (such as after niu_init_hw).
6432 netif_tx_wake_all_queues(np
->dev
);
6434 niu_enable_napi(np
);
6436 niu_enable_interrupts(np
, 1);
6439 static void niu_reset_buffers(struct niu
*np
)
6444 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6445 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6447 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
6450 page
= rp
->rxhash
[j
];
6453 (struct page
*) page
->mapping
;
6454 u64 base
= page
->index
;
6455 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6456 rp
->rbr
[k
++] = cpu_to_le32(base
);
6460 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6461 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6466 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6468 rp
->rbr_pending
= 0;
6469 rp
->rbr_refill_pending
= 0;
6473 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6474 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6476 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6477 if (rp
->tx_buffs
[j
].skb
)
6478 (void) release_tx_packet(np
, rp
, j
);
6481 rp
->pending
= MAX_TX_RING_SIZE
;
6489 static void niu_reset_task(struct work_struct
*work
)
6491 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6492 unsigned long flags
;
6495 spin_lock_irqsave(&np
->lock
, flags
);
6496 if (!netif_running(np
->dev
)) {
6497 spin_unlock_irqrestore(&np
->lock
, flags
);
6501 spin_unlock_irqrestore(&np
->lock
, flags
);
6503 del_timer_sync(&np
->timer
);
6507 spin_lock_irqsave(&np
->lock
, flags
);
6511 spin_unlock_irqrestore(&np
->lock
, flags
);
6513 niu_reset_buffers(np
);
6515 spin_lock_irqsave(&np
->lock
, flags
);
6517 err
= niu_init_hw(np
);
6519 np
->timer
.expires
= jiffies
+ HZ
;
6520 add_timer(&np
->timer
);
6521 niu_netif_start(np
);
6524 spin_unlock_irqrestore(&np
->lock
, flags
);
6527 static void niu_tx_timeout(struct net_device
*dev
)
6529 struct niu
*np
= netdev_priv(dev
);
6531 dev_err(np
->device
, "%s: Transmit timed out, resetting\n",
6534 schedule_work(&np
->reset_task
);
6537 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6538 u64 mapping
, u64 len
, u64 mark
,
6541 __le64
*desc
= &rp
->descr
[index
];
6543 *desc
= cpu_to_le64(mark
|
6544 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6545 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6546 (mapping
& TX_DESC_SAD
));
6549 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6550 u64 pad_bytes
, u64 len
)
6552 u16 eth_proto
, eth_proto_inner
;
6553 u64 csum_bits
, l3off
, ihl
, ret
;
6557 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6558 eth_proto_inner
= eth_proto
;
6559 if (eth_proto
== ETH_P_8021Q
) {
6560 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6561 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6563 eth_proto_inner
= be16_to_cpu(val
);
6567 switch (skb
->protocol
) {
6568 case cpu_to_be16(ETH_P_IP
):
6569 ip_proto
= ip_hdr(skb
)->protocol
;
6570 ihl
= ip_hdr(skb
)->ihl
;
6572 case cpu_to_be16(ETH_P_IPV6
):
6573 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6582 csum_bits
= TXHDR_CSUM_NONE
;
6583 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6586 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6588 (ip_proto
== IPPROTO_UDP
?
6589 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6591 start
= skb_transport_offset(skb
) -
6592 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6593 stuff
= start
+ skb
->csum_offset
;
6595 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6596 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6599 l3off
= skb_network_offset(skb
) -
6600 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6602 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6603 (len
<< TXHDR_LEN_SHIFT
) |
6604 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6605 (ihl
<< TXHDR_IHL_SHIFT
) |
6606 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6607 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6608 (ipv6
? TXHDR_IP_VER
: 0) |
6614 static netdev_tx_t
niu_start_xmit(struct sk_buff
*skb
,
6615 struct net_device
*dev
)
6617 struct niu
*np
= netdev_priv(dev
);
6618 unsigned long align
, headroom
;
6619 struct netdev_queue
*txq
;
6620 struct tx_ring_info
*rp
;
6621 struct tx_pkt_hdr
*tp
;
6622 unsigned int len
, nfg
;
6623 struct ethhdr
*ehdr
;
6627 i
= skb_get_queue_mapping(skb
);
6628 rp
= &np
->tx_rings
[i
];
6629 txq
= netdev_get_tx_queue(dev
, i
);
6631 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6632 netif_tx_stop_queue(txq
);
6633 dev_err(np
->device
, "%s: BUG! Tx ring full when queue awake!\n", dev
->name
);
6635 return NETDEV_TX_BUSY
;
6638 if (skb
->len
< ETH_ZLEN
) {
6639 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6641 if (skb_pad(skb
, pad_bytes
))
6643 skb_put(skb
, pad_bytes
);
6646 len
= sizeof(struct tx_pkt_hdr
) + 15;
6647 if (skb_headroom(skb
) < len
) {
6648 struct sk_buff
*skb_new
;
6650 skb_new
= skb_realloc_headroom(skb
, len
);
6660 align
= ((unsigned long) skb
->data
& (16 - 1));
6661 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6663 ehdr
= (struct ethhdr
*) skb
->data
;
6664 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6666 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6667 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6670 len
= skb_headlen(skb
);
6671 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6672 len
, DMA_TO_DEVICE
);
6676 rp
->tx_buffs
[prod
].skb
= skb
;
6677 rp
->tx_buffs
[prod
].mapping
= mapping
;
6680 if (++rp
->mark_counter
== rp
->mark_freq
) {
6681 rp
->mark_counter
= 0;
6682 mrk
|= TX_DESC_MARK
;
6687 nfg
= skb_shinfo(skb
)->nr_frags
;
6689 tlen
-= MAX_TX_DESC_LEN
;
6694 unsigned int this_len
= len
;
6696 if (this_len
> MAX_TX_DESC_LEN
)
6697 this_len
= MAX_TX_DESC_LEN
;
6699 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6702 prod
= NEXT_TX(rp
, prod
);
6703 mapping
+= this_len
;
6707 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6708 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6711 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6712 frag
->page_offset
, len
,
6715 rp
->tx_buffs
[prod
].skb
= NULL
;
6716 rp
->tx_buffs
[prod
].mapping
= mapping
;
6718 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6720 prod
= NEXT_TX(rp
, prod
);
6723 if (prod
< rp
->prod
)
6724 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6727 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6729 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6730 netif_tx_stop_queue(txq
);
6731 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6732 netif_tx_wake_queue(txq
);
6736 return NETDEV_TX_OK
;
6744 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6746 struct niu
*np
= netdev_priv(dev
);
6747 int err
, orig_jumbo
, new_jumbo
;
6749 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6752 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6753 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6757 if (!netif_running(dev
) ||
6758 (orig_jumbo
== new_jumbo
))
6761 niu_full_shutdown(np
, dev
);
6763 niu_free_channels(np
);
6765 niu_enable_napi(np
);
6767 err
= niu_alloc_channels(np
);
6771 spin_lock_irq(&np
->lock
);
6773 err
= niu_init_hw(np
);
6775 init_timer(&np
->timer
);
6776 np
->timer
.expires
= jiffies
+ HZ
;
6777 np
->timer
.data
= (unsigned long) np
;
6778 np
->timer
.function
= niu_timer
;
6780 err
= niu_enable_interrupts(np
, 1);
6785 spin_unlock_irq(&np
->lock
);
6788 netif_tx_start_all_queues(dev
);
6789 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6790 netif_carrier_on(dev
);
6792 add_timer(&np
->timer
);
6798 static void niu_get_drvinfo(struct net_device
*dev
,
6799 struct ethtool_drvinfo
*info
)
6801 struct niu
*np
= netdev_priv(dev
);
6802 struct niu_vpd
*vpd
= &np
->vpd
;
6804 strcpy(info
->driver
, DRV_MODULE_NAME
);
6805 strcpy(info
->version
, DRV_MODULE_VERSION
);
6806 sprintf(info
->fw_version
, "%d.%d",
6807 vpd
->fcode_major
, vpd
->fcode_minor
);
6808 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6809 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6812 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6814 struct niu
*np
= netdev_priv(dev
);
6815 struct niu_link_config
*lp
;
6817 lp
= &np
->link_config
;
6819 memset(cmd
, 0, sizeof(*cmd
));
6820 cmd
->phy_address
= np
->phy_addr
;
6821 cmd
->supported
= lp
->supported
;
6822 cmd
->advertising
= lp
->active_advertising
;
6823 cmd
->autoneg
= lp
->active_autoneg
;
6824 cmd
->speed
= lp
->active_speed
;
6825 cmd
->duplex
= lp
->active_duplex
;
6826 cmd
->port
= (np
->flags
& NIU_FLAGS_FIBER
) ? PORT_FIBRE
: PORT_TP
;
6827 cmd
->transceiver
= (np
->flags
& NIU_FLAGS_XCVR_SERDES
) ?
6828 XCVR_EXTERNAL
: XCVR_INTERNAL
;
6833 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6835 struct niu
*np
= netdev_priv(dev
);
6836 struct niu_link_config
*lp
= &np
->link_config
;
6838 lp
->advertising
= cmd
->advertising
;
6839 lp
->speed
= cmd
->speed
;
6840 lp
->duplex
= cmd
->duplex
;
6841 lp
->autoneg
= cmd
->autoneg
;
6842 return niu_init_link(np
);
6845 static u32
niu_get_msglevel(struct net_device
*dev
)
6847 struct niu
*np
= netdev_priv(dev
);
6848 return np
->msg_enable
;
6851 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6853 struct niu
*np
= netdev_priv(dev
);
6854 np
->msg_enable
= value
;
6857 static int niu_nway_reset(struct net_device
*dev
)
6859 struct niu
*np
= netdev_priv(dev
);
6861 if (np
->link_config
.autoneg
)
6862 return niu_init_link(np
);
6867 static int niu_get_eeprom_len(struct net_device
*dev
)
6869 struct niu
*np
= netdev_priv(dev
);
6871 return np
->eeprom_len
;
6874 static int niu_get_eeprom(struct net_device
*dev
,
6875 struct ethtool_eeprom
*eeprom
, u8
*data
)
6877 struct niu
*np
= netdev_priv(dev
);
6878 u32 offset
, len
, val
;
6880 offset
= eeprom
->offset
;
6883 if (offset
+ len
< offset
)
6885 if (offset
>= np
->eeprom_len
)
6887 if (offset
+ len
> np
->eeprom_len
)
6888 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6891 u32 b_offset
, b_count
;
6893 b_offset
= offset
& 3;
6894 b_count
= 4 - b_offset
;
6898 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6899 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6905 val
= nr64(ESPC_NCR(offset
/ 4));
6906 memcpy(data
, &val
, 4);
6912 val
= nr64(ESPC_NCR(offset
/ 4));
6913 memcpy(data
, &val
, len
);
6918 static void niu_ethflow_to_l3proto(int flow_type
, u8
*pid
)
6920 switch (flow_type
) {
6931 *pid
= IPPROTO_SCTP
;
6947 static int niu_class_to_ethflow(u64
class, int *flow_type
)
6950 case CLASS_CODE_TCP_IPV4
:
6951 *flow_type
= TCP_V4_FLOW
;
6953 case CLASS_CODE_UDP_IPV4
:
6954 *flow_type
= UDP_V4_FLOW
;
6956 case CLASS_CODE_AH_ESP_IPV4
:
6957 *flow_type
= AH_V4_FLOW
;
6959 case CLASS_CODE_SCTP_IPV4
:
6960 *flow_type
= SCTP_V4_FLOW
;
6962 case CLASS_CODE_TCP_IPV6
:
6963 *flow_type
= TCP_V6_FLOW
;
6965 case CLASS_CODE_UDP_IPV6
:
6966 *flow_type
= UDP_V6_FLOW
;
6968 case CLASS_CODE_AH_ESP_IPV6
:
6969 *flow_type
= AH_V6_FLOW
;
6971 case CLASS_CODE_SCTP_IPV6
:
6972 *flow_type
= SCTP_V6_FLOW
;
6974 case CLASS_CODE_USER_PROG1
:
6975 case CLASS_CODE_USER_PROG2
:
6976 case CLASS_CODE_USER_PROG3
:
6977 case CLASS_CODE_USER_PROG4
:
6978 *flow_type
= IP_USER_FLOW
;
6987 static int niu_ethflow_to_class(int flow_type
, u64
*class)
6989 switch (flow_type
) {
6991 *class = CLASS_CODE_TCP_IPV4
;
6994 *class = CLASS_CODE_UDP_IPV4
;
6998 *class = CLASS_CODE_AH_ESP_IPV4
;
7001 *class = CLASS_CODE_SCTP_IPV4
;
7004 *class = CLASS_CODE_TCP_IPV6
;
7007 *class = CLASS_CODE_UDP_IPV6
;
7011 *class = CLASS_CODE_AH_ESP_IPV6
;
7014 *class = CLASS_CODE_SCTP_IPV6
;
7023 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
7027 if (flow_key
& FLOW_KEY_L2DA
)
7028 ethflow
|= RXH_L2DA
;
7029 if (flow_key
& FLOW_KEY_VLAN
)
7030 ethflow
|= RXH_VLAN
;
7031 if (flow_key
& FLOW_KEY_IPSA
)
7032 ethflow
|= RXH_IP_SRC
;
7033 if (flow_key
& FLOW_KEY_IPDA
)
7034 ethflow
|= RXH_IP_DST
;
7035 if (flow_key
& FLOW_KEY_PROTO
)
7036 ethflow
|= RXH_L3_PROTO
;
7037 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
7038 ethflow
|= RXH_L4_B_0_1
;
7039 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
7040 ethflow
|= RXH_L4_B_2_3
;
7046 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
7050 if (ethflow
& RXH_L2DA
)
7051 key
|= FLOW_KEY_L2DA
;
7052 if (ethflow
& RXH_VLAN
)
7053 key
|= FLOW_KEY_VLAN
;
7054 if (ethflow
& RXH_IP_SRC
)
7055 key
|= FLOW_KEY_IPSA
;
7056 if (ethflow
& RXH_IP_DST
)
7057 key
|= FLOW_KEY_IPDA
;
7058 if (ethflow
& RXH_L3_PROTO
)
7059 key
|= FLOW_KEY_PROTO
;
7060 if (ethflow
& RXH_L4_B_0_1
)
7061 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
7062 if (ethflow
& RXH_L4_B_2_3
)
7063 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
7071 static int niu_get_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7077 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7080 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7082 nfc
->data
= RXH_DISCARD
;
7084 nfc
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
7085 CLASS_CODE_USER_PROG1
]);
7089 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry
*tp
,
7090 struct ethtool_rx_flow_spec
*fsp
)
7093 fsp
->h_u
.tcp_ip4_spec
.ip4src
= (tp
->key
[3] & TCAM_V4KEY3_SADDR
) >>
7094 TCAM_V4KEY3_SADDR_SHIFT
;
7095 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= (tp
->key
[3] & TCAM_V4KEY3_DADDR
) >>
7096 TCAM_V4KEY3_DADDR_SHIFT
;
7097 fsp
->m_u
.tcp_ip4_spec
.ip4src
= (tp
->key_mask
[3] & TCAM_V4KEY3_SADDR
) >>
7098 TCAM_V4KEY3_SADDR_SHIFT
;
7099 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= (tp
->key_mask
[3] & TCAM_V4KEY3_DADDR
) >>
7100 TCAM_V4KEY3_DADDR_SHIFT
;
7102 fsp
->h_u
.tcp_ip4_spec
.ip4src
=
7103 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7104 fsp
->m_u
.tcp_ip4_spec
.ip4src
=
7105 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7106 fsp
->h_u
.tcp_ip4_spec
.ip4dst
=
7107 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7108 fsp
->m_u
.tcp_ip4_spec
.ip4dst
=
7109 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7111 fsp
->h_u
.tcp_ip4_spec
.tos
= (tp
->key
[2] & TCAM_V4KEY2_TOS
) >>
7112 TCAM_V4KEY2_TOS_SHIFT
;
7113 fsp
->m_u
.tcp_ip4_spec
.tos
= (tp
->key_mask
[2] & TCAM_V4KEY2_TOS
) >>
7114 TCAM_V4KEY2_TOS_SHIFT
;
7116 switch (fsp
->flow_type
) {
7120 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7121 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7122 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7123 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7124 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7125 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7126 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7127 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7128 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7129 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7130 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7131 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7133 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7134 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7135 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7136 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7137 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7138 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7139 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7140 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7144 fsp
->h_u
.ah_ip4_spec
.spi
=
7145 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7146 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7147 fsp
->m_u
.ah_ip4_spec
.spi
=
7148 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7149 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7151 fsp
->h_u
.ah_ip4_spec
.spi
=
7152 cpu_to_be32(fsp
->h_u
.ah_ip4_spec
.spi
);
7153 fsp
->m_u
.ah_ip4_spec
.spi
=
7154 cpu_to_be32(fsp
->m_u
.ah_ip4_spec
.spi
);
7157 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7158 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7159 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7160 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7161 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7162 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7164 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7165 cpu_to_be32(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7166 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7167 cpu_to_be32(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7169 fsp
->h_u
.usr_ip4_spec
.proto
=
7170 (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7171 TCAM_V4KEY2_PROTO_SHIFT
;
7172 fsp
->m_u
.usr_ip4_spec
.proto
=
7173 (tp
->key_mask
[2] & TCAM_V4KEY2_PROTO
) >>
7174 TCAM_V4KEY2_PROTO_SHIFT
;
7176 fsp
->h_u
.usr_ip4_spec
.ip_ver
= ETH_RX_NFC_IP4
;
7183 static int niu_get_ethtool_tcam_entry(struct niu
*np
,
7184 struct ethtool_rxnfc
*nfc
)
7186 struct niu_parent
*parent
= np
->parent
;
7187 struct niu_tcam_entry
*tp
;
7188 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7193 idx
= tcam_get_index(np
, (u16
)nfc
->fs
.location
);
7195 tp
= &parent
->tcam
[idx
];
7197 netdev_info(np
->dev
, "niu%d: entry [%d] invalid for idx[%d]\n",
7198 parent
->index
, (u16
)nfc
->fs
.location
, idx
);
7202 /* fill the flow spec entry */
7203 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7204 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7205 ret
= niu_class_to_ethflow(class, &fsp
->flow_type
);
7208 netdev_info(np
->dev
, "niu%d: niu_class_to_ethflow failed\n",
7214 if (fsp
->flow_type
== AH_V4_FLOW
|| fsp
->flow_type
== AH_V6_FLOW
) {
7215 u32 proto
= (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7216 TCAM_V4KEY2_PROTO_SHIFT
;
7217 if (proto
== IPPROTO_ESP
) {
7218 if (fsp
->flow_type
== AH_V4_FLOW
)
7219 fsp
->flow_type
= ESP_V4_FLOW
;
7221 fsp
->flow_type
= ESP_V6_FLOW
;
7225 switch (fsp
->flow_type
) {
7231 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7238 /* Not yet implemented */
7242 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7252 if (tp
->assoc_data
& TCAM_ASSOCDATA_DISC
)
7253 fsp
->ring_cookie
= RX_CLS_FLOW_DISC
;
7255 fsp
->ring_cookie
= (tp
->assoc_data
& TCAM_ASSOCDATA_OFFSET
) >>
7256 TCAM_ASSOCDATA_OFFSET_SHIFT
;
7258 /* put the tcam size here */
7259 nfc
->data
= tcam_get_size(np
);
7264 static int niu_get_ethtool_tcam_all(struct niu
*np
,
7265 struct ethtool_rxnfc
*nfc
,
7268 struct niu_parent
*parent
= np
->parent
;
7269 struct niu_tcam_entry
*tp
;
7271 unsigned long flags
;
7274 /* put the tcam size here */
7275 nfc
->data
= tcam_get_size(np
);
7277 niu_lock_parent(np
, flags
);
7278 for (cnt
= 0, i
= 0; i
< nfc
->data
; i
++) {
7279 idx
= tcam_get_index(np
, i
);
7280 tp
= &parent
->tcam
[idx
];
7283 if (cnt
== nfc
->rule_cnt
) {
7290 niu_unlock_parent(np
, flags
);
7295 static int niu_get_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
7298 struct niu
*np
= netdev_priv(dev
);
7303 ret
= niu_get_hash_opts(np
, cmd
);
7305 case ETHTOOL_GRXRINGS
:
7306 cmd
->data
= np
->num_rx_rings
;
7308 case ETHTOOL_GRXCLSRLCNT
:
7309 cmd
->rule_cnt
= tcam_get_valid_entry_cnt(np
);
7311 case ETHTOOL_GRXCLSRULE
:
7312 ret
= niu_get_ethtool_tcam_entry(np
, cmd
);
7314 case ETHTOOL_GRXCLSRLALL
:
7315 ret
= niu_get_ethtool_tcam_all(np
, cmd
, (u32
*)rule_locs
);
7325 static int niu_set_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7329 unsigned long flags
;
7331 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7334 if (class < CLASS_CODE_USER_PROG1
||
7335 class > CLASS_CODE_SCTP_IPV6
)
7338 if (nfc
->data
& RXH_DISCARD
) {
7339 niu_lock_parent(np
, flags
);
7340 flow_key
= np
->parent
->tcam_key
[class -
7341 CLASS_CODE_USER_PROG1
];
7342 flow_key
|= TCAM_KEY_DISC
;
7343 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7344 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7345 niu_unlock_parent(np
, flags
);
7348 /* Discard was set before, but is not set now */
7349 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7351 niu_lock_parent(np
, flags
);
7352 flow_key
= np
->parent
->tcam_key
[class -
7353 CLASS_CODE_USER_PROG1
];
7354 flow_key
&= ~TCAM_KEY_DISC
;
7355 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
7357 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
7359 niu_unlock_parent(np
, flags
);
7363 if (!niu_ethflow_to_flowkey(nfc
->data
, &flow_key
))
7366 niu_lock_parent(np
, flags
);
7367 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7368 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7369 niu_unlock_parent(np
, flags
);
7374 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec
*fsp
,
7375 struct niu_tcam_entry
*tp
,
7376 int l2_rdc_tab
, u64
class)
7379 u32 sip
, dip
, sipm
, dipm
, spi
, spim
;
7380 u16 sport
, dport
, spm
, dpm
;
7382 sip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7383 sipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7384 dip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7385 dipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7387 tp
->key
[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7388 tp
->key_mask
[0] = TCAM_V4KEY0_CLASS_CODE
;
7389 tp
->key
[1] = (u64
)l2_rdc_tab
<< TCAM_V4KEY1_L2RDCNUM_SHIFT
;
7390 tp
->key_mask
[1] = TCAM_V4KEY1_L2RDCNUM
;
7392 tp
->key
[3] = (u64
)sip
<< TCAM_V4KEY3_SADDR_SHIFT
;
7395 tp
->key_mask
[3] = (u64
)sipm
<< TCAM_V4KEY3_SADDR_SHIFT
;
7396 tp
->key_mask
[3] |= dipm
;
7398 tp
->key
[2] |= ((u64
)fsp
->h_u
.tcp_ip4_spec
.tos
<<
7399 TCAM_V4KEY2_TOS_SHIFT
);
7400 tp
->key_mask
[2] |= ((u64
)fsp
->m_u
.tcp_ip4_spec
.tos
<<
7401 TCAM_V4KEY2_TOS_SHIFT
);
7402 switch (fsp
->flow_type
) {
7406 sport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7407 spm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7408 dport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7409 dpm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7411 tp
->key
[2] |= (((u64
)sport
<< 16) | dport
);
7412 tp
->key_mask
[2] |= (((u64
)spm
<< 16) | dpm
);
7413 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7417 spi
= be32_to_cpu(fsp
->h_u
.ah_ip4_spec
.spi
);
7418 spim
= be32_to_cpu(fsp
->m_u
.ah_ip4_spec
.spi
);
7421 tp
->key_mask
[2] |= spim
;
7422 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7425 spi
= be32_to_cpu(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7426 spim
= be32_to_cpu(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7429 tp
->key_mask
[2] |= spim
;
7430 pid
= fsp
->h_u
.usr_ip4_spec
.proto
;
7436 tp
->key
[2] |= ((u64
)pid
<< TCAM_V4KEY2_PROTO_SHIFT
);
7438 tp
->key_mask
[2] |= TCAM_V4KEY2_PROTO
;
7442 static int niu_add_ethtool_tcam_entry(struct niu
*np
,
7443 struct ethtool_rxnfc
*nfc
)
7445 struct niu_parent
*parent
= np
->parent
;
7446 struct niu_tcam_entry
*tp
;
7447 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7448 struct niu_rdc_tables
*rdc_table
= &parent
->rdc_group_cfg
[np
->port
];
7449 int l2_rdc_table
= rdc_table
->first_table_num
;
7452 unsigned long flags
;
7457 idx
= nfc
->fs
.location
;
7458 if (idx
>= tcam_get_size(np
))
7461 if (fsp
->flow_type
== IP_USER_FLOW
) {
7463 int add_usr_cls
= 0;
7464 struct ethtool_usrip4_spec
*uspec
= &fsp
->h_u
.usr_ip4_spec
;
7465 struct ethtool_usrip4_spec
*umask
= &fsp
->m_u
.usr_ip4_spec
;
7467 if (uspec
->ip_ver
!= ETH_RX_NFC_IP4
)
7470 niu_lock_parent(np
, flags
);
7472 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7473 if (parent
->l3_cls
[i
]) {
7474 if (uspec
->proto
== parent
->l3_cls_pid
[i
]) {
7475 class = parent
->l3_cls
[i
];
7476 parent
->l3_cls_refcnt
[i
]++;
7481 /* Program new user IP class */
7484 class = CLASS_CODE_USER_PROG1
;
7487 class = CLASS_CODE_USER_PROG2
;
7490 class = CLASS_CODE_USER_PROG3
;
7493 class = CLASS_CODE_USER_PROG4
;
7498 ret
= tcam_user_ip_class_set(np
, class, 0,
7505 ret
= tcam_user_ip_class_enable(np
, class, 1);
7508 parent
->l3_cls
[i
] = class;
7509 parent
->l3_cls_pid
[i
] = uspec
->proto
;
7510 parent
->l3_cls_refcnt
[i
]++;
7516 netdev_info(np
->dev
, "niu%d: %s(): Could not find/insert class for pid %d\n",
7517 parent
->index
, __func__
, uspec
->proto
);
7521 niu_unlock_parent(np
, flags
);
7523 if (!niu_ethflow_to_class(fsp
->flow_type
, &class)) {
7528 niu_lock_parent(np
, flags
);
7530 idx
= tcam_get_index(np
, idx
);
7531 tp
= &parent
->tcam
[idx
];
7533 memset(tp
, 0, sizeof(*tp
));
7535 /* fill in the tcam key and mask */
7536 switch (fsp
->flow_type
) {
7542 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7549 /* Not yet implemented */
7550 netdev_info(np
->dev
, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7551 parent
->index
, __func__
, fsp
->flow_type
);
7555 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7558 netdev_info(np
->dev
, "niu%d: In %s(): Unknown flow type %d\n",
7559 parent
->index
, __func__
, fsp
->flow_type
);
7564 /* fill in the assoc data */
7565 if (fsp
->ring_cookie
== RX_CLS_FLOW_DISC
) {
7566 tp
->assoc_data
= TCAM_ASSOCDATA_DISC
;
7568 if (fsp
->ring_cookie
>= np
->num_rx_rings
) {
7569 netdev_info(np
->dev
, "niu%d: In %s(): Invalid RX ring %lld\n",
7570 parent
->index
, __func__
,
7571 (long long)fsp
->ring_cookie
);
7575 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
7576 (fsp
->ring_cookie
<<
7577 TCAM_ASSOCDATA_OFFSET_SHIFT
));
7580 err
= tcam_write(np
, idx
, tp
->key
, tp
->key_mask
);
7585 err
= tcam_assoc_write(np
, idx
, tp
->assoc_data
);
7591 /* validate the entry */
7593 np
->clas
.tcam_valid_entries
++;
7595 niu_unlock_parent(np
, flags
);
7600 static int niu_del_ethtool_tcam_entry(struct niu
*np
, u32 loc
)
7602 struct niu_parent
*parent
= np
->parent
;
7603 struct niu_tcam_entry
*tp
;
7605 unsigned long flags
;
7609 if (loc
>= tcam_get_size(np
))
7612 niu_lock_parent(np
, flags
);
7614 idx
= tcam_get_index(np
, loc
);
7615 tp
= &parent
->tcam
[idx
];
7617 /* if the entry is of a user defined class, then update*/
7618 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7619 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7621 if (class >= CLASS_CODE_USER_PROG1
&& class <= CLASS_CODE_USER_PROG4
) {
7623 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7624 if (parent
->l3_cls
[i
] == class) {
7625 parent
->l3_cls_refcnt
[i
]--;
7626 if (!parent
->l3_cls_refcnt
[i
]) {
7628 ret
= tcam_user_ip_class_enable(np
,
7633 parent
->l3_cls
[i
] = 0;
7634 parent
->l3_cls_pid
[i
] = 0;
7639 if (i
== NIU_L3_PROG_CLS
) {
7640 netdev_info(np
->dev
, "niu%d: In %s(): Usr class 0x%llx not found\n",
7641 parent
->index
, __func__
,
7642 (unsigned long long)class);
7648 ret
= tcam_flush(np
, idx
);
7652 /* invalidate the entry */
7654 np
->clas
.tcam_valid_entries
--;
7656 niu_unlock_parent(np
, flags
);
7661 static int niu_set_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
7663 struct niu
*np
= netdev_priv(dev
);
7668 ret
= niu_set_hash_opts(np
, cmd
);
7670 case ETHTOOL_SRXCLSRLINS
:
7671 ret
= niu_add_ethtool_tcam_entry(np
, cmd
);
7673 case ETHTOOL_SRXCLSRLDEL
:
7674 ret
= niu_del_ethtool_tcam_entry(np
, cmd
->fs
.location
);
7684 static const struct {
7685 const char string
[ETH_GSTRING_LEN
];
7686 } niu_xmac_stat_keys
[] = {
7689 { "tx_fifo_errors" },
7690 { "tx_overflow_errors" },
7691 { "tx_max_pkt_size_errors" },
7692 { "tx_underflow_errors" },
7693 { "rx_local_faults" },
7694 { "rx_remote_faults" },
7695 { "rx_link_faults" },
7696 { "rx_align_errors" },
7708 { "rx_code_violations" },
7709 { "rx_len_errors" },
7710 { "rx_crc_errors" },
7711 { "rx_underflows" },
7713 { "pause_off_state" },
7714 { "pause_on_state" },
7715 { "pause_received" },
7718 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7720 static const struct {
7721 const char string
[ETH_GSTRING_LEN
];
7722 } niu_bmac_stat_keys
[] = {
7723 { "tx_underflow_errors" },
7724 { "tx_max_pkt_size_errors" },
7729 { "rx_align_errors" },
7730 { "rx_crc_errors" },
7731 { "rx_len_errors" },
7732 { "pause_off_state" },
7733 { "pause_on_state" },
7734 { "pause_received" },
7737 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7739 static const struct {
7740 const char string
[ETH_GSTRING_LEN
];
7741 } niu_rxchan_stat_keys
[] = {
7749 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7751 static const struct {
7752 const char string
[ETH_GSTRING_LEN
];
7753 } niu_txchan_stat_keys
[] = {
7760 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7762 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
7764 struct niu
*np
= netdev_priv(dev
);
7767 if (stringset
!= ETH_SS_STATS
)
7770 if (np
->flags
& NIU_FLAGS_XMAC
) {
7771 memcpy(data
, niu_xmac_stat_keys
,
7772 sizeof(niu_xmac_stat_keys
));
7773 data
+= sizeof(niu_xmac_stat_keys
);
7775 memcpy(data
, niu_bmac_stat_keys
,
7776 sizeof(niu_bmac_stat_keys
));
7777 data
+= sizeof(niu_bmac_stat_keys
);
7779 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7780 memcpy(data
, niu_rxchan_stat_keys
,
7781 sizeof(niu_rxchan_stat_keys
));
7782 data
+= sizeof(niu_rxchan_stat_keys
);
7784 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7785 memcpy(data
, niu_txchan_stat_keys
,
7786 sizeof(niu_txchan_stat_keys
));
7787 data
+= sizeof(niu_txchan_stat_keys
);
7791 static int niu_get_sset_count(struct net_device
*dev
, int stringset
)
7793 struct niu
*np
= netdev_priv(dev
);
7795 if (stringset
!= ETH_SS_STATS
)
7798 return (np
->flags
& NIU_FLAGS_XMAC
?
7799 NUM_XMAC_STAT_KEYS
:
7800 NUM_BMAC_STAT_KEYS
) +
7801 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
7802 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
);
7805 static void niu_get_ethtool_stats(struct net_device
*dev
,
7806 struct ethtool_stats
*stats
, u64
*data
)
7808 struct niu
*np
= netdev_priv(dev
);
7811 niu_sync_mac_stats(np
);
7812 if (np
->flags
& NIU_FLAGS_XMAC
) {
7813 memcpy(data
, &np
->mac_stats
.xmac
,
7814 sizeof(struct niu_xmac_stats
));
7815 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
7817 memcpy(data
, &np
->mac_stats
.bmac
,
7818 sizeof(struct niu_bmac_stats
));
7819 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
7821 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7822 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
7824 niu_sync_rx_discard_stats(np
, rp
, 0);
7826 data
[0] = rp
->rx_channel
;
7827 data
[1] = rp
->rx_packets
;
7828 data
[2] = rp
->rx_bytes
;
7829 data
[3] = rp
->rx_dropped
;
7830 data
[4] = rp
->rx_errors
;
7833 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7834 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
7836 data
[0] = rp
->tx_channel
;
7837 data
[1] = rp
->tx_packets
;
7838 data
[2] = rp
->tx_bytes
;
7839 data
[3] = rp
->tx_errors
;
7844 static u64
niu_led_state_save(struct niu
*np
)
7846 if (np
->flags
& NIU_FLAGS_XMAC
)
7847 return nr64_mac(XMAC_CONFIG
);
7849 return nr64_mac(BMAC_XIF_CONFIG
);
7852 static void niu_led_state_restore(struct niu
*np
, u64 val
)
7854 if (np
->flags
& NIU_FLAGS_XMAC
)
7855 nw64_mac(XMAC_CONFIG
, val
);
7857 nw64_mac(BMAC_XIF_CONFIG
, val
);
7860 static void niu_force_led(struct niu
*np
, int on
)
7864 if (np
->flags
& NIU_FLAGS_XMAC
) {
7866 bit
= XMAC_CONFIG_FORCE_LED_ON
;
7868 reg
= BMAC_XIF_CONFIG
;
7869 bit
= BMAC_XIF_CONFIG_LINK_LED
;
7872 val
= nr64_mac(reg
);
7880 static int niu_phys_id(struct net_device
*dev
, u32 data
)
7882 struct niu
*np
= netdev_priv(dev
);
7886 if (!netif_running(dev
))
7892 orig_led_state
= niu_led_state_save(np
);
7893 for (i
= 0; i
< (data
* 2); i
++) {
7894 int on
= ((i
% 2) == 0);
7896 niu_force_led(np
, on
);
7898 if (msleep_interruptible(500))
7901 niu_led_state_restore(np
, orig_led_state
);
7906 static int niu_set_flags(struct net_device
*dev
, u32 data
)
7908 return ethtool_op_set_flags(dev
, data
, ETH_FLAG_RXHASH
);
7911 static const struct ethtool_ops niu_ethtool_ops
= {
7912 .get_drvinfo
= niu_get_drvinfo
,
7913 .get_link
= ethtool_op_get_link
,
7914 .get_msglevel
= niu_get_msglevel
,
7915 .set_msglevel
= niu_set_msglevel
,
7916 .nway_reset
= niu_nway_reset
,
7917 .get_eeprom_len
= niu_get_eeprom_len
,
7918 .get_eeprom
= niu_get_eeprom
,
7919 .get_settings
= niu_get_settings
,
7920 .set_settings
= niu_set_settings
,
7921 .get_strings
= niu_get_strings
,
7922 .get_sset_count
= niu_get_sset_count
,
7923 .get_ethtool_stats
= niu_get_ethtool_stats
,
7924 .phys_id
= niu_phys_id
,
7925 .get_rxnfc
= niu_get_nfc
,
7926 .set_rxnfc
= niu_set_nfc
,
7927 .set_flags
= niu_set_flags
,
7928 .get_flags
= ethtool_op_get_flags
,
7931 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
7934 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
7936 if (ldn
< 0 || ldn
> LDN_MAX
)
7939 parent
->ldg_map
[ldn
] = ldg
;
7941 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
7942 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7943 * the firmware, and we're not supposed to change them.
7944 * Validate the mapping, because if it's wrong we probably
7945 * won't get any interrupts and that's painful to debug.
7947 if (nr64(LDG_NUM(ldn
)) != ldg
) {
7948 dev_err(np
->device
, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7950 (unsigned long long) nr64(LDG_NUM(ldn
)));
7954 nw64(LDG_NUM(ldn
), ldg
);
7959 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
7961 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
7965 nw64(LDG_TIMER_RES
, res
);
7970 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
7972 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
7973 (func
< 0 || func
> 3) ||
7974 (vector
< 0 || vector
> 0x1f))
7977 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
7982 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
7984 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
7985 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
7988 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
7992 nw64(ESPC_PIO_STAT
, frame
);
7996 frame
= nr64(ESPC_PIO_STAT
);
7997 if (frame
& ESPC_PIO_STAT_READ_END
)
8000 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8001 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8002 (unsigned long long) frame
);
8007 nw64(ESPC_PIO_STAT
, frame
);
8011 frame
= nr64(ESPC_PIO_STAT
);
8012 if (frame
& ESPC_PIO_STAT_READ_END
)
8015 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8016 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8017 (unsigned long long) frame
);
8021 frame
= nr64(ESPC_PIO_STAT
);
8022 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
8025 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
8027 int err
= niu_pci_eeprom_read(np
, off
);
8033 err
= niu_pci_eeprom_read(np
, off
+ 1);
8036 val
|= (err
& 0xff);
8041 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
8043 int err
= niu_pci_eeprom_read(np
, off
);
8050 err
= niu_pci_eeprom_read(np
, off
+ 1);
8054 val
|= (err
& 0xff) << 8;
8059 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
8066 for (i
= 0; i
< namebuf_len
; i
++) {
8067 int err
= niu_pci_eeprom_read(np
, off
+ i
);
8074 if (i
>= namebuf_len
)
8080 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
8082 struct niu_vpd
*vpd
= &np
->vpd
;
8083 int len
= strlen(vpd
->version
) + 1;
8084 const char *s
= vpd
->version
;
8087 for (i
= 0; i
< len
- 5; i
++) {
8088 if (!strncmp(s
+ i
, "FCode ", 6))
8095 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
8097 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8098 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8099 vpd
->fcode_major
, vpd
->fcode_minor
);
8100 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
8101 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
8102 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
8103 np
->flags
|= NIU_FLAGS_VPD_VALID
;
8106 /* ESPC_PIO_EN_ENABLE must be set */
8107 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
8110 unsigned int found_mask
= 0;
8111 #define FOUND_MASK_MODEL 0x00000001
8112 #define FOUND_MASK_BMODEL 0x00000002
8113 #define FOUND_MASK_VERS 0x00000004
8114 #define FOUND_MASK_MAC 0x00000008
8115 #define FOUND_MASK_NMAC 0x00000010
8116 #define FOUND_MASK_PHY 0x00000020
8117 #define FOUND_MASK_ALL 0x0000003f
8119 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8120 "VPD_SCAN: start[%x] end[%x]\n", start
, end
);
8121 while (start
< end
) {
8122 int len
, err
, instance
, type
, prop_len
;
8127 if (found_mask
== FOUND_MASK_ALL
) {
8128 niu_vpd_parse_version(np
);
8132 err
= niu_pci_eeprom_read(np
, start
+ 2);
8138 instance
= niu_pci_eeprom_read(np
, start
);
8139 type
= niu_pci_eeprom_read(np
, start
+ 3);
8140 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
8141 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
8147 if (!strcmp(namebuf
, "model")) {
8148 prop_buf
= np
->vpd
.model
;
8149 max_len
= NIU_VPD_MODEL_MAX
;
8150 found_mask
|= FOUND_MASK_MODEL
;
8151 } else if (!strcmp(namebuf
, "board-model")) {
8152 prop_buf
= np
->vpd
.board_model
;
8153 max_len
= NIU_VPD_BD_MODEL_MAX
;
8154 found_mask
|= FOUND_MASK_BMODEL
;
8155 } else if (!strcmp(namebuf
, "version")) {
8156 prop_buf
= np
->vpd
.version
;
8157 max_len
= NIU_VPD_VERSION_MAX
;
8158 found_mask
|= FOUND_MASK_VERS
;
8159 } else if (!strcmp(namebuf
, "local-mac-address")) {
8160 prop_buf
= np
->vpd
.local_mac
;
8162 found_mask
|= FOUND_MASK_MAC
;
8163 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
8164 prop_buf
= &np
->vpd
.mac_num
;
8166 found_mask
|= FOUND_MASK_NMAC
;
8167 } else if (!strcmp(namebuf
, "phy-type")) {
8168 prop_buf
= np
->vpd
.phy_type
;
8169 max_len
= NIU_VPD_PHY_TYPE_MAX
;
8170 found_mask
|= FOUND_MASK_PHY
;
8173 if (max_len
&& prop_len
> max_len
) {
8174 dev_err(np
->device
, "Property '%s' length (%d) is too long\n", namebuf
, prop_len
);
8179 u32 off
= start
+ 5 + err
;
8182 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8183 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8185 for (i
= 0; i
< prop_len
; i
++)
8186 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
8195 /* ESPC_PIO_EN_ENABLE must be set */
8196 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
8201 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
8207 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
8208 u32 here
= start
+ offset
;
8211 err
= niu_pci_eeprom_read(np
, here
);
8215 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
8219 here
= start
+ offset
+ 3;
8220 end
= start
+ offset
+ err
;
8224 err
= niu_pci_vpd_scan_props(np
, here
, end
);
8225 if (err
< 0 || err
== 1)
8230 /* ESPC_PIO_EN_ENABLE must be set */
8231 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
8233 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
8236 while (start
< end
) {
8239 /* ROM header signature? */
8240 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8244 /* Apply offset to PCI data structure. */
8245 err
= niu_pci_eeprom_read16(np
, start
+ 23);
8250 /* Check for "PCIR" signature. */
8251 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8254 err
= niu_pci_eeprom_read16(np
, start
+ 2);
8258 /* Check for OBP image type. */
8259 err
= niu_pci_eeprom_read(np
, start
+ 20);
8263 err
= niu_pci_eeprom_read(np
, ret
+ 2);
8267 start
= ret
+ (err
* 512);
8271 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
8276 err
= niu_pci_eeprom_read(np
, ret
+ 0);
8286 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
8287 const char *phy_prop
)
8289 if (!strcmp(phy_prop
, "mif")) {
8290 /* 1G copper, MII */
8291 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8293 np
->mac_xcvr
= MAC_XCVR_MII
;
8294 } else if (!strcmp(phy_prop
, "xgf")) {
8295 /* 10G fiber, XPCS */
8296 np
->flags
|= (NIU_FLAGS_10G
|
8298 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8299 } else if (!strcmp(phy_prop
, "pcs")) {
8301 np
->flags
&= ~NIU_FLAGS_10G
;
8302 np
->flags
|= NIU_FLAGS_FIBER
;
8303 np
->mac_xcvr
= MAC_XCVR_PCS
;
8304 } else if (!strcmp(phy_prop
, "xgc")) {
8305 /* 10G copper, XPCS */
8306 np
->flags
|= NIU_FLAGS_10G
;
8307 np
->flags
&= ~NIU_FLAGS_FIBER
;
8308 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8309 } else if (!strcmp(phy_prop
, "xgsd") || !strcmp(phy_prop
, "gsd")) {
8310 /* 10G Serdes or 1G Serdes, default to 10G */
8311 np
->flags
|= NIU_FLAGS_10G
;
8312 np
->flags
&= ~NIU_FLAGS_FIBER
;
8313 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8314 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8321 static int niu_pci_vpd_get_nports(struct niu
*np
)
8325 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
8326 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
8327 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
8328 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
8329 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
8331 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
8332 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
8333 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
8334 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
8341 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
8343 struct net_device
*dev
= np
->dev
;
8344 struct niu_vpd
*vpd
= &np
->vpd
;
8347 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
8348 dev_err(np
->device
, "VPD MAC invalid, falling back to SPROM\n");
8350 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8354 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8355 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8356 np
->flags
|= NIU_FLAGS_10G
;
8357 np
->flags
&= ~NIU_FLAGS_FIBER
;
8358 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8359 np
->mac_xcvr
= MAC_XCVR_PCS
;
8361 np
->flags
|= NIU_FLAGS_FIBER
;
8362 np
->flags
&= ~NIU_FLAGS_10G
;
8364 if (np
->flags
& NIU_FLAGS_10G
)
8365 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8366 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8367 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
8368 NIU_FLAGS_HOTPLUG_PHY
);
8369 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8370 dev_err(np
->device
, "Illegal phy string [%s]\n",
8372 dev_err(np
->device
, "Falling back to SPROM\n");
8373 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8377 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
8379 val8
= dev
->perm_addr
[5];
8380 dev
->perm_addr
[5] += np
->port
;
8381 if (dev
->perm_addr
[5] < val8
)
8382 dev
->perm_addr
[4]++;
8384 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8387 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
8389 struct net_device
*dev
= np
->dev
;
8394 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
8395 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
8398 np
->eeprom_len
= len
;
8400 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8401 "SPROM: Image size %llu\n", (unsigned long long)val
);
8404 for (i
= 0; i
< len
; i
++) {
8405 val
= nr64(ESPC_NCR(i
));
8406 sum
+= (val
>> 0) & 0xff;
8407 sum
+= (val
>> 8) & 0xff;
8408 sum
+= (val
>> 16) & 0xff;
8409 sum
+= (val
>> 24) & 0xff;
8411 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8412 "SPROM: Checksum %x\n", (int)(sum
& 0xff));
8413 if ((sum
& 0xff) != 0xab) {
8414 dev_err(np
->device
, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum
& 0xff));
8418 val
= nr64(ESPC_PHY_TYPE
);
8421 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
8422 ESPC_PHY_TYPE_PORT0_SHIFT
;
8425 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
8426 ESPC_PHY_TYPE_PORT1_SHIFT
;
8429 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
8430 ESPC_PHY_TYPE_PORT2_SHIFT
;
8433 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
8434 ESPC_PHY_TYPE_PORT3_SHIFT
;
8437 dev_err(np
->device
, "Bogus port number %u\n",
8441 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8442 "SPROM: PHY type %x\n", val8
);
8445 case ESPC_PHY_TYPE_1G_COPPER
:
8446 /* 1G copper, MII */
8447 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8449 np
->mac_xcvr
= MAC_XCVR_MII
;
8452 case ESPC_PHY_TYPE_1G_FIBER
:
8454 np
->flags
&= ~NIU_FLAGS_10G
;
8455 np
->flags
|= NIU_FLAGS_FIBER
;
8456 np
->mac_xcvr
= MAC_XCVR_PCS
;
8459 case ESPC_PHY_TYPE_10G_COPPER
:
8460 /* 10G copper, XPCS */
8461 np
->flags
|= NIU_FLAGS_10G
;
8462 np
->flags
&= ~NIU_FLAGS_FIBER
;
8463 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8466 case ESPC_PHY_TYPE_10G_FIBER
:
8467 /* 10G fiber, XPCS */
8468 np
->flags
|= (NIU_FLAGS_10G
|
8470 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8474 dev_err(np
->device
, "Bogus SPROM phy type %u\n", val8
);
8478 val
= nr64(ESPC_MAC_ADDR0
);
8479 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8480 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val
);
8481 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
8482 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
8483 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
8484 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
8486 val
= nr64(ESPC_MAC_ADDR1
);
8487 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8488 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val
);
8489 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
8490 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
8492 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
8493 dev_err(np
->device
, "SPROM MAC address invalid [ %pM ]\n",
8498 val8
= dev
->perm_addr
[5];
8499 dev
->perm_addr
[5] += np
->port
;
8500 if (dev
->perm_addr
[5] < val8
)
8501 dev
->perm_addr
[4]++;
8503 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8505 val
= nr64(ESPC_MOD_STR_LEN
);
8506 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8507 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8511 for (i
= 0; i
< val
; i
+= 4) {
8512 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
8514 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
8515 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
8516 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
8517 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
8519 np
->vpd
.model
[val
] = '\0';
8521 val
= nr64(ESPC_BD_MOD_STR_LEN
);
8522 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8523 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8527 for (i
= 0; i
< val
; i
+= 4) {
8528 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
8530 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
8531 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
8532 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
8533 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
8535 np
->vpd
.board_model
[val
] = '\0';
8538 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
8539 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8540 "SPROM: NUM_PORTS_MACS[%d]\n", np
->vpd
.mac_num
);
8545 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
8547 struct niu_parent
*parent
= np
->parent
;
8550 np
->flags
|= NIU_FLAGS_XMAC
;
8552 if (!parent
->num_ports
) {
8553 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8554 parent
->num_ports
= 2;
8556 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
8557 if (!parent
->num_ports
) {
8558 /* Fall back to SPROM as last resort.
8559 * This will fail on most cards.
8561 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
8562 ESPC_NUM_PORTS_MACS_VAL
;
8564 /* All of the current probing methods fail on
8565 * Maramba on-board parts.
8567 if (!parent
->num_ports
)
8568 parent
->num_ports
= 4;
8573 if (np
->port
>= parent
->num_ports
)
8579 static int __devinit
phy_record(struct niu_parent
*parent
,
8580 struct phy_probe_info
*p
,
8581 int dev_id_1
, int dev_id_2
, u8 phy_port
,
8584 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
8587 if (dev_id_1
< 0 || dev_id_2
< 0)
8589 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
8590 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
8591 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
8592 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
8595 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
8599 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8601 type
== PHY_TYPE_PMA_PMD
? "PMA/PMD" :
8602 type
== PHY_TYPE_PCS
? "PCS" : "MII",
8605 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
8606 pr_err("Too many PHY ports\n");
8610 p
->phy_id
[type
][idx
] = id
;
8611 p
->phy_port
[type
][idx
] = phy_port
;
8612 p
->cur
[type
] = idx
+ 1;
8616 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
8620 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
8621 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
8624 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
8625 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
8632 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
8638 for (port
= 8; port
< 32; port
++) {
8639 if (port_has_10g(p
, port
)) {
8649 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
8652 if (p
->cur
[PHY_TYPE_MII
])
8653 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
8655 return p
->cur
[PHY_TYPE_MII
];
8658 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
8660 int num_ports
= parent
->num_ports
;
8663 for (i
= 0; i
< num_ports
; i
++) {
8664 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
8665 parent
->txchan_per_port
[i
] = (16 / num_ports
);
8667 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8669 parent
->rxchan_per_port
[i
],
8670 parent
->txchan_per_port
[i
]);
8674 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
8675 int num_10g
, int num_1g
)
8677 int num_ports
= parent
->num_ports
;
8678 int rx_chans_per_10g
, rx_chans_per_1g
;
8679 int tx_chans_per_10g
, tx_chans_per_1g
;
8680 int i
, tot_rx
, tot_tx
;
8682 if (!num_10g
|| !num_1g
) {
8683 rx_chans_per_10g
= rx_chans_per_1g
=
8684 (NIU_NUM_RXCHAN
/ num_ports
);
8685 tx_chans_per_10g
= tx_chans_per_1g
=
8686 (NIU_NUM_TXCHAN
/ num_ports
);
8688 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
8689 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
8690 (rx_chans_per_1g
* num_1g
)) /
8693 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
8694 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
8695 (tx_chans_per_1g
* num_1g
)) /
8699 tot_rx
= tot_tx
= 0;
8700 for (i
= 0; i
< num_ports
; i
++) {
8701 int type
= phy_decode(parent
->port_phy
, i
);
8703 if (type
== PORT_TYPE_10G
) {
8704 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
8705 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
8707 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
8708 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
8710 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8712 parent
->rxchan_per_port
[i
],
8713 parent
->txchan_per_port
[i
]);
8714 tot_rx
+= parent
->rxchan_per_port
[i
];
8715 tot_tx
+= parent
->txchan_per_port
[i
];
8718 if (tot_rx
> NIU_NUM_RXCHAN
) {
8719 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8720 parent
->index
, tot_rx
);
8721 for (i
= 0; i
< num_ports
; i
++)
8722 parent
->rxchan_per_port
[i
] = 1;
8724 if (tot_tx
> NIU_NUM_TXCHAN
) {
8725 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8726 parent
->index
, tot_tx
);
8727 for (i
= 0; i
< num_ports
; i
++)
8728 parent
->txchan_per_port
[i
] = 1;
8730 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
8731 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8732 parent
->index
, tot_rx
, tot_tx
);
8736 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
8737 int num_10g
, int num_1g
)
8739 int i
, num_ports
= parent
->num_ports
;
8740 int rdc_group
, rdc_groups_per_port
;
8741 int rdc_channel_base
;
8744 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
8746 rdc_channel_base
= 0;
8748 for (i
= 0; i
< num_ports
; i
++) {
8749 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
8750 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
8751 int this_channel_offset
;
8753 tp
->first_table_num
= rdc_group
;
8754 tp
->num_tables
= rdc_groups_per_port
;
8755 this_channel_offset
= 0;
8756 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
8757 struct rdc_table
*rt
= &tp
->tables
[grp
];
8760 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8761 parent
->index
, i
, tp
->first_table_num
+ grp
);
8762 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
8763 rt
->rxdma_channel
[slot
] =
8764 rdc_channel_base
+ this_channel_offset
;
8766 pr_cont("%d ", rt
->rxdma_channel
[slot
]);
8768 if (++this_channel_offset
== num_channels
)
8769 this_channel_offset
= 0;
8774 parent
->rdc_default
[i
] = rdc_channel_base
;
8776 rdc_channel_base
+= num_channels
;
8777 rdc_group
+= rdc_groups_per_port
;
8781 static int __devinit
fill_phy_probe_info(struct niu
*np
,
8782 struct niu_parent
*parent
,
8783 struct phy_probe_info
*info
)
8785 unsigned long flags
;
8788 memset(info
, 0, sizeof(*info
));
8790 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8791 niu_lock_parent(np
, flags
);
8793 for (port
= 8; port
< 32; port
++) {
8794 int dev_id_1
, dev_id_2
;
8796 dev_id_1
= mdio_read(np
, port
,
8797 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
8798 dev_id_2
= mdio_read(np
, port
,
8799 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
8800 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8804 dev_id_1
= mdio_read(np
, port
,
8805 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
8806 dev_id_2
= mdio_read(np
, port
,
8807 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
8808 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8812 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
8813 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
8814 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8819 niu_unlock_parent(np
, flags
);
8824 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
8826 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
8827 int lowest_10g
, lowest_1g
;
8828 int num_10g
, num_1g
;
8832 num_10g
= num_1g
= 0;
8834 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8835 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8838 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
8839 parent
->num_ports
= 4;
8840 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8841 phy_encode(PORT_TYPE_1G
, 1) |
8842 phy_encode(PORT_TYPE_1G
, 2) |
8843 phy_encode(PORT_TYPE_1G
, 3));
8844 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8847 parent
->num_ports
= 2;
8848 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8849 phy_encode(PORT_TYPE_10G
, 1));
8850 } else if ((np
->flags
& NIU_FLAGS_XCVR_SERDES
) &&
8851 (parent
->plat_type
== PLAT_TYPE_NIU
)) {
8852 /* this is the Monza case */
8853 if (np
->flags
& NIU_FLAGS_10G
) {
8854 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8855 phy_encode(PORT_TYPE_10G
, 1));
8857 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8858 phy_encode(PORT_TYPE_1G
, 1));
8861 err
= fill_phy_probe_info(np
, parent
, info
);
8865 num_10g
= count_10g_ports(info
, &lowest_10g
);
8866 num_1g
= count_1g_ports(info
, &lowest_1g
);
8868 switch ((num_10g
<< 4) | num_1g
) {
8870 if (lowest_1g
== 10)
8871 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8872 else if (lowest_1g
== 26)
8873 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8875 goto unknown_vg_1g_port
;
8879 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8880 phy_encode(PORT_TYPE_10G
, 1) |
8881 phy_encode(PORT_TYPE_1G
, 2) |
8882 phy_encode(PORT_TYPE_1G
, 3));
8886 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8887 phy_encode(PORT_TYPE_10G
, 1));
8891 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
8895 if (lowest_1g
== 10)
8896 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8897 else if (lowest_1g
== 26)
8898 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8900 goto unknown_vg_1g_port
;
8904 if ((lowest_10g
& 0x7) == 0)
8905 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8906 phy_encode(PORT_TYPE_1G
, 1) |
8907 phy_encode(PORT_TYPE_1G
, 2) |
8908 phy_encode(PORT_TYPE_1G
, 3));
8910 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8911 phy_encode(PORT_TYPE_10G
, 1) |
8912 phy_encode(PORT_TYPE_1G
, 2) |
8913 phy_encode(PORT_TYPE_1G
, 3));
8917 if (lowest_1g
== 10)
8918 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8919 else if (lowest_1g
== 26)
8920 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8922 goto unknown_vg_1g_port
;
8924 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8925 phy_encode(PORT_TYPE_1G
, 1) |
8926 phy_encode(PORT_TYPE_1G
, 2) |
8927 phy_encode(PORT_TYPE_1G
, 3));
8931 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8937 parent
->port_phy
= val
;
8939 if (parent
->plat_type
== PLAT_TYPE_NIU
)
8940 niu_n2_divide_channels(parent
);
8942 niu_divide_channels(parent
, num_10g
, num_1g
);
8944 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
8949 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g
);
8953 static int __devinit
niu_probe_ports(struct niu
*np
)
8955 struct niu_parent
*parent
= np
->parent
;
8958 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
8959 err
= walk_phys(np
, parent
);
8963 niu_set_ldg_timer_res(np
, 2);
8964 for (i
= 0; i
<= LDN_MAX
; i
++)
8965 niu_ldn_irq_enable(np
, i
, 0);
8968 if (parent
->port_phy
== PORT_PHY_INVALID
)
8974 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
8976 struct niu_classifier
*cp
= &np
->clas
;
8978 cp
->tcam_top
= (u16
) np
->port
;
8979 cp
->tcam_sz
= np
->parent
->tcam_num_entries
/ np
->parent
->num_ports
;
8980 cp
->h1_init
= 0xffffffff;
8981 cp
->h2_init
= 0xffff;
8983 return fflp_early_init(np
);
8986 static void __devinit
niu_link_config_init(struct niu
*np
)
8988 struct niu_link_config
*lp
= &np
->link_config
;
8990 lp
->advertising
= (ADVERTISED_10baseT_Half
|
8991 ADVERTISED_10baseT_Full
|
8992 ADVERTISED_100baseT_Half
|
8993 ADVERTISED_100baseT_Full
|
8994 ADVERTISED_1000baseT_Half
|
8995 ADVERTISED_1000baseT_Full
|
8996 ADVERTISED_10000baseT_Full
|
8997 ADVERTISED_Autoneg
);
8998 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
8999 lp
->duplex
= DUPLEX_FULL
;
9000 lp
->active_duplex
= DUPLEX_INVALID
;
9003 lp
->loopback_mode
= LOOPBACK_MAC
;
9004 lp
->active_speed
= SPEED_10000
;
9005 lp
->active_duplex
= DUPLEX_FULL
;
9007 lp
->loopback_mode
= LOOPBACK_DISABLED
;
9011 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
9015 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
9016 np
->ipp_off
= 0x00000;
9017 np
->pcs_off
= 0x04000;
9018 np
->xpcs_off
= 0x02000;
9022 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
9023 np
->ipp_off
= 0x08000;
9024 np
->pcs_off
= 0x0a000;
9025 np
->xpcs_off
= 0x08000;
9029 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
9030 np
->ipp_off
= 0x04000;
9031 np
->pcs_off
= 0x0e000;
9032 np
->xpcs_off
= ~0UL;
9036 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
9037 np
->ipp_off
= 0x0c000;
9038 np
->pcs_off
= 0x12000;
9039 np
->xpcs_off
= ~0UL;
9043 dev_err(np
->device
, "Port %u is invalid, cannot compute MAC block offset\n", np
->port
);
9050 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
9052 struct msix_entry msi_vec
[NIU_NUM_LDG
];
9053 struct niu_parent
*parent
= np
->parent
;
9054 struct pci_dev
*pdev
= np
->pdev
;
9055 int i
, num_irqs
, err
;
9058 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
9059 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
9060 ldg_num_map
[i
] = first_ldg
+ i
;
9062 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
9063 parent
->txchan_per_port
[np
->port
] +
9064 (np
->port
== 0 ? 3 : 1));
9065 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
9068 for (i
= 0; i
< num_irqs
; i
++) {
9069 msi_vec
[i
].vector
= 0;
9070 msi_vec
[i
].entry
= i
;
9073 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
9075 np
->flags
&= ~NIU_FLAGS_MSIX
;
9083 np
->flags
|= NIU_FLAGS_MSIX
;
9084 for (i
= 0; i
< num_irqs
; i
++)
9085 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
9086 np
->num_ldg
= num_irqs
;
9089 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
9091 #ifdef CONFIG_SPARC64
9092 struct platform_device
*op
= np
->op
;
9093 const u32
*int_prop
;
9096 int_prop
= of_get_property(op
->dev
.of_node
, "interrupts", NULL
);
9100 for (i
= 0; i
< op
->archdata
.num_irqs
; i
++) {
9101 ldg_num_map
[i
] = int_prop
[i
];
9102 np
->ldg
[i
].irq
= op
->archdata
.irqs
[i
];
9105 np
->num_ldg
= op
->archdata
.num_irqs
;
9113 static int __devinit
niu_ldg_init(struct niu
*np
)
9115 struct niu_parent
*parent
= np
->parent
;
9116 u8 ldg_num_map
[NIU_NUM_LDG
];
9117 int first_chan
, num_chan
;
9118 int i
, err
, ldg_rotor
;
9122 np
->ldg
[0].irq
= np
->dev
->irq
;
9123 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
9124 err
= niu_n2_irq_init(np
, ldg_num_map
);
9128 niu_try_msix(np
, ldg_num_map
);
9131 for (i
= 0; i
< np
->num_ldg
; i
++) {
9132 struct niu_ldg
*lp
= &np
->ldg
[i
];
9134 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
9137 lp
->ldg_num
= ldg_num_map
[i
];
9138 lp
->timer
= 2; /* XXX */
9140 /* On N2 NIU the firmware has setup the SID mappings so they go
9141 * to the correct values that will route the LDG to the proper
9142 * interrupt in the NCU interrupt table.
9144 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
9145 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
9151 /* We adopt the LDG assignment ordering used by the N2 NIU
9152 * 'interrupt' properties because that simplifies a lot of
9153 * things. This ordering is:
9156 * MIF (if port zero)
9157 * SYSERR (if port zero)
9164 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
9170 if (ldg_rotor
== np
->num_ldg
)
9174 err
= niu_ldg_assign_ldn(np
, parent
,
9175 ldg_num_map
[ldg_rotor
],
9181 if (ldg_rotor
== np
->num_ldg
)
9184 err
= niu_ldg_assign_ldn(np
, parent
,
9185 ldg_num_map
[ldg_rotor
],
9191 if (ldg_rotor
== np
->num_ldg
)
9197 for (i
= 0; i
< port
; i
++)
9198 first_chan
+= parent
->rxchan_per_port
[port
];
9199 num_chan
= parent
->rxchan_per_port
[port
];
9201 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9202 err
= niu_ldg_assign_ldn(np
, parent
,
9203 ldg_num_map
[ldg_rotor
],
9208 if (ldg_rotor
== np
->num_ldg
)
9213 for (i
= 0; i
< port
; i
++)
9214 first_chan
+= parent
->txchan_per_port
[port
];
9215 num_chan
= parent
->txchan_per_port
[port
];
9216 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9217 err
= niu_ldg_assign_ldn(np
, parent
,
9218 ldg_num_map
[ldg_rotor
],
9223 if (ldg_rotor
== np
->num_ldg
)
9230 static void __devexit
niu_ldg_free(struct niu
*np
)
9232 if (np
->flags
& NIU_FLAGS_MSIX
)
9233 pci_disable_msix(np
->pdev
);
9236 static int __devinit
niu_get_of_props(struct niu
*np
)
9238 #ifdef CONFIG_SPARC64
9239 struct net_device
*dev
= np
->dev
;
9240 struct device_node
*dp
;
9241 const char *phy_type
;
9246 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9247 dp
= np
->op
->dev
.of_node
;
9249 dp
= pci_device_to_OF_node(np
->pdev
);
9251 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
9253 netdev_err(dev
, "%s: OF node lacks phy-type property\n",
9258 if (!strcmp(phy_type
, "none"))
9261 strcpy(np
->vpd
.phy_type
, phy_type
);
9263 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
9264 netdev_err(dev
, "%s: Illegal phy string [%s]\n",
9265 dp
->full_name
, np
->vpd
.phy_type
);
9269 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
9271 netdev_err(dev
, "%s: OF node lacks local-mac-address property\n",
9275 if (prop_len
!= dev
->addr_len
) {
9276 netdev_err(dev
, "%s: OF MAC address prop len (%d) is wrong\n",
9277 dp
->full_name
, prop_len
);
9279 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
9280 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
9281 netdev_err(dev
, "%s: OF MAC address is invalid\n",
9283 netdev_err(dev
, "%s: [ %pM ]\n", dp
->full_name
, dev
->perm_addr
);
9287 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
9289 model
= of_get_property(dp
, "model", &prop_len
);
9292 strcpy(np
->vpd
.model
, model
);
9294 if (of_find_property(dp
, "hot-swappable-phy", &prop_len
)) {
9295 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
9296 NIU_FLAGS_HOTPLUG_PHY
);
9305 static int __devinit
niu_get_invariants(struct niu
*np
)
9307 int err
, have_props
;
9310 err
= niu_get_of_props(np
);
9316 err
= niu_init_mac_ipp_pcs_base(np
);
9321 err
= niu_get_and_validate_port(np
);
9326 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9329 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
9330 offset
= niu_pci_vpd_offset(np
);
9331 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9332 "%s() VPD offset [%08x]\n", __func__
, offset
);
9334 niu_pci_vpd_fetch(np
, offset
);
9335 nw64(ESPC_PIO_EN
, 0);
9337 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
9338 niu_pci_vpd_validate(np
);
9339 err
= niu_get_and_validate_port(np
);
9344 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
9345 err
= niu_get_and_validate_port(np
);
9348 err
= niu_pci_probe_sprom(np
);
9354 err
= niu_probe_ports(np
);
9360 niu_classifier_swstate_init(np
);
9361 niu_link_config_init(np
);
9363 err
= niu_determine_phy_disposition(np
);
9365 err
= niu_init_link(np
);
9370 static LIST_HEAD(niu_parent_list
);
9371 static DEFINE_MUTEX(niu_parent_lock
);
9372 static int niu_parent_index
;
9374 static ssize_t
show_port_phy(struct device
*dev
,
9375 struct device_attribute
*attr
, char *buf
)
9377 struct platform_device
*plat_dev
= to_platform_device(dev
);
9378 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9379 u32 port_phy
= p
->port_phy
;
9380 char *orig_buf
= buf
;
9383 if (port_phy
== PORT_PHY_UNKNOWN
||
9384 port_phy
== PORT_PHY_INVALID
)
9387 for (i
= 0; i
< p
->num_ports
; i
++) {
9388 const char *type_str
;
9391 type
= phy_decode(port_phy
, i
);
9392 if (type
== PORT_TYPE_10G
)
9397 (i
== 0) ? "%s" : " %s",
9400 buf
+= sprintf(buf
, "\n");
9401 return buf
- orig_buf
;
9404 static ssize_t
show_plat_type(struct device
*dev
,
9405 struct device_attribute
*attr
, char *buf
)
9407 struct platform_device
*plat_dev
= to_platform_device(dev
);
9408 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9409 const char *type_str
;
9411 switch (p
->plat_type
) {
9412 case PLAT_TYPE_ATLAS
:
9418 case PLAT_TYPE_VF_P0
:
9421 case PLAT_TYPE_VF_P1
:
9425 type_str
= "unknown";
9429 return sprintf(buf
, "%s\n", type_str
);
9432 static ssize_t
__show_chan_per_port(struct device
*dev
,
9433 struct device_attribute
*attr
, char *buf
,
9436 struct platform_device
*plat_dev
= to_platform_device(dev
);
9437 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9438 char *orig_buf
= buf
;
9442 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
9444 for (i
= 0; i
< p
->num_ports
; i
++) {
9446 (i
== 0) ? "%d" : " %d",
9449 buf
+= sprintf(buf
, "\n");
9451 return buf
- orig_buf
;
9454 static ssize_t
show_rxchan_per_port(struct device
*dev
,
9455 struct device_attribute
*attr
, char *buf
)
9457 return __show_chan_per_port(dev
, attr
, buf
, 1);
9460 static ssize_t
show_txchan_per_port(struct device
*dev
,
9461 struct device_attribute
*attr
, char *buf
)
9463 return __show_chan_per_port(dev
, attr
, buf
, 1);
9466 static ssize_t
show_num_ports(struct device
*dev
,
9467 struct device_attribute
*attr
, char *buf
)
9469 struct platform_device
*plat_dev
= to_platform_device(dev
);
9470 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9472 return sprintf(buf
, "%d\n", p
->num_ports
);
9475 static struct device_attribute niu_parent_attributes
[] = {
9476 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
9477 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
9478 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
9479 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
9480 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
9484 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
9485 union niu_parent_id
*id
,
9488 struct platform_device
*plat_dev
;
9489 struct niu_parent
*p
;
9492 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
9494 if (IS_ERR(plat_dev
))
9497 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
9498 int err
= device_create_file(&plat_dev
->dev
,
9499 &niu_parent_attributes
[i
]);
9501 goto fail_unregister
;
9504 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
9506 goto fail_unregister
;
9508 p
->index
= niu_parent_index
++;
9510 plat_dev
->dev
.platform_data
= p
;
9511 p
->plat_dev
= plat_dev
;
9513 memcpy(&p
->id
, id
, sizeof(*id
));
9514 p
->plat_type
= ptype
;
9515 INIT_LIST_HEAD(&p
->list
);
9516 atomic_set(&p
->refcnt
, 0);
9517 list_add(&p
->list
, &niu_parent_list
);
9518 spin_lock_init(&p
->lock
);
9520 p
->rxdma_clock_divider
= 7500;
9522 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
9523 if (p
->plat_type
== PLAT_TYPE_NIU
)
9524 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
9526 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
9527 int index
= i
- CLASS_CODE_USER_PROG1
;
9529 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
9530 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
9533 (FLOW_KEY_L4_BYTE12
<<
9534 FLOW_KEY_L4_0_SHIFT
) |
9535 (FLOW_KEY_L4_BYTE12
<<
9536 FLOW_KEY_L4_1_SHIFT
));
9539 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
9540 p
->ldg_map
[i
] = LDG_INVALID
;
9545 platform_device_unregister(plat_dev
);
9549 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
9550 union niu_parent_id
*id
,
9553 struct niu_parent
*p
, *tmp
;
9554 int port
= np
->port
;
9556 mutex_lock(&niu_parent_lock
);
9558 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
9559 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
9565 p
= niu_new_parent(np
, id
, ptype
);
9571 sprintf(port_name
, "port%d", port
);
9572 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
9576 p
->ports
[port
] = np
;
9577 atomic_inc(&p
->refcnt
);
9580 mutex_unlock(&niu_parent_lock
);
9585 static void niu_put_parent(struct niu
*np
)
9587 struct niu_parent
*p
= np
->parent
;
9591 BUG_ON(!p
|| p
->ports
[port
] != np
);
9593 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9594 "%s() port[%u]\n", __func__
, port
);
9596 sprintf(port_name
, "port%d", port
);
9598 mutex_lock(&niu_parent_lock
);
9600 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
9602 p
->ports
[port
] = NULL
;
9605 if (atomic_dec_and_test(&p
->refcnt
)) {
9607 platform_device_unregister(p
->plat_dev
);
9610 mutex_unlock(&niu_parent_lock
);
9613 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
9614 u64
*handle
, gfp_t flag
)
9619 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
9625 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
9626 void *cpu_addr
, u64 handle
)
9628 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
9631 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
9632 unsigned long offset
, size_t size
,
9633 enum dma_data_direction direction
)
9635 return dma_map_page(dev
, page
, offset
, size
, direction
);
9638 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
9639 size_t size
, enum dma_data_direction direction
)
9641 dma_unmap_page(dev
, dma_address
, size
, direction
);
9644 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
9646 enum dma_data_direction direction
)
9648 return dma_map_single(dev
, cpu_addr
, size
, direction
);
9651 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
9653 enum dma_data_direction direction
)
9655 dma_unmap_single(dev
, dma_address
, size
, direction
);
9658 static const struct niu_ops niu_pci_ops
= {
9659 .alloc_coherent
= niu_pci_alloc_coherent
,
9660 .free_coherent
= niu_pci_free_coherent
,
9661 .map_page
= niu_pci_map_page
,
9662 .unmap_page
= niu_pci_unmap_page
,
9663 .map_single
= niu_pci_map_single
,
9664 .unmap_single
= niu_pci_unmap_single
,
9667 static void __devinit
niu_driver_version(void)
9669 static int niu_version_printed
;
9671 if (niu_version_printed
++ == 0)
9672 pr_info("%s", version
);
9675 static struct net_device
* __devinit
niu_alloc_and_init(
9676 struct device
*gen_dev
, struct pci_dev
*pdev
,
9677 struct platform_device
*op
, const struct niu_ops
*ops
,
9680 struct net_device
*dev
;
9683 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
9685 dev_err(gen_dev
, "Etherdev alloc failed, aborting\n");
9689 SET_NETDEV_DEV(dev
, gen_dev
);
9691 np
= netdev_priv(dev
);
9695 np
->device
= gen_dev
;
9698 np
->msg_enable
= niu_debug
;
9700 spin_lock_init(&np
->lock
);
9701 INIT_WORK(&np
->reset_task
, niu_reset_task
);
9708 static const struct net_device_ops niu_netdev_ops
= {
9709 .ndo_open
= niu_open
,
9710 .ndo_stop
= niu_close
,
9711 .ndo_start_xmit
= niu_start_xmit
,
9712 .ndo_get_stats
= niu_get_stats
,
9713 .ndo_set_multicast_list
= niu_set_rx_mode
,
9714 .ndo_validate_addr
= eth_validate_addr
,
9715 .ndo_set_mac_address
= niu_set_mac_addr
,
9716 .ndo_do_ioctl
= niu_ioctl
,
9717 .ndo_tx_timeout
= niu_tx_timeout
,
9718 .ndo_change_mtu
= niu_change_mtu
,
9721 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
9723 dev
->netdev_ops
= &niu_netdev_ops
;
9724 dev
->ethtool_ops
= &niu_ethtool_ops
;
9725 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
9728 static void __devinit
niu_device_announce(struct niu
*np
)
9730 struct net_device
*dev
= np
->dev
;
9732 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
9734 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
9735 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9737 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9738 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9739 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
9740 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9741 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9744 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9746 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9747 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9748 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" :
9749 (np
->flags
& NIU_FLAGS_XCVR_SERDES
? "SERDES" :
9751 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9752 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9757 static void __devinit
niu_set_basic_features(struct net_device
*dev
)
9759 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
|
9760 NETIF_F_GRO
| NETIF_F_RXHASH
);
9763 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
9764 const struct pci_device_id
*ent
)
9766 union niu_parent_id parent_id
;
9767 struct net_device
*dev
;
9773 niu_driver_version();
9775 err
= pci_enable_device(pdev
);
9777 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
9781 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
9782 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
9783 dev_err(&pdev
->dev
, "Cannot find proper PCI device base addresses, aborting\n");
9785 goto err_out_disable_pdev
;
9788 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9790 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
9791 goto err_out_disable_pdev
;
9794 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
9796 dev_err(&pdev
->dev
, "Cannot find PCI Express capability, aborting\n");
9797 goto err_out_free_res
;
9800 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
9801 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
9804 goto err_out_free_res
;
9806 np
= netdev_priv(dev
);
9808 memset(&parent_id
, 0, sizeof(parent_id
));
9809 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
9810 parent_id
.pci
.bus
= pdev
->bus
->number
;
9811 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
9813 np
->parent
= niu_get_parent(np
, &parent_id
,
9817 goto err_out_free_dev
;
9820 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
9821 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
9822 val16
|= (PCI_EXP_DEVCTL_CERE
|
9823 PCI_EXP_DEVCTL_NFERE
|
9824 PCI_EXP_DEVCTL_FERE
|
9825 PCI_EXP_DEVCTL_URRE
|
9826 PCI_EXP_DEVCTL_RELAX_EN
);
9827 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
9829 dma_mask
= DMA_BIT_MASK(44);
9830 err
= pci_set_dma_mask(pdev
, dma_mask
);
9832 dev
->features
|= NETIF_F_HIGHDMA
;
9833 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
9835 dev_err(&pdev
->dev
, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9836 goto err_out_release_parent
;
9839 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
9840 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
9842 dev_err(&pdev
->dev
, "No usable DMA configuration, aborting\n");
9843 goto err_out_release_parent
;
9847 niu_set_basic_features(dev
);
9849 np
->regs
= pci_ioremap_bar(pdev
, 0);
9851 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
9853 goto err_out_release_parent
;
9856 pci_set_master(pdev
);
9857 pci_save_state(pdev
);
9859 dev
->irq
= pdev
->irq
;
9861 niu_assign_netdev_ops(dev
);
9863 err
= niu_get_invariants(np
);
9866 dev_err(&pdev
->dev
, "Problem fetching invariants of chip, aborting\n");
9867 goto err_out_iounmap
;
9870 err
= register_netdev(dev
);
9872 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
9873 goto err_out_iounmap
;
9876 pci_set_drvdata(pdev
, dev
);
9878 niu_device_announce(np
);
9888 err_out_release_parent
:
9895 pci_release_regions(pdev
);
9897 err_out_disable_pdev
:
9898 pci_disable_device(pdev
);
9899 pci_set_drvdata(pdev
, NULL
);
9904 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
9906 struct net_device
*dev
= pci_get_drvdata(pdev
);
9909 struct niu
*np
= netdev_priv(dev
);
9911 unregister_netdev(dev
);
9922 pci_release_regions(pdev
);
9923 pci_disable_device(pdev
);
9924 pci_set_drvdata(pdev
, NULL
);
9928 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
9930 struct net_device
*dev
= pci_get_drvdata(pdev
);
9931 struct niu
*np
= netdev_priv(dev
);
9932 unsigned long flags
;
9934 if (!netif_running(dev
))
9937 flush_scheduled_work();
9940 del_timer_sync(&np
->timer
);
9942 spin_lock_irqsave(&np
->lock
, flags
);
9943 niu_enable_interrupts(np
, 0);
9944 spin_unlock_irqrestore(&np
->lock
, flags
);
9946 netif_device_detach(dev
);
9948 spin_lock_irqsave(&np
->lock
, flags
);
9950 spin_unlock_irqrestore(&np
->lock
, flags
);
9952 pci_save_state(pdev
);
9957 static int niu_resume(struct pci_dev
*pdev
)
9959 struct net_device
*dev
= pci_get_drvdata(pdev
);
9960 struct niu
*np
= netdev_priv(dev
);
9961 unsigned long flags
;
9964 if (!netif_running(dev
))
9967 pci_restore_state(pdev
);
9969 netif_device_attach(dev
);
9971 spin_lock_irqsave(&np
->lock
, flags
);
9973 err
= niu_init_hw(np
);
9975 np
->timer
.expires
= jiffies
+ HZ
;
9976 add_timer(&np
->timer
);
9977 niu_netif_start(np
);
9980 spin_unlock_irqrestore(&np
->lock
, flags
);
9985 static struct pci_driver niu_pci_driver
= {
9986 .name
= DRV_MODULE_NAME
,
9987 .id_table
= niu_pci_tbl
,
9988 .probe
= niu_pci_init_one
,
9989 .remove
= __devexit_p(niu_pci_remove_one
),
9990 .suspend
= niu_suspend
,
9991 .resume
= niu_resume
,
9994 #ifdef CONFIG_SPARC64
9995 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
9996 u64
*dma_addr
, gfp_t flag
)
9998 unsigned long order
= get_order(size
);
9999 unsigned long page
= __get_free_pages(flag
, order
);
10003 memset((char *)page
, 0, PAGE_SIZE
<< order
);
10004 *dma_addr
= __pa(page
);
10006 return (void *) page
;
10009 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
10010 void *cpu_addr
, u64 handle
)
10012 unsigned long order
= get_order(size
);
10014 free_pages((unsigned long) cpu_addr
, order
);
10017 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
10018 unsigned long offset
, size_t size
,
10019 enum dma_data_direction direction
)
10021 return page_to_phys(page
) + offset
;
10024 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
10025 size_t size
, enum dma_data_direction direction
)
10027 /* Nothing to do. */
10030 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
10032 enum dma_data_direction direction
)
10034 return __pa(cpu_addr
);
10037 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
10039 enum dma_data_direction direction
)
10041 /* Nothing to do. */
10044 static const struct niu_ops niu_phys_ops
= {
10045 .alloc_coherent
= niu_phys_alloc_coherent
,
10046 .free_coherent
= niu_phys_free_coherent
,
10047 .map_page
= niu_phys_map_page
,
10048 .unmap_page
= niu_phys_unmap_page
,
10049 .map_single
= niu_phys_map_single
,
10050 .unmap_single
= niu_phys_unmap_single
,
10053 static int __devinit
niu_of_probe(struct platform_device
*op
,
10054 const struct of_device_id
*match
)
10056 union niu_parent_id parent_id
;
10057 struct net_device
*dev
;
10062 niu_driver_version();
10064 reg
= of_get_property(op
->dev
.of_node
, "reg", NULL
);
10066 dev_err(&op
->dev
, "%s: No 'reg' property, aborting\n",
10067 op
->dev
.of_node
->full_name
);
10071 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
10072 &niu_phys_ops
, reg
[0] & 0x1);
10077 np
= netdev_priv(dev
);
10079 memset(&parent_id
, 0, sizeof(parent_id
));
10080 parent_id
.of
= of_get_parent(op
->dev
.of_node
);
10082 np
->parent
= niu_get_parent(np
, &parent_id
,
10086 goto err_out_free_dev
;
10089 niu_set_basic_features(dev
);
10091 np
->regs
= of_ioremap(&op
->resource
[1], 0,
10092 resource_size(&op
->resource
[1]),
10095 dev_err(&op
->dev
, "Cannot map device registers, aborting\n");
10097 goto err_out_release_parent
;
10100 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
10101 resource_size(&op
->resource
[2]),
10103 if (!np
->vir_regs_1
) {
10104 dev_err(&op
->dev
, "Cannot map device vir registers 1, aborting\n");
10106 goto err_out_iounmap
;
10109 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
10110 resource_size(&op
->resource
[3]),
10112 if (!np
->vir_regs_2
) {
10113 dev_err(&op
->dev
, "Cannot map device vir registers 2, aborting\n");
10115 goto err_out_iounmap
;
10118 niu_assign_netdev_ops(dev
);
10120 err
= niu_get_invariants(np
);
10122 if (err
!= -ENODEV
)
10123 dev_err(&op
->dev
, "Problem fetching invariants of chip, aborting\n");
10124 goto err_out_iounmap
;
10127 err
= register_netdev(dev
);
10129 dev_err(&op
->dev
, "Cannot register net device, aborting\n");
10130 goto err_out_iounmap
;
10133 dev_set_drvdata(&op
->dev
, dev
);
10135 niu_device_announce(np
);
10140 if (np
->vir_regs_1
) {
10141 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10142 resource_size(&op
->resource
[2]));
10143 np
->vir_regs_1
= NULL
;
10146 if (np
->vir_regs_2
) {
10147 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10148 resource_size(&op
->resource
[3]));
10149 np
->vir_regs_2
= NULL
;
10153 of_iounmap(&op
->resource
[1], np
->regs
,
10154 resource_size(&op
->resource
[1]));
10158 err_out_release_parent
:
10159 niu_put_parent(np
);
10168 static int __devexit
niu_of_remove(struct platform_device
*op
)
10170 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
10173 struct niu
*np
= netdev_priv(dev
);
10175 unregister_netdev(dev
);
10177 if (np
->vir_regs_1
) {
10178 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10179 resource_size(&op
->resource
[2]));
10180 np
->vir_regs_1
= NULL
;
10183 if (np
->vir_regs_2
) {
10184 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10185 resource_size(&op
->resource
[3]));
10186 np
->vir_regs_2
= NULL
;
10190 of_iounmap(&op
->resource
[1], np
->regs
,
10191 resource_size(&op
->resource
[1]));
10197 niu_put_parent(np
);
10200 dev_set_drvdata(&op
->dev
, NULL
);
10205 static const struct of_device_id niu_match
[] = {
10208 .compatible
= "SUNW,niusl",
10212 MODULE_DEVICE_TABLE(of
, niu_match
);
10214 static struct of_platform_driver niu_of_driver
= {
10217 .owner
= THIS_MODULE
,
10218 .of_match_table
= niu_match
,
10220 .probe
= niu_of_probe
,
10221 .remove
= __devexit_p(niu_of_remove
),
10224 #endif /* CONFIG_SPARC64 */
10226 static int __init
niu_init(void)
10230 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
10232 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
10234 #ifdef CONFIG_SPARC64
10235 err
= of_register_platform_driver(&niu_of_driver
);
10239 err
= pci_register_driver(&niu_pci_driver
);
10240 #ifdef CONFIG_SPARC64
10242 of_unregister_platform_driver(&niu_of_driver
);
10249 static void __exit
niu_exit(void)
10251 pci_unregister_driver(&niu_pci_driver
);
10252 #ifdef CONFIG_SPARC64
10253 of_unregister_platform_driver(&niu_of_driver
);
10257 module_init(niu_init
);
10258 module_exit(niu_exit
);