1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 #include <linux/module.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/netdevice.h>
13 #include <linux/ethtool.h>
14 #include <linux/etherdevice.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/bitops.h>
18 #include <linux/mii.h>
19 #include <linux/if_ether.h>
20 #include <linux/if_vlan.h>
23 #include <linux/ipv6.h>
24 #include <linux/log2.h>
25 #include <linux/jiffies.h>
26 #include <linux/crc32.h>
27 #include <linux/list.h>
28 #include <linux/slab.h>
33 #include <linux/of_device.h>
38 #define DRV_MODULE_NAME "niu"
39 #define DRV_MODULE_VERSION "1.1"
40 #define DRV_MODULE_RELDATE "Apr 22, 2010"
42 static char version
[] __devinitdata
=
43 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
45 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
46 MODULE_DESCRIPTION("NIU ethernet driver");
47 MODULE_LICENSE("GPL");
48 MODULE_VERSION(DRV_MODULE_VERSION
);
51 static u64
readq(void __iomem
*reg
)
53 return ((u64
) readl(reg
)) | (((u64
) readl(reg
+ 4UL)) << 32);
56 static void writeq(u64 val
, void __iomem
*reg
)
58 writel(val
& 0xffffffff, reg
);
59 writel(val
>> 32, reg
+ 0x4UL
);
63 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl
) = {
64 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
68 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
70 #define NIU_TX_TIMEOUT (5 * HZ)
72 #define nr64(reg) readq(np->regs + (reg))
73 #define nw64(reg, val) writeq((val), np->regs + (reg))
75 #define nr64_mac(reg) readq(np->mac_regs + (reg))
76 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
78 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
79 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
81 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
82 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
84 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
85 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
87 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
90 static int debug
= -1;
91 module_param(debug
, int, 0);
92 MODULE_PARM_DESC(debug
, "NIU debug level");
94 #define niu_lock_parent(np, flags) \
95 spin_lock_irqsave(&np->parent->lock, flags)
96 #define niu_unlock_parent(np, flags) \
97 spin_unlock_irqrestore(&np->parent->lock, flags)
99 static int serdes_init_10g_serdes(struct niu
*np
);
101 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
102 u64 bits
, int limit
, int delay
)
104 while (--limit
>= 0) {
105 u64 val
= nr64_mac(reg
);
116 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
117 u64 bits
, int limit
, int delay
,
118 const char *reg_name
)
123 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
125 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
126 (unsigned long long)bits
, reg_name
,
127 (unsigned long long)nr64_mac(reg
));
131 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
132 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
133 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
136 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
137 u64 bits
, int limit
, int delay
)
139 while (--limit
>= 0) {
140 u64 val
= nr64_ipp(reg
);
151 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
152 u64 bits
, int limit
, int delay
,
153 const char *reg_name
)
162 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
164 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
165 (unsigned long long)bits
, reg_name
,
166 (unsigned long long)nr64_ipp(reg
));
170 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
171 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
172 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
175 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
176 u64 bits
, int limit
, int delay
)
178 while (--limit
>= 0) {
190 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
191 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
192 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
195 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
196 u64 bits
, int limit
, int delay
,
197 const char *reg_name
)
202 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
204 netdev_err(np
->dev
, "bits (%llx) of register %s would not clear, val[%llx]\n",
205 (unsigned long long)bits
, reg_name
,
206 (unsigned long long)nr64(reg
));
210 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
211 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
212 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
215 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
217 u64 val
= (u64
) lp
->timer
;
220 val
|= LDG_IMGMT_ARM
;
222 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
225 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
227 unsigned long mask_reg
, bits
;
230 if (ldn
< 0 || ldn
> LDN_MAX
)
234 mask_reg
= LD_IM0(ldn
);
237 mask_reg
= LD_IM1(ldn
- 64);
241 val
= nr64(mask_reg
);
251 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
253 struct niu_parent
*parent
= np
->parent
;
256 for (i
= 0; i
<= LDN_MAX
; i
++) {
259 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
262 err
= niu_ldn_irq_enable(np
, i
, on
);
269 static int niu_enable_interrupts(struct niu
*np
, int on
)
273 for (i
= 0; i
< np
->num_ldg
; i
++) {
274 struct niu_ldg
*lp
= &np
->ldg
[i
];
277 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
281 for (i
= 0; i
< np
->num_ldg
; i
++)
282 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
287 static u32
phy_encode(u32 type
, int port
)
289 return (type
<< (port
* 2));
292 static u32
phy_decode(u32 val
, int port
)
294 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
297 static int mdio_wait(struct niu
*np
)
302 while (--limit
> 0) {
303 val
= nr64(MIF_FRAME_OUTPUT
);
304 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
305 return val
& MIF_FRAME_OUTPUT_DATA
;
313 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
317 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
322 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
323 return mdio_wait(np
);
326 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
330 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
335 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
343 static int mii_read(struct niu
*np
, int port
, int reg
)
345 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
346 return mdio_wait(np
);
349 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
353 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
361 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
365 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
366 ESR2_TI_PLL_TX_CFG_L(channel
),
369 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
370 ESR2_TI_PLL_TX_CFG_H(channel
),
375 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
379 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
380 ESR2_TI_PLL_RX_CFG_L(channel
),
383 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
384 ESR2_TI_PLL_RX_CFG_H(channel
),
389 /* Mode is always 10G fiber. */
390 static int serdes_init_niu_10g_fiber(struct niu
*np
)
392 struct niu_link_config
*lp
= &np
->link_config
;
396 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
397 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
398 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
399 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
401 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
402 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
404 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
405 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
407 tx_cfg
|= PLL_TX_CFG_ENTEST
;
408 rx_cfg
|= PLL_RX_CFG_ENTEST
;
411 /* Initialize all 4 lanes of the SERDES. */
412 for (i
= 0; i
< 4; i
++) {
413 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
418 for (i
= 0; i
< 4; i
++) {
419 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
427 static int serdes_init_niu_1g_serdes(struct niu
*np
)
429 struct niu_link_config
*lp
= &np
->link_config
;
430 u16 pll_cfg
, pll_sts
;
432 u64
uninitialized_var(sig
), mask
, val
;
437 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
|
438 PLL_TX_CFG_RATE_HALF
);
439 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
440 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
441 PLL_RX_CFG_RATE_HALF
);
444 rx_cfg
|= PLL_RX_CFG_EQ_LP_ADAPTIVE
;
446 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
447 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
449 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
450 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
452 tx_cfg
|= PLL_TX_CFG_ENTEST
;
453 rx_cfg
|= PLL_RX_CFG_ENTEST
;
456 /* Initialize PLL for 1G */
457 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_8X
);
459 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
460 ESR2_TI_PLL_CFG_L
, pll_cfg
);
462 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
467 pll_sts
= PLL_CFG_ENPLL
;
469 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
470 ESR2_TI_PLL_STS_L
, pll_sts
);
472 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
479 /* Initialize all 4 lanes of the SERDES. */
480 for (i
= 0; i
< 4; i
++) {
481 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
486 for (i
= 0; i
< 4; i
++) {
487 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
494 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
499 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
507 while (max_retry
--) {
508 sig
= nr64(ESR_INT_SIGNALS
);
509 if ((sig
& mask
) == val
)
515 if ((sig
& mask
) != val
) {
516 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
517 np
->port
, (int)(sig
& mask
), (int)val
);
524 static int serdes_init_niu_10g_serdes(struct niu
*np
)
526 struct niu_link_config
*lp
= &np
->link_config
;
527 u32 tx_cfg
, rx_cfg
, pll_cfg
, pll_sts
;
529 u64
uninitialized_var(sig
), mask
, val
;
533 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
534 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
535 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
536 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
538 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
539 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
541 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
542 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
544 tx_cfg
|= PLL_TX_CFG_ENTEST
;
545 rx_cfg
|= PLL_RX_CFG_ENTEST
;
548 /* Initialize PLL for 10G */
549 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_10X
);
551 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
552 ESR2_TI_PLL_CFG_L
, pll_cfg
& 0xffff);
554 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n",
559 pll_sts
= PLL_CFG_ENPLL
;
561 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
562 ESR2_TI_PLL_STS_L
, pll_sts
& 0xffff);
564 netdev_err(np
->dev
, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n",
571 /* Initialize all 4 lanes of the SERDES. */
572 for (i
= 0; i
< 4; i
++) {
573 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
578 for (i
= 0; i
< 4; i
++) {
579 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
584 /* check if serdes is ready */
588 mask
= ESR_INT_SIGNALS_P0_BITS
;
589 val
= (ESR_INT_SRDY0_P0
|
599 mask
= ESR_INT_SIGNALS_P1_BITS
;
600 val
= (ESR_INT_SRDY0_P1
|
613 while (max_retry
--) {
614 sig
= nr64(ESR_INT_SIGNALS
);
615 if ((sig
& mask
) == val
)
621 if ((sig
& mask
) != val
) {
622 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n",
623 np
->port
, (int)(sig
& mask
), (int)val
);
625 /* 10G failed, try initializing at 1G */
626 err
= serdes_init_niu_1g_serdes(np
);
628 np
->flags
&= ~NIU_FLAGS_10G
;
629 np
->mac_xcvr
= MAC_XCVR_PCS
;
631 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
639 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
643 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
645 *val
= (err
& 0xffff);
646 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
647 ESR_RXTX_CTRL_H(chan
));
649 *val
|= ((err
& 0xffff) << 16);
655 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
659 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
660 ESR_GLUE_CTRL0_L(chan
));
662 *val
= (err
& 0xffff);
663 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
664 ESR_GLUE_CTRL0_H(chan
));
666 *val
|= ((err
& 0xffff) << 16);
673 static int esr_read_reset(struct niu
*np
, u32
*val
)
677 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
678 ESR_RXTX_RESET_CTRL_L
);
680 *val
= (err
& 0xffff);
681 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
682 ESR_RXTX_RESET_CTRL_H
);
684 *val
|= ((err
& 0xffff) << 16);
691 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
695 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
696 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
698 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
699 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
703 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
707 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
708 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
710 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
711 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
715 static int esr_reset(struct niu
*np
)
717 u32
uninitialized_var(reset
);
720 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
721 ESR_RXTX_RESET_CTRL_L
, 0x0000);
724 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
725 ESR_RXTX_RESET_CTRL_H
, 0xffff);
730 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
731 ESR_RXTX_RESET_CTRL_L
, 0xffff);
736 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
737 ESR_RXTX_RESET_CTRL_H
, 0x0000);
742 err
= esr_read_reset(np
, &reset
);
746 netdev_err(np
->dev
, "Port %u ESR_RESET did not clear [%08x]\n",
754 static int serdes_init_10g(struct niu
*np
)
756 struct niu_link_config
*lp
= &np
->link_config
;
757 unsigned long ctrl_reg
, test_cfg_reg
, i
;
758 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
763 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
764 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
767 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
768 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
774 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
775 ENET_SERDES_CTRL_SDET_1
|
776 ENET_SERDES_CTRL_SDET_2
|
777 ENET_SERDES_CTRL_SDET_3
|
778 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
779 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
780 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
781 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
782 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
783 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
784 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
785 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
788 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
789 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
790 ENET_SERDES_TEST_MD_0_SHIFT
) |
791 (ENET_TEST_MD_PAD_LOOPBACK
<<
792 ENET_SERDES_TEST_MD_1_SHIFT
) |
793 (ENET_TEST_MD_PAD_LOOPBACK
<<
794 ENET_SERDES_TEST_MD_2_SHIFT
) |
795 (ENET_TEST_MD_PAD_LOOPBACK
<<
796 ENET_SERDES_TEST_MD_3_SHIFT
));
799 nw64(ctrl_reg
, ctrl_val
);
800 nw64(test_cfg_reg
, test_cfg_val
);
802 /* Initialize all 4 lanes of the SERDES. */
803 for (i
= 0; i
< 4; i
++) {
804 u32 rxtx_ctrl
, glue0
;
806 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
809 err
= esr_read_glue0(np
, i
, &glue0
);
813 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
814 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
815 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
817 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
818 ESR_GLUE_CTRL0_THCNT
|
819 ESR_GLUE_CTRL0_BLTIME
);
820 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
821 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
822 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
823 (BLTIME_300_CYCLES
<<
824 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
826 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
829 err
= esr_write_glue0(np
, i
, glue0
);
838 sig
= nr64(ESR_INT_SIGNALS
);
841 mask
= ESR_INT_SIGNALS_P0_BITS
;
842 val
= (ESR_INT_SRDY0_P0
|
852 mask
= ESR_INT_SIGNALS_P1_BITS
;
853 val
= (ESR_INT_SRDY0_P1
|
866 if ((sig
& mask
) != val
) {
867 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
868 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
871 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
872 np
->port
, (int)(sig
& mask
), (int)val
);
875 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
876 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
880 static int serdes_init_1g(struct niu
*np
)
884 val
= nr64(ENET_SERDES_1_PLL_CFG
);
885 val
&= ~ENET_SERDES_PLL_FBDIV2
;
888 val
|= ENET_SERDES_PLL_HRATE0
;
891 val
|= ENET_SERDES_PLL_HRATE1
;
894 val
|= ENET_SERDES_PLL_HRATE2
;
897 val
|= ENET_SERDES_PLL_HRATE3
;
902 nw64(ENET_SERDES_1_PLL_CFG
, val
);
907 static int serdes_init_1g_serdes(struct niu
*np
)
909 struct niu_link_config
*lp
= &np
->link_config
;
910 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
911 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
913 u64 reset_val
, val_rd
;
915 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
916 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
917 ENET_SERDES_PLL_FBDIV0
;
920 reset_val
= ENET_SERDES_RESET_0
;
921 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
922 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
923 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
926 reset_val
= ENET_SERDES_RESET_1
;
927 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
928 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
929 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
935 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
936 ENET_SERDES_CTRL_SDET_1
|
937 ENET_SERDES_CTRL_SDET_2
|
938 ENET_SERDES_CTRL_SDET_3
|
939 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
940 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
941 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
942 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
943 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
944 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
945 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
946 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
949 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
950 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
951 ENET_SERDES_TEST_MD_0_SHIFT
) |
952 (ENET_TEST_MD_PAD_LOOPBACK
<<
953 ENET_SERDES_TEST_MD_1_SHIFT
) |
954 (ENET_TEST_MD_PAD_LOOPBACK
<<
955 ENET_SERDES_TEST_MD_2_SHIFT
) |
956 (ENET_TEST_MD_PAD_LOOPBACK
<<
957 ENET_SERDES_TEST_MD_3_SHIFT
));
960 nw64(ENET_SERDES_RESET
, reset_val
);
962 val_rd
= nr64(ENET_SERDES_RESET
);
963 val_rd
&= ~reset_val
;
965 nw64(ctrl_reg
, ctrl_val
);
966 nw64(test_cfg_reg
, test_cfg_val
);
967 nw64(ENET_SERDES_RESET
, val_rd
);
970 /* Initialize all 4 lanes of the SERDES. */
971 for (i
= 0; i
< 4; i
++) {
972 u32 rxtx_ctrl
, glue0
;
974 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
977 err
= esr_read_glue0(np
, i
, &glue0
);
981 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
982 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
983 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
985 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
986 ESR_GLUE_CTRL0_THCNT
|
987 ESR_GLUE_CTRL0_BLTIME
);
988 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
989 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
990 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
991 (BLTIME_300_CYCLES
<<
992 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
994 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
997 err
= esr_write_glue0(np
, i
, glue0
);
1003 sig
= nr64(ESR_INT_SIGNALS
);
1006 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
1011 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
1019 if ((sig
& mask
) != val
) {
1020 netdev_err(np
->dev
, "Port %u signal bits [%08x] are not [%08x]\n",
1021 np
->port
, (int)(sig
& mask
), (int)val
);
1028 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
1030 struct niu_link_config
*lp
= &np
->link_config
;
1034 unsigned long flags
;
1038 current_speed
= SPEED_INVALID
;
1039 current_duplex
= DUPLEX_INVALID
;
1041 spin_lock_irqsave(&np
->lock
, flags
);
1043 val
= nr64_pcs(PCS_MII_STAT
);
1045 if (val
& PCS_MII_STAT_LINK_STATUS
) {
1047 current_speed
= SPEED_1000
;
1048 current_duplex
= DUPLEX_FULL
;
1051 lp
->active_speed
= current_speed
;
1052 lp
->active_duplex
= current_duplex
;
1053 spin_unlock_irqrestore(&np
->lock
, flags
);
1055 *link_up_p
= link_up
;
1059 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
1061 unsigned long flags
;
1062 struct niu_link_config
*lp
= &np
->link_config
;
1069 if (!(np
->flags
& NIU_FLAGS_10G
))
1070 return link_status_1g_serdes(np
, link_up_p
);
1072 current_speed
= SPEED_INVALID
;
1073 current_duplex
= DUPLEX_INVALID
;
1074 spin_lock_irqsave(&np
->lock
, flags
);
1076 val
= nr64_xpcs(XPCS_STATUS(0));
1077 val2
= nr64_mac(XMAC_INTER2
);
1078 if (val2
& 0x01000000)
1081 if ((val
& 0x1000ULL
) && link_ok
) {
1083 current_speed
= SPEED_10000
;
1084 current_duplex
= DUPLEX_FULL
;
1086 lp
->active_speed
= current_speed
;
1087 lp
->active_duplex
= current_duplex
;
1088 spin_unlock_irqrestore(&np
->lock
, flags
);
1089 *link_up_p
= link_up
;
1093 static int link_status_mii(struct niu
*np
, int *link_up_p
)
1095 struct niu_link_config
*lp
= &np
->link_config
;
1097 int bmsr
, advert
, ctrl1000
, stat1000
, lpa
, bmcr
, estatus
;
1098 int supported
, advertising
, active_speed
, active_duplex
;
1100 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1101 if (unlikely(err
< 0))
1105 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1106 if (unlikely(err
< 0))
1110 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1111 if (unlikely(err
< 0))
1115 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1116 if (unlikely(err
< 0))
1120 if (likely(bmsr
& BMSR_ESTATEN
)) {
1121 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1122 if (unlikely(err
< 0))
1126 err
= mii_read(np
, np
->phy_addr
, MII_CTRL1000
);
1127 if (unlikely(err
< 0))
1131 err
= mii_read(np
, np
->phy_addr
, MII_STAT1000
);
1132 if (unlikely(err
< 0))
1136 estatus
= ctrl1000
= stat1000
= 0;
1139 if (bmsr
& BMSR_ANEGCAPABLE
)
1140 supported
|= SUPPORTED_Autoneg
;
1141 if (bmsr
& BMSR_10HALF
)
1142 supported
|= SUPPORTED_10baseT_Half
;
1143 if (bmsr
& BMSR_10FULL
)
1144 supported
|= SUPPORTED_10baseT_Full
;
1145 if (bmsr
& BMSR_100HALF
)
1146 supported
|= SUPPORTED_100baseT_Half
;
1147 if (bmsr
& BMSR_100FULL
)
1148 supported
|= SUPPORTED_100baseT_Full
;
1149 if (estatus
& ESTATUS_1000_THALF
)
1150 supported
|= SUPPORTED_1000baseT_Half
;
1151 if (estatus
& ESTATUS_1000_TFULL
)
1152 supported
|= SUPPORTED_1000baseT_Full
;
1153 lp
->supported
= supported
;
1156 if (advert
& ADVERTISE_10HALF
)
1157 advertising
|= ADVERTISED_10baseT_Half
;
1158 if (advert
& ADVERTISE_10FULL
)
1159 advertising
|= ADVERTISED_10baseT_Full
;
1160 if (advert
& ADVERTISE_100HALF
)
1161 advertising
|= ADVERTISED_100baseT_Half
;
1162 if (advert
& ADVERTISE_100FULL
)
1163 advertising
|= ADVERTISED_100baseT_Full
;
1164 if (ctrl1000
& ADVERTISE_1000HALF
)
1165 advertising
|= ADVERTISED_1000baseT_Half
;
1166 if (ctrl1000
& ADVERTISE_1000FULL
)
1167 advertising
|= ADVERTISED_1000baseT_Full
;
1169 if (bmcr
& BMCR_ANENABLE
) {
1172 lp
->active_autoneg
= 1;
1173 advertising
|= ADVERTISED_Autoneg
;
1176 neg1000
= (ctrl1000
<< 2) & stat1000
;
1178 if (neg1000
& (LPA_1000FULL
| LPA_1000HALF
))
1179 active_speed
= SPEED_1000
;
1180 else if (neg
& LPA_100
)
1181 active_speed
= SPEED_100
;
1182 else if (neg
& (LPA_10HALF
| LPA_10FULL
))
1183 active_speed
= SPEED_10
;
1185 active_speed
= SPEED_INVALID
;
1187 if ((neg1000
& LPA_1000FULL
) || (neg
& LPA_DUPLEX
))
1188 active_duplex
= DUPLEX_FULL
;
1189 else if (active_speed
!= SPEED_INVALID
)
1190 active_duplex
= DUPLEX_HALF
;
1192 active_duplex
= DUPLEX_INVALID
;
1194 lp
->active_autoneg
= 0;
1196 if ((bmcr
& BMCR_SPEED1000
) && !(bmcr
& BMCR_SPEED100
))
1197 active_speed
= SPEED_1000
;
1198 else if (bmcr
& BMCR_SPEED100
)
1199 active_speed
= SPEED_100
;
1201 active_speed
= SPEED_10
;
1203 if (bmcr
& BMCR_FULLDPLX
)
1204 active_duplex
= DUPLEX_FULL
;
1206 active_duplex
= DUPLEX_HALF
;
1209 lp
->active_advertising
= advertising
;
1210 lp
->active_speed
= active_speed
;
1211 lp
->active_duplex
= active_duplex
;
1212 *link_up_p
= !!(bmsr
& BMSR_LSTATUS
);
1217 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
1219 struct niu_link_config
*lp
= &np
->link_config
;
1220 u16 current_speed
, bmsr
;
1221 unsigned long flags
;
1226 current_speed
= SPEED_INVALID
;
1227 current_duplex
= DUPLEX_INVALID
;
1229 spin_lock_irqsave(&np
->lock
, flags
);
1233 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1238 if (bmsr
& BMSR_LSTATUS
) {
1239 u16 adv
, lpa
, common
, estat
;
1241 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1246 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1253 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1258 current_speed
= SPEED_1000
;
1259 current_duplex
= DUPLEX_FULL
;
1262 lp
->active_speed
= current_speed
;
1263 lp
->active_duplex
= current_duplex
;
1267 spin_unlock_irqrestore(&np
->lock
, flags
);
1269 *link_up_p
= link_up
;
1273 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1275 struct niu_link_config
*lp
= &np
->link_config
;
1276 unsigned long flags
;
1279 spin_lock_irqsave(&np
->lock
, flags
);
1281 err
= link_status_mii(np
, link_up_p
);
1282 lp
->supported
|= SUPPORTED_TP
;
1283 lp
->active_advertising
|= ADVERTISED_TP
;
1285 spin_unlock_irqrestore(&np
->lock
, flags
);
1289 static int bcm8704_reset(struct niu
*np
)
1293 err
= mdio_read(np
, np
->phy_addr
,
1294 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1295 if (err
< 0 || err
== 0xffff)
1298 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1304 while (--limit
>= 0) {
1305 err
= mdio_read(np
, np
->phy_addr
,
1306 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1309 if (!(err
& BMCR_RESET
))
1313 netdev_err(np
->dev
, "Port %u PHY will not reset (bmcr=%04x)\n",
1314 np
->port
, (err
& 0xffff));
1320 /* When written, certain PHY registers need to be read back twice
1321 * in order for the bits to settle properly.
1323 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
1325 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1328 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1334 static int bcm8706_init_user_dev3(struct niu
*np
)
1339 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1340 BCM8704_USER_OPT_DIGITAL_CTRL
);
1343 err
&= ~USER_ODIG_CTRL_GPIOS
;
1344 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1345 err
|= USER_ODIG_CTRL_RESV2
;
1346 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1347 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1356 static int bcm8704_init_user_dev3(struct niu
*np
)
1360 err
= mdio_write(np
, np
->phy_addr
,
1361 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1362 (USER_CONTROL_OPTXRST_LVL
|
1363 USER_CONTROL_OPBIASFLT_LVL
|
1364 USER_CONTROL_OBTMPFLT_LVL
|
1365 USER_CONTROL_OPPRFLT_LVL
|
1366 USER_CONTROL_OPTXFLT_LVL
|
1367 USER_CONTROL_OPRXLOS_LVL
|
1368 USER_CONTROL_OPRXFLT_LVL
|
1369 USER_CONTROL_OPTXON_LVL
|
1370 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1374 err
= mdio_write(np
, np
->phy_addr
,
1375 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1376 (USER_PMD_TX_CTL_XFP_CLKEN
|
1377 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1378 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1379 USER_PMD_TX_CTL_TSCK_LPWREN
));
1383 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1386 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1390 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1391 BCM8704_USER_OPT_DIGITAL_CTRL
);
1394 err
&= ~USER_ODIG_CTRL_GPIOS
;
1395 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1396 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1397 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1406 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1410 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1411 MRVL88X2011_LED_8_TO_11_CTL
);
1415 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1416 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1418 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1419 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1422 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1426 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1427 MRVL88X2011_LED_BLINK_CTL
);
1429 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1432 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1433 MRVL88X2011_LED_BLINK_CTL
, err
);
1439 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1443 /* Set LED functions */
1444 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1449 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1453 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1454 MRVL88X2011_GENERAL_CTL
);
1458 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1460 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1461 MRVL88X2011_GENERAL_CTL
, err
);
1465 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1466 MRVL88X2011_PMA_PMD_CTL_1
);
1470 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1471 err
|= MRVL88X2011_LOOPBACK
;
1473 err
&= ~MRVL88X2011_LOOPBACK
;
1475 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1476 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1481 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1482 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1486 static int xcvr_diag_bcm870x(struct niu
*np
)
1488 u16 analog_stat0
, tx_alarm_status
;
1492 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1496 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np
->port
, err
);
1498 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1501 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np
->port
, err
);
1503 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1507 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np
->port
, err
);
1510 /* XXX dig this out it might not be so useful XXX */
1511 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1512 BCM8704_USER_ANALOG_STATUS0
);
1515 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1516 BCM8704_USER_ANALOG_STATUS0
);
1521 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1522 BCM8704_USER_TX_ALARM_STATUS
);
1525 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1526 BCM8704_USER_TX_ALARM_STATUS
);
1529 tx_alarm_status
= err
;
1531 if (analog_stat0
!= 0x03fc) {
1532 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1533 pr_info("Port %u cable not connected or bad cable\n",
1535 } else if (analog_stat0
== 0x639c) {
1536 pr_info("Port %u optical module is bad or missing\n",
1544 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1546 struct niu_link_config
*lp
= &np
->link_config
;
1549 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1554 err
&= ~BMCR_LOOPBACK
;
1556 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1557 err
|= BMCR_LOOPBACK
;
1559 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1567 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1572 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1573 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1576 val
= nr64_mac(XMAC_CONFIG
);
1577 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1578 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1579 nw64_mac(XMAC_CONFIG
, val
);
1581 val
= nr64(MIF_CONFIG
);
1582 val
|= MIF_CONFIG_INDIRECT_MODE
;
1583 nw64(MIF_CONFIG
, val
);
1585 err
= bcm8704_reset(np
);
1589 err
= xcvr_10g_set_lb_bcm870x(np
);
1593 err
= bcm8706_init_user_dev3(np
);
1597 err
= xcvr_diag_bcm870x(np
);
1604 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1608 err
= bcm8704_reset(np
);
1612 err
= bcm8704_init_user_dev3(np
);
1616 err
= xcvr_10g_set_lb_bcm870x(np
);
1620 err
= xcvr_diag_bcm870x(np
);
1627 static int xcvr_init_10g(struct niu
*np
)
1632 val
= nr64_mac(XMAC_CONFIG
);
1633 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1634 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1635 nw64_mac(XMAC_CONFIG
, val
);
1637 /* XXX shared resource, lock parent XXX */
1638 val
= nr64(MIF_CONFIG
);
1639 val
|= MIF_CONFIG_INDIRECT_MODE
;
1640 nw64(MIF_CONFIG
, val
);
1642 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1643 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1645 /* handle different phy types */
1646 switch (phy_id
& NIU_PHY_ID_MASK
) {
1647 case NIU_PHY_ID_MRVL88X2011
:
1648 err
= xcvr_init_10g_mrvl88x2011(np
);
1651 default: /* bcom 8704 */
1652 err
= xcvr_init_10g_bcm8704(np
);
1659 static int mii_reset(struct niu
*np
)
1663 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1668 while (--limit
>= 0) {
1670 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1673 if (!(err
& BMCR_RESET
))
1677 netdev_err(np
->dev
, "Port %u MII would not reset, bmcr[%04x]\n",
1685 static int xcvr_init_1g_rgmii(struct niu
*np
)
1689 u16 bmcr
, bmsr
, estat
;
1691 val
= nr64(MIF_CONFIG
);
1692 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1693 nw64(MIF_CONFIG
, val
);
1695 err
= mii_reset(np
);
1699 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1705 if (bmsr
& BMSR_ESTATEN
) {
1706 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1713 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1717 if (bmsr
& BMSR_ESTATEN
) {
1720 if (estat
& ESTATUS_1000_TFULL
)
1721 ctrl1000
|= ADVERTISE_1000FULL
;
1722 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1727 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1729 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1733 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1736 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1738 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1745 static int mii_init_common(struct niu
*np
)
1747 struct niu_link_config
*lp
= &np
->link_config
;
1748 u16 bmcr
, bmsr
, adv
, estat
;
1751 err
= mii_reset(np
);
1755 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1761 if (bmsr
& BMSR_ESTATEN
) {
1762 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1769 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1773 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1774 bmcr
|= BMCR_LOOPBACK
;
1775 if (lp
->active_speed
== SPEED_1000
)
1776 bmcr
|= BMCR_SPEED1000
;
1777 if (lp
->active_duplex
== DUPLEX_FULL
)
1778 bmcr
|= BMCR_FULLDPLX
;
1781 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1784 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1785 BCM5464R_AUX_CTL_WRITE_1
);
1786 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1794 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1795 if ((bmsr
& BMSR_10HALF
) &&
1796 (lp
->advertising
& ADVERTISED_10baseT_Half
))
1797 adv
|= ADVERTISE_10HALF
;
1798 if ((bmsr
& BMSR_10FULL
) &&
1799 (lp
->advertising
& ADVERTISED_10baseT_Full
))
1800 adv
|= ADVERTISE_10FULL
;
1801 if ((bmsr
& BMSR_100HALF
) &&
1802 (lp
->advertising
& ADVERTISED_100baseT_Half
))
1803 adv
|= ADVERTISE_100HALF
;
1804 if ((bmsr
& BMSR_100FULL
) &&
1805 (lp
->advertising
& ADVERTISED_100baseT_Full
))
1806 adv
|= ADVERTISE_100FULL
;
1807 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1811 if (likely(bmsr
& BMSR_ESTATEN
)) {
1813 if ((estat
& ESTATUS_1000_THALF
) &&
1814 (lp
->advertising
& ADVERTISED_1000baseT_Half
))
1815 ctrl1000
|= ADVERTISE_1000HALF
;
1816 if ((estat
& ESTATUS_1000_TFULL
) &&
1817 (lp
->advertising
& ADVERTISED_1000baseT_Full
))
1818 ctrl1000
|= ADVERTISE_1000FULL
;
1819 err
= mii_write(np
, np
->phy_addr
,
1820 MII_CTRL1000
, ctrl1000
);
1825 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1830 if (lp
->duplex
== DUPLEX_FULL
) {
1831 bmcr
|= BMCR_FULLDPLX
;
1833 } else if (lp
->duplex
== DUPLEX_HALF
)
1838 if (lp
->speed
== SPEED_1000
) {
1839 /* if X-full requested while not supported, or
1840 X-half requested while not supported... */
1841 if ((fulldpx
&& !(estat
& ESTATUS_1000_TFULL
)) ||
1842 (!fulldpx
&& !(estat
& ESTATUS_1000_THALF
)))
1844 bmcr
|= BMCR_SPEED1000
;
1845 } else if (lp
->speed
== SPEED_100
) {
1846 if ((fulldpx
&& !(bmsr
& BMSR_100FULL
)) ||
1847 (!fulldpx
&& !(bmsr
& BMSR_100HALF
)))
1849 bmcr
|= BMCR_SPEED100
;
1850 } else if (lp
->speed
== SPEED_10
) {
1851 if ((fulldpx
&& !(bmsr
& BMSR_10FULL
)) ||
1852 (!fulldpx
&& !(bmsr
& BMSR_10HALF
)))
1858 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1863 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1868 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1873 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1874 np
->port
, bmcr
, bmsr
);
1880 static int xcvr_init_1g(struct niu
*np
)
1884 /* XXX shared resource, lock parent XXX */
1885 val
= nr64(MIF_CONFIG
);
1886 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1887 nw64(MIF_CONFIG
, val
);
1889 return mii_init_common(np
);
1892 static int niu_xcvr_init(struct niu
*np
)
1894 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1899 err
= ops
->xcvr_init(np
);
1904 static int niu_serdes_init(struct niu
*np
)
1906 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1910 if (ops
->serdes_init
)
1911 err
= ops
->serdes_init(np
);
1916 static void niu_init_xif(struct niu
*);
1917 static void niu_handle_led(struct niu
*, int status
);
1919 static int niu_link_status_common(struct niu
*np
, int link_up
)
1921 struct niu_link_config
*lp
= &np
->link_config
;
1922 struct net_device
*dev
= np
->dev
;
1923 unsigned long flags
;
1925 if (!netif_carrier_ok(dev
) && link_up
) {
1926 netif_info(np
, link
, dev
, "Link is up at %s, %s duplex\n",
1927 lp
->active_speed
== SPEED_10000
? "10Gb/sec" :
1928 lp
->active_speed
== SPEED_1000
? "1Gb/sec" :
1929 lp
->active_speed
== SPEED_100
? "100Mbit/sec" :
1931 lp
->active_duplex
== DUPLEX_FULL
? "full" : "half");
1933 spin_lock_irqsave(&np
->lock
, flags
);
1935 niu_handle_led(np
, 1);
1936 spin_unlock_irqrestore(&np
->lock
, flags
);
1938 netif_carrier_on(dev
);
1939 } else if (netif_carrier_ok(dev
) && !link_up
) {
1940 netif_warn(np
, link
, dev
, "Link is down\n");
1941 spin_lock_irqsave(&np
->lock
, flags
);
1942 niu_handle_led(np
, 0);
1943 spin_unlock_irqrestore(&np
->lock
, flags
);
1944 netif_carrier_off(dev
);
1950 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1952 int err
, link_up
, pma_status
, pcs_status
;
1956 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1957 MRVL88X2011_10G_PMD_STATUS_2
);
1961 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1962 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1963 MRVL88X2011_PMA_PMD_STATUS_1
);
1967 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1969 /* Check PMC Register : 3.0001.2 == 1: read twice */
1970 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1971 MRVL88X2011_PMA_PMD_STATUS_1
);
1975 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1976 MRVL88X2011_PMA_PMD_STATUS_1
);
1980 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
1982 /* Check XGXS Register : 4.0018.[0-3,12] */
1983 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
1984 MRVL88X2011_10G_XGXS_LANE_STAT
);
1988 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
1989 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
1990 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
1992 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
1994 np
->link_config
.active_speed
= SPEED_10000
;
1995 np
->link_config
.active_duplex
= DUPLEX_FULL
;
1998 mrvl88x2011_act_led(np
, (link_up
?
1999 MRVL88X2011_LED_CTL_PCS_ACT
:
2000 MRVL88X2011_LED_CTL_OFF
));
2002 *link_up_p
= link_up
;
2006 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
2011 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2012 BCM8704_PMD_RCV_SIGDET
);
2013 if (err
< 0 || err
== 0xffff)
2015 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2020 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2021 BCM8704_PCS_10G_R_STATUS
);
2025 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2030 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2031 BCM8704_PHYXS_XGXS_LANE_STAT
);
2034 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2035 PHYXS_XGXS_LANE_STAT_MAGIC
|
2036 PHYXS_XGXS_LANE_STAT_PATTEST
|
2037 PHYXS_XGXS_LANE_STAT_LANE3
|
2038 PHYXS_XGXS_LANE_STAT_LANE2
|
2039 PHYXS_XGXS_LANE_STAT_LANE1
|
2040 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2042 np
->link_config
.active_speed
= SPEED_INVALID
;
2043 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
2048 np
->link_config
.active_speed
= SPEED_10000
;
2049 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2053 *link_up_p
= link_up
;
2057 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
2063 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2064 BCM8704_PMD_RCV_SIGDET
);
2067 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2072 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2073 BCM8704_PCS_10G_R_STATUS
);
2076 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2081 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2082 BCM8704_PHYXS_XGXS_LANE_STAT
);
2086 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2087 PHYXS_XGXS_LANE_STAT_MAGIC
|
2088 PHYXS_XGXS_LANE_STAT_LANE3
|
2089 PHYXS_XGXS_LANE_STAT_LANE2
|
2090 PHYXS_XGXS_LANE_STAT_LANE1
|
2091 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2097 np
->link_config
.active_speed
= SPEED_10000
;
2098 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2102 *link_up_p
= link_up
;
2106 static int link_status_10g(struct niu
*np
, int *link_up_p
)
2108 unsigned long flags
;
2111 spin_lock_irqsave(&np
->lock
, flags
);
2113 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2116 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
2117 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
2119 /* handle different phy types */
2120 switch (phy_id
& NIU_PHY_ID_MASK
) {
2121 case NIU_PHY_ID_MRVL88X2011
:
2122 err
= link_status_10g_mrvl(np
, link_up_p
);
2125 default: /* bcom 8704 */
2126 err
= link_status_10g_bcom(np
, link_up_p
);
2131 spin_unlock_irqrestore(&np
->lock
, flags
);
2136 static int niu_10g_phy_present(struct niu
*np
)
2140 sig
= nr64(ESR_INT_SIGNALS
);
2143 mask
= ESR_INT_SIGNALS_P0_BITS
;
2144 val
= (ESR_INT_SRDY0_P0
|
2147 ESR_INT_XDP_P0_CH3
|
2148 ESR_INT_XDP_P0_CH2
|
2149 ESR_INT_XDP_P0_CH1
|
2150 ESR_INT_XDP_P0_CH0
);
2154 mask
= ESR_INT_SIGNALS_P1_BITS
;
2155 val
= (ESR_INT_SRDY0_P1
|
2158 ESR_INT_XDP_P1_CH3
|
2159 ESR_INT_XDP_P1_CH2
|
2160 ESR_INT_XDP_P1_CH1
|
2161 ESR_INT_XDP_P1_CH0
);
2168 if ((sig
& mask
) != val
)
2173 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
2175 unsigned long flags
;
2178 int phy_present_prev
;
2180 spin_lock_irqsave(&np
->lock
, flags
);
2182 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2183 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
2185 phy_present
= niu_10g_phy_present(np
);
2186 if (phy_present
!= phy_present_prev
) {
2189 /* A NEM was just plugged in */
2190 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2191 if (np
->phy_ops
->xcvr_init
)
2192 err
= np
->phy_ops
->xcvr_init(np
);
2194 err
= mdio_read(np
, np
->phy_addr
,
2195 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
2196 if (err
== 0xffff) {
2197 /* No mdio, back-to-back XAUI */
2201 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2204 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2206 netif_warn(np
, link
, np
->dev
,
2207 "Hotplug PHY Removed\n");
2211 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) {
2212 err
= link_status_10g_bcm8706(np
, link_up_p
);
2213 if (err
== 0xffff) {
2214 /* No mdio, back-to-back XAUI: it is C10NEM */
2216 np
->link_config
.active_speed
= SPEED_10000
;
2217 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2222 spin_unlock_irqrestore(&np
->lock
, flags
);
2227 static int niu_link_status(struct niu
*np
, int *link_up_p
)
2229 const struct niu_phy_ops
*ops
= np
->phy_ops
;
2233 if (ops
->link_status
)
2234 err
= ops
->link_status(np
, link_up_p
);
2239 static void niu_timer(unsigned long __opaque
)
2241 struct niu
*np
= (struct niu
*) __opaque
;
2245 err
= niu_link_status(np
, &link_up
);
2247 niu_link_status_common(np
, link_up
);
2249 if (netif_carrier_ok(np
->dev
))
2253 np
->timer
.expires
= jiffies
+ off
;
2255 add_timer(&np
->timer
);
2258 static const struct niu_phy_ops phy_ops_10g_serdes
= {
2259 .serdes_init
= serdes_init_10g_serdes
,
2260 .link_status
= link_status_10g_serdes
,
2263 static const struct niu_phy_ops phy_ops_10g_serdes_niu
= {
2264 .serdes_init
= serdes_init_niu_10g_serdes
,
2265 .link_status
= link_status_10g_serdes
,
2268 static const struct niu_phy_ops phy_ops_1g_serdes_niu
= {
2269 .serdes_init
= serdes_init_niu_1g_serdes
,
2270 .link_status
= link_status_1g_serdes
,
2273 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
2274 .xcvr_init
= xcvr_init_1g_rgmii
,
2275 .link_status
= link_status_1g_rgmii
,
2278 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
2279 .serdes_init
= serdes_init_niu_10g_fiber
,
2280 .xcvr_init
= xcvr_init_10g
,
2281 .link_status
= link_status_10g
,
2284 static const struct niu_phy_ops phy_ops_10g_fiber
= {
2285 .serdes_init
= serdes_init_10g
,
2286 .xcvr_init
= xcvr_init_10g
,
2287 .link_status
= link_status_10g
,
2290 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
2291 .serdes_init
= serdes_init_10g
,
2292 .xcvr_init
= xcvr_init_10g_bcm8706
,
2293 .link_status
= link_status_10g_hotplug
,
2296 static const struct niu_phy_ops phy_ops_niu_10g_hotplug
= {
2297 .serdes_init
= serdes_init_niu_10g_fiber
,
2298 .xcvr_init
= xcvr_init_10g_bcm8706
,
2299 .link_status
= link_status_10g_hotplug
,
2302 static const struct niu_phy_ops phy_ops_10g_copper
= {
2303 .serdes_init
= serdes_init_10g
,
2304 .link_status
= link_status_10g
, /* XXX */
2307 static const struct niu_phy_ops phy_ops_1g_fiber
= {
2308 .serdes_init
= serdes_init_1g
,
2309 .xcvr_init
= xcvr_init_1g
,
2310 .link_status
= link_status_1g
,
2313 static const struct niu_phy_ops phy_ops_1g_copper
= {
2314 .xcvr_init
= xcvr_init_1g
,
2315 .link_status
= link_status_1g
,
2318 struct niu_phy_template
{
2319 const struct niu_phy_ops
*ops
;
2323 static const struct niu_phy_template phy_template_niu_10g_fiber
= {
2324 .ops
= &phy_ops_10g_fiber_niu
,
2325 .phy_addr_base
= 16,
2328 static const struct niu_phy_template phy_template_niu_10g_serdes
= {
2329 .ops
= &phy_ops_10g_serdes_niu
,
2333 static const struct niu_phy_template phy_template_niu_1g_serdes
= {
2334 .ops
= &phy_ops_1g_serdes_niu
,
2338 static const struct niu_phy_template phy_template_10g_fiber
= {
2339 .ops
= &phy_ops_10g_fiber
,
2343 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2344 .ops
= &phy_ops_10g_fiber_hotplug
,
2348 static const struct niu_phy_template phy_template_niu_10g_hotplug
= {
2349 .ops
= &phy_ops_niu_10g_hotplug
,
2353 static const struct niu_phy_template phy_template_10g_copper
= {
2354 .ops
= &phy_ops_10g_copper
,
2355 .phy_addr_base
= 10,
2358 static const struct niu_phy_template phy_template_1g_fiber
= {
2359 .ops
= &phy_ops_1g_fiber
,
2363 static const struct niu_phy_template phy_template_1g_copper
= {
2364 .ops
= &phy_ops_1g_copper
,
2368 static const struct niu_phy_template phy_template_1g_rgmii
= {
2369 .ops
= &phy_ops_1g_rgmii
,
2373 static const struct niu_phy_template phy_template_10g_serdes
= {
2374 .ops
= &phy_ops_10g_serdes
,
2378 static int niu_atca_port_num
[4] = {
2382 static int serdes_init_10g_serdes(struct niu
*np
)
2384 struct niu_link_config
*lp
= &np
->link_config
;
2385 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2386 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2391 reset_val
= ENET_SERDES_RESET_0
;
2392 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2393 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2394 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2397 reset_val
= ENET_SERDES_RESET_1
;
2398 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2399 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2400 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2406 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2407 ENET_SERDES_CTRL_SDET_1
|
2408 ENET_SERDES_CTRL_SDET_2
|
2409 ENET_SERDES_CTRL_SDET_3
|
2410 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2411 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2412 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2413 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2414 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2415 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2416 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2417 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2420 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2421 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2422 ENET_SERDES_TEST_MD_0_SHIFT
) |
2423 (ENET_TEST_MD_PAD_LOOPBACK
<<
2424 ENET_SERDES_TEST_MD_1_SHIFT
) |
2425 (ENET_TEST_MD_PAD_LOOPBACK
<<
2426 ENET_SERDES_TEST_MD_2_SHIFT
) |
2427 (ENET_TEST_MD_PAD_LOOPBACK
<<
2428 ENET_SERDES_TEST_MD_3_SHIFT
));
2432 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2433 nw64(ctrl_reg
, ctrl_val
);
2434 nw64(test_cfg_reg
, test_cfg_val
);
2436 /* Initialize all 4 lanes of the SERDES. */
2437 for (i
= 0; i
< 4; i
++) {
2438 u32 rxtx_ctrl
, glue0
;
2441 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2444 err
= esr_read_glue0(np
, i
, &glue0
);
2448 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2449 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2450 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2452 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2453 ESR_GLUE_CTRL0_THCNT
|
2454 ESR_GLUE_CTRL0_BLTIME
);
2455 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2456 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2457 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2458 (BLTIME_300_CYCLES
<<
2459 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2461 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2464 err
= esr_write_glue0(np
, i
, glue0
);
2470 sig
= nr64(ESR_INT_SIGNALS
);
2473 mask
= ESR_INT_SIGNALS_P0_BITS
;
2474 val
= (ESR_INT_SRDY0_P0
|
2477 ESR_INT_XDP_P0_CH3
|
2478 ESR_INT_XDP_P0_CH2
|
2479 ESR_INT_XDP_P0_CH1
|
2480 ESR_INT_XDP_P0_CH0
);
2484 mask
= ESR_INT_SIGNALS_P1_BITS
;
2485 val
= (ESR_INT_SRDY0_P1
|
2488 ESR_INT_XDP_P1_CH3
|
2489 ESR_INT_XDP_P1_CH2
|
2490 ESR_INT_XDP_P1_CH1
|
2491 ESR_INT_XDP_P1_CH0
);
2498 if ((sig
& mask
) != val
) {
2500 err
= serdes_init_1g_serdes(np
);
2502 np
->flags
&= ~NIU_FLAGS_10G
;
2503 np
->mac_xcvr
= MAC_XCVR_PCS
;
2505 netdev_err(np
->dev
, "Port %u 10G/1G SERDES Link Failed\n",
2514 static int niu_determine_phy_disposition(struct niu
*np
)
2516 struct niu_parent
*parent
= np
->parent
;
2517 u8 plat_type
= parent
->plat_type
;
2518 const struct niu_phy_template
*tp
;
2519 u32 phy_addr_off
= 0;
2521 if (plat_type
== PLAT_TYPE_NIU
) {
2525 NIU_FLAGS_XCVR_SERDES
)) {
2526 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2528 tp
= &phy_template_niu_10g_serdes
;
2530 case NIU_FLAGS_XCVR_SERDES
:
2532 tp
= &phy_template_niu_1g_serdes
;
2534 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2537 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2538 tp
= &phy_template_niu_10g_hotplug
;
2544 tp
= &phy_template_niu_10g_fiber
;
2545 phy_addr_off
+= np
->port
;
2553 NIU_FLAGS_XCVR_SERDES
)) {
2556 tp
= &phy_template_1g_copper
;
2557 if (plat_type
== PLAT_TYPE_VF_P0
)
2559 else if (plat_type
== PLAT_TYPE_VF_P1
)
2562 phy_addr_off
+= (np
->port
^ 0x3);
2567 tp
= &phy_template_10g_copper
;
2570 case NIU_FLAGS_FIBER
:
2572 tp
= &phy_template_1g_fiber
;
2575 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2577 tp
= &phy_template_10g_fiber
;
2578 if (plat_type
== PLAT_TYPE_VF_P0
||
2579 plat_type
== PLAT_TYPE_VF_P1
)
2581 phy_addr_off
+= np
->port
;
2582 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2583 tp
= &phy_template_10g_fiber_hotplug
;
2591 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2592 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2593 case NIU_FLAGS_XCVR_SERDES
:
2597 tp
= &phy_template_10g_serdes
;
2601 tp
= &phy_template_1g_rgmii
;
2607 phy_addr_off
= niu_atca_port_num
[np
->port
];
2615 np
->phy_ops
= tp
->ops
;
2616 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2621 static int niu_init_link(struct niu
*np
)
2623 struct niu_parent
*parent
= np
->parent
;
2626 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2627 err
= niu_xcvr_init(np
);
2632 err
= niu_serdes_init(np
);
2633 if (err
&& !(np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2636 err
= niu_xcvr_init(np
);
2637 if (!err
|| (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2638 niu_link_status(np
, &ignore
);
2642 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2644 u16 reg0
= addr
[4] << 8 | addr
[5];
2645 u16 reg1
= addr
[2] << 8 | addr
[3];
2646 u16 reg2
= addr
[0] << 8 | addr
[1];
2648 if (np
->flags
& NIU_FLAGS_XMAC
) {
2649 nw64_mac(XMAC_ADDR0
, reg0
);
2650 nw64_mac(XMAC_ADDR1
, reg1
);
2651 nw64_mac(XMAC_ADDR2
, reg2
);
2653 nw64_mac(BMAC_ADDR0
, reg0
);
2654 nw64_mac(BMAC_ADDR1
, reg1
);
2655 nw64_mac(BMAC_ADDR2
, reg2
);
2659 static int niu_num_alt_addr(struct niu
*np
)
2661 if (np
->flags
& NIU_FLAGS_XMAC
)
2662 return XMAC_NUM_ALT_ADDR
;
2664 return BMAC_NUM_ALT_ADDR
;
2667 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2669 u16 reg0
= addr
[4] << 8 | addr
[5];
2670 u16 reg1
= addr
[2] << 8 | addr
[3];
2671 u16 reg2
= addr
[0] << 8 | addr
[1];
2673 if (index
>= niu_num_alt_addr(np
))
2676 if (np
->flags
& NIU_FLAGS_XMAC
) {
2677 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2678 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2679 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2681 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2682 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2683 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2689 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2694 if (index
>= niu_num_alt_addr(np
))
2697 if (np
->flags
& NIU_FLAGS_XMAC
) {
2698 reg
= XMAC_ADDR_CMPEN
;
2701 reg
= BMAC_ADDR_CMPEN
;
2702 mask
= 1 << (index
+ 1);
2705 val
= nr64_mac(reg
);
2715 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2716 int num
, int mac_pref
)
2718 u64 val
= nr64_mac(reg
);
2719 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2722 val
|= HOST_INFO_MPR
;
2726 static int __set_rdc_table_num(struct niu
*np
,
2727 int xmac_index
, int bmac_index
,
2728 int rdc_table_num
, int mac_pref
)
2732 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2734 if (np
->flags
& NIU_FLAGS_XMAC
)
2735 reg
= XMAC_HOST_INFO(xmac_index
);
2737 reg
= BMAC_HOST_INFO(bmac_index
);
2738 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2742 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2745 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2748 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2751 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2754 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2755 int table_num
, int mac_pref
)
2757 if (idx
>= niu_num_alt_addr(np
))
2759 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2762 static u64
vlan_entry_set_parity(u64 reg_val
)
2767 port01_mask
= 0x00ff;
2768 port23_mask
= 0xff00;
2770 if (hweight64(reg_val
& port01_mask
) & 1)
2771 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2773 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2775 if (hweight64(reg_val
& port23_mask
) & 1)
2776 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2778 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2783 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2784 int port
, int vpr
, int rdc_table
)
2786 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2788 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2789 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2790 ENET_VLAN_TBL_SHIFT(port
));
2792 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2793 ENET_VLAN_TBL_SHIFT(port
));
2794 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2796 reg_val
= vlan_entry_set_parity(reg_val
);
2798 nw64(ENET_VLAN_TBL(index
), reg_val
);
2801 static void vlan_tbl_clear(struct niu
*np
)
2805 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2806 nw64(ENET_VLAN_TBL(i
), 0);
2809 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2813 while (--limit
> 0) {
2814 if (nr64(TCAM_CTL
) & bit
)
2824 static int tcam_flush(struct niu
*np
, int index
)
2826 nw64(TCAM_KEY_0
, 0x00);
2827 nw64(TCAM_KEY_MASK_0
, 0xff);
2828 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2830 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2834 static int tcam_read(struct niu
*np
, int index
,
2835 u64
*key
, u64
*mask
)
2839 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2840 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2842 key
[0] = nr64(TCAM_KEY_0
);
2843 key
[1] = nr64(TCAM_KEY_1
);
2844 key
[2] = nr64(TCAM_KEY_2
);
2845 key
[3] = nr64(TCAM_KEY_3
);
2846 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2847 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2848 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2849 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2855 static int tcam_write(struct niu
*np
, int index
,
2856 u64
*key
, u64
*mask
)
2858 nw64(TCAM_KEY_0
, key
[0]);
2859 nw64(TCAM_KEY_1
, key
[1]);
2860 nw64(TCAM_KEY_2
, key
[2]);
2861 nw64(TCAM_KEY_3
, key
[3]);
2862 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2863 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2864 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2865 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2866 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2868 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2872 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2876 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2877 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2879 *data
= nr64(TCAM_KEY_1
);
2885 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2887 nw64(TCAM_KEY_1
, assoc_data
);
2888 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2890 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2893 static void tcam_enable(struct niu
*np
, int on
)
2895 u64 val
= nr64(FFLP_CFG_1
);
2898 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2900 val
|= FFLP_CFG_1_TCAM_DIS
;
2901 nw64(FFLP_CFG_1
, val
);
2904 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2906 u64 val
= nr64(FFLP_CFG_1
);
2908 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2910 FFLP_CFG_1_CAMRATIO
);
2911 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2912 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2913 nw64(FFLP_CFG_1
, val
);
2915 val
= nr64(FFLP_CFG_1
);
2916 val
|= FFLP_CFG_1_FFLPINITDONE
;
2917 nw64(FFLP_CFG_1
, val
);
2920 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2926 if (class < CLASS_CODE_ETHERTYPE1
||
2927 class > CLASS_CODE_ETHERTYPE2
)
2930 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2942 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2948 if (class < CLASS_CODE_ETHERTYPE1
||
2949 class > CLASS_CODE_ETHERTYPE2
||
2950 (ether_type
& ~(u64
)0xffff) != 0)
2953 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2955 val
&= ~L2_CLS_ETYPE
;
2956 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2963 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
2969 if (class < CLASS_CODE_USER_PROG1
||
2970 class > CLASS_CODE_USER_PROG4
)
2973 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
2976 val
|= L3_CLS_VALID
;
2978 val
&= ~L3_CLS_VALID
;
2984 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
2985 int ipv6
, u64 protocol_id
,
2986 u64 tos_mask
, u64 tos_val
)
2991 if (class < CLASS_CODE_USER_PROG1
||
2992 class > CLASS_CODE_USER_PROG4
||
2993 (protocol_id
& ~(u64
)0xff) != 0 ||
2994 (tos_mask
& ~(u64
)0xff) != 0 ||
2995 (tos_val
& ~(u64
)0xff) != 0)
2998 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
3000 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
3001 L3_CLS_TOSMASK
| L3_CLS_TOS
);
3003 val
|= L3_CLS_IPVER
;
3004 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
3005 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
3006 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
3012 static int tcam_early_init(struct niu
*np
)
3018 tcam_set_lat_and_ratio(np
,
3019 DEFAULT_TCAM_LATENCY
,
3020 DEFAULT_TCAM_ACCESS_RATIO
);
3021 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
3022 err
= tcam_user_eth_class_enable(np
, i
, 0);
3026 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
3027 err
= tcam_user_ip_class_enable(np
, i
, 0);
3035 static int tcam_flush_all(struct niu
*np
)
3039 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
3040 int err
= tcam_flush(np
, i
);
3047 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
3049 return ((u64
)index
| (num_entries
== 1 ?
3050 HASH_TBL_ADDR_AUTOINC
: 0));
3054 static int hash_read(struct niu
*np
, unsigned long partition
,
3055 unsigned long index
, unsigned long num_entries
,
3058 u64 val
= hash_addr_regval(index
, num_entries
);
3061 if (partition
>= FCRAM_NUM_PARTITIONS
||
3062 index
+ num_entries
> FCRAM_SIZE
)
3065 nw64(HASH_TBL_ADDR(partition
), val
);
3066 for (i
= 0; i
< num_entries
; i
++)
3067 data
[i
] = nr64(HASH_TBL_DATA(partition
));
3073 static int hash_write(struct niu
*np
, unsigned long partition
,
3074 unsigned long index
, unsigned long num_entries
,
3077 u64 val
= hash_addr_regval(index
, num_entries
);
3080 if (partition
>= FCRAM_NUM_PARTITIONS
||
3081 index
+ (num_entries
* 8) > FCRAM_SIZE
)
3084 nw64(HASH_TBL_ADDR(partition
), val
);
3085 for (i
= 0; i
< num_entries
; i
++)
3086 nw64(HASH_TBL_DATA(partition
), data
[i
]);
3091 static void fflp_reset(struct niu
*np
)
3095 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
3097 nw64(FFLP_CFG_1
, 0);
3099 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
3100 nw64(FFLP_CFG_1
, val
);
3103 static void fflp_set_timings(struct niu
*np
)
3105 u64 val
= nr64(FFLP_CFG_1
);
3107 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
3108 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
3109 nw64(FFLP_CFG_1
, val
);
3111 val
= nr64(FFLP_CFG_1
);
3112 val
|= FFLP_CFG_1_FFLPINITDONE
;
3113 nw64(FFLP_CFG_1
, val
);
3115 val
= nr64(FCRAM_REF_TMR
);
3116 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
3117 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
3118 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
3119 nw64(FCRAM_REF_TMR
, val
);
3122 static int fflp_set_partition(struct niu
*np
, u64 partition
,
3123 u64 mask
, u64 base
, int enable
)
3128 if (partition
>= FCRAM_NUM_PARTITIONS
||
3129 (mask
& ~(u64
)0x1f) != 0 ||
3130 (base
& ~(u64
)0x1f) != 0)
3133 reg
= FLW_PRT_SEL(partition
);
3136 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
3137 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
3138 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
3140 val
|= FLW_PRT_SEL_EXT
;
3146 static int fflp_disable_all_partitions(struct niu
*np
)
3150 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
3151 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
3158 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
3160 u64 val
= nr64(FFLP_CFG_1
);
3163 val
|= FFLP_CFG_1_LLCSNAP
;
3165 val
&= ~FFLP_CFG_1_LLCSNAP
;
3166 nw64(FFLP_CFG_1
, val
);
3169 static void fflp_errors_enable(struct niu
*np
, int on
)
3171 u64 val
= nr64(FFLP_CFG_1
);
3174 val
&= ~FFLP_CFG_1_ERRORDIS
;
3176 val
|= FFLP_CFG_1_ERRORDIS
;
3177 nw64(FFLP_CFG_1
, val
);
3180 static int fflp_hash_clear(struct niu
*np
)
3182 struct fcram_hash_ipv4 ent
;
3185 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3186 memset(&ent
, 0, sizeof(ent
));
3187 ent
.header
= HASH_HEADER_EXT
;
3189 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
3190 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
3197 static int fflp_early_init(struct niu
*np
)
3199 struct niu_parent
*parent
;
3200 unsigned long flags
;
3203 niu_lock_parent(np
, flags
);
3205 parent
= np
->parent
;
3207 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
3208 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3210 fflp_set_timings(np
);
3211 err
= fflp_disable_all_partitions(np
);
3213 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3214 "fflp_disable_all_partitions failed, err=%d\n",
3220 err
= tcam_early_init(np
);
3222 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3223 "tcam_early_init failed, err=%d\n", err
);
3226 fflp_llcsnap_enable(np
, 1);
3227 fflp_errors_enable(np
, 0);
3231 err
= tcam_flush_all(np
);
3233 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3234 "tcam_flush_all failed, err=%d\n", err
);
3237 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3238 err
= fflp_hash_clear(np
);
3240 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
3241 "fflp_hash_clear failed, err=%d\n",
3249 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
3252 niu_unlock_parent(np
, flags
);
3256 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3258 if (class_code
< CLASS_CODE_USER_PROG1
||
3259 class_code
> CLASS_CODE_SCTP_IPV6
)
3262 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3266 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3268 if (class_code
< CLASS_CODE_USER_PROG1
||
3269 class_code
> CLASS_CODE_SCTP_IPV6
)
3272 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3276 /* Entries for the ports are interleaved in the TCAM */
3277 static u16
tcam_get_index(struct niu
*np
, u16 idx
)
3279 /* One entry reserved for IP fragment rule */
3280 if (idx
>= (np
->clas
.tcam_sz
- 1))
3282 return (np
->clas
.tcam_top
+ ((idx
+1) * np
->parent
->num_ports
));
3285 static u16
tcam_get_size(struct niu
*np
)
3287 /* One entry reserved for IP fragment rule */
3288 return np
->clas
.tcam_sz
- 1;
3291 static u16
tcam_get_valid_entry_cnt(struct niu
*np
)
3293 /* One entry reserved for IP fragment rule */
3294 return np
->clas
.tcam_valid_entries
- 1;
3297 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
3298 u32 offset
, u32 size
)
3300 int i
= skb_shinfo(skb
)->nr_frags
;
3301 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3304 frag
->page_offset
= offset
;
3308 skb
->data_len
+= size
;
3309 skb
->truesize
+= size
;
3311 skb_shinfo(skb
)->nr_frags
= i
+ 1;
3314 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
3317 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
3319 return (a
& (MAX_RBR_RING_SIZE
- 1));
3322 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
3323 struct page
***link
)
3325 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
3326 struct page
*p
, **pp
;
3329 pp
= &rp
->rxhash
[h
];
3330 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
3331 if (p
->index
== addr
) {
3342 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
3344 unsigned int h
= niu_hash_rxaddr(rp
, base
);
3347 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
3348 rp
->rxhash
[h
] = page
;
3351 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
3352 gfp_t mask
, int start_index
)
3358 page
= alloc_page(mask
);
3362 addr
= np
->ops
->map_page(np
->device
, page
, 0,
3363 PAGE_SIZE
, DMA_FROM_DEVICE
);
3365 niu_hash_page(rp
, page
, addr
);
3366 if (rp
->rbr_blocks_per_page
> 1)
3367 atomic_add(rp
->rbr_blocks_per_page
- 1,
3368 &compound_head(page
)->_count
);
3370 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
3371 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
3373 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
3374 addr
+= rp
->rbr_block_size
;
3380 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3382 int index
= rp
->rbr_index
;
3385 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3386 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3388 if (unlikely(err
)) {
3393 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3394 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3395 if (rp
->rbr_index
== rp
->rbr_table_size
)
3398 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3399 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3400 rp
->rbr_pending
= 0;
3405 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3407 unsigned int index
= rp
->rcr_index
;
3412 struct page
*page
, **link
;
3418 val
= le64_to_cpup(&rp
->rcr
[index
]);
3419 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3420 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3421 page
= niu_find_rxpage(rp
, addr
, &link
);
3423 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3424 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3425 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3426 *link
= (struct page
*) page
->mapping
;
3427 np
->ops
->unmap_page(np
->device
, page
->index
,
3428 PAGE_SIZE
, DMA_FROM_DEVICE
);
3430 page
->mapping
= NULL
;
3432 rp
->rbr_refill_pending
++;
3435 index
= NEXT_RCR(rp
, index
);
3436 if (!(val
& RCR_ENTRY_MULTI
))
3440 rp
->rcr_index
= index
;
3445 static int niu_process_rx_pkt(struct napi_struct
*napi
, struct niu
*np
,
3446 struct rx_ring_info
*rp
)
3448 unsigned int index
= rp
->rcr_index
;
3449 struct rx_pkt_hdr1
*rh
;
3450 struct sk_buff
*skb
;
3453 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3455 return niu_rx_pkt_ignore(np
, rp
);
3459 struct page
*page
, **link
;
3460 u32 rcr_size
, append_size
;
3465 val
= le64_to_cpup(&rp
->rcr
[index
]);
3467 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3468 RCR_ENTRY_L2_LEN_SHIFT
;
3471 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3472 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3473 page
= niu_find_rxpage(rp
, addr
, &link
);
3475 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3476 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3478 off
= addr
& ~PAGE_MASK
;
3479 append_size
= rcr_size
;
3483 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3484 if ((ptype
== RCR_PKT_TYPE_TCP
||
3485 ptype
== RCR_PKT_TYPE_UDP
) &&
3486 !(val
& (RCR_ENTRY_NOPORT
|
3488 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3490 skb
->ip_summed
= CHECKSUM_NONE
;
3491 } else if (!(val
& RCR_ENTRY_MULTI
))
3492 append_size
= len
- skb
->len
;
3494 niu_rx_skb_append(skb
, page
, off
, append_size
);
3495 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3496 *link
= (struct page
*) page
->mapping
;
3497 np
->ops
->unmap_page(np
->device
, page
->index
,
3498 PAGE_SIZE
, DMA_FROM_DEVICE
);
3500 page
->mapping
= NULL
;
3501 rp
->rbr_refill_pending
++;
3505 index
= NEXT_RCR(rp
, index
);
3506 if (!(val
& RCR_ENTRY_MULTI
))
3510 rp
->rcr_index
= index
;
3513 len
= min_t(int, len
, sizeof(*rh
) + VLAN_ETH_HLEN
);
3514 __pskb_pull_tail(skb
, len
);
3516 rh
= (struct rx_pkt_hdr1
*) skb
->data
;
3517 if (np
->dev
->features
& NETIF_F_RXHASH
)
3518 skb
->rxhash
= ((u32
)rh
->hashval2_0
<< 24 |
3519 (u32
)rh
->hashval2_1
<< 16 |
3520 (u32
)rh
->hashval1_1
<< 8 |
3521 (u32
)rh
->hashval1_2
<< 0);
3522 skb_pull(skb
, sizeof(*rh
));
3525 rp
->rx_bytes
+= skb
->len
;
3527 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3528 skb_record_rx_queue(skb
, rp
->rx_channel
);
3529 napi_gro_receive(napi
, skb
);
3534 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3536 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3537 int err
, index
= rp
->rbr_index
;
3540 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3541 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3545 index
+= blocks_per_page
;
3548 rp
->rbr_index
= index
;
3552 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3556 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3559 page
= rp
->rxhash
[i
];
3561 struct page
*next
= (struct page
*) page
->mapping
;
3562 u64 base
= page
->index
;
3564 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3567 page
->mapping
= NULL
;
3575 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3576 rp
->rbr
[i
] = cpu_to_le32(0);
3580 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3582 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3583 struct sk_buff
*skb
= tb
->skb
;
3584 struct tx_pkt_hdr
*tp
;
3588 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3589 tx_flags
= le64_to_cpup(&tp
->flags
);
3592 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3593 ((tx_flags
& TXHDR_PAD
) / 2));
3595 len
= skb_headlen(skb
);
3596 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3597 len
, DMA_TO_DEVICE
);
3599 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3604 idx
= NEXT_TX(rp
, idx
);
3605 len
-= MAX_TX_DESC_LEN
;
3608 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3609 tb
= &rp
->tx_buffs
[idx
];
3610 BUG_ON(tb
->skb
!= NULL
);
3611 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3612 skb_shinfo(skb
)->frags
[i
].size
,
3614 idx
= NEXT_TX(rp
, idx
);
3622 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3624 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3626 struct netdev_queue
*txq
;
3631 index
= (rp
- np
->tx_rings
);
3632 txq
= netdev_get_tx_queue(np
->dev
, index
);
3635 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3638 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3639 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3640 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3642 rp
->last_pkt_cnt
= tmp
;
3646 netif_printk(np
, tx_done
, KERN_DEBUG
, np
->dev
,
3647 "%s() pkt_cnt[%u] cons[%d]\n", __func__
, pkt_cnt
, cons
);
3650 cons
= release_tx_packet(np
, rp
, cons
);
3656 if (unlikely(netif_tx_queue_stopped(txq
) &&
3657 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3658 __netif_tx_lock(txq
, smp_processor_id());
3659 if (netif_tx_queue_stopped(txq
) &&
3660 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3661 netif_tx_wake_queue(txq
);
3662 __netif_tx_unlock(txq
);
3666 static inline void niu_sync_rx_discard_stats(struct niu
*np
,
3667 struct rx_ring_info
*rp
,
3670 /* This elaborate scheme is needed for reading the RX discard
3671 * counters, as they are only 16-bit and can overflow quickly,
3672 * and because the overflow indication bit is not usable as
3673 * the counter value does not wrap, but remains at max value
3676 * In theory and in practice counters can be lost in between
3677 * reading nr64() and clearing the counter nw64(). For this
3678 * reason, the number of counter clearings nw64() is
3679 * limited/reduced though the limit parameter.
3681 int rx_channel
= rp
->rx_channel
;
3684 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3685 * following discard events: IPP (Input Port Process),
3686 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3687 * Block Ring) prefetch buffer is empty.
3689 misc
= nr64(RXMISC(rx_channel
));
3690 if (unlikely((misc
& RXMISC_COUNT
) > limit
)) {
3691 nw64(RXMISC(rx_channel
), 0);
3692 rp
->rx_errors
+= misc
& RXMISC_COUNT
;
3694 if (unlikely(misc
& RXMISC_OFLOW
))
3695 dev_err(np
->device
, "rx-%d: Counter overflow RXMISC discard\n",
3698 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3699 "rx-%d: MISC drop=%u over=%u\n",
3700 rx_channel
, misc
, misc
-limit
);
3703 /* WRED (Weighted Random Early Discard) by hardware */
3704 wred
= nr64(RED_DIS_CNT(rx_channel
));
3705 if (unlikely((wred
& RED_DIS_CNT_COUNT
) > limit
)) {
3706 nw64(RED_DIS_CNT(rx_channel
), 0);
3707 rp
->rx_dropped
+= wred
& RED_DIS_CNT_COUNT
;
3709 if (unlikely(wred
& RED_DIS_CNT_OFLOW
))
3710 dev_err(np
->device
, "rx-%d: Counter overflow WRED discard\n", rx_channel
);
3712 netif_printk(np
, rx_err
, KERN_DEBUG
, np
->dev
,
3713 "rx-%d: WRED drop=%u over=%u\n",
3714 rx_channel
, wred
, wred
-limit
);
3718 static int niu_rx_work(struct napi_struct
*napi
, struct niu
*np
,
3719 struct rx_ring_info
*rp
, int budget
)
3721 int qlen
, rcr_done
= 0, work_done
= 0;
3722 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3726 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3727 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3729 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3730 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3732 mbox
->rx_dma_ctl_stat
= 0;
3733 mbox
->rcrstat_a
= 0;
3735 netif_printk(np
, rx_status
, KERN_DEBUG
, np
->dev
,
3736 "%s(chan[%d]), stat[%llx] qlen=%d\n",
3737 __func__
, rp
->rx_channel
, (unsigned long long)stat
, qlen
);
3739 rcr_done
= work_done
= 0;
3740 qlen
= min(qlen
, budget
);
3741 while (work_done
< qlen
) {
3742 rcr_done
+= niu_process_rx_pkt(napi
, np
, rp
);
3746 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3749 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3750 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3751 rp
->rbr_refill_pending
= 0;
3754 stat
= (RX_DMA_CTL_STAT_MEX
|
3755 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3756 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3758 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3760 /* Only sync discards stats when qlen indicate potential for drops */
3762 niu_sync_rx_discard_stats(np
, rp
, 0x7FFF);
3767 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3770 u32 tx_vec
= (v0
>> 32);
3771 u32 rx_vec
= (v0
& 0xffffffff);
3772 int i
, work_done
= 0;
3774 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
3775 "%s() v0[%016llx]\n", __func__
, (unsigned long long)v0
);
3777 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3778 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3779 if (tx_vec
& (1 << rp
->tx_channel
))
3780 niu_tx_work(np
, rp
);
3781 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3784 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3785 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3787 if (rx_vec
& (1 << rp
->rx_channel
)) {
3790 this_work_done
= niu_rx_work(&lp
->napi
, np
, rp
,
3793 budget
-= this_work_done
;
3794 work_done
+= this_work_done
;
3796 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3802 static int niu_poll(struct napi_struct
*napi
, int budget
)
3804 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3805 struct niu
*np
= lp
->np
;
3808 work_done
= niu_poll_core(np
, lp
, budget
);
3810 if (work_done
< budget
) {
3811 napi_complete(napi
);
3812 niu_ldg_rearm(np
, lp
, 1);
3817 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3820 netdev_err(np
->dev
, "RX channel %u errors ( ", rp
->rx_channel
);
3822 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3823 pr_cont("RBR_TMOUT ");
3824 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3825 pr_cont("RSP_CNT ");
3826 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3827 pr_cont("BYTE_EN_BUS ");
3828 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3829 pr_cont("RSP_DAT ");
3830 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3831 pr_cont("RCR_ACK ");
3832 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3833 pr_cont("RCR_SHA_PAR ");
3834 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3835 pr_cont("RBR_PRE_PAR ");
3836 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3838 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3839 pr_cont("RCRINCON ");
3840 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3841 pr_cont("RCRFULL ");
3842 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3843 pr_cont("RBRFULL ");
3844 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3845 pr_cont("RBRLOGPAGE ");
3846 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3847 pr_cont("CFIGLOGPAGE ");
3848 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3849 pr_cont("DC_FIDO ");
3854 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3856 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3860 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3861 RX_DMA_CTL_STAT_PORT_FATAL
))
3865 netdev_err(np
->dev
, "RX channel %u error, stat[%llx]\n",
3867 (unsigned long long) stat
);
3869 niu_log_rxchan_errors(np
, rp
, stat
);
3872 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3873 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3878 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3881 netdev_err(np
->dev
, "TX channel %u errors ( ", rp
->tx_channel
);
3883 if (cs
& TX_CS_MBOX_ERR
)
3885 if (cs
& TX_CS_PKT_SIZE_ERR
)
3886 pr_cont("PKT_SIZE ");
3887 if (cs
& TX_CS_TX_RING_OFLOW
)
3888 pr_cont("TX_RING_OFLOW ");
3889 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3890 pr_cont("PREF_BUF_PAR ");
3891 if (cs
& TX_CS_NACK_PREF
)
3892 pr_cont("NACK_PREF ");
3893 if (cs
& TX_CS_NACK_PKT_RD
)
3894 pr_cont("NACK_PKT_RD ");
3895 if (cs
& TX_CS_CONF_PART_ERR
)
3896 pr_cont("CONF_PART ");
3897 if (cs
& TX_CS_PKT_PRT_ERR
)
3898 pr_cont("PKT_PTR ");
3903 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3907 cs
= nr64(TX_CS(rp
->tx_channel
));
3908 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3909 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3911 netdev_err(np
->dev
, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n",
3913 (unsigned long long)cs
,
3914 (unsigned long long)logh
,
3915 (unsigned long long)logl
);
3917 niu_log_txchan_errors(np
, rp
, cs
);
3922 static int niu_mif_interrupt(struct niu
*np
)
3924 u64 mif_status
= nr64(MIF_STATUS
);
3927 if (np
->flags
& NIU_FLAGS_XMAC
) {
3928 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3930 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3934 netdev_err(np
->dev
, "MIF interrupt, stat[%llx] phy_mdint(%d)\n",
3935 (unsigned long long)mif_status
, phy_mdint
);
3940 static void niu_xmac_interrupt(struct niu
*np
)
3942 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3945 val
= nr64_mac(XTXMAC_STATUS
);
3946 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3947 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3948 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3949 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3950 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3951 mp
->tx_fifo_errors
++;
3952 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3953 mp
->tx_overflow_errors
++;
3954 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3955 mp
->tx_max_pkt_size_errors
++;
3956 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3957 mp
->tx_underflow_errors
++;
3959 val
= nr64_mac(XRXMAC_STATUS
);
3960 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3961 mp
->rx_local_faults
++;
3962 if (val
& XRXMAC_STATUS_RFLT_DET
)
3963 mp
->rx_remote_faults
++;
3964 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3965 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3966 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3967 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3968 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3969 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3970 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3971 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3972 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3973 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3974 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
3975 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
3976 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
3977 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
3978 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
3979 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
3980 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
3981 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
3982 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
3983 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
3984 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
3985 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
3986 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
3987 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
3988 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
3989 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
3990 if (val
& XRXMAC_STATUS_RXOCTET_CNT_EXP
)
3991 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
3992 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
3993 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
3994 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
3995 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
3996 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
3997 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
3998 if (val
& XRXMAC_STATUS_RXUFLOW
)
3999 mp
->rx_underflows
++;
4000 if (val
& XRXMAC_STATUS_RXOFLOW
)
4003 val
= nr64_mac(XMAC_FC_STAT
);
4004 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
4005 mp
->pause_off_state
++;
4006 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
4007 mp
->pause_on_state
++;
4008 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
4009 mp
->pause_received
++;
4012 static void niu_bmac_interrupt(struct niu
*np
)
4014 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
4017 val
= nr64_mac(BTXMAC_STATUS
);
4018 if (val
& BTXMAC_STATUS_UNDERRUN
)
4019 mp
->tx_underflow_errors
++;
4020 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
4021 mp
->tx_max_pkt_size_errors
++;
4022 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
4023 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
4024 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
4025 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
4027 val
= nr64_mac(BRXMAC_STATUS
);
4028 if (val
& BRXMAC_STATUS_OVERFLOW
)
4030 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
4031 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
4032 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
4033 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4034 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
4035 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4036 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
4037 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
4039 val
= nr64_mac(BMAC_CTRL_STATUS
);
4040 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
4041 mp
->pause_off_state
++;
4042 if (val
& BMAC_CTRL_STATUS_PAUSE
)
4043 mp
->pause_on_state
++;
4044 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
4045 mp
->pause_received
++;
4048 static int niu_mac_interrupt(struct niu
*np
)
4050 if (np
->flags
& NIU_FLAGS_XMAC
)
4051 niu_xmac_interrupt(np
);
4053 niu_bmac_interrupt(np
);
4058 static void niu_log_device_error(struct niu
*np
, u64 stat
)
4060 netdev_err(np
->dev
, "Core device errors ( ");
4062 if (stat
& SYS_ERR_MASK_META2
)
4064 if (stat
& SYS_ERR_MASK_META1
)
4066 if (stat
& SYS_ERR_MASK_PEU
)
4068 if (stat
& SYS_ERR_MASK_TXC
)
4070 if (stat
& SYS_ERR_MASK_RDMC
)
4072 if (stat
& SYS_ERR_MASK_TDMC
)
4074 if (stat
& SYS_ERR_MASK_ZCP
)
4076 if (stat
& SYS_ERR_MASK_FFLP
)
4078 if (stat
& SYS_ERR_MASK_IPP
)
4080 if (stat
& SYS_ERR_MASK_MAC
)
4082 if (stat
& SYS_ERR_MASK_SMX
)
4088 static int niu_device_error(struct niu
*np
)
4090 u64 stat
= nr64(SYS_ERR_STAT
);
4092 netdev_err(np
->dev
, "Core device error, stat[%llx]\n",
4093 (unsigned long long)stat
);
4095 niu_log_device_error(np
, stat
);
4100 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
4101 u64 v0
, u64 v1
, u64 v2
)
4110 if (v1
& 0x00000000ffffffffULL
) {
4111 u32 rx_vec
= (v1
& 0xffffffff);
4113 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4114 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4116 if (rx_vec
& (1 << rp
->rx_channel
)) {
4117 int r
= niu_rx_error(np
, rp
);
4122 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
4123 RX_DMA_CTL_STAT_MEX
);
4128 if (v1
& 0x7fffffff00000000ULL
) {
4129 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
4131 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4132 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4134 if (tx_vec
& (1 << rp
->tx_channel
)) {
4135 int r
= niu_tx_error(np
, rp
);
4141 if ((v0
| v1
) & 0x8000000000000000ULL
) {
4142 int r
= niu_mif_interrupt(np
);
4148 int r
= niu_mac_interrupt(np
);
4153 int r
= niu_device_error(np
);
4160 niu_enable_interrupts(np
, 0);
4165 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
4168 struct rxdma_mailbox
*mbox
= rp
->mbox
;
4169 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
4171 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
4172 RX_DMA_CTL_STAT_RCRTO
);
4173 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
4175 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4176 "%s() stat[%llx]\n", __func__
, (unsigned long long)stat
);
4179 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
4182 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
4184 netif_printk(np
, intr
, KERN_DEBUG
, np
->dev
,
4185 "%s() cs[%llx]\n", __func__
, (unsigned long long)rp
->tx_cs
);
4188 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
4190 struct niu_parent
*parent
= np
->parent
;
4194 tx_vec
= (v0
>> 32);
4195 rx_vec
= (v0
& 0xffffffff);
4197 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4198 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4199 int ldn
= LDN_RXDMA(rp
->rx_channel
);
4201 if (parent
->ldg_map
[ldn
] != ldg
)
4204 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4205 if (rx_vec
& (1 << rp
->rx_channel
))
4206 niu_rxchan_intr(np
, rp
, ldn
);
4209 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4210 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4211 int ldn
= LDN_TXDMA(rp
->tx_channel
);
4213 if (parent
->ldg_map
[ldn
] != ldg
)
4216 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4217 if (tx_vec
& (1 << rp
->tx_channel
))
4218 niu_txchan_intr(np
, rp
, ldn
);
4222 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
4223 u64 v0
, u64 v1
, u64 v2
)
4225 if (likely(napi_schedule_prep(&lp
->napi
))) {
4229 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
4230 __napi_schedule(&lp
->napi
);
4234 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
4236 struct niu_ldg
*lp
= dev_id
;
4237 struct niu
*np
= lp
->np
;
4238 int ldg
= lp
->ldg_num
;
4239 unsigned long flags
;
4242 if (netif_msg_intr(np
))
4243 printk(KERN_DEBUG KBUILD_MODNAME
": " "%s() ldg[%p](%d)",
4246 spin_lock_irqsave(&np
->lock
, flags
);
4248 v0
= nr64(LDSV0(ldg
));
4249 v1
= nr64(LDSV1(ldg
));
4250 v2
= nr64(LDSV2(ldg
));
4252 if (netif_msg_intr(np
))
4253 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n",
4254 (unsigned long long) v0
,
4255 (unsigned long long) v1
,
4256 (unsigned long long) v2
);
4258 if (unlikely(!v0
&& !v1
&& !v2
)) {
4259 spin_unlock_irqrestore(&np
->lock
, flags
);
4263 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
4264 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
4268 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
4269 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
4271 niu_ldg_rearm(np
, lp
, 1);
4273 spin_unlock_irqrestore(&np
->lock
, flags
);
4278 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
4281 np
->ops
->free_coherent(np
->device
,
4282 sizeof(struct rxdma_mailbox
),
4283 rp
->mbox
, rp
->mbox_dma
);
4287 np
->ops
->free_coherent(np
->device
,
4288 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4289 rp
->rcr
, rp
->rcr_dma
);
4291 rp
->rcr_table_size
= 0;
4295 niu_rbr_free(np
, rp
);
4297 np
->ops
->free_coherent(np
->device
,
4298 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4299 rp
->rbr
, rp
->rbr_dma
);
4301 rp
->rbr_table_size
= 0;
4308 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
4311 np
->ops
->free_coherent(np
->device
,
4312 sizeof(struct txdma_mailbox
),
4313 rp
->mbox
, rp
->mbox_dma
);
4319 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
4320 if (rp
->tx_buffs
[i
].skb
)
4321 (void) release_tx_packet(np
, rp
, i
);
4324 np
->ops
->free_coherent(np
->device
,
4325 MAX_TX_RING_SIZE
* sizeof(__le64
),
4326 rp
->descr
, rp
->descr_dma
);
4335 static void niu_free_channels(struct niu
*np
)
4340 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4341 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4343 niu_free_rx_ring_info(np
, rp
);
4345 kfree(np
->rx_rings
);
4346 np
->rx_rings
= NULL
;
4347 np
->num_rx_rings
= 0;
4351 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4352 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4354 niu_free_tx_ring_info(np
, rp
);
4356 kfree(np
->tx_rings
);
4357 np
->tx_rings
= NULL
;
4358 np
->num_tx_rings
= 0;
4362 static int niu_alloc_rx_ring_info(struct niu
*np
,
4363 struct rx_ring_info
*rp
)
4365 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
4367 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
4372 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4373 sizeof(struct rxdma_mailbox
),
4374 &rp
->mbox_dma
, GFP_KERNEL
);
4377 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4378 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA mailbox %p\n",
4383 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
4384 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4385 &rp
->rcr_dma
, GFP_KERNEL
);
4388 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
4389 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RCR table %p\n",
4393 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
4396 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
4397 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4398 &rp
->rbr_dma
, GFP_KERNEL
);
4401 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
4402 netdev_err(np
->dev
, "Coherent alloc gives misaligned RXDMA RBR table %p\n",
4406 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
4408 rp
->rbr_pending
= 0;
4413 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
4415 int mtu
= np
->dev
->mtu
;
4417 /* These values are recommended by the HW designers for fair
4418 * utilization of DRR amongst the rings.
4420 rp
->max_burst
= mtu
+ 32;
4421 if (rp
->max_burst
> 4096)
4422 rp
->max_burst
= 4096;
4425 static int niu_alloc_tx_ring_info(struct niu
*np
,
4426 struct tx_ring_info
*rp
)
4428 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
4430 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4431 sizeof(struct txdma_mailbox
),
4432 &rp
->mbox_dma
, GFP_KERNEL
);
4435 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4436 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA mailbox %p\n",
4441 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4442 MAX_TX_RING_SIZE
* sizeof(__le64
),
4443 &rp
->descr_dma
, GFP_KERNEL
);
4446 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4447 netdev_err(np
->dev
, "Coherent alloc gives misaligned TXDMA descr table %p\n",
4452 rp
->pending
= MAX_TX_RING_SIZE
;
4457 /* XXX make these configurable... XXX */
4458 rp
->mark_freq
= rp
->pending
/ 4;
4460 niu_set_max_burst(np
, rp
);
4465 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4469 bss
= min(PAGE_SHIFT
, 15);
4471 rp
->rbr_block_size
= 1 << bss
;
4472 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4474 rp
->rbr_sizes
[0] = 256;
4475 rp
->rbr_sizes
[1] = 1024;
4476 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4477 switch (PAGE_SIZE
) {
4479 rp
->rbr_sizes
[2] = 4096;
4483 rp
->rbr_sizes
[2] = 8192;
4487 rp
->rbr_sizes
[2] = 2048;
4489 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4492 static int niu_alloc_channels(struct niu
*np
)
4494 struct niu_parent
*parent
= np
->parent
;
4495 int first_rx_channel
, first_tx_channel
;
4499 first_rx_channel
= first_tx_channel
= 0;
4500 for (i
= 0; i
< port
; i
++) {
4501 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4502 first_tx_channel
+= parent
->txchan_per_port
[i
];
4505 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4506 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4508 np
->dev
->real_num_tx_queues
= np
->num_tx_rings
;
4510 np
->rx_rings
= kzalloc(np
->num_rx_rings
* sizeof(struct rx_ring_info
),
4516 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4517 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4520 rp
->rx_channel
= first_rx_channel
+ i
;
4522 err
= niu_alloc_rx_ring_info(np
, rp
);
4526 niu_size_rbr(np
, rp
);
4528 /* XXX better defaults, configurable, etc... XXX */
4529 rp
->nonsyn_window
= 64;
4530 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4531 rp
->syn_window
= 64;
4532 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4533 rp
->rcr_pkt_threshold
= 16;
4534 rp
->rcr_timeout
= 8;
4535 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4536 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4537 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4539 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4544 np
->tx_rings
= kzalloc(np
->num_tx_rings
* sizeof(struct tx_ring_info
),
4550 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4551 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4554 rp
->tx_channel
= first_tx_channel
+ i
;
4556 err
= niu_alloc_tx_ring_info(np
, rp
);
4564 niu_free_channels(np
);
4568 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4572 while (--limit
> 0) {
4573 u64 val
= nr64(TX_CS(channel
));
4574 if (val
& TX_CS_SNG_STATE
)
4580 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4582 u64 val
= nr64(TX_CS(channel
));
4584 val
|= TX_CS_STOP_N_GO
;
4585 nw64(TX_CS(channel
), val
);
4587 return niu_tx_cs_sng_poll(np
, channel
);
4590 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4594 while (--limit
> 0) {
4595 u64 val
= nr64(TX_CS(channel
));
4596 if (!(val
& TX_CS_RST
))
4602 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4604 u64 val
= nr64(TX_CS(channel
));
4608 nw64(TX_CS(channel
), val
);
4610 err
= niu_tx_cs_reset_poll(np
, channel
);
4612 nw64(TX_RING_KICK(channel
), 0);
4617 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4621 nw64(TX_LOG_MASK1(channel
), 0);
4622 nw64(TX_LOG_VAL1(channel
), 0);
4623 nw64(TX_LOG_MASK2(channel
), 0);
4624 nw64(TX_LOG_VAL2(channel
), 0);
4625 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4626 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4627 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4629 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4630 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4631 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4633 /* XXX TXDMA 32bit mode? XXX */
4638 static void niu_txc_enable_port(struct niu
*np
, int on
)
4640 unsigned long flags
;
4643 niu_lock_parent(np
, flags
);
4644 val
= nr64(TXC_CONTROL
);
4645 mask
= (u64
)1 << np
->port
;
4647 val
|= TXC_CONTROL_ENABLE
| mask
;
4650 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4651 val
&= ~TXC_CONTROL_ENABLE
;
4653 nw64(TXC_CONTROL
, val
);
4654 niu_unlock_parent(np
, flags
);
4657 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4659 unsigned long flags
;
4662 niu_lock_parent(np
, flags
);
4663 val
= nr64(TXC_INT_MASK
);
4664 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4665 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4666 niu_unlock_parent(np
, flags
);
4669 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4676 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4677 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4679 nw64(TXC_PORT_DMA(np
->port
), val
);
4682 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4684 int err
, channel
= rp
->tx_channel
;
4687 err
= niu_tx_channel_stop(np
, channel
);
4691 err
= niu_tx_channel_reset(np
, channel
);
4695 err
= niu_tx_channel_lpage_init(np
, channel
);
4699 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4700 nw64(TX_ENT_MSK(channel
), 0);
4702 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4703 TX_RNG_CFIG_STADDR
)) {
4704 netdev_err(np
->dev
, "TX ring channel %d DMA addr (%llx) is not aligned\n",
4705 channel
, (unsigned long long)rp
->descr_dma
);
4709 /* The length field in TX_RNG_CFIG is measured in 64-byte
4710 * blocks. rp->pending is the number of TX descriptors in
4711 * our ring, 8 bytes each, thus we divide by 8 bytes more
4712 * to get the proper value the chip wants.
4714 ring_len
= (rp
->pending
/ 8);
4716 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4718 nw64(TX_RNG_CFIG(channel
), val
);
4720 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4721 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4722 netdev_err(np
->dev
, "TX ring channel %d MBOX addr (%llx) has invalid bits\n",
4723 channel
, (unsigned long long)rp
->mbox_dma
);
4726 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4727 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4729 nw64(TX_CS(channel
), 0);
4731 rp
->last_pkt_cnt
= 0;
4736 static void niu_init_rdc_groups(struct niu
*np
)
4738 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4739 int i
, first_table_num
= tp
->first_table_num
;
4741 for (i
= 0; i
< tp
->num_tables
; i
++) {
4742 struct rdc_table
*tbl
= &tp
->tables
[i
];
4743 int this_table
= first_table_num
+ i
;
4746 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4747 nw64(RDC_TBL(this_table
, slot
),
4748 tbl
->rxdma_channel
[slot
]);
4751 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4754 static void niu_init_drr_weight(struct niu
*np
)
4756 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4761 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4766 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4769 nw64(PT_DRR_WT(np
->port
), val
);
4772 static int niu_init_hostinfo(struct niu
*np
)
4774 struct niu_parent
*parent
= np
->parent
;
4775 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4776 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4777 int first_rdc_table
= tp
->first_table_num
;
4779 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4783 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4787 for (i
= 0; i
< num_alt
; i
++) {
4788 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4796 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4798 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4799 RXDMA_CFIG1_RST
, 1000, 10,
4803 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4807 nw64(RX_LOG_MASK1(channel
), 0);
4808 nw64(RX_LOG_VAL1(channel
), 0);
4809 nw64(RX_LOG_MASK2(channel
), 0);
4810 nw64(RX_LOG_VAL2(channel
), 0);
4811 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4812 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4813 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4815 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4816 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4817 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4822 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4826 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4827 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4828 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4829 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4830 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4833 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4838 switch (rp
->rbr_block_size
) {
4840 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4843 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4846 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4849 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4854 val
|= RBR_CFIG_B_VLD2
;
4855 switch (rp
->rbr_sizes
[2]) {
4857 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4860 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4863 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4866 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4872 val
|= RBR_CFIG_B_VLD1
;
4873 switch (rp
->rbr_sizes
[1]) {
4875 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4878 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4881 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4884 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4890 val
|= RBR_CFIG_B_VLD0
;
4891 switch (rp
->rbr_sizes
[0]) {
4893 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4896 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4899 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4902 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4913 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4915 u64 val
= nr64(RXDMA_CFIG1(channel
));
4919 val
|= RXDMA_CFIG1_EN
;
4921 val
&= ~RXDMA_CFIG1_EN
;
4922 nw64(RXDMA_CFIG1(channel
), val
);
4925 while (--limit
> 0) {
4926 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4935 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4937 int err
, channel
= rp
->rx_channel
;
4940 err
= niu_rx_channel_reset(np
, channel
);
4944 err
= niu_rx_channel_lpage_init(np
, channel
);
4948 niu_rx_channel_wred_init(np
, rp
);
4950 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4951 nw64(RX_DMA_CTL_STAT(channel
),
4952 (RX_DMA_CTL_STAT_MEX
|
4953 RX_DMA_CTL_STAT_RCRTHRES
|
4954 RX_DMA_CTL_STAT_RCRTO
|
4955 RX_DMA_CTL_STAT_RBR_EMPTY
));
4956 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4957 nw64(RXDMA_CFIG2(channel
),
4958 ((rp
->mbox_dma
& RXDMA_CFIG2_MBADDR_L
) |
4959 RXDMA_CFIG2_FULL_HDR
));
4960 nw64(RBR_CFIG_A(channel
),
4961 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4962 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4963 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4966 nw64(RBR_CFIG_B(channel
), val
);
4967 nw64(RCRCFIG_A(channel
),
4968 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4969 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
4970 nw64(RCRCFIG_B(channel
),
4971 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
4973 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
4975 err
= niu_enable_rx_channel(np
, channel
, 1);
4979 nw64(RBR_KICK(channel
), rp
->rbr_index
);
4981 val
= nr64(RX_DMA_CTL_STAT(channel
));
4982 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
4983 nw64(RX_DMA_CTL_STAT(channel
), val
);
4988 static int niu_init_rx_channels(struct niu
*np
)
4990 unsigned long flags
;
4991 u64 seed
= jiffies_64
;
4994 niu_lock_parent(np
, flags
);
4995 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
4996 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
4997 niu_unlock_parent(np
, flags
);
4999 /* XXX RXDMA 32bit mode? XXX */
5001 niu_init_rdc_groups(np
);
5002 niu_init_drr_weight(np
);
5004 err
= niu_init_hostinfo(np
);
5008 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5009 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5011 err
= niu_init_one_rx_channel(np
, rp
);
5019 static int niu_set_ip_frag_rule(struct niu
*np
)
5021 struct niu_parent
*parent
= np
->parent
;
5022 struct niu_classifier
*cp
= &np
->clas
;
5023 struct niu_tcam_entry
*tp
;
5026 index
= cp
->tcam_top
;
5027 tp
= &parent
->tcam
[index
];
5029 /* Note that the noport bit is the same in both ipv4 and
5030 * ipv6 format TCAM entries.
5032 memset(tp
, 0, sizeof(*tp
));
5033 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
5034 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
5035 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
5036 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
5037 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
5040 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
5044 cp
->tcam_valid_entries
++;
5049 static int niu_init_classifier_hw(struct niu
*np
)
5051 struct niu_parent
*parent
= np
->parent
;
5052 struct niu_classifier
*cp
= &np
->clas
;
5055 nw64(H1POLY
, cp
->h1_init
);
5056 nw64(H2POLY
, cp
->h2_init
);
5058 err
= niu_init_hostinfo(np
);
5062 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
5063 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
5065 vlan_tbl_write(np
, i
, np
->port
,
5066 vp
->vlan_pref
, vp
->rdc_num
);
5069 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
5070 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
5072 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
5073 ap
->rdc_num
, ap
->mac_pref
);
5078 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
5079 int index
= i
- CLASS_CODE_USER_PROG1
;
5081 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
5084 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
5089 err
= niu_set_ip_frag_rule(np
);
5098 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
5100 nw64(ZCP_RAM_DATA0
, data
[0]);
5101 nw64(ZCP_RAM_DATA1
, data
[1]);
5102 nw64(ZCP_RAM_DATA2
, data
[2]);
5103 nw64(ZCP_RAM_DATA3
, data
[3]);
5104 nw64(ZCP_RAM_DATA4
, data
[4]);
5105 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
5107 (ZCP_RAM_ACC_WRITE
|
5108 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5109 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5111 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5115 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
5119 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5122 netdev_err(np
->dev
, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n",
5123 (unsigned long long)nr64(ZCP_RAM_ACC
));
5129 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5130 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5132 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5135 netdev_err(np
->dev
, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n",
5136 (unsigned long long)nr64(ZCP_RAM_ACC
));
5140 data
[0] = nr64(ZCP_RAM_DATA0
);
5141 data
[1] = nr64(ZCP_RAM_DATA1
);
5142 data
[2] = nr64(ZCP_RAM_DATA2
);
5143 data
[3] = nr64(ZCP_RAM_DATA3
);
5144 data
[4] = nr64(ZCP_RAM_DATA4
);
5149 static void niu_zcp_cfifo_reset(struct niu
*np
)
5151 u64 val
= nr64(RESET_CFIFO
);
5153 val
|= RESET_CFIFO_RST(np
->port
);
5154 nw64(RESET_CFIFO
, val
);
5157 val
&= ~RESET_CFIFO_RST(np
->port
);
5158 nw64(RESET_CFIFO
, val
);
5161 static int niu_init_zcp(struct niu
*np
)
5163 u64 data
[5], rbuf
[5];
5166 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5167 if (np
->port
== 0 || np
->port
== 1)
5168 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
5170 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
5172 max
= NIU_CFIFO_ENTRIES
;
5180 for (i
= 0; i
< max
; i
++) {
5181 err
= niu_zcp_write(np
, i
, data
);
5184 err
= niu_zcp_read(np
, i
, rbuf
);
5189 niu_zcp_cfifo_reset(np
);
5190 nw64(CFIFO_ECC(np
->port
), 0);
5191 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
5192 (void) nr64(ZCP_INT_STAT
);
5193 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
5198 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
5200 u64 val
= nr64_ipp(IPP_CFIG
);
5202 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
5203 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
5204 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
5205 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
5206 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
5207 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
5208 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
5209 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
5212 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
5214 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
5215 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
5216 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
5217 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
5218 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
5219 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
5222 static int niu_ipp_reset(struct niu
*np
)
5224 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
5225 1000, 100, "IPP_CFIG");
5228 static int niu_init_ipp(struct niu
*np
)
5230 u64 data
[5], rbuf
[5], val
;
5233 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5234 if (np
->port
== 0 || np
->port
== 1)
5235 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
5237 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
5239 max
= NIU_DFIFO_ENTRIES
;
5247 for (i
= 0; i
< max
; i
++) {
5248 niu_ipp_write(np
, i
, data
);
5249 niu_ipp_read(np
, i
, rbuf
);
5252 (void) nr64_ipp(IPP_INT_STAT
);
5253 (void) nr64_ipp(IPP_INT_STAT
);
5255 err
= niu_ipp_reset(np
);
5259 (void) nr64_ipp(IPP_PKT_DIS
);
5260 (void) nr64_ipp(IPP_BAD_CS_CNT
);
5261 (void) nr64_ipp(IPP_ECC
);
5263 (void) nr64_ipp(IPP_INT_STAT
);
5265 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
5267 val
= nr64_ipp(IPP_CFIG
);
5268 val
&= ~IPP_CFIG_IP_MAX_PKT
;
5269 val
|= (IPP_CFIG_IPP_ENABLE
|
5270 IPP_CFIG_DFIFO_ECC_EN
|
5271 IPP_CFIG_DROP_BAD_CRC
|
5273 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
5274 nw64_ipp(IPP_CFIG
, val
);
5279 static void niu_handle_led(struct niu
*np
, int status
)
5282 val
= nr64_mac(XMAC_CONFIG
);
5284 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
5285 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
5287 val
|= XMAC_CONFIG_LED_POLARITY
;
5288 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
5290 val
|= XMAC_CONFIG_FORCE_LED_ON
;
5291 val
&= ~XMAC_CONFIG_LED_POLARITY
;
5295 nw64_mac(XMAC_CONFIG
, val
);
5298 static void niu_init_xif_xmac(struct niu
*np
)
5300 struct niu_link_config
*lp
= &np
->link_config
;
5303 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
5304 val
= nr64(MIF_CONFIG
);
5305 val
|= MIF_CONFIG_ATCA_GE
;
5306 nw64(MIF_CONFIG
, val
);
5309 val
= nr64_mac(XMAC_CONFIG
);
5310 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5312 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
5314 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
5315 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5316 val
|= XMAC_CONFIG_LOOPBACK
;
5318 val
&= ~XMAC_CONFIG_LOOPBACK
;
5321 if (np
->flags
& NIU_FLAGS_10G
) {
5322 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
5324 val
|= XMAC_CONFIG_LFS_DISABLE
;
5325 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
5326 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
5327 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
5329 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
5332 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5334 if (lp
->active_speed
== SPEED_100
)
5335 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
5337 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
5339 nw64_mac(XMAC_CONFIG
, val
);
5341 val
= nr64_mac(XMAC_CONFIG
);
5342 val
&= ~XMAC_CONFIG_MODE_MASK
;
5343 if (np
->flags
& NIU_FLAGS_10G
) {
5344 val
|= XMAC_CONFIG_MODE_XGMII
;
5346 if (lp
->active_speed
== SPEED_1000
)
5347 val
|= XMAC_CONFIG_MODE_GMII
;
5349 val
|= XMAC_CONFIG_MODE_MII
;
5352 nw64_mac(XMAC_CONFIG
, val
);
5355 static void niu_init_xif_bmac(struct niu
*np
)
5357 struct niu_link_config
*lp
= &np
->link_config
;
5360 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
5362 if (lp
->loopback_mode
== LOOPBACK_MAC
)
5363 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
5365 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
5367 if (lp
->active_speed
== SPEED_1000
)
5368 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
5370 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
5372 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
5373 BMAC_XIF_CONFIG_LED_POLARITY
);
5375 if (!(np
->flags
& NIU_FLAGS_10G
) &&
5376 !(np
->flags
& NIU_FLAGS_FIBER
) &&
5377 lp
->active_speed
== SPEED_100
)
5378 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5380 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5382 nw64_mac(BMAC_XIF_CONFIG
, val
);
5385 static void niu_init_xif(struct niu
*np
)
5387 if (np
->flags
& NIU_FLAGS_XMAC
)
5388 niu_init_xif_xmac(np
);
5390 niu_init_xif_bmac(np
);
5393 static void niu_pcs_mii_reset(struct niu
*np
)
5396 u64 val
= nr64_pcs(PCS_MII_CTL
);
5397 val
|= PCS_MII_CTL_RST
;
5398 nw64_pcs(PCS_MII_CTL
, val
);
5399 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
5401 val
= nr64_pcs(PCS_MII_CTL
);
5405 static void niu_xpcs_reset(struct niu
*np
)
5408 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
5409 val
|= XPCS_CONTROL1_RESET
;
5410 nw64_xpcs(XPCS_CONTROL1
, val
);
5411 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
5413 val
= nr64_xpcs(XPCS_CONTROL1
);
5417 static int niu_init_pcs(struct niu
*np
)
5419 struct niu_link_config
*lp
= &np
->link_config
;
5422 switch (np
->flags
& (NIU_FLAGS_10G
|
5424 NIU_FLAGS_XCVR_SERDES
)) {
5425 case NIU_FLAGS_FIBER
:
5427 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5428 nw64_pcs(PCS_DPATH_MODE
, 0);
5429 niu_pcs_mii_reset(np
);
5433 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
5434 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
5436 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5439 /* 10G copper or fiber */
5440 val
= nr64_mac(XMAC_CONFIG
);
5441 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5442 nw64_mac(XMAC_CONFIG
, val
);
5446 val
= nr64_xpcs(XPCS_CONTROL1
);
5447 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5448 val
|= XPCS_CONTROL1_LOOPBACK
;
5450 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5451 nw64_xpcs(XPCS_CONTROL1
, val
);
5453 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5454 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5455 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5459 case NIU_FLAGS_XCVR_SERDES
:
5461 niu_pcs_mii_reset(np
);
5462 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5463 nw64_pcs(PCS_DPATH_MODE
, 0);
5468 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5469 /* 1G RGMII FIBER */
5470 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5471 niu_pcs_mii_reset(np
);
5481 static int niu_reset_tx_xmac(struct niu
*np
)
5483 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5484 (XTXMAC_SW_RST_REG_RS
|
5485 XTXMAC_SW_RST_SOFT_RST
),
5486 1000, 100, "XTXMAC_SW_RST");
5489 static int niu_reset_tx_bmac(struct niu
*np
)
5493 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5495 while (--limit
>= 0) {
5496 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5501 dev_err(np
->device
, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n",
5503 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5510 static int niu_reset_tx_mac(struct niu
*np
)
5512 if (np
->flags
& NIU_FLAGS_XMAC
)
5513 return niu_reset_tx_xmac(np
);
5515 return niu_reset_tx_bmac(np
);
5518 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5522 val
= nr64_mac(XMAC_MIN
);
5523 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5524 XMAC_MIN_RX_MIN_PKT_SIZE
);
5525 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5526 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5527 nw64_mac(XMAC_MIN
, val
);
5529 nw64_mac(XMAC_MAX
, max
);
5531 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5533 val
= nr64_mac(XMAC_IPG
);
5534 if (np
->flags
& NIU_FLAGS_10G
) {
5535 val
&= ~XMAC_IPG_IPG_XGMII
;
5536 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5538 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5539 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5541 nw64_mac(XMAC_IPG
, val
);
5543 val
= nr64_mac(XMAC_CONFIG
);
5544 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5545 XMAC_CONFIG_STRETCH_MODE
|
5546 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5547 XMAC_CONFIG_TX_ENABLE
);
5548 nw64_mac(XMAC_CONFIG
, val
);
5550 nw64_mac(TXMAC_FRM_CNT
, 0);
5551 nw64_mac(TXMAC_BYTE_CNT
, 0);
5554 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5558 nw64_mac(BMAC_MIN_FRAME
, min
);
5559 nw64_mac(BMAC_MAX_FRAME
, max
);
5561 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5562 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5563 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5565 val
= nr64_mac(BTXMAC_CONFIG
);
5566 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5567 BTXMAC_CONFIG_ENABLE
);
5568 nw64_mac(BTXMAC_CONFIG
, val
);
5571 static void niu_init_tx_mac(struct niu
*np
)
5576 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5581 /* The XMAC_MIN register only accepts values for TX min which
5582 * have the low 3 bits cleared.
5586 if (np
->flags
& NIU_FLAGS_XMAC
)
5587 niu_init_tx_xmac(np
, min
, max
);
5589 niu_init_tx_bmac(np
, min
, max
);
5592 static int niu_reset_rx_xmac(struct niu
*np
)
5596 nw64_mac(XRXMAC_SW_RST
,
5597 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5599 while (--limit
>= 0) {
5600 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5601 XRXMAC_SW_RST_SOFT_RST
)))
5606 dev_err(np
->device
, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n",
5608 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5615 static int niu_reset_rx_bmac(struct niu
*np
)
5619 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5621 while (--limit
>= 0) {
5622 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5627 dev_err(np
->device
, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n",
5629 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5636 static int niu_reset_rx_mac(struct niu
*np
)
5638 if (np
->flags
& NIU_FLAGS_XMAC
)
5639 return niu_reset_rx_xmac(np
);
5641 return niu_reset_rx_bmac(np
);
5644 static void niu_init_rx_xmac(struct niu
*np
)
5646 struct niu_parent
*parent
= np
->parent
;
5647 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5648 int first_rdc_table
= tp
->first_table_num
;
5652 nw64_mac(XMAC_ADD_FILT0
, 0);
5653 nw64_mac(XMAC_ADD_FILT1
, 0);
5654 nw64_mac(XMAC_ADD_FILT2
, 0);
5655 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5656 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5657 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5658 nw64_mac(XMAC_HASH_TBL(i
), 0);
5659 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5660 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5661 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5663 val
= nr64_mac(XMAC_CONFIG
);
5664 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5665 XMAC_CONFIG_PROMISCUOUS
|
5666 XMAC_CONFIG_PROMISC_GROUP
|
5667 XMAC_CONFIG_ERR_CHK_DIS
|
5668 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5669 XMAC_CONFIG_RESERVED_MULTICAST
|
5670 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5671 XMAC_CONFIG_ADDR_FILTER_EN
|
5672 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5673 XMAC_CONFIG_STRIP_CRC
|
5674 XMAC_CONFIG_PASS_FLOW_CTRL
|
5675 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5676 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5677 nw64_mac(XMAC_CONFIG
, val
);
5679 nw64_mac(RXMAC_BT_CNT
, 0);
5680 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5681 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5682 nw64_mac(RXMAC_FRAG_CNT
, 0);
5683 nw64_mac(RXMAC_HIST_CNT1
, 0);
5684 nw64_mac(RXMAC_HIST_CNT2
, 0);
5685 nw64_mac(RXMAC_HIST_CNT3
, 0);
5686 nw64_mac(RXMAC_HIST_CNT4
, 0);
5687 nw64_mac(RXMAC_HIST_CNT5
, 0);
5688 nw64_mac(RXMAC_HIST_CNT6
, 0);
5689 nw64_mac(RXMAC_HIST_CNT7
, 0);
5690 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5691 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5692 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5693 nw64_mac(LINK_FAULT_CNT
, 0);
5696 static void niu_init_rx_bmac(struct niu
*np
)
5698 struct niu_parent
*parent
= np
->parent
;
5699 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5700 int first_rdc_table
= tp
->first_table_num
;
5704 nw64_mac(BMAC_ADD_FILT0
, 0);
5705 nw64_mac(BMAC_ADD_FILT1
, 0);
5706 nw64_mac(BMAC_ADD_FILT2
, 0);
5707 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5708 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5709 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5710 nw64_mac(BMAC_HASH_TBL(i
), 0);
5711 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5712 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5713 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5715 val
= nr64_mac(BRXMAC_CONFIG
);
5716 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5717 BRXMAC_CONFIG_STRIP_PAD
|
5718 BRXMAC_CONFIG_STRIP_FCS
|
5719 BRXMAC_CONFIG_PROMISC
|
5720 BRXMAC_CONFIG_PROMISC_GRP
|
5721 BRXMAC_CONFIG_ADDR_FILT_EN
|
5722 BRXMAC_CONFIG_DISCARD_DIS
);
5723 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5724 nw64_mac(BRXMAC_CONFIG
, val
);
5726 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5727 val
|= BMAC_ADDR_CMPEN_EN0
;
5728 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5731 static void niu_init_rx_mac(struct niu
*np
)
5733 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5735 if (np
->flags
& NIU_FLAGS_XMAC
)
5736 niu_init_rx_xmac(np
);
5738 niu_init_rx_bmac(np
);
5741 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5743 u64 val
= nr64_mac(XMAC_CONFIG
);
5746 val
|= XMAC_CONFIG_TX_ENABLE
;
5748 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5749 nw64_mac(XMAC_CONFIG
, val
);
5752 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5754 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5757 val
|= BTXMAC_CONFIG_ENABLE
;
5759 val
&= ~BTXMAC_CONFIG_ENABLE
;
5760 nw64_mac(BTXMAC_CONFIG
, val
);
5763 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5765 if (np
->flags
& NIU_FLAGS_XMAC
)
5766 niu_enable_tx_xmac(np
, on
);
5768 niu_enable_tx_bmac(np
, on
);
5771 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5773 u64 val
= nr64_mac(XMAC_CONFIG
);
5775 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5776 XMAC_CONFIG_PROMISCUOUS
);
5778 if (np
->flags
& NIU_FLAGS_MCAST
)
5779 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5780 if (np
->flags
& NIU_FLAGS_PROMISC
)
5781 val
|= XMAC_CONFIG_PROMISCUOUS
;
5784 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5786 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5787 nw64_mac(XMAC_CONFIG
, val
);
5790 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5792 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5794 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5795 BRXMAC_CONFIG_PROMISC
);
5797 if (np
->flags
& NIU_FLAGS_MCAST
)
5798 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5799 if (np
->flags
& NIU_FLAGS_PROMISC
)
5800 val
|= BRXMAC_CONFIG_PROMISC
;
5803 val
|= BRXMAC_CONFIG_ENABLE
;
5805 val
&= ~BRXMAC_CONFIG_ENABLE
;
5806 nw64_mac(BRXMAC_CONFIG
, val
);
5809 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5811 if (np
->flags
& NIU_FLAGS_XMAC
)
5812 niu_enable_rx_xmac(np
, on
);
5814 niu_enable_rx_bmac(np
, on
);
5817 static int niu_init_mac(struct niu
*np
)
5822 err
= niu_init_pcs(np
);
5826 err
= niu_reset_tx_mac(np
);
5829 niu_init_tx_mac(np
);
5830 err
= niu_reset_rx_mac(np
);
5833 niu_init_rx_mac(np
);
5835 /* This looks hookey but the RX MAC reset we just did will
5836 * undo some of the state we setup in niu_init_tx_mac() so we
5837 * have to call it again. In particular, the RX MAC reset will
5838 * set the XMAC_MAX register back to it's default value.
5840 niu_init_tx_mac(np
);
5841 niu_enable_tx_mac(np
, 1);
5843 niu_enable_rx_mac(np
, 1);
5848 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5850 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5853 static void niu_stop_tx_channels(struct niu
*np
)
5857 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5858 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5860 niu_stop_one_tx_channel(np
, rp
);
5864 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5866 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5869 static void niu_reset_tx_channels(struct niu
*np
)
5873 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5874 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5876 niu_reset_one_tx_channel(np
, rp
);
5880 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5882 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5885 static void niu_stop_rx_channels(struct niu
*np
)
5889 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5890 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5892 niu_stop_one_rx_channel(np
, rp
);
5896 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5898 int channel
= rp
->rx_channel
;
5900 (void) niu_rx_channel_reset(np
, channel
);
5901 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5902 nw64(RX_DMA_CTL_STAT(channel
), 0);
5903 (void) niu_enable_rx_channel(np
, channel
, 0);
5906 static void niu_reset_rx_channels(struct niu
*np
)
5910 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5911 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5913 niu_reset_one_rx_channel(np
, rp
);
5917 static void niu_disable_ipp(struct niu
*np
)
5922 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5923 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5925 while (--limit
>= 0 && (rd
!= wr
)) {
5926 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5927 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5930 (rd
!= 0 && wr
!= 1)) {
5931 netdev_err(np
->dev
, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n",
5932 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR
),
5933 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR
));
5936 val
= nr64_ipp(IPP_CFIG
);
5937 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5938 IPP_CFIG_DFIFO_ECC_EN
|
5939 IPP_CFIG_DROP_BAD_CRC
|
5941 nw64_ipp(IPP_CFIG
, val
);
5943 (void) niu_ipp_reset(np
);
5946 static int niu_init_hw(struct niu
*np
)
5950 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TXC\n");
5951 niu_txc_enable_port(np
, 1);
5952 niu_txc_port_dma_enable(np
, 1);
5953 niu_txc_set_imask(np
, 0);
5955 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize TX channels\n");
5956 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5957 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5959 err
= niu_init_one_tx_channel(np
, rp
);
5964 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize RX channels\n");
5965 err
= niu_init_rx_channels(np
);
5967 goto out_uninit_tx_channels
;
5969 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize classifier\n");
5970 err
= niu_init_classifier_hw(np
);
5972 goto out_uninit_rx_channels
;
5974 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize ZCP\n");
5975 err
= niu_init_zcp(np
);
5977 goto out_uninit_rx_channels
;
5979 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize IPP\n");
5980 err
= niu_init_ipp(np
);
5982 goto out_uninit_rx_channels
;
5984 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Initialize MAC\n");
5985 err
= niu_init_mac(np
);
5987 goto out_uninit_ipp
;
5992 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit IPP\n");
5993 niu_disable_ipp(np
);
5995 out_uninit_rx_channels
:
5996 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit RX channels\n");
5997 niu_stop_rx_channels(np
);
5998 niu_reset_rx_channels(np
);
6000 out_uninit_tx_channels
:
6001 netif_printk(np
, ifup
, KERN_DEBUG
, np
->dev
, "Uninit TX channels\n");
6002 niu_stop_tx_channels(np
);
6003 niu_reset_tx_channels(np
);
6008 static void niu_stop_hw(struct niu
*np
)
6010 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable interrupts\n");
6011 niu_enable_interrupts(np
, 0);
6013 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable RX MAC\n");
6014 niu_enable_rx_mac(np
, 0);
6016 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Disable IPP\n");
6017 niu_disable_ipp(np
);
6019 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop TX channels\n");
6020 niu_stop_tx_channels(np
);
6022 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Stop RX channels\n");
6023 niu_stop_rx_channels(np
);
6025 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset TX channels\n");
6026 niu_reset_tx_channels(np
);
6028 netif_printk(np
, ifdown
, KERN_DEBUG
, np
->dev
, "Reset RX channels\n");
6029 niu_reset_rx_channels(np
);
6032 static void niu_set_irq_name(struct niu
*np
)
6034 int port
= np
->port
;
6037 sprintf(np
->irq_name
[0], "%s:MAC", np
->dev
->name
);
6040 sprintf(np
->irq_name
[1], "%s:MIF", np
->dev
->name
);
6041 sprintf(np
->irq_name
[2], "%s:SYSERR", np
->dev
->name
);
6045 for (i
= 0; i
< np
->num_ldg
- j
; i
++) {
6046 if (i
< np
->num_rx_rings
)
6047 sprintf(np
->irq_name
[i
+j
], "%s-rx-%d",
6049 else if (i
< np
->num_tx_rings
+ np
->num_rx_rings
)
6050 sprintf(np
->irq_name
[i
+j
], "%s-tx-%d", np
->dev
->name
,
6051 i
- np
->num_rx_rings
);
6055 static int niu_request_irq(struct niu
*np
)
6059 niu_set_irq_name(np
);
6062 for (i
= 0; i
< np
->num_ldg
; i
++) {
6063 struct niu_ldg
*lp
= &np
->ldg
[i
];
6065 err
= request_irq(lp
->irq
, niu_interrupt
,
6066 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
6067 np
->irq_name
[i
], lp
);
6076 for (j
= 0; j
< i
; j
++) {
6077 struct niu_ldg
*lp
= &np
->ldg
[j
];
6079 free_irq(lp
->irq
, lp
);
6084 static void niu_free_irq(struct niu
*np
)
6088 for (i
= 0; i
< np
->num_ldg
; i
++) {
6089 struct niu_ldg
*lp
= &np
->ldg
[i
];
6091 free_irq(lp
->irq
, lp
);
6095 static void niu_enable_napi(struct niu
*np
)
6099 for (i
= 0; i
< np
->num_ldg
; i
++)
6100 napi_enable(&np
->ldg
[i
].napi
);
6103 static void niu_disable_napi(struct niu
*np
)
6107 for (i
= 0; i
< np
->num_ldg
; i
++)
6108 napi_disable(&np
->ldg
[i
].napi
);
6111 static int niu_open(struct net_device
*dev
)
6113 struct niu
*np
= netdev_priv(dev
);
6116 netif_carrier_off(dev
);
6118 err
= niu_alloc_channels(np
);
6122 err
= niu_enable_interrupts(np
, 0);
6124 goto out_free_channels
;
6126 err
= niu_request_irq(np
);
6128 goto out_free_channels
;
6130 niu_enable_napi(np
);
6132 spin_lock_irq(&np
->lock
);
6134 err
= niu_init_hw(np
);
6136 init_timer(&np
->timer
);
6137 np
->timer
.expires
= jiffies
+ HZ
;
6138 np
->timer
.data
= (unsigned long) np
;
6139 np
->timer
.function
= niu_timer
;
6141 err
= niu_enable_interrupts(np
, 1);
6146 spin_unlock_irq(&np
->lock
);
6149 niu_disable_napi(np
);
6153 netif_tx_start_all_queues(dev
);
6155 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6156 netif_carrier_on(dev
);
6158 add_timer(&np
->timer
);
6166 niu_free_channels(np
);
6172 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
6174 cancel_work_sync(&np
->reset_task
);
6176 niu_disable_napi(np
);
6177 netif_tx_stop_all_queues(dev
);
6179 del_timer_sync(&np
->timer
);
6181 spin_lock_irq(&np
->lock
);
6185 spin_unlock_irq(&np
->lock
);
6188 static int niu_close(struct net_device
*dev
)
6190 struct niu
*np
= netdev_priv(dev
);
6192 niu_full_shutdown(np
, dev
);
6196 niu_free_channels(np
);
6198 niu_handle_led(np
, 0);
6203 static void niu_sync_xmac_stats(struct niu
*np
)
6205 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
6207 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
6208 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
6210 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
6211 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
6212 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
6213 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
6214 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
6215 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
6216 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
6217 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
6218 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
6219 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
6220 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
6221 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
6222 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
6223 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
6224 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
6225 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
6228 static void niu_sync_bmac_stats(struct niu
*np
)
6230 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
6232 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
6233 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
6235 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
6236 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6237 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6238 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
6241 static void niu_sync_mac_stats(struct niu
*np
)
6243 if (np
->flags
& NIU_FLAGS_XMAC
)
6244 niu_sync_xmac_stats(np
);
6246 niu_sync_bmac_stats(np
);
6249 static void niu_get_rx_stats(struct niu
*np
)
6251 unsigned long pkts
, dropped
, errors
, bytes
;
6254 pkts
= dropped
= errors
= bytes
= 0;
6255 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6256 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6258 niu_sync_rx_discard_stats(np
, rp
, 0);
6260 pkts
+= rp
->rx_packets
;
6261 bytes
+= rp
->rx_bytes
;
6262 dropped
+= rp
->rx_dropped
;
6263 errors
+= rp
->rx_errors
;
6265 np
->dev
->stats
.rx_packets
= pkts
;
6266 np
->dev
->stats
.rx_bytes
= bytes
;
6267 np
->dev
->stats
.rx_dropped
= dropped
;
6268 np
->dev
->stats
.rx_errors
= errors
;
6271 static void niu_get_tx_stats(struct niu
*np
)
6273 unsigned long pkts
, errors
, bytes
;
6276 pkts
= errors
= bytes
= 0;
6277 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6278 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6280 pkts
+= rp
->tx_packets
;
6281 bytes
+= rp
->tx_bytes
;
6282 errors
+= rp
->tx_errors
;
6284 np
->dev
->stats
.tx_packets
= pkts
;
6285 np
->dev
->stats
.tx_bytes
= bytes
;
6286 np
->dev
->stats
.tx_errors
= errors
;
6289 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
6291 struct niu
*np
= netdev_priv(dev
);
6293 niu_get_rx_stats(np
);
6294 niu_get_tx_stats(np
);
6299 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
6303 for (i
= 0; i
< 16; i
++)
6304 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
6307 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
6311 for (i
= 0; i
< 16; i
++)
6312 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
6315 static void niu_load_hash(struct niu
*np
, u16
*hash
)
6317 if (np
->flags
& NIU_FLAGS_XMAC
)
6318 niu_load_hash_xmac(np
, hash
);
6320 niu_load_hash_bmac(np
, hash
);
6323 static void niu_set_rx_mode(struct net_device
*dev
)
6325 struct niu
*np
= netdev_priv(dev
);
6326 int i
, alt_cnt
, err
;
6327 struct netdev_hw_addr
*ha
;
6328 unsigned long flags
;
6329 u16 hash
[16] = { 0, };
6331 spin_lock_irqsave(&np
->lock
, flags
);
6332 niu_enable_rx_mac(np
, 0);
6334 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
6335 if (dev
->flags
& IFF_PROMISC
)
6336 np
->flags
|= NIU_FLAGS_PROMISC
;
6337 if ((dev
->flags
& IFF_ALLMULTI
) || (!netdev_mc_empty(dev
)))
6338 np
->flags
|= NIU_FLAGS_MCAST
;
6340 alt_cnt
= netdev_uc_count(dev
);
6341 if (alt_cnt
> niu_num_alt_addr(np
)) {
6343 np
->flags
|= NIU_FLAGS_PROMISC
;
6349 netdev_for_each_uc_addr(ha
, dev
) {
6350 err
= niu_set_alt_mac(np
, index
, ha
->addr
);
6352 netdev_warn(dev
, "Error %d adding alt mac %d\n",
6354 err
= niu_enable_alt_mac(np
, index
, 1);
6356 netdev_warn(dev
, "Error %d enabling alt mac %d\n",
6363 if (np
->flags
& NIU_FLAGS_XMAC
)
6367 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
6368 err
= niu_enable_alt_mac(np
, i
, 0);
6370 netdev_warn(dev
, "Error %d disabling alt mac %d\n",
6374 if (dev
->flags
& IFF_ALLMULTI
) {
6375 for (i
= 0; i
< 16; i
++)
6377 } else if (!netdev_mc_empty(dev
)) {
6378 netdev_for_each_mc_addr(ha
, dev
) {
6379 u32 crc
= ether_crc_le(ETH_ALEN
, ha
->addr
);
6382 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
6386 if (np
->flags
& NIU_FLAGS_MCAST
)
6387 niu_load_hash(np
, hash
);
6389 niu_enable_rx_mac(np
, 1);
6390 spin_unlock_irqrestore(&np
->lock
, flags
);
6393 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
6395 struct niu
*np
= netdev_priv(dev
);
6396 struct sockaddr
*addr
= p
;
6397 unsigned long flags
;
6399 if (!is_valid_ether_addr(addr
->sa_data
))
6402 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
6404 if (!netif_running(dev
))
6407 spin_lock_irqsave(&np
->lock
, flags
);
6408 niu_enable_rx_mac(np
, 0);
6409 niu_set_primary_mac(np
, dev
->dev_addr
);
6410 niu_enable_rx_mac(np
, 1);
6411 spin_unlock_irqrestore(&np
->lock
, flags
);
6416 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6421 static void niu_netif_stop(struct niu
*np
)
6423 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6425 niu_disable_napi(np
);
6427 netif_tx_disable(np
->dev
);
6430 static void niu_netif_start(struct niu
*np
)
6432 /* NOTE: unconditional netif_wake_queue is only appropriate
6433 * so long as all callers are assured to have free tx slots
6434 * (such as after niu_init_hw).
6436 netif_tx_wake_all_queues(np
->dev
);
6438 niu_enable_napi(np
);
6440 niu_enable_interrupts(np
, 1);
6443 static void niu_reset_buffers(struct niu
*np
)
6448 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6449 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6451 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
6454 page
= rp
->rxhash
[j
];
6457 (struct page
*) page
->mapping
;
6458 u64 base
= page
->index
;
6459 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6460 rp
->rbr
[k
++] = cpu_to_le32(base
);
6464 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6465 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6470 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6472 rp
->rbr_pending
= 0;
6473 rp
->rbr_refill_pending
= 0;
6477 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6478 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6480 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6481 if (rp
->tx_buffs
[j
].skb
)
6482 (void) release_tx_packet(np
, rp
, j
);
6485 rp
->pending
= MAX_TX_RING_SIZE
;
6493 static void niu_reset_task(struct work_struct
*work
)
6495 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6496 unsigned long flags
;
6499 spin_lock_irqsave(&np
->lock
, flags
);
6500 if (!netif_running(np
->dev
)) {
6501 spin_unlock_irqrestore(&np
->lock
, flags
);
6505 spin_unlock_irqrestore(&np
->lock
, flags
);
6507 del_timer_sync(&np
->timer
);
6511 spin_lock_irqsave(&np
->lock
, flags
);
6515 spin_unlock_irqrestore(&np
->lock
, flags
);
6517 niu_reset_buffers(np
);
6519 spin_lock_irqsave(&np
->lock
, flags
);
6521 err
= niu_init_hw(np
);
6523 np
->timer
.expires
= jiffies
+ HZ
;
6524 add_timer(&np
->timer
);
6525 niu_netif_start(np
);
6528 spin_unlock_irqrestore(&np
->lock
, flags
);
6531 static void niu_tx_timeout(struct net_device
*dev
)
6533 struct niu
*np
= netdev_priv(dev
);
6535 dev_err(np
->device
, "%s: Transmit timed out, resetting\n",
6538 schedule_work(&np
->reset_task
);
6541 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6542 u64 mapping
, u64 len
, u64 mark
,
6545 __le64
*desc
= &rp
->descr
[index
];
6547 *desc
= cpu_to_le64(mark
|
6548 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6549 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6550 (mapping
& TX_DESC_SAD
));
6553 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6554 u64 pad_bytes
, u64 len
)
6556 u16 eth_proto
, eth_proto_inner
;
6557 u64 csum_bits
, l3off
, ihl
, ret
;
6561 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6562 eth_proto_inner
= eth_proto
;
6563 if (eth_proto
== ETH_P_8021Q
) {
6564 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6565 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6567 eth_proto_inner
= be16_to_cpu(val
);
6571 switch (skb
->protocol
) {
6572 case cpu_to_be16(ETH_P_IP
):
6573 ip_proto
= ip_hdr(skb
)->protocol
;
6574 ihl
= ip_hdr(skb
)->ihl
;
6576 case cpu_to_be16(ETH_P_IPV6
):
6577 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6586 csum_bits
= TXHDR_CSUM_NONE
;
6587 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6590 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6592 (ip_proto
== IPPROTO_UDP
?
6593 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6595 start
= skb_transport_offset(skb
) -
6596 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6597 stuff
= start
+ skb
->csum_offset
;
6599 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6600 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6603 l3off
= skb_network_offset(skb
) -
6604 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6606 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6607 (len
<< TXHDR_LEN_SHIFT
) |
6608 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6609 (ihl
<< TXHDR_IHL_SHIFT
) |
6610 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6611 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6612 (ipv6
? TXHDR_IP_VER
: 0) |
6618 static netdev_tx_t
niu_start_xmit(struct sk_buff
*skb
,
6619 struct net_device
*dev
)
6621 struct niu
*np
= netdev_priv(dev
);
6622 unsigned long align
, headroom
;
6623 struct netdev_queue
*txq
;
6624 struct tx_ring_info
*rp
;
6625 struct tx_pkt_hdr
*tp
;
6626 unsigned int len
, nfg
;
6627 struct ethhdr
*ehdr
;
6631 i
= skb_get_queue_mapping(skb
);
6632 rp
= &np
->tx_rings
[i
];
6633 txq
= netdev_get_tx_queue(dev
, i
);
6635 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6636 netif_tx_stop_queue(txq
);
6637 dev_err(np
->device
, "%s: BUG! Tx ring full when queue awake!\n", dev
->name
);
6639 return NETDEV_TX_BUSY
;
6642 if (skb
->len
< ETH_ZLEN
) {
6643 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6645 if (skb_pad(skb
, pad_bytes
))
6647 skb_put(skb
, pad_bytes
);
6650 len
= sizeof(struct tx_pkt_hdr
) + 15;
6651 if (skb_headroom(skb
) < len
) {
6652 struct sk_buff
*skb_new
;
6654 skb_new
= skb_realloc_headroom(skb
, len
);
6664 align
= ((unsigned long) skb
->data
& (16 - 1));
6665 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6667 ehdr
= (struct ethhdr
*) skb
->data
;
6668 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6670 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6671 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6674 len
= skb_headlen(skb
);
6675 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6676 len
, DMA_TO_DEVICE
);
6680 rp
->tx_buffs
[prod
].skb
= skb
;
6681 rp
->tx_buffs
[prod
].mapping
= mapping
;
6684 if (++rp
->mark_counter
== rp
->mark_freq
) {
6685 rp
->mark_counter
= 0;
6686 mrk
|= TX_DESC_MARK
;
6691 nfg
= skb_shinfo(skb
)->nr_frags
;
6693 tlen
-= MAX_TX_DESC_LEN
;
6698 unsigned int this_len
= len
;
6700 if (this_len
> MAX_TX_DESC_LEN
)
6701 this_len
= MAX_TX_DESC_LEN
;
6703 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6706 prod
= NEXT_TX(rp
, prod
);
6707 mapping
+= this_len
;
6711 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6712 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6715 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6716 frag
->page_offset
, len
,
6719 rp
->tx_buffs
[prod
].skb
= NULL
;
6720 rp
->tx_buffs
[prod
].mapping
= mapping
;
6722 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6724 prod
= NEXT_TX(rp
, prod
);
6727 if (prod
< rp
->prod
)
6728 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6731 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6733 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6734 netif_tx_stop_queue(txq
);
6735 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6736 netif_tx_wake_queue(txq
);
6740 return NETDEV_TX_OK
;
6748 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6750 struct niu
*np
= netdev_priv(dev
);
6751 int err
, orig_jumbo
, new_jumbo
;
6753 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6756 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6757 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6761 if (!netif_running(dev
) ||
6762 (orig_jumbo
== new_jumbo
))
6765 niu_full_shutdown(np
, dev
);
6767 niu_free_channels(np
);
6769 niu_enable_napi(np
);
6771 err
= niu_alloc_channels(np
);
6775 spin_lock_irq(&np
->lock
);
6777 err
= niu_init_hw(np
);
6779 init_timer(&np
->timer
);
6780 np
->timer
.expires
= jiffies
+ HZ
;
6781 np
->timer
.data
= (unsigned long) np
;
6782 np
->timer
.function
= niu_timer
;
6784 err
= niu_enable_interrupts(np
, 1);
6789 spin_unlock_irq(&np
->lock
);
6792 netif_tx_start_all_queues(dev
);
6793 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6794 netif_carrier_on(dev
);
6796 add_timer(&np
->timer
);
6802 static void niu_get_drvinfo(struct net_device
*dev
,
6803 struct ethtool_drvinfo
*info
)
6805 struct niu
*np
= netdev_priv(dev
);
6806 struct niu_vpd
*vpd
= &np
->vpd
;
6808 strcpy(info
->driver
, DRV_MODULE_NAME
);
6809 strcpy(info
->version
, DRV_MODULE_VERSION
);
6810 sprintf(info
->fw_version
, "%d.%d",
6811 vpd
->fcode_major
, vpd
->fcode_minor
);
6812 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6813 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6816 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6818 struct niu
*np
= netdev_priv(dev
);
6819 struct niu_link_config
*lp
;
6821 lp
= &np
->link_config
;
6823 memset(cmd
, 0, sizeof(*cmd
));
6824 cmd
->phy_address
= np
->phy_addr
;
6825 cmd
->supported
= lp
->supported
;
6826 cmd
->advertising
= lp
->active_advertising
;
6827 cmd
->autoneg
= lp
->active_autoneg
;
6828 cmd
->speed
= lp
->active_speed
;
6829 cmd
->duplex
= lp
->active_duplex
;
6830 cmd
->port
= (np
->flags
& NIU_FLAGS_FIBER
) ? PORT_FIBRE
: PORT_TP
;
6831 cmd
->transceiver
= (np
->flags
& NIU_FLAGS_XCVR_SERDES
) ?
6832 XCVR_EXTERNAL
: XCVR_INTERNAL
;
6837 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6839 struct niu
*np
= netdev_priv(dev
);
6840 struct niu_link_config
*lp
= &np
->link_config
;
6842 lp
->advertising
= cmd
->advertising
;
6843 lp
->speed
= cmd
->speed
;
6844 lp
->duplex
= cmd
->duplex
;
6845 lp
->autoneg
= cmd
->autoneg
;
6846 return niu_init_link(np
);
6849 static u32
niu_get_msglevel(struct net_device
*dev
)
6851 struct niu
*np
= netdev_priv(dev
);
6852 return np
->msg_enable
;
6855 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6857 struct niu
*np
= netdev_priv(dev
);
6858 np
->msg_enable
= value
;
6861 static int niu_nway_reset(struct net_device
*dev
)
6863 struct niu
*np
= netdev_priv(dev
);
6865 if (np
->link_config
.autoneg
)
6866 return niu_init_link(np
);
6871 static int niu_get_eeprom_len(struct net_device
*dev
)
6873 struct niu
*np
= netdev_priv(dev
);
6875 return np
->eeprom_len
;
6878 static int niu_get_eeprom(struct net_device
*dev
,
6879 struct ethtool_eeprom
*eeprom
, u8
*data
)
6881 struct niu
*np
= netdev_priv(dev
);
6882 u32 offset
, len
, val
;
6884 offset
= eeprom
->offset
;
6887 if (offset
+ len
< offset
)
6889 if (offset
>= np
->eeprom_len
)
6891 if (offset
+ len
> np
->eeprom_len
)
6892 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6895 u32 b_offset
, b_count
;
6897 b_offset
= offset
& 3;
6898 b_count
= 4 - b_offset
;
6902 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6903 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6909 val
= nr64(ESPC_NCR(offset
/ 4));
6910 memcpy(data
, &val
, 4);
6916 val
= nr64(ESPC_NCR(offset
/ 4));
6917 memcpy(data
, &val
, len
);
6922 static void niu_ethflow_to_l3proto(int flow_type
, u8
*pid
)
6924 switch (flow_type
) {
6935 *pid
= IPPROTO_SCTP
;
6951 static int niu_class_to_ethflow(u64
class, int *flow_type
)
6954 case CLASS_CODE_TCP_IPV4
:
6955 *flow_type
= TCP_V4_FLOW
;
6957 case CLASS_CODE_UDP_IPV4
:
6958 *flow_type
= UDP_V4_FLOW
;
6960 case CLASS_CODE_AH_ESP_IPV4
:
6961 *flow_type
= AH_V4_FLOW
;
6963 case CLASS_CODE_SCTP_IPV4
:
6964 *flow_type
= SCTP_V4_FLOW
;
6966 case CLASS_CODE_TCP_IPV6
:
6967 *flow_type
= TCP_V6_FLOW
;
6969 case CLASS_CODE_UDP_IPV6
:
6970 *flow_type
= UDP_V6_FLOW
;
6972 case CLASS_CODE_AH_ESP_IPV6
:
6973 *flow_type
= AH_V6_FLOW
;
6975 case CLASS_CODE_SCTP_IPV6
:
6976 *flow_type
= SCTP_V6_FLOW
;
6978 case CLASS_CODE_USER_PROG1
:
6979 case CLASS_CODE_USER_PROG2
:
6980 case CLASS_CODE_USER_PROG3
:
6981 case CLASS_CODE_USER_PROG4
:
6982 *flow_type
= IP_USER_FLOW
;
6991 static int niu_ethflow_to_class(int flow_type
, u64
*class)
6993 switch (flow_type
) {
6995 *class = CLASS_CODE_TCP_IPV4
;
6998 *class = CLASS_CODE_UDP_IPV4
;
7002 *class = CLASS_CODE_AH_ESP_IPV4
;
7005 *class = CLASS_CODE_SCTP_IPV4
;
7008 *class = CLASS_CODE_TCP_IPV6
;
7011 *class = CLASS_CODE_UDP_IPV6
;
7015 *class = CLASS_CODE_AH_ESP_IPV6
;
7018 *class = CLASS_CODE_SCTP_IPV6
;
7027 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
7031 if (flow_key
& FLOW_KEY_L2DA
)
7032 ethflow
|= RXH_L2DA
;
7033 if (flow_key
& FLOW_KEY_VLAN
)
7034 ethflow
|= RXH_VLAN
;
7035 if (flow_key
& FLOW_KEY_IPSA
)
7036 ethflow
|= RXH_IP_SRC
;
7037 if (flow_key
& FLOW_KEY_IPDA
)
7038 ethflow
|= RXH_IP_DST
;
7039 if (flow_key
& FLOW_KEY_PROTO
)
7040 ethflow
|= RXH_L3_PROTO
;
7041 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
7042 ethflow
|= RXH_L4_B_0_1
;
7043 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
7044 ethflow
|= RXH_L4_B_2_3
;
7050 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
7054 if (ethflow
& RXH_L2DA
)
7055 key
|= FLOW_KEY_L2DA
;
7056 if (ethflow
& RXH_VLAN
)
7057 key
|= FLOW_KEY_VLAN
;
7058 if (ethflow
& RXH_IP_SRC
)
7059 key
|= FLOW_KEY_IPSA
;
7060 if (ethflow
& RXH_IP_DST
)
7061 key
|= FLOW_KEY_IPDA
;
7062 if (ethflow
& RXH_L3_PROTO
)
7063 key
|= FLOW_KEY_PROTO
;
7064 if (ethflow
& RXH_L4_B_0_1
)
7065 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
7066 if (ethflow
& RXH_L4_B_2_3
)
7067 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
7075 static int niu_get_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7081 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7084 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7086 nfc
->data
= RXH_DISCARD
;
7088 nfc
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
7089 CLASS_CODE_USER_PROG1
]);
7093 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry
*tp
,
7094 struct ethtool_rx_flow_spec
*fsp
)
7097 fsp
->h_u
.tcp_ip4_spec
.ip4src
= (tp
->key
[3] & TCAM_V4KEY3_SADDR
) >>
7098 TCAM_V4KEY3_SADDR_SHIFT
;
7099 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= (tp
->key
[3] & TCAM_V4KEY3_DADDR
) >>
7100 TCAM_V4KEY3_DADDR_SHIFT
;
7101 fsp
->m_u
.tcp_ip4_spec
.ip4src
= (tp
->key_mask
[3] & TCAM_V4KEY3_SADDR
) >>
7102 TCAM_V4KEY3_SADDR_SHIFT
;
7103 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= (tp
->key_mask
[3] & TCAM_V4KEY3_DADDR
) >>
7104 TCAM_V4KEY3_DADDR_SHIFT
;
7106 fsp
->h_u
.tcp_ip4_spec
.ip4src
=
7107 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7108 fsp
->m_u
.tcp_ip4_spec
.ip4src
=
7109 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7110 fsp
->h_u
.tcp_ip4_spec
.ip4dst
=
7111 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7112 fsp
->m_u
.tcp_ip4_spec
.ip4dst
=
7113 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7115 fsp
->h_u
.tcp_ip4_spec
.tos
= (tp
->key
[2] & TCAM_V4KEY2_TOS
) >>
7116 TCAM_V4KEY2_TOS_SHIFT
;
7117 fsp
->m_u
.tcp_ip4_spec
.tos
= (tp
->key_mask
[2] & TCAM_V4KEY2_TOS
) >>
7118 TCAM_V4KEY2_TOS_SHIFT
;
7120 switch (fsp
->flow_type
) {
7124 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7125 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7126 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7127 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7128 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7129 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7130 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7131 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7132 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7133 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7134 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7135 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7137 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7138 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7139 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7140 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7141 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7142 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7143 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7144 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7148 fsp
->h_u
.ah_ip4_spec
.spi
=
7149 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7150 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7151 fsp
->m_u
.ah_ip4_spec
.spi
=
7152 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7153 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7155 fsp
->h_u
.ah_ip4_spec
.spi
=
7156 cpu_to_be32(fsp
->h_u
.ah_ip4_spec
.spi
);
7157 fsp
->m_u
.ah_ip4_spec
.spi
=
7158 cpu_to_be32(fsp
->m_u
.ah_ip4_spec
.spi
);
7161 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7162 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7163 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7164 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7165 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7166 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7168 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7169 cpu_to_be32(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7170 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7171 cpu_to_be32(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7173 fsp
->h_u
.usr_ip4_spec
.proto
=
7174 (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7175 TCAM_V4KEY2_PROTO_SHIFT
;
7176 fsp
->m_u
.usr_ip4_spec
.proto
=
7177 (tp
->key_mask
[2] & TCAM_V4KEY2_PROTO
) >>
7178 TCAM_V4KEY2_PROTO_SHIFT
;
7180 fsp
->h_u
.usr_ip4_spec
.ip_ver
= ETH_RX_NFC_IP4
;
7187 static int niu_get_ethtool_tcam_entry(struct niu
*np
,
7188 struct ethtool_rxnfc
*nfc
)
7190 struct niu_parent
*parent
= np
->parent
;
7191 struct niu_tcam_entry
*tp
;
7192 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7197 idx
= tcam_get_index(np
, (u16
)nfc
->fs
.location
);
7199 tp
= &parent
->tcam
[idx
];
7201 netdev_info(np
->dev
, "niu%d: entry [%d] invalid for idx[%d]\n",
7202 parent
->index
, (u16
)nfc
->fs
.location
, idx
);
7206 /* fill the flow spec entry */
7207 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7208 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7209 ret
= niu_class_to_ethflow(class, &fsp
->flow_type
);
7212 netdev_info(np
->dev
, "niu%d: niu_class_to_ethflow failed\n",
7218 if (fsp
->flow_type
== AH_V4_FLOW
|| fsp
->flow_type
== AH_V6_FLOW
) {
7219 u32 proto
= (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7220 TCAM_V4KEY2_PROTO_SHIFT
;
7221 if (proto
== IPPROTO_ESP
) {
7222 if (fsp
->flow_type
== AH_V4_FLOW
)
7223 fsp
->flow_type
= ESP_V4_FLOW
;
7225 fsp
->flow_type
= ESP_V6_FLOW
;
7229 switch (fsp
->flow_type
) {
7235 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7242 /* Not yet implemented */
7246 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7256 if (tp
->assoc_data
& TCAM_ASSOCDATA_DISC
)
7257 fsp
->ring_cookie
= RX_CLS_FLOW_DISC
;
7259 fsp
->ring_cookie
= (tp
->assoc_data
& TCAM_ASSOCDATA_OFFSET
) >>
7260 TCAM_ASSOCDATA_OFFSET_SHIFT
;
7262 /* put the tcam size here */
7263 nfc
->data
= tcam_get_size(np
);
7268 static int niu_get_ethtool_tcam_all(struct niu
*np
,
7269 struct ethtool_rxnfc
*nfc
,
7272 struct niu_parent
*parent
= np
->parent
;
7273 struct niu_tcam_entry
*tp
;
7276 unsigned long flags
;
7279 /* put the tcam size here */
7280 nfc
->data
= tcam_get_size(np
);
7282 niu_lock_parent(np
, flags
);
7283 n_entries
= nfc
->rule_cnt
;
7284 for (cnt
= 0, i
= 0; i
< nfc
->data
; i
++) {
7285 idx
= tcam_get_index(np
, i
);
7286 tp
= &parent
->tcam
[idx
];
7292 niu_unlock_parent(np
, flags
);
7294 if (n_entries
!= cnt
) {
7295 /* print warning, this should not happen */
7296 netdev_info(np
->dev
, "niu%d: In %s(): n_entries[%d] != cnt[%d]!!!\n",
7297 np
->parent
->index
, __func__
, n_entries
, cnt
);
7303 static int niu_get_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
7306 struct niu
*np
= netdev_priv(dev
);
7311 ret
= niu_get_hash_opts(np
, cmd
);
7313 case ETHTOOL_GRXRINGS
:
7314 cmd
->data
= np
->num_rx_rings
;
7316 case ETHTOOL_GRXCLSRLCNT
:
7317 cmd
->rule_cnt
= tcam_get_valid_entry_cnt(np
);
7319 case ETHTOOL_GRXCLSRULE
:
7320 ret
= niu_get_ethtool_tcam_entry(np
, cmd
);
7322 case ETHTOOL_GRXCLSRLALL
:
7323 ret
= niu_get_ethtool_tcam_all(np
, cmd
, (u32
*)rule_locs
);
7333 static int niu_set_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7337 unsigned long flags
;
7339 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7342 if (class < CLASS_CODE_USER_PROG1
||
7343 class > CLASS_CODE_SCTP_IPV6
)
7346 if (nfc
->data
& RXH_DISCARD
) {
7347 niu_lock_parent(np
, flags
);
7348 flow_key
= np
->parent
->tcam_key
[class -
7349 CLASS_CODE_USER_PROG1
];
7350 flow_key
|= TCAM_KEY_DISC
;
7351 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7352 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7353 niu_unlock_parent(np
, flags
);
7356 /* Discard was set before, but is not set now */
7357 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7359 niu_lock_parent(np
, flags
);
7360 flow_key
= np
->parent
->tcam_key
[class -
7361 CLASS_CODE_USER_PROG1
];
7362 flow_key
&= ~TCAM_KEY_DISC
;
7363 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
7365 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
7367 niu_unlock_parent(np
, flags
);
7371 if (!niu_ethflow_to_flowkey(nfc
->data
, &flow_key
))
7374 niu_lock_parent(np
, flags
);
7375 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7376 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7377 niu_unlock_parent(np
, flags
);
7382 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec
*fsp
,
7383 struct niu_tcam_entry
*tp
,
7384 int l2_rdc_tab
, u64
class)
7387 u32 sip
, dip
, sipm
, dipm
, spi
, spim
;
7388 u16 sport
, dport
, spm
, dpm
;
7390 sip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7391 sipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7392 dip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7393 dipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7395 tp
->key
[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7396 tp
->key_mask
[0] = TCAM_V4KEY0_CLASS_CODE
;
7397 tp
->key
[1] = (u64
)l2_rdc_tab
<< TCAM_V4KEY1_L2RDCNUM_SHIFT
;
7398 tp
->key_mask
[1] = TCAM_V4KEY1_L2RDCNUM
;
7400 tp
->key
[3] = (u64
)sip
<< TCAM_V4KEY3_SADDR_SHIFT
;
7403 tp
->key_mask
[3] = (u64
)sipm
<< TCAM_V4KEY3_SADDR_SHIFT
;
7404 tp
->key_mask
[3] |= dipm
;
7406 tp
->key
[2] |= ((u64
)fsp
->h_u
.tcp_ip4_spec
.tos
<<
7407 TCAM_V4KEY2_TOS_SHIFT
);
7408 tp
->key_mask
[2] |= ((u64
)fsp
->m_u
.tcp_ip4_spec
.tos
<<
7409 TCAM_V4KEY2_TOS_SHIFT
);
7410 switch (fsp
->flow_type
) {
7414 sport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7415 spm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7416 dport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7417 dpm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7419 tp
->key
[2] |= (((u64
)sport
<< 16) | dport
);
7420 tp
->key_mask
[2] |= (((u64
)spm
<< 16) | dpm
);
7421 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7425 spi
= be32_to_cpu(fsp
->h_u
.ah_ip4_spec
.spi
);
7426 spim
= be32_to_cpu(fsp
->m_u
.ah_ip4_spec
.spi
);
7429 tp
->key_mask
[2] |= spim
;
7430 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7433 spi
= be32_to_cpu(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7434 spim
= be32_to_cpu(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7437 tp
->key_mask
[2] |= spim
;
7438 pid
= fsp
->h_u
.usr_ip4_spec
.proto
;
7444 tp
->key
[2] |= ((u64
)pid
<< TCAM_V4KEY2_PROTO_SHIFT
);
7446 tp
->key_mask
[2] |= TCAM_V4KEY2_PROTO
;
7450 static int niu_add_ethtool_tcam_entry(struct niu
*np
,
7451 struct ethtool_rxnfc
*nfc
)
7453 struct niu_parent
*parent
= np
->parent
;
7454 struct niu_tcam_entry
*tp
;
7455 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7456 struct niu_rdc_tables
*rdc_table
= &parent
->rdc_group_cfg
[np
->port
];
7457 int l2_rdc_table
= rdc_table
->first_table_num
;
7460 unsigned long flags
;
7465 idx
= nfc
->fs
.location
;
7466 if (idx
>= tcam_get_size(np
))
7469 if (fsp
->flow_type
== IP_USER_FLOW
) {
7471 int add_usr_cls
= 0;
7473 struct ethtool_usrip4_spec
*uspec
= &fsp
->h_u
.usr_ip4_spec
;
7474 struct ethtool_usrip4_spec
*umask
= &fsp
->m_u
.usr_ip4_spec
;
7476 niu_lock_parent(np
, flags
);
7478 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7479 if (parent
->l3_cls
[i
]) {
7480 if (uspec
->proto
== parent
->l3_cls_pid
[i
]) {
7481 class = parent
->l3_cls
[i
];
7482 parent
->l3_cls_refcnt
[i
]++;
7487 /* Program new user IP class */
7490 class = CLASS_CODE_USER_PROG1
;
7493 class = CLASS_CODE_USER_PROG2
;
7496 class = CLASS_CODE_USER_PROG3
;
7499 class = CLASS_CODE_USER_PROG4
;
7504 if (uspec
->ip_ver
== ETH_RX_NFC_IP6
)
7506 ret
= tcam_user_ip_class_set(np
, class, ipv6
,
7513 ret
= tcam_user_ip_class_enable(np
, class, 1);
7516 parent
->l3_cls
[i
] = class;
7517 parent
->l3_cls_pid
[i
] = uspec
->proto
;
7518 parent
->l3_cls_refcnt
[i
]++;
7524 netdev_info(np
->dev
, "niu%d: %s(): Could not find/insert class for pid %d\n",
7525 parent
->index
, __func__
, uspec
->proto
);
7529 niu_unlock_parent(np
, flags
);
7531 if (!niu_ethflow_to_class(fsp
->flow_type
, &class)) {
7536 niu_lock_parent(np
, flags
);
7538 idx
= tcam_get_index(np
, idx
);
7539 tp
= &parent
->tcam
[idx
];
7541 memset(tp
, 0, sizeof(*tp
));
7543 /* fill in the tcam key and mask */
7544 switch (fsp
->flow_type
) {
7550 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7557 /* Not yet implemented */
7558 netdev_info(np
->dev
, "niu%d: In %s(): flow %d for IPv6 not implemented\n",
7559 parent
->index
, __func__
, fsp
->flow_type
);
7563 if (fsp
->h_u
.usr_ip4_spec
.ip_ver
== ETH_RX_NFC_IP4
) {
7564 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
,
7567 /* Not yet implemented */
7568 netdev_info(np
->dev
, "niu%d: In %s(): usr flow for IPv6 not implemented\n",
7569 parent
->index
, __func__
);
7575 netdev_info(np
->dev
, "niu%d: In %s(): Unknown flow type %d\n",
7576 parent
->index
, __func__
, fsp
->flow_type
);
7581 /* fill in the assoc data */
7582 if (fsp
->ring_cookie
== RX_CLS_FLOW_DISC
) {
7583 tp
->assoc_data
= TCAM_ASSOCDATA_DISC
;
7585 if (fsp
->ring_cookie
>= np
->num_rx_rings
) {
7586 netdev_info(np
->dev
, "niu%d: In %s(): Invalid RX ring %lld\n",
7587 parent
->index
, __func__
,
7588 (long long)fsp
->ring_cookie
);
7592 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
7593 (fsp
->ring_cookie
<<
7594 TCAM_ASSOCDATA_OFFSET_SHIFT
));
7597 err
= tcam_write(np
, idx
, tp
->key
, tp
->key_mask
);
7602 err
= tcam_assoc_write(np
, idx
, tp
->assoc_data
);
7608 /* validate the entry */
7610 np
->clas
.tcam_valid_entries
++;
7612 niu_unlock_parent(np
, flags
);
7617 static int niu_del_ethtool_tcam_entry(struct niu
*np
, u32 loc
)
7619 struct niu_parent
*parent
= np
->parent
;
7620 struct niu_tcam_entry
*tp
;
7622 unsigned long flags
;
7626 if (loc
>= tcam_get_size(np
))
7629 niu_lock_parent(np
, flags
);
7631 idx
= tcam_get_index(np
, loc
);
7632 tp
= &parent
->tcam
[idx
];
7634 /* if the entry is of a user defined class, then update*/
7635 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7636 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7638 if (class >= CLASS_CODE_USER_PROG1
&& class <= CLASS_CODE_USER_PROG4
) {
7640 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7641 if (parent
->l3_cls
[i
] == class) {
7642 parent
->l3_cls_refcnt
[i
]--;
7643 if (!parent
->l3_cls_refcnt
[i
]) {
7645 ret
= tcam_user_ip_class_enable(np
,
7650 parent
->l3_cls
[i
] = 0;
7651 parent
->l3_cls_pid
[i
] = 0;
7656 if (i
== NIU_L3_PROG_CLS
) {
7657 netdev_info(np
->dev
, "niu%d: In %s(): Usr class 0x%llx not found\n",
7658 parent
->index
, __func__
,
7659 (unsigned long long)class);
7665 ret
= tcam_flush(np
, idx
);
7669 /* invalidate the entry */
7671 np
->clas
.tcam_valid_entries
--;
7673 niu_unlock_parent(np
, flags
);
7678 static int niu_set_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
7680 struct niu
*np
= netdev_priv(dev
);
7685 ret
= niu_set_hash_opts(np
, cmd
);
7687 case ETHTOOL_SRXCLSRLINS
:
7688 ret
= niu_add_ethtool_tcam_entry(np
, cmd
);
7690 case ETHTOOL_SRXCLSRLDEL
:
7691 ret
= niu_del_ethtool_tcam_entry(np
, cmd
->fs
.location
);
7701 static const struct {
7702 const char string
[ETH_GSTRING_LEN
];
7703 } niu_xmac_stat_keys
[] = {
7706 { "tx_fifo_errors" },
7707 { "tx_overflow_errors" },
7708 { "tx_max_pkt_size_errors" },
7709 { "tx_underflow_errors" },
7710 { "rx_local_faults" },
7711 { "rx_remote_faults" },
7712 { "rx_link_faults" },
7713 { "rx_align_errors" },
7725 { "rx_code_violations" },
7726 { "rx_len_errors" },
7727 { "rx_crc_errors" },
7728 { "rx_underflows" },
7730 { "pause_off_state" },
7731 { "pause_on_state" },
7732 { "pause_received" },
7735 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7737 static const struct {
7738 const char string
[ETH_GSTRING_LEN
];
7739 } niu_bmac_stat_keys
[] = {
7740 { "tx_underflow_errors" },
7741 { "tx_max_pkt_size_errors" },
7746 { "rx_align_errors" },
7747 { "rx_crc_errors" },
7748 { "rx_len_errors" },
7749 { "pause_off_state" },
7750 { "pause_on_state" },
7751 { "pause_received" },
7754 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7756 static const struct {
7757 const char string
[ETH_GSTRING_LEN
];
7758 } niu_rxchan_stat_keys
[] = {
7766 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7768 static const struct {
7769 const char string
[ETH_GSTRING_LEN
];
7770 } niu_txchan_stat_keys
[] = {
7777 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7779 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
7781 struct niu
*np
= netdev_priv(dev
);
7784 if (stringset
!= ETH_SS_STATS
)
7787 if (np
->flags
& NIU_FLAGS_XMAC
) {
7788 memcpy(data
, niu_xmac_stat_keys
,
7789 sizeof(niu_xmac_stat_keys
));
7790 data
+= sizeof(niu_xmac_stat_keys
);
7792 memcpy(data
, niu_bmac_stat_keys
,
7793 sizeof(niu_bmac_stat_keys
));
7794 data
+= sizeof(niu_bmac_stat_keys
);
7796 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7797 memcpy(data
, niu_rxchan_stat_keys
,
7798 sizeof(niu_rxchan_stat_keys
));
7799 data
+= sizeof(niu_rxchan_stat_keys
);
7801 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7802 memcpy(data
, niu_txchan_stat_keys
,
7803 sizeof(niu_txchan_stat_keys
));
7804 data
+= sizeof(niu_txchan_stat_keys
);
7808 static int niu_get_sset_count(struct net_device
*dev
, int stringset
)
7810 struct niu
*np
= netdev_priv(dev
);
7812 if (stringset
!= ETH_SS_STATS
)
7815 return ((np
->flags
& NIU_FLAGS_XMAC
?
7816 NUM_XMAC_STAT_KEYS
:
7817 NUM_BMAC_STAT_KEYS
) +
7818 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
7819 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
));
7822 static void niu_get_ethtool_stats(struct net_device
*dev
,
7823 struct ethtool_stats
*stats
, u64
*data
)
7825 struct niu
*np
= netdev_priv(dev
);
7828 niu_sync_mac_stats(np
);
7829 if (np
->flags
& NIU_FLAGS_XMAC
) {
7830 memcpy(data
, &np
->mac_stats
.xmac
,
7831 sizeof(struct niu_xmac_stats
));
7832 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
7834 memcpy(data
, &np
->mac_stats
.bmac
,
7835 sizeof(struct niu_bmac_stats
));
7836 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
7838 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7839 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
7841 niu_sync_rx_discard_stats(np
, rp
, 0);
7843 data
[0] = rp
->rx_channel
;
7844 data
[1] = rp
->rx_packets
;
7845 data
[2] = rp
->rx_bytes
;
7846 data
[3] = rp
->rx_dropped
;
7847 data
[4] = rp
->rx_errors
;
7850 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7851 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
7853 data
[0] = rp
->tx_channel
;
7854 data
[1] = rp
->tx_packets
;
7855 data
[2] = rp
->tx_bytes
;
7856 data
[3] = rp
->tx_errors
;
7861 static u64
niu_led_state_save(struct niu
*np
)
7863 if (np
->flags
& NIU_FLAGS_XMAC
)
7864 return nr64_mac(XMAC_CONFIG
);
7866 return nr64_mac(BMAC_XIF_CONFIG
);
7869 static void niu_led_state_restore(struct niu
*np
, u64 val
)
7871 if (np
->flags
& NIU_FLAGS_XMAC
)
7872 nw64_mac(XMAC_CONFIG
, val
);
7874 nw64_mac(BMAC_XIF_CONFIG
, val
);
7877 static void niu_force_led(struct niu
*np
, int on
)
7881 if (np
->flags
& NIU_FLAGS_XMAC
) {
7883 bit
= XMAC_CONFIG_FORCE_LED_ON
;
7885 reg
= BMAC_XIF_CONFIG
;
7886 bit
= BMAC_XIF_CONFIG_LINK_LED
;
7889 val
= nr64_mac(reg
);
7897 static int niu_phys_id(struct net_device
*dev
, u32 data
)
7899 struct niu
*np
= netdev_priv(dev
);
7903 if (!netif_running(dev
))
7909 orig_led_state
= niu_led_state_save(np
);
7910 for (i
= 0; i
< (data
* 2); i
++) {
7911 int on
= ((i
% 2) == 0);
7913 niu_force_led(np
, on
);
7915 if (msleep_interruptible(500))
7918 niu_led_state_restore(np
, orig_led_state
);
7923 static int niu_set_flags(struct net_device
*dev
, u32 data
)
7925 return ethtool_op_set_flags(dev
, data
, ETH_FLAG_RXHASH
);
7928 static const struct ethtool_ops niu_ethtool_ops
= {
7929 .get_drvinfo
= niu_get_drvinfo
,
7930 .get_link
= ethtool_op_get_link
,
7931 .get_msglevel
= niu_get_msglevel
,
7932 .set_msglevel
= niu_set_msglevel
,
7933 .nway_reset
= niu_nway_reset
,
7934 .get_eeprom_len
= niu_get_eeprom_len
,
7935 .get_eeprom
= niu_get_eeprom
,
7936 .get_settings
= niu_get_settings
,
7937 .set_settings
= niu_set_settings
,
7938 .get_strings
= niu_get_strings
,
7939 .get_sset_count
= niu_get_sset_count
,
7940 .get_ethtool_stats
= niu_get_ethtool_stats
,
7941 .phys_id
= niu_phys_id
,
7942 .get_rxnfc
= niu_get_nfc
,
7943 .set_rxnfc
= niu_set_nfc
,
7944 .set_flags
= niu_set_flags
,
7945 .get_flags
= ethtool_op_get_flags
,
7948 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
7951 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
7953 if (ldn
< 0 || ldn
> LDN_MAX
)
7956 parent
->ldg_map
[ldn
] = ldg
;
7958 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
7959 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
7960 * the firmware, and we're not supposed to change them.
7961 * Validate the mapping, because if it's wrong we probably
7962 * won't get any interrupts and that's painful to debug.
7964 if (nr64(LDG_NUM(ldn
)) != ldg
) {
7965 dev_err(np
->device
, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n",
7967 (unsigned long long) nr64(LDG_NUM(ldn
)));
7971 nw64(LDG_NUM(ldn
), ldg
);
7976 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
7978 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
7982 nw64(LDG_TIMER_RES
, res
);
7987 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
7989 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
7990 (func
< 0 || func
> 3) ||
7991 (vector
< 0 || vector
> 0x1f))
7994 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
7999 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
8001 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
8002 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
8005 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
8009 nw64(ESPC_PIO_STAT
, frame
);
8013 frame
= nr64(ESPC_PIO_STAT
);
8014 if (frame
& ESPC_PIO_STAT_READ_END
)
8017 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8018 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8019 (unsigned long long) frame
);
8024 nw64(ESPC_PIO_STAT
, frame
);
8028 frame
= nr64(ESPC_PIO_STAT
);
8029 if (frame
& ESPC_PIO_STAT_READ_END
)
8032 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8033 dev_err(np
->device
, "EEPROM read timeout frame[%llx]\n",
8034 (unsigned long long) frame
);
8038 frame
= nr64(ESPC_PIO_STAT
);
8039 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
8042 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
8044 int err
= niu_pci_eeprom_read(np
, off
);
8050 err
= niu_pci_eeprom_read(np
, off
+ 1);
8053 val
|= (err
& 0xff);
8058 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
8060 int err
= niu_pci_eeprom_read(np
, off
);
8067 err
= niu_pci_eeprom_read(np
, off
+ 1);
8071 val
|= (err
& 0xff) << 8;
8076 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
8083 for (i
= 0; i
< namebuf_len
; i
++) {
8084 int err
= niu_pci_eeprom_read(np
, off
+ i
);
8091 if (i
>= namebuf_len
)
8097 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
8099 struct niu_vpd
*vpd
= &np
->vpd
;
8100 int len
= strlen(vpd
->version
) + 1;
8101 const char *s
= vpd
->version
;
8104 for (i
= 0; i
< len
- 5; i
++) {
8105 if (!strncmp(s
+ i
, "FCode ", 6))
8112 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
8114 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8115 "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8116 vpd
->fcode_major
, vpd
->fcode_minor
);
8117 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
8118 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
8119 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
8120 np
->flags
|= NIU_FLAGS_VPD_VALID
;
8123 /* ESPC_PIO_EN_ENABLE must be set */
8124 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
8127 unsigned int found_mask
= 0;
8128 #define FOUND_MASK_MODEL 0x00000001
8129 #define FOUND_MASK_BMODEL 0x00000002
8130 #define FOUND_MASK_VERS 0x00000004
8131 #define FOUND_MASK_MAC 0x00000008
8132 #define FOUND_MASK_NMAC 0x00000010
8133 #define FOUND_MASK_PHY 0x00000020
8134 #define FOUND_MASK_ALL 0x0000003f
8136 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8137 "VPD_SCAN: start[%x] end[%x]\n", start
, end
);
8138 while (start
< end
) {
8139 int len
, err
, instance
, type
, prop_len
;
8144 if (found_mask
== FOUND_MASK_ALL
) {
8145 niu_vpd_parse_version(np
);
8149 err
= niu_pci_eeprom_read(np
, start
+ 2);
8155 instance
= niu_pci_eeprom_read(np
, start
);
8156 type
= niu_pci_eeprom_read(np
, start
+ 3);
8157 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
8158 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
8164 if (!strcmp(namebuf
, "model")) {
8165 prop_buf
= np
->vpd
.model
;
8166 max_len
= NIU_VPD_MODEL_MAX
;
8167 found_mask
|= FOUND_MASK_MODEL
;
8168 } else if (!strcmp(namebuf
, "board-model")) {
8169 prop_buf
= np
->vpd
.board_model
;
8170 max_len
= NIU_VPD_BD_MODEL_MAX
;
8171 found_mask
|= FOUND_MASK_BMODEL
;
8172 } else if (!strcmp(namebuf
, "version")) {
8173 prop_buf
= np
->vpd
.version
;
8174 max_len
= NIU_VPD_VERSION_MAX
;
8175 found_mask
|= FOUND_MASK_VERS
;
8176 } else if (!strcmp(namebuf
, "local-mac-address")) {
8177 prop_buf
= np
->vpd
.local_mac
;
8179 found_mask
|= FOUND_MASK_MAC
;
8180 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
8181 prop_buf
= &np
->vpd
.mac_num
;
8183 found_mask
|= FOUND_MASK_NMAC
;
8184 } else if (!strcmp(namebuf
, "phy-type")) {
8185 prop_buf
= np
->vpd
.phy_type
;
8186 max_len
= NIU_VPD_PHY_TYPE_MAX
;
8187 found_mask
|= FOUND_MASK_PHY
;
8190 if (max_len
&& prop_len
> max_len
) {
8191 dev_err(np
->device
, "Property '%s' length (%d) is too long\n", namebuf
, prop_len
);
8196 u32 off
= start
+ 5 + err
;
8199 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8200 "VPD_SCAN: Reading in property [%s] len[%d]\n",
8202 for (i
= 0; i
< prop_len
; i
++)
8203 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
8212 /* ESPC_PIO_EN_ENABLE must be set */
8213 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
8218 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
8224 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
8225 u32 here
= start
+ offset
;
8228 err
= niu_pci_eeprom_read(np
, here
);
8232 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
8236 here
= start
+ offset
+ 3;
8237 end
= start
+ offset
+ err
;
8241 err
= niu_pci_vpd_scan_props(np
, here
, end
);
8242 if (err
< 0 || err
== 1)
8247 /* ESPC_PIO_EN_ENABLE must be set */
8248 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
8250 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
8253 while (start
< end
) {
8256 /* ROM header signature? */
8257 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8261 /* Apply offset to PCI data structure. */
8262 err
= niu_pci_eeprom_read16(np
, start
+ 23);
8267 /* Check for "PCIR" signature. */
8268 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8271 err
= niu_pci_eeprom_read16(np
, start
+ 2);
8275 /* Check for OBP image type. */
8276 err
= niu_pci_eeprom_read(np
, start
+ 20);
8280 err
= niu_pci_eeprom_read(np
, ret
+ 2);
8284 start
= ret
+ (err
* 512);
8288 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
8293 err
= niu_pci_eeprom_read(np
, ret
+ 0);
8303 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
8304 const char *phy_prop
)
8306 if (!strcmp(phy_prop
, "mif")) {
8307 /* 1G copper, MII */
8308 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8310 np
->mac_xcvr
= MAC_XCVR_MII
;
8311 } else if (!strcmp(phy_prop
, "xgf")) {
8312 /* 10G fiber, XPCS */
8313 np
->flags
|= (NIU_FLAGS_10G
|
8315 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8316 } else if (!strcmp(phy_prop
, "pcs")) {
8318 np
->flags
&= ~NIU_FLAGS_10G
;
8319 np
->flags
|= NIU_FLAGS_FIBER
;
8320 np
->mac_xcvr
= MAC_XCVR_PCS
;
8321 } else if (!strcmp(phy_prop
, "xgc")) {
8322 /* 10G copper, XPCS */
8323 np
->flags
|= NIU_FLAGS_10G
;
8324 np
->flags
&= ~NIU_FLAGS_FIBER
;
8325 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8326 } else if (!strcmp(phy_prop
, "xgsd") || !strcmp(phy_prop
, "gsd")) {
8327 /* 10G Serdes or 1G Serdes, default to 10G */
8328 np
->flags
|= NIU_FLAGS_10G
;
8329 np
->flags
&= ~NIU_FLAGS_FIBER
;
8330 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8331 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8338 static int niu_pci_vpd_get_nports(struct niu
*np
)
8342 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
8343 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
8344 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
8345 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
8346 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
8348 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
8349 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
8350 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
8351 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
8358 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
8360 struct net_device
*dev
= np
->dev
;
8361 struct niu_vpd
*vpd
= &np
->vpd
;
8364 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
8365 dev_err(np
->device
, "VPD MAC invalid, falling back to SPROM\n");
8367 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8371 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8372 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8373 np
->flags
|= NIU_FLAGS_10G
;
8374 np
->flags
&= ~NIU_FLAGS_FIBER
;
8375 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8376 np
->mac_xcvr
= MAC_XCVR_PCS
;
8378 np
->flags
|= NIU_FLAGS_FIBER
;
8379 np
->flags
&= ~NIU_FLAGS_10G
;
8381 if (np
->flags
& NIU_FLAGS_10G
)
8382 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8383 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8384 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
8385 NIU_FLAGS_HOTPLUG_PHY
);
8386 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8387 dev_err(np
->device
, "Illegal phy string [%s]\n",
8389 dev_err(np
->device
, "Falling back to SPROM\n");
8390 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8394 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
8396 val8
= dev
->perm_addr
[5];
8397 dev
->perm_addr
[5] += np
->port
;
8398 if (dev
->perm_addr
[5] < val8
)
8399 dev
->perm_addr
[4]++;
8401 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8404 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
8406 struct net_device
*dev
= np
->dev
;
8411 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
8412 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
8415 np
->eeprom_len
= len
;
8417 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8418 "SPROM: Image size %llu\n", (unsigned long long)val
);
8421 for (i
= 0; i
< len
; i
++) {
8422 val
= nr64(ESPC_NCR(i
));
8423 sum
+= (val
>> 0) & 0xff;
8424 sum
+= (val
>> 8) & 0xff;
8425 sum
+= (val
>> 16) & 0xff;
8426 sum
+= (val
>> 24) & 0xff;
8428 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8429 "SPROM: Checksum %x\n", (int)(sum
& 0xff));
8430 if ((sum
& 0xff) != 0xab) {
8431 dev_err(np
->device
, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum
& 0xff));
8435 val
= nr64(ESPC_PHY_TYPE
);
8438 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
8439 ESPC_PHY_TYPE_PORT0_SHIFT
;
8442 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
8443 ESPC_PHY_TYPE_PORT1_SHIFT
;
8446 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
8447 ESPC_PHY_TYPE_PORT2_SHIFT
;
8450 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
8451 ESPC_PHY_TYPE_PORT3_SHIFT
;
8454 dev_err(np
->device
, "Bogus port number %u\n",
8458 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8459 "SPROM: PHY type %x\n", val8
);
8462 case ESPC_PHY_TYPE_1G_COPPER
:
8463 /* 1G copper, MII */
8464 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8466 np
->mac_xcvr
= MAC_XCVR_MII
;
8469 case ESPC_PHY_TYPE_1G_FIBER
:
8471 np
->flags
&= ~NIU_FLAGS_10G
;
8472 np
->flags
|= NIU_FLAGS_FIBER
;
8473 np
->mac_xcvr
= MAC_XCVR_PCS
;
8476 case ESPC_PHY_TYPE_10G_COPPER
:
8477 /* 10G copper, XPCS */
8478 np
->flags
|= NIU_FLAGS_10G
;
8479 np
->flags
&= ~NIU_FLAGS_FIBER
;
8480 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8483 case ESPC_PHY_TYPE_10G_FIBER
:
8484 /* 10G fiber, XPCS */
8485 np
->flags
|= (NIU_FLAGS_10G
|
8487 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8491 dev_err(np
->device
, "Bogus SPROM phy type %u\n", val8
);
8495 val
= nr64(ESPC_MAC_ADDR0
);
8496 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8497 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val
);
8498 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
8499 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
8500 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
8501 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
8503 val
= nr64(ESPC_MAC_ADDR1
);
8504 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8505 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val
);
8506 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
8507 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
8509 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
8510 dev_err(np
->device
, "SPROM MAC address invalid [ %pM ]\n",
8515 val8
= dev
->perm_addr
[5];
8516 dev
->perm_addr
[5] += np
->port
;
8517 if (dev
->perm_addr
[5] < val8
)
8518 dev
->perm_addr
[4]++;
8520 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8522 val
= nr64(ESPC_MOD_STR_LEN
);
8523 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8524 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8528 for (i
= 0; i
< val
; i
+= 4) {
8529 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
8531 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
8532 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
8533 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
8534 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
8536 np
->vpd
.model
[val
] = '\0';
8538 val
= nr64(ESPC_BD_MOD_STR_LEN
);
8539 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8540 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val
);
8544 for (i
= 0; i
< val
; i
+= 4) {
8545 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
8547 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
8548 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
8549 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
8550 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
8552 np
->vpd
.board_model
[val
] = '\0';
8555 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
8556 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
8557 "SPROM: NUM_PORTS_MACS[%d]\n", np
->vpd
.mac_num
);
8562 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
8564 struct niu_parent
*parent
= np
->parent
;
8567 np
->flags
|= NIU_FLAGS_XMAC
;
8569 if (!parent
->num_ports
) {
8570 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8571 parent
->num_ports
= 2;
8573 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
8574 if (!parent
->num_ports
) {
8575 /* Fall back to SPROM as last resort.
8576 * This will fail on most cards.
8578 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
8579 ESPC_NUM_PORTS_MACS_VAL
;
8581 /* All of the current probing methods fail on
8582 * Maramba on-board parts.
8584 if (!parent
->num_ports
)
8585 parent
->num_ports
= 4;
8590 if (np
->port
>= parent
->num_ports
)
8596 static int __devinit
phy_record(struct niu_parent
*parent
,
8597 struct phy_probe_info
*p
,
8598 int dev_id_1
, int dev_id_2
, u8 phy_port
,
8601 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
8604 if (dev_id_1
< 0 || dev_id_2
< 0)
8606 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
8607 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
8608 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
8609 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
8612 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
8616 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8618 type
== PHY_TYPE_PMA_PMD
? "PMA/PMD" :
8619 type
== PHY_TYPE_PCS
? "PCS" : "MII",
8622 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
8623 pr_err("Too many PHY ports\n");
8627 p
->phy_id
[type
][idx
] = id
;
8628 p
->phy_port
[type
][idx
] = phy_port
;
8629 p
->cur
[type
] = idx
+ 1;
8633 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
8637 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
8638 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
8641 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
8642 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
8649 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
8655 for (port
= 8; port
< 32; port
++) {
8656 if (port_has_10g(p
, port
)) {
8666 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
8669 if (p
->cur
[PHY_TYPE_MII
])
8670 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
8672 return p
->cur
[PHY_TYPE_MII
];
8675 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
8677 int num_ports
= parent
->num_ports
;
8680 for (i
= 0; i
< num_ports
; i
++) {
8681 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
8682 parent
->txchan_per_port
[i
] = (16 / num_ports
);
8684 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8686 parent
->rxchan_per_port
[i
],
8687 parent
->txchan_per_port
[i
]);
8691 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
8692 int num_10g
, int num_1g
)
8694 int num_ports
= parent
->num_ports
;
8695 int rx_chans_per_10g
, rx_chans_per_1g
;
8696 int tx_chans_per_10g
, tx_chans_per_1g
;
8697 int i
, tot_rx
, tot_tx
;
8699 if (!num_10g
|| !num_1g
) {
8700 rx_chans_per_10g
= rx_chans_per_1g
=
8701 (NIU_NUM_RXCHAN
/ num_ports
);
8702 tx_chans_per_10g
= tx_chans_per_1g
=
8703 (NIU_NUM_TXCHAN
/ num_ports
);
8705 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
8706 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
8707 (rx_chans_per_1g
* num_1g
)) /
8710 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
8711 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
8712 (tx_chans_per_1g
* num_1g
)) /
8716 tot_rx
= tot_tx
= 0;
8717 for (i
= 0; i
< num_ports
; i
++) {
8718 int type
= phy_decode(parent
->port_phy
, i
);
8720 if (type
== PORT_TYPE_10G
) {
8721 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
8722 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
8724 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
8725 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
8727 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n",
8729 parent
->rxchan_per_port
[i
],
8730 parent
->txchan_per_port
[i
]);
8731 tot_rx
+= parent
->rxchan_per_port
[i
];
8732 tot_tx
+= parent
->txchan_per_port
[i
];
8735 if (tot_rx
> NIU_NUM_RXCHAN
) {
8736 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8737 parent
->index
, tot_rx
);
8738 for (i
= 0; i
< num_ports
; i
++)
8739 parent
->rxchan_per_port
[i
] = 1;
8741 if (tot_tx
> NIU_NUM_TXCHAN
) {
8742 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8743 parent
->index
, tot_tx
);
8744 for (i
= 0; i
< num_ports
; i
++)
8745 parent
->txchan_per_port
[i
] = 1;
8747 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
8748 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n",
8749 parent
->index
, tot_rx
, tot_tx
);
8753 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
8754 int num_10g
, int num_1g
)
8756 int i
, num_ports
= parent
->num_ports
;
8757 int rdc_group
, rdc_groups_per_port
;
8758 int rdc_channel_base
;
8761 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
8763 rdc_channel_base
= 0;
8765 for (i
= 0; i
< num_ports
; i
++) {
8766 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
8767 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
8768 int this_channel_offset
;
8770 tp
->first_table_num
= rdc_group
;
8771 tp
->num_tables
= rdc_groups_per_port
;
8772 this_channel_offset
= 0;
8773 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
8774 struct rdc_table
*rt
= &tp
->tables
[grp
];
8777 pr_info("niu%d: Port %d RDC tbl(%d) [ ",
8778 parent
->index
, i
, tp
->first_table_num
+ grp
);
8779 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
8780 rt
->rxdma_channel
[slot
] =
8781 rdc_channel_base
+ this_channel_offset
;
8783 pr_cont("%d ", rt
->rxdma_channel
[slot
]);
8785 if (++this_channel_offset
== num_channels
)
8786 this_channel_offset
= 0;
8791 parent
->rdc_default
[i
] = rdc_channel_base
;
8793 rdc_channel_base
+= num_channels
;
8794 rdc_group
+= rdc_groups_per_port
;
8798 static int __devinit
fill_phy_probe_info(struct niu
*np
,
8799 struct niu_parent
*parent
,
8800 struct phy_probe_info
*info
)
8802 unsigned long flags
;
8805 memset(info
, 0, sizeof(*info
));
8807 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8808 niu_lock_parent(np
, flags
);
8810 for (port
= 8; port
< 32; port
++) {
8811 int dev_id_1
, dev_id_2
;
8813 dev_id_1
= mdio_read(np
, port
,
8814 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
8815 dev_id_2
= mdio_read(np
, port
,
8816 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
8817 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8821 dev_id_1
= mdio_read(np
, port
,
8822 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
8823 dev_id_2
= mdio_read(np
, port
,
8824 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
8825 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8829 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
8830 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
8831 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8836 niu_unlock_parent(np
, flags
);
8841 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
8843 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
8844 int lowest_10g
, lowest_1g
;
8845 int num_10g
, num_1g
;
8849 num_10g
= num_1g
= 0;
8851 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8852 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8855 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
8856 parent
->num_ports
= 4;
8857 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8858 phy_encode(PORT_TYPE_1G
, 1) |
8859 phy_encode(PORT_TYPE_1G
, 2) |
8860 phy_encode(PORT_TYPE_1G
, 3));
8861 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8864 parent
->num_ports
= 2;
8865 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8866 phy_encode(PORT_TYPE_10G
, 1));
8867 } else if ((np
->flags
& NIU_FLAGS_XCVR_SERDES
) &&
8868 (parent
->plat_type
== PLAT_TYPE_NIU
)) {
8869 /* this is the Monza case */
8870 if (np
->flags
& NIU_FLAGS_10G
) {
8871 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8872 phy_encode(PORT_TYPE_10G
, 1));
8874 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8875 phy_encode(PORT_TYPE_1G
, 1));
8878 err
= fill_phy_probe_info(np
, parent
, info
);
8882 num_10g
= count_10g_ports(info
, &lowest_10g
);
8883 num_1g
= count_1g_ports(info
, &lowest_1g
);
8885 switch ((num_10g
<< 4) | num_1g
) {
8887 if (lowest_1g
== 10)
8888 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8889 else if (lowest_1g
== 26)
8890 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8892 goto unknown_vg_1g_port
;
8896 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8897 phy_encode(PORT_TYPE_10G
, 1) |
8898 phy_encode(PORT_TYPE_1G
, 2) |
8899 phy_encode(PORT_TYPE_1G
, 3));
8903 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8904 phy_encode(PORT_TYPE_10G
, 1));
8908 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
8912 if (lowest_1g
== 10)
8913 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8914 else if (lowest_1g
== 26)
8915 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8917 goto unknown_vg_1g_port
;
8921 if ((lowest_10g
& 0x7) == 0)
8922 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8923 phy_encode(PORT_TYPE_1G
, 1) |
8924 phy_encode(PORT_TYPE_1G
, 2) |
8925 phy_encode(PORT_TYPE_1G
, 3));
8927 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8928 phy_encode(PORT_TYPE_10G
, 1) |
8929 phy_encode(PORT_TYPE_1G
, 2) |
8930 phy_encode(PORT_TYPE_1G
, 3));
8934 if (lowest_1g
== 10)
8935 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8936 else if (lowest_1g
== 26)
8937 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8939 goto unknown_vg_1g_port
;
8941 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8942 phy_encode(PORT_TYPE_1G
, 1) |
8943 phy_encode(PORT_TYPE_1G
, 2) |
8944 phy_encode(PORT_TYPE_1G
, 3));
8948 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8954 parent
->port_phy
= val
;
8956 if (parent
->plat_type
== PLAT_TYPE_NIU
)
8957 niu_n2_divide_channels(parent
);
8959 niu_divide_channels(parent
, num_10g
, num_1g
);
8961 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
8966 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g
);
8970 static int __devinit
niu_probe_ports(struct niu
*np
)
8972 struct niu_parent
*parent
= np
->parent
;
8975 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
8976 err
= walk_phys(np
, parent
);
8980 niu_set_ldg_timer_res(np
, 2);
8981 for (i
= 0; i
<= LDN_MAX
; i
++)
8982 niu_ldn_irq_enable(np
, i
, 0);
8985 if (parent
->port_phy
== PORT_PHY_INVALID
)
8991 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
8993 struct niu_classifier
*cp
= &np
->clas
;
8995 cp
->tcam_top
= (u16
) np
->port
;
8996 cp
->tcam_sz
= np
->parent
->tcam_num_entries
/ np
->parent
->num_ports
;
8997 cp
->h1_init
= 0xffffffff;
8998 cp
->h2_init
= 0xffff;
9000 return fflp_early_init(np
);
9003 static void __devinit
niu_link_config_init(struct niu
*np
)
9005 struct niu_link_config
*lp
= &np
->link_config
;
9007 lp
->advertising
= (ADVERTISED_10baseT_Half
|
9008 ADVERTISED_10baseT_Full
|
9009 ADVERTISED_100baseT_Half
|
9010 ADVERTISED_100baseT_Full
|
9011 ADVERTISED_1000baseT_Half
|
9012 ADVERTISED_1000baseT_Full
|
9013 ADVERTISED_10000baseT_Full
|
9014 ADVERTISED_Autoneg
);
9015 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
9016 lp
->duplex
= DUPLEX_FULL
;
9017 lp
->active_duplex
= DUPLEX_INVALID
;
9020 lp
->loopback_mode
= LOOPBACK_MAC
;
9021 lp
->active_speed
= SPEED_10000
;
9022 lp
->active_duplex
= DUPLEX_FULL
;
9024 lp
->loopback_mode
= LOOPBACK_DISABLED
;
9028 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
9032 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
9033 np
->ipp_off
= 0x00000;
9034 np
->pcs_off
= 0x04000;
9035 np
->xpcs_off
= 0x02000;
9039 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
9040 np
->ipp_off
= 0x08000;
9041 np
->pcs_off
= 0x0a000;
9042 np
->xpcs_off
= 0x08000;
9046 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
9047 np
->ipp_off
= 0x04000;
9048 np
->pcs_off
= 0x0e000;
9049 np
->xpcs_off
= ~0UL;
9053 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
9054 np
->ipp_off
= 0x0c000;
9055 np
->pcs_off
= 0x12000;
9056 np
->xpcs_off
= ~0UL;
9060 dev_err(np
->device
, "Port %u is invalid, cannot compute MAC block offset\n", np
->port
);
9067 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
9069 struct msix_entry msi_vec
[NIU_NUM_LDG
];
9070 struct niu_parent
*parent
= np
->parent
;
9071 struct pci_dev
*pdev
= np
->pdev
;
9072 int i
, num_irqs
, err
;
9075 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
9076 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
9077 ldg_num_map
[i
] = first_ldg
+ i
;
9079 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
9080 parent
->txchan_per_port
[np
->port
] +
9081 (np
->port
== 0 ? 3 : 1));
9082 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
9085 for (i
= 0; i
< num_irqs
; i
++) {
9086 msi_vec
[i
].vector
= 0;
9087 msi_vec
[i
].entry
= i
;
9090 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
9092 np
->flags
&= ~NIU_FLAGS_MSIX
;
9100 np
->flags
|= NIU_FLAGS_MSIX
;
9101 for (i
= 0; i
< num_irqs
; i
++)
9102 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
9103 np
->num_ldg
= num_irqs
;
9106 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
9108 #ifdef CONFIG_SPARC64
9109 struct of_device
*op
= np
->op
;
9110 const u32
*int_prop
;
9113 int_prop
= of_get_property(op
->dev
.of_node
, "interrupts", NULL
);
9117 for (i
= 0; i
< op
->num_irqs
; i
++) {
9118 ldg_num_map
[i
] = int_prop
[i
];
9119 np
->ldg
[i
].irq
= op
->irqs
[i
];
9122 np
->num_ldg
= op
->num_irqs
;
9130 static int __devinit
niu_ldg_init(struct niu
*np
)
9132 struct niu_parent
*parent
= np
->parent
;
9133 u8 ldg_num_map
[NIU_NUM_LDG
];
9134 int first_chan
, num_chan
;
9135 int i
, err
, ldg_rotor
;
9139 np
->ldg
[0].irq
= np
->dev
->irq
;
9140 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
9141 err
= niu_n2_irq_init(np
, ldg_num_map
);
9145 niu_try_msix(np
, ldg_num_map
);
9148 for (i
= 0; i
< np
->num_ldg
; i
++) {
9149 struct niu_ldg
*lp
= &np
->ldg
[i
];
9151 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
9154 lp
->ldg_num
= ldg_num_map
[i
];
9155 lp
->timer
= 2; /* XXX */
9157 /* On N2 NIU the firmware has setup the SID mappings so they go
9158 * to the correct values that will route the LDG to the proper
9159 * interrupt in the NCU interrupt table.
9161 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
9162 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
9168 /* We adopt the LDG assignment ordering used by the N2 NIU
9169 * 'interrupt' properties because that simplifies a lot of
9170 * things. This ordering is:
9173 * MIF (if port zero)
9174 * SYSERR (if port zero)
9181 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
9187 if (ldg_rotor
== np
->num_ldg
)
9191 err
= niu_ldg_assign_ldn(np
, parent
,
9192 ldg_num_map
[ldg_rotor
],
9198 if (ldg_rotor
== np
->num_ldg
)
9201 err
= niu_ldg_assign_ldn(np
, parent
,
9202 ldg_num_map
[ldg_rotor
],
9208 if (ldg_rotor
== np
->num_ldg
)
9214 for (i
= 0; i
< port
; i
++)
9215 first_chan
+= parent
->rxchan_per_port
[port
];
9216 num_chan
= parent
->rxchan_per_port
[port
];
9218 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9219 err
= niu_ldg_assign_ldn(np
, parent
,
9220 ldg_num_map
[ldg_rotor
],
9225 if (ldg_rotor
== np
->num_ldg
)
9230 for (i
= 0; i
< port
; i
++)
9231 first_chan
+= parent
->txchan_per_port
[port
];
9232 num_chan
= parent
->txchan_per_port
[port
];
9233 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9234 err
= niu_ldg_assign_ldn(np
, parent
,
9235 ldg_num_map
[ldg_rotor
],
9240 if (ldg_rotor
== np
->num_ldg
)
9247 static void __devexit
niu_ldg_free(struct niu
*np
)
9249 if (np
->flags
& NIU_FLAGS_MSIX
)
9250 pci_disable_msix(np
->pdev
);
9253 static int __devinit
niu_get_of_props(struct niu
*np
)
9255 #ifdef CONFIG_SPARC64
9256 struct net_device
*dev
= np
->dev
;
9257 struct device_node
*dp
;
9258 const char *phy_type
;
9263 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9264 dp
= np
->op
->dev
.of_node
;
9266 dp
= pci_device_to_OF_node(np
->pdev
);
9268 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
9270 netdev_err(dev
, "%s: OF node lacks phy-type property\n",
9275 if (!strcmp(phy_type
, "none"))
9278 strcpy(np
->vpd
.phy_type
, phy_type
);
9280 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
9281 netdev_err(dev
, "%s: Illegal phy string [%s]\n",
9282 dp
->full_name
, np
->vpd
.phy_type
);
9286 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
9288 netdev_err(dev
, "%s: OF node lacks local-mac-address property\n",
9292 if (prop_len
!= dev
->addr_len
) {
9293 netdev_err(dev
, "%s: OF MAC address prop len (%d) is wrong\n",
9294 dp
->full_name
, prop_len
);
9296 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
9297 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
9298 netdev_err(dev
, "%s: OF MAC address is invalid\n",
9300 netdev_err(dev
, "%s: [ %pM ]\n", dp
->full_name
, dev
->perm_addr
);
9304 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
9306 model
= of_get_property(dp
, "model", &prop_len
);
9309 strcpy(np
->vpd
.model
, model
);
9311 if (of_find_property(dp
, "hot-swappable-phy", &prop_len
)) {
9312 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
9313 NIU_FLAGS_HOTPLUG_PHY
);
9322 static int __devinit
niu_get_invariants(struct niu
*np
)
9324 int err
, have_props
;
9327 err
= niu_get_of_props(np
);
9333 err
= niu_init_mac_ipp_pcs_base(np
);
9338 err
= niu_get_and_validate_port(np
);
9343 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9346 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
9347 offset
= niu_pci_vpd_offset(np
);
9348 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9349 "%s() VPD offset [%08x]\n", __func__
, offset
);
9351 niu_pci_vpd_fetch(np
, offset
);
9352 nw64(ESPC_PIO_EN
, 0);
9354 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
9355 niu_pci_vpd_validate(np
);
9356 err
= niu_get_and_validate_port(np
);
9361 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
9362 err
= niu_get_and_validate_port(np
);
9365 err
= niu_pci_probe_sprom(np
);
9371 err
= niu_probe_ports(np
);
9377 niu_classifier_swstate_init(np
);
9378 niu_link_config_init(np
);
9380 err
= niu_determine_phy_disposition(np
);
9382 err
= niu_init_link(np
);
9387 static LIST_HEAD(niu_parent_list
);
9388 static DEFINE_MUTEX(niu_parent_lock
);
9389 static int niu_parent_index
;
9391 static ssize_t
show_port_phy(struct device
*dev
,
9392 struct device_attribute
*attr
, char *buf
)
9394 struct platform_device
*plat_dev
= to_platform_device(dev
);
9395 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9396 u32 port_phy
= p
->port_phy
;
9397 char *orig_buf
= buf
;
9400 if (port_phy
== PORT_PHY_UNKNOWN
||
9401 port_phy
== PORT_PHY_INVALID
)
9404 for (i
= 0; i
< p
->num_ports
; i
++) {
9405 const char *type_str
;
9408 type
= phy_decode(port_phy
, i
);
9409 if (type
== PORT_TYPE_10G
)
9414 (i
== 0) ? "%s" : " %s",
9417 buf
+= sprintf(buf
, "\n");
9418 return buf
- orig_buf
;
9421 static ssize_t
show_plat_type(struct device
*dev
,
9422 struct device_attribute
*attr
, char *buf
)
9424 struct platform_device
*plat_dev
= to_platform_device(dev
);
9425 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9426 const char *type_str
;
9428 switch (p
->plat_type
) {
9429 case PLAT_TYPE_ATLAS
:
9435 case PLAT_TYPE_VF_P0
:
9438 case PLAT_TYPE_VF_P1
:
9442 type_str
= "unknown";
9446 return sprintf(buf
, "%s\n", type_str
);
9449 static ssize_t
__show_chan_per_port(struct device
*dev
,
9450 struct device_attribute
*attr
, char *buf
,
9453 struct platform_device
*plat_dev
= to_platform_device(dev
);
9454 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9455 char *orig_buf
= buf
;
9459 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
9461 for (i
= 0; i
< p
->num_ports
; i
++) {
9463 (i
== 0) ? "%d" : " %d",
9466 buf
+= sprintf(buf
, "\n");
9468 return buf
- orig_buf
;
9471 static ssize_t
show_rxchan_per_port(struct device
*dev
,
9472 struct device_attribute
*attr
, char *buf
)
9474 return __show_chan_per_port(dev
, attr
, buf
, 1);
9477 static ssize_t
show_txchan_per_port(struct device
*dev
,
9478 struct device_attribute
*attr
, char *buf
)
9480 return __show_chan_per_port(dev
, attr
, buf
, 1);
9483 static ssize_t
show_num_ports(struct device
*dev
,
9484 struct device_attribute
*attr
, char *buf
)
9486 struct platform_device
*plat_dev
= to_platform_device(dev
);
9487 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9489 return sprintf(buf
, "%d\n", p
->num_ports
);
9492 static struct device_attribute niu_parent_attributes
[] = {
9493 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
9494 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
9495 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
9496 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
9497 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
9501 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
9502 union niu_parent_id
*id
,
9505 struct platform_device
*plat_dev
;
9506 struct niu_parent
*p
;
9509 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
9511 if (IS_ERR(plat_dev
))
9514 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
9515 int err
= device_create_file(&plat_dev
->dev
,
9516 &niu_parent_attributes
[i
]);
9518 goto fail_unregister
;
9521 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
9523 goto fail_unregister
;
9525 p
->index
= niu_parent_index
++;
9527 plat_dev
->dev
.platform_data
= p
;
9528 p
->plat_dev
= plat_dev
;
9530 memcpy(&p
->id
, id
, sizeof(*id
));
9531 p
->plat_type
= ptype
;
9532 INIT_LIST_HEAD(&p
->list
);
9533 atomic_set(&p
->refcnt
, 0);
9534 list_add(&p
->list
, &niu_parent_list
);
9535 spin_lock_init(&p
->lock
);
9537 p
->rxdma_clock_divider
= 7500;
9539 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
9540 if (p
->plat_type
== PLAT_TYPE_NIU
)
9541 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
9543 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
9544 int index
= i
- CLASS_CODE_USER_PROG1
;
9546 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
9547 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
9550 (FLOW_KEY_L4_BYTE12
<<
9551 FLOW_KEY_L4_0_SHIFT
) |
9552 (FLOW_KEY_L4_BYTE12
<<
9553 FLOW_KEY_L4_1_SHIFT
));
9556 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
9557 p
->ldg_map
[i
] = LDG_INVALID
;
9562 platform_device_unregister(plat_dev
);
9566 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
9567 union niu_parent_id
*id
,
9570 struct niu_parent
*p
, *tmp
;
9571 int port
= np
->port
;
9573 mutex_lock(&niu_parent_lock
);
9575 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
9576 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
9582 p
= niu_new_parent(np
, id
, ptype
);
9588 sprintf(port_name
, "port%d", port
);
9589 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
9593 p
->ports
[port
] = np
;
9594 atomic_inc(&p
->refcnt
);
9597 mutex_unlock(&niu_parent_lock
);
9602 static void niu_put_parent(struct niu
*np
)
9604 struct niu_parent
*p
= np
->parent
;
9608 BUG_ON(!p
|| p
->ports
[port
] != np
);
9610 netif_printk(np
, probe
, KERN_DEBUG
, np
->dev
,
9611 "%s() port[%u]\n", __func__
, port
);
9613 sprintf(port_name
, "port%d", port
);
9615 mutex_lock(&niu_parent_lock
);
9617 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
9619 p
->ports
[port
] = NULL
;
9622 if (atomic_dec_and_test(&p
->refcnt
)) {
9624 platform_device_unregister(p
->plat_dev
);
9627 mutex_unlock(&niu_parent_lock
);
9630 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
9631 u64
*handle
, gfp_t flag
)
9636 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
9642 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
9643 void *cpu_addr
, u64 handle
)
9645 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
9648 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
9649 unsigned long offset
, size_t size
,
9650 enum dma_data_direction direction
)
9652 return dma_map_page(dev
, page
, offset
, size
, direction
);
9655 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
9656 size_t size
, enum dma_data_direction direction
)
9658 dma_unmap_page(dev
, dma_address
, size
, direction
);
9661 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
9663 enum dma_data_direction direction
)
9665 return dma_map_single(dev
, cpu_addr
, size
, direction
);
9668 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
9670 enum dma_data_direction direction
)
9672 dma_unmap_single(dev
, dma_address
, size
, direction
);
9675 static const struct niu_ops niu_pci_ops
= {
9676 .alloc_coherent
= niu_pci_alloc_coherent
,
9677 .free_coherent
= niu_pci_free_coherent
,
9678 .map_page
= niu_pci_map_page
,
9679 .unmap_page
= niu_pci_unmap_page
,
9680 .map_single
= niu_pci_map_single
,
9681 .unmap_single
= niu_pci_unmap_single
,
9684 static void __devinit
niu_driver_version(void)
9686 static int niu_version_printed
;
9688 if (niu_version_printed
++ == 0)
9689 pr_info("%s", version
);
9692 static struct net_device
* __devinit
niu_alloc_and_init(
9693 struct device
*gen_dev
, struct pci_dev
*pdev
,
9694 struct of_device
*op
, const struct niu_ops
*ops
,
9697 struct net_device
*dev
;
9700 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
9702 dev_err(gen_dev
, "Etherdev alloc failed, aborting\n");
9706 SET_NETDEV_DEV(dev
, gen_dev
);
9708 np
= netdev_priv(dev
);
9712 np
->device
= gen_dev
;
9715 np
->msg_enable
= niu_debug
;
9717 spin_lock_init(&np
->lock
);
9718 INIT_WORK(&np
->reset_task
, niu_reset_task
);
9725 static const struct net_device_ops niu_netdev_ops
= {
9726 .ndo_open
= niu_open
,
9727 .ndo_stop
= niu_close
,
9728 .ndo_start_xmit
= niu_start_xmit
,
9729 .ndo_get_stats
= niu_get_stats
,
9730 .ndo_set_multicast_list
= niu_set_rx_mode
,
9731 .ndo_validate_addr
= eth_validate_addr
,
9732 .ndo_set_mac_address
= niu_set_mac_addr
,
9733 .ndo_do_ioctl
= niu_ioctl
,
9734 .ndo_tx_timeout
= niu_tx_timeout
,
9735 .ndo_change_mtu
= niu_change_mtu
,
9738 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
9740 dev
->netdev_ops
= &niu_netdev_ops
;
9741 dev
->ethtool_ops
= &niu_ethtool_ops
;
9742 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
9745 static void __devinit
niu_device_announce(struct niu
*np
)
9747 struct net_device
*dev
= np
->dev
;
9749 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
9751 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
9752 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9754 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9755 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9756 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
9757 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9758 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9761 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9763 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9764 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9765 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" :
9766 (np
->flags
& NIU_FLAGS_XCVR_SERDES
? "SERDES" :
9768 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9769 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9774 static void __devinit
niu_set_basic_features(struct net_device
*dev
)
9776 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
|
9777 NETIF_F_GRO
| NETIF_F_RXHASH
);
9780 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
9781 const struct pci_device_id
*ent
)
9783 union niu_parent_id parent_id
;
9784 struct net_device
*dev
;
9790 niu_driver_version();
9792 err
= pci_enable_device(pdev
);
9794 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
9798 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
9799 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
9800 dev_err(&pdev
->dev
, "Cannot find proper PCI device base addresses, aborting\n");
9802 goto err_out_disable_pdev
;
9805 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9807 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
9808 goto err_out_disable_pdev
;
9811 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
9813 dev_err(&pdev
->dev
, "Cannot find PCI Express capability, aborting\n");
9814 goto err_out_free_res
;
9817 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
9818 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
9821 goto err_out_free_res
;
9823 np
= netdev_priv(dev
);
9825 memset(&parent_id
, 0, sizeof(parent_id
));
9826 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
9827 parent_id
.pci
.bus
= pdev
->bus
->number
;
9828 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
9830 np
->parent
= niu_get_parent(np
, &parent_id
,
9834 goto err_out_free_dev
;
9837 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
9838 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
9839 val16
|= (PCI_EXP_DEVCTL_CERE
|
9840 PCI_EXP_DEVCTL_NFERE
|
9841 PCI_EXP_DEVCTL_FERE
|
9842 PCI_EXP_DEVCTL_URRE
|
9843 PCI_EXP_DEVCTL_RELAX_EN
);
9844 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
9846 dma_mask
= DMA_BIT_MASK(44);
9847 err
= pci_set_dma_mask(pdev
, dma_mask
);
9849 dev
->features
|= NETIF_F_HIGHDMA
;
9850 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
9852 dev_err(&pdev
->dev
, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n");
9853 goto err_out_release_parent
;
9856 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
9857 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
9859 dev_err(&pdev
->dev
, "No usable DMA configuration, aborting\n");
9860 goto err_out_release_parent
;
9864 niu_set_basic_features(dev
);
9866 np
->regs
= pci_ioremap_bar(pdev
, 0);
9868 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
9870 goto err_out_release_parent
;
9873 pci_set_master(pdev
);
9874 pci_save_state(pdev
);
9876 dev
->irq
= pdev
->irq
;
9878 niu_assign_netdev_ops(dev
);
9880 err
= niu_get_invariants(np
);
9883 dev_err(&pdev
->dev
, "Problem fetching invariants of chip, aborting\n");
9884 goto err_out_iounmap
;
9887 err
= register_netdev(dev
);
9889 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
9890 goto err_out_iounmap
;
9893 pci_set_drvdata(pdev
, dev
);
9895 niu_device_announce(np
);
9905 err_out_release_parent
:
9912 pci_release_regions(pdev
);
9914 err_out_disable_pdev
:
9915 pci_disable_device(pdev
);
9916 pci_set_drvdata(pdev
, NULL
);
9921 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
9923 struct net_device
*dev
= pci_get_drvdata(pdev
);
9926 struct niu
*np
= netdev_priv(dev
);
9928 unregister_netdev(dev
);
9939 pci_release_regions(pdev
);
9940 pci_disable_device(pdev
);
9941 pci_set_drvdata(pdev
, NULL
);
9945 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
9947 struct net_device
*dev
= pci_get_drvdata(pdev
);
9948 struct niu
*np
= netdev_priv(dev
);
9949 unsigned long flags
;
9951 if (!netif_running(dev
))
9954 flush_scheduled_work();
9957 del_timer_sync(&np
->timer
);
9959 spin_lock_irqsave(&np
->lock
, flags
);
9960 niu_enable_interrupts(np
, 0);
9961 spin_unlock_irqrestore(&np
->lock
, flags
);
9963 netif_device_detach(dev
);
9965 spin_lock_irqsave(&np
->lock
, flags
);
9967 spin_unlock_irqrestore(&np
->lock
, flags
);
9969 pci_save_state(pdev
);
9974 static int niu_resume(struct pci_dev
*pdev
)
9976 struct net_device
*dev
= pci_get_drvdata(pdev
);
9977 struct niu
*np
= netdev_priv(dev
);
9978 unsigned long flags
;
9981 if (!netif_running(dev
))
9984 pci_restore_state(pdev
);
9986 netif_device_attach(dev
);
9988 spin_lock_irqsave(&np
->lock
, flags
);
9990 err
= niu_init_hw(np
);
9992 np
->timer
.expires
= jiffies
+ HZ
;
9993 add_timer(&np
->timer
);
9994 niu_netif_start(np
);
9997 spin_unlock_irqrestore(&np
->lock
, flags
);
10002 static struct pci_driver niu_pci_driver
= {
10003 .name
= DRV_MODULE_NAME
,
10004 .id_table
= niu_pci_tbl
,
10005 .probe
= niu_pci_init_one
,
10006 .remove
= __devexit_p(niu_pci_remove_one
),
10007 .suspend
= niu_suspend
,
10008 .resume
= niu_resume
,
10011 #ifdef CONFIG_SPARC64
10012 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
10013 u64
*dma_addr
, gfp_t flag
)
10015 unsigned long order
= get_order(size
);
10016 unsigned long page
= __get_free_pages(flag
, order
);
10020 memset((char *)page
, 0, PAGE_SIZE
<< order
);
10021 *dma_addr
= __pa(page
);
10023 return (void *) page
;
10026 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
10027 void *cpu_addr
, u64 handle
)
10029 unsigned long order
= get_order(size
);
10031 free_pages((unsigned long) cpu_addr
, order
);
10034 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
10035 unsigned long offset
, size_t size
,
10036 enum dma_data_direction direction
)
10038 return page_to_phys(page
) + offset
;
10041 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
10042 size_t size
, enum dma_data_direction direction
)
10044 /* Nothing to do. */
10047 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
10049 enum dma_data_direction direction
)
10051 return __pa(cpu_addr
);
10054 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
10056 enum dma_data_direction direction
)
10058 /* Nothing to do. */
10061 static const struct niu_ops niu_phys_ops
= {
10062 .alloc_coherent
= niu_phys_alloc_coherent
,
10063 .free_coherent
= niu_phys_free_coherent
,
10064 .map_page
= niu_phys_map_page
,
10065 .unmap_page
= niu_phys_unmap_page
,
10066 .map_single
= niu_phys_map_single
,
10067 .unmap_single
= niu_phys_unmap_single
,
10070 static int __devinit
niu_of_probe(struct of_device
*op
,
10071 const struct of_device_id
*match
)
10073 union niu_parent_id parent_id
;
10074 struct net_device
*dev
;
10079 niu_driver_version();
10081 reg
= of_get_property(op
->dev
.of_node
, "reg", NULL
);
10083 dev_err(&op
->dev
, "%s: No 'reg' property, aborting\n",
10084 op
->dev
.of_node
->full_name
);
10088 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
10089 &niu_phys_ops
, reg
[0] & 0x1);
10094 np
= netdev_priv(dev
);
10096 memset(&parent_id
, 0, sizeof(parent_id
));
10097 parent_id
.of
= of_get_parent(op
->dev
.of_node
);
10099 np
->parent
= niu_get_parent(np
, &parent_id
,
10103 goto err_out_free_dev
;
10106 niu_set_basic_features(dev
);
10108 np
->regs
= of_ioremap(&op
->resource
[1], 0,
10109 resource_size(&op
->resource
[1]),
10112 dev_err(&op
->dev
, "Cannot map device registers, aborting\n");
10114 goto err_out_release_parent
;
10117 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
10118 resource_size(&op
->resource
[2]),
10120 if (!np
->vir_regs_1
) {
10121 dev_err(&op
->dev
, "Cannot map device vir registers 1, aborting\n");
10123 goto err_out_iounmap
;
10126 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
10127 resource_size(&op
->resource
[3]),
10129 if (!np
->vir_regs_2
) {
10130 dev_err(&op
->dev
, "Cannot map device vir registers 2, aborting\n");
10132 goto err_out_iounmap
;
10135 niu_assign_netdev_ops(dev
);
10137 err
= niu_get_invariants(np
);
10139 if (err
!= -ENODEV
)
10140 dev_err(&op
->dev
, "Problem fetching invariants of chip, aborting\n");
10141 goto err_out_iounmap
;
10144 err
= register_netdev(dev
);
10146 dev_err(&op
->dev
, "Cannot register net device, aborting\n");
10147 goto err_out_iounmap
;
10150 dev_set_drvdata(&op
->dev
, dev
);
10152 niu_device_announce(np
);
10157 if (np
->vir_regs_1
) {
10158 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10159 resource_size(&op
->resource
[2]));
10160 np
->vir_regs_1
= NULL
;
10163 if (np
->vir_regs_2
) {
10164 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10165 resource_size(&op
->resource
[3]));
10166 np
->vir_regs_2
= NULL
;
10170 of_iounmap(&op
->resource
[1], np
->regs
,
10171 resource_size(&op
->resource
[1]));
10175 err_out_release_parent
:
10176 niu_put_parent(np
);
10185 static int __devexit
niu_of_remove(struct of_device
*op
)
10187 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
10190 struct niu
*np
= netdev_priv(dev
);
10192 unregister_netdev(dev
);
10194 if (np
->vir_regs_1
) {
10195 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10196 resource_size(&op
->resource
[2]));
10197 np
->vir_regs_1
= NULL
;
10200 if (np
->vir_regs_2
) {
10201 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10202 resource_size(&op
->resource
[3]));
10203 np
->vir_regs_2
= NULL
;
10207 of_iounmap(&op
->resource
[1], np
->regs
,
10208 resource_size(&op
->resource
[1]));
10214 niu_put_parent(np
);
10217 dev_set_drvdata(&op
->dev
, NULL
);
10222 static const struct of_device_id niu_match
[] = {
10225 .compatible
= "SUNW,niusl",
10229 MODULE_DEVICE_TABLE(of
, niu_match
);
10231 static struct of_platform_driver niu_of_driver
= {
10234 .owner
= THIS_MODULE
,
10235 .of_match_table
= niu_match
,
10237 .probe
= niu_of_probe
,
10238 .remove
= __devexit_p(niu_of_remove
),
10241 #endif /* CONFIG_SPARC64 */
10243 static int __init
niu_init(void)
10247 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
10249 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
10251 #ifdef CONFIG_SPARC64
10252 err
= of_register_driver(&niu_of_driver
, &of_bus_type
);
10256 err
= pci_register_driver(&niu_pci_driver
);
10257 #ifdef CONFIG_SPARC64
10259 of_unregister_driver(&niu_of_driver
);
10266 static void __exit
niu_exit(void)
10268 pci_unregister_driver(&niu_pci_driver
);
10269 #ifdef CONFIG_SPARC64
10270 of_unregister_driver(&niu_of_driver
);
10274 module_init(niu_init
);
10275 module_exit(niu_exit
);