1 /* niu.c: Neptune ethernet driver.
3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
6 #include <linux/module.h>
7 #include <linux/init.h>
9 #include <linux/dma-mapping.h>
10 #include <linux/netdevice.h>
11 #include <linux/ethtool.h>
12 #include <linux/etherdevice.h>
13 #include <linux/platform_device.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/mii.h>
17 #include <linux/if_ether.h>
18 #include <linux/if_vlan.h>
21 #include <linux/ipv6.h>
22 #include <linux/log2.h>
23 #include <linux/jiffies.h>
24 #include <linux/crc32.h>
29 #include <linux/of_device.h>
34 #define DRV_MODULE_NAME "niu"
35 #define PFX DRV_MODULE_NAME ": "
36 #define DRV_MODULE_VERSION "1.0"
37 #define DRV_MODULE_RELDATE "Nov 14, 2008"
39 static char version
[] __devinitdata
=
40 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
42 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
43 MODULE_DESCRIPTION("NIU ethernet driver");
44 MODULE_LICENSE("GPL");
45 MODULE_VERSION(DRV_MODULE_VERSION
);
47 #ifndef DMA_44BIT_MASK
48 #define DMA_44BIT_MASK 0x00000fffffffffffULL
52 static u64
readq(void __iomem
*reg
)
54 return ((u64
) readl(reg
)) | (((u64
) readl(reg
+ 4UL)) << 32);
57 static void writeq(u64 val
, void __iomem
*reg
)
59 writel(val
& 0xffffffff, reg
);
60 writel(val
>> 32, reg
+ 0x4UL
);
64 static struct pci_device_id niu_pci_tbl
[] = {
65 {PCI_DEVICE(PCI_VENDOR_ID_SUN
, 0xabcd)},
69 MODULE_DEVICE_TABLE(pci
, niu_pci_tbl
);
71 #define NIU_TX_TIMEOUT (5 * HZ)
73 #define nr64(reg) readq(np->regs + (reg))
74 #define nw64(reg, val) writeq((val), np->regs + (reg))
76 #define nr64_mac(reg) readq(np->mac_regs + (reg))
77 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg))
80 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg))
83 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg))
86 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
88 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
91 static int debug
= -1;
92 module_param(debug
, int, 0);
93 MODULE_PARM_DESC(debug
, "NIU debug level");
95 #define niudbg(TYPE, f, a...) \
96 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
97 printk(KERN_DEBUG PFX f, ## a); \
100 #define niuinfo(TYPE, f, a...) \
101 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
102 printk(KERN_INFO PFX f, ## a); \
105 #define niuwarn(TYPE, f, a...) \
106 do { if ((np)->msg_enable & NETIF_MSG_##TYPE) \
107 printk(KERN_WARNING PFX f, ## a); \
110 #define niu_lock_parent(np, flags) \
111 spin_lock_irqsave(&np->parent->lock, flags)
112 #define niu_unlock_parent(np, flags) \
113 spin_unlock_irqrestore(&np->parent->lock, flags)
115 static int serdes_init_10g_serdes(struct niu
*np
);
117 static int __niu_wait_bits_clear_mac(struct niu
*np
, unsigned long reg
,
118 u64 bits
, int limit
, int delay
)
120 while (--limit
>= 0) {
121 u64 val
= nr64_mac(reg
);
132 static int __niu_set_and_wait_clear_mac(struct niu
*np
, unsigned long reg
,
133 u64 bits
, int limit
, int delay
,
134 const char *reg_name
)
139 err
= __niu_wait_bits_clear_mac(np
, reg
, bits
, limit
, delay
);
141 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
142 "would not clear, val[%llx]\n",
143 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
144 (unsigned long long) nr64_mac(reg
));
148 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
149 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
150 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
153 static int __niu_wait_bits_clear_ipp(struct niu
*np
, unsigned long reg
,
154 u64 bits
, int limit
, int delay
)
156 while (--limit
>= 0) {
157 u64 val
= nr64_ipp(reg
);
168 static int __niu_set_and_wait_clear_ipp(struct niu
*np
, unsigned long reg
,
169 u64 bits
, int limit
, int delay
,
170 const char *reg_name
)
179 err
= __niu_wait_bits_clear_ipp(np
, reg
, bits
, limit
, delay
);
181 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
182 "would not clear, val[%llx]\n",
183 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
184 (unsigned long long) nr64_ipp(reg
));
188 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
189 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
190 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
193 static int __niu_wait_bits_clear(struct niu
*np
, unsigned long reg
,
194 u64 bits
, int limit
, int delay
)
196 while (--limit
>= 0) {
208 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \
209 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
210 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \
213 static int __niu_set_and_wait_clear(struct niu
*np
, unsigned long reg
,
214 u64 bits
, int limit
, int delay
,
215 const char *reg_name
)
220 err
= __niu_wait_bits_clear(np
, reg
, bits
, limit
, delay
);
222 dev_err(np
->device
, PFX
"%s: bits (%llx) of register %s "
223 "would not clear, val[%llx]\n",
224 np
->dev
->name
, (unsigned long long) bits
, reg_name
,
225 (unsigned long long) nr64(reg
));
229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \
230 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \
231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \
234 static void niu_ldg_rearm(struct niu
*np
, struct niu_ldg
*lp
, int on
)
236 u64 val
= (u64
) lp
->timer
;
239 val
|= LDG_IMGMT_ARM
;
241 nw64(LDG_IMGMT(lp
->ldg_num
), val
);
244 static int niu_ldn_irq_enable(struct niu
*np
, int ldn
, int on
)
246 unsigned long mask_reg
, bits
;
249 if (ldn
< 0 || ldn
> LDN_MAX
)
253 mask_reg
= LD_IM0(ldn
);
256 mask_reg
= LD_IM1(ldn
- 64);
260 val
= nr64(mask_reg
);
270 static int niu_enable_ldn_in_ldg(struct niu
*np
, struct niu_ldg
*lp
, int on
)
272 struct niu_parent
*parent
= np
->parent
;
275 for (i
= 0; i
<= LDN_MAX
; i
++) {
278 if (parent
->ldg_map
[i
] != lp
->ldg_num
)
281 err
= niu_ldn_irq_enable(np
, i
, on
);
288 static int niu_enable_interrupts(struct niu
*np
, int on
)
292 for (i
= 0; i
< np
->num_ldg
; i
++) {
293 struct niu_ldg
*lp
= &np
->ldg
[i
];
296 err
= niu_enable_ldn_in_ldg(np
, lp
, on
);
300 for (i
= 0; i
< np
->num_ldg
; i
++)
301 niu_ldg_rearm(np
, &np
->ldg
[i
], on
);
306 static u32
phy_encode(u32 type
, int port
)
308 return (type
<< (port
* 2));
311 static u32
phy_decode(u32 val
, int port
)
313 return (val
>> (port
* 2)) & PORT_TYPE_MASK
;
316 static int mdio_wait(struct niu
*np
)
321 while (--limit
> 0) {
322 val
= nr64(MIF_FRAME_OUTPUT
);
323 if ((val
>> MIF_FRAME_OUTPUT_TA_SHIFT
) & 0x1)
324 return val
& MIF_FRAME_OUTPUT_DATA
;
332 static int mdio_read(struct niu
*np
, int port
, int dev
, int reg
)
336 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
341 nw64(MIF_FRAME_OUTPUT
, MDIO_READ_OP(port
, dev
));
342 return mdio_wait(np
);
345 static int mdio_write(struct niu
*np
, int port
, int dev
, int reg
, int data
)
349 nw64(MIF_FRAME_OUTPUT
, MDIO_ADDR_OP(port
, dev
, reg
));
354 nw64(MIF_FRAME_OUTPUT
, MDIO_WRITE_OP(port
, dev
, data
));
362 static int mii_read(struct niu
*np
, int port
, int reg
)
364 nw64(MIF_FRAME_OUTPUT
, MII_READ_OP(port
, reg
));
365 return mdio_wait(np
);
368 static int mii_write(struct niu
*np
, int port
, int reg
, int data
)
372 nw64(MIF_FRAME_OUTPUT
, MII_WRITE_OP(port
, reg
, data
));
380 static int esr2_set_tx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
384 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
385 ESR2_TI_PLL_TX_CFG_L(channel
),
388 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
389 ESR2_TI_PLL_TX_CFG_H(channel
),
394 static int esr2_set_rx_cfg(struct niu
*np
, unsigned long channel
, u32 val
)
398 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
399 ESR2_TI_PLL_RX_CFG_L(channel
),
402 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
403 ESR2_TI_PLL_RX_CFG_H(channel
),
408 /* Mode is always 10G fiber. */
409 static int serdes_init_niu_10g_fiber(struct niu
*np
)
411 struct niu_link_config
*lp
= &np
->link_config
;
415 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
416 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
417 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
418 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
420 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
421 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
423 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
424 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
426 tx_cfg
|= PLL_TX_CFG_ENTEST
;
427 rx_cfg
|= PLL_RX_CFG_ENTEST
;
430 /* Initialize all 4 lanes of the SERDES. */
431 for (i
= 0; i
< 4; i
++) {
432 int err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
437 for (i
= 0; i
< 4; i
++) {
438 int err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
446 static int serdes_init_niu_1g_serdes(struct niu
*np
)
448 struct niu_link_config
*lp
= &np
->link_config
;
449 u16 pll_cfg
, pll_sts
;
451 u64
uninitialized_var(sig
), mask
, val
;
456 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
|
457 PLL_TX_CFG_RATE_HALF
);
458 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
459 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
460 PLL_RX_CFG_RATE_HALF
);
463 rx_cfg
|= PLL_RX_CFG_EQ_LP_ADAPTIVE
;
465 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
466 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
468 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
469 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
471 tx_cfg
|= PLL_TX_CFG_ENTEST
;
472 rx_cfg
|= PLL_RX_CFG_ENTEST
;
475 /* Initialize PLL for 1G */
476 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_8X
);
478 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
479 ESR2_TI_PLL_CFG_L
, pll_cfg
);
481 dev_err(np
->device
, PFX
"NIU Port %d "
482 "serdes_init_niu_1g_serdes: "
483 "mdio write to ESR2_TI_PLL_CFG_L failed", np
->port
);
487 pll_sts
= PLL_CFG_ENPLL
;
489 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
490 ESR2_TI_PLL_STS_L
, pll_sts
);
492 dev_err(np
->device
, PFX
"NIU Port %d "
493 "serdes_init_niu_1g_serdes: "
494 "mdio write to ESR2_TI_PLL_STS_L failed", np
->port
);
500 /* Initialize all 4 lanes of the SERDES. */
501 for (i
= 0; i
< 4; i
++) {
502 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
507 for (i
= 0; i
< 4; i
++) {
508 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
515 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
520 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
528 while (max_retry
--) {
529 sig
= nr64(ESR_INT_SIGNALS
);
530 if ((sig
& mask
) == val
)
536 if ((sig
& mask
) != val
) {
537 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
538 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
545 static int serdes_init_niu_10g_serdes(struct niu
*np
)
547 struct niu_link_config
*lp
= &np
->link_config
;
548 u32 tx_cfg
, rx_cfg
, pll_cfg
, pll_sts
;
550 u64
uninitialized_var(sig
), mask
, val
;
554 tx_cfg
= (PLL_TX_CFG_ENTX
| PLL_TX_CFG_SWING_1375MV
);
555 rx_cfg
= (PLL_RX_CFG_ENRX
| PLL_RX_CFG_TERM_0P8VDDT
|
556 PLL_RX_CFG_ALIGN_ENA
| PLL_RX_CFG_LOS_LTHRESH
|
557 PLL_RX_CFG_EQ_LP_ADAPTIVE
);
559 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
560 u16 test_cfg
= PLL_TEST_CFG_LOOPBACK_CML_DIS
;
562 mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
563 ESR2_TI_PLL_TEST_CFG_L
, test_cfg
);
565 tx_cfg
|= PLL_TX_CFG_ENTEST
;
566 rx_cfg
|= PLL_RX_CFG_ENTEST
;
569 /* Initialize PLL for 10G */
570 pll_cfg
= (PLL_CFG_ENPLL
| PLL_CFG_MPY_10X
);
572 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
573 ESR2_TI_PLL_CFG_L
, pll_cfg
& 0xffff);
575 dev_err(np
->device
, PFX
"NIU Port %d "
576 "serdes_init_niu_10g_serdes: "
577 "mdio write to ESR2_TI_PLL_CFG_L failed", np
->port
);
581 pll_sts
= PLL_CFG_ENPLL
;
583 err
= mdio_write(np
, np
->port
, NIU_ESR2_DEV_ADDR
,
584 ESR2_TI_PLL_STS_L
, pll_sts
& 0xffff);
586 dev_err(np
->device
, PFX
"NIU Port %d "
587 "serdes_init_niu_10g_serdes: "
588 "mdio write to ESR2_TI_PLL_STS_L failed", np
->port
);
594 /* Initialize all 4 lanes of the SERDES. */
595 for (i
= 0; i
< 4; i
++) {
596 err
= esr2_set_tx_cfg(np
, i
, tx_cfg
);
601 for (i
= 0; i
< 4; i
++) {
602 err
= esr2_set_rx_cfg(np
, i
, rx_cfg
);
607 /* check if serdes is ready */
611 mask
= ESR_INT_SIGNALS_P0_BITS
;
612 val
= (ESR_INT_SRDY0_P0
|
622 mask
= ESR_INT_SIGNALS_P1_BITS
;
623 val
= (ESR_INT_SRDY0_P1
|
636 while (max_retry
--) {
637 sig
= nr64(ESR_INT_SIGNALS
);
638 if ((sig
& mask
) == val
)
644 if ((sig
& mask
) != val
) {
645 pr_info(PFX
"NIU Port %u signal bits [%08x] are not "
646 "[%08x] for 10G...trying 1G\n",
647 np
->port
, (int) (sig
& mask
), (int) val
);
649 /* 10G failed, try initializing at 1G */
650 err
= serdes_init_niu_1g_serdes(np
);
652 np
->flags
&= ~NIU_FLAGS_10G
;
653 np
->mac_xcvr
= MAC_XCVR_PCS
;
655 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES "
656 "Link Failed \n", np
->port
);
663 static int esr_read_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32
*val
)
667 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
, ESR_RXTX_CTRL_L(chan
));
669 *val
= (err
& 0xffff);
670 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
671 ESR_RXTX_CTRL_H(chan
));
673 *val
|= ((err
& 0xffff) << 16);
679 static int esr_read_glue0(struct niu
*np
, unsigned long chan
, u32
*val
)
683 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
684 ESR_GLUE_CTRL0_L(chan
));
686 *val
= (err
& 0xffff);
687 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
688 ESR_GLUE_CTRL0_H(chan
));
690 *val
|= ((err
& 0xffff) << 16);
697 static int esr_read_reset(struct niu
*np
, u32
*val
)
701 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
702 ESR_RXTX_RESET_CTRL_L
);
704 *val
= (err
& 0xffff);
705 err
= mdio_read(np
, np
->port
, NIU_ESR_DEV_ADDR
,
706 ESR_RXTX_RESET_CTRL_H
);
708 *val
|= ((err
& 0xffff) << 16);
715 static int esr_write_rxtx_ctrl(struct niu
*np
, unsigned long chan
, u32 val
)
719 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
720 ESR_RXTX_CTRL_L(chan
), val
& 0xffff);
722 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
723 ESR_RXTX_CTRL_H(chan
), (val
>> 16));
727 static int esr_write_glue0(struct niu
*np
, unsigned long chan
, u32 val
)
731 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
732 ESR_GLUE_CTRL0_L(chan
), val
& 0xffff);
734 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
735 ESR_GLUE_CTRL0_H(chan
), (val
>> 16));
739 static int esr_reset(struct niu
*np
)
741 u32
uninitialized_var(reset
);
744 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
745 ESR_RXTX_RESET_CTRL_L
, 0x0000);
748 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
749 ESR_RXTX_RESET_CTRL_H
, 0xffff);
754 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
755 ESR_RXTX_RESET_CTRL_L
, 0xffff);
760 err
= mdio_write(np
, np
->port
, NIU_ESR_DEV_ADDR
,
761 ESR_RXTX_RESET_CTRL_H
, 0x0000);
766 err
= esr_read_reset(np
, &reset
);
770 dev_err(np
->device
, PFX
"Port %u ESR_RESET "
771 "did not clear [%08x]\n",
779 static int serdes_init_10g(struct niu
*np
)
781 struct niu_link_config
*lp
= &np
->link_config
;
782 unsigned long ctrl_reg
, test_cfg_reg
, i
;
783 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
788 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
789 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
792 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
793 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
799 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
800 ENET_SERDES_CTRL_SDET_1
|
801 ENET_SERDES_CTRL_SDET_2
|
802 ENET_SERDES_CTRL_SDET_3
|
803 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
804 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
805 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
806 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
807 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
808 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
809 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
810 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
813 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
814 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
815 ENET_SERDES_TEST_MD_0_SHIFT
) |
816 (ENET_TEST_MD_PAD_LOOPBACK
<<
817 ENET_SERDES_TEST_MD_1_SHIFT
) |
818 (ENET_TEST_MD_PAD_LOOPBACK
<<
819 ENET_SERDES_TEST_MD_2_SHIFT
) |
820 (ENET_TEST_MD_PAD_LOOPBACK
<<
821 ENET_SERDES_TEST_MD_3_SHIFT
));
824 nw64(ctrl_reg
, ctrl_val
);
825 nw64(test_cfg_reg
, test_cfg_val
);
827 /* Initialize all 4 lanes of the SERDES. */
828 for (i
= 0; i
< 4; i
++) {
829 u32 rxtx_ctrl
, glue0
;
831 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
834 err
= esr_read_glue0(np
, i
, &glue0
);
838 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
839 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
840 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
842 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
843 ESR_GLUE_CTRL0_THCNT
|
844 ESR_GLUE_CTRL0_BLTIME
);
845 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
846 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
847 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
848 (BLTIME_300_CYCLES
<<
849 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
851 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
854 err
= esr_write_glue0(np
, i
, glue0
);
863 sig
= nr64(ESR_INT_SIGNALS
);
866 mask
= ESR_INT_SIGNALS_P0_BITS
;
867 val
= (ESR_INT_SRDY0_P0
|
877 mask
= ESR_INT_SIGNALS_P1_BITS
;
878 val
= (ESR_INT_SRDY0_P1
|
891 if ((sig
& mask
) != val
) {
892 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
893 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
896 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
897 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
900 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
)
901 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
905 static int serdes_init_1g(struct niu
*np
)
909 val
= nr64(ENET_SERDES_1_PLL_CFG
);
910 val
&= ~ENET_SERDES_PLL_FBDIV2
;
913 val
|= ENET_SERDES_PLL_HRATE0
;
916 val
|= ENET_SERDES_PLL_HRATE1
;
919 val
|= ENET_SERDES_PLL_HRATE2
;
922 val
|= ENET_SERDES_PLL_HRATE3
;
927 nw64(ENET_SERDES_1_PLL_CFG
, val
);
932 static int serdes_init_1g_serdes(struct niu
*np
)
934 struct niu_link_config
*lp
= &np
->link_config
;
935 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
936 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
938 u64 reset_val
, val_rd
;
940 val
= ENET_SERDES_PLL_HRATE0
| ENET_SERDES_PLL_HRATE1
|
941 ENET_SERDES_PLL_HRATE2
| ENET_SERDES_PLL_HRATE3
|
942 ENET_SERDES_PLL_FBDIV0
;
945 reset_val
= ENET_SERDES_RESET_0
;
946 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
947 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
948 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
951 reset_val
= ENET_SERDES_RESET_1
;
952 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
953 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
954 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
960 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
961 ENET_SERDES_CTRL_SDET_1
|
962 ENET_SERDES_CTRL_SDET_2
|
963 ENET_SERDES_CTRL_SDET_3
|
964 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
965 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
966 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
967 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
968 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
969 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
970 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
971 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
974 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
975 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
976 ENET_SERDES_TEST_MD_0_SHIFT
) |
977 (ENET_TEST_MD_PAD_LOOPBACK
<<
978 ENET_SERDES_TEST_MD_1_SHIFT
) |
979 (ENET_TEST_MD_PAD_LOOPBACK
<<
980 ENET_SERDES_TEST_MD_2_SHIFT
) |
981 (ENET_TEST_MD_PAD_LOOPBACK
<<
982 ENET_SERDES_TEST_MD_3_SHIFT
));
985 nw64(ENET_SERDES_RESET
, reset_val
);
987 val_rd
= nr64(ENET_SERDES_RESET
);
988 val_rd
&= ~reset_val
;
990 nw64(ctrl_reg
, ctrl_val
);
991 nw64(test_cfg_reg
, test_cfg_val
);
992 nw64(ENET_SERDES_RESET
, val_rd
);
995 /* Initialize all 4 lanes of the SERDES. */
996 for (i
= 0; i
< 4; i
++) {
997 u32 rxtx_ctrl
, glue0
;
999 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
1002 err
= esr_read_glue0(np
, i
, &glue0
);
1006 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
1007 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
1008 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
1010 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
1011 ESR_GLUE_CTRL0_THCNT
|
1012 ESR_GLUE_CTRL0_BLTIME
);
1013 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
1014 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
1015 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
1016 (BLTIME_300_CYCLES
<<
1017 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
1019 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
1022 err
= esr_write_glue0(np
, i
, glue0
);
1028 sig
= nr64(ESR_INT_SIGNALS
);
1031 val
= (ESR_INT_SRDY0_P0
| ESR_INT_DET0_P0
);
1036 val
= (ESR_INT_SRDY0_P1
| ESR_INT_DET0_P1
);
1044 if ((sig
& mask
) != val
) {
1045 dev_err(np
->device
, PFX
"Port %u signal bits [%08x] are not "
1046 "[%08x]\n", np
->port
, (int) (sig
& mask
), (int) val
);
1053 static int link_status_1g_serdes(struct niu
*np
, int *link_up_p
)
1055 struct niu_link_config
*lp
= &np
->link_config
;
1059 unsigned long flags
;
1063 current_speed
= SPEED_INVALID
;
1064 current_duplex
= DUPLEX_INVALID
;
1066 spin_lock_irqsave(&np
->lock
, flags
);
1068 val
= nr64_pcs(PCS_MII_STAT
);
1070 if (val
& PCS_MII_STAT_LINK_STATUS
) {
1072 current_speed
= SPEED_1000
;
1073 current_duplex
= DUPLEX_FULL
;
1076 lp
->active_speed
= current_speed
;
1077 lp
->active_duplex
= current_duplex
;
1078 spin_unlock_irqrestore(&np
->lock
, flags
);
1080 *link_up_p
= link_up
;
1084 static int link_status_10g_serdes(struct niu
*np
, int *link_up_p
)
1086 unsigned long flags
;
1087 struct niu_link_config
*lp
= &np
->link_config
;
1094 if (!(np
->flags
& NIU_FLAGS_10G
))
1095 return link_status_1g_serdes(np
, link_up_p
);
1097 current_speed
= SPEED_INVALID
;
1098 current_duplex
= DUPLEX_INVALID
;
1099 spin_lock_irqsave(&np
->lock
, flags
);
1101 val
= nr64_xpcs(XPCS_STATUS(0));
1102 val2
= nr64_mac(XMAC_INTER2
);
1103 if (val2
& 0x01000000)
1106 if ((val
& 0x1000ULL
) && link_ok
) {
1108 current_speed
= SPEED_10000
;
1109 current_duplex
= DUPLEX_FULL
;
1111 lp
->active_speed
= current_speed
;
1112 lp
->active_duplex
= current_duplex
;
1113 spin_unlock_irqrestore(&np
->lock
, flags
);
1114 *link_up_p
= link_up
;
1118 static int link_status_mii(struct niu
*np
, int *link_up_p
)
1120 struct niu_link_config
*lp
= &np
->link_config
;
1122 int bmsr
, advert
, ctrl1000
, stat1000
, lpa
, bmcr
, estatus
;
1123 int supported
, advertising
, active_speed
, active_duplex
;
1125 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1126 if (unlikely(err
< 0))
1130 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1131 if (unlikely(err
< 0))
1135 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1136 if (unlikely(err
< 0))
1140 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1141 if (unlikely(err
< 0))
1145 if (likely(bmsr
& BMSR_ESTATEN
)) {
1146 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1147 if (unlikely(err
< 0))
1151 err
= mii_read(np
, np
->phy_addr
, MII_CTRL1000
);
1152 if (unlikely(err
< 0))
1156 err
= mii_read(np
, np
->phy_addr
, MII_STAT1000
);
1157 if (unlikely(err
< 0))
1161 estatus
= ctrl1000
= stat1000
= 0;
1164 if (bmsr
& BMSR_ANEGCAPABLE
)
1165 supported
|= SUPPORTED_Autoneg
;
1166 if (bmsr
& BMSR_10HALF
)
1167 supported
|= SUPPORTED_10baseT_Half
;
1168 if (bmsr
& BMSR_10FULL
)
1169 supported
|= SUPPORTED_10baseT_Full
;
1170 if (bmsr
& BMSR_100HALF
)
1171 supported
|= SUPPORTED_100baseT_Half
;
1172 if (bmsr
& BMSR_100FULL
)
1173 supported
|= SUPPORTED_100baseT_Full
;
1174 if (estatus
& ESTATUS_1000_THALF
)
1175 supported
|= SUPPORTED_1000baseT_Half
;
1176 if (estatus
& ESTATUS_1000_TFULL
)
1177 supported
|= SUPPORTED_1000baseT_Full
;
1178 lp
->supported
= supported
;
1181 if (advert
& ADVERTISE_10HALF
)
1182 advertising
|= ADVERTISED_10baseT_Half
;
1183 if (advert
& ADVERTISE_10FULL
)
1184 advertising
|= ADVERTISED_10baseT_Full
;
1185 if (advert
& ADVERTISE_100HALF
)
1186 advertising
|= ADVERTISED_100baseT_Half
;
1187 if (advert
& ADVERTISE_100FULL
)
1188 advertising
|= ADVERTISED_100baseT_Full
;
1189 if (ctrl1000
& ADVERTISE_1000HALF
)
1190 advertising
|= ADVERTISED_1000baseT_Half
;
1191 if (ctrl1000
& ADVERTISE_1000FULL
)
1192 advertising
|= ADVERTISED_1000baseT_Full
;
1194 if (bmcr
& BMCR_ANENABLE
) {
1197 lp
->active_autoneg
= 1;
1198 advertising
|= ADVERTISED_Autoneg
;
1201 neg1000
= (ctrl1000
<< 2) & stat1000
;
1203 if (neg1000
& (LPA_1000FULL
| LPA_1000HALF
))
1204 active_speed
= SPEED_1000
;
1205 else if (neg
& LPA_100
)
1206 active_speed
= SPEED_100
;
1207 else if (neg
& (LPA_10HALF
| LPA_10FULL
))
1208 active_speed
= SPEED_10
;
1210 active_speed
= SPEED_INVALID
;
1212 if ((neg1000
& LPA_1000FULL
) || (neg
& LPA_DUPLEX
))
1213 active_duplex
= DUPLEX_FULL
;
1214 else if (active_speed
!= SPEED_INVALID
)
1215 active_duplex
= DUPLEX_HALF
;
1217 active_duplex
= DUPLEX_INVALID
;
1219 lp
->active_autoneg
= 0;
1221 if ((bmcr
& BMCR_SPEED1000
) && !(bmcr
& BMCR_SPEED100
))
1222 active_speed
= SPEED_1000
;
1223 else if (bmcr
& BMCR_SPEED100
)
1224 active_speed
= SPEED_100
;
1226 active_speed
= SPEED_10
;
1228 if (bmcr
& BMCR_FULLDPLX
)
1229 active_duplex
= DUPLEX_FULL
;
1231 active_duplex
= DUPLEX_HALF
;
1234 lp
->active_advertising
= advertising
;
1235 lp
->active_speed
= active_speed
;
1236 lp
->active_duplex
= active_duplex
;
1237 *link_up_p
= !!(bmsr
& BMSR_LSTATUS
);
1242 static int link_status_1g_rgmii(struct niu
*np
, int *link_up_p
)
1244 struct niu_link_config
*lp
= &np
->link_config
;
1245 u16 current_speed
, bmsr
;
1246 unsigned long flags
;
1251 current_speed
= SPEED_INVALID
;
1252 current_duplex
= DUPLEX_INVALID
;
1254 spin_lock_irqsave(&np
->lock
, flags
);
1258 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1263 if (bmsr
& BMSR_LSTATUS
) {
1264 u16 adv
, lpa
, common
, estat
;
1266 err
= mii_read(np
, np
->phy_addr
, MII_ADVERTISE
);
1271 err
= mii_read(np
, np
->phy_addr
, MII_LPA
);
1278 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1283 current_speed
= SPEED_1000
;
1284 current_duplex
= DUPLEX_FULL
;
1287 lp
->active_speed
= current_speed
;
1288 lp
->active_duplex
= current_duplex
;
1292 spin_unlock_irqrestore(&np
->lock
, flags
);
1294 *link_up_p
= link_up
;
1298 static int link_status_1g(struct niu
*np
, int *link_up_p
)
1300 struct niu_link_config
*lp
= &np
->link_config
;
1301 unsigned long flags
;
1304 spin_lock_irqsave(&np
->lock
, flags
);
1306 err
= link_status_mii(np
, link_up_p
);
1307 lp
->supported
|= SUPPORTED_TP
;
1308 lp
->active_advertising
|= ADVERTISED_TP
;
1310 spin_unlock_irqrestore(&np
->lock
, flags
);
1314 static int bcm8704_reset(struct niu
*np
)
1318 err
= mdio_read(np
, np
->phy_addr
,
1319 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1320 if (err
< 0 || err
== 0xffff)
1323 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1329 while (--limit
>= 0) {
1330 err
= mdio_read(np
, np
->phy_addr
,
1331 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
1334 if (!(err
& BMCR_RESET
))
1338 dev_err(np
->device
, PFX
"Port %u PHY will not reset "
1339 "(bmcr=%04x)\n", np
->port
, (err
& 0xffff));
1345 /* When written, certain PHY registers need to be read back twice
1346 * in order for the bits to settle properly.
1348 static int bcm8704_user_dev3_readback(struct niu
*np
, int reg
)
1350 int err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1353 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, reg
);
1359 static int bcm8706_init_user_dev3(struct niu
*np
)
1364 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1365 BCM8704_USER_OPT_DIGITAL_CTRL
);
1368 err
&= ~USER_ODIG_CTRL_GPIOS
;
1369 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1370 err
|= USER_ODIG_CTRL_RESV2
;
1371 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1372 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1381 static int bcm8704_init_user_dev3(struct niu
*np
)
1385 err
= mdio_write(np
, np
->phy_addr
,
1386 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_CONTROL
,
1387 (USER_CONTROL_OPTXRST_LVL
|
1388 USER_CONTROL_OPBIASFLT_LVL
|
1389 USER_CONTROL_OBTMPFLT_LVL
|
1390 USER_CONTROL_OPPRFLT_LVL
|
1391 USER_CONTROL_OPTXFLT_LVL
|
1392 USER_CONTROL_OPRXLOS_LVL
|
1393 USER_CONTROL_OPRXFLT_LVL
|
1394 USER_CONTROL_OPTXON_LVL
|
1395 (0x3f << USER_CONTROL_RES1_SHIFT
)));
1399 err
= mdio_write(np
, np
->phy_addr
,
1400 BCM8704_USER_DEV3_ADDR
, BCM8704_USER_PMD_TX_CONTROL
,
1401 (USER_PMD_TX_CTL_XFP_CLKEN
|
1402 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH
) |
1403 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH
) |
1404 USER_PMD_TX_CTL_TSCK_LPWREN
));
1408 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_CONTROL
);
1411 err
= bcm8704_user_dev3_readback(np
, BCM8704_USER_PMD_TX_CONTROL
);
1415 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1416 BCM8704_USER_OPT_DIGITAL_CTRL
);
1419 err
&= ~USER_ODIG_CTRL_GPIOS
;
1420 err
|= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT
);
1421 err
= mdio_write(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1422 BCM8704_USER_OPT_DIGITAL_CTRL
, err
);
1431 static int mrvl88x2011_act_led(struct niu
*np
, int val
)
1435 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1436 MRVL88X2011_LED_8_TO_11_CTL
);
1440 err
&= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT
,MRVL88X2011_LED_CTL_MASK
);
1441 err
|= MRVL88X2011_LED(MRVL88X2011_LED_ACT
,val
);
1443 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1444 MRVL88X2011_LED_8_TO_11_CTL
, err
);
1447 static int mrvl88x2011_led_blink_rate(struct niu
*np
, int rate
)
1451 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1452 MRVL88X2011_LED_BLINK_CTL
);
1454 err
&= ~MRVL88X2011_LED_BLKRATE_MASK
;
1457 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV2_ADDR
,
1458 MRVL88X2011_LED_BLINK_CTL
, err
);
1464 static int xcvr_init_10g_mrvl88x2011(struct niu
*np
)
1468 /* Set LED functions */
1469 err
= mrvl88x2011_led_blink_rate(np
, MRVL88X2011_LED_BLKRATE_134MS
);
1474 err
= mrvl88x2011_act_led(np
, MRVL88X2011_LED_CTL_OFF
);
1478 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1479 MRVL88X2011_GENERAL_CTL
);
1483 err
|= MRVL88X2011_ENA_XFPREFCLK
;
1485 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
1486 MRVL88X2011_GENERAL_CTL
, err
);
1490 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1491 MRVL88X2011_PMA_PMD_CTL_1
);
1495 if (np
->link_config
.loopback_mode
== LOOPBACK_MAC
)
1496 err
|= MRVL88X2011_LOOPBACK
;
1498 err
&= ~MRVL88X2011_LOOPBACK
;
1500 err
= mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1501 MRVL88X2011_PMA_PMD_CTL_1
, err
);
1506 return mdio_write(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1507 MRVL88X2011_10G_PMD_TX_DIS
, MRVL88X2011_ENA_PMDTX
);
1511 static int xcvr_diag_bcm870x(struct niu
*np
)
1513 u16 analog_stat0
, tx_alarm_status
;
1517 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
1521 pr_info(PFX
"Port %u PMA_PMD(MII_STAT1000) [%04x]\n",
1524 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
, 0x20);
1527 pr_info(PFX
"Port %u USER_DEV3(0x20) [%04x]\n",
1530 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
1534 pr_info(PFX
"Port %u PHYXS(MII_NWAYTEST) [%04x]\n",
1538 /* XXX dig this out it might not be so useful XXX */
1539 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1540 BCM8704_USER_ANALOG_STATUS0
);
1543 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1544 BCM8704_USER_ANALOG_STATUS0
);
1549 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1550 BCM8704_USER_TX_ALARM_STATUS
);
1553 err
= mdio_read(np
, np
->phy_addr
, BCM8704_USER_DEV3_ADDR
,
1554 BCM8704_USER_TX_ALARM_STATUS
);
1557 tx_alarm_status
= err
;
1559 if (analog_stat0
!= 0x03fc) {
1560 if ((analog_stat0
== 0x43bc) && (tx_alarm_status
!= 0)) {
1561 pr_info(PFX
"Port %u cable not connected "
1562 "or bad cable.\n", np
->port
);
1563 } else if (analog_stat0
== 0x639c) {
1564 pr_info(PFX
"Port %u optical module is bad "
1565 "or missing.\n", np
->port
);
1572 static int xcvr_10g_set_lb_bcm870x(struct niu
*np
)
1574 struct niu_link_config
*lp
= &np
->link_config
;
1577 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1582 err
&= ~BMCR_LOOPBACK
;
1584 if (lp
->loopback_mode
== LOOPBACK_MAC
)
1585 err
|= BMCR_LOOPBACK
;
1587 err
= mdio_write(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
1595 static int xcvr_init_10g_bcm8706(struct niu
*np
)
1600 if ((np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) &&
1601 (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) == 0)
1604 val
= nr64_mac(XMAC_CONFIG
);
1605 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1606 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1607 nw64_mac(XMAC_CONFIG
, val
);
1609 val
= nr64(MIF_CONFIG
);
1610 val
|= MIF_CONFIG_INDIRECT_MODE
;
1611 nw64(MIF_CONFIG
, val
);
1613 err
= bcm8704_reset(np
);
1617 err
= xcvr_10g_set_lb_bcm870x(np
);
1621 err
= bcm8706_init_user_dev3(np
);
1625 err
= xcvr_diag_bcm870x(np
);
1632 static int xcvr_init_10g_bcm8704(struct niu
*np
)
1636 err
= bcm8704_reset(np
);
1640 err
= bcm8704_init_user_dev3(np
);
1644 err
= xcvr_10g_set_lb_bcm870x(np
);
1648 err
= xcvr_diag_bcm870x(np
);
1655 static int xcvr_init_10g(struct niu
*np
)
1660 val
= nr64_mac(XMAC_CONFIG
);
1661 val
&= ~XMAC_CONFIG_LED_POLARITY
;
1662 val
|= XMAC_CONFIG_FORCE_LED_ON
;
1663 nw64_mac(XMAC_CONFIG
, val
);
1665 /* XXX shared resource, lock parent XXX */
1666 val
= nr64(MIF_CONFIG
);
1667 val
|= MIF_CONFIG_INDIRECT_MODE
;
1668 nw64(MIF_CONFIG
, val
);
1670 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
1671 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
1673 /* handle different phy types */
1674 switch (phy_id
& NIU_PHY_ID_MASK
) {
1675 case NIU_PHY_ID_MRVL88X2011
:
1676 err
= xcvr_init_10g_mrvl88x2011(np
);
1679 default: /* bcom 8704 */
1680 err
= xcvr_init_10g_bcm8704(np
);
1687 static int mii_reset(struct niu
*np
)
1691 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, BMCR_RESET
);
1696 while (--limit
>= 0) {
1698 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1701 if (!(err
& BMCR_RESET
))
1705 dev_err(np
->device
, PFX
"Port %u MII would not reset, "
1706 "bmcr[%04x]\n", np
->port
, err
);
1713 static int xcvr_init_1g_rgmii(struct niu
*np
)
1717 u16 bmcr
, bmsr
, estat
;
1719 val
= nr64(MIF_CONFIG
);
1720 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1721 nw64(MIF_CONFIG
, val
);
1723 err
= mii_reset(np
);
1727 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1733 if (bmsr
& BMSR_ESTATEN
) {
1734 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1741 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1745 if (bmsr
& BMSR_ESTATEN
) {
1748 if (estat
& ESTATUS_1000_TFULL
)
1749 ctrl1000
|= ADVERTISE_1000FULL
;
1750 err
= mii_write(np
, np
->phy_addr
, MII_CTRL1000
, ctrl1000
);
1755 bmcr
= (BMCR_SPEED1000
| BMCR_FULLDPLX
);
1757 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1761 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1764 bmcr
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1766 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1773 static int mii_init_common(struct niu
*np
)
1775 struct niu_link_config
*lp
= &np
->link_config
;
1776 u16 bmcr
, bmsr
, adv
, estat
;
1779 err
= mii_reset(np
);
1783 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1789 if (bmsr
& BMSR_ESTATEN
) {
1790 err
= mii_read(np
, np
->phy_addr
, MII_ESTATUS
);
1797 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1801 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
1802 bmcr
|= BMCR_LOOPBACK
;
1803 if (lp
->active_speed
== SPEED_1000
)
1804 bmcr
|= BMCR_SPEED1000
;
1805 if (lp
->active_duplex
== DUPLEX_FULL
)
1806 bmcr
|= BMCR_FULLDPLX
;
1809 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
1812 aux
= (BCM5464R_AUX_CTL_EXT_LB
|
1813 BCM5464R_AUX_CTL_WRITE_1
);
1814 err
= mii_write(np
, np
->phy_addr
, BCM5464R_AUX_CTL
, aux
);
1822 adv
= ADVERTISE_CSMA
| ADVERTISE_PAUSE_CAP
;
1823 if ((bmsr
& BMSR_10HALF
) &&
1824 (lp
->advertising
& ADVERTISED_10baseT_Half
))
1825 adv
|= ADVERTISE_10HALF
;
1826 if ((bmsr
& BMSR_10FULL
) &&
1827 (lp
->advertising
& ADVERTISED_10baseT_Full
))
1828 adv
|= ADVERTISE_10FULL
;
1829 if ((bmsr
& BMSR_100HALF
) &&
1830 (lp
->advertising
& ADVERTISED_100baseT_Half
))
1831 adv
|= ADVERTISE_100HALF
;
1832 if ((bmsr
& BMSR_100FULL
) &&
1833 (lp
->advertising
& ADVERTISED_100baseT_Full
))
1834 adv
|= ADVERTISE_100FULL
;
1835 err
= mii_write(np
, np
->phy_addr
, MII_ADVERTISE
, adv
);
1839 if (likely(bmsr
& BMSR_ESTATEN
)) {
1841 if ((estat
& ESTATUS_1000_THALF
) &&
1842 (lp
->advertising
& ADVERTISED_1000baseT_Half
))
1843 ctrl1000
|= ADVERTISE_1000HALF
;
1844 if ((estat
& ESTATUS_1000_TFULL
) &&
1845 (lp
->advertising
& ADVERTISED_1000baseT_Full
))
1846 ctrl1000
|= ADVERTISE_1000FULL
;
1847 err
= mii_write(np
, np
->phy_addr
,
1848 MII_CTRL1000
, ctrl1000
);
1853 bmcr
|= (BMCR_ANENABLE
| BMCR_ANRESTART
);
1858 if (lp
->duplex
== DUPLEX_FULL
) {
1859 bmcr
|= BMCR_FULLDPLX
;
1861 } else if (lp
->duplex
== DUPLEX_HALF
)
1866 if (lp
->speed
== SPEED_1000
) {
1867 /* if X-full requested while not supported, or
1868 X-half requested while not supported... */
1869 if ((fulldpx
&& !(estat
& ESTATUS_1000_TFULL
)) ||
1870 (!fulldpx
&& !(estat
& ESTATUS_1000_THALF
)))
1872 bmcr
|= BMCR_SPEED1000
;
1873 } else if (lp
->speed
== SPEED_100
) {
1874 if ((fulldpx
&& !(bmsr
& BMSR_100FULL
)) ||
1875 (!fulldpx
&& !(bmsr
& BMSR_100HALF
)))
1877 bmcr
|= BMCR_SPEED100
;
1878 } else if (lp
->speed
== SPEED_10
) {
1879 if ((fulldpx
&& !(bmsr
& BMSR_10FULL
)) ||
1880 (!fulldpx
&& !(bmsr
& BMSR_10HALF
)))
1886 err
= mii_write(np
, np
->phy_addr
, MII_BMCR
, bmcr
);
1891 err
= mii_read(np
, np
->phy_addr
, MII_BMCR
);
1896 err
= mii_read(np
, np
->phy_addr
, MII_BMSR
);
1901 pr_info(PFX
"Port %u after MII init bmcr[%04x] bmsr[%04x]\n",
1902 np
->port
, bmcr
, bmsr
);
1908 static int xcvr_init_1g(struct niu
*np
)
1912 /* XXX shared resource, lock parent XXX */
1913 val
= nr64(MIF_CONFIG
);
1914 val
&= ~MIF_CONFIG_INDIRECT_MODE
;
1915 nw64(MIF_CONFIG
, val
);
1917 return mii_init_common(np
);
1920 static int niu_xcvr_init(struct niu
*np
)
1922 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1927 err
= ops
->xcvr_init(np
);
1932 static int niu_serdes_init(struct niu
*np
)
1934 const struct niu_phy_ops
*ops
= np
->phy_ops
;
1938 if (ops
->serdes_init
)
1939 err
= ops
->serdes_init(np
);
1944 static void niu_init_xif(struct niu
*);
1945 static void niu_handle_led(struct niu
*, int status
);
1947 static int niu_link_status_common(struct niu
*np
, int link_up
)
1949 struct niu_link_config
*lp
= &np
->link_config
;
1950 struct net_device
*dev
= np
->dev
;
1951 unsigned long flags
;
1953 if (!netif_carrier_ok(dev
) && link_up
) {
1954 niuinfo(LINK
, "%s: Link is up at %s, %s duplex\n",
1956 (lp
->active_speed
== SPEED_10000
?
1958 (lp
->active_speed
== SPEED_1000
?
1960 (lp
->active_speed
== SPEED_100
?
1961 "100Mbit/sec" : "10Mbit/sec"))),
1962 (lp
->active_duplex
== DUPLEX_FULL
?
1965 spin_lock_irqsave(&np
->lock
, flags
);
1967 niu_handle_led(np
, 1);
1968 spin_unlock_irqrestore(&np
->lock
, flags
);
1970 netif_carrier_on(dev
);
1971 } else if (netif_carrier_ok(dev
) && !link_up
) {
1972 niuwarn(LINK
, "%s: Link is down\n", dev
->name
);
1973 spin_lock_irqsave(&np
->lock
, flags
);
1974 niu_handle_led(np
, 0);
1975 spin_unlock_irqrestore(&np
->lock
, flags
);
1976 netif_carrier_off(dev
);
1982 static int link_status_10g_mrvl(struct niu
*np
, int *link_up_p
)
1984 int err
, link_up
, pma_status
, pcs_status
;
1988 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1989 MRVL88X2011_10G_PMD_STATUS_2
);
1993 /* Check PMA/PMD Register: 1.0001.2 == 1 */
1994 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV1_ADDR
,
1995 MRVL88X2011_PMA_PMD_STATUS_1
);
1999 pma_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
2001 /* Check PMC Register : 3.0001.2 == 1: read twice */
2002 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
2003 MRVL88X2011_PMA_PMD_STATUS_1
);
2007 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV3_ADDR
,
2008 MRVL88X2011_PMA_PMD_STATUS_1
);
2012 pcs_status
= ((err
& MRVL88X2011_LNK_STATUS_OK
) ? 1 : 0);
2014 /* Check XGXS Register : 4.0018.[0-3,12] */
2015 err
= mdio_read(np
, np
->phy_addr
, MRVL88X2011_USER_DEV4_ADDR
,
2016 MRVL88X2011_10G_XGXS_LANE_STAT
);
2020 if (err
== (PHYXS_XGXS_LANE_STAT_ALINGED
| PHYXS_XGXS_LANE_STAT_LANE3
|
2021 PHYXS_XGXS_LANE_STAT_LANE2
| PHYXS_XGXS_LANE_STAT_LANE1
|
2022 PHYXS_XGXS_LANE_STAT_LANE0
| PHYXS_XGXS_LANE_STAT_MAGIC
|
2024 link_up
= (pma_status
&& pcs_status
) ? 1 : 0;
2026 np
->link_config
.active_speed
= SPEED_10000
;
2027 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2030 mrvl88x2011_act_led(np
, (link_up
?
2031 MRVL88X2011_LED_CTL_PCS_ACT
:
2032 MRVL88X2011_LED_CTL_OFF
));
2034 *link_up_p
= link_up
;
2038 static int link_status_10g_bcm8706(struct niu
*np
, int *link_up_p
)
2043 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2044 BCM8704_PMD_RCV_SIGDET
);
2045 if (err
< 0 || err
== 0xffff)
2047 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2052 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2053 BCM8704_PCS_10G_R_STATUS
);
2057 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2062 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2063 BCM8704_PHYXS_XGXS_LANE_STAT
);
2066 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2067 PHYXS_XGXS_LANE_STAT_MAGIC
|
2068 PHYXS_XGXS_LANE_STAT_PATTEST
|
2069 PHYXS_XGXS_LANE_STAT_LANE3
|
2070 PHYXS_XGXS_LANE_STAT_LANE2
|
2071 PHYXS_XGXS_LANE_STAT_LANE1
|
2072 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2074 np
->link_config
.active_speed
= SPEED_INVALID
;
2075 np
->link_config
.active_duplex
= DUPLEX_INVALID
;
2080 np
->link_config
.active_speed
= SPEED_10000
;
2081 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2085 *link_up_p
= link_up
;
2089 static int link_status_10g_bcom(struct niu
*np
, int *link_up_p
)
2095 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PMA_PMD_DEV_ADDR
,
2096 BCM8704_PMD_RCV_SIGDET
);
2099 if (!(err
& PMD_RCV_SIGDET_GLOBAL
)) {
2104 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PCS_DEV_ADDR
,
2105 BCM8704_PCS_10G_R_STATUS
);
2108 if (!(err
& PCS_10G_R_STATUS_BLK_LOCK
)) {
2113 err
= mdio_read(np
, np
->phy_addr
, BCM8704_PHYXS_DEV_ADDR
,
2114 BCM8704_PHYXS_XGXS_LANE_STAT
);
2118 if (err
!= (PHYXS_XGXS_LANE_STAT_ALINGED
|
2119 PHYXS_XGXS_LANE_STAT_MAGIC
|
2120 PHYXS_XGXS_LANE_STAT_LANE3
|
2121 PHYXS_XGXS_LANE_STAT_LANE2
|
2122 PHYXS_XGXS_LANE_STAT_LANE1
|
2123 PHYXS_XGXS_LANE_STAT_LANE0
)) {
2129 np
->link_config
.active_speed
= SPEED_10000
;
2130 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2134 *link_up_p
= link_up
;
2138 static int link_status_10g(struct niu
*np
, int *link_up_p
)
2140 unsigned long flags
;
2143 spin_lock_irqsave(&np
->lock
, flags
);
2145 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2148 phy_id
= phy_decode(np
->parent
->port_phy
, np
->port
);
2149 phy_id
= np
->parent
->phy_probe_info
.phy_id
[phy_id
][np
->port
];
2151 /* handle different phy types */
2152 switch (phy_id
& NIU_PHY_ID_MASK
) {
2153 case NIU_PHY_ID_MRVL88X2011
:
2154 err
= link_status_10g_mrvl(np
, link_up_p
);
2157 default: /* bcom 8704 */
2158 err
= link_status_10g_bcom(np
, link_up_p
);
2163 spin_unlock_irqrestore(&np
->lock
, flags
);
2168 static int niu_10g_phy_present(struct niu
*np
)
2172 sig
= nr64(ESR_INT_SIGNALS
);
2175 mask
= ESR_INT_SIGNALS_P0_BITS
;
2176 val
= (ESR_INT_SRDY0_P0
|
2179 ESR_INT_XDP_P0_CH3
|
2180 ESR_INT_XDP_P0_CH2
|
2181 ESR_INT_XDP_P0_CH1
|
2182 ESR_INT_XDP_P0_CH0
);
2186 mask
= ESR_INT_SIGNALS_P1_BITS
;
2187 val
= (ESR_INT_SRDY0_P1
|
2190 ESR_INT_XDP_P1_CH3
|
2191 ESR_INT_XDP_P1_CH2
|
2192 ESR_INT_XDP_P1_CH1
|
2193 ESR_INT_XDP_P1_CH0
);
2200 if ((sig
& mask
) != val
)
2205 static int link_status_10g_hotplug(struct niu
*np
, int *link_up_p
)
2207 unsigned long flags
;
2210 int phy_present_prev
;
2212 spin_lock_irqsave(&np
->lock
, flags
);
2214 if (np
->link_config
.loopback_mode
== LOOPBACK_DISABLED
) {
2215 phy_present_prev
= (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) ?
2217 phy_present
= niu_10g_phy_present(np
);
2218 if (phy_present
!= phy_present_prev
) {
2221 /* A NEM was just plugged in */
2222 np
->flags
|= NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2223 if (np
->phy_ops
->xcvr_init
)
2224 err
= np
->phy_ops
->xcvr_init(np
);
2226 err
= mdio_read(np
, np
->phy_addr
,
2227 BCM8704_PHYXS_DEV_ADDR
, MII_BMCR
);
2228 if (err
== 0xffff) {
2229 /* No mdio, back-to-back XAUI */
2233 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2236 np
->flags
&= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT
;
2238 niuwarn(LINK
, "%s: Hotplug PHY Removed\n",
2243 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY_PRESENT
) {
2244 err
= link_status_10g_bcm8706(np
, link_up_p
);
2245 if (err
== 0xffff) {
2246 /* No mdio, back-to-back XAUI: it is C10NEM */
2248 np
->link_config
.active_speed
= SPEED_10000
;
2249 np
->link_config
.active_duplex
= DUPLEX_FULL
;
2254 spin_unlock_irqrestore(&np
->lock
, flags
);
2259 static int niu_link_status(struct niu
*np
, int *link_up_p
)
2261 const struct niu_phy_ops
*ops
= np
->phy_ops
;
2265 if (ops
->link_status
)
2266 err
= ops
->link_status(np
, link_up_p
);
2271 static void niu_timer(unsigned long __opaque
)
2273 struct niu
*np
= (struct niu
*) __opaque
;
2277 err
= niu_link_status(np
, &link_up
);
2279 niu_link_status_common(np
, link_up
);
2281 if (netif_carrier_ok(np
->dev
))
2285 np
->timer
.expires
= jiffies
+ off
;
2287 add_timer(&np
->timer
);
2290 static const struct niu_phy_ops phy_ops_10g_serdes
= {
2291 .serdes_init
= serdes_init_10g_serdes
,
2292 .link_status
= link_status_10g_serdes
,
2295 static const struct niu_phy_ops phy_ops_10g_serdes_niu
= {
2296 .serdes_init
= serdes_init_niu_10g_serdes
,
2297 .link_status
= link_status_10g_serdes
,
2300 static const struct niu_phy_ops phy_ops_1g_serdes_niu
= {
2301 .serdes_init
= serdes_init_niu_1g_serdes
,
2302 .link_status
= link_status_1g_serdes
,
2305 static const struct niu_phy_ops phy_ops_1g_rgmii
= {
2306 .xcvr_init
= xcvr_init_1g_rgmii
,
2307 .link_status
= link_status_1g_rgmii
,
2310 static const struct niu_phy_ops phy_ops_10g_fiber_niu
= {
2311 .serdes_init
= serdes_init_niu_10g_fiber
,
2312 .xcvr_init
= xcvr_init_10g
,
2313 .link_status
= link_status_10g
,
2316 static const struct niu_phy_ops phy_ops_10g_fiber
= {
2317 .serdes_init
= serdes_init_10g
,
2318 .xcvr_init
= xcvr_init_10g
,
2319 .link_status
= link_status_10g
,
2322 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug
= {
2323 .serdes_init
= serdes_init_10g
,
2324 .xcvr_init
= xcvr_init_10g_bcm8706
,
2325 .link_status
= link_status_10g_hotplug
,
2328 static const struct niu_phy_ops phy_ops_niu_10g_hotplug
= {
2329 .serdes_init
= serdes_init_niu_10g_fiber
,
2330 .xcvr_init
= xcvr_init_10g_bcm8706
,
2331 .link_status
= link_status_10g_hotplug
,
2334 static const struct niu_phy_ops phy_ops_10g_copper
= {
2335 .serdes_init
= serdes_init_10g
,
2336 .link_status
= link_status_10g
, /* XXX */
2339 static const struct niu_phy_ops phy_ops_1g_fiber
= {
2340 .serdes_init
= serdes_init_1g
,
2341 .xcvr_init
= xcvr_init_1g
,
2342 .link_status
= link_status_1g
,
2345 static const struct niu_phy_ops phy_ops_1g_copper
= {
2346 .xcvr_init
= xcvr_init_1g
,
2347 .link_status
= link_status_1g
,
2350 struct niu_phy_template
{
2351 const struct niu_phy_ops
*ops
;
2355 static const struct niu_phy_template phy_template_niu_10g_fiber
= {
2356 .ops
= &phy_ops_10g_fiber_niu
,
2357 .phy_addr_base
= 16,
2360 static const struct niu_phy_template phy_template_niu_10g_serdes
= {
2361 .ops
= &phy_ops_10g_serdes_niu
,
2365 static const struct niu_phy_template phy_template_niu_1g_serdes
= {
2366 .ops
= &phy_ops_1g_serdes_niu
,
2370 static const struct niu_phy_template phy_template_10g_fiber
= {
2371 .ops
= &phy_ops_10g_fiber
,
2375 static const struct niu_phy_template phy_template_10g_fiber_hotplug
= {
2376 .ops
= &phy_ops_10g_fiber_hotplug
,
2380 static const struct niu_phy_template phy_template_niu_10g_hotplug
= {
2381 .ops
= &phy_ops_niu_10g_hotplug
,
2385 static const struct niu_phy_template phy_template_10g_copper
= {
2386 .ops
= &phy_ops_10g_copper
,
2387 .phy_addr_base
= 10,
2390 static const struct niu_phy_template phy_template_1g_fiber
= {
2391 .ops
= &phy_ops_1g_fiber
,
2395 static const struct niu_phy_template phy_template_1g_copper
= {
2396 .ops
= &phy_ops_1g_copper
,
2400 static const struct niu_phy_template phy_template_1g_rgmii
= {
2401 .ops
= &phy_ops_1g_rgmii
,
2405 static const struct niu_phy_template phy_template_10g_serdes
= {
2406 .ops
= &phy_ops_10g_serdes
,
2410 static int niu_atca_port_num
[4] = {
2414 static int serdes_init_10g_serdes(struct niu
*np
)
2416 struct niu_link_config
*lp
= &np
->link_config
;
2417 unsigned long ctrl_reg
, test_cfg_reg
, pll_cfg
, i
;
2418 u64 ctrl_val
, test_cfg_val
, sig
, mask
, val
;
2423 reset_val
= ENET_SERDES_RESET_0
;
2424 ctrl_reg
= ENET_SERDES_0_CTRL_CFG
;
2425 test_cfg_reg
= ENET_SERDES_0_TEST_CFG
;
2426 pll_cfg
= ENET_SERDES_0_PLL_CFG
;
2429 reset_val
= ENET_SERDES_RESET_1
;
2430 ctrl_reg
= ENET_SERDES_1_CTRL_CFG
;
2431 test_cfg_reg
= ENET_SERDES_1_TEST_CFG
;
2432 pll_cfg
= ENET_SERDES_1_PLL_CFG
;
2438 ctrl_val
= (ENET_SERDES_CTRL_SDET_0
|
2439 ENET_SERDES_CTRL_SDET_1
|
2440 ENET_SERDES_CTRL_SDET_2
|
2441 ENET_SERDES_CTRL_SDET_3
|
2442 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT
) |
2443 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT
) |
2444 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT
) |
2445 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT
) |
2446 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT
) |
2447 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT
) |
2448 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT
) |
2449 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT
));
2452 if (lp
->loopback_mode
== LOOPBACK_PHY
) {
2453 test_cfg_val
|= ((ENET_TEST_MD_PAD_LOOPBACK
<<
2454 ENET_SERDES_TEST_MD_0_SHIFT
) |
2455 (ENET_TEST_MD_PAD_LOOPBACK
<<
2456 ENET_SERDES_TEST_MD_1_SHIFT
) |
2457 (ENET_TEST_MD_PAD_LOOPBACK
<<
2458 ENET_SERDES_TEST_MD_2_SHIFT
) |
2459 (ENET_TEST_MD_PAD_LOOPBACK
<<
2460 ENET_SERDES_TEST_MD_3_SHIFT
));
2464 nw64(pll_cfg
, ENET_SERDES_PLL_FBDIV2
);
2465 nw64(ctrl_reg
, ctrl_val
);
2466 nw64(test_cfg_reg
, test_cfg_val
);
2468 /* Initialize all 4 lanes of the SERDES. */
2469 for (i
= 0; i
< 4; i
++) {
2470 u32 rxtx_ctrl
, glue0
;
2473 err
= esr_read_rxtx_ctrl(np
, i
, &rxtx_ctrl
);
2476 err
= esr_read_glue0(np
, i
, &glue0
);
2480 rxtx_ctrl
&= ~(ESR_RXTX_CTRL_VMUXLO
);
2481 rxtx_ctrl
|= (ESR_RXTX_CTRL_ENSTRETCH
|
2482 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT
));
2484 glue0
&= ~(ESR_GLUE_CTRL0_SRATE
|
2485 ESR_GLUE_CTRL0_THCNT
|
2486 ESR_GLUE_CTRL0_BLTIME
);
2487 glue0
|= (ESR_GLUE_CTRL0_RXLOSENAB
|
2488 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT
) |
2489 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT
) |
2490 (BLTIME_300_CYCLES
<<
2491 ESR_GLUE_CTRL0_BLTIME_SHIFT
));
2493 err
= esr_write_rxtx_ctrl(np
, i
, rxtx_ctrl
);
2496 err
= esr_write_glue0(np
, i
, glue0
);
2502 sig
= nr64(ESR_INT_SIGNALS
);
2505 mask
= ESR_INT_SIGNALS_P0_BITS
;
2506 val
= (ESR_INT_SRDY0_P0
|
2509 ESR_INT_XDP_P0_CH3
|
2510 ESR_INT_XDP_P0_CH2
|
2511 ESR_INT_XDP_P0_CH1
|
2512 ESR_INT_XDP_P0_CH0
);
2516 mask
= ESR_INT_SIGNALS_P1_BITS
;
2517 val
= (ESR_INT_SRDY0_P1
|
2520 ESR_INT_XDP_P1_CH3
|
2521 ESR_INT_XDP_P1_CH2
|
2522 ESR_INT_XDP_P1_CH1
|
2523 ESR_INT_XDP_P1_CH0
);
2530 if ((sig
& mask
) != val
) {
2532 err
= serdes_init_1g_serdes(np
);
2534 np
->flags
&= ~NIU_FLAGS_10G
;
2535 np
->mac_xcvr
= MAC_XCVR_PCS
;
2537 dev_err(np
->device
, PFX
"Port %u 10G/1G SERDES Link Failed \n",
2546 static int niu_determine_phy_disposition(struct niu
*np
)
2548 struct niu_parent
*parent
= np
->parent
;
2549 u8 plat_type
= parent
->plat_type
;
2550 const struct niu_phy_template
*tp
;
2551 u32 phy_addr_off
= 0;
2553 if (plat_type
== PLAT_TYPE_NIU
) {
2557 NIU_FLAGS_XCVR_SERDES
)) {
2558 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2560 tp
= &phy_template_niu_10g_serdes
;
2562 case NIU_FLAGS_XCVR_SERDES
:
2564 tp
= &phy_template_niu_1g_serdes
;
2566 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2569 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2570 tp
= &phy_template_niu_10g_hotplug
;
2576 tp
= &phy_template_niu_10g_fiber
;
2577 phy_addr_off
+= np
->port
;
2585 NIU_FLAGS_XCVR_SERDES
)) {
2588 tp
= &phy_template_1g_copper
;
2589 if (plat_type
== PLAT_TYPE_VF_P0
)
2591 else if (plat_type
== PLAT_TYPE_VF_P1
)
2594 phy_addr_off
+= (np
->port
^ 0x3);
2599 tp
= &phy_template_10g_copper
;
2602 case NIU_FLAGS_FIBER
:
2604 tp
= &phy_template_1g_fiber
;
2607 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
2609 tp
= &phy_template_10g_fiber
;
2610 if (plat_type
== PLAT_TYPE_VF_P0
||
2611 plat_type
== PLAT_TYPE_VF_P1
)
2613 phy_addr_off
+= np
->port
;
2614 if (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
) {
2615 tp
= &phy_template_10g_fiber_hotplug
;
2623 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
2624 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
2625 case NIU_FLAGS_XCVR_SERDES
:
2629 tp
= &phy_template_10g_serdes
;
2633 tp
= &phy_template_1g_rgmii
;
2639 phy_addr_off
= niu_atca_port_num
[np
->port
];
2647 np
->phy_ops
= tp
->ops
;
2648 np
->phy_addr
= tp
->phy_addr_base
+ phy_addr_off
;
2653 static int niu_init_link(struct niu
*np
)
2655 struct niu_parent
*parent
= np
->parent
;
2658 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
2659 err
= niu_xcvr_init(np
);
2664 err
= niu_serdes_init(np
);
2665 if (err
&& !(np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2668 err
= niu_xcvr_init(np
);
2669 if (!err
|| (np
->flags
& NIU_FLAGS_HOTPLUG_PHY
))
2670 niu_link_status(np
, &ignore
);
2674 static void niu_set_primary_mac(struct niu
*np
, unsigned char *addr
)
2676 u16 reg0
= addr
[4] << 8 | addr
[5];
2677 u16 reg1
= addr
[2] << 8 | addr
[3];
2678 u16 reg2
= addr
[0] << 8 | addr
[1];
2680 if (np
->flags
& NIU_FLAGS_XMAC
) {
2681 nw64_mac(XMAC_ADDR0
, reg0
);
2682 nw64_mac(XMAC_ADDR1
, reg1
);
2683 nw64_mac(XMAC_ADDR2
, reg2
);
2685 nw64_mac(BMAC_ADDR0
, reg0
);
2686 nw64_mac(BMAC_ADDR1
, reg1
);
2687 nw64_mac(BMAC_ADDR2
, reg2
);
2691 static int niu_num_alt_addr(struct niu
*np
)
2693 if (np
->flags
& NIU_FLAGS_XMAC
)
2694 return XMAC_NUM_ALT_ADDR
;
2696 return BMAC_NUM_ALT_ADDR
;
2699 static int niu_set_alt_mac(struct niu
*np
, int index
, unsigned char *addr
)
2701 u16 reg0
= addr
[4] << 8 | addr
[5];
2702 u16 reg1
= addr
[2] << 8 | addr
[3];
2703 u16 reg2
= addr
[0] << 8 | addr
[1];
2705 if (index
>= niu_num_alt_addr(np
))
2708 if (np
->flags
& NIU_FLAGS_XMAC
) {
2709 nw64_mac(XMAC_ALT_ADDR0(index
), reg0
);
2710 nw64_mac(XMAC_ALT_ADDR1(index
), reg1
);
2711 nw64_mac(XMAC_ALT_ADDR2(index
), reg2
);
2713 nw64_mac(BMAC_ALT_ADDR0(index
), reg0
);
2714 nw64_mac(BMAC_ALT_ADDR1(index
), reg1
);
2715 nw64_mac(BMAC_ALT_ADDR2(index
), reg2
);
2721 static int niu_enable_alt_mac(struct niu
*np
, int index
, int on
)
2726 if (index
>= niu_num_alt_addr(np
))
2729 if (np
->flags
& NIU_FLAGS_XMAC
) {
2730 reg
= XMAC_ADDR_CMPEN
;
2733 reg
= BMAC_ADDR_CMPEN
;
2734 mask
= 1 << (index
+ 1);
2737 val
= nr64_mac(reg
);
2747 static void __set_rdc_table_num_hw(struct niu
*np
, unsigned long reg
,
2748 int num
, int mac_pref
)
2750 u64 val
= nr64_mac(reg
);
2751 val
&= ~(HOST_INFO_MACRDCTBLN
| HOST_INFO_MPR
);
2754 val
|= HOST_INFO_MPR
;
2758 static int __set_rdc_table_num(struct niu
*np
,
2759 int xmac_index
, int bmac_index
,
2760 int rdc_table_num
, int mac_pref
)
2764 if (rdc_table_num
& ~HOST_INFO_MACRDCTBLN
)
2766 if (np
->flags
& NIU_FLAGS_XMAC
)
2767 reg
= XMAC_HOST_INFO(xmac_index
);
2769 reg
= BMAC_HOST_INFO(bmac_index
);
2770 __set_rdc_table_num_hw(np
, reg
, rdc_table_num
, mac_pref
);
2774 static int niu_set_primary_mac_rdc_table(struct niu
*np
, int table_num
,
2777 return __set_rdc_table_num(np
, 17, 0, table_num
, mac_pref
);
2780 static int niu_set_multicast_mac_rdc_table(struct niu
*np
, int table_num
,
2783 return __set_rdc_table_num(np
, 16, 8, table_num
, mac_pref
);
2786 static int niu_set_alt_mac_rdc_table(struct niu
*np
, int idx
,
2787 int table_num
, int mac_pref
)
2789 if (idx
>= niu_num_alt_addr(np
))
2791 return __set_rdc_table_num(np
, idx
, idx
+ 1, table_num
, mac_pref
);
2794 static u64
vlan_entry_set_parity(u64 reg_val
)
2799 port01_mask
= 0x00ff;
2800 port23_mask
= 0xff00;
2802 if (hweight64(reg_val
& port01_mask
) & 1)
2803 reg_val
|= ENET_VLAN_TBL_PARITY0
;
2805 reg_val
&= ~ENET_VLAN_TBL_PARITY0
;
2807 if (hweight64(reg_val
& port23_mask
) & 1)
2808 reg_val
|= ENET_VLAN_TBL_PARITY1
;
2810 reg_val
&= ~ENET_VLAN_TBL_PARITY1
;
2815 static void vlan_tbl_write(struct niu
*np
, unsigned long index
,
2816 int port
, int vpr
, int rdc_table
)
2818 u64 reg_val
= nr64(ENET_VLAN_TBL(index
));
2820 reg_val
&= ~((ENET_VLAN_TBL_VPR
|
2821 ENET_VLAN_TBL_VLANRDCTBLN
) <<
2822 ENET_VLAN_TBL_SHIFT(port
));
2824 reg_val
|= (ENET_VLAN_TBL_VPR
<<
2825 ENET_VLAN_TBL_SHIFT(port
));
2826 reg_val
|= (rdc_table
<< ENET_VLAN_TBL_SHIFT(port
));
2828 reg_val
= vlan_entry_set_parity(reg_val
);
2830 nw64(ENET_VLAN_TBL(index
), reg_val
);
2833 static void vlan_tbl_clear(struct niu
*np
)
2837 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++)
2838 nw64(ENET_VLAN_TBL(i
), 0);
2841 static int tcam_wait_bit(struct niu
*np
, u64 bit
)
2845 while (--limit
> 0) {
2846 if (nr64(TCAM_CTL
) & bit
)
2856 static int tcam_flush(struct niu
*np
, int index
)
2858 nw64(TCAM_KEY_0
, 0x00);
2859 nw64(TCAM_KEY_MASK_0
, 0xff);
2860 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2862 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2866 static int tcam_read(struct niu
*np
, int index
,
2867 u64
*key
, u64
*mask
)
2871 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_READ
| index
));
2872 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2874 key
[0] = nr64(TCAM_KEY_0
);
2875 key
[1] = nr64(TCAM_KEY_1
);
2876 key
[2] = nr64(TCAM_KEY_2
);
2877 key
[3] = nr64(TCAM_KEY_3
);
2878 mask
[0] = nr64(TCAM_KEY_MASK_0
);
2879 mask
[1] = nr64(TCAM_KEY_MASK_1
);
2880 mask
[2] = nr64(TCAM_KEY_MASK_2
);
2881 mask
[3] = nr64(TCAM_KEY_MASK_3
);
2887 static int tcam_write(struct niu
*np
, int index
,
2888 u64
*key
, u64
*mask
)
2890 nw64(TCAM_KEY_0
, key
[0]);
2891 nw64(TCAM_KEY_1
, key
[1]);
2892 nw64(TCAM_KEY_2
, key
[2]);
2893 nw64(TCAM_KEY_3
, key
[3]);
2894 nw64(TCAM_KEY_MASK_0
, mask
[0]);
2895 nw64(TCAM_KEY_MASK_1
, mask
[1]);
2896 nw64(TCAM_KEY_MASK_2
, mask
[2]);
2897 nw64(TCAM_KEY_MASK_3
, mask
[3]);
2898 nw64(TCAM_CTL
, (TCAM_CTL_RWC_TCAM_WRITE
| index
));
2900 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2904 static int tcam_assoc_read(struct niu
*np
, int index
, u64
*data
)
2908 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_READ
| index
));
2909 err
= tcam_wait_bit(np
, TCAM_CTL_STAT
);
2911 *data
= nr64(TCAM_KEY_1
);
2917 static int tcam_assoc_write(struct niu
*np
, int index
, u64 assoc_data
)
2919 nw64(TCAM_KEY_1
, assoc_data
);
2920 nw64(TCAM_CTL
, (TCAM_CTL_RWC_RAM_WRITE
| index
));
2922 return tcam_wait_bit(np
, TCAM_CTL_STAT
);
2925 static void tcam_enable(struct niu
*np
, int on
)
2927 u64 val
= nr64(FFLP_CFG_1
);
2930 val
&= ~FFLP_CFG_1_TCAM_DIS
;
2932 val
|= FFLP_CFG_1_TCAM_DIS
;
2933 nw64(FFLP_CFG_1
, val
);
2936 static void tcam_set_lat_and_ratio(struct niu
*np
, u64 latency
, u64 ratio
)
2938 u64 val
= nr64(FFLP_CFG_1
);
2940 val
&= ~(FFLP_CFG_1_FFLPINITDONE
|
2942 FFLP_CFG_1_CAMRATIO
);
2943 val
|= (latency
<< FFLP_CFG_1_CAMLAT_SHIFT
);
2944 val
|= (ratio
<< FFLP_CFG_1_CAMRATIO_SHIFT
);
2945 nw64(FFLP_CFG_1
, val
);
2947 val
= nr64(FFLP_CFG_1
);
2948 val
|= FFLP_CFG_1_FFLPINITDONE
;
2949 nw64(FFLP_CFG_1
, val
);
2952 static int tcam_user_eth_class_enable(struct niu
*np
, unsigned long class,
2958 if (class < CLASS_CODE_ETHERTYPE1
||
2959 class > CLASS_CODE_ETHERTYPE2
)
2962 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2974 static int tcam_user_eth_class_set(struct niu
*np
, unsigned long class,
2980 if (class < CLASS_CODE_ETHERTYPE1
||
2981 class > CLASS_CODE_ETHERTYPE2
||
2982 (ether_type
& ~(u64
)0xffff) != 0)
2985 reg
= L2_CLS(class - CLASS_CODE_ETHERTYPE1
);
2987 val
&= ~L2_CLS_ETYPE
;
2988 val
|= (ether_type
<< L2_CLS_ETYPE_SHIFT
);
2995 static int tcam_user_ip_class_enable(struct niu
*np
, unsigned long class,
3001 if (class < CLASS_CODE_USER_PROG1
||
3002 class > CLASS_CODE_USER_PROG4
)
3005 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
3008 val
|= L3_CLS_VALID
;
3010 val
&= ~L3_CLS_VALID
;
3016 static int tcam_user_ip_class_set(struct niu
*np
, unsigned long class,
3017 int ipv6
, u64 protocol_id
,
3018 u64 tos_mask
, u64 tos_val
)
3023 if (class < CLASS_CODE_USER_PROG1
||
3024 class > CLASS_CODE_USER_PROG4
||
3025 (protocol_id
& ~(u64
)0xff) != 0 ||
3026 (tos_mask
& ~(u64
)0xff) != 0 ||
3027 (tos_val
& ~(u64
)0xff) != 0)
3030 reg
= L3_CLS(class - CLASS_CODE_USER_PROG1
);
3032 val
&= ~(L3_CLS_IPVER
| L3_CLS_PID
|
3033 L3_CLS_TOSMASK
| L3_CLS_TOS
);
3035 val
|= L3_CLS_IPVER
;
3036 val
|= (protocol_id
<< L3_CLS_PID_SHIFT
);
3037 val
|= (tos_mask
<< L3_CLS_TOSMASK_SHIFT
);
3038 val
|= (tos_val
<< L3_CLS_TOS_SHIFT
);
3044 static int tcam_early_init(struct niu
*np
)
3050 tcam_set_lat_and_ratio(np
,
3051 DEFAULT_TCAM_LATENCY
,
3052 DEFAULT_TCAM_ACCESS_RATIO
);
3053 for (i
= CLASS_CODE_ETHERTYPE1
; i
<= CLASS_CODE_ETHERTYPE2
; i
++) {
3054 err
= tcam_user_eth_class_enable(np
, i
, 0);
3058 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_USER_PROG4
; i
++) {
3059 err
= tcam_user_ip_class_enable(np
, i
, 0);
3067 static int tcam_flush_all(struct niu
*np
)
3071 for (i
= 0; i
< np
->parent
->tcam_num_entries
; i
++) {
3072 int err
= tcam_flush(np
, i
);
3079 static u64
hash_addr_regval(unsigned long index
, unsigned long num_entries
)
3081 return ((u64
)index
| (num_entries
== 1 ?
3082 HASH_TBL_ADDR_AUTOINC
: 0));
3086 static int hash_read(struct niu
*np
, unsigned long partition
,
3087 unsigned long index
, unsigned long num_entries
,
3090 u64 val
= hash_addr_regval(index
, num_entries
);
3093 if (partition
>= FCRAM_NUM_PARTITIONS
||
3094 index
+ num_entries
> FCRAM_SIZE
)
3097 nw64(HASH_TBL_ADDR(partition
), val
);
3098 for (i
= 0; i
< num_entries
; i
++)
3099 data
[i
] = nr64(HASH_TBL_DATA(partition
));
3105 static int hash_write(struct niu
*np
, unsigned long partition
,
3106 unsigned long index
, unsigned long num_entries
,
3109 u64 val
= hash_addr_regval(index
, num_entries
);
3112 if (partition
>= FCRAM_NUM_PARTITIONS
||
3113 index
+ (num_entries
* 8) > FCRAM_SIZE
)
3116 nw64(HASH_TBL_ADDR(partition
), val
);
3117 for (i
= 0; i
< num_entries
; i
++)
3118 nw64(HASH_TBL_DATA(partition
), data
[i
]);
3123 static void fflp_reset(struct niu
*np
)
3127 nw64(FFLP_CFG_1
, FFLP_CFG_1_PIO_FIO_RST
);
3129 nw64(FFLP_CFG_1
, 0);
3131 val
= FFLP_CFG_1_FCRAMOUTDR_NORMAL
| FFLP_CFG_1_FFLPINITDONE
;
3132 nw64(FFLP_CFG_1
, val
);
3135 static void fflp_set_timings(struct niu
*np
)
3137 u64 val
= nr64(FFLP_CFG_1
);
3139 val
&= ~FFLP_CFG_1_FFLPINITDONE
;
3140 val
|= (DEFAULT_FCRAMRATIO
<< FFLP_CFG_1_FCRAMRATIO_SHIFT
);
3141 nw64(FFLP_CFG_1
, val
);
3143 val
= nr64(FFLP_CFG_1
);
3144 val
|= FFLP_CFG_1_FFLPINITDONE
;
3145 nw64(FFLP_CFG_1
, val
);
3147 val
= nr64(FCRAM_REF_TMR
);
3148 val
&= ~(FCRAM_REF_TMR_MAX
| FCRAM_REF_TMR_MIN
);
3149 val
|= (DEFAULT_FCRAM_REFRESH_MAX
<< FCRAM_REF_TMR_MAX_SHIFT
);
3150 val
|= (DEFAULT_FCRAM_REFRESH_MIN
<< FCRAM_REF_TMR_MIN_SHIFT
);
3151 nw64(FCRAM_REF_TMR
, val
);
3154 static int fflp_set_partition(struct niu
*np
, u64 partition
,
3155 u64 mask
, u64 base
, int enable
)
3160 if (partition
>= FCRAM_NUM_PARTITIONS
||
3161 (mask
& ~(u64
)0x1f) != 0 ||
3162 (base
& ~(u64
)0x1f) != 0)
3165 reg
= FLW_PRT_SEL(partition
);
3168 val
&= ~(FLW_PRT_SEL_EXT
| FLW_PRT_SEL_MASK
| FLW_PRT_SEL_BASE
);
3169 val
|= (mask
<< FLW_PRT_SEL_MASK_SHIFT
);
3170 val
|= (base
<< FLW_PRT_SEL_BASE_SHIFT
);
3172 val
|= FLW_PRT_SEL_EXT
;
3178 static int fflp_disable_all_partitions(struct niu
*np
)
3182 for (i
= 0; i
< FCRAM_NUM_PARTITIONS
; i
++) {
3183 int err
= fflp_set_partition(np
, 0, 0, 0, 0);
3190 static void fflp_llcsnap_enable(struct niu
*np
, int on
)
3192 u64 val
= nr64(FFLP_CFG_1
);
3195 val
|= FFLP_CFG_1_LLCSNAP
;
3197 val
&= ~FFLP_CFG_1_LLCSNAP
;
3198 nw64(FFLP_CFG_1
, val
);
3201 static void fflp_errors_enable(struct niu
*np
, int on
)
3203 u64 val
= nr64(FFLP_CFG_1
);
3206 val
&= ~FFLP_CFG_1_ERRORDIS
;
3208 val
|= FFLP_CFG_1_ERRORDIS
;
3209 nw64(FFLP_CFG_1
, val
);
3212 static int fflp_hash_clear(struct niu
*np
)
3214 struct fcram_hash_ipv4 ent
;
3217 /* IPV4 hash entry with valid bit clear, rest is don't care. */
3218 memset(&ent
, 0, sizeof(ent
));
3219 ent
.header
= HASH_HEADER_EXT
;
3221 for (i
= 0; i
< FCRAM_SIZE
; i
+= sizeof(ent
)) {
3222 int err
= hash_write(np
, 0, i
, 1, (u64
*) &ent
);
3229 static int fflp_early_init(struct niu
*np
)
3231 struct niu_parent
*parent
;
3232 unsigned long flags
;
3235 niu_lock_parent(np
, flags
);
3237 parent
= np
->parent
;
3239 if (!(parent
->flags
& PARENT_FLGS_CLS_HWINIT
)) {
3240 niudbg(PROBE
, "fflp_early_init: Initting hw on port %u\n",
3242 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3244 fflp_set_timings(np
);
3245 err
= fflp_disable_all_partitions(np
);
3247 niudbg(PROBE
, "fflp_disable_all_partitions "
3248 "failed, err=%d\n", err
);
3253 err
= tcam_early_init(np
);
3255 niudbg(PROBE
, "tcam_early_init failed, err=%d\n",
3259 fflp_llcsnap_enable(np
, 1);
3260 fflp_errors_enable(np
, 0);
3264 err
= tcam_flush_all(np
);
3266 niudbg(PROBE
, "tcam_flush_all failed, err=%d\n",
3270 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
3271 err
= fflp_hash_clear(np
);
3273 niudbg(PROBE
, "fflp_hash_clear failed, "
3281 niudbg(PROBE
, "fflp_early_init: Success\n");
3282 parent
->flags
|= PARENT_FLGS_CLS_HWINIT
;
3285 niu_unlock_parent(np
, flags
);
3289 static int niu_set_flow_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3291 if (class_code
< CLASS_CODE_USER_PROG1
||
3292 class_code
> CLASS_CODE_SCTP_IPV6
)
3295 nw64(FLOW_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3299 static int niu_set_tcam_key(struct niu
*np
, unsigned long class_code
, u64 key
)
3301 if (class_code
< CLASS_CODE_USER_PROG1
||
3302 class_code
> CLASS_CODE_SCTP_IPV6
)
3305 nw64(TCAM_KEY(class_code
- CLASS_CODE_USER_PROG1
), key
);
3309 /* Entries for the ports are interleaved in the TCAM */
3310 static u16
tcam_get_index(struct niu
*np
, u16 idx
)
3312 /* One entry reserved for IP fragment rule */
3313 if (idx
>= (np
->clas
.tcam_sz
- 1))
3315 return (np
->clas
.tcam_top
+ ((idx
+1) * np
->parent
->num_ports
));
3318 static u16
tcam_get_size(struct niu
*np
)
3320 /* One entry reserved for IP fragment rule */
3321 return np
->clas
.tcam_sz
- 1;
3324 static u16
tcam_get_valid_entry_cnt(struct niu
*np
)
3326 /* One entry reserved for IP fragment rule */
3327 return np
->clas
.tcam_valid_entries
- 1;
3330 static void niu_rx_skb_append(struct sk_buff
*skb
, struct page
*page
,
3331 u32 offset
, u32 size
)
3333 int i
= skb_shinfo(skb
)->nr_frags
;
3334 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
3337 frag
->page_offset
= offset
;
3341 skb
->data_len
+= size
;
3342 skb
->truesize
+= size
;
3344 skb_shinfo(skb
)->nr_frags
= i
+ 1;
3347 static unsigned int niu_hash_rxaddr(struct rx_ring_info
*rp
, u64 a
)
3350 a
^= (a
>> ilog2(MAX_RBR_RING_SIZE
));
3352 return (a
& (MAX_RBR_RING_SIZE
- 1));
3355 static struct page
*niu_find_rxpage(struct rx_ring_info
*rp
, u64 addr
,
3356 struct page
***link
)
3358 unsigned int h
= niu_hash_rxaddr(rp
, addr
);
3359 struct page
*p
, **pp
;
3362 pp
= &rp
->rxhash
[h
];
3363 for (; (p
= *pp
) != NULL
; pp
= (struct page
**) &p
->mapping
) {
3364 if (p
->index
== addr
) {
3373 static void niu_hash_page(struct rx_ring_info
*rp
, struct page
*page
, u64 base
)
3375 unsigned int h
= niu_hash_rxaddr(rp
, base
);
3378 page
->mapping
= (struct address_space
*) rp
->rxhash
[h
];
3379 rp
->rxhash
[h
] = page
;
3382 static int niu_rbr_add_page(struct niu
*np
, struct rx_ring_info
*rp
,
3383 gfp_t mask
, int start_index
)
3389 page
= alloc_page(mask
);
3393 addr
= np
->ops
->map_page(np
->device
, page
, 0,
3394 PAGE_SIZE
, DMA_FROM_DEVICE
);
3396 niu_hash_page(rp
, page
, addr
);
3397 if (rp
->rbr_blocks_per_page
> 1)
3398 atomic_add(rp
->rbr_blocks_per_page
- 1,
3399 &compound_head(page
)->_count
);
3401 for (i
= 0; i
< rp
->rbr_blocks_per_page
; i
++) {
3402 __le32
*rbr
= &rp
->rbr
[start_index
+ i
];
3404 *rbr
= cpu_to_le32(addr
>> RBR_DESCR_ADDR_SHIFT
);
3405 addr
+= rp
->rbr_block_size
;
3411 static void niu_rbr_refill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3413 int index
= rp
->rbr_index
;
3416 if ((rp
->rbr_pending
% rp
->rbr_blocks_per_page
) == 0) {
3417 int err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3419 if (unlikely(err
)) {
3424 rp
->rbr_index
+= rp
->rbr_blocks_per_page
;
3425 BUG_ON(rp
->rbr_index
> rp
->rbr_table_size
);
3426 if (rp
->rbr_index
== rp
->rbr_table_size
)
3429 if (rp
->rbr_pending
>= rp
->rbr_kick_thresh
) {
3430 nw64(RBR_KICK(rp
->rx_channel
), rp
->rbr_pending
);
3431 rp
->rbr_pending
= 0;
3436 static int niu_rx_pkt_ignore(struct niu
*np
, struct rx_ring_info
*rp
)
3438 unsigned int index
= rp
->rcr_index
;
3443 struct page
*page
, **link
;
3449 val
= le64_to_cpup(&rp
->rcr
[index
]);
3450 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3451 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3452 page
= niu_find_rxpage(rp
, addr
, &link
);
3454 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3455 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3456 if ((page
->index
+ PAGE_SIZE
) - rcr_size
== addr
) {
3457 *link
= (struct page
*) page
->mapping
;
3458 np
->ops
->unmap_page(np
->device
, page
->index
,
3459 PAGE_SIZE
, DMA_FROM_DEVICE
);
3461 page
->mapping
= NULL
;
3463 rp
->rbr_refill_pending
++;
3466 index
= NEXT_RCR(rp
, index
);
3467 if (!(val
& RCR_ENTRY_MULTI
))
3471 rp
->rcr_index
= index
;
3476 static int niu_process_rx_pkt(struct napi_struct
*napi
, struct niu
*np
,
3477 struct rx_ring_info
*rp
)
3479 unsigned int index
= rp
->rcr_index
;
3480 struct sk_buff
*skb
;
3483 skb
= netdev_alloc_skb(np
->dev
, RX_SKB_ALLOC_SIZE
);
3485 return niu_rx_pkt_ignore(np
, rp
);
3489 struct page
*page
, **link
;
3490 u32 rcr_size
, append_size
;
3495 val
= le64_to_cpup(&rp
->rcr
[index
]);
3497 len
= (val
& RCR_ENTRY_L2_LEN
) >>
3498 RCR_ENTRY_L2_LEN_SHIFT
;
3501 addr
= (val
& RCR_ENTRY_PKT_BUF_ADDR
) <<
3502 RCR_ENTRY_PKT_BUF_ADDR_SHIFT
;
3503 page
= niu_find_rxpage(rp
, addr
, &link
);
3505 rcr_size
= rp
->rbr_sizes
[(val
& RCR_ENTRY_PKTBUFSZ
) >>
3506 RCR_ENTRY_PKTBUFSZ_SHIFT
];
3508 off
= addr
& ~PAGE_MASK
;
3509 append_size
= rcr_size
;
3516 ptype
= (val
>> RCR_ENTRY_PKT_TYPE_SHIFT
);
3517 if ((ptype
== RCR_PKT_TYPE_TCP
||
3518 ptype
== RCR_PKT_TYPE_UDP
) &&
3519 !(val
& (RCR_ENTRY_NOPORT
|
3521 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
3523 skb
->ip_summed
= CHECKSUM_NONE
;
3525 if (!(val
& RCR_ENTRY_MULTI
))
3526 append_size
= len
- skb
->len
;
3528 niu_rx_skb_append(skb
, page
, off
, append_size
);
3529 if ((page
->index
+ rp
->rbr_block_size
) - rcr_size
== addr
) {
3530 *link
= (struct page
*) page
->mapping
;
3531 np
->ops
->unmap_page(np
->device
, page
->index
,
3532 PAGE_SIZE
, DMA_FROM_DEVICE
);
3534 page
->mapping
= NULL
;
3535 rp
->rbr_refill_pending
++;
3539 index
= NEXT_RCR(rp
, index
);
3540 if (!(val
& RCR_ENTRY_MULTI
))
3544 rp
->rcr_index
= index
;
3546 skb_reserve(skb
, NET_IP_ALIGN
);
3547 __pskb_pull_tail(skb
, min(len
, NIU_RXPULL_MAX
));
3550 rp
->rx_bytes
+= skb
->len
;
3552 skb
->protocol
= eth_type_trans(skb
, np
->dev
);
3553 skb_record_rx_queue(skb
, rp
->rx_channel
);
3554 napi_gro_receive(napi
, skb
);
3559 static int niu_rbr_fill(struct niu
*np
, struct rx_ring_info
*rp
, gfp_t mask
)
3561 int blocks_per_page
= rp
->rbr_blocks_per_page
;
3562 int err
, index
= rp
->rbr_index
;
3565 while (index
< (rp
->rbr_table_size
- blocks_per_page
)) {
3566 err
= niu_rbr_add_page(np
, rp
, mask
, index
);
3570 index
+= blocks_per_page
;
3573 rp
->rbr_index
= index
;
3577 static void niu_rbr_free(struct niu
*np
, struct rx_ring_info
*rp
)
3581 for (i
= 0; i
< MAX_RBR_RING_SIZE
; i
++) {
3584 page
= rp
->rxhash
[i
];
3586 struct page
*next
= (struct page
*) page
->mapping
;
3587 u64 base
= page
->index
;
3589 np
->ops
->unmap_page(np
->device
, base
, PAGE_SIZE
,
3592 page
->mapping
= NULL
;
3600 for (i
= 0; i
< rp
->rbr_table_size
; i
++)
3601 rp
->rbr
[i
] = cpu_to_le32(0);
3605 static int release_tx_packet(struct niu
*np
, struct tx_ring_info
*rp
, int idx
)
3607 struct tx_buff_info
*tb
= &rp
->tx_buffs
[idx
];
3608 struct sk_buff
*skb
= tb
->skb
;
3609 struct tx_pkt_hdr
*tp
;
3613 tp
= (struct tx_pkt_hdr
*) skb
->data
;
3614 tx_flags
= le64_to_cpup(&tp
->flags
);
3617 rp
->tx_bytes
+= (((tx_flags
& TXHDR_LEN
) >> TXHDR_LEN_SHIFT
) -
3618 ((tx_flags
& TXHDR_PAD
) / 2));
3620 len
= skb_headlen(skb
);
3621 np
->ops
->unmap_single(np
->device
, tb
->mapping
,
3622 len
, DMA_TO_DEVICE
);
3624 if (le64_to_cpu(rp
->descr
[idx
]) & TX_DESC_MARK
)
3629 idx
= NEXT_TX(rp
, idx
);
3630 len
-= MAX_TX_DESC_LEN
;
3633 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
3634 tb
= &rp
->tx_buffs
[idx
];
3635 BUG_ON(tb
->skb
!= NULL
);
3636 np
->ops
->unmap_page(np
->device
, tb
->mapping
,
3637 skb_shinfo(skb
)->frags
[i
].size
,
3639 idx
= NEXT_TX(rp
, idx
);
3647 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4)
3649 static void niu_tx_work(struct niu
*np
, struct tx_ring_info
*rp
)
3651 struct netdev_queue
*txq
;
3656 index
= (rp
- np
->tx_rings
);
3657 txq
= netdev_get_tx_queue(np
->dev
, index
);
3660 if (unlikely(!(cs
& (TX_CS_MK
| TX_CS_MMK
))))
3663 tmp
= pkt_cnt
= (cs
& TX_CS_PKT_CNT
) >> TX_CS_PKT_CNT_SHIFT
;
3664 pkt_cnt
= (pkt_cnt
- rp
->last_pkt_cnt
) &
3665 (TX_CS_PKT_CNT
>> TX_CS_PKT_CNT_SHIFT
);
3667 rp
->last_pkt_cnt
= tmp
;
3671 niudbg(TX_DONE
, "%s: niu_tx_work() pkt_cnt[%u] cons[%d]\n",
3672 np
->dev
->name
, pkt_cnt
, cons
);
3675 cons
= release_tx_packet(np
, rp
, cons
);
3681 if (unlikely(netif_tx_queue_stopped(txq
) &&
3682 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))) {
3683 __netif_tx_lock(txq
, smp_processor_id());
3684 if (netif_tx_queue_stopped(txq
) &&
3685 (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
)))
3686 netif_tx_wake_queue(txq
);
3687 __netif_tx_unlock(txq
);
3691 static inline void niu_sync_rx_discard_stats(struct niu
*np
,
3692 struct rx_ring_info
*rp
,
3695 /* This elaborate scheme is needed for reading the RX discard
3696 * counters, as they are only 16-bit and can overflow quickly,
3697 * and because the overflow indication bit is not usable as
3698 * the counter value does not wrap, but remains at max value
3701 * In theory and in practice counters can be lost in between
3702 * reading nr64() and clearing the counter nw64(). For this
3703 * reason, the number of counter clearings nw64() is
3704 * limited/reduced though the limit parameter.
3706 int rx_channel
= rp
->rx_channel
;
3709 /* RXMISC (Receive Miscellaneous Discard Count), covers the
3710 * following discard events: IPP (Input Port Process),
3711 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive
3712 * Block Ring) prefetch buffer is empty.
3714 misc
= nr64(RXMISC(rx_channel
));
3715 if (unlikely((misc
& RXMISC_COUNT
) > limit
)) {
3716 nw64(RXMISC(rx_channel
), 0);
3717 rp
->rx_errors
+= misc
& RXMISC_COUNT
;
3719 if (unlikely(misc
& RXMISC_OFLOW
))
3720 dev_err(np
->device
, "rx-%d: Counter overflow "
3721 "RXMISC discard\n", rx_channel
);
3723 niudbg(RX_ERR
, "%s-rx-%d: MISC drop=%u over=%u\n",
3724 np
->dev
->name
, rx_channel
, misc
, misc
-limit
);
3727 /* WRED (Weighted Random Early Discard) by hardware */
3728 wred
= nr64(RED_DIS_CNT(rx_channel
));
3729 if (unlikely((wred
& RED_DIS_CNT_COUNT
) > limit
)) {
3730 nw64(RED_DIS_CNT(rx_channel
), 0);
3731 rp
->rx_dropped
+= wred
& RED_DIS_CNT_COUNT
;
3733 if (unlikely(wred
& RED_DIS_CNT_OFLOW
))
3734 dev_err(np
->device
, "rx-%d: Counter overflow "
3735 "WRED discard\n", rx_channel
);
3737 niudbg(RX_ERR
, "%s-rx-%d: WRED drop=%u over=%u\n",
3738 np
->dev
->name
, rx_channel
, wred
, wred
-limit
);
3742 static int niu_rx_work(struct napi_struct
*napi
, struct niu
*np
,
3743 struct rx_ring_info
*rp
, int budget
)
3745 int qlen
, rcr_done
= 0, work_done
= 0;
3746 struct rxdma_mailbox
*mbox
= rp
->mbox
;
3750 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3751 qlen
= nr64(RCRSTAT_A(rp
->rx_channel
)) & RCRSTAT_A_QLEN
;
3753 stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
3754 qlen
= (le64_to_cpup(&mbox
->rcrstat_a
) & RCRSTAT_A_QLEN
);
3756 mbox
->rx_dma_ctl_stat
= 0;
3757 mbox
->rcrstat_a
= 0;
3759 niudbg(RX_STATUS
, "%s: niu_rx_work(chan[%d]), stat[%llx] qlen=%d\n",
3760 np
->dev
->name
, rp
->rx_channel
, (unsigned long long) stat
, qlen
);
3762 rcr_done
= work_done
= 0;
3763 qlen
= min(qlen
, budget
);
3764 while (work_done
< qlen
) {
3765 rcr_done
+= niu_process_rx_pkt(napi
, np
, rp
);
3769 if (rp
->rbr_refill_pending
>= rp
->rbr_kick_thresh
) {
3772 for (i
= 0; i
< rp
->rbr_refill_pending
; i
++)
3773 niu_rbr_refill(np
, rp
, GFP_ATOMIC
);
3774 rp
->rbr_refill_pending
= 0;
3777 stat
= (RX_DMA_CTL_STAT_MEX
|
3778 ((u64
)work_done
<< RX_DMA_CTL_STAT_PKTREAD_SHIFT
) |
3779 ((u64
)rcr_done
<< RX_DMA_CTL_STAT_PTRREAD_SHIFT
));
3781 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat
);
3783 /* Only sync discards stats when qlen indicate potential for drops */
3785 niu_sync_rx_discard_stats(np
, rp
, 0x7FFF);
3790 static int niu_poll_core(struct niu
*np
, struct niu_ldg
*lp
, int budget
)
3793 u32 tx_vec
= (v0
>> 32);
3794 u32 rx_vec
= (v0
& 0xffffffff);
3795 int i
, work_done
= 0;
3797 niudbg(INTR
, "%s: niu_poll_core() v0[%016llx]\n",
3798 np
->dev
->name
, (unsigned long long) v0
);
3800 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
3801 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
3802 if (tx_vec
& (1 << rp
->tx_channel
))
3803 niu_tx_work(np
, rp
);
3804 nw64(LD_IM0(LDN_TXDMA(rp
->tx_channel
)), 0);
3807 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
3808 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
3810 if (rx_vec
& (1 << rp
->rx_channel
)) {
3813 this_work_done
= niu_rx_work(&lp
->napi
, np
, rp
,
3816 budget
-= this_work_done
;
3817 work_done
+= this_work_done
;
3819 nw64(LD_IM0(LDN_RXDMA(rp
->rx_channel
)), 0);
3825 static int niu_poll(struct napi_struct
*napi
, int budget
)
3827 struct niu_ldg
*lp
= container_of(napi
, struct niu_ldg
, napi
);
3828 struct niu
*np
= lp
->np
;
3831 work_done
= niu_poll_core(np
, lp
, budget
);
3833 if (work_done
< budget
) {
3834 napi_complete(napi
);
3835 niu_ldg_rearm(np
, lp
, 1);
3840 static void niu_log_rxchan_errors(struct niu
*np
, struct rx_ring_info
*rp
,
3843 dev_err(np
->device
, PFX
"%s: RX channel %u errors ( ",
3844 np
->dev
->name
, rp
->rx_channel
);
3846 if (stat
& RX_DMA_CTL_STAT_RBR_TMOUT
)
3847 printk("RBR_TMOUT ");
3848 if (stat
& RX_DMA_CTL_STAT_RSP_CNT_ERR
)
3850 if (stat
& RX_DMA_CTL_STAT_BYTE_EN_BUS
)
3851 printk("BYTE_EN_BUS ");
3852 if (stat
& RX_DMA_CTL_STAT_RSP_DAT_ERR
)
3854 if (stat
& RX_DMA_CTL_STAT_RCR_ACK_ERR
)
3856 if (stat
& RX_DMA_CTL_STAT_RCR_SHA_PAR
)
3857 printk("RCR_SHA_PAR ");
3858 if (stat
& RX_DMA_CTL_STAT_RBR_PRE_PAR
)
3859 printk("RBR_PRE_PAR ");
3860 if (stat
& RX_DMA_CTL_STAT_CONFIG_ERR
)
3862 if (stat
& RX_DMA_CTL_STAT_RCRINCON
)
3863 printk("RCRINCON ");
3864 if (stat
& RX_DMA_CTL_STAT_RCRFULL
)
3866 if (stat
& RX_DMA_CTL_STAT_RBRFULL
)
3868 if (stat
& RX_DMA_CTL_STAT_RBRLOGPAGE
)
3869 printk("RBRLOGPAGE ");
3870 if (stat
& RX_DMA_CTL_STAT_CFIGLOGPAGE
)
3871 printk("CFIGLOGPAGE ");
3872 if (stat
& RX_DMA_CTL_STAT_DC_FIFO_ERR
)
3878 static int niu_rx_error(struct niu
*np
, struct rx_ring_info
*rp
)
3880 u64 stat
= nr64(RX_DMA_CTL_STAT(rp
->rx_channel
));
3884 if (stat
& (RX_DMA_CTL_STAT_CHAN_FATAL
|
3885 RX_DMA_CTL_STAT_PORT_FATAL
))
3889 dev_err(np
->device
, PFX
"%s: RX channel %u error, stat[%llx]\n",
3890 np
->dev
->name
, rp
->rx_channel
,
3891 (unsigned long long) stat
);
3893 niu_log_rxchan_errors(np
, rp
, stat
);
3896 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
3897 stat
& RX_DMA_CTL_WRITE_CLEAR_ERRS
);
3902 static void niu_log_txchan_errors(struct niu
*np
, struct tx_ring_info
*rp
,
3905 dev_err(np
->device
, PFX
"%s: TX channel %u errors ( ",
3906 np
->dev
->name
, rp
->tx_channel
);
3908 if (cs
& TX_CS_MBOX_ERR
)
3910 if (cs
& TX_CS_PKT_SIZE_ERR
)
3911 printk("PKT_SIZE ");
3912 if (cs
& TX_CS_TX_RING_OFLOW
)
3913 printk("TX_RING_OFLOW ");
3914 if (cs
& TX_CS_PREF_BUF_PAR_ERR
)
3915 printk("PREF_BUF_PAR ");
3916 if (cs
& TX_CS_NACK_PREF
)
3917 printk("NACK_PREF ");
3918 if (cs
& TX_CS_NACK_PKT_RD
)
3919 printk("NACK_PKT_RD ");
3920 if (cs
& TX_CS_CONF_PART_ERR
)
3921 printk("CONF_PART ");
3922 if (cs
& TX_CS_PKT_PRT_ERR
)
3928 static int niu_tx_error(struct niu
*np
, struct tx_ring_info
*rp
)
3932 cs
= nr64(TX_CS(rp
->tx_channel
));
3933 logh
= nr64(TX_RNG_ERR_LOGH(rp
->tx_channel
));
3934 logl
= nr64(TX_RNG_ERR_LOGL(rp
->tx_channel
));
3936 dev_err(np
->device
, PFX
"%s: TX channel %u error, "
3937 "cs[%llx] logh[%llx] logl[%llx]\n",
3938 np
->dev
->name
, rp
->tx_channel
,
3939 (unsigned long long) cs
,
3940 (unsigned long long) logh
,
3941 (unsigned long long) logl
);
3943 niu_log_txchan_errors(np
, rp
, cs
);
3948 static int niu_mif_interrupt(struct niu
*np
)
3950 u64 mif_status
= nr64(MIF_STATUS
);
3953 if (np
->flags
& NIU_FLAGS_XMAC
) {
3954 u64 xrxmac_stat
= nr64_mac(XRXMAC_STATUS
);
3956 if (xrxmac_stat
& XRXMAC_STATUS_PHY_MDINT
)
3960 dev_err(np
->device
, PFX
"%s: MIF interrupt, "
3961 "stat[%llx] phy_mdint(%d)\n",
3962 np
->dev
->name
, (unsigned long long) mif_status
, phy_mdint
);
3967 static void niu_xmac_interrupt(struct niu
*np
)
3969 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
3972 val
= nr64_mac(XTXMAC_STATUS
);
3973 if (val
& XTXMAC_STATUS_FRAME_CNT_EXP
)
3974 mp
->tx_frames
+= TXMAC_FRM_CNT_COUNT
;
3975 if (val
& XTXMAC_STATUS_BYTE_CNT_EXP
)
3976 mp
->tx_bytes
+= TXMAC_BYTE_CNT_COUNT
;
3977 if (val
& XTXMAC_STATUS_TXFIFO_XFR_ERR
)
3978 mp
->tx_fifo_errors
++;
3979 if (val
& XTXMAC_STATUS_TXMAC_OFLOW
)
3980 mp
->tx_overflow_errors
++;
3981 if (val
& XTXMAC_STATUS_MAX_PSIZE_ERR
)
3982 mp
->tx_max_pkt_size_errors
++;
3983 if (val
& XTXMAC_STATUS_TXMAC_UFLOW
)
3984 mp
->tx_underflow_errors
++;
3986 val
= nr64_mac(XRXMAC_STATUS
);
3987 if (val
& XRXMAC_STATUS_LCL_FLT_STATUS
)
3988 mp
->rx_local_faults
++;
3989 if (val
& XRXMAC_STATUS_RFLT_DET
)
3990 mp
->rx_remote_faults
++;
3991 if (val
& XRXMAC_STATUS_LFLT_CNT_EXP
)
3992 mp
->rx_link_faults
+= LINK_FAULT_CNT_COUNT
;
3993 if (val
& XRXMAC_STATUS_ALIGNERR_CNT_EXP
)
3994 mp
->rx_align_errors
+= RXMAC_ALIGN_ERR_CNT_COUNT
;
3995 if (val
& XRXMAC_STATUS_RXFRAG_CNT_EXP
)
3996 mp
->rx_frags
+= RXMAC_FRAG_CNT_COUNT
;
3997 if (val
& XRXMAC_STATUS_RXMULTF_CNT_EXP
)
3998 mp
->rx_mcasts
+= RXMAC_MC_FRM_CNT_COUNT
;
3999 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
4000 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
4001 if (val
& XRXMAC_STATUS_RXBCAST_CNT_EXP
)
4002 mp
->rx_bcasts
+= RXMAC_BC_FRM_CNT_COUNT
;
4003 if (val
& XRXMAC_STATUS_RXHIST1_CNT_EXP
)
4004 mp
->rx_hist_cnt1
+= RXMAC_HIST_CNT1_COUNT
;
4005 if (val
& XRXMAC_STATUS_RXHIST2_CNT_EXP
)
4006 mp
->rx_hist_cnt2
+= RXMAC_HIST_CNT2_COUNT
;
4007 if (val
& XRXMAC_STATUS_RXHIST3_CNT_EXP
)
4008 mp
->rx_hist_cnt3
+= RXMAC_HIST_CNT3_COUNT
;
4009 if (val
& XRXMAC_STATUS_RXHIST4_CNT_EXP
)
4010 mp
->rx_hist_cnt4
+= RXMAC_HIST_CNT4_COUNT
;
4011 if (val
& XRXMAC_STATUS_RXHIST5_CNT_EXP
)
4012 mp
->rx_hist_cnt5
+= RXMAC_HIST_CNT5_COUNT
;
4013 if (val
& XRXMAC_STATUS_RXHIST6_CNT_EXP
)
4014 mp
->rx_hist_cnt6
+= RXMAC_HIST_CNT6_COUNT
;
4015 if (val
& XRXMAC_STATUS_RXHIST7_CNT_EXP
)
4016 mp
->rx_hist_cnt7
+= RXMAC_HIST_CNT7_COUNT
;
4017 if (val
& XRXMAC_STAT_MSK_RXOCTET_CNT_EXP
)
4018 mp
->rx_octets
+= RXMAC_BT_CNT_COUNT
;
4019 if (val
& XRXMAC_STATUS_CVIOLERR_CNT_EXP
)
4020 mp
->rx_code_violations
+= RXMAC_CD_VIO_CNT_COUNT
;
4021 if (val
& XRXMAC_STATUS_LENERR_CNT_EXP
)
4022 mp
->rx_len_errors
+= RXMAC_MPSZER_CNT_COUNT
;
4023 if (val
& XRXMAC_STATUS_CRCERR_CNT_EXP
)
4024 mp
->rx_crc_errors
+= RXMAC_CRC_ER_CNT_COUNT
;
4025 if (val
& XRXMAC_STATUS_RXUFLOW
)
4026 mp
->rx_underflows
++;
4027 if (val
& XRXMAC_STATUS_RXOFLOW
)
4030 val
= nr64_mac(XMAC_FC_STAT
);
4031 if (val
& XMAC_FC_STAT_TX_MAC_NPAUSE
)
4032 mp
->pause_off_state
++;
4033 if (val
& XMAC_FC_STAT_TX_MAC_PAUSE
)
4034 mp
->pause_on_state
++;
4035 if (val
& XMAC_FC_STAT_RX_MAC_RPAUSE
)
4036 mp
->pause_received
++;
4039 static void niu_bmac_interrupt(struct niu
*np
)
4041 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
4044 val
= nr64_mac(BTXMAC_STATUS
);
4045 if (val
& BTXMAC_STATUS_UNDERRUN
)
4046 mp
->tx_underflow_errors
++;
4047 if (val
& BTXMAC_STATUS_MAX_PKT_ERR
)
4048 mp
->tx_max_pkt_size_errors
++;
4049 if (val
& BTXMAC_STATUS_BYTE_CNT_EXP
)
4050 mp
->tx_bytes
+= BTXMAC_BYTE_CNT_COUNT
;
4051 if (val
& BTXMAC_STATUS_FRAME_CNT_EXP
)
4052 mp
->tx_frames
+= BTXMAC_FRM_CNT_COUNT
;
4054 val
= nr64_mac(BRXMAC_STATUS
);
4055 if (val
& BRXMAC_STATUS_OVERFLOW
)
4057 if (val
& BRXMAC_STATUS_FRAME_CNT_EXP
)
4058 mp
->rx_frames
+= BRXMAC_FRAME_CNT_COUNT
;
4059 if (val
& BRXMAC_STATUS_ALIGN_ERR_EXP
)
4060 mp
->rx_align_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4061 if (val
& BRXMAC_STATUS_CRC_ERR_EXP
)
4062 mp
->rx_crc_errors
+= BRXMAC_ALIGN_ERR_CNT_COUNT
;
4063 if (val
& BRXMAC_STATUS_LEN_ERR_EXP
)
4064 mp
->rx_len_errors
+= BRXMAC_CODE_VIOL_ERR_CNT_COUNT
;
4066 val
= nr64_mac(BMAC_CTRL_STATUS
);
4067 if (val
& BMAC_CTRL_STATUS_NOPAUSE
)
4068 mp
->pause_off_state
++;
4069 if (val
& BMAC_CTRL_STATUS_PAUSE
)
4070 mp
->pause_on_state
++;
4071 if (val
& BMAC_CTRL_STATUS_PAUSE_RECV
)
4072 mp
->pause_received
++;
4075 static int niu_mac_interrupt(struct niu
*np
)
4077 if (np
->flags
& NIU_FLAGS_XMAC
)
4078 niu_xmac_interrupt(np
);
4080 niu_bmac_interrupt(np
);
4085 static void niu_log_device_error(struct niu
*np
, u64 stat
)
4087 dev_err(np
->device
, PFX
"%s: Core device errors ( ",
4090 if (stat
& SYS_ERR_MASK_META2
)
4092 if (stat
& SYS_ERR_MASK_META1
)
4094 if (stat
& SYS_ERR_MASK_PEU
)
4096 if (stat
& SYS_ERR_MASK_TXC
)
4098 if (stat
& SYS_ERR_MASK_RDMC
)
4100 if (stat
& SYS_ERR_MASK_TDMC
)
4102 if (stat
& SYS_ERR_MASK_ZCP
)
4104 if (stat
& SYS_ERR_MASK_FFLP
)
4106 if (stat
& SYS_ERR_MASK_IPP
)
4108 if (stat
& SYS_ERR_MASK_MAC
)
4110 if (stat
& SYS_ERR_MASK_SMX
)
4116 static int niu_device_error(struct niu
*np
)
4118 u64 stat
= nr64(SYS_ERR_STAT
);
4120 dev_err(np
->device
, PFX
"%s: Core device error, stat[%llx]\n",
4121 np
->dev
->name
, (unsigned long long) stat
);
4123 niu_log_device_error(np
, stat
);
4128 static int niu_slowpath_interrupt(struct niu
*np
, struct niu_ldg
*lp
,
4129 u64 v0
, u64 v1
, u64 v2
)
4138 if (v1
& 0x00000000ffffffffULL
) {
4139 u32 rx_vec
= (v1
& 0xffffffff);
4141 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4142 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4144 if (rx_vec
& (1 << rp
->rx_channel
)) {
4145 int r
= niu_rx_error(np
, rp
);
4150 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
),
4151 RX_DMA_CTL_STAT_MEX
);
4156 if (v1
& 0x7fffffff00000000ULL
) {
4157 u32 tx_vec
= (v1
>> 32) & 0x7fffffff;
4159 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4160 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4162 if (tx_vec
& (1 << rp
->tx_channel
)) {
4163 int r
= niu_tx_error(np
, rp
);
4169 if ((v0
| v1
) & 0x8000000000000000ULL
) {
4170 int r
= niu_mif_interrupt(np
);
4176 int r
= niu_mac_interrupt(np
);
4181 int r
= niu_device_error(np
);
4188 niu_enable_interrupts(np
, 0);
4193 static void niu_rxchan_intr(struct niu
*np
, struct rx_ring_info
*rp
,
4196 struct rxdma_mailbox
*mbox
= rp
->mbox
;
4197 u64 stat_write
, stat
= le64_to_cpup(&mbox
->rx_dma_ctl_stat
);
4199 stat_write
= (RX_DMA_CTL_STAT_RCRTHRES
|
4200 RX_DMA_CTL_STAT_RCRTO
);
4201 nw64(RX_DMA_CTL_STAT(rp
->rx_channel
), stat_write
);
4203 niudbg(INTR
, "%s: rxchan_intr stat[%llx]\n",
4204 np
->dev
->name
, (unsigned long long) stat
);
4207 static void niu_txchan_intr(struct niu
*np
, struct tx_ring_info
*rp
,
4210 rp
->tx_cs
= nr64(TX_CS(rp
->tx_channel
));
4212 niudbg(INTR
, "%s: txchan_intr cs[%llx]\n",
4213 np
->dev
->name
, (unsigned long long) rp
->tx_cs
);
4216 static void __niu_fastpath_interrupt(struct niu
*np
, int ldg
, u64 v0
)
4218 struct niu_parent
*parent
= np
->parent
;
4222 tx_vec
= (v0
>> 32);
4223 rx_vec
= (v0
& 0xffffffff);
4225 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4226 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4227 int ldn
= LDN_RXDMA(rp
->rx_channel
);
4229 if (parent
->ldg_map
[ldn
] != ldg
)
4232 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4233 if (rx_vec
& (1 << rp
->rx_channel
))
4234 niu_rxchan_intr(np
, rp
, ldn
);
4237 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4238 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4239 int ldn
= LDN_TXDMA(rp
->tx_channel
);
4241 if (parent
->ldg_map
[ldn
] != ldg
)
4244 nw64(LD_IM0(ldn
), LD_IM0_MASK
);
4245 if (tx_vec
& (1 << rp
->tx_channel
))
4246 niu_txchan_intr(np
, rp
, ldn
);
4250 static void niu_schedule_napi(struct niu
*np
, struct niu_ldg
*lp
,
4251 u64 v0
, u64 v1
, u64 v2
)
4253 if (likely(napi_schedule_prep(&lp
->napi
))) {
4257 __niu_fastpath_interrupt(np
, lp
->ldg_num
, v0
);
4258 __napi_schedule(&lp
->napi
);
4262 static irqreturn_t
niu_interrupt(int irq
, void *dev_id
)
4264 struct niu_ldg
*lp
= dev_id
;
4265 struct niu
*np
= lp
->np
;
4266 int ldg
= lp
->ldg_num
;
4267 unsigned long flags
;
4270 if (netif_msg_intr(np
))
4271 printk(KERN_DEBUG PFX
"niu_interrupt() ldg[%p](%d) ",
4274 spin_lock_irqsave(&np
->lock
, flags
);
4276 v0
= nr64(LDSV0(ldg
));
4277 v1
= nr64(LDSV1(ldg
));
4278 v2
= nr64(LDSV2(ldg
));
4280 if (netif_msg_intr(np
))
4281 printk("v0[%llx] v1[%llx] v2[%llx]\n",
4282 (unsigned long long) v0
,
4283 (unsigned long long) v1
,
4284 (unsigned long long) v2
);
4286 if (unlikely(!v0
&& !v1
&& !v2
)) {
4287 spin_unlock_irqrestore(&np
->lock
, flags
);
4291 if (unlikely((v0
& ((u64
)1 << LDN_MIF
)) || v1
|| v2
)) {
4292 int err
= niu_slowpath_interrupt(np
, lp
, v0
, v1
, v2
);
4296 if (likely(v0
& ~((u64
)1 << LDN_MIF
)))
4297 niu_schedule_napi(np
, lp
, v0
, v1
, v2
);
4299 niu_ldg_rearm(np
, lp
, 1);
4301 spin_unlock_irqrestore(&np
->lock
, flags
);
4306 static void niu_free_rx_ring_info(struct niu
*np
, struct rx_ring_info
*rp
)
4309 np
->ops
->free_coherent(np
->device
,
4310 sizeof(struct rxdma_mailbox
),
4311 rp
->mbox
, rp
->mbox_dma
);
4315 np
->ops
->free_coherent(np
->device
,
4316 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4317 rp
->rcr
, rp
->rcr_dma
);
4319 rp
->rcr_table_size
= 0;
4323 niu_rbr_free(np
, rp
);
4325 np
->ops
->free_coherent(np
->device
,
4326 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4327 rp
->rbr
, rp
->rbr_dma
);
4329 rp
->rbr_table_size
= 0;
4336 static void niu_free_tx_ring_info(struct niu
*np
, struct tx_ring_info
*rp
)
4339 np
->ops
->free_coherent(np
->device
,
4340 sizeof(struct txdma_mailbox
),
4341 rp
->mbox
, rp
->mbox_dma
);
4347 for (i
= 0; i
< MAX_TX_RING_SIZE
; i
++) {
4348 if (rp
->tx_buffs
[i
].skb
)
4349 (void) release_tx_packet(np
, rp
, i
);
4352 np
->ops
->free_coherent(np
->device
,
4353 MAX_TX_RING_SIZE
* sizeof(__le64
),
4354 rp
->descr
, rp
->descr_dma
);
4363 static void niu_free_channels(struct niu
*np
)
4368 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4369 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4371 niu_free_rx_ring_info(np
, rp
);
4373 kfree(np
->rx_rings
);
4374 np
->rx_rings
= NULL
;
4375 np
->num_rx_rings
= 0;
4379 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4380 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4382 niu_free_tx_ring_info(np
, rp
);
4384 kfree(np
->tx_rings
);
4385 np
->tx_rings
= NULL
;
4386 np
->num_tx_rings
= 0;
4390 static int niu_alloc_rx_ring_info(struct niu
*np
,
4391 struct rx_ring_info
*rp
)
4393 BUILD_BUG_ON(sizeof(struct rxdma_mailbox
) != 64);
4395 rp
->rxhash
= kzalloc(MAX_RBR_RING_SIZE
* sizeof(struct page
*),
4400 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4401 sizeof(struct rxdma_mailbox
),
4402 &rp
->mbox_dma
, GFP_KERNEL
);
4405 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4406 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4407 "RXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
4411 rp
->rcr
= np
->ops
->alloc_coherent(np
->device
,
4412 MAX_RCR_RING_SIZE
* sizeof(__le64
),
4413 &rp
->rcr_dma
, GFP_KERNEL
);
4416 if ((unsigned long)rp
->rcr
& (64UL - 1)) {
4417 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4418 "RXDMA RCR table %p\n", np
->dev
->name
, rp
->rcr
);
4421 rp
->rcr_table_size
= MAX_RCR_RING_SIZE
;
4424 rp
->rbr
= np
->ops
->alloc_coherent(np
->device
,
4425 MAX_RBR_RING_SIZE
* sizeof(__le32
),
4426 &rp
->rbr_dma
, GFP_KERNEL
);
4429 if ((unsigned long)rp
->rbr
& (64UL - 1)) {
4430 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4431 "RXDMA RBR table %p\n", np
->dev
->name
, rp
->rbr
);
4434 rp
->rbr_table_size
= MAX_RBR_RING_SIZE
;
4436 rp
->rbr_pending
= 0;
4441 static void niu_set_max_burst(struct niu
*np
, struct tx_ring_info
*rp
)
4443 int mtu
= np
->dev
->mtu
;
4445 /* These values are recommended by the HW designers for fair
4446 * utilization of DRR amongst the rings.
4448 rp
->max_burst
= mtu
+ 32;
4449 if (rp
->max_burst
> 4096)
4450 rp
->max_burst
= 4096;
4453 static int niu_alloc_tx_ring_info(struct niu
*np
,
4454 struct tx_ring_info
*rp
)
4456 BUILD_BUG_ON(sizeof(struct txdma_mailbox
) != 64);
4458 rp
->mbox
= np
->ops
->alloc_coherent(np
->device
,
4459 sizeof(struct txdma_mailbox
),
4460 &rp
->mbox_dma
, GFP_KERNEL
);
4463 if ((unsigned long)rp
->mbox
& (64UL - 1)) {
4464 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4465 "TXDMA mailbox %p\n", np
->dev
->name
, rp
->mbox
);
4469 rp
->descr
= np
->ops
->alloc_coherent(np
->device
,
4470 MAX_TX_RING_SIZE
* sizeof(__le64
),
4471 &rp
->descr_dma
, GFP_KERNEL
);
4474 if ((unsigned long)rp
->descr
& (64UL - 1)) {
4475 dev_err(np
->device
, PFX
"%s: Coherent alloc gives misaligned "
4476 "TXDMA descr table %p\n", np
->dev
->name
, rp
->descr
);
4480 rp
->pending
= MAX_TX_RING_SIZE
;
4485 /* XXX make these configurable... XXX */
4486 rp
->mark_freq
= rp
->pending
/ 4;
4488 niu_set_max_burst(np
, rp
);
4493 static void niu_size_rbr(struct niu
*np
, struct rx_ring_info
*rp
)
4497 bss
= min(PAGE_SHIFT
, 15);
4499 rp
->rbr_block_size
= 1 << bss
;
4500 rp
->rbr_blocks_per_page
= 1 << (PAGE_SHIFT
-bss
);
4502 rp
->rbr_sizes
[0] = 256;
4503 rp
->rbr_sizes
[1] = 1024;
4504 if (np
->dev
->mtu
> ETH_DATA_LEN
) {
4505 switch (PAGE_SIZE
) {
4507 rp
->rbr_sizes
[2] = 4096;
4511 rp
->rbr_sizes
[2] = 8192;
4515 rp
->rbr_sizes
[2] = 2048;
4517 rp
->rbr_sizes
[3] = rp
->rbr_block_size
;
4520 static int niu_alloc_channels(struct niu
*np
)
4522 struct niu_parent
*parent
= np
->parent
;
4523 int first_rx_channel
, first_tx_channel
;
4527 first_rx_channel
= first_tx_channel
= 0;
4528 for (i
= 0; i
< port
; i
++) {
4529 first_rx_channel
+= parent
->rxchan_per_port
[i
];
4530 first_tx_channel
+= parent
->txchan_per_port
[i
];
4533 np
->num_rx_rings
= parent
->rxchan_per_port
[port
];
4534 np
->num_tx_rings
= parent
->txchan_per_port
[port
];
4536 np
->dev
->real_num_tx_queues
= np
->num_tx_rings
;
4538 np
->rx_rings
= kzalloc(np
->num_rx_rings
* sizeof(struct rx_ring_info
),
4544 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
4545 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
4548 rp
->rx_channel
= first_rx_channel
+ i
;
4550 err
= niu_alloc_rx_ring_info(np
, rp
);
4554 niu_size_rbr(np
, rp
);
4556 /* XXX better defaults, configurable, etc... XXX */
4557 rp
->nonsyn_window
= 64;
4558 rp
->nonsyn_threshold
= rp
->rcr_table_size
- 64;
4559 rp
->syn_window
= 64;
4560 rp
->syn_threshold
= rp
->rcr_table_size
- 64;
4561 rp
->rcr_pkt_threshold
= 16;
4562 rp
->rcr_timeout
= 8;
4563 rp
->rbr_kick_thresh
= RBR_REFILL_MIN
;
4564 if (rp
->rbr_kick_thresh
< rp
->rbr_blocks_per_page
)
4565 rp
->rbr_kick_thresh
= rp
->rbr_blocks_per_page
;
4567 err
= niu_rbr_fill(np
, rp
, GFP_KERNEL
);
4572 np
->tx_rings
= kzalloc(np
->num_tx_rings
* sizeof(struct tx_ring_info
),
4578 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
4579 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
4582 rp
->tx_channel
= first_tx_channel
+ i
;
4584 err
= niu_alloc_tx_ring_info(np
, rp
);
4592 niu_free_channels(np
);
4596 static int niu_tx_cs_sng_poll(struct niu
*np
, int channel
)
4600 while (--limit
> 0) {
4601 u64 val
= nr64(TX_CS(channel
));
4602 if (val
& TX_CS_SNG_STATE
)
4608 static int niu_tx_channel_stop(struct niu
*np
, int channel
)
4610 u64 val
= nr64(TX_CS(channel
));
4612 val
|= TX_CS_STOP_N_GO
;
4613 nw64(TX_CS(channel
), val
);
4615 return niu_tx_cs_sng_poll(np
, channel
);
4618 static int niu_tx_cs_reset_poll(struct niu
*np
, int channel
)
4622 while (--limit
> 0) {
4623 u64 val
= nr64(TX_CS(channel
));
4624 if (!(val
& TX_CS_RST
))
4630 static int niu_tx_channel_reset(struct niu
*np
, int channel
)
4632 u64 val
= nr64(TX_CS(channel
));
4636 nw64(TX_CS(channel
), val
);
4638 err
= niu_tx_cs_reset_poll(np
, channel
);
4640 nw64(TX_RING_KICK(channel
), 0);
4645 static int niu_tx_channel_lpage_init(struct niu
*np
, int channel
)
4649 nw64(TX_LOG_MASK1(channel
), 0);
4650 nw64(TX_LOG_VAL1(channel
), 0);
4651 nw64(TX_LOG_MASK2(channel
), 0);
4652 nw64(TX_LOG_VAL2(channel
), 0);
4653 nw64(TX_LOG_PAGE_RELO1(channel
), 0);
4654 nw64(TX_LOG_PAGE_RELO2(channel
), 0);
4655 nw64(TX_LOG_PAGE_HDL(channel
), 0);
4657 val
= (u64
)np
->port
<< TX_LOG_PAGE_VLD_FUNC_SHIFT
;
4658 val
|= (TX_LOG_PAGE_VLD_PAGE0
| TX_LOG_PAGE_VLD_PAGE1
);
4659 nw64(TX_LOG_PAGE_VLD(channel
), val
);
4661 /* XXX TXDMA 32bit mode? XXX */
4666 static void niu_txc_enable_port(struct niu
*np
, int on
)
4668 unsigned long flags
;
4671 niu_lock_parent(np
, flags
);
4672 val
= nr64(TXC_CONTROL
);
4673 mask
= (u64
)1 << np
->port
;
4675 val
|= TXC_CONTROL_ENABLE
| mask
;
4678 if ((val
& ~TXC_CONTROL_ENABLE
) == 0)
4679 val
&= ~TXC_CONTROL_ENABLE
;
4681 nw64(TXC_CONTROL
, val
);
4682 niu_unlock_parent(np
, flags
);
4685 static void niu_txc_set_imask(struct niu
*np
, u64 imask
)
4687 unsigned long flags
;
4690 niu_lock_parent(np
, flags
);
4691 val
= nr64(TXC_INT_MASK
);
4692 val
&= ~TXC_INT_MASK_VAL(np
->port
);
4693 val
|= (imask
<< TXC_INT_MASK_VAL_SHIFT(np
->port
));
4694 niu_unlock_parent(np
, flags
);
4697 static void niu_txc_port_dma_enable(struct niu
*np
, int on
)
4704 for (i
= 0; i
< np
->num_tx_rings
; i
++)
4705 val
|= (1 << np
->tx_rings
[i
].tx_channel
);
4707 nw64(TXC_PORT_DMA(np
->port
), val
);
4710 static int niu_init_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
4712 int err
, channel
= rp
->tx_channel
;
4715 err
= niu_tx_channel_stop(np
, channel
);
4719 err
= niu_tx_channel_reset(np
, channel
);
4723 err
= niu_tx_channel_lpage_init(np
, channel
);
4727 nw64(TXC_DMA_MAX(channel
), rp
->max_burst
);
4728 nw64(TX_ENT_MSK(channel
), 0);
4730 if (rp
->descr_dma
& ~(TX_RNG_CFIG_STADDR_BASE
|
4731 TX_RNG_CFIG_STADDR
)) {
4732 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4733 "DMA addr (%llx) is not aligned.\n",
4734 np
->dev
->name
, channel
,
4735 (unsigned long long) rp
->descr_dma
);
4739 /* The length field in TX_RNG_CFIG is measured in 64-byte
4740 * blocks. rp->pending is the number of TX descriptors in
4741 * our ring, 8 bytes each, thus we divide by 8 bytes more
4742 * to get the proper value the chip wants.
4744 ring_len
= (rp
->pending
/ 8);
4746 val
= ((ring_len
<< TX_RNG_CFIG_LEN_SHIFT
) |
4748 nw64(TX_RNG_CFIG(channel
), val
);
4750 if (((rp
->mbox_dma
>> 32) & ~TXDMA_MBH_MBADDR
) ||
4751 ((u32
)rp
->mbox_dma
& ~TXDMA_MBL_MBADDR
)) {
4752 dev_err(np
->device
, PFX
"%s: TX ring channel %d "
4753 "MBOX addr (%llx) is has illegal bits.\n",
4754 np
->dev
->name
, channel
,
4755 (unsigned long long) rp
->mbox_dma
);
4758 nw64(TXDMA_MBH(channel
), rp
->mbox_dma
>> 32);
4759 nw64(TXDMA_MBL(channel
), rp
->mbox_dma
& TXDMA_MBL_MBADDR
);
4761 nw64(TX_CS(channel
), 0);
4763 rp
->last_pkt_cnt
= 0;
4768 static void niu_init_rdc_groups(struct niu
*np
)
4770 struct niu_rdc_tables
*tp
= &np
->parent
->rdc_group_cfg
[np
->port
];
4771 int i
, first_table_num
= tp
->first_table_num
;
4773 for (i
= 0; i
< tp
->num_tables
; i
++) {
4774 struct rdc_table
*tbl
= &tp
->tables
[i
];
4775 int this_table
= first_table_num
+ i
;
4778 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++)
4779 nw64(RDC_TBL(this_table
, slot
),
4780 tbl
->rxdma_channel
[slot
]);
4783 nw64(DEF_RDC(np
->port
), np
->parent
->rdc_default
[np
->port
]);
4786 static void niu_init_drr_weight(struct niu
*np
)
4788 int type
= phy_decode(np
->parent
->port_phy
, np
->port
);
4793 val
= PT_DRR_WEIGHT_DEFAULT_10G
;
4798 val
= PT_DRR_WEIGHT_DEFAULT_1G
;
4801 nw64(PT_DRR_WT(np
->port
), val
);
4804 static int niu_init_hostinfo(struct niu
*np
)
4806 struct niu_parent
*parent
= np
->parent
;
4807 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
4808 int i
, err
, num_alt
= niu_num_alt_addr(np
);
4809 int first_rdc_table
= tp
->first_table_num
;
4811 err
= niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
4815 err
= niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
4819 for (i
= 0; i
< num_alt
; i
++) {
4820 err
= niu_set_alt_mac_rdc_table(np
, i
, first_rdc_table
, 1);
4828 static int niu_rx_channel_reset(struct niu
*np
, int channel
)
4830 return niu_set_and_wait_clear(np
, RXDMA_CFIG1(channel
),
4831 RXDMA_CFIG1_RST
, 1000, 10,
4835 static int niu_rx_channel_lpage_init(struct niu
*np
, int channel
)
4839 nw64(RX_LOG_MASK1(channel
), 0);
4840 nw64(RX_LOG_VAL1(channel
), 0);
4841 nw64(RX_LOG_MASK2(channel
), 0);
4842 nw64(RX_LOG_VAL2(channel
), 0);
4843 nw64(RX_LOG_PAGE_RELO1(channel
), 0);
4844 nw64(RX_LOG_PAGE_RELO2(channel
), 0);
4845 nw64(RX_LOG_PAGE_HDL(channel
), 0);
4847 val
= (u64
)np
->port
<< RX_LOG_PAGE_VLD_FUNC_SHIFT
;
4848 val
|= (RX_LOG_PAGE_VLD_PAGE0
| RX_LOG_PAGE_VLD_PAGE1
);
4849 nw64(RX_LOG_PAGE_VLD(channel
), val
);
4854 static void niu_rx_channel_wred_init(struct niu
*np
, struct rx_ring_info
*rp
)
4858 val
= (((u64
)rp
->nonsyn_window
<< RDC_RED_PARA_WIN_SHIFT
) |
4859 ((u64
)rp
->nonsyn_threshold
<< RDC_RED_PARA_THRE_SHIFT
) |
4860 ((u64
)rp
->syn_window
<< RDC_RED_PARA_WIN_SYN_SHIFT
) |
4861 ((u64
)rp
->syn_threshold
<< RDC_RED_PARA_THRE_SYN_SHIFT
));
4862 nw64(RDC_RED_PARA(rp
->rx_channel
), val
);
4865 static int niu_compute_rbr_cfig_b(struct rx_ring_info
*rp
, u64
*ret
)
4870 switch (rp
->rbr_block_size
) {
4872 val
|= (RBR_BLKSIZE_4K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4875 val
|= (RBR_BLKSIZE_8K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4878 val
|= (RBR_BLKSIZE_16K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4881 val
|= (RBR_BLKSIZE_32K
<< RBR_CFIG_B_BLKSIZE_SHIFT
);
4886 val
|= RBR_CFIG_B_VLD2
;
4887 switch (rp
->rbr_sizes
[2]) {
4889 val
|= (RBR_BUFSZ2_2K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4892 val
|= (RBR_BUFSZ2_4K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4895 val
|= (RBR_BUFSZ2_8K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4898 val
|= (RBR_BUFSZ2_16K
<< RBR_CFIG_B_BUFSZ2_SHIFT
);
4904 val
|= RBR_CFIG_B_VLD1
;
4905 switch (rp
->rbr_sizes
[1]) {
4907 val
|= (RBR_BUFSZ1_1K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4910 val
|= (RBR_BUFSZ1_2K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4913 val
|= (RBR_BUFSZ1_4K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4916 val
|= (RBR_BUFSZ1_8K
<< RBR_CFIG_B_BUFSZ1_SHIFT
);
4922 val
|= RBR_CFIG_B_VLD0
;
4923 switch (rp
->rbr_sizes
[0]) {
4925 val
|= (RBR_BUFSZ0_256
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4928 val
|= (RBR_BUFSZ0_512
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4931 val
|= (RBR_BUFSZ0_1K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4934 val
|= (RBR_BUFSZ0_2K
<< RBR_CFIG_B_BUFSZ0_SHIFT
);
4945 static int niu_enable_rx_channel(struct niu
*np
, int channel
, int on
)
4947 u64 val
= nr64(RXDMA_CFIG1(channel
));
4951 val
|= RXDMA_CFIG1_EN
;
4953 val
&= ~RXDMA_CFIG1_EN
;
4954 nw64(RXDMA_CFIG1(channel
), val
);
4957 while (--limit
> 0) {
4958 if (nr64(RXDMA_CFIG1(channel
)) & RXDMA_CFIG1_QST
)
4967 static int niu_init_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
4969 int err
, channel
= rp
->rx_channel
;
4972 err
= niu_rx_channel_reset(np
, channel
);
4976 err
= niu_rx_channel_lpage_init(np
, channel
);
4980 niu_rx_channel_wred_init(np
, rp
);
4982 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_RBR_EMPTY
);
4983 nw64(RX_DMA_CTL_STAT(channel
),
4984 (RX_DMA_CTL_STAT_MEX
|
4985 RX_DMA_CTL_STAT_RCRTHRES
|
4986 RX_DMA_CTL_STAT_RCRTO
|
4987 RX_DMA_CTL_STAT_RBR_EMPTY
));
4988 nw64(RXDMA_CFIG1(channel
), rp
->mbox_dma
>> 32);
4989 nw64(RXDMA_CFIG2(channel
), (rp
->mbox_dma
& 0x00000000ffffffc0));
4990 nw64(RBR_CFIG_A(channel
),
4991 ((u64
)rp
->rbr_table_size
<< RBR_CFIG_A_LEN_SHIFT
) |
4992 (rp
->rbr_dma
& (RBR_CFIG_A_STADDR_BASE
| RBR_CFIG_A_STADDR
)));
4993 err
= niu_compute_rbr_cfig_b(rp
, &val
);
4996 nw64(RBR_CFIG_B(channel
), val
);
4997 nw64(RCRCFIG_A(channel
),
4998 ((u64
)rp
->rcr_table_size
<< RCRCFIG_A_LEN_SHIFT
) |
4999 (rp
->rcr_dma
& (RCRCFIG_A_STADDR_BASE
| RCRCFIG_A_STADDR
)));
5000 nw64(RCRCFIG_B(channel
),
5001 ((u64
)rp
->rcr_pkt_threshold
<< RCRCFIG_B_PTHRES_SHIFT
) |
5003 ((u64
)rp
->rcr_timeout
<< RCRCFIG_B_TIMEOUT_SHIFT
));
5005 err
= niu_enable_rx_channel(np
, channel
, 1);
5009 nw64(RBR_KICK(channel
), rp
->rbr_index
);
5011 val
= nr64(RX_DMA_CTL_STAT(channel
));
5012 val
|= RX_DMA_CTL_STAT_RBR_EMPTY
;
5013 nw64(RX_DMA_CTL_STAT(channel
), val
);
5018 static int niu_init_rx_channels(struct niu
*np
)
5020 unsigned long flags
;
5021 u64 seed
= jiffies_64
;
5024 niu_lock_parent(np
, flags
);
5025 nw64(RX_DMA_CK_DIV
, np
->parent
->rxdma_clock_divider
);
5026 nw64(RED_RAN_INIT
, RED_RAN_INIT_OPMODE
| (seed
& RED_RAN_INIT_VAL
));
5027 niu_unlock_parent(np
, flags
);
5029 /* XXX RXDMA 32bit mode? XXX */
5031 niu_init_rdc_groups(np
);
5032 niu_init_drr_weight(np
);
5034 err
= niu_init_hostinfo(np
);
5038 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5039 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5041 err
= niu_init_one_rx_channel(np
, rp
);
5049 static int niu_set_ip_frag_rule(struct niu
*np
)
5051 struct niu_parent
*parent
= np
->parent
;
5052 struct niu_classifier
*cp
= &np
->clas
;
5053 struct niu_tcam_entry
*tp
;
5056 index
= cp
->tcam_top
;
5057 tp
= &parent
->tcam
[index
];
5059 /* Note that the noport bit is the same in both ipv4 and
5060 * ipv6 format TCAM entries.
5062 memset(tp
, 0, sizeof(*tp
));
5063 tp
->key
[1] = TCAM_V4KEY1_NOPORT
;
5064 tp
->key_mask
[1] = TCAM_V4KEY1_NOPORT
;
5065 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
5066 ((u64
)0 << TCAM_ASSOCDATA_OFFSET_SHIFT
));
5067 err
= tcam_write(np
, index
, tp
->key
, tp
->key_mask
);
5070 err
= tcam_assoc_write(np
, index
, tp
->assoc_data
);
5074 cp
->tcam_valid_entries
++;
5079 static int niu_init_classifier_hw(struct niu
*np
)
5081 struct niu_parent
*parent
= np
->parent
;
5082 struct niu_classifier
*cp
= &np
->clas
;
5085 nw64(H1POLY
, cp
->h1_init
);
5086 nw64(H2POLY
, cp
->h2_init
);
5088 err
= niu_init_hostinfo(np
);
5092 for (i
= 0; i
< ENET_VLAN_TBL_NUM_ENTRIES
; i
++) {
5093 struct niu_vlan_rdc
*vp
= &cp
->vlan_mappings
[i
];
5095 vlan_tbl_write(np
, i
, np
->port
,
5096 vp
->vlan_pref
, vp
->rdc_num
);
5099 for (i
= 0; i
< cp
->num_alt_mac_mappings
; i
++) {
5100 struct niu_altmac_rdc
*ap
= &cp
->alt_mac_mappings
[i
];
5102 err
= niu_set_alt_mac_rdc_table(np
, ap
->alt_mac_num
,
5103 ap
->rdc_num
, ap
->mac_pref
);
5108 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
5109 int index
= i
- CLASS_CODE_USER_PROG1
;
5111 err
= niu_set_tcam_key(np
, i
, parent
->tcam_key
[index
]);
5114 err
= niu_set_flow_key(np
, i
, parent
->flow_key
[index
]);
5119 err
= niu_set_ip_frag_rule(np
);
5128 static int niu_zcp_write(struct niu
*np
, int index
, u64
*data
)
5130 nw64(ZCP_RAM_DATA0
, data
[0]);
5131 nw64(ZCP_RAM_DATA1
, data
[1]);
5132 nw64(ZCP_RAM_DATA2
, data
[2]);
5133 nw64(ZCP_RAM_DATA3
, data
[3]);
5134 nw64(ZCP_RAM_DATA4
, data
[4]);
5135 nw64(ZCP_RAM_BE
, ZCP_RAM_BE_VAL
);
5137 (ZCP_RAM_ACC_WRITE
|
5138 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5139 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5141 return niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5145 static int niu_zcp_read(struct niu
*np
, int index
, u64
*data
)
5149 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5152 dev_err(np
->device
, PFX
"%s: ZCP read busy won't clear, "
5153 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
5154 (unsigned long long) nr64(ZCP_RAM_ACC
));
5160 (0 << ZCP_RAM_ACC_ZFCID_SHIFT
) |
5161 (ZCP_RAM_SEL_CFIFO(np
->port
) << ZCP_RAM_ACC_RAM_SEL_SHIFT
)));
5163 err
= niu_wait_bits_clear(np
, ZCP_RAM_ACC
, ZCP_RAM_ACC_BUSY
,
5166 dev_err(np
->device
, PFX
"%s: ZCP read busy2 won't clear, "
5167 "ZCP_RAM_ACC[%llx]\n", np
->dev
->name
,
5168 (unsigned long long) nr64(ZCP_RAM_ACC
));
5172 data
[0] = nr64(ZCP_RAM_DATA0
);
5173 data
[1] = nr64(ZCP_RAM_DATA1
);
5174 data
[2] = nr64(ZCP_RAM_DATA2
);
5175 data
[3] = nr64(ZCP_RAM_DATA3
);
5176 data
[4] = nr64(ZCP_RAM_DATA4
);
5181 static void niu_zcp_cfifo_reset(struct niu
*np
)
5183 u64 val
= nr64(RESET_CFIFO
);
5185 val
|= RESET_CFIFO_RST(np
->port
);
5186 nw64(RESET_CFIFO
, val
);
5189 val
&= ~RESET_CFIFO_RST(np
->port
);
5190 nw64(RESET_CFIFO
, val
);
5193 static int niu_init_zcp(struct niu
*np
)
5195 u64 data
[5], rbuf
[5];
5198 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5199 if (np
->port
== 0 || np
->port
== 1)
5200 max
= ATLAS_P0_P1_CFIFO_ENTRIES
;
5202 max
= ATLAS_P2_P3_CFIFO_ENTRIES
;
5204 max
= NIU_CFIFO_ENTRIES
;
5212 for (i
= 0; i
< max
; i
++) {
5213 err
= niu_zcp_write(np
, i
, data
);
5216 err
= niu_zcp_read(np
, i
, rbuf
);
5221 niu_zcp_cfifo_reset(np
);
5222 nw64(CFIFO_ECC(np
->port
), 0);
5223 nw64(ZCP_INT_STAT
, ZCP_INT_STAT_ALL
);
5224 (void) nr64(ZCP_INT_STAT
);
5225 nw64(ZCP_INT_MASK
, ZCP_INT_MASK_ALL
);
5230 static void niu_ipp_write(struct niu
*np
, int index
, u64
*data
)
5232 u64 val
= nr64_ipp(IPP_CFIG
);
5234 nw64_ipp(IPP_CFIG
, val
| IPP_CFIG_DFIFO_PIO_W
);
5235 nw64_ipp(IPP_DFIFO_WR_PTR
, index
);
5236 nw64_ipp(IPP_DFIFO_WR0
, data
[0]);
5237 nw64_ipp(IPP_DFIFO_WR1
, data
[1]);
5238 nw64_ipp(IPP_DFIFO_WR2
, data
[2]);
5239 nw64_ipp(IPP_DFIFO_WR3
, data
[3]);
5240 nw64_ipp(IPP_DFIFO_WR4
, data
[4]);
5241 nw64_ipp(IPP_CFIG
, val
& ~IPP_CFIG_DFIFO_PIO_W
);
5244 static void niu_ipp_read(struct niu
*np
, int index
, u64
*data
)
5246 nw64_ipp(IPP_DFIFO_RD_PTR
, index
);
5247 data
[0] = nr64_ipp(IPP_DFIFO_RD0
);
5248 data
[1] = nr64_ipp(IPP_DFIFO_RD1
);
5249 data
[2] = nr64_ipp(IPP_DFIFO_RD2
);
5250 data
[3] = nr64_ipp(IPP_DFIFO_RD3
);
5251 data
[4] = nr64_ipp(IPP_DFIFO_RD4
);
5254 static int niu_ipp_reset(struct niu
*np
)
5256 return niu_set_and_wait_clear_ipp(np
, IPP_CFIG
, IPP_CFIG_SOFT_RST
,
5257 1000, 100, "IPP_CFIG");
5260 static int niu_init_ipp(struct niu
*np
)
5262 u64 data
[5], rbuf
[5], val
;
5265 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
5266 if (np
->port
== 0 || np
->port
== 1)
5267 max
= ATLAS_P0_P1_DFIFO_ENTRIES
;
5269 max
= ATLAS_P2_P3_DFIFO_ENTRIES
;
5271 max
= NIU_DFIFO_ENTRIES
;
5279 for (i
= 0; i
< max
; i
++) {
5280 niu_ipp_write(np
, i
, data
);
5281 niu_ipp_read(np
, i
, rbuf
);
5284 (void) nr64_ipp(IPP_INT_STAT
);
5285 (void) nr64_ipp(IPP_INT_STAT
);
5287 err
= niu_ipp_reset(np
);
5291 (void) nr64_ipp(IPP_PKT_DIS
);
5292 (void) nr64_ipp(IPP_BAD_CS_CNT
);
5293 (void) nr64_ipp(IPP_ECC
);
5295 (void) nr64_ipp(IPP_INT_STAT
);
5297 nw64_ipp(IPP_MSK
, ~IPP_MSK_ALL
);
5299 val
= nr64_ipp(IPP_CFIG
);
5300 val
&= ~IPP_CFIG_IP_MAX_PKT
;
5301 val
|= (IPP_CFIG_IPP_ENABLE
|
5302 IPP_CFIG_DFIFO_ECC_EN
|
5303 IPP_CFIG_DROP_BAD_CRC
|
5305 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT
));
5306 nw64_ipp(IPP_CFIG
, val
);
5311 static void niu_handle_led(struct niu
*np
, int status
)
5314 val
= nr64_mac(XMAC_CONFIG
);
5316 if ((np
->flags
& NIU_FLAGS_10G
) != 0 &&
5317 (np
->flags
& NIU_FLAGS_FIBER
) != 0) {
5319 val
|= XMAC_CONFIG_LED_POLARITY
;
5320 val
&= ~XMAC_CONFIG_FORCE_LED_ON
;
5322 val
|= XMAC_CONFIG_FORCE_LED_ON
;
5323 val
&= ~XMAC_CONFIG_LED_POLARITY
;
5327 nw64_mac(XMAC_CONFIG
, val
);
5330 static void niu_init_xif_xmac(struct niu
*np
)
5332 struct niu_link_config
*lp
= &np
->link_config
;
5335 if (np
->flags
& NIU_FLAGS_XCVR_SERDES
) {
5336 val
= nr64(MIF_CONFIG
);
5337 val
|= MIF_CONFIG_ATCA_GE
;
5338 nw64(MIF_CONFIG
, val
);
5341 val
= nr64_mac(XMAC_CONFIG
);
5342 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5344 val
|= XMAC_CONFIG_TX_OUTPUT_EN
;
5346 if (lp
->loopback_mode
== LOOPBACK_MAC
) {
5347 val
&= ~XMAC_CONFIG_SEL_POR_CLK_SRC
;
5348 val
|= XMAC_CONFIG_LOOPBACK
;
5350 val
&= ~XMAC_CONFIG_LOOPBACK
;
5353 if (np
->flags
& NIU_FLAGS_10G
) {
5354 val
&= ~XMAC_CONFIG_LFS_DISABLE
;
5356 val
|= XMAC_CONFIG_LFS_DISABLE
;
5357 if (!(np
->flags
& NIU_FLAGS_FIBER
) &&
5358 !(np
->flags
& NIU_FLAGS_XCVR_SERDES
))
5359 val
|= XMAC_CONFIG_1G_PCS_BYPASS
;
5361 val
&= ~XMAC_CONFIG_1G_PCS_BYPASS
;
5364 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5366 if (lp
->active_speed
== SPEED_100
)
5367 val
|= XMAC_CONFIG_SEL_CLK_25MHZ
;
5369 val
&= ~XMAC_CONFIG_SEL_CLK_25MHZ
;
5371 nw64_mac(XMAC_CONFIG
, val
);
5373 val
= nr64_mac(XMAC_CONFIG
);
5374 val
&= ~XMAC_CONFIG_MODE_MASK
;
5375 if (np
->flags
& NIU_FLAGS_10G
) {
5376 val
|= XMAC_CONFIG_MODE_XGMII
;
5378 if (lp
->active_speed
== SPEED_1000
)
5379 val
|= XMAC_CONFIG_MODE_GMII
;
5381 val
|= XMAC_CONFIG_MODE_MII
;
5384 nw64_mac(XMAC_CONFIG
, val
);
5387 static void niu_init_xif_bmac(struct niu
*np
)
5389 struct niu_link_config
*lp
= &np
->link_config
;
5392 val
= BMAC_XIF_CONFIG_TX_OUTPUT_EN
;
5394 if (lp
->loopback_mode
== LOOPBACK_MAC
)
5395 val
|= BMAC_XIF_CONFIG_MII_LOOPBACK
;
5397 val
&= ~BMAC_XIF_CONFIG_MII_LOOPBACK
;
5399 if (lp
->active_speed
== SPEED_1000
)
5400 val
|= BMAC_XIF_CONFIG_GMII_MODE
;
5402 val
&= ~BMAC_XIF_CONFIG_GMII_MODE
;
5404 val
&= ~(BMAC_XIF_CONFIG_LINK_LED
|
5405 BMAC_XIF_CONFIG_LED_POLARITY
);
5407 if (!(np
->flags
& NIU_FLAGS_10G
) &&
5408 !(np
->flags
& NIU_FLAGS_FIBER
) &&
5409 lp
->active_speed
== SPEED_100
)
5410 val
|= BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5412 val
&= ~BMAC_XIF_CONFIG_25MHZ_CLOCK
;
5414 nw64_mac(BMAC_XIF_CONFIG
, val
);
5417 static void niu_init_xif(struct niu
*np
)
5419 if (np
->flags
& NIU_FLAGS_XMAC
)
5420 niu_init_xif_xmac(np
);
5422 niu_init_xif_bmac(np
);
5425 static void niu_pcs_mii_reset(struct niu
*np
)
5428 u64 val
= nr64_pcs(PCS_MII_CTL
);
5429 val
|= PCS_MII_CTL_RST
;
5430 nw64_pcs(PCS_MII_CTL
, val
);
5431 while ((--limit
>= 0) && (val
& PCS_MII_CTL_RST
)) {
5433 val
= nr64_pcs(PCS_MII_CTL
);
5437 static void niu_xpcs_reset(struct niu
*np
)
5440 u64 val
= nr64_xpcs(XPCS_CONTROL1
);
5441 val
|= XPCS_CONTROL1_RESET
;
5442 nw64_xpcs(XPCS_CONTROL1
, val
);
5443 while ((--limit
>= 0) && (val
& XPCS_CONTROL1_RESET
)) {
5445 val
= nr64_xpcs(XPCS_CONTROL1
);
5449 static int niu_init_pcs(struct niu
*np
)
5451 struct niu_link_config
*lp
= &np
->link_config
;
5454 switch (np
->flags
& (NIU_FLAGS_10G
|
5456 NIU_FLAGS_XCVR_SERDES
)) {
5457 case NIU_FLAGS_FIBER
:
5459 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5460 nw64_pcs(PCS_DPATH_MODE
, 0);
5461 niu_pcs_mii_reset(np
);
5465 case NIU_FLAGS_10G
| NIU_FLAGS_FIBER
:
5466 case NIU_FLAGS_10G
| NIU_FLAGS_XCVR_SERDES
:
5468 if (!(np
->flags
& NIU_FLAGS_XMAC
))
5471 /* 10G copper or fiber */
5472 val
= nr64_mac(XMAC_CONFIG
);
5473 val
&= ~XMAC_CONFIG_10G_XPCS_BYPASS
;
5474 nw64_mac(XMAC_CONFIG
, val
);
5478 val
= nr64_xpcs(XPCS_CONTROL1
);
5479 if (lp
->loopback_mode
== LOOPBACK_PHY
)
5480 val
|= XPCS_CONTROL1_LOOPBACK
;
5482 val
&= ~XPCS_CONTROL1_LOOPBACK
;
5483 nw64_xpcs(XPCS_CONTROL1
, val
);
5485 nw64_xpcs(XPCS_DESKEW_ERR_CNT
, 0);
5486 (void) nr64_xpcs(XPCS_SYMERR_CNT01
);
5487 (void) nr64_xpcs(XPCS_SYMERR_CNT23
);
5491 case NIU_FLAGS_XCVR_SERDES
:
5493 niu_pcs_mii_reset(np
);
5494 nw64_pcs(PCS_CONF
, PCS_CONF_MASK
| PCS_CONF_ENABLE
);
5495 nw64_pcs(PCS_DPATH_MODE
, 0);
5500 case NIU_FLAGS_XCVR_SERDES
| NIU_FLAGS_FIBER
:
5501 /* 1G RGMII FIBER */
5502 nw64_pcs(PCS_DPATH_MODE
, PCS_DPATH_MODE_MII
);
5503 niu_pcs_mii_reset(np
);
5513 static int niu_reset_tx_xmac(struct niu
*np
)
5515 return niu_set_and_wait_clear_mac(np
, XTXMAC_SW_RST
,
5516 (XTXMAC_SW_RST_REG_RS
|
5517 XTXMAC_SW_RST_SOFT_RST
),
5518 1000, 100, "XTXMAC_SW_RST");
5521 static int niu_reset_tx_bmac(struct niu
*np
)
5525 nw64_mac(BTXMAC_SW_RST
, BTXMAC_SW_RST_RESET
);
5527 while (--limit
>= 0) {
5528 if (!(nr64_mac(BTXMAC_SW_RST
) & BTXMAC_SW_RST_RESET
))
5533 dev_err(np
->device
, PFX
"Port %u TX BMAC would not reset, "
5534 "BTXMAC_SW_RST[%llx]\n",
5536 (unsigned long long) nr64_mac(BTXMAC_SW_RST
));
5543 static int niu_reset_tx_mac(struct niu
*np
)
5545 if (np
->flags
& NIU_FLAGS_XMAC
)
5546 return niu_reset_tx_xmac(np
);
5548 return niu_reset_tx_bmac(np
);
5551 static void niu_init_tx_xmac(struct niu
*np
, u64 min
, u64 max
)
5555 val
= nr64_mac(XMAC_MIN
);
5556 val
&= ~(XMAC_MIN_TX_MIN_PKT_SIZE
|
5557 XMAC_MIN_RX_MIN_PKT_SIZE
);
5558 val
|= (min
<< XMAC_MIN_RX_MIN_PKT_SIZE_SHFT
);
5559 val
|= (min
<< XMAC_MIN_TX_MIN_PKT_SIZE_SHFT
);
5560 nw64_mac(XMAC_MIN
, val
);
5562 nw64_mac(XMAC_MAX
, max
);
5564 nw64_mac(XTXMAC_STAT_MSK
, ~(u64
)0);
5566 val
= nr64_mac(XMAC_IPG
);
5567 if (np
->flags
& NIU_FLAGS_10G
) {
5568 val
&= ~XMAC_IPG_IPG_XGMII
;
5569 val
|= (IPG_12_15_XGMII
<< XMAC_IPG_IPG_XGMII_SHIFT
);
5571 val
&= ~XMAC_IPG_IPG_MII_GMII
;
5572 val
|= (IPG_12_MII_GMII
<< XMAC_IPG_IPG_MII_GMII_SHIFT
);
5574 nw64_mac(XMAC_IPG
, val
);
5576 val
= nr64_mac(XMAC_CONFIG
);
5577 val
&= ~(XMAC_CONFIG_ALWAYS_NO_CRC
|
5578 XMAC_CONFIG_STRETCH_MODE
|
5579 XMAC_CONFIG_VAR_MIN_IPG_EN
|
5580 XMAC_CONFIG_TX_ENABLE
);
5581 nw64_mac(XMAC_CONFIG
, val
);
5583 nw64_mac(TXMAC_FRM_CNT
, 0);
5584 nw64_mac(TXMAC_BYTE_CNT
, 0);
5587 static void niu_init_tx_bmac(struct niu
*np
, u64 min
, u64 max
)
5591 nw64_mac(BMAC_MIN_FRAME
, min
);
5592 nw64_mac(BMAC_MAX_FRAME
, max
);
5594 nw64_mac(BTXMAC_STATUS_MASK
, ~(u64
)0);
5595 nw64_mac(BMAC_CTRL_TYPE
, 0x8808);
5596 nw64_mac(BMAC_PREAMBLE_SIZE
, 7);
5598 val
= nr64_mac(BTXMAC_CONFIG
);
5599 val
&= ~(BTXMAC_CONFIG_FCS_DISABLE
|
5600 BTXMAC_CONFIG_ENABLE
);
5601 nw64_mac(BTXMAC_CONFIG
, val
);
5604 static void niu_init_tx_mac(struct niu
*np
)
5609 if (np
->dev
->mtu
> ETH_DATA_LEN
)
5614 /* The XMAC_MIN register only accepts values for TX min which
5615 * have the low 3 bits cleared.
5617 BUILD_BUG_ON(min
& 0x7);
5619 if (np
->flags
& NIU_FLAGS_XMAC
)
5620 niu_init_tx_xmac(np
, min
, max
);
5622 niu_init_tx_bmac(np
, min
, max
);
5625 static int niu_reset_rx_xmac(struct niu
*np
)
5629 nw64_mac(XRXMAC_SW_RST
,
5630 XRXMAC_SW_RST_REG_RS
| XRXMAC_SW_RST_SOFT_RST
);
5632 while (--limit
>= 0) {
5633 if (!(nr64_mac(XRXMAC_SW_RST
) & (XRXMAC_SW_RST_REG_RS
|
5634 XRXMAC_SW_RST_SOFT_RST
)))
5639 dev_err(np
->device
, PFX
"Port %u RX XMAC would not reset, "
5640 "XRXMAC_SW_RST[%llx]\n",
5642 (unsigned long long) nr64_mac(XRXMAC_SW_RST
));
5649 static int niu_reset_rx_bmac(struct niu
*np
)
5653 nw64_mac(BRXMAC_SW_RST
, BRXMAC_SW_RST_RESET
);
5655 while (--limit
>= 0) {
5656 if (!(nr64_mac(BRXMAC_SW_RST
) & BRXMAC_SW_RST_RESET
))
5661 dev_err(np
->device
, PFX
"Port %u RX BMAC would not reset, "
5662 "BRXMAC_SW_RST[%llx]\n",
5664 (unsigned long long) nr64_mac(BRXMAC_SW_RST
));
5671 static int niu_reset_rx_mac(struct niu
*np
)
5673 if (np
->flags
& NIU_FLAGS_XMAC
)
5674 return niu_reset_rx_xmac(np
);
5676 return niu_reset_rx_bmac(np
);
5679 static void niu_init_rx_xmac(struct niu
*np
)
5681 struct niu_parent
*parent
= np
->parent
;
5682 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5683 int first_rdc_table
= tp
->first_table_num
;
5687 nw64_mac(XMAC_ADD_FILT0
, 0);
5688 nw64_mac(XMAC_ADD_FILT1
, 0);
5689 nw64_mac(XMAC_ADD_FILT2
, 0);
5690 nw64_mac(XMAC_ADD_FILT12_MASK
, 0);
5691 nw64_mac(XMAC_ADD_FILT00_MASK
, 0);
5692 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5693 nw64_mac(XMAC_HASH_TBL(i
), 0);
5694 nw64_mac(XRXMAC_STAT_MSK
, ~(u64
)0);
5695 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5696 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5698 val
= nr64_mac(XMAC_CONFIG
);
5699 val
&= ~(XMAC_CONFIG_RX_MAC_ENABLE
|
5700 XMAC_CONFIG_PROMISCUOUS
|
5701 XMAC_CONFIG_PROMISC_GROUP
|
5702 XMAC_CONFIG_ERR_CHK_DIS
|
5703 XMAC_CONFIG_RX_CRC_CHK_DIS
|
5704 XMAC_CONFIG_RESERVED_MULTICAST
|
5705 XMAC_CONFIG_RX_CODEV_CHK_DIS
|
5706 XMAC_CONFIG_ADDR_FILTER_EN
|
5707 XMAC_CONFIG_RCV_PAUSE_ENABLE
|
5708 XMAC_CONFIG_STRIP_CRC
|
5709 XMAC_CONFIG_PASS_FLOW_CTRL
|
5710 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN
);
5711 val
|= (XMAC_CONFIG_HASH_FILTER_EN
);
5712 nw64_mac(XMAC_CONFIG
, val
);
5714 nw64_mac(RXMAC_BT_CNT
, 0);
5715 nw64_mac(RXMAC_BC_FRM_CNT
, 0);
5716 nw64_mac(RXMAC_MC_FRM_CNT
, 0);
5717 nw64_mac(RXMAC_FRAG_CNT
, 0);
5718 nw64_mac(RXMAC_HIST_CNT1
, 0);
5719 nw64_mac(RXMAC_HIST_CNT2
, 0);
5720 nw64_mac(RXMAC_HIST_CNT3
, 0);
5721 nw64_mac(RXMAC_HIST_CNT4
, 0);
5722 nw64_mac(RXMAC_HIST_CNT5
, 0);
5723 nw64_mac(RXMAC_HIST_CNT6
, 0);
5724 nw64_mac(RXMAC_HIST_CNT7
, 0);
5725 nw64_mac(RXMAC_MPSZER_CNT
, 0);
5726 nw64_mac(RXMAC_CRC_ER_CNT
, 0);
5727 nw64_mac(RXMAC_CD_VIO_CNT
, 0);
5728 nw64_mac(LINK_FAULT_CNT
, 0);
5731 static void niu_init_rx_bmac(struct niu
*np
)
5733 struct niu_parent
*parent
= np
->parent
;
5734 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[np
->port
];
5735 int first_rdc_table
= tp
->first_table_num
;
5739 nw64_mac(BMAC_ADD_FILT0
, 0);
5740 nw64_mac(BMAC_ADD_FILT1
, 0);
5741 nw64_mac(BMAC_ADD_FILT2
, 0);
5742 nw64_mac(BMAC_ADD_FILT12_MASK
, 0);
5743 nw64_mac(BMAC_ADD_FILT00_MASK
, 0);
5744 for (i
= 0; i
< MAC_NUM_HASH
; i
++)
5745 nw64_mac(BMAC_HASH_TBL(i
), 0);
5746 niu_set_primary_mac_rdc_table(np
, first_rdc_table
, 1);
5747 niu_set_multicast_mac_rdc_table(np
, first_rdc_table
, 1);
5748 nw64_mac(BRXMAC_STATUS_MASK
, ~(u64
)0);
5750 val
= nr64_mac(BRXMAC_CONFIG
);
5751 val
&= ~(BRXMAC_CONFIG_ENABLE
|
5752 BRXMAC_CONFIG_STRIP_PAD
|
5753 BRXMAC_CONFIG_STRIP_FCS
|
5754 BRXMAC_CONFIG_PROMISC
|
5755 BRXMAC_CONFIG_PROMISC_GRP
|
5756 BRXMAC_CONFIG_ADDR_FILT_EN
|
5757 BRXMAC_CONFIG_DISCARD_DIS
);
5758 val
|= (BRXMAC_CONFIG_HASH_FILT_EN
);
5759 nw64_mac(BRXMAC_CONFIG
, val
);
5761 val
= nr64_mac(BMAC_ADDR_CMPEN
);
5762 val
|= BMAC_ADDR_CMPEN_EN0
;
5763 nw64_mac(BMAC_ADDR_CMPEN
, val
);
5766 static void niu_init_rx_mac(struct niu
*np
)
5768 niu_set_primary_mac(np
, np
->dev
->dev_addr
);
5770 if (np
->flags
& NIU_FLAGS_XMAC
)
5771 niu_init_rx_xmac(np
);
5773 niu_init_rx_bmac(np
);
5776 static void niu_enable_tx_xmac(struct niu
*np
, int on
)
5778 u64 val
= nr64_mac(XMAC_CONFIG
);
5781 val
|= XMAC_CONFIG_TX_ENABLE
;
5783 val
&= ~XMAC_CONFIG_TX_ENABLE
;
5784 nw64_mac(XMAC_CONFIG
, val
);
5787 static void niu_enable_tx_bmac(struct niu
*np
, int on
)
5789 u64 val
= nr64_mac(BTXMAC_CONFIG
);
5792 val
|= BTXMAC_CONFIG_ENABLE
;
5794 val
&= ~BTXMAC_CONFIG_ENABLE
;
5795 nw64_mac(BTXMAC_CONFIG
, val
);
5798 static void niu_enable_tx_mac(struct niu
*np
, int on
)
5800 if (np
->flags
& NIU_FLAGS_XMAC
)
5801 niu_enable_tx_xmac(np
, on
);
5803 niu_enable_tx_bmac(np
, on
);
5806 static void niu_enable_rx_xmac(struct niu
*np
, int on
)
5808 u64 val
= nr64_mac(XMAC_CONFIG
);
5810 val
&= ~(XMAC_CONFIG_HASH_FILTER_EN
|
5811 XMAC_CONFIG_PROMISCUOUS
);
5813 if (np
->flags
& NIU_FLAGS_MCAST
)
5814 val
|= XMAC_CONFIG_HASH_FILTER_EN
;
5815 if (np
->flags
& NIU_FLAGS_PROMISC
)
5816 val
|= XMAC_CONFIG_PROMISCUOUS
;
5819 val
|= XMAC_CONFIG_RX_MAC_ENABLE
;
5821 val
&= ~XMAC_CONFIG_RX_MAC_ENABLE
;
5822 nw64_mac(XMAC_CONFIG
, val
);
5825 static void niu_enable_rx_bmac(struct niu
*np
, int on
)
5827 u64 val
= nr64_mac(BRXMAC_CONFIG
);
5829 val
&= ~(BRXMAC_CONFIG_HASH_FILT_EN
|
5830 BRXMAC_CONFIG_PROMISC
);
5832 if (np
->flags
& NIU_FLAGS_MCAST
)
5833 val
|= BRXMAC_CONFIG_HASH_FILT_EN
;
5834 if (np
->flags
& NIU_FLAGS_PROMISC
)
5835 val
|= BRXMAC_CONFIG_PROMISC
;
5838 val
|= BRXMAC_CONFIG_ENABLE
;
5840 val
&= ~BRXMAC_CONFIG_ENABLE
;
5841 nw64_mac(BRXMAC_CONFIG
, val
);
5844 static void niu_enable_rx_mac(struct niu
*np
, int on
)
5846 if (np
->flags
& NIU_FLAGS_XMAC
)
5847 niu_enable_rx_xmac(np
, on
);
5849 niu_enable_rx_bmac(np
, on
);
5852 static int niu_init_mac(struct niu
*np
)
5857 err
= niu_init_pcs(np
);
5861 err
= niu_reset_tx_mac(np
);
5864 niu_init_tx_mac(np
);
5865 err
= niu_reset_rx_mac(np
);
5868 niu_init_rx_mac(np
);
5870 /* This looks hookey but the RX MAC reset we just did will
5871 * undo some of the state we setup in niu_init_tx_mac() so we
5872 * have to call it again. In particular, the RX MAC reset will
5873 * set the XMAC_MAX register back to it's default value.
5875 niu_init_tx_mac(np
);
5876 niu_enable_tx_mac(np
, 1);
5878 niu_enable_rx_mac(np
, 1);
5883 static void niu_stop_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5885 (void) niu_tx_channel_stop(np
, rp
->tx_channel
);
5888 static void niu_stop_tx_channels(struct niu
*np
)
5892 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5893 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5895 niu_stop_one_tx_channel(np
, rp
);
5899 static void niu_reset_one_tx_channel(struct niu
*np
, struct tx_ring_info
*rp
)
5901 (void) niu_tx_channel_reset(np
, rp
->tx_channel
);
5904 static void niu_reset_tx_channels(struct niu
*np
)
5908 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5909 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5911 niu_reset_one_tx_channel(np
, rp
);
5915 static void niu_stop_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5917 (void) niu_enable_rx_channel(np
, rp
->rx_channel
, 0);
5920 static void niu_stop_rx_channels(struct niu
*np
)
5924 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5925 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5927 niu_stop_one_rx_channel(np
, rp
);
5931 static void niu_reset_one_rx_channel(struct niu
*np
, struct rx_ring_info
*rp
)
5933 int channel
= rp
->rx_channel
;
5935 (void) niu_rx_channel_reset(np
, channel
);
5936 nw64(RX_DMA_ENT_MSK(channel
), RX_DMA_ENT_MSK_ALL
);
5937 nw64(RX_DMA_CTL_STAT(channel
), 0);
5938 (void) niu_enable_rx_channel(np
, channel
, 0);
5941 static void niu_reset_rx_channels(struct niu
*np
)
5945 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
5946 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
5948 niu_reset_one_rx_channel(np
, rp
);
5952 static void niu_disable_ipp(struct niu
*np
)
5957 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5958 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5960 while (--limit
>= 0 && (rd
!= wr
)) {
5961 rd
= nr64_ipp(IPP_DFIFO_RD_PTR
);
5962 wr
= nr64_ipp(IPP_DFIFO_WR_PTR
);
5965 (rd
!= 0 && wr
!= 1)) {
5966 dev_err(np
->device
, PFX
"%s: IPP would not quiesce, "
5967 "rd_ptr[%llx] wr_ptr[%llx]\n",
5969 (unsigned long long) nr64_ipp(IPP_DFIFO_RD_PTR
),
5970 (unsigned long long) nr64_ipp(IPP_DFIFO_WR_PTR
));
5973 val
= nr64_ipp(IPP_CFIG
);
5974 val
&= ~(IPP_CFIG_IPP_ENABLE
|
5975 IPP_CFIG_DFIFO_ECC_EN
|
5976 IPP_CFIG_DROP_BAD_CRC
|
5978 nw64_ipp(IPP_CFIG
, val
);
5980 (void) niu_ipp_reset(np
);
5983 static int niu_init_hw(struct niu
*np
)
5987 niudbg(IFUP
, "%s: Initialize TXC\n", np
->dev
->name
);
5988 niu_txc_enable_port(np
, 1);
5989 niu_txc_port_dma_enable(np
, 1);
5990 niu_txc_set_imask(np
, 0);
5992 niudbg(IFUP
, "%s: Initialize TX channels\n", np
->dev
->name
);
5993 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
5994 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
5996 err
= niu_init_one_tx_channel(np
, rp
);
6001 niudbg(IFUP
, "%s: Initialize RX channels\n", np
->dev
->name
);
6002 err
= niu_init_rx_channels(np
);
6004 goto out_uninit_tx_channels
;
6006 niudbg(IFUP
, "%s: Initialize classifier\n", np
->dev
->name
);
6007 err
= niu_init_classifier_hw(np
);
6009 goto out_uninit_rx_channels
;
6011 niudbg(IFUP
, "%s: Initialize ZCP\n", np
->dev
->name
);
6012 err
= niu_init_zcp(np
);
6014 goto out_uninit_rx_channels
;
6016 niudbg(IFUP
, "%s: Initialize IPP\n", np
->dev
->name
);
6017 err
= niu_init_ipp(np
);
6019 goto out_uninit_rx_channels
;
6021 niudbg(IFUP
, "%s: Initialize MAC\n", np
->dev
->name
);
6022 err
= niu_init_mac(np
);
6024 goto out_uninit_ipp
;
6029 niudbg(IFUP
, "%s: Uninit IPP\n", np
->dev
->name
);
6030 niu_disable_ipp(np
);
6032 out_uninit_rx_channels
:
6033 niudbg(IFUP
, "%s: Uninit RX channels\n", np
->dev
->name
);
6034 niu_stop_rx_channels(np
);
6035 niu_reset_rx_channels(np
);
6037 out_uninit_tx_channels
:
6038 niudbg(IFUP
, "%s: Uninit TX channels\n", np
->dev
->name
);
6039 niu_stop_tx_channels(np
);
6040 niu_reset_tx_channels(np
);
6045 static void niu_stop_hw(struct niu
*np
)
6047 niudbg(IFDOWN
, "%s: Disable interrupts\n", np
->dev
->name
);
6048 niu_enable_interrupts(np
, 0);
6050 niudbg(IFDOWN
, "%s: Disable RX MAC\n", np
->dev
->name
);
6051 niu_enable_rx_mac(np
, 0);
6053 niudbg(IFDOWN
, "%s: Disable IPP\n", np
->dev
->name
);
6054 niu_disable_ipp(np
);
6056 niudbg(IFDOWN
, "%s: Stop TX channels\n", np
->dev
->name
);
6057 niu_stop_tx_channels(np
);
6059 niudbg(IFDOWN
, "%s: Stop RX channels\n", np
->dev
->name
);
6060 niu_stop_rx_channels(np
);
6062 niudbg(IFDOWN
, "%s: Reset TX channels\n", np
->dev
->name
);
6063 niu_reset_tx_channels(np
);
6065 niudbg(IFDOWN
, "%s: Reset RX channels\n", np
->dev
->name
);
6066 niu_reset_rx_channels(np
);
6069 static void niu_set_irq_name(struct niu
*np
)
6071 int port
= np
->port
;
6074 sprintf(np
->irq_name
[0], "%s:MAC", np
->dev
->name
);
6077 sprintf(np
->irq_name
[1], "%s:MIF", np
->dev
->name
);
6078 sprintf(np
->irq_name
[2], "%s:SYSERR", np
->dev
->name
);
6082 for (i
= 0; i
< np
->num_ldg
- j
; i
++) {
6083 if (i
< np
->num_rx_rings
)
6084 sprintf(np
->irq_name
[i
+j
], "%s-rx-%d",
6086 else if (i
< np
->num_tx_rings
+ np
->num_rx_rings
)
6087 sprintf(np
->irq_name
[i
+j
], "%s-tx-%d", np
->dev
->name
,
6088 i
- np
->num_rx_rings
);
6092 static int niu_request_irq(struct niu
*np
)
6096 niu_set_irq_name(np
);
6099 for (i
= 0; i
< np
->num_ldg
; i
++) {
6100 struct niu_ldg
*lp
= &np
->ldg
[i
];
6102 err
= request_irq(lp
->irq
, niu_interrupt
,
6103 IRQF_SHARED
| IRQF_SAMPLE_RANDOM
,
6104 np
->irq_name
[i
], lp
);
6113 for (j
= 0; j
< i
; j
++) {
6114 struct niu_ldg
*lp
= &np
->ldg
[j
];
6116 free_irq(lp
->irq
, lp
);
6121 static void niu_free_irq(struct niu
*np
)
6125 for (i
= 0; i
< np
->num_ldg
; i
++) {
6126 struct niu_ldg
*lp
= &np
->ldg
[i
];
6128 free_irq(lp
->irq
, lp
);
6132 static void niu_enable_napi(struct niu
*np
)
6136 for (i
= 0; i
< np
->num_ldg
; i
++)
6137 napi_enable(&np
->ldg
[i
].napi
);
6140 static void niu_disable_napi(struct niu
*np
)
6144 for (i
= 0; i
< np
->num_ldg
; i
++)
6145 napi_disable(&np
->ldg
[i
].napi
);
6148 static int niu_open(struct net_device
*dev
)
6150 struct niu
*np
= netdev_priv(dev
);
6153 netif_carrier_off(dev
);
6155 err
= niu_alloc_channels(np
);
6159 err
= niu_enable_interrupts(np
, 0);
6161 goto out_free_channels
;
6163 err
= niu_request_irq(np
);
6165 goto out_free_channels
;
6167 niu_enable_napi(np
);
6169 spin_lock_irq(&np
->lock
);
6171 err
= niu_init_hw(np
);
6173 init_timer(&np
->timer
);
6174 np
->timer
.expires
= jiffies
+ HZ
;
6175 np
->timer
.data
= (unsigned long) np
;
6176 np
->timer
.function
= niu_timer
;
6178 err
= niu_enable_interrupts(np
, 1);
6183 spin_unlock_irq(&np
->lock
);
6186 niu_disable_napi(np
);
6190 netif_tx_start_all_queues(dev
);
6192 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6193 netif_carrier_on(dev
);
6195 add_timer(&np
->timer
);
6203 niu_free_channels(np
);
6209 static void niu_full_shutdown(struct niu
*np
, struct net_device
*dev
)
6211 cancel_work_sync(&np
->reset_task
);
6213 niu_disable_napi(np
);
6214 netif_tx_stop_all_queues(dev
);
6216 del_timer_sync(&np
->timer
);
6218 spin_lock_irq(&np
->lock
);
6222 spin_unlock_irq(&np
->lock
);
6225 static int niu_close(struct net_device
*dev
)
6227 struct niu
*np
= netdev_priv(dev
);
6229 niu_full_shutdown(np
, dev
);
6233 niu_free_channels(np
);
6235 niu_handle_led(np
, 0);
6240 static void niu_sync_xmac_stats(struct niu
*np
)
6242 struct niu_xmac_stats
*mp
= &np
->mac_stats
.xmac
;
6244 mp
->tx_frames
+= nr64_mac(TXMAC_FRM_CNT
);
6245 mp
->tx_bytes
+= nr64_mac(TXMAC_BYTE_CNT
);
6247 mp
->rx_link_faults
+= nr64_mac(LINK_FAULT_CNT
);
6248 mp
->rx_align_errors
+= nr64_mac(RXMAC_ALIGN_ERR_CNT
);
6249 mp
->rx_frags
+= nr64_mac(RXMAC_FRAG_CNT
);
6250 mp
->rx_mcasts
+= nr64_mac(RXMAC_MC_FRM_CNT
);
6251 mp
->rx_bcasts
+= nr64_mac(RXMAC_BC_FRM_CNT
);
6252 mp
->rx_hist_cnt1
+= nr64_mac(RXMAC_HIST_CNT1
);
6253 mp
->rx_hist_cnt2
+= nr64_mac(RXMAC_HIST_CNT2
);
6254 mp
->rx_hist_cnt3
+= nr64_mac(RXMAC_HIST_CNT3
);
6255 mp
->rx_hist_cnt4
+= nr64_mac(RXMAC_HIST_CNT4
);
6256 mp
->rx_hist_cnt5
+= nr64_mac(RXMAC_HIST_CNT5
);
6257 mp
->rx_hist_cnt6
+= nr64_mac(RXMAC_HIST_CNT6
);
6258 mp
->rx_hist_cnt7
+= nr64_mac(RXMAC_HIST_CNT7
);
6259 mp
->rx_octets
+= nr64_mac(RXMAC_BT_CNT
);
6260 mp
->rx_code_violations
+= nr64_mac(RXMAC_CD_VIO_CNT
);
6261 mp
->rx_len_errors
+= nr64_mac(RXMAC_MPSZER_CNT
);
6262 mp
->rx_crc_errors
+= nr64_mac(RXMAC_CRC_ER_CNT
);
6265 static void niu_sync_bmac_stats(struct niu
*np
)
6267 struct niu_bmac_stats
*mp
= &np
->mac_stats
.bmac
;
6269 mp
->tx_bytes
+= nr64_mac(BTXMAC_BYTE_CNT
);
6270 mp
->tx_frames
+= nr64_mac(BTXMAC_FRM_CNT
);
6272 mp
->rx_frames
+= nr64_mac(BRXMAC_FRAME_CNT
);
6273 mp
->rx_align_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6274 mp
->rx_crc_errors
+= nr64_mac(BRXMAC_ALIGN_ERR_CNT
);
6275 mp
->rx_len_errors
+= nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT
);
6278 static void niu_sync_mac_stats(struct niu
*np
)
6280 if (np
->flags
& NIU_FLAGS_XMAC
)
6281 niu_sync_xmac_stats(np
);
6283 niu_sync_bmac_stats(np
);
6286 static void niu_get_rx_stats(struct niu
*np
)
6288 unsigned long pkts
, dropped
, errors
, bytes
;
6291 pkts
= dropped
= errors
= bytes
= 0;
6292 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6293 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6295 niu_sync_rx_discard_stats(np
, rp
, 0);
6297 pkts
+= rp
->rx_packets
;
6298 bytes
+= rp
->rx_bytes
;
6299 dropped
+= rp
->rx_dropped
;
6300 errors
+= rp
->rx_errors
;
6302 np
->dev
->stats
.rx_packets
= pkts
;
6303 np
->dev
->stats
.rx_bytes
= bytes
;
6304 np
->dev
->stats
.rx_dropped
= dropped
;
6305 np
->dev
->stats
.rx_errors
= errors
;
6308 static void niu_get_tx_stats(struct niu
*np
)
6310 unsigned long pkts
, errors
, bytes
;
6313 pkts
= errors
= bytes
= 0;
6314 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6315 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6317 pkts
+= rp
->tx_packets
;
6318 bytes
+= rp
->tx_bytes
;
6319 errors
+= rp
->tx_errors
;
6321 np
->dev
->stats
.tx_packets
= pkts
;
6322 np
->dev
->stats
.tx_bytes
= bytes
;
6323 np
->dev
->stats
.tx_errors
= errors
;
6326 static struct net_device_stats
*niu_get_stats(struct net_device
*dev
)
6328 struct niu
*np
= netdev_priv(dev
);
6330 niu_get_rx_stats(np
);
6331 niu_get_tx_stats(np
);
6336 static void niu_load_hash_xmac(struct niu
*np
, u16
*hash
)
6340 for (i
= 0; i
< 16; i
++)
6341 nw64_mac(XMAC_HASH_TBL(i
), hash
[i
]);
6344 static void niu_load_hash_bmac(struct niu
*np
, u16
*hash
)
6348 for (i
= 0; i
< 16; i
++)
6349 nw64_mac(BMAC_HASH_TBL(i
), hash
[i
]);
6352 static void niu_load_hash(struct niu
*np
, u16
*hash
)
6354 if (np
->flags
& NIU_FLAGS_XMAC
)
6355 niu_load_hash_xmac(np
, hash
);
6357 niu_load_hash_bmac(np
, hash
);
6360 static void niu_set_rx_mode(struct net_device
*dev
)
6362 struct niu
*np
= netdev_priv(dev
);
6363 int i
, alt_cnt
, err
;
6364 struct dev_addr_list
*addr
;
6365 unsigned long flags
;
6366 u16 hash
[16] = { 0, };
6368 spin_lock_irqsave(&np
->lock
, flags
);
6369 niu_enable_rx_mac(np
, 0);
6371 np
->flags
&= ~(NIU_FLAGS_MCAST
| NIU_FLAGS_PROMISC
);
6372 if (dev
->flags
& IFF_PROMISC
)
6373 np
->flags
|= NIU_FLAGS_PROMISC
;
6374 if ((dev
->flags
& IFF_ALLMULTI
) || (dev
->mc_count
> 0))
6375 np
->flags
|= NIU_FLAGS_MCAST
;
6377 alt_cnt
= dev
->uc_count
;
6378 if (alt_cnt
> niu_num_alt_addr(np
)) {
6380 np
->flags
|= NIU_FLAGS_PROMISC
;
6386 for (addr
= dev
->uc_list
; addr
; addr
= addr
->next
) {
6387 err
= niu_set_alt_mac(np
, index
,
6390 printk(KERN_WARNING PFX
"%s: Error %d "
6391 "adding alt mac %d\n",
6392 dev
->name
, err
, index
);
6393 err
= niu_enable_alt_mac(np
, index
, 1);
6395 printk(KERN_WARNING PFX
"%s: Error %d "
6396 "enabling alt mac %d\n",
6397 dev
->name
, err
, index
);
6403 if (np
->flags
& NIU_FLAGS_XMAC
)
6407 for (i
= alt_start
; i
< niu_num_alt_addr(np
); i
++) {
6408 err
= niu_enable_alt_mac(np
, i
, 0);
6410 printk(KERN_WARNING PFX
"%s: Error %d "
6411 "disabling alt mac %d\n",
6415 if (dev
->flags
& IFF_ALLMULTI
) {
6416 for (i
= 0; i
< 16; i
++)
6418 } else if (dev
->mc_count
> 0) {
6419 for (addr
= dev
->mc_list
; addr
; addr
= addr
->next
) {
6420 u32 crc
= ether_crc_le(ETH_ALEN
, addr
->da_addr
);
6423 hash
[crc
>> 4] |= (1 << (15 - (crc
& 0xf)));
6427 if (np
->flags
& NIU_FLAGS_MCAST
)
6428 niu_load_hash(np
, hash
);
6430 niu_enable_rx_mac(np
, 1);
6431 spin_unlock_irqrestore(&np
->lock
, flags
);
6434 static int niu_set_mac_addr(struct net_device
*dev
, void *p
)
6436 struct niu
*np
= netdev_priv(dev
);
6437 struct sockaddr
*addr
= p
;
6438 unsigned long flags
;
6440 if (!is_valid_ether_addr(addr
->sa_data
))
6443 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
6445 if (!netif_running(dev
))
6448 spin_lock_irqsave(&np
->lock
, flags
);
6449 niu_enable_rx_mac(np
, 0);
6450 niu_set_primary_mac(np
, dev
->dev_addr
);
6451 niu_enable_rx_mac(np
, 1);
6452 spin_unlock_irqrestore(&np
->lock
, flags
);
6457 static int niu_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
6462 static void niu_netif_stop(struct niu
*np
)
6464 np
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
6466 niu_disable_napi(np
);
6468 netif_tx_disable(np
->dev
);
6471 static void niu_netif_start(struct niu
*np
)
6473 /* NOTE: unconditional netif_wake_queue is only appropriate
6474 * so long as all callers are assured to have free tx slots
6475 * (such as after niu_init_hw).
6477 netif_tx_wake_all_queues(np
->dev
);
6479 niu_enable_napi(np
);
6481 niu_enable_interrupts(np
, 1);
6484 static void niu_reset_buffers(struct niu
*np
)
6489 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
6490 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
6492 for (j
= 0, k
= 0; j
< MAX_RBR_RING_SIZE
; j
++) {
6495 page
= rp
->rxhash
[j
];
6498 (struct page
*) page
->mapping
;
6499 u64 base
= page
->index
;
6500 base
= base
>> RBR_DESCR_ADDR_SHIFT
;
6501 rp
->rbr
[k
++] = cpu_to_le32(base
);
6505 for (; k
< MAX_RBR_RING_SIZE
; k
++) {
6506 err
= niu_rbr_add_page(np
, rp
, GFP_ATOMIC
, k
);
6511 rp
->rbr_index
= rp
->rbr_table_size
- 1;
6513 rp
->rbr_pending
= 0;
6514 rp
->rbr_refill_pending
= 0;
6518 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
6519 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
6521 for (j
= 0; j
< MAX_TX_RING_SIZE
; j
++) {
6522 if (rp
->tx_buffs
[j
].skb
)
6523 (void) release_tx_packet(np
, rp
, j
);
6526 rp
->pending
= MAX_TX_RING_SIZE
;
6534 static void niu_reset_task(struct work_struct
*work
)
6536 struct niu
*np
= container_of(work
, struct niu
, reset_task
);
6537 unsigned long flags
;
6540 spin_lock_irqsave(&np
->lock
, flags
);
6541 if (!netif_running(np
->dev
)) {
6542 spin_unlock_irqrestore(&np
->lock
, flags
);
6546 spin_unlock_irqrestore(&np
->lock
, flags
);
6548 del_timer_sync(&np
->timer
);
6552 spin_lock_irqsave(&np
->lock
, flags
);
6556 spin_unlock_irqrestore(&np
->lock
, flags
);
6558 niu_reset_buffers(np
);
6560 spin_lock_irqsave(&np
->lock
, flags
);
6562 err
= niu_init_hw(np
);
6564 np
->timer
.expires
= jiffies
+ HZ
;
6565 add_timer(&np
->timer
);
6566 niu_netif_start(np
);
6569 spin_unlock_irqrestore(&np
->lock
, flags
);
6572 static void niu_tx_timeout(struct net_device
*dev
)
6574 struct niu
*np
= netdev_priv(dev
);
6576 dev_err(np
->device
, PFX
"%s: Transmit timed out, resetting\n",
6579 schedule_work(&np
->reset_task
);
6582 static void niu_set_txd(struct tx_ring_info
*rp
, int index
,
6583 u64 mapping
, u64 len
, u64 mark
,
6586 __le64
*desc
= &rp
->descr
[index
];
6588 *desc
= cpu_to_le64(mark
|
6589 (n_frags
<< TX_DESC_NUM_PTR_SHIFT
) |
6590 (len
<< TX_DESC_TR_LEN_SHIFT
) |
6591 (mapping
& TX_DESC_SAD
));
6594 static u64
niu_compute_tx_flags(struct sk_buff
*skb
, struct ethhdr
*ehdr
,
6595 u64 pad_bytes
, u64 len
)
6597 u16 eth_proto
, eth_proto_inner
;
6598 u64 csum_bits
, l3off
, ihl
, ret
;
6602 eth_proto
= be16_to_cpu(ehdr
->h_proto
);
6603 eth_proto_inner
= eth_proto
;
6604 if (eth_proto
== ETH_P_8021Q
) {
6605 struct vlan_ethhdr
*vp
= (struct vlan_ethhdr
*) ehdr
;
6606 __be16 val
= vp
->h_vlan_encapsulated_proto
;
6608 eth_proto_inner
= be16_to_cpu(val
);
6612 switch (skb
->protocol
) {
6613 case cpu_to_be16(ETH_P_IP
):
6614 ip_proto
= ip_hdr(skb
)->protocol
;
6615 ihl
= ip_hdr(skb
)->ihl
;
6617 case cpu_to_be16(ETH_P_IPV6
):
6618 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
6627 csum_bits
= TXHDR_CSUM_NONE
;
6628 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
6631 csum_bits
= (ip_proto
== IPPROTO_TCP
?
6633 (ip_proto
== IPPROTO_UDP
?
6634 TXHDR_CSUM_UDP
: TXHDR_CSUM_SCTP
));
6636 start
= skb_transport_offset(skb
) -
6637 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6638 stuff
= start
+ skb
->csum_offset
;
6640 csum_bits
|= (start
/ 2) << TXHDR_L4START_SHIFT
;
6641 csum_bits
|= (stuff
/ 2) << TXHDR_L4STUFF_SHIFT
;
6644 l3off
= skb_network_offset(skb
) -
6645 (pad_bytes
+ sizeof(struct tx_pkt_hdr
));
6647 ret
= (((pad_bytes
/ 2) << TXHDR_PAD_SHIFT
) |
6648 (len
<< TXHDR_LEN_SHIFT
) |
6649 ((l3off
/ 2) << TXHDR_L3START_SHIFT
) |
6650 (ihl
<< TXHDR_IHL_SHIFT
) |
6651 ((eth_proto_inner
< 1536) ? TXHDR_LLC
: 0) |
6652 ((eth_proto
== ETH_P_8021Q
) ? TXHDR_VLAN
: 0) |
6653 (ipv6
? TXHDR_IP_VER
: 0) |
6659 static int niu_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
6661 struct niu
*np
= netdev_priv(dev
);
6662 unsigned long align
, headroom
;
6663 struct netdev_queue
*txq
;
6664 struct tx_ring_info
*rp
;
6665 struct tx_pkt_hdr
*tp
;
6666 unsigned int len
, nfg
;
6667 struct ethhdr
*ehdr
;
6671 i
= skb_get_queue_mapping(skb
);
6672 rp
= &np
->tx_rings
[i
];
6673 txq
= netdev_get_tx_queue(dev
, i
);
6675 if (niu_tx_avail(rp
) <= (skb_shinfo(skb
)->nr_frags
+ 1)) {
6676 netif_tx_stop_queue(txq
);
6677 dev_err(np
->device
, PFX
"%s: BUG! Tx ring full when "
6678 "queue awake!\n", dev
->name
);
6680 return NETDEV_TX_BUSY
;
6683 if (skb
->len
< ETH_ZLEN
) {
6684 unsigned int pad_bytes
= ETH_ZLEN
- skb
->len
;
6686 if (skb_pad(skb
, pad_bytes
))
6688 skb_put(skb
, pad_bytes
);
6691 len
= sizeof(struct tx_pkt_hdr
) + 15;
6692 if (skb_headroom(skb
) < len
) {
6693 struct sk_buff
*skb_new
;
6695 skb_new
= skb_realloc_headroom(skb
, len
);
6705 align
= ((unsigned long) skb
->data
& (16 - 1));
6706 headroom
= align
+ sizeof(struct tx_pkt_hdr
);
6708 ehdr
= (struct ethhdr
*) skb
->data
;
6709 tp
= (struct tx_pkt_hdr
*) skb_push(skb
, headroom
);
6711 len
= skb
->len
- sizeof(struct tx_pkt_hdr
);
6712 tp
->flags
= cpu_to_le64(niu_compute_tx_flags(skb
, ehdr
, align
, len
));
6715 len
= skb_headlen(skb
);
6716 mapping
= np
->ops
->map_single(np
->device
, skb
->data
,
6717 len
, DMA_TO_DEVICE
);
6721 rp
->tx_buffs
[prod
].skb
= skb
;
6722 rp
->tx_buffs
[prod
].mapping
= mapping
;
6725 if (++rp
->mark_counter
== rp
->mark_freq
) {
6726 rp
->mark_counter
= 0;
6727 mrk
|= TX_DESC_MARK
;
6732 nfg
= skb_shinfo(skb
)->nr_frags
;
6734 tlen
-= MAX_TX_DESC_LEN
;
6739 unsigned int this_len
= len
;
6741 if (this_len
> MAX_TX_DESC_LEN
)
6742 this_len
= MAX_TX_DESC_LEN
;
6744 niu_set_txd(rp
, prod
, mapping
, this_len
, mrk
, nfg
);
6747 prod
= NEXT_TX(rp
, prod
);
6748 mapping
+= this_len
;
6752 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6753 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
6756 mapping
= np
->ops
->map_page(np
->device
, frag
->page
,
6757 frag
->page_offset
, len
,
6760 rp
->tx_buffs
[prod
].skb
= NULL
;
6761 rp
->tx_buffs
[prod
].mapping
= mapping
;
6763 niu_set_txd(rp
, prod
, mapping
, len
, 0, 0);
6765 prod
= NEXT_TX(rp
, prod
);
6768 if (prod
< rp
->prod
)
6769 rp
->wrap_bit
^= TX_RING_KICK_WRAP
;
6772 nw64(TX_RING_KICK(rp
->tx_channel
), rp
->wrap_bit
| (prod
<< 3));
6774 if (unlikely(niu_tx_avail(rp
) <= (MAX_SKB_FRAGS
+ 1))) {
6775 netif_tx_stop_queue(txq
);
6776 if (niu_tx_avail(rp
) > NIU_TX_WAKEUP_THRESH(rp
))
6777 netif_tx_wake_queue(txq
);
6780 dev
->trans_start
= jiffies
;
6783 return NETDEV_TX_OK
;
6791 static int niu_change_mtu(struct net_device
*dev
, int new_mtu
)
6793 struct niu
*np
= netdev_priv(dev
);
6794 int err
, orig_jumbo
, new_jumbo
;
6796 if (new_mtu
< 68 || new_mtu
> NIU_MAX_MTU
)
6799 orig_jumbo
= (dev
->mtu
> ETH_DATA_LEN
);
6800 new_jumbo
= (new_mtu
> ETH_DATA_LEN
);
6804 if (!netif_running(dev
) ||
6805 (orig_jumbo
== new_jumbo
))
6808 niu_full_shutdown(np
, dev
);
6810 niu_free_channels(np
);
6812 niu_enable_napi(np
);
6814 err
= niu_alloc_channels(np
);
6818 spin_lock_irq(&np
->lock
);
6820 err
= niu_init_hw(np
);
6822 init_timer(&np
->timer
);
6823 np
->timer
.expires
= jiffies
+ HZ
;
6824 np
->timer
.data
= (unsigned long) np
;
6825 np
->timer
.function
= niu_timer
;
6827 err
= niu_enable_interrupts(np
, 1);
6832 spin_unlock_irq(&np
->lock
);
6835 netif_tx_start_all_queues(dev
);
6836 if (np
->link_config
.loopback_mode
!= LOOPBACK_DISABLED
)
6837 netif_carrier_on(dev
);
6839 add_timer(&np
->timer
);
6845 static void niu_get_drvinfo(struct net_device
*dev
,
6846 struct ethtool_drvinfo
*info
)
6848 struct niu
*np
= netdev_priv(dev
);
6849 struct niu_vpd
*vpd
= &np
->vpd
;
6851 strcpy(info
->driver
, DRV_MODULE_NAME
);
6852 strcpy(info
->version
, DRV_MODULE_VERSION
);
6853 sprintf(info
->fw_version
, "%d.%d",
6854 vpd
->fcode_major
, vpd
->fcode_minor
);
6855 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
)
6856 strcpy(info
->bus_info
, pci_name(np
->pdev
));
6859 static int niu_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6861 struct niu
*np
= netdev_priv(dev
);
6862 struct niu_link_config
*lp
;
6864 lp
= &np
->link_config
;
6866 memset(cmd
, 0, sizeof(*cmd
));
6867 cmd
->phy_address
= np
->phy_addr
;
6868 cmd
->supported
= lp
->supported
;
6869 cmd
->advertising
= lp
->active_advertising
;
6870 cmd
->autoneg
= lp
->active_autoneg
;
6871 cmd
->speed
= lp
->active_speed
;
6872 cmd
->duplex
= lp
->active_duplex
;
6873 cmd
->port
= (np
->flags
& NIU_FLAGS_FIBER
) ? PORT_FIBRE
: PORT_TP
;
6874 cmd
->transceiver
= (np
->flags
& NIU_FLAGS_XCVR_SERDES
) ?
6875 XCVR_EXTERNAL
: XCVR_INTERNAL
;
6880 static int niu_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
6882 struct niu
*np
= netdev_priv(dev
);
6883 struct niu_link_config
*lp
= &np
->link_config
;
6885 lp
->advertising
= cmd
->advertising
;
6886 lp
->speed
= cmd
->speed
;
6887 lp
->duplex
= cmd
->duplex
;
6888 lp
->autoneg
= cmd
->autoneg
;
6889 return niu_init_link(np
);
6892 static u32
niu_get_msglevel(struct net_device
*dev
)
6894 struct niu
*np
= netdev_priv(dev
);
6895 return np
->msg_enable
;
6898 static void niu_set_msglevel(struct net_device
*dev
, u32 value
)
6900 struct niu
*np
= netdev_priv(dev
);
6901 np
->msg_enable
= value
;
6904 static int niu_nway_reset(struct net_device
*dev
)
6906 struct niu
*np
= netdev_priv(dev
);
6908 if (np
->link_config
.autoneg
)
6909 return niu_init_link(np
);
6914 static int niu_get_eeprom_len(struct net_device
*dev
)
6916 struct niu
*np
= netdev_priv(dev
);
6918 return np
->eeprom_len
;
6921 static int niu_get_eeprom(struct net_device
*dev
,
6922 struct ethtool_eeprom
*eeprom
, u8
*data
)
6924 struct niu
*np
= netdev_priv(dev
);
6925 u32 offset
, len
, val
;
6927 offset
= eeprom
->offset
;
6930 if (offset
+ len
< offset
)
6932 if (offset
>= np
->eeprom_len
)
6934 if (offset
+ len
> np
->eeprom_len
)
6935 len
= eeprom
->len
= np
->eeprom_len
- offset
;
6938 u32 b_offset
, b_count
;
6940 b_offset
= offset
& 3;
6941 b_count
= 4 - b_offset
;
6945 val
= nr64(ESPC_NCR((offset
- b_offset
) / 4));
6946 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
6952 val
= nr64(ESPC_NCR(offset
/ 4));
6953 memcpy(data
, &val
, 4);
6959 val
= nr64(ESPC_NCR(offset
/ 4));
6960 memcpy(data
, &val
, len
);
6965 static void niu_ethflow_to_l3proto(int flow_type
, u8
*pid
)
6967 switch (flow_type
) {
6978 *pid
= IPPROTO_SCTP
;
6994 static int niu_class_to_ethflow(u64
class, int *flow_type
)
6997 case CLASS_CODE_TCP_IPV4
:
6998 *flow_type
= TCP_V4_FLOW
;
7000 case CLASS_CODE_UDP_IPV4
:
7001 *flow_type
= UDP_V4_FLOW
;
7003 case CLASS_CODE_AH_ESP_IPV4
:
7004 *flow_type
= AH_V4_FLOW
;
7006 case CLASS_CODE_SCTP_IPV4
:
7007 *flow_type
= SCTP_V4_FLOW
;
7009 case CLASS_CODE_TCP_IPV6
:
7010 *flow_type
= TCP_V6_FLOW
;
7012 case CLASS_CODE_UDP_IPV6
:
7013 *flow_type
= UDP_V6_FLOW
;
7015 case CLASS_CODE_AH_ESP_IPV6
:
7016 *flow_type
= AH_V6_FLOW
;
7018 case CLASS_CODE_SCTP_IPV6
:
7019 *flow_type
= SCTP_V6_FLOW
;
7021 case CLASS_CODE_USER_PROG1
:
7022 case CLASS_CODE_USER_PROG2
:
7023 case CLASS_CODE_USER_PROG3
:
7024 case CLASS_CODE_USER_PROG4
:
7025 *flow_type
= IP_USER_FLOW
;
7034 static int niu_ethflow_to_class(int flow_type
, u64
*class)
7036 switch (flow_type
) {
7038 *class = CLASS_CODE_TCP_IPV4
;
7041 *class = CLASS_CODE_UDP_IPV4
;
7045 *class = CLASS_CODE_AH_ESP_IPV4
;
7048 *class = CLASS_CODE_SCTP_IPV4
;
7051 *class = CLASS_CODE_TCP_IPV6
;
7054 *class = CLASS_CODE_UDP_IPV6
;
7058 *class = CLASS_CODE_AH_ESP_IPV6
;
7061 *class = CLASS_CODE_SCTP_IPV6
;
7070 static u64
niu_flowkey_to_ethflow(u64 flow_key
)
7074 if (flow_key
& FLOW_KEY_L2DA
)
7075 ethflow
|= RXH_L2DA
;
7076 if (flow_key
& FLOW_KEY_VLAN
)
7077 ethflow
|= RXH_VLAN
;
7078 if (flow_key
& FLOW_KEY_IPSA
)
7079 ethflow
|= RXH_IP_SRC
;
7080 if (flow_key
& FLOW_KEY_IPDA
)
7081 ethflow
|= RXH_IP_DST
;
7082 if (flow_key
& FLOW_KEY_PROTO
)
7083 ethflow
|= RXH_L3_PROTO
;
7084 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
))
7085 ethflow
|= RXH_L4_B_0_1
;
7086 if (flow_key
& (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
))
7087 ethflow
|= RXH_L4_B_2_3
;
7093 static int niu_ethflow_to_flowkey(u64 ethflow
, u64
*flow_key
)
7097 if (ethflow
& RXH_L2DA
)
7098 key
|= FLOW_KEY_L2DA
;
7099 if (ethflow
& RXH_VLAN
)
7100 key
|= FLOW_KEY_VLAN
;
7101 if (ethflow
& RXH_IP_SRC
)
7102 key
|= FLOW_KEY_IPSA
;
7103 if (ethflow
& RXH_IP_DST
)
7104 key
|= FLOW_KEY_IPDA
;
7105 if (ethflow
& RXH_L3_PROTO
)
7106 key
|= FLOW_KEY_PROTO
;
7107 if (ethflow
& RXH_L4_B_0_1
)
7108 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_0_SHIFT
);
7109 if (ethflow
& RXH_L4_B_2_3
)
7110 key
|= (FLOW_KEY_L4_BYTE12
<< FLOW_KEY_L4_1_SHIFT
);
7118 static int niu_get_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7124 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7127 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7129 nfc
->data
= RXH_DISCARD
;
7131 nfc
->data
= niu_flowkey_to_ethflow(np
->parent
->flow_key
[class -
7132 CLASS_CODE_USER_PROG1
]);
7136 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry
*tp
,
7137 struct ethtool_rx_flow_spec
*fsp
)
7140 fsp
->h_u
.tcp_ip4_spec
.ip4src
= (tp
->key
[3] & TCAM_V4KEY3_SADDR
) >>
7141 TCAM_V4KEY3_SADDR_SHIFT
;
7142 fsp
->h_u
.tcp_ip4_spec
.ip4dst
= (tp
->key
[3] & TCAM_V4KEY3_DADDR
) >>
7143 TCAM_V4KEY3_DADDR_SHIFT
;
7144 fsp
->m_u
.tcp_ip4_spec
.ip4src
= (tp
->key_mask
[3] & TCAM_V4KEY3_SADDR
) >>
7145 TCAM_V4KEY3_SADDR_SHIFT
;
7146 fsp
->m_u
.tcp_ip4_spec
.ip4dst
= (tp
->key_mask
[3] & TCAM_V4KEY3_DADDR
) >>
7147 TCAM_V4KEY3_DADDR_SHIFT
;
7149 fsp
->h_u
.tcp_ip4_spec
.ip4src
=
7150 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7151 fsp
->m_u
.tcp_ip4_spec
.ip4src
=
7152 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7153 fsp
->h_u
.tcp_ip4_spec
.ip4dst
=
7154 cpu_to_be32(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7155 fsp
->m_u
.tcp_ip4_spec
.ip4dst
=
7156 cpu_to_be32(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7158 fsp
->h_u
.tcp_ip4_spec
.tos
= (tp
->key
[2] & TCAM_V4KEY2_TOS
) >>
7159 TCAM_V4KEY2_TOS_SHIFT
;
7160 fsp
->m_u
.tcp_ip4_spec
.tos
= (tp
->key_mask
[2] & TCAM_V4KEY2_TOS
) >>
7161 TCAM_V4KEY2_TOS_SHIFT
;
7163 switch (fsp
->flow_type
) {
7167 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7168 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7169 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7170 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7171 ((tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7172 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7173 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7174 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7175 TCAM_V4KEY2_PORT_SPI_SHIFT
) >> 16;
7176 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7177 ((tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7178 TCAM_V4KEY2_PORT_SPI_SHIFT
) & 0xffff;
7180 fsp
->h_u
.tcp_ip4_spec
.psrc
=
7181 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7182 fsp
->h_u
.tcp_ip4_spec
.pdst
=
7183 cpu_to_be16(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7184 fsp
->m_u
.tcp_ip4_spec
.psrc
=
7185 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7186 fsp
->m_u
.tcp_ip4_spec
.pdst
=
7187 cpu_to_be16(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7191 fsp
->h_u
.ah_ip4_spec
.spi
=
7192 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7193 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7194 fsp
->m_u
.ah_ip4_spec
.spi
=
7195 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7196 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7198 fsp
->h_u
.ah_ip4_spec
.spi
=
7199 cpu_to_be32(fsp
->h_u
.ah_ip4_spec
.spi
);
7200 fsp
->m_u
.ah_ip4_spec
.spi
=
7201 cpu_to_be32(fsp
->m_u
.ah_ip4_spec
.spi
);
7204 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7205 (tp
->key
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7206 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7207 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7208 (tp
->key_mask
[2] & TCAM_V4KEY2_PORT_SPI
) >>
7209 TCAM_V4KEY2_PORT_SPI_SHIFT
;
7211 fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
=
7212 cpu_to_be32(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7213 fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
=
7214 cpu_to_be32(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7216 fsp
->h_u
.usr_ip4_spec
.proto
=
7217 (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7218 TCAM_V4KEY2_PROTO_SHIFT
;
7219 fsp
->m_u
.usr_ip4_spec
.proto
=
7220 (tp
->key_mask
[2] & TCAM_V4KEY2_PROTO
) >>
7221 TCAM_V4KEY2_PROTO_SHIFT
;
7223 fsp
->h_u
.usr_ip4_spec
.ip_ver
= ETH_RX_NFC_IP4
;
7230 static int niu_get_ethtool_tcam_entry(struct niu
*np
,
7231 struct ethtool_rxnfc
*nfc
)
7233 struct niu_parent
*parent
= np
->parent
;
7234 struct niu_tcam_entry
*tp
;
7235 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7240 idx
= tcam_get_index(np
, (u16
)nfc
->fs
.location
);
7242 tp
= &parent
->tcam
[idx
];
7244 pr_info(PFX
"niu%d: %s entry [%d] invalid for idx[%d]\n",
7245 parent
->index
, np
->dev
->name
, (u16
)nfc
->fs
.location
, idx
);
7249 /* fill the flow spec entry */
7250 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7251 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7252 ret
= niu_class_to_ethflow(class, &fsp
->flow_type
);
7255 pr_info(PFX
"niu%d: %s niu_class_to_ethflow failed\n",
7256 parent
->index
, np
->dev
->name
);
7261 if (fsp
->flow_type
== AH_V4_FLOW
|| fsp
->flow_type
== AH_V6_FLOW
) {
7262 u32 proto
= (tp
->key
[2] & TCAM_V4KEY2_PROTO
) >>
7263 TCAM_V4KEY2_PROTO_SHIFT
;
7264 if (proto
== IPPROTO_ESP
) {
7265 if (fsp
->flow_type
== AH_V4_FLOW
)
7266 fsp
->flow_type
= ESP_V4_FLOW
;
7268 fsp
->flow_type
= ESP_V6_FLOW
;
7272 switch (fsp
->flow_type
) {
7278 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7285 /* Not yet implemented */
7289 niu_get_ip4fs_from_tcam_key(tp
, fsp
);
7299 if (tp
->assoc_data
& TCAM_ASSOCDATA_DISC
)
7300 fsp
->ring_cookie
= RX_CLS_FLOW_DISC
;
7302 fsp
->ring_cookie
= (tp
->assoc_data
& TCAM_ASSOCDATA_OFFSET
) >>
7303 TCAM_ASSOCDATA_OFFSET_SHIFT
;
7305 /* put the tcam size here */
7306 nfc
->data
= tcam_get_size(np
);
7311 static int niu_get_ethtool_tcam_all(struct niu
*np
,
7312 struct ethtool_rxnfc
*nfc
,
7315 struct niu_parent
*parent
= np
->parent
;
7316 struct niu_tcam_entry
*tp
;
7319 unsigned long flags
;
7322 /* put the tcam size here */
7323 nfc
->data
= tcam_get_size(np
);
7325 niu_lock_parent(np
, flags
);
7326 n_entries
= nfc
->rule_cnt
;
7327 for (cnt
= 0, i
= 0; i
< nfc
->data
; i
++) {
7328 idx
= tcam_get_index(np
, i
);
7329 tp
= &parent
->tcam
[idx
];
7335 niu_unlock_parent(np
, flags
);
7337 if (n_entries
!= cnt
) {
7338 /* print warning, this should not happen */
7339 pr_info(PFX
"niu%d: %s In niu_get_ethtool_tcam_all, "
7340 "n_entries[%d] != cnt[%d]!!!\n\n",
7341 np
->parent
->index
, np
->dev
->name
, n_entries
, cnt
);
7347 static int niu_get_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
,
7350 struct niu
*np
= netdev_priv(dev
);
7355 ret
= niu_get_hash_opts(np
, cmd
);
7357 case ETHTOOL_GRXRINGS
:
7358 cmd
->data
= np
->num_rx_rings
;
7360 case ETHTOOL_GRXCLSRLCNT
:
7361 cmd
->rule_cnt
= tcam_get_valid_entry_cnt(np
);
7363 case ETHTOOL_GRXCLSRULE
:
7364 ret
= niu_get_ethtool_tcam_entry(np
, cmd
);
7366 case ETHTOOL_GRXCLSRLALL
:
7367 ret
= niu_get_ethtool_tcam_all(np
, cmd
, (u32
*)rule_locs
);
7377 static int niu_set_hash_opts(struct niu
*np
, struct ethtool_rxnfc
*nfc
)
7381 unsigned long flags
;
7383 if (!niu_ethflow_to_class(nfc
->flow_type
, &class))
7386 if (class < CLASS_CODE_USER_PROG1
||
7387 class > CLASS_CODE_SCTP_IPV6
)
7390 if (nfc
->data
& RXH_DISCARD
) {
7391 niu_lock_parent(np
, flags
);
7392 flow_key
= np
->parent
->tcam_key
[class -
7393 CLASS_CODE_USER_PROG1
];
7394 flow_key
|= TCAM_KEY_DISC
;
7395 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7396 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7397 niu_unlock_parent(np
, flags
);
7400 /* Discard was set before, but is not set now */
7401 if (np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] &
7403 niu_lock_parent(np
, flags
);
7404 flow_key
= np
->parent
->tcam_key
[class -
7405 CLASS_CODE_USER_PROG1
];
7406 flow_key
&= ~TCAM_KEY_DISC
;
7407 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1
),
7409 np
->parent
->tcam_key
[class - CLASS_CODE_USER_PROG1
] =
7411 niu_unlock_parent(np
, flags
);
7415 if (!niu_ethflow_to_flowkey(nfc
->data
, &flow_key
))
7418 niu_lock_parent(np
, flags
);
7419 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1
), flow_key
);
7420 np
->parent
->flow_key
[class - CLASS_CODE_USER_PROG1
] = flow_key
;
7421 niu_unlock_parent(np
, flags
);
7426 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec
*fsp
,
7427 struct niu_tcam_entry
*tp
,
7428 int l2_rdc_tab
, u64
class)
7431 u32 sip
, dip
, sipm
, dipm
, spi
, spim
;
7432 u16 sport
, dport
, spm
, dpm
;
7434 sip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4src
);
7435 sipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4src
);
7436 dip
= be32_to_cpu(fsp
->h_u
.tcp_ip4_spec
.ip4dst
);
7437 dipm
= be32_to_cpu(fsp
->m_u
.tcp_ip4_spec
.ip4dst
);
7439 tp
->key
[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7440 tp
->key_mask
[0] = TCAM_V4KEY0_CLASS_CODE
;
7441 tp
->key
[1] = (u64
)l2_rdc_tab
<< TCAM_V4KEY1_L2RDCNUM_SHIFT
;
7442 tp
->key_mask
[1] = TCAM_V4KEY1_L2RDCNUM
;
7444 tp
->key
[3] = (u64
)sip
<< TCAM_V4KEY3_SADDR_SHIFT
;
7447 tp
->key_mask
[3] = (u64
)sipm
<< TCAM_V4KEY3_SADDR_SHIFT
;
7448 tp
->key_mask
[3] |= dipm
;
7450 tp
->key
[2] |= ((u64
)fsp
->h_u
.tcp_ip4_spec
.tos
<<
7451 TCAM_V4KEY2_TOS_SHIFT
);
7452 tp
->key_mask
[2] |= ((u64
)fsp
->m_u
.tcp_ip4_spec
.tos
<<
7453 TCAM_V4KEY2_TOS_SHIFT
);
7454 switch (fsp
->flow_type
) {
7458 sport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.psrc
);
7459 spm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.psrc
);
7460 dport
= be16_to_cpu(fsp
->h_u
.tcp_ip4_spec
.pdst
);
7461 dpm
= be16_to_cpu(fsp
->m_u
.tcp_ip4_spec
.pdst
);
7463 tp
->key
[2] |= (((u64
)sport
<< 16) | dport
);
7464 tp
->key_mask
[2] |= (((u64
)spm
<< 16) | dpm
);
7465 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7469 spi
= be32_to_cpu(fsp
->h_u
.ah_ip4_spec
.spi
);
7470 spim
= be32_to_cpu(fsp
->m_u
.ah_ip4_spec
.spi
);
7473 tp
->key_mask
[2] |= spim
;
7474 niu_ethflow_to_l3proto(fsp
->flow_type
, &pid
);
7477 spi
= be32_to_cpu(fsp
->h_u
.usr_ip4_spec
.l4_4_bytes
);
7478 spim
= be32_to_cpu(fsp
->m_u
.usr_ip4_spec
.l4_4_bytes
);
7481 tp
->key_mask
[2] |= spim
;
7482 pid
= fsp
->h_u
.usr_ip4_spec
.proto
;
7488 tp
->key
[2] |= ((u64
)pid
<< TCAM_V4KEY2_PROTO_SHIFT
);
7490 tp
->key_mask
[2] |= TCAM_V4KEY2_PROTO
;
7494 static int niu_add_ethtool_tcam_entry(struct niu
*np
,
7495 struct ethtool_rxnfc
*nfc
)
7497 struct niu_parent
*parent
= np
->parent
;
7498 struct niu_tcam_entry
*tp
;
7499 struct ethtool_rx_flow_spec
*fsp
= &nfc
->fs
;
7500 struct niu_rdc_tables
*rdc_table
= &parent
->rdc_group_cfg
[np
->port
];
7501 int l2_rdc_table
= rdc_table
->first_table_num
;
7504 unsigned long flags
;
7509 idx
= nfc
->fs
.location
;
7510 if (idx
>= tcam_get_size(np
))
7513 if (fsp
->flow_type
== IP_USER_FLOW
) {
7515 int add_usr_cls
= 0;
7517 struct ethtool_usrip4_spec
*uspec
= &fsp
->h_u
.usr_ip4_spec
;
7518 struct ethtool_usrip4_spec
*umask
= &fsp
->m_u
.usr_ip4_spec
;
7520 niu_lock_parent(np
, flags
);
7522 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7523 if (parent
->l3_cls
[i
]) {
7524 if (uspec
->proto
== parent
->l3_cls_pid
[i
]) {
7525 class = parent
->l3_cls
[i
];
7526 parent
->l3_cls_refcnt
[i
]++;
7531 /* Program new user IP class */
7534 class = CLASS_CODE_USER_PROG1
;
7537 class = CLASS_CODE_USER_PROG2
;
7540 class = CLASS_CODE_USER_PROG3
;
7543 class = CLASS_CODE_USER_PROG4
;
7548 if (uspec
->ip_ver
== ETH_RX_NFC_IP6
)
7550 ret
= tcam_user_ip_class_set(np
, class, ipv6
,
7557 ret
= tcam_user_ip_class_enable(np
, class, 1);
7560 parent
->l3_cls
[i
] = class;
7561 parent
->l3_cls_pid
[i
] = uspec
->proto
;
7562 parent
->l3_cls_refcnt
[i
]++;
7568 pr_info(PFX
"niu%d: %s niu_add_ethtool_tcam_entry: "
7569 "Could not find/insert class for pid %d\n",
7570 parent
->index
, np
->dev
->name
, uspec
->proto
);
7574 niu_unlock_parent(np
, flags
);
7576 if (!niu_ethflow_to_class(fsp
->flow_type
, &class)) {
7581 niu_lock_parent(np
, flags
);
7583 idx
= tcam_get_index(np
, idx
);
7584 tp
= &parent
->tcam
[idx
];
7586 memset(tp
, 0, sizeof(*tp
));
7588 /* fill in the tcam key and mask */
7589 switch (fsp
->flow_type
) {
7595 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
, class);
7602 /* Not yet implemented */
7603 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7604 "flow %d for IPv6 not implemented\n\n",
7605 parent
->index
, np
->dev
->name
, fsp
->flow_type
);
7609 if (fsp
->h_u
.usr_ip4_spec
.ip_ver
== ETH_RX_NFC_IP4
) {
7610 niu_get_tcamkey_from_ip4fs(fsp
, tp
, l2_rdc_table
,
7613 /* Not yet implemented */
7614 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7615 "usr flow for IPv6 not implemented\n\n",
7616 parent
->index
, np
->dev
->name
);
7622 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7623 "Unknown flow type %d\n\n",
7624 parent
->index
, np
->dev
->name
, fsp
->flow_type
);
7629 /* fill in the assoc data */
7630 if (fsp
->ring_cookie
== RX_CLS_FLOW_DISC
) {
7631 tp
->assoc_data
= TCAM_ASSOCDATA_DISC
;
7633 if (fsp
->ring_cookie
>= np
->num_rx_rings
) {
7634 pr_info(PFX
"niu%d: %s In niu_add_ethtool_tcam_entry: "
7635 "Invalid RX ring %lld\n\n",
7636 parent
->index
, np
->dev
->name
,
7637 (long long) fsp
->ring_cookie
);
7641 tp
->assoc_data
= (TCAM_ASSOCDATA_TRES_USE_OFFSET
|
7642 (fsp
->ring_cookie
<<
7643 TCAM_ASSOCDATA_OFFSET_SHIFT
));
7646 err
= tcam_write(np
, idx
, tp
->key
, tp
->key_mask
);
7651 err
= tcam_assoc_write(np
, idx
, tp
->assoc_data
);
7657 /* validate the entry */
7659 np
->clas
.tcam_valid_entries
++;
7661 niu_unlock_parent(np
, flags
);
7666 static int niu_del_ethtool_tcam_entry(struct niu
*np
, u32 loc
)
7668 struct niu_parent
*parent
= np
->parent
;
7669 struct niu_tcam_entry
*tp
;
7671 unsigned long flags
;
7675 if (loc
>= tcam_get_size(np
))
7678 niu_lock_parent(np
, flags
);
7680 idx
= tcam_get_index(np
, loc
);
7681 tp
= &parent
->tcam
[idx
];
7683 /* if the entry is of a user defined class, then update*/
7684 class = (tp
->key
[0] & TCAM_V4KEY0_CLASS_CODE
) >>
7685 TCAM_V4KEY0_CLASS_CODE_SHIFT
;
7687 if (class >= CLASS_CODE_USER_PROG1
&& class <= CLASS_CODE_USER_PROG4
) {
7689 for (i
= 0; i
< NIU_L3_PROG_CLS
; i
++) {
7690 if (parent
->l3_cls
[i
] == class) {
7691 parent
->l3_cls_refcnt
[i
]--;
7692 if (!parent
->l3_cls_refcnt
[i
]) {
7694 ret
= tcam_user_ip_class_enable(np
,
7699 parent
->l3_cls
[i
] = 0;
7700 parent
->l3_cls_pid
[i
] = 0;
7705 if (i
== NIU_L3_PROG_CLS
) {
7706 pr_info(PFX
"niu%d: %s In niu_del_ethtool_tcam_entry,"
7707 "Usr class 0x%llx not found \n",
7708 parent
->index
, np
->dev
->name
,
7709 (unsigned long long) class);
7715 ret
= tcam_flush(np
, idx
);
7719 /* invalidate the entry */
7721 np
->clas
.tcam_valid_entries
--;
7723 niu_unlock_parent(np
, flags
);
7728 static int niu_set_nfc(struct net_device
*dev
, struct ethtool_rxnfc
*cmd
)
7730 struct niu
*np
= netdev_priv(dev
);
7735 ret
= niu_set_hash_opts(np
, cmd
);
7737 case ETHTOOL_SRXCLSRLINS
:
7738 ret
= niu_add_ethtool_tcam_entry(np
, cmd
);
7740 case ETHTOOL_SRXCLSRLDEL
:
7741 ret
= niu_del_ethtool_tcam_entry(np
, cmd
->fs
.location
);
7751 static const struct {
7752 const char string
[ETH_GSTRING_LEN
];
7753 } niu_xmac_stat_keys
[] = {
7756 { "tx_fifo_errors" },
7757 { "tx_overflow_errors" },
7758 { "tx_max_pkt_size_errors" },
7759 { "tx_underflow_errors" },
7760 { "rx_local_faults" },
7761 { "rx_remote_faults" },
7762 { "rx_link_faults" },
7763 { "rx_align_errors" },
7775 { "rx_code_violations" },
7776 { "rx_len_errors" },
7777 { "rx_crc_errors" },
7778 { "rx_underflows" },
7780 { "pause_off_state" },
7781 { "pause_on_state" },
7782 { "pause_received" },
7785 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys)
7787 static const struct {
7788 const char string
[ETH_GSTRING_LEN
];
7789 } niu_bmac_stat_keys
[] = {
7790 { "tx_underflow_errors" },
7791 { "tx_max_pkt_size_errors" },
7796 { "rx_align_errors" },
7797 { "rx_crc_errors" },
7798 { "rx_len_errors" },
7799 { "pause_off_state" },
7800 { "pause_on_state" },
7801 { "pause_received" },
7804 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys)
7806 static const struct {
7807 const char string
[ETH_GSTRING_LEN
];
7808 } niu_rxchan_stat_keys
[] = {
7816 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys)
7818 static const struct {
7819 const char string
[ETH_GSTRING_LEN
];
7820 } niu_txchan_stat_keys
[] = {
7827 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys)
7829 static void niu_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
7831 struct niu
*np
= netdev_priv(dev
);
7834 if (stringset
!= ETH_SS_STATS
)
7837 if (np
->flags
& NIU_FLAGS_XMAC
) {
7838 memcpy(data
, niu_xmac_stat_keys
,
7839 sizeof(niu_xmac_stat_keys
));
7840 data
+= sizeof(niu_xmac_stat_keys
);
7842 memcpy(data
, niu_bmac_stat_keys
,
7843 sizeof(niu_bmac_stat_keys
));
7844 data
+= sizeof(niu_bmac_stat_keys
);
7846 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7847 memcpy(data
, niu_rxchan_stat_keys
,
7848 sizeof(niu_rxchan_stat_keys
));
7849 data
+= sizeof(niu_rxchan_stat_keys
);
7851 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7852 memcpy(data
, niu_txchan_stat_keys
,
7853 sizeof(niu_txchan_stat_keys
));
7854 data
+= sizeof(niu_txchan_stat_keys
);
7858 static int niu_get_stats_count(struct net_device
*dev
)
7860 struct niu
*np
= netdev_priv(dev
);
7862 return ((np
->flags
& NIU_FLAGS_XMAC
?
7863 NUM_XMAC_STAT_KEYS
:
7864 NUM_BMAC_STAT_KEYS
) +
7865 (np
->num_rx_rings
* NUM_RXCHAN_STAT_KEYS
) +
7866 (np
->num_tx_rings
* NUM_TXCHAN_STAT_KEYS
));
7869 static void niu_get_ethtool_stats(struct net_device
*dev
,
7870 struct ethtool_stats
*stats
, u64
*data
)
7872 struct niu
*np
= netdev_priv(dev
);
7875 niu_sync_mac_stats(np
);
7876 if (np
->flags
& NIU_FLAGS_XMAC
) {
7877 memcpy(data
, &np
->mac_stats
.xmac
,
7878 sizeof(struct niu_xmac_stats
));
7879 data
+= (sizeof(struct niu_xmac_stats
) / sizeof(u64
));
7881 memcpy(data
, &np
->mac_stats
.bmac
,
7882 sizeof(struct niu_bmac_stats
));
7883 data
+= (sizeof(struct niu_bmac_stats
) / sizeof(u64
));
7885 for (i
= 0; i
< np
->num_rx_rings
; i
++) {
7886 struct rx_ring_info
*rp
= &np
->rx_rings
[i
];
7888 niu_sync_rx_discard_stats(np
, rp
, 0);
7890 data
[0] = rp
->rx_channel
;
7891 data
[1] = rp
->rx_packets
;
7892 data
[2] = rp
->rx_bytes
;
7893 data
[3] = rp
->rx_dropped
;
7894 data
[4] = rp
->rx_errors
;
7897 for (i
= 0; i
< np
->num_tx_rings
; i
++) {
7898 struct tx_ring_info
*rp
= &np
->tx_rings
[i
];
7900 data
[0] = rp
->tx_channel
;
7901 data
[1] = rp
->tx_packets
;
7902 data
[2] = rp
->tx_bytes
;
7903 data
[3] = rp
->tx_errors
;
7908 static u64
niu_led_state_save(struct niu
*np
)
7910 if (np
->flags
& NIU_FLAGS_XMAC
)
7911 return nr64_mac(XMAC_CONFIG
);
7913 return nr64_mac(BMAC_XIF_CONFIG
);
7916 static void niu_led_state_restore(struct niu
*np
, u64 val
)
7918 if (np
->flags
& NIU_FLAGS_XMAC
)
7919 nw64_mac(XMAC_CONFIG
, val
);
7921 nw64_mac(BMAC_XIF_CONFIG
, val
);
7924 static void niu_force_led(struct niu
*np
, int on
)
7928 if (np
->flags
& NIU_FLAGS_XMAC
) {
7930 bit
= XMAC_CONFIG_FORCE_LED_ON
;
7932 reg
= BMAC_XIF_CONFIG
;
7933 bit
= BMAC_XIF_CONFIG_LINK_LED
;
7936 val
= nr64_mac(reg
);
7944 static int niu_phys_id(struct net_device
*dev
, u32 data
)
7946 struct niu
*np
= netdev_priv(dev
);
7950 if (!netif_running(dev
))
7956 orig_led_state
= niu_led_state_save(np
);
7957 for (i
= 0; i
< (data
* 2); i
++) {
7958 int on
= ((i
% 2) == 0);
7960 niu_force_led(np
, on
);
7962 if (msleep_interruptible(500))
7965 niu_led_state_restore(np
, orig_led_state
);
7970 static const struct ethtool_ops niu_ethtool_ops
= {
7971 .get_drvinfo
= niu_get_drvinfo
,
7972 .get_link
= ethtool_op_get_link
,
7973 .get_msglevel
= niu_get_msglevel
,
7974 .set_msglevel
= niu_set_msglevel
,
7975 .nway_reset
= niu_nway_reset
,
7976 .get_eeprom_len
= niu_get_eeprom_len
,
7977 .get_eeprom
= niu_get_eeprom
,
7978 .get_settings
= niu_get_settings
,
7979 .set_settings
= niu_set_settings
,
7980 .get_strings
= niu_get_strings
,
7981 .get_stats_count
= niu_get_stats_count
,
7982 .get_ethtool_stats
= niu_get_ethtool_stats
,
7983 .phys_id
= niu_phys_id
,
7984 .get_rxnfc
= niu_get_nfc
,
7985 .set_rxnfc
= niu_set_nfc
,
7988 static int niu_ldg_assign_ldn(struct niu
*np
, struct niu_parent
*parent
,
7991 if (ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
)
7993 if (ldn
< 0 || ldn
> LDN_MAX
)
7996 parent
->ldg_map
[ldn
] = ldg
;
7998 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
) {
7999 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by
8000 * the firmware, and we're not supposed to change them.
8001 * Validate the mapping, because if it's wrong we probably
8002 * won't get any interrupts and that's painful to debug.
8004 if (nr64(LDG_NUM(ldn
)) != ldg
) {
8005 dev_err(np
->device
, PFX
"Port %u, mis-matched "
8007 "for ldn %d, should be %d is %llu\n",
8009 (unsigned long long) nr64(LDG_NUM(ldn
)));
8013 nw64(LDG_NUM(ldn
), ldg
);
8018 static int niu_set_ldg_timer_res(struct niu
*np
, int res
)
8020 if (res
< 0 || res
> LDG_TIMER_RES_VAL
)
8024 nw64(LDG_TIMER_RES
, res
);
8029 static int niu_set_ldg_sid(struct niu
*np
, int ldg
, int func
, int vector
)
8031 if ((ldg
< NIU_LDG_MIN
|| ldg
> NIU_LDG_MAX
) ||
8032 (func
< 0 || func
> 3) ||
8033 (vector
< 0 || vector
> 0x1f))
8036 nw64(SID(ldg
), (func
<< SID_FUNC_SHIFT
) | vector
);
8041 static int __devinit
niu_pci_eeprom_read(struct niu
*np
, u32 addr
)
8043 u64 frame
, frame_base
= (ESPC_PIO_STAT_READ_START
|
8044 (addr
<< ESPC_PIO_STAT_ADDR_SHIFT
));
8047 if (addr
> (ESPC_PIO_STAT_ADDR
>> ESPC_PIO_STAT_ADDR_SHIFT
))
8051 nw64(ESPC_PIO_STAT
, frame
);
8055 frame
= nr64(ESPC_PIO_STAT
);
8056 if (frame
& ESPC_PIO_STAT_READ_END
)
8059 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8060 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
8061 (unsigned long long) frame
);
8066 nw64(ESPC_PIO_STAT
, frame
);
8070 frame
= nr64(ESPC_PIO_STAT
);
8071 if (frame
& ESPC_PIO_STAT_READ_END
)
8074 if (!(frame
& ESPC_PIO_STAT_READ_END
)) {
8075 dev_err(np
->device
, PFX
"EEPROM read timeout frame[%llx]\n",
8076 (unsigned long long) frame
);
8080 frame
= nr64(ESPC_PIO_STAT
);
8081 return (frame
& ESPC_PIO_STAT_DATA
) >> ESPC_PIO_STAT_DATA_SHIFT
;
8084 static int __devinit
niu_pci_eeprom_read16(struct niu
*np
, u32 off
)
8086 int err
= niu_pci_eeprom_read(np
, off
);
8092 err
= niu_pci_eeprom_read(np
, off
+ 1);
8095 val
|= (err
& 0xff);
8100 static int __devinit
niu_pci_eeprom_read16_swp(struct niu
*np
, u32 off
)
8102 int err
= niu_pci_eeprom_read(np
, off
);
8109 err
= niu_pci_eeprom_read(np
, off
+ 1);
8113 val
|= (err
& 0xff) << 8;
8118 static int __devinit
niu_pci_vpd_get_propname(struct niu
*np
,
8125 for (i
= 0; i
< namebuf_len
; i
++) {
8126 int err
= niu_pci_eeprom_read(np
, off
+ i
);
8133 if (i
>= namebuf_len
)
8139 static void __devinit
niu_vpd_parse_version(struct niu
*np
)
8141 struct niu_vpd
*vpd
= &np
->vpd
;
8142 int len
= strlen(vpd
->version
) + 1;
8143 const char *s
= vpd
->version
;
8146 for (i
= 0; i
< len
- 5; i
++) {
8147 if (!strncmp(s
+ i
, "FCode ", 5))
8154 sscanf(s
, "%d.%d", &vpd
->fcode_major
, &vpd
->fcode_minor
);
8156 niudbg(PROBE
, "VPD_SCAN: FCODE major(%d) minor(%d)\n",
8157 vpd
->fcode_major
, vpd
->fcode_minor
);
8158 if (vpd
->fcode_major
> NIU_VPD_MIN_MAJOR
||
8159 (vpd
->fcode_major
== NIU_VPD_MIN_MAJOR
&&
8160 vpd
->fcode_minor
>= NIU_VPD_MIN_MINOR
))
8161 np
->flags
|= NIU_FLAGS_VPD_VALID
;
8164 /* ESPC_PIO_EN_ENABLE must be set */
8165 static int __devinit
niu_pci_vpd_scan_props(struct niu
*np
,
8168 unsigned int found_mask
= 0;
8169 #define FOUND_MASK_MODEL 0x00000001
8170 #define FOUND_MASK_BMODEL 0x00000002
8171 #define FOUND_MASK_VERS 0x00000004
8172 #define FOUND_MASK_MAC 0x00000008
8173 #define FOUND_MASK_NMAC 0x00000010
8174 #define FOUND_MASK_PHY 0x00000020
8175 #define FOUND_MASK_ALL 0x0000003f
8177 niudbg(PROBE
, "VPD_SCAN: start[%x] end[%x]\n",
8179 while (start
< end
) {
8180 int len
, err
, instance
, type
, prop_len
;
8185 if (found_mask
== FOUND_MASK_ALL
) {
8186 niu_vpd_parse_version(np
);
8190 err
= niu_pci_eeprom_read(np
, start
+ 2);
8196 instance
= niu_pci_eeprom_read(np
, start
);
8197 type
= niu_pci_eeprom_read(np
, start
+ 3);
8198 prop_len
= niu_pci_eeprom_read(np
, start
+ 4);
8199 err
= niu_pci_vpd_get_propname(np
, start
+ 5, namebuf
, 64);
8205 if (!strcmp(namebuf
, "model")) {
8206 prop_buf
= np
->vpd
.model
;
8207 max_len
= NIU_VPD_MODEL_MAX
;
8208 found_mask
|= FOUND_MASK_MODEL
;
8209 } else if (!strcmp(namebuf
, "board-model")) {
8210 prop_buf
= np
->vpd
.board_model
;
8211 max_len
= NIU_VPD_BD_MODEL_MAX
;
8212 found_mask
|= FOUND_MASK_BMODEL
;
8213 } else if (!strcmp(namebuf
, "version")) {
8214 prop_buf
= np
->vpd
.version
;
8215 max_len
= NIU_VPD_VERSION_MAX
;
8216 found_mask
|= FOUND_MASK_VERS
;
8217 } else if (!strcmp(namebuf
, "local-mac-address")) {
8218 prop_buf
= np
->vpd
.local_mac
;
8220 found_mask
|= FOUND_MASK_MAC
;
8221 } else if (!strcmp(namebuf
, "num-mac-addresses")) {
8222 prop_buf
= &np
->vpd
.mac_num
;
8224 found_mask
|= FOUND_MASK_NMAC
;
8225 } else if (!strcmp(namebuf
, "phy-type")) {
8226 prop_buf
= np
->vpd
.phy_type
;
8227 max_len
= NIU_VPD_PHY_TYPE_MAX
;
8228 found_mask
|= FOUND_MASK_PHY
;
8231 if (max_len
&& prop_len
> max_len
) {
8232 dev_err(np
->device
, PFX
"Property '%s' length (%d) is "
8233 "too long.\n", namebuf
, prop_len
);
8238 u32 off
= start
+ 5 + err
;
8241 niudbg(PROBE
, "VPD_SCAN: Reading in property [%s] "
8242 "len[%d]\n", namebuf
, prop_len
);
8243 for (i
= 0; i
< prop_len
; i
++)
8244 *prop_buf
++ = niu_pci_eeprom_read(np
, off
+ i
);
8253 /* ESPC_PIO_EN_ENABLE must be set */
8254 static void __devinit
niu_pci_vpd_fetch(struct niu
*np
, u32 start
)
8259 err
= niu_pci_eeprom_read16_swp(np
, start
+ 1);
8265 while (start
+ offset
< ESPC_EEPROM_SIZE
) {
8266 u32 here
= start
+ offset
;
8269 err
= niu_pci_eeprom_read(np
, here
);
8273 err
= niu_pci_eeprom_read16_swp(np
, here
+ 1);
8277 here
= start
+ offset
+ 3;
8278 end
= start
+ offset
+ err
;
8282 err
= niu_pci_vpd_scan_props(np
, here
, end
);
8283 if (err
< 0 || err
== 1)
8288 /* ESPC_PIO_EN_ENABLE must be set */
8289 static u32 __devinit
niu_pci_vpd_offset(struct niu
*np
)
8291 u32 start
= 0, end
= ESPC_EEPROM_SIZE
, ret
;
8294 while (start
< end
) {
8297 /* ROM header signature? */
8298 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8302 /* Apply offset to PCI data structure. */
8303 err
= niu_pci_eeprom_read16(np
, start
+ 23);
8308 /* Check for "PCIR" signature. */
8309 err
= niu_pci_eeprom_read16(np
, start
+ 0);
8312 err
= niu_pci_eeprom_read16(np
, start
+ 2);
8316 /* Check for OBP image type. */
8317 err
= niu_pci_eeprom_read(np
, start
+ 20);
8321 err
= niu_pci_eeprom_read(np
, ret
+ 2);
8325 start
= ret
+ (err
* 512);
8329 err
= niu_pci_eeprom_read16_swp(np
, start
+ 8);
8334 err
= niu_pci_eeprom_read(np
, ret
+ 0);
8344 static int __devinit
niu_phy_type_prop_decode(struct niu
*np
,
8345 const char *phy_prop
)
8347 if (!strcmp(phy_prop
, "mif")) {
8348 /* 1G copper, MII */
8349 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8351 np
->mac_xcvr
= MAC_XCVR_MII
;
8352 } else if (!strcmp(phy_prop
, "xgf")) {
8353 /* 10G fiber, XPCS */
8354 np
->flags
|= (NIU_FLAGS_10G
|
8356 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8357 } else if (!strcmp(phy_prop
, "pcs")) {
8359 np
->flags
&= ~NIU_FLAGS_10G
;
8360 np
->flags
|= NIU_FLAGS_FIBER
;
8361 np
->mac_xcvr
= MAC_XCVR_PCS
;
8362 } else if (!strcmp(phy_prop
, "xgc")) {
8363 /* 10G copper, XPCS */
8364 np
->flags
|= NIU_FLAGS_10G
;
8365 np
->flags
&= ~NIU_FLAGS_FIBER
;
8366 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8367 } else if (!strcmp(phy_prop
, "xgsd") || !strcmp(phy_prop
, "gsd")) {
8368 /* 10G Serdes or 1G Serdes, default to 10G */
8369 np
->flags
|= NIU_FLAGS_10G
;
8370 np
->flags
&= ~NIU_FLAGS_FIBER
;
8371 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8372 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8379 static int niu_pci_vpd_get_nports(struct niu
*np
)
8383 if ((!strcmp(np
->vpd
.model
, NIU_QGC_LP_MDL_STR
)) ||
8384 (!strcmp(np
->vpd
.model
, NIU_QGC_PEM_MDL_STR
)) ||
8385 (!strcmp(np
->vpd
.model
, NIU_MARAMBA_MDL_STR
)) ||
8386 (!strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) ||
8387 (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
))) {
8389 } else if ((!strcmp(np
->vpd
.model
, NIU_2XGF_LP_MDL_STR
)) ||
8390 (!strcmp(np
->vpd
.model
, NIU_2XGF_PEM_MDL_STR
)) ||
8391 (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) ||
8392 (!strcmp(np
->vpd
.model
, NIU_2XGF_MRVL_MDL_STR
))) {
8399 static void __devinit
niu_pci_vpd_validate(struct niu
*np
)
8401 struct net_device
*dev
= np
->dev
;
8402 struct niu_vpd
*vpd
= &np
->vpd
;
8405 if (!is_valid_ether_addr(&vpd
->local_mac
[0])) {
8406 dev_err(np
->device
, PFX
"VPD MAC invalid, "
8407 "falling back to SPROM.\n");
8409 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8413 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8414 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8415 np
->flags
|= NIU_FLAGS_10G
;
8416 np
->flags
&= ~NIU_FLAGS_FIBER
;
8417 np
->flags
|= NIU_FLAGS_XCVR_SERDES
;
8418 np
->mac_xcvr
= MAC_XCVR_PCS
;
8420 np
->flags
|= NIU_FLAGS_FIBER
;
8421 np
->flags
&= ~NIU_FLAGS_10G
;
8423 if (np
->flags
& NIU_FLAGS_10G
)
8424 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8425 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8426 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
8427 NIU_FLAGS_HOTPLUG_PHY
);
8428 } else if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
8429 dev_err(np
->device
, PFX
"Illegal phy string [%s].\n",
8431 dev_err(np
->device
, PFX
"Falling back to SPROM.\n");
8432 np
->flags
&= ~NIU_FLAGS_VPD_VALID
;
8436 memcpy(dev
->perm_addr
, vpd
->local_mac
, ETH_ALEN
);
8438 val8
= dev
->perm_addr
[5];
8439 dev
->perm_addr
[5] += np
->port
;
8440 if (dev
->perm_addr
[5] < val8
)
8441 dev
->perm_addr
[4]++;
8443 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8446 static int __devinit
niu_pci_probe_sprom(struct niu
*np
)
8448 struct net_device
*dev
= np
->dev
;
8453 val
= (nr64(ESPC_VER_IMGSZ
) & ESPC_VER_IMGSZ_IMGSZ
);
8454 val
>>= ESPC_VER_IMGSZ_IMGSZ_SHIFT
;
8457 np
->eeprom_len
= len
;
8459 niudbg(PROBE
, "SPROM: Image size %llu\n", (unsigned long long) val
);
8462 for (i
= 0; i
< len
; i
++) {
8463 val
= nr64(ESPC_NCR(i
));
8464 sum
+= (val
>> 0) & 0xff;
8465 sum
+= (val
>> 8) & 0xff;
8466 sum
+= (val
>> 16) & 0xff;
8467 sum
+= (val
>> 24) & 0xff;
8469 niudbg(PROBE
, "SPROM: Checksum %x\n", (int)(sum
& 0xff));
8470 if ((sum
& 0xff) != 0xab) {
8471 dev_err(np
->device
, PFX
"Bad SPROM checksum "
8472 "(%x, should be 0xab)\n", (int) (sum
& 0xff));
8476 val
= nr64(ESPC_PHY_TYPE
);
8479 val8
= (val
& ESPC_PHY_TYPE_PORT0
) >>
8480 ESPC_PHY_TYPE_PORT0_SHIFT
;
8483 val8
= (val
& ESPC_PHY_TYPE_PORT1
) >>
8484 ESPC_PHY_TYPE_PORT1_SHIFT
;
8487 val8
= (val
& ESPC_PHY_TYPE_PORT2
) >>
8488 ESPC_PHY_TYPE_PORT2_SHIFT
;
8491 val8
= (val
& ESPC_PHY_TYPE_PORT3
) >>
8492 ESPC_PHY_TYPE_PORT3_SHIFT
;
8495 dev_err(np
->device
, PFX
"Bogus port number %u\n",
8499 niudbg(PROBE
, "SPROM: PHY type %x\n", val8
);
8502 case ESPC_PHY_TYPE_1G_COPPER
:
8503 /* 1G copper, MII */
8504 np
->flags
&= ~(NIU_FLAGS_FIBER
|
8506 np
->mac_xcvr
= MAC_XCVR_MII
;
8509 case ESPC_PHY_TYPE_1G_FIBER
:
8511 np
->flags
&= ~NIU_FLAGS_10G
;
8512 np
->flags
|= NIU_FLAGS_FIBER
;
8513 np
->mac_xcvr
= MAC_XCVR_PCS
;
8516 case ESPC_PHY_TYPE_10G_COPPER
:
8517 /* 10G copper, XPCS */
8518 np
->flags
|= NIU_FLAGS_10G
;
8519 np
->flags
&= ~NIU_FLAGS_FIBER
;
8520 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8523 case ESPC_PHY_TYPE_10G_FIBER
:
8524 /* 10G fiber, XPCS */
8525 np
->flags
|= (NIU_FLAGS_10G
|
8527 np
->mac_xcvr
= MAC_XCVR_XPCS
;
8531 dev_err(np
->device
, PFX
"Bogus SPROM phy type %u\n", val8
);
8535 val
= nr64(ESPC_MAC_ADDR0
);
8536 niudbg(PROBE
, "SPROM: MAC_ADDR0[%08llx]\n",
8537 (unsigned long long) val
);
8538 dev
->perm_addr
[0] = (val
>> 0) & 0xff;
8539 dev
->perm_addr
[1] = (val
>> 8) & 0xff;
8540 dev
->perm_addr
[2] = (val
>> 16) & 0xff;
8541 dev
->perm_addr
[3] = (val
>> 24) & 0xff;
8543 val
= nr64(ESPC_MAC_ADDR1
);
8544 niudbg(PROBE
, "SPROM: MAC_ADDR1[%08llx]\n",
8545 (unsigned long long) val
);
8546 dev
->perm_addr
[4] = (val
>> 0) & 0xff;
8547 dev
->perm_addr
[5] = (val
>> 8) & 0xff;
8549 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
8550 dev_err(np
->device
, PFX
"SPROM MAC address invalid\n");
8551 dev_err(np
->device
, PFX
"[ \n");
8552 for (i
= 0; i
< 6; i
++)
8553 printk("%02x ", dev
->perm_addr
[i
]);
8558 val8
= dev
->perm_addr
[5];
8559 dev
->perm_addr
[5] += np
->port
;
8560 if (dev
->perm_addr
[5] < val8
)
8561 dev
->perm_addr
[4]++;
8563 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
8565 val
= nr64(ESPC_MOD_STR_LEN
);
8566 niudbg(PROBE
, "SPROM: MOD_STR_LEN[%llu]\n",
8567 (unsigned long long) val
);
8571 for (i
= 0; i
< val
; i
+= 4) {
8572 u64 tmp
= nr64(ESPC_NCR(5 + (i
/ 4)));
8574 np
->vpd
.model
[i
+ 3] = (tmp
>> 0) & 0xff;
8575 np
->vpd
.model
[i
+ 2] = (tmp
>> 8) & 0xff;
8576 np
->vpd
.model
[i
+ 1] = (tmp
>> 16) & 0xff;
8577 np
->vpd
.model
[i
+ 0] = (tmp
>> 24) & 0xff;
8579 np
->vpd
.model
[val
] = '\0';
8581 val
= nr64(ESPC_BD_MOD_STR_LEN
);
8582 niudbg(PROBE
, "SPROM: BD_MOD_STR_LEN[%llu]\n",
8583 (unsigned long long) val
);
8587 for (i
= 0; i
< val
; i
+= 4) {
8588 u64 tmp
= nr64(ESPC_NCR(14 + (i
/ 4)));
8590 np
->vpd
.board_model
[i
+ 3] = (tmp
>> 0) & 0xff;
8591 np
->vpd
.board_model
[i
+ 2] = (tmp
>> 8) & 0xff;
8592 np
->vpd
.board_model
[i
+ 1] = (tmp
>> 16) & 0xff;
8593 np
->vpd
.board_model
[i
+ 0] = (tmp
>> 24) & 0xff;
8595 np
->vpd
.board_model
[val
] = '\0';
8598 nr64(ESPC_NUM_PORTS_MACS
) & ESPC_NUM_PORTS_MACS_VAL
;
8599 niudbg(PROBE
, "SPROM: NUM_PORTS_MACS[%d]\n",
8605 static int __devinit
niu_get_and_validate_port(struct niu
*np
)
8607 struct niu_parent
*parent
= np
->parent
;
8610 np
->flags
|= NIU_FLAGS_XMAC
;
8612 if (!parent
->num_ports
) {
8613 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
8614 parent
->num_ports
= 2;
8616 parent
->num_ports
= niu_pci_vpd_get_nports(np
);
8617 if (!parent
->num_ports
) {
8618 /* Fall back to SPROM as last resort.
8619 * This will fail on most cards.
8621 parent
->num_ports
= nr64(ESPC_NUM_PORTS_MACS
) &
8622 ESPC_NUM_PORTS_MACS_VAL
;
8624 /* All of the current probing methods fail on
8625 * Maramba on-board parts.
8627 if (!parent
->num_ports
)
8628 parent
->num_ports
= 4;
8633 niudbg(PROBE
, "niu_get_and_validate_port: port[%d] num_ports[%d]\n",
8634 np
->port
, parent
->num_ports
);
8635 if (np
->port
>= parent
->num_ports
)
8641 static int __devinit
phy_record(struct niu_parent
*parent
,
8642 struct phy_probe_info
*p
,
8643 int dev_id_1
, int dev_id_2
, u8 phy_port
,
8646 u32 id
= (dev_id_1
<< 16) | dev_id_2
;
8649 if (dev_id_1
< 0 || dev_id_2
< 0)
8651 if (type
== PHY_TYPE_PMA_PMD
|| type
== PHY_TYPE_PCS
) {
8652 if (((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8704
) &&
8653 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_MRVL88X2011
) &&
8654 ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM8706
))
8657 if ((id
& NIU_PHY_ID_MASK
) != NIU_PHY_ID_BCM5464R
)
8661 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n",
8663 (type
== PHY_TYPE_PMA_PMD
?
8665 (type
== PHY_TYPE_PCS
?
8669 if (p
->cur
[type
] >= NIU_MAX_PORTS
) {
8670 printk(KERN_ERR PFX
"Too many PHY ports.\n");
8674 p
->phy_id
[type
][idx
] = id
;
8675 p
->phy_port
[type
][idx
] = phy_port
;
8676 p
->cur
[type
] = idx
+ 1;
8680 static int __devinit
port_has_10g(struct phy_probe_info
*p
, int port
)
8684 for (i
= 0; i
< p
->cur
[PHY_TYPE_PMA_PMD
]; i
++) {
8685 if (p
->phy_port
[PHY_TYPE_PMA_PMD
][i
] == port
)
8688 for (i
= 0; i
< p
->cur
[PHY_TYPE_PCS
]; i
++) {
8689 if (p
->phy_port
[PHY_TYPE_PCS
][i
] == port
)
8696 static int __devinit
count_10g_ports(struct phy_probe_info
*p
, int *lowest
)
8702 for (port
= 8; port
< 32; port
++) {
8703 if (port_has_10g(p
, port
)) {
8713 static int __devinit
count_1g_ports(struct phy_probe_info
*p
, int *lowest
)
8716 if (p
->cur
[PHY_TYPE_MII
])
8717 *lowest
= p
->phy_port
[PHY_TYPE_MII
][0];
8719 return p
->cur
[PHY_TYPE_MII
];
8722 static void __devinit
niu_n2_divide_channels(struct niu_parent
*parent
)
8724 int num_ports
= parent
->num_ports
;
8727 for (i
= 0; i
< num_ports
; i
++) {
8728 parent
->rxchan_per_port
[i
] = (16 / num_ports
);
8729 parent
->txchan_per_port
[i
] = (16 / num_ports
);
8731 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
8734 parent
->rxchan_per_port
[i
],
8735 parent
->txchan_per_port
[i
]);
8739 static void __devinit
niu_divide_channels(struct niu_parent
*parent
,
8740 int num_10g
, int num_1g
)
8742 int num_ports
= parent
->num_ports
;
8743 int rx_chans_per_10g
, rx_chans_per_1g
;
8744 int tx_chans_per_10g
, tx_chans_per_1g
;
8745 int i
, tot_rx
, tot_tx
;
8747 if (!num_10g
|| !num_1g
) {
8748 rx_chans_per_10g
= rx_chans_per_1g
=
8749 (NIU_NUM_RXCHAN
/ num_ports
);
8750 tx_chans_per_10g
= tx_chans_per_1g
=
8751 (NIU_NUM_TXCHAN
/ num_ports
);
8753 rx_chans_per_1g
= NIU_NUM_RXCHAN
/ 8;
8754 rx_chans_per_10g
= (NIU_NUM_RXCHAN
-
8755 (rx_chans_per_1g
* num_1g
)) /
8758 tx_chans_per_1g
= NIU_NUM_TXCHAN
/ 6;
8759 tx_chans_per_10g
= (NIU_NUM_TXCHAN
-
8760 (tx_chans_per_1g
* num_1g
)) /
8764 tot_rx
= tot_tx
= 0;
8765 for (i
= 0; i
< num_ports
; i
++) {
8766 int type
= phy_decode(parent
->port_phy
, i
);
8768 if (type
== PORT_TYPE_10G
) {
8769 parent
->rxchan_per_port
[i
] = rx_chans_per_10g
;
8770 parent
->txchan_per_port
[i
] = tx_chans_per_10g
;
8772 parent
->rxchan_per_port
[i
] = rx_chans_per_1g
;
8773 parent
->txchan_per_port
[i
] = tx_chans_per_1g
;
8775 pr_info(PFX
"niu%d: Port %u [%u RX chans] "
8778 parent
->rxchan_per_port
[i
],
8779 parent
->txchan_per_port
[i
]);
8780 tot_rx
+= parent
->rxchan_per_port
[i
];
8781 tot_tx
+= parent
->txchan_per_port
[i
];
8784 if (tot_rx
> NIU_NUM_RXCHAN
) {
8785 printk(KERN_ERR PFX
"niu%d: Too many RX channels (%d), "
8786 "resetting to one per port.\n",
8787 parent
->index
, tot_rx
);
8788 for (i
= 0; i
< num_ports
; i
++)
8789 parent
->rxchan_per_port
[i
] = 1;
8791 if (tot_tx
> NIU_NUM_TXCHAN
) {
8792 printk(KERN_ERR PFX
"niu%d: Too many TX channels (%d), "
8793 "resetting to one per port.\n",
8794 parent
->index
, tot_tx
);
8795 for (i
= 0; i
< num_ports
; i
++)
8796 parent
->txchan_per_port
[i
] = 1;
8798 if (tot_rx
< NIU_NUM_RXCHAN
|| tot_tx
< NIU_NUM_TXCHAN
) {
8799 printk(KERN_WARNING PFX
"niu%d: Driver bug, wasted channels, "
8801 parent
->index
, tot_rx
, tot_tx
);
8805 static void __devinit
niu_divide_rdc_groups(struct niu_parent
*parent
,
8806 int num_10g
, int num_1g
)
8808 int i
, num_ports
= parent
->num_ports
;
8809 int rdc_group
, rdc_groups_per_port
;
8810 int rdc_channel_base
;
8813 rdc_groups_per_port
= NIU_NUM_RDC_TABLES
/ num_ports
;
8815 rdc_channel_base
= 0;
8817 for (i
= 0; i
< num_ports
; i
++) {
8818 struct niu_rdc_tables
*tp
= &parent
->rdc_group_cfg
[i
];
8819 int grp
, num_channels
= parent
->rxchan_per_port
[i
];
8820 int this_channel_offset
;
8822 tp
->first_table_num
= rdc_group
;
8823 tp
->num_tables
= rdc_groups_per_port
;
8824 this_channel_offset
= 0;
8825 for (grp
= 0; grp
< tp
->num_tables
; grp
++) {
8826 struct rdc_table
*rt
= &tp
->tables
[grp
];
8829 pr_info(PFX
"niu%d: Port %d RDC tbl(%d) [ ",
8830 parent
->index
, i
, tp
->first_table_num
+ grp
);
8831 for (slot
= 0; slot
< NIU_RDC_TABLE_SLOTS
; slot
++) {
8832 rt
->rxdma_channel
[slot
] =
8833 rdc_channel_base
+ this_channel_offset
;
8835 printk("%d ", rt
->rxdma_channel
[slot
]);
8837 if (++this_channel_offset
== num_channels
)
8838 this_channel_offset
= 0;
8843 parent
->rdc_default
[i
] = rdc_channel_base
;
8845 rdc_channel_base
+= num_channels
;
8846 rdc_group
+= rdc_groups_per_port
;
8850 static int __devinit
fill_phy_probe_info(struct niu
*np
,
8851 struct niu_parent
*parent
,
8852 struct phy_probe_info
*info
)
8854 unsigned long flags
;
8857 memset(info
, 0, sizeof(*info
));
8859 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */
8860 niu_lock_parent(np
, flags
);
8862 for (port
= 8; port
< 32; port
++) {
8863 int dev_id_1
, dev_id_2
;
8865 dev_id_1
= mdio_read(np
, port
,
8866 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID1
);
8867 dev_id_2
= mdio_read(np
, port
,
8868 NIU_PMA_PMD_DEV_ADDR
, MII_PHYSID2
);
8869 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8873 dev_id_1
= mdio_read(np
, port
,
8874 NIU_PCS_DEV_ADDR
, MII_PHYSID1
);
8875 dev_id_2
= mdio_read(np
, port
,
8876 NIU_PCS_DEV_ADDR
, MII_PHYSID2
);
8877 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8881 dev_id_1
= mii_read(np
, port
, MII_PHYSID1
);
8882 dev_id_2
= mii_read(np
, port
, MII_PHYSID2
);
8883 err
= phy_record(parent
, info
, dev_id_1
, dev_id_2
, port
,
8888 niu_unlock_parent(np
, flags
);
8893 static int __devinit
walk_phys(struct niu
*np
, struct niu_parent
*parent
)
8895 struct phy_probe_info
*info
= &parent
->phy_probe_info
;
8896 int lowest_10g
, lowest_1g
;
8897 int num_10g
, num_1g
;
8901 num_10g
= num_1g
= 0;
8903 if (!strcmp(np
->vpd
.model
, NIU_ALONSO_MDL_STR
) ||
8904 !strcmp(np
->vpd
.model
, NIU_KIMI_MDL_STR
)) {
8907 parent
->plat_type
= PLAT_TYPE_ATCA_CP3220
;
8908 parent
->num_ports
= 4;
8909 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8910 phy_encode(PORT_TYPE_1G
, 1) |
8911 phy_encode(PORT_TYPE_1G
, 2) |
8912 phy_encode(PORT_TYPE_1G
, 3));
8913 } else if (!strcmp(np
->vpd
.model
, NIU_FOXXY_MDL_STR
)) {
8916 parent
->num_ports
= 2;
8917 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8918 phy_encode(PORT_TYPE_10G
, 1));
8919 } else if ((np
->flags
& NIU_FLAGS_XCVR_SERDES
) &&
8920 (parent
->plat_type
== PLAT_TYPE_NIU
)) {
8921 /* this is the Monza case */
8922 if (np
->flags
& NIU_FLAGS_10G
) {
8923 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8924 phy_encode(PORT_TYPE_10G
, 1));
8926 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8927 phy_encode(PORT_TYPE_1G
, 1));
8930 err
= fill_phy_probe_info(np
, parent
, info
);
8934 num_10g
= count_10g_ports(info
, &lowest_10g
);
8935 num_1g
= count_1g_ports(info
, &lowest_1g
);
8937 switch ((num_10g
<< 4) | num_1g
) {
8939 if (lowest_1g
== 10)
8940 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8941 else if (lowest_1g
== 26)
8942 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8944 goto unknown_vg_1g_port
;
8948 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8949 phy_encode(PORT_TYPE_10G
, 1) |
8950 phy_encode(PORT_TYPE_1G
, 2) |
8951 phy_encode(PORT_TYPE_1G
, 3));
8955 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8956 phy_encode(PORT_TYPE_10G
, 1));
8960 val
= phy_encode(PORT_TYPE_10G
, np
->port
);
8964 if (lowest_1g
== 10)
8965 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8966 else if (lowest_1g
== 26)
8967 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8969 goto unknown_vg_1g_port
;
8973 if ((lowest_10g
& 0x7) == 0)
8974 val
= (phy_encode(PORT_TYPE_10G
, 0) |
8975 phy_encode(PORT_TYPE_1G
, 1) |
8976 phy_encode(PORT_TYPE_1G
, 2) |
8977 phy_encode(PORT_TYPE_1G
, 3));
8979 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8980 phy_encode(PORT_TYPE_10G
, 1) |
8981 phy_encode(PORT_TYPE_1G
, 2) |
8982 phy_encode(PORT_TYPE_1G
, 3));
8986 if (lowest_1g
== 10)
8987 parent
->plat_type
= PLAT_TYPE_VF_P0
;
8988 else if (lowest_1g
== 26)
8989 parent
->plat_type
= PLAT_TYPE_VF_P1
;
8991 goto unknown_vg_1g_port
;
8993 val
= (phy_encode(PORT_TYPE_1G
, 0) |
8994 phy_encode(PORT_TYPE_1G
, 1) |
8995 phy_encode(PORT_TYPE_1G
, 2) |
8996 phy_encode(PORT_TYPE_1G
, 3));
9000 printk(KERN_ERR PFX
"Unsupported port config "
9007 parent
->port_phy
= val
;
9009 if (parent
->plat_type
== PLAT_TYPE_NIU
)
9010 niu_n2_divide_channels(parent
);
9012 niu_divide_channels(parent
, num_10g
, num_1g
);
9014 niu_divide_rdc_groups(parent
, num_10g
, num_1g
);
9019 printk(KERN_ERR PFX
"Cannot identify platform type, 1gport=%d\n",
9024 static int __devinit
niu_probe_ports(struct niu
*np
)
9026 struct niu_parent
*parent
= np
->parent
;
9029 niudbg(PROBE
, "niu_probe_ports(): port_phy[%08x]\n",
9032 if (parent
->port_phy
== PORT_PHY_UNKNOWN
) {
9033 err
= walk_phys(np
, parent
);
9037 niu_set_ldg_timer_res(np
, 2);
9038 for (i
= 0; i
<= LDN_MAX
; i
++)
9039 niu_ldn_irq_enable(np
, i
, 0);
9042 if (parent
->port_phy
== PORT_PHY_INVALID
)
9048 static int __devinit
niu_classifier_swstate_init(struct niu
*np
)
9050 struct niu_classifier
*cp
= &np
->clas
;
9052 niudbg(PROBE
, "niu_classifier_swstate_init: num_tcam(%d)\n",
9053 np
->parent
->tcam_num_entries
);
9055 cp
->tcam_top
= (u16
) np
->port
;
9056 cp
->tcam_sz
= np
->parent
->tcam_num_entries
/ np
->parent
->num_ports
;
9057 cp
->h1_init
= 0xffffffff;
9058 cp
->h2_init
= 0xffff;
9060 return fflp_early_init(np
);
9063 static void __devinit
niu_link_config_init(struct niu
*np
)
9065 struct niu_link_config
*lp
= &np
->link_config
;
9067 lp
->advertising
= (ADVERTISED_10baseT_Half
|
9068 ADVERTISED_10baseT_Full
|
9069 ADVERTISED_100baseT_Half
|
9070 ADVERTISED_100baseT_Full
|
9071 ADVERTISED_1000baseT_Half
|
9072 ADVERTISED_1000baseT_Full
|
9073 ADVERTISED_10000baseT_Full
|
9074 ADVERTISED_Autoneg
);
9075 lp
->speed
= lp
->active_speed
= SPEED_INVALID
;
9076 lp
->duplex
= DUPLEX_FULL
;
9077 lp
->active_duplex
= DUPLEX_INVALID
;
9080 lp
->loopback_mode
= LOOPBACK_MAC
;
9081 lp
->active_speed
= SPEED_10000
;
9082 lp
->active_duplex
= DUPLEX_FULL
;
9084 lp
->loopback_mode
= LOOPBACK_DISABLED
;
9088 static int __devinit
niu_init_mac_ipp_pcs_base(struct niu
*np
)
9092 np
->mac_regs
= np
->regs
+ XMAC_PORT0_OFF
;
9093 np
->ipp_off
= 0x00000;
9094 np
->pcs_off
= 0x04000;
9095 np
->xpcs_off
= 0x02000;
9099 np
->mac_regs
= np
->regs
+ XMAC_PORT1_OFF
;
9100 np
->ipp_off
= 0x08000;
9101 np
->pcs_off
= 0x0a000;
9102 np
->xpcs_off
= 0x08000;
9106 np
->mac_regs
= np
->regs
+ BMAC_PORT2_OFF
;
9107 np
->ipp_off
= 0x04000;
9108 np
->pcs_off
= 0x0e000;
9109 np
->xpcs_off
= ~0UL;
9113 np
->mac_regs
= np
->regs
+ BMAC_PORT3_OFF
;
9114 np
->ipp_off
= 0x0c000;
9115 np
->pcs_off
= 0x12000;
9116 np
->xpcs_off
= ~0UL;
9120 dev_err(np
->device
, PFX
"Port %u is invalid, cannot "
9121 "compute MAC block offset.\n", np
->port
);
9128 static void __devinit
niu_try_msix(struct niu
*np
, u8
*ldg_num_map
)
9130 struct msix_entry msi_vec
[NIU_NUM_LDG
];
9131 struct niu_parent
*parent
= np
->parent
;
9132 struct pci_dev
*pdev
= np
->pdev
;
9133 int i
, num_irqs
, err
;
9136 first_ldg
= (NIU_NUM_LDG
/ parent
->num_ports
) * np
->port
;
9137 for (i
= 0; i
< (NIU_NUM_LDG
/ parent
->num_ports
); i
++)
9138 ldg_num_map
[i
] = first_ldg
+ i
;
9140 num_irqs
= (parent
->rxchan_per_port
[np
->port
] +
9141 parent
->txchan_per_port
[np
->port
] +
9142 (np
->port
== 0 ? 3 : 1));
9143 BUG_ON(num_irqs
> (NIU_NUM_LDG
/ parent
->num_ports
));
9146 for (i
= 0; i
< num_irqs
; i
++) {
9147 msi_vec
[i
].vector
= 0;
9148 msi_vec
[i
].entry
= i
;
9151 err
= pci_enable_msix(pdev
, msi_vec
, num_irqs
);
9153 np
->flags
&= ~NIU_FLAGS_MSIX
;
9161 np
->flags
|= NIU_FLAGS_MSIX
;
9162 for (i
= 0; i
< num_irqs
; i
++)
9163 np
->ldg
[i
].irq
= msi_vec
[i
].vector
;
9164 np
->num_ldg
= num_irqs
;
9167 static int __devinit
niu_n2_irq_init(struct niu
*np
, u8
*ldg_num_map
)
9169 #ifdef CONFIG_SPARC64
9170 struct of_device
*op
= np
->op
;
9171 const u32
*int_prop
;
9174 int_prop
= of_get_property(op
->node
, "interrupts", NULL
);
9178 for (i
= 0; i
< op
->num_irqs
; i
++) {
9179 ldg_num_map
[i
] = int_prop
[i
];
9180 np
->ldg
[i
].irq
= op
->irqs
[i
];
9183 np
->num_ldg
= op
->num_irqs
;
9191 static int __devinit
niu_ldg_init(struct niu
*np
)
9193 struct niu_parent
*parent
= np
->parent
;
9194 u8 ldg_num_map
[NIU_NUM_LDG
];
9195 int first_chan
, num_chan
;
9196 int i
, err
, ldg_rotor
;
9200 np
->ldg
[0].irq
= np
->dev
->irq
;
9201 if (parent
->plat_type
== PLAT_TYPE_NIU
) {
9202 err
= niu_n2_irq_init(np
, ldg_num_map
);
9206 niu_try_msix(np
, ldg_num_map
);
9209 for (i
= 0; i
< np
->num_ldg
; i
++) {
9210 struct niu_ldg
*lp
= &np
->ldg
[i
];
9212 netif_napi_add(np
->dev
, &lp
->napi
, niu_poll
, 64);
9215 lp
->ldg_num
= ldg_num_map
[i
];
9216 lp
->timer
= 2; /* XXX */
9218 /* On N2 NIU the firmware has setup the SID mappings so they go
9219 * to the correct values that will route the LDG to the proper
9220 * interrupt in the NCU interrupt table.
9222 if (np
->parent
->plat_type
!= PLAT_TYPE_NIU
) {
9223 err
= niu_set_ldg_sid(np
, lp
->ldg_num
, port
, i
);
9229 /* We adopt the LDG assignment ordering used by the N2 NIU
9230 * 'interrupt' properties because that simplifies a lot of
9231 * things. This ordering is:
9234 * MIF (if port zero)
9235 * SYSERR (if port zero)
9242 err
= niu_ldg_assign_ldn(np
, parent
, ldg_num_map
[ldg_rotor
],
9248 if (ldg_rotor
== np
->num_ldg
)
9252 err
= niu_ldg_assign_ldn(np
, parent
,
9253 ldg_num_map
[ldg_rotor
],
9259 if (ldg_rotor
== np
->num_ldg
)
9262 err
= niu_ldg_assign_ldn(np
, parent
,
9263 ldg_num_map
[ldg_rotor
],
9269 if (ldg_rotor
== np
->num_ldg
)
9275 for (i
= 0; i
< port
; i
++)
9276 first_chan
+= parent
->rxchan_per_port
[port
];
9277 num_chan
= parent
->rxchan_per_port
[port
];
9279 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9280 err
= niu_ldg_assign_ldn(np
, parent
,
9281 ldg_num_map
[ldg_rotor
],
9286 if (ldg_rotor
== np
->num_ldg
)
9291 for (i
= 0; i
< port
; i
++)
9292 first_chan
+= parent
->txchan_per_port
[port
];
9293 num_chan
= parent
->txchan_per_port
[port
];
9294 for (i
= first_chan
; i
< (first_chan
+ num_chan
); i
++) {
9295 err
= niu_ldg_assign_ldn(np
, parent
,
9296 ldg_num_map
[ldg_rotor
],
9301 if (ldg_rotor
== np
->num_ldg
)
9308 static void __devexit
niu_ldg_free(struct niu
*np
)
9310 if (np
->flags
& NIU_FLAGS_MSIX
)
9311 pci_disable_msix(np
->pdev
);
9314 static int __devinit
niu_get_of_props(struct niu
*np
)
9316 #ifdef CONFIG_SPARC64
9317 struct net_device
*dev
= np
->dev
;
9318 struct device_node
*dp
;
9319 const char *phy_type
;
9324 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9327 dp
= pci_device_to_OF_node(np
->pdev
);
9329 phy_type
= of_get_property(dp
, "phy-type", &prop_len
);
9331 dev_err(np
->device
, PFX
"%s: OF node lacks "
9332 "phy-type property\n",
9337 if (!strcmp(phy_type
, "none"))
9340 strcpy(np
->vpd
.phy_type
, phy_type
);
9342 if (niu_phy_type_prop_decode(np
, np
->vpd
.phy_type
)) {
9343 dev_err(np
->device
, PFX
"%s: Illegal phy string [%s].\n",
9344 dp
->full_name
, np
->vpd
.phy_type
);
9348 mac_addr
= of_get_property(dp
, "local-mac-address", &prop_len
);
9350 dev_err(np
->device
, PFX
"%s: OF node lacks "
9351 "local-mac-address property\n",
9355 if (prop_len
!= dev
->addr_len
) {
9356 dev_err(np
->device
, PFX
"%s: OF MAC address prop len (%d) "
9358 dp
->full_name
, prop_len
);
9360 memcpy(dev
->perm_addr
, mac_addr
, dev
->addr_len
);
9361 if (!is_valid_ether_addr(&dev
->perm_addr
[0])) {
9364 dev_err(np
->device
, PFX
"%s: OF MAC address is invalid\n",
9366 dev_err(np
->device
, PFX
"%s: [ \n",
9368 for (i
= 0; i
< 6; i
++)
9369 printk("%02x ", dev
->perm_addr
[i
]);
9374 memcpy(dev
->dev_addr
, dev
->perm_addr
, dev
->addr_len
);
9376 model
= of_get_property(dp
, "model", &prop_len
);
9379 strcpy(np
->vpd
.model
, model
);
9381 if (of_find_property(dp
, "hot-swappable-phy", &prop_len
)) {
9382 np
->flags
|= (NIU_FLAGS_10G
| NIU_FLAGS_FIBER
|
9383 NIU_FLAGS_HOTPLUG_PHY
);
9392 static int __devinit
niu_get_invariants(struct niu
*np
)
9394 int err
, have_props
;
9397 err
= niu_get_of_props(np
);
9403 err
= niu_init_mac_ipp_pcs_base(np
);
9408 err
= niu_get_and_validate_port(np
);
9413 if (np
->parent
->plat_type
== PLAT_TYPE_NIU
)
9416 nw64(ESPC_PIO_EN
, ESPC_PIO_EN_ENABLE
);
9417 offset
= niu_pci_vpd_offset(np
);
9418 niudbg(PROBE
, "niu_get_invariants: VPD offset [%08x]\n",
9421 niu_pci_vpd_fetch(np
, offset
);
9422 nw64(ESPC_PIO_EN
, 0);
9424 if (np
->flags
& NIU_FLAGS_VPD_VALID
) {
9425 niu_pci_vpd_validate(np
);
9426 err
= niu_get_and_validate_port(np
);
9431 if (!(np
->flags
& NIU_FLAGS_VPD_VALID
)) {
9432 err
= niu_get_and_validate_port(np
);
9435 err
= niu_pci_probe_sprom(np
);
9441 err
= niu_probe_ports(np
);
9447 niu_classifier_swstate_init(np
);
9448 niu_link_config_init(np
);
9450 err
= niu_determine_phy_disposition(np
);
9452 err
= niu_init_link(np
);
9457 static LIST_HEAD(niu_parent_list
);
9458 static DEFINE_MUTEX(niu_parent_lock
);
9459 static int niu_parent_index
;
9461 static ssize_t
show_port_phy(struct device
*dev
,
9462 struct device_attribute
*attr
, char *buf
)
9464 struct platform_device
*plat_dev
= to_platform_device(dev
);
9465 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9466 u32 port_phy
= p
->port_phy
;
9467 char *orig_buf
= buf
;
9470 if (port_phy
== PORT_PHY_UNKNOWN
||
9471 port_phy
== PORT_PHY_INVALID
)
9474 for (i
= 0; i
< p
->num_ports
; i
++) {
9475 const char *type_str
;
9478 type
= phy_decode(port_phy
, i
);
9479 if (type
== PORT_TYPE_10G
)
9484 (i
== 0) ? "%s" : " %s",
9487 buf
+= sprintf(buf
, "\n");
9488 return buf
- orig_buf
;
9491 static ssize_t
show_plat_type(struct device
*dev
,
9492 struct device_attribute
*attr
, char *buf
)
9494 struct platform_device
*plat_dev
= to_platform_device(dev
);
9495 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9496 const char *type_str
;
9498 switch (p
->plat_type
) {
9499 case PLAT_TYPE_ATLAS
:
9505 case PLAT_TYPE_VF_P0
:
9508 case PLAT_TYPE_VF_P1
:
9512 type_str
= "unknown";
9516 return sprintf(buf
, "%s\n", type_str
);
9519 static ssize_t
__show_chan_per_port(struct device
*dev
,
9520 struct device_attribute
*attr
, char *buf
,
9523 struct platform_device
*plat_dev
= to_platform_device(dev
);
9524 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9525 char *orig_buf
= buf
;
9529 arr
= (rx
? p
->rxchan_per_port
: p
->txchan_per_port
);
9531 for (i
= 0; i
< p
->num_ports
; i
++) {
9533 (i
== 0) ? "%d" : " %d",
9536 buf
+= sprintf(buf
, "\n");
9538 return buf
- orig_buf
;
9541 static ssize_t
show_rxchan_per_port(struct device
*dev
,
9542 struct device_attribute
*attr
, char *buf
)
9544 return __show_chan_per_port(dev
, attr
, buf
, 1);
9547 static ssize_t
show_txchan_per_port(struct device
*dev
,
9548 struct device_attribute
*attr
, char *buf
)
9550 return __show_chan_per_port(dev
, attr
, buf
, 1);
9553 static ssize_t
show_num_ports(struct device
*dev
,
9554 struct device_attribute
*attr
, char *buf
)
9556 struct platform_device
*plat_dev
= to_platform_device(dev
);
9557 struct niu_parent
*p
= plat_dev
->dev
.platform_data
;
9559 return sprintf(buf
, "%d\n", p
->num_ports
);
9562 static struct device_attribute niu_parent_attributes
[] = {
9563 __ATTR(port_phy
, S_IRUGO
, show_port_phy
, NULL
),
9564 __ATTR(plat_type
, S_IRUGO
, show_plat_type
, NULL
),
9565 __ATTR(rxchan_per_port
, S_IRUGO
, show_rxchan_per_port
, NULL
),
9566 __ATTR(txchan_per_port
, S_IRUGO
, show_txchan_per_port
, NULL
),
9567 __ATTR(num_ports
, S_IRUGO
, show_num_ports
, NULL
),
9571 static struct niu_parent
* __devinit
niu_new_parent(struct niu
*np
,
9572 union niu_parent_id
*id
,
9575 struct platform_device
*plat_dev
;
9576 struct niu_parent
*p
;
9579 niudbg(PROBE
, "niu_new_parent: Creating new parent.\n");
9581 plat_dev
= platform_device_register_simple("niu", niu_parent_index
,
9583 if (IS_ERR(plat_dev
))
9586 for (i
= 0; attr_name(niu_parent_attributes
[i
]); i
++) {
9587 int err
= device_create_file(&plat_dev
->dev
,
9588 &niu_parent_attributes
[i
]);
9590 goto fail_unregister
;
9593 p
= kzalloc(sizeof(*p
), GFP_KERNEL
);
9595 goto fail_unregister
;
9597 p
->index
= niu_parent_index
++;
9599 plat_dev
->dev
.platform_data
= p
;
9600 p
->plat_dev
= plat_dev
;
9602 memcpy(&p
->id
, id
, sizeof(*id
));
9603 p
->plat_type
= ptype
;
9604 INIT_LIST_HEAD(&p
->list
);
9605 atomic_set(&p
->refcnt
, 0);
9606 list_add(&p
->list
, &niu_parent_list
);
9607 spin_lock_init(&p
->lock
);
9609 p
->rxdma_clock_divider
= 7500;
9611 p
->tcam_num_entries
= NIU_PCI_TCAM_ENTRIES
;
9612 if (p
->plat_type
== PLAT_TYPE_NIU
)
9613 p
->tcam_num_entries
= NIU_NONPCI_TCAM_ENTRIES
;
9615 for (i
= CLASS_CODE_USER_PROG1
; i
<= CLASS_CODE_SCTP_IPV6
; i
++) {
9616 int index
= i
- CLASS_CODE_USER_PROG1
;
9618 p
->tcam_key
[index
] = TCAM_KEY_TSEL
;
9619 p
->flow_key
[index
] = (FLOW_KEY_IPSA
|
9622 (FLOW_KEY_L4_BYTE12
<<
9623 FLOW_KEY_L4_0_SHIFT
) |
9624 (FLOW_KEY_L4_BYTE12
<<
9625 FLOW_KEY_L4_1_SHIFT
));
9628 for (i
= 0; i
< LDN_MAX
+ 1; i
++)
9629 p
->ldg_map
[i
] = LDG_INVALID
;
9634 platform_device_unregister(plat_dev
);
9638 static struct niu_parent
* __devinit
niu_get_parent(struct niu
*np
,
9639 union niu_parent_id
*id
,
9642 struct niu_parent
*p
, *tmp
;
9643 int port
= np
->port
;
9645 niudbg(PROBE
, "niu_get_parent: platform_type[%u] port[%u]\n",
9648 mutex_lock(&niu_parent_lock
);
9650 list_for_each_entry(tmp
, &niu_parent_list
, list
) {
9651 if (!memcmp(id
, &tmp
->id
, sizeof(*id
))) {
9657 p
= niu_new_parent(np
, id
, ptype
);
9663 sprintf(port_name
, "port%d", port
);
9664 err
= sysfs_create_link(&p
->plat_dev
->dev
.kobj
,
9668 p
->ports
[port
] = np
;
9669 atomic_inc(&p
->refcnt
);
9672 mutex_unlock(&niu_parent_lock
);
9677 static void niu_put_parent(struct niu
*np
)
9679 struct niu_parent
*p
= np
->parent
;
9683 BUG_ON(!p
|| p
->ports
[port
] != np
);
9685 niudbg(PROBE
, "niu_put_parent: port[%u]\n", port
);
9687 sprintf(port_name
, "port%d", port
);
9689 mutex_lock(&niu_parent_lock
);
9691 sysfs_remove_link(&p
->plat_dev
->dev
.kobj
, port_name
);
9693 p
->ports
[port
] = NULL
;
9696 if (atomic_dec_and_test(&p
->refcnt
)) {
9698 platform_device_unregister(p
->plat_dev
);
9701 mutex_unlock(&niu_parent_lock
);
9704 static void *niu_pci_alloc_coherent(struct device
*dev
, size_t size
,
9705 u64
*handle
, gfp_t flag
)
9710 ret
= dma_alloc_coherent(dev
, size
, &dh
, flag
);
9716 static void niu_pci_free_coherent(struct device
*dev
, size_t size
,
9717 void *cpu_addr
, u64 handle
)
9719 dma_free_coherent(dev
, size
, cpu_addr
, handle
);
9722 static u64
niu_pci_map_page(struct device
*dev
, struct page
*page
,
9723 unsigned long offset
, size_t size
,
9724 enum dma_data_direction direction
)
9726 return dma_map_page(dev
, page
, offset
, size
, direction
);
9729 static void niu_pci_unmap_page(struct device
*dev
, u64 dma_address
,
9730 size_t size
, enum dma_data_direction direction
)
9732 dma_unmap_page(dev
, dma_address
, size
, direction
);
9735 static u64
niu_pci_map_single(struct device
*dev
, void *cpu_addr
,
9737 enum dma_data_direction direction
)
9739 return dma_map_single(dev
, cpu_addr
, size
, direction
);
9742 static void niu_pci_unmap_single(struct device
*dev
, u64 dma_address
,
9744 enum dma_data_direction direction
)
9746 dma_unmap_single(dev
, dma_address
, size
, direction
);
9749 static const struct niu_ops niu_pci_ops
= {
9750 .alloc_coherent
= niu_pci_alloc_coherent
,
9751 .free_coherent
= niu_pci_free_coherent
,
9752 .map_page
= niu_pci_map_page
,
9753 .unmap_page
= niu_pci_unmap_page
,
9754 .map_single
= niu_pci_map_single
,
9755 .unmap_single
= niu_pci_unmap_single
,
9758 static void __devinit
niu_driver_version(void)
9760 static int niu_version_printed
;
9762 if (niu_version_printed
++ == 0)
9763 pr_info("%s", version
);
9766 static struct net_device
* __devinit
niu_alloc_and_init(
9767 struct device
*gen_dev
, struct pci_dev
*pdev
,
9768 struct of_device
*op
, const struct niu_ops
*ops
,
9771 struct net_device
*dev
;
9774 dev
= alloc_etherdev_mq(sizeof(struct niu
), NIU_NUM_TXCHAN
);
9776 dev_err(gen_dev
, PFX
"Etherdev alloc failed, aborting.\n");
9780 SET_NETDEV_DEV(dev
, gen_dev
);
9782 np
= netdev_priv(dev
);
9786 np
->device
= gen_dev
;
9789 np
->msg_enable
= niu_debug
;
9791 spin_lock_init(&np
->lock
);
9792 INIT_WORK(&np
->reset_task
, niu_reset_task
);
9799 static const struct net_device_ops niu_netdev_ops
= {
9800 .ndo_open
= niu_open
,
9801 .ndo_stop
= niu_close
,
9802 .ndo_start_xmit
= niu_start_xmit
,
9803 .ndo_get_stats
= niu_get_stats
,
9804 .ndo_set_multicast_list
= niu_set_rx_mode
,
9805 .ndo_validate_addr
= eth_validate_addr
,
9806 .ndo_set_mac_address
= niu_set_mac_addr
,
9807 .ndo_do_ioctl
= niu_ioctl
,
9808 .ndo_tx_timeout
= niu_tx_timeout
,
9809 .ndo_change_mtu
= niu_change_mtu
,
9812 static void __devinit
niu_assign_netdev_ops(struct net_device
*dev
)
9814 dev
->netdev_ops
= &niu_netdev_ops
;
9815 dev
->ethtool_ops
= &niu_ethtool_ops
;
9816 dev
->watchdog_timeo
= NIU_TX_TIMEOUT
;
9819 static void __devinit
niu_device_announce(struct niu
*np
)
9821 struct net_device
*dev
= np
->dev
;
9823 pr_info("%s: NIU Ethernet %pM\n", dev
->name
, dev
->dev_addr
);
9825 if (np
->parent
->plat_type
== PLAT_TYPE_ATCA_CP3220
) {
9826 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9828 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9829 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9830 (np
->flags
& NIU_FLAGS_FIBER
? "RGMII FIBER" : "SERDES"),
9831 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9832 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9835 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n",
9837 (np
->flags
& NIU_FLAGS_XMAC
? "XMAC" : "BMAC"),
9838 (np
->flags
& NIU_FLAGS_10G
? "10G" : "1G"),
9839 (np
->flags
& NIU_FLAGS_FIBER
? "FIBER" :
9840 (np
->flags
& NIU_FLAGS_XCVR_SERDES
? "SERDES" :
9842 (np
->mac_xcvr
== MAC_XCVR_MII
? "MII" :
9843 (np
->mac_xcvr
== MAC_XCVR_PCS
? "PCS" : "XPCS")),
9848 static int __devinit
niu_pci_init_one(struct pci_dev
*pdev
,
9849 const struct pci_device_id
*ent
)
9851 union niu_parent_id parent_id
;
9852 struct net_device
*dev
;
9858 niu_driver_version();
9860 err
= pci_enable_device(pdev
);
9862 dev_err(&pdev
->dev
, PFX
"Cannot enable PCI device, "
9867 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
) ||
9868 !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
9869 dev_err(&pdev
->dev
, PFX
"Cannot find proper PCI device "
9870 "base addresses, aborting.\n");
9872 goto err_out_disable_pdev
;
9875 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
9877 dev_err(&pdev
->dev
, PFX
"Cannot obtain PCI resources, "
9879 goto err_out_disable_pdev
;
9882 pos
= pci_find_capability(pdev
, PCI_CAP_ID_EXP
);
9884 dev_err(&pdev
->dev
, PFX
"Cannot find PCI Express capability, "
9886 goto err_out_free_res
;
9889 dev
= niu_alloc_and_init(&pdev
->dev
, pdev
, NULL
,
9890 &niu_pci_ops
, PCI_FUNC(pdev
->devfn
));
9893 goto err_out_free_res
;
9895 np
= netdev_priv(dev
);
9897 memset(&parent_id
, 0, sizeof(parent_id
));
9898 parent_id
.pci
.domain
= pci_domain_nr(pdev
->bus
);
9899 parent_id
.pci
.bus
= pdev
->bus
->number
;
9900 parent_id
.pci
.device
= PCI_SLOT(pdev
->devfn
);
9902 np
->parent
= niu_get_parent(np
, &parent_id
,
9906 goto err_out_free_dev
;
9909 pci_read_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, &val16
);
9910 val16
&= ~PCI_EXP_DEVCTL_NOSNOOP_EN
;
9911 val16
|= (PCI_EXP_DEVCTL_CERE
|
9912 PCI_EXP_DEVCTL_NFERE
|
9913 PCI_EXP_DEVCTL_FERE
|
9914 PCI_EXP_DEVCTL_URRE
|
9915 PCI_EXP_DEVCTL_RELAX_EN
);
9916 pci_write_config_word(pdev
, pos
+ PCI_EXP_DEVCTL
, val16
);
9918 dma_mask
= DMA_44BIT_MASK
;
9919 err
= pci_set_dma_mask(pdev
, dma_mask
);
9921 dev
->features
|= NETIF_F_HIGHDMA
;
9922 err
= pci_set_consistent_dma_mask(pdev
, dma_mask
);
9924 dev_err(&pdev
->dev
, PFX
"Unable to obtain 44 bit "
9925 "DMA for consistent allocations, "
9927 goto err_out_release_parent
;
9930 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
9931 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
9933 dev_err(&pdev
->dev
, PFX
"No usable DMA configuration, "
9935 goto err_out_release_parent
;
9939 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
9941 np
->regs
= pci_ioremap_bar(pdev
, 0);
9943 dev_err(&pdev
->dev
, PFX
"Cannot map device registers, "
9946 goto err_out_release_parent
;
9949 pci_set_master(pdev
);
9950 pci_save_state(pdev
);
9952 dev
->irq
= pdev
->irq
;
9954 niu_assign_netdev_ops(dev
);
9956 err
= niu_get_invariants(np
);
9959 dev_err(&pdev
->dev
, PFX
"Problem fetching invariants "
9960 "of chip, aborting.\n");
9961 goto err_out_iounmap
;
9964 err
= register_netdev(dev
);
9966 dev_err(&pdev
->dev
, PFX
"Cannot register net device, "
9968 goto err_out_iounmap
;
9971 pci_set_drvdata(pdev
, dev
);
9973 niu_device_announce(np
);
9983 err_out_release_parent
:
9990 pci_release_regions(pdev
);
9992 err_out_disable_pdev
:
9993 pci_disable_device(pdev
);
9994 pci_set_drvdata(pdev
, NULL
);
9999 static void __devexit
niu_pci_remove_one(struct pci_dev
*pdev
)
10001 struct net_device
*dev
= pci_get_drvdata(pdev
);
10004 struct niu
*np
= netdev_priv(dev
);
10006 unregister_netdev(dev
);
10014 niu_put_parent(np
);
10017 pci_release_regions(pdev
);
10018 pci_disable_device(pdev
);
10019 pci_set_drvdata(pdev
, NULL
);
10023 static int niu_suspend(struct pci_dev
*pdev
, pm_message_t state
)
10025 struct net_device
*dev
= pci_get_drvdata(pdev
);
10026 struct niu
*np
= netdev_priv(dev
);
10027 unsigned long flags
;
10029 if (!netif_running(dev
))
10032 flush_scheduled_work();
10033 niu_netif_stop(np
);
10035 del_timer_sync(&np
->timer
);
10037 spin_lock_irqsave(&np
->lock
, flags
);
10038 niu_enable_interrupts(np
, 0);
10039 spin_unlock_irqrestore(&np
->lock
, flags
);
10041 netif_device_detach(dev
);
10043 spin_lock_irqsave(&np
->lock
, flags
);
10045 spin_unlock_irqrestore(&np
->lock
, flags
);
10047 pci_save_state(pdev
);
10052 static int niu_resume(struct pci_dev
*pdev
)
10054 struct net_device
*dev
= pci_get_drvdata(pdev
);
10055 struct niu
*np
= netdev_priv(dev
);
10056 unsigned long flags
;
10059 if (!netif_running(dev
))
10062 pci_restore_state(pdev
);
10064 netif_device_attach(dev
);
10066 spin_lock_irqsave(&np
->lock
, flags
);
10068 err
= niu_init_hw(np
);
10070 np
->timer
.expires
= jiffies
+ HZ
;
10071 add_timer(&np
->timer
);
10072 niu_netif_start(np
);
10075 spin_unlock_irqrestore(&np
->lock
, flags
);
10080 static struct pci_driver niu_pci_driver
= {
10081 .name
= DRV_MODULE_NAME
,
10082 .id_table
= niu_pci_tbl
,
10083 .probe
= niu_pci_init_one
,
10084 .remove
= __devexit_p(niu_pci_remove_one
),
10085 .suspend
= niu_suspend
,
10086 .resume
= niu_resume
,
10089 #ifdef CONFIG_SPARC64
10090 static void *niu_phys_alloc_coherent(struct device
*dev
, size_t size
,
10091 u64
*dma_addr
, gfp_t flag
)
10093 unsigned long order
= get_order(size
);
10094 unsigned long page
= __get_free_pages(flag
, order
);
10098 memset((char *)page
, 0, PAGE_SIZE
<< order
);
10099 *dma_addr
= __pa(page
);
10101 return (void *) page
;
10104 static void niu_phys_free_coherent(struct device
*dev
, size_t size
,
10105 void *cpu_addr
, u64 handle
)
10107 unsigned long order
= get_order(size
);
10109 free_pages((unsigned long) cpu_addr
, order
);
10112 static u64
niu_phys_map_page(struct device
*dev
, struct page
*page
,
10113 unsigned long offset
, size_t size
,
10114 enum dma_data_direction direction
)
10116 return page_to_phys(page
) + offset
;
10119 static void niu_phys_unmap_page(struct device
*dev
, u64 dma_address
,
10120 size_t size
, enum dma_data_direction direction
)
10122 /* Nothing to do. */
10125 static u64
niu_phys_map_single(struct device
*dev
, void *cpu_addr
,
10127 enum dma_data_direction direction
)
10129 return __pa(cpu_addr
);
10132 static void niu_phys_unmap_single(struct device
*dev
, u64 dma_address
,
10134 enum dma_data_direction direction
)
10136 /* Nothing to do. */
10139 static const struct niu_ops niu_phys_ops
= {
10140 .alloc_coherent
= niu_phys_alloc_coherent
,
10141 .free_coherent
= niu_phys_free_coherent
,
10142 .map_page
= niu_phys_map_page
,
10143 .unmap_page
= niu_phys_unmap_page
,
10144 .map_single
= niu_phys_map_single
,
10145 .unmap_single
= niu_phys_unmap_single
,
10148 static unsigned long res_size(struct resource
*r
)
10150 return r
->end
- r
->start
+ 1UL;
10153 static int __devinit
niu_of_probe(struct of_device
*op
,
10154 const struct of_device_id
*match
)
10156 union niu_parent_id parent_id
;
10157 struct net_device
*dev
;
10162 niu_driver_version();
10164 reg
= of_get_property(op
->node
, "reg", NULL
);
10166 dev_err(&op
->dev
, PFX
"%s: No 'reg' property, aborting.\n",
10167 op
->node
->full_name
);
10171 dev
= niu_alloc_and_init(&op
->dev
, NULL
, op
,
10172 &niu_phys_ops
, reg
[0] & 0x1);
10177 np
= netdev_priv(dev
);
10179 memset(&parent_id
, 0, sizeof(parent_id
));
10180 parent_id
.of
= of_get_parent(op
->node
);
10182 np
->parent
= niu_get_parent(np
, &parent_id
,
10186 goto err_out_free_dev
;
10189 dev
->features
|= (NETIF_F_SG
| NETIF_F_HW_CSUM
);
10191 np
->regs
= of_ioremap(&op
->resource
[1], 0,
10192 res_size(&op
->resource
[1]),
10195 dev_err(&op
->dev
, PFX
"Cannot map device registers, "
10198 goto err_out_release_parent
;
10201 np
->vir_regs_1
= of_ioremap(&op
->resource
[2], 0,
10202 res_size(&op
->resource
[2]),
10204 if (!np
->vir_regs_1
) {
10205 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 1, "
10208 goto err_out_iounmap
;
10211 np
->vir_regs_2
= of_ioremap(&op
->resource
[3], 0,
10212 res_size(&op
->resource
[3]),
10214 if (!np
->vir_regs_2
) {
10215 dev_err(&op
->dev
, PFX
"Cannot map device vir registers 2, "
10218 goto err_out_iounmap
;
10221 niu_assign_netdev_ops(dev
);
10223 err
= niu_get_invariants(np
);
10225 if (err
!= -ENODEV
)
10226 dev_err(&op
->dev
, PFX
"Problem fetching invariants "
10227 "of chip, aborting.\n");
10228 goto err_out_iounmap
;
10231 err
= register_netdev(dev
);
10233 dev_err(&op
->dev
, PFX
"Cannot register net device, "
10235 goto err_out_iounmap
;
10238 dev_set_drvdata(&op
->dev
, dev
);
10240 niu_device_announce(np
);
10245 if (np
->vir_regs_1
) {
10246 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10247 res_size(&op
->resource
[2]));
10248 np
->vir_regs_1
= NULL
;
10251 if (np
->vir_regs_2
) {
10252 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10253 res_size(&op
->resource
[3]));
10254 np
->vir_regs_2
= NULL
;
10258 of_iounmap(&op
->resource
[1], np
->regs
,
10259 res_size(&op
->resource
[1]));
10263 err_out_release_parent
:
10264 niu_put_parent(np
);
10273 static int __devexit
niu_of_remove(struct of_device
*op
)
10275 struct net_device
*dev
= dev_get_drvdata(&op
->dev
);
10278 struct niu
*np
= netdev_priv(dev
);
10280 unregister_netdev(dev
);
10282 if (np
->vir_regs_1
) {
10283 of_iounmap(&op
->resource
[2], np
->vir_regs_1
,
10284 res_size(&op
->resource
[2]));
10285 np
->vir_regs_1
= NULL
;
10288 if (np
->vir_regs_2
) {
10289 of_iounmap(&op
->resource
[3], np
->vir_regs_2
,
10290 res_size(&op
->resource
[3]));
10291 np
->vir_regs_2
= NULL
;
10295 of_iounmap(&op
->resource
[1], np
->regs
,
10296 res_size(&op
->resource
[1]));
10302 niu_put_parent(np
);
10305 dev_set_drvdata(&op
->dev
, NULL
);
10310 static const struct of_device_id niu_match
[] = {
10313 .compatible
= "SUNW,niusl",
10317 MODULE_DEVICE_TABLE(of
, niu_match
);
10319 static struct of_platform_driver niu_of_driver
= {
10321 .match_table
= niu_match
,
10322 .probe
= niu_of_probe
,
10323 .remove
= __devexit_p(niu_of_remove
),
10326 #endif /* CONFIG_SPARC64 */
10328 static int __init
niu_init(void)
10332 BUILD_BUG_ON(PAGE_SIZE
< 4 * 1024);
10334 niu_debug
= netif_msg_init(debug
, NIU_MSG_DEFAULT
);
10336 #ifdef CONFIG_SPARC64
10337 err
= of_register_driver(&niu_of_driver
, &of_bus_type
);
10341 err
= pci_register_driver(&niu_pci_driver
);
10342 #ifdef CONFIG_SPARC64
10344 of_unregister_driver(&niu_of_driver
);
10351 static void __exit
niu_exit(void)
10353 pci_unregister_driver(&niu_pci_driver
);
10354 #ifdef CONFIG_SPARC64
10355 of_unregister_driver(&niu_of_driver
);
10359 module_init(niu_init
);
10360 module_exit(niu_exit
);