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drivers/net: const-ify ethtool_ops declarations
[deliverable/linux.git] / drivers / net / pcmcia / nmclan_cs.c
1 /* ----------------------------------------------------------------------------
2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9 Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16 Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19 References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47 -------------------------------------------------------------------------------
48 Driver Notes and Issues
49 -------------------------------------------------------------------------------
50
51 1. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
63 4. There is a bad slow-down problem in this driver.
64
65 5. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68 -------------------------------------------------------------------------------
69 History
70 -------------------------------------------------------------------------------
71 Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
96 95/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
100 95/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
103 95/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
105 95/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
109 95/05/10 rpao V0.07 Statistics.
110 95/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112 ---------------------------------------------------------------------------- */
113
114 #define DRV_NAME "nmclan_cs"
115 #define DRV_VERSION "0.16"
116
117
118 /* ----------------------------------------------------------------------------
119 Conditional Compilation Options
120 ---------------------------------------------------------------------------- */
121
122 #define MULTI_TX 0
123 #define RESET_ON_TIMEOUT 1
124 #define TX_INTERRUPTABLE 1
125 #define RESET_XILINX 0
126
127 /* ----------------------------------------------------------------------------
128 Include Files
129 ---------------------------------------------------------------------------- */
130
131 #include <linux/module.h>
132 #include <linux/kernel.h>
133 #include <linux/init.h>
134 #include <linux/ptrace.h>
135 #include <linux/slab.h>
136 #include <linux/string.h>
137 #include <linux/timer.h>
138 #include <linux/interrupt.h>
139 #include <linux/in.h>
140 #include <linux/delay.h>
141 #include <linux/ethtool.h>
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145 #include <linux/if_arp.h>
146 #include <linux/ioport.h>
147 #include <linux/bitops.h>
148
149 #include <pcmcia/cs_types.h>
150 #include <pcmcia/cs.h>
151 #include <pcmcia/cisreg.h>
152 #include <pcmcia/cistpl.h>
153 #include <pcmcia/ds.h>
154
155 #include <asm/uaccess.h>
156 #include <asm/io.h>
157 #include <asm/system.h>
158
159 /* ----------------------------------------------------------------------------
160 Defines
161 ---------------------------------------------------------------------------- */
162
163 #define ETHER_ADDR_LEN ETH_ALEN
164 /* 6 bytes in an Ethernet Address */
165 #define MACE_LADRF_LEN 8
166 /* 8 bytes in Logical Address Filter */
167
168 /* Loop Control Defines */
169 #define MACE_MAX_IR_ITERATIONS 10
170 #define MACE_MAX_RX_ITERATIONS 12
171 /*
172 TBD: Dean brought this up, and I assumed the hardware would
173 handle it:
174
175 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
176 non-zero when the isr exits. We may not get another interrupt
177 to process the remaining packets for some time.
178 */
179
180 /*
181 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
182 which manages the interface between the MACE and the PCMCIA bus. It
183 also includes buffer management for the 32K x 8 SRAM to control up to
184 four transmit and 12 receive frames at a time.
185 */
186 #define AM2150_MAX_TX_FRAMES 4
187 #define AM2150_MAX_RX_FRAMES 12
188
189 /* Am2150 Ethernet Card I/O Mapping */
190 #define AM2150_RCV 0x00
191 #define AM2150_XMT 0x04
192 #define AM2150_XMT_SKIP 0x09
193 #define AM2150_RCV_NEXT 0x0A
194 #define AM2150_RCV_FRAME_COUNT 0x0B
195 #define AM2150_MACE_BANK 0x0C
196 #define AM2150_MACE_BASE 0x10
197
198 /* MACE Registers */
199 #define MACE_RCVFIFO 0
200 #define MACE_XMTFIFO 1
201 #define MACE_XMTFC 2
202 #define MACE_XMTFS 3
203 #define MACE_XMTRC 4
204 #define MACE_RCVFC 5
205 #define MACE_RCVFS 6
206 #define MACE_FIFOFC 7
207 #define MACE_IR 8
208 #define MACE_IMR 9
209 #define MACE_PR 10
210 #define MACE_BIUCC 11
211 #define MACE_FIFOCC 12
212 #define MACE_MACCC 13
213 #define MACE_PLSCC 14
214 #define MACE_PHYCC 15
215 #define MACE_CHIPIDL 16
216 #define MACE_CHIPIDH 17
217 #define MACE_IAC 18
218 /* Reserved */
219 #define MACE_LADRF 20
220 #define MACE_PADR 21
221 /* Reserved */
222 /* Reserved */
223 #define MACE_MPC 24
224 /* Reserved */
225 #define MACE_RNTPC 26
226 #define MACE_RCVCC 27
227 /* Reserved */
228 #define MACE_UTR 29
229 #define MACE_RTR1 30
230 #define MACE_RTR2 31
231
232 /* MACE Bit Masks */
233 #define MACE_XMTRC_EXDEF 0x80
234 #define MACE_XMTRC_XMTRC 0x0F
235
236 #define MACE_XMTFS_XMTSV 0x80
237 #define MACE_XMTFS_UFLO 0x40
238 #define MACE_XMTFS_LCOL 0x20
239 #define MACE_XMTFS_MORE 0x10
240 #define MACE_XMTFS_ONE 0x08
241 #define MACE_XMTFS_DEFER 0x04
242 #define MACE_XMTFS_LCAR 0x02
243 #define MACE_XMTFS_RTRY 0x01
244
245 #define MACE_RCVFS_RCVSTS 0xF000
246 #define MACE_RCVFS_OFLO 0x8000
247 #define MACE_RCVFS_CLSN 0x4000
248 #define MACE_RCVFS_FRAM 0x2000
249 #define MACE_RCVFS_FCS 0x1000
250
251 #define MACE_FIFOFC_RCVFC 0xF0
252 #define MACE_FIFOFC_XMTFC 0x0F
253
254 #define MACE_IR_JAB 0x80
255 #define MACE_IR_BABL 0x40
256 #define MACE_IR_CERR 0x20
257 #define MACE_IR_RCVCCO 0x10
258 #define MACE_IR_RNTPCO 0x08
259 #define MACE_IR_MPCO 0x04
260 #define MACE_IR_RCVINT 0x02
261 #define MACE_IR_XMTINT 0x01
262
263 #define MACE_MACCC_PROM 0x80
264 #define MACE_MACCC_DXMT2PD 0x40
265 #define MACE_MACCC_EMBA 0x20
266 #define MACE_MACCC_RESERVED 0x10
267 #define MACE_MACCC_DRCVPA 0x08
268 #define MACE_MACCC_DRCVBC 0x04
269 #define MACE_MACCC_ENXMT 0x02
270 #define MACE_MACCC_ENRCV 0x01
271
272 #define MACE_PHYCC_LNKFL 0x80
273 #define MACE_PHYCC_DLNKTST 0x40
274 #define MACE_PHYCC_REVPOL 0x20
275 #define MACE_PHYCC_DAPC 0x10
276 #define MACE_PHYCC_LRT 0x08
277 #define MACE_PHYCC_ASEL 0x04
278 #define MACE_PHYCC_RWAKE 0x02
279 #define MACE_PHYCC_AWAKE 0x01
280
281 #define MACE_IAC_ADDRCHG 0x80
282 #define MACE_IAC_PHYADDR 0x04
283 #define MACE_IAC_LOGADDR 0x02
284
285 #define MACE_UTR_RTRE 0x80
286 #define MACE_UTR_RTRD 0x40
287 #define MACE_UTR_RPA 0x20
288 #define MACE_UTR_FCOLL 0x10
289 #define MACE_UTR_RCVFCSE 0x08
290 #define MACE_UTR_LOOP_INCL_MENDEC 0x06
291 #define MACE_UTR_LOOP_NO_MENDEC 0x04
292 #define MACE_UTR_LOOP_EXTERNAL 0x02
293 #define MACE_UTR_LOOP_NONE 0x00
294 #define MACE_UTR_RESERVED 0x01
295
296 /* Switch MACE register bank (only 0 and 1 are valid) */
297 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
298
299 #define MACE_IMR_DEFAULT \
300 (0xFF - \
301 ( \
302 MACE_IR_CERR | \
303 MACE_IR_RCVCCO | \
304 MACE_IR_RNTPCO | \
305 MACE_IR_MPCO | \
306 MACE_IR_RCVINT | \
307 MACE_IR_XMTINT \
308 ) \
309 )
310 #undef MACE_IMR_DEFAULT
311 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
312
313 #define TX_TIMEOUT ((400*HZ)/1000)
314
315 /* ----------------------------------------------------------------------------
316 Type Definitions
317 ---------------------------------------------------------------------------- */
318
319 typedef struct _mace_statistics {
320 /* MACE_XMTFS */
321 int xmtsv;
322 int uflo;
323 int lcol;
324 int more;
325 int one;
326 int defer;
327 int lcar;
328 int rtry;
329
330 /* MACE_XMTRC */
331 int exdef;
332 int xmtrc;
333
334 /* RFS1--Receive Status (RCVSTS) */
335 int oflo;
336 int clsn;
337 int fram;
338 int fcs;
339
340 /* RFS2--Runt Packet Count (RNTPC) */
341 int rfs_rntpc;
342
343 /* RFS3--Receive Collision Count (RCVCC) */
344 int rfs_rcvcc;
345
346 /* MACE_IR */
347 int jab;
348 int babl;
349 int cerr;
350 int rcvcco;
351 int rntpco;
352 int mpco;
353
354 /* MACE_MPC */
355 int mpc;
356
357 /* MACE_RNTPC */
358 int rntpc;
359
360 /* MACE_RCVCC */
361 int rcvcc;
362 } mace_statistics;
363
364 typedef struct _mace_private {
365 struct pcmcia_device *p_dev;
366 dev_node_t node;
367 struct net_device_stats linux_stats; /* Linux statistics counters */
368 mace_statistics mace_stats; /* MACE chip statistics counters */
369
370 /* restore_multicast_list() state variables */
371 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
372 int multicast_num_addrs;
373
374 char tx_free_frames; /* Number of free transmit frame buffers */
375 char tx_irq_disabled; /* MACE TX interrupt disabled */
376
377 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
378 } mace_private;
379
380 /* ----------------------------------------------------------------------------
381 Private Global Variables
382 ---------------------------------------------------------------------------- */
383
384 #ifdef PCMCIA_DEBUG
385 static char rcsid[] =
386 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
387 static char *version =
388 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
389 #endif
390
391 static const char *if_names[]={
392 "Auto", "10baseT", "BNC",
393 };
394
395 /* ----------------------------------------------------------------------------
396 Parameters
397 These are the parameters that can be set during loading with
398 'insmod'.
399 ---------------------------------------------------------------------------- */
400
401 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
402 MODULE_LICENSE("GPL");
403
404 #define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
405
406 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
407 INT_MODULE_PARM(if_port, 0);
408
409 #ifdef PCMCIA_DEBUG
410 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
411 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
412 #else
413 #define DEBUG(n, args...)
414 #endif
415
416 /* ----------------------------------------------------------------------------
417 Function Prototypes
418 ---------------------------------------------------------------------------- */
419
420 static int nmclan_config(struct pcmcia_device *link);
421 static void nmclan_release(struct pcmcia_device *link);
422
423 static void nmclan_reset(struct net_device *dev);
424 static int mace_config(struct net_device *dev, struct ifmap *map);
425 static int mace_open(struct net_device *dev);
426 static int mace_close(struct net_device *dev);
427 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
428 static void mace_tx_timeout(struct net_device *dev);
429 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
430 static struct net_device_stats *mace_get_stats(struct net_device *dev);
431 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
432 static void restore_multicast_list(struct net_device *dev);
433 static void set_multicast_list(struct net_device *dev);
434 static const struct ethtool_ops netdev_ethtool_ops;
435
436
437 static void nmclan_detach(struct pcmcia_device *p_dev);
438
439 /* ----------------------------------------------------------------------------
440 nmclan_attach
441 Creates an "instance" of the driver, allocating local data
442 structures for one device. The device is registered with Card
443 Services.
444 ---------------------------------------------------------------------------- */
445
446 static int nmclan_probe(struct pcmcia_device *link)
447 {
448 mace_private *lp;
449 struct net_device *dev;
450
451 DEBUG(0, "nmclan_attach()\n");
452 DEBUG(1, "%s\n", rcsid);
453
454 /* Create new ethernet device */
455 dev = alloc_etherdev(sizeof(mace_private));
456 if (!dev)
457 return -ENOMEM;
458 lp = netdev_priv(dev);
459 lp->p_dev = link;
460 link->priv = dev;
461
462 spin_lock_init(&lp->bank_lock);
463 link->io.NumPorts1 = 32;
464 link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
465 link->io.IOAddrLines = 5;
466 link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
467 link->irq.IRQInfo1 = IRQ_LEVEL_ID;
468 link->irq.Handler = &mace_interrupt;
469 link->irq.Instance = dev;
470 link->conf.Attributes = CONF_ENABLE_IRQ;
471 link->conf.IntType = INT_MEMORY_AND_IO;
472 link->conf.ConfigIndex = 1;
473 link->conf.Present = PRESENT_OPTION;
474
475 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
476
477 SET_MODULE_OWNER(dev);
478 dev->hard_start_xmit = &mace_start_xmit;
479 dev->set_config = &mace_config;
480 dev->get_stats = &mace_get_stats;
481 dev->set_multicast_list = &set_multicast_list;
482 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
483 dev->open = &mace_open;
484 dev->stop = &mace_close;
485 #ifdef HAVE_TX_TIMEOUT
486 dev->tx_timeout = mace_tx_timeout;
487 dev->watchdog_timeo = TX_TIMEOUT;
488 #endif
489
490 return nmclan_config(link);
491 } /* nmclan_attach */
492
493 /* ----------------------------------------------------------------------------
494 nmclan_detach
495 This deletes a driver "instance". The device is de-registered
496 with Card Services. If it has been released, all local data
497 structures are freed. Otherwise, the structures will be freed
498 when the device is released.
499 ---------------------------------------------------------------------------- */
500
501 static void nmclan_detach(struct pcmcia_device *link)
502 {
503 struct net_device *dev = link->priv;
504
505 DEBUG(0, "nmclan_detach(0x%p)\n", link);
506
507 if (link->dev_node)
508 unregister_netdev(dev);
509
510 nmclan_release(link);
511
512 free_netdev(dev);
513 } /* nmclan_detach */
514
515 /* ----------------------------------------------------------------------------
516 mace_read
517 Reads a MACE register. This is bank independent; however, the
518 caller must ensure that this call is not interruptable. We are
519 assuming that during normal operation, the MACE is always in
520 bank 0.
521 ---------------------------------------------------------------------------- */
522 static int mace_read(mace_private *lp, kio_addr_t ioaddr, int reg)
523 {
524 int data = 0xFF;
525 unsigned long flags;
526
527 switch (reg >> 4) {
528 case 0: /* register 0-15 */
529 data = inb(ioaddr + AM2150_MACE_BASE + reg);
530 break;
531 case 1: /* register 16-31 */
532 spin_lock_irqsave(&lp->bank_lock, flags);
533 MACEBANK(1);
534 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
535 MACEBANK(0);
536 spin_unlock_irqrestore(&lp->bank_lock, flags);
537 break;
538 }
539 return (data & 0xFF);
540 } /* mace_read */
541
542 /* ----------------------------------------------------------------------------
543 mace_write
544 Writes to a MACE register. This is bank independent; however,
545 the caller must ensure that this call is not interruptable. We
546 are assuming that during normal operation, the MACE is always in
547 bank 0.
548 ---------------------------------------------------------------------------- */
549 static void mace_write(mace_private *lp, kio_addr_t ioaddr, int reg, int data)
550 {
551 unsigned long flags;
552
553 switch (reg >> 4) {
554 case 0: /* register 0-15 */
555 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
556 break;
557 case 1: /* register 16-31 */
558 spin_lock_irqsave(&lp->bank_lock, flags);
559 MACEBANK(1);
560 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
561 MACEBANK(0);
562 spin_unlock_irqrestore(&lp->bank_lock, flags);
563 break;
564 }
565 } /* mace_write */
566
567 /* ----------------------------------------------------------------------------
568 mace_init
569 Resets the MACE chip.
570 ---------------------------------------------------------------------------- */
571 static int mace_init(mace_private *lp, kio_addr_t ioaddr, char *enet_addr)
572 {
573 int i;
574 int ct = 0;
575
576 /* MACE Software reset */
577 mace_write(lp, ioaddr, MACE_BIUCC, 1);
578 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
579 /* Wait for reset bit to be cleared automatically after <= 200ns */;
580 if(++ct > 500)
581 {
582 printk(KERN_ERR "mace: reset failed, card removed ?\n");
583 return -1;
584 }
585 udelay(1);
586 }
587 mace_write(lp, ioaddr, MACE_BIUCC, 0);
588
589 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
590 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
591
592 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
593 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
594
595 /*
596 * Bit 2-1 PORTSEL[1-0] Port Select.
597 * 00 AUI/10Base-2
598 * 01 10Base-T
599 * 10 DAI Port (reserved in Am2150)
600 * 11 GPSI
601 * For this card, only the first two are valid.
602 * So, PLSCC should be set to
603 * 0x00 for 10Base-2
604 * 0x02 for 10Base-T
605 * Or just set ASEL in PHYCC below!
606 */
607 switch (if_port) {
608 case 1:
609 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
610 break;
611 case 2:
612 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
613 break;
614 default:
615 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
616 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
617 and the MACE device will automatically select the operating media
618 interface port. */
619 break;
620 }
621
622 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
623 /* Poll ADDRCHG bit */
624 ct = 0;
625 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
626 {
627 if(++ ct > 500)
628 {
629 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
630 return -1;
631 }
632 }
633 /* Set PADR register */
634 for (i = 0; i < ETHER_ADDR_LEN; i++)
635 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
636
637 /* MAC Configuration Control Register should be written last */
638 /* Let set_multicast_list set this. */
639 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
640 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
641 return 0;
642 } /* mace_init */
643
644 /* ----------------------------------------------------------------------------
645 nmclan_config
646 This routine is scheduled to run after a CARD_INSERTION event
647 is received, to configure the PCMCIA socket, and to make the
648 ethernet device available to the system.
649 ---------------------------------------------------------------------------- */
650
651 #define CS_CHECK(fn, ret) \
652 do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
653
654 static int nmclan_config(struct pcmcia_device *link)
655 {
656 struct net_device *dev = link->priv;
657 mace_private *lp = netdev_priv(dev);
658 tuple_t tuple;
659 cisparse_t parse;
660 u_char buf[64];
661 int i, last_ret, last_fn;
662 kio_addr_t ioaddr;
663
664 DEBUG(0, "nmclan_config(0x%p)\n", link);
665
666 tuple.Attributes = 0;
667 tuple.TupleData = buf;
668 tuple.TupleDataMax = 64;
669 tuple.TupleOffset = 0;
670 tuple.DesiredTuple = CISTPL_CONFIG;
671 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
672 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
673 CS_CHECK(ParseTuple, pcmcia_parse_tuple(link, &tuple, &parse));
674 link->conf.ConfigBase = parse.config.base;
675
676 CS_CHECK(RequestIO, pcmcia_request_io(link, &link->io));
677 CS_CHECK(RequestIRQ, pcmcia_request_irq(link, &link->irq));
678 CS_CHECK(RequestConfiguration, pcmcia_request_configuration(link, &link->conf));
679 dev->irq = link->irq.AssignedIRQ;
680 dev->base_addr = link->io.BasePort1;
681
682 ioaddr = dev->base_addr;
683
684 /* Read the ethernet address from the CIS. */
685 tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
686 tuple.TupleData = buf;
687 tuple.TupleDataMax = 64;
688 tuple.TupleOffset = 0;
689 CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(link, &tuple));
690 CS_CHECK(GetTupleData, pcmcia_get_tuple_data(link, &tuple));
691 memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
692
693 /* Verify configuration by reading the MACE ID. */
694 {
695 char sig[2];
696
697 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
698 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
699 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
700 DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
701 sig[0], sig[1]);
702 } else {
703 printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
704 " be 0x40 0x?9\n", sig[0], sig[1]);
705 return -ENODEV;
706 }
707 }
708
709 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
710 goto failed;
711
712 /* The if_port symbol can be set when the module is loaded */
713 if (if_port <= 2)
714 dev->if_port = if_port;
715 else
716 printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
717
718 link->dev_node = &lp->node;
719 SET_NETDEV_DEV(dev, &handle_to_dev(link));
720
721 i = register_netdev(dev);
722 if (i != 0) {
723 printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
724 link->dev_node = NULL;
725 goto failed;
726 }
727
728 strcpy(lp->node.dev_name, dev->name);
729
730 printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
731 dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
732 for (i = 0; i < 6; i++)
733 printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
734 return 0;
735
736 cs_failed:
737 cs_error(link, last_fn, last_ret);
738 failed:
739 nmclan_release(link);
740 return -ENODEV;
741 } /* nmclan_config */
742
743 /* ----------------------------------------------------------------------------
744 nmclan_release
745 After a card is removed, nmclan_release() will unregister the
746 net device, and release the PCMCIA configuration. If the device
747 is still open, this will be postponed until it is closed.
748 ---------------------------------------------------------------------------- */
749 static void nmclan_release(struct pcmcia_device *link)
750 {
751 DEBUG(0, "nmclan_release(0x%p)\n", link);
752 pcmcia_disable_device(link);
753 }
754
755 static int nmclan_suspend(struct pcmcia_device *link)
756 {
757 struct net_device *dev = link->priv;
758
759 if (link->open)
760 netif_device_detach(dev);
761
762 return 0;
763 }
764
765 static int nmclan_resume(struct pcmcia_device *link)
766 {
767 struct net_device *dev = link->priv;
768
769 if (link->open) {
770 nmclan_reset(dev);
771 netif_device_attach(dev);
772 }
773
774 return 0;
775 }
776
777
778 /* ----------------------------------------------------------------------------
779 nmclan_reset
780 Reset and restore all of the Xilinx and MACE registers.
781 ---------------------------------------------------------------------------- */
782 static void nmclan_reset(struct net_device *dev)
783 {
784 mace_private *lp = netdev_priv(dev);
785
786 #if RESET_XILINX
787 struct pcmcia_device *link = &lp->link;
788 conf_reg_t reg;
789 u_long OrigCorValue;
790
791 /* Save original COR value */
792 reg.Function = 0;
793 reg.Action = CS_READ;
794 reg.Offset = CISREG_COR;
795 reg.Value = 0;
796 pcmcia_access_configuration_register(link, &reg);
797 OrigCorValue = reg.Value;
798
799 /* Reset Xilinx */
800 reg.Action = CS_WRITE;
801 reg.Offset = CISREG_COR;
802 DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
803 OrigCorValue);
804 reg.Value = COR_SOFT_RESET;
805 pcmcia_access_configuration_register(link, &reg);
806 /* Need to wait for 20 ms for PCMCIA to finish reset. */
807
808 /* Restore original COR configuration index */
809 reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
810 pcmcia_access_configuration_register(link, &reg);
811 /* Xilinx is now completely reset along with the MACE chip. */
812 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
813
814 #endif /* #if RESET_XILINX */
815
816 /* Xilinx is now completely reset along with the MACE chip. */
817 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
818
819 /* Reinitialize the MACE chip for operation. */
820 mace_init(lp, dev->base_addr, dev->dev_addr);
821 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
822
823 /* Restore the multicast list and enable TX and RX. */
824 restore_multicast_list(dev);
825 } /* nmclan_reset */
826
827 /* ----------------------------------------------------------------------------
828 mace_config
829 [Someone tell me what this is supposed to do? Is if_port a defined
830 standard? If so, there should be defines to indicate 1=10Base-T,
831 2=10Base-2, etc. including limited automatic detection.]
832 ---------------------------------------------------------------------------- */
833 static int mace_config(struct net_device *dev, struct ifmap *map)
834 {
835 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
836 if (map->port <= 2) {
837 dev->if_port = map->port;
838 printk(KERN_INFO "%s: switched to %s port\n", dev->name,
839 if_names[dev->if_port]);
840 } else
841 return -EINVAL;
842 }
843 return 0;
844 } /* mace_config */
845
846 /* ----------------------------------------------------------------------------
847 mace_open
848 Open device driver.
849 ---------------------------------------------------------------------------- */
850 static int mace_open(struct net_device *dev)
851 {
852 kio_addr_t ioaddr = dev->base_addr;
853 mace_private *lp = netdev_priv(dev);
854 struct pcmcia_device *link = lp->p_dev;
855
856 if (!pcmcia_dev_present(link))
857 return -ENODEV;
858
859 link->open++;
860
861 MACEBANK(0);
862
863 netif_start_queue(dev);
864 nmclan_reset(dev);
865
866 return 0; /* Always succeed */
867 } /* mace_open */
868
869 /* ----------------------------------------------------------------------------
870 mace_close
871 Closes device driver.
872 ---------------------------------------------------------------------------- */
873 static int mace_close(struct net_device *dev)
874 {
875 kio_addr_t ioaddr = dev->base_addr;
876 mace_private *lp = netdev_priv(dev);
877 struct pcmcia_device *link = lp->p_dev;
878
879 DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
880
881 /* Mask off all interrupts from the MACE chip. */
882 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
883
884 link->open--;
885 netif_stop_queue(dev);
886
887 return 0;
888 } /* mace_close */
889
890 static void netdev_get_drvinfo(struct net_device *dev,
891 struct ethtool_drvinfo *info)
892 {
893 strcpy(info->driver, DRV_NAME);
894 strcpy(info->version, DRV_VERSION);
895 sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
896 }
897
898 #ifdef PCMCIA_DEBUG
899 static u32 netdev_get_msglevel(struct net_device *dev)
900 {
901 return pc_debug;
902 }
903
904 static void netdev_set_msglevel(struct net_device *dev, u32 level)
905 {
906 pc_debug = level;
907 }
908 #endif /* PCMCIA_DEBUG */
909
910 static const struct ethtool_ops netdev_ethtool_ops = {
911 .get_drvinfo = netdev_get_drvinfo,
912 #ifdef PCMCIA_DEBUG
913 .get_msglevel = netdev_get_msglevel,
914 .set_msglevel = netdev_set_msglevel,
915 #endif /* PCMCIA_DEBUG */
916 };
917
918 /* ----------------------------------------------------------------------------
919 mace_start_xmit
920 This routine begins the packet transmit function. When completed,
921 it will generate a transmit interrupt.
922
923 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
924 returns 0, the "packet is now solely the responsibility of the
925 driver." If _start_xmit returns non-zero, the "transmission
926 failed, put skb back into a list."
927 ---------------------------------------------------------------------------- */
928
929 static void mace_tx_timeout(struct net_device *dev)
930 {
931 mace_private *lp = netdev_priv(dev);
932 struct pcmcia_device *link = lp->p_dev;
933
934 printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
935 #if RESET_ON_TIMEOUT
936 printk("resetting card\n");
937 pcmcia_reset_card(link, NULL);
938 #else /* #if RESET_ON_TIMEOUT */
939 printk("NOT resetting card\n");
940 #endif /* #if RESET_ON_TIMEOUT */
941 dev->trans_start = jiffies;
942 netif_wake_queue(dev);
943 }
944
945 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
946 {
947 mace_private *lp = netdev_priv(dev);
948 kio_addr_t ioaddr = dev->base_addr;
949
950 netif_stop_queue(dev);
951
952 DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
953 dev->name, (long)skb->len);
954
955 #if (!TX_INTERRUPTABLE)
956 /* Disable MACE TX interrupts. */
957 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
958 ioaddr + AM2150_MACE_BASE + MACE_IMR);
959 lp->tx_irq_disabled=1;
960 #endif /* #if (!TX_INTERRUPTABLE) */
961
962 {
963 /* This block must not be interrupted by another transmit request!
964 mace_tx_timeout will take care of timer-based retransmissions from
965 the upper layers. The interrupt handler is guaranteed never to
966 service a transmit interrupt while we are in here.
967 */
968
969 lp->linux_stats.tx_bytes += skb->len;
970 lp->tx_free_frames--;
971
972 /* WARNING: Write the _exact_ number of bytes written in the header! */
973 /* Put out the word header [must be an outw()] . . . */
974 outw(skb->len, ioaddr + AM2150_XMT);
975 /* . . . and the packet [may be any combination of outw() and outb()] */
976 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
977 if (skb->len & 1) {
978 /* Odd byte transfer */
979 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
980 }
981
982 dev->trans_start = jiffies;
983
984 #if MULTI_TX
985 if (lp->tx_free_frames > 0)
986 netif_start_queue(dev);
987 #endif /* #if MULTI_TX */
988 }
989
990 #if (!TX_INTERRUPTABLE)
991 /* Re-enable MACE TX interrupts. */
992 lp->tx_irq_disabled=0;
993 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
994 #endif /* #if (!TX_INTERRUPTABLE) */
995
996 dev_kfree_skb(skb);
997
998 return 0;
999 } /* mace_start_xmit */
1000
1001 /* ----------------------------------------------------------------------------
1002 mace_interrupt
1003 The interrupt handler.
1004 ---------------------------------------------------------------------------- */
1005 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1006 {
1007 struct net_device *dev = (struct net_device *) dev_id;
1008 mace_private *lp = netdev_priv(dev);
1009 kio_addr_t ioaddr = dev->base_addr;
1010 int status;
1011 int IntrCnt = MACE_MAX_IR_ITERATIONS;
1012
1013 if (dev == NULL) {
1014 DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1015 irq);
1016 return IRQ_NONE;
1017 }
1018
1019 if (lp->tx_irq_disabled) {
1020 printk(
1021 (lp->tx_irq_disabled?
1022 KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1023 "[isr=%02X, imr=%02X]\n":
1024 KERN_NOTICE "%s: Re-entering the interrupt handler "
1025 "[isr=%02X, imr=%02X]\n"),
1026 dev->name,
1027 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1028 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1029 );
1030 /* WARNING: MACE_IR has been read! */
1031 return IRQ_NONE;
1032 }
1033
1034 if (!netif_device_present(dev)) {
1035 DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1036 return IRQ_NONE;
1037 }
1038
1039 do {
1040 /* WARNING: MACE_IR is a READ/CLEAR port! */
1041 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1042
1043 DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1044
1045 if (status & MACE_IR_RCVINT) {
1046 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1047 }
1048
1049 if (status & MACE_IR_XMTINT) {
1050 unsigned char fifofc;
1051 unsigned char xmtrc;
1052 unsigned char xmtfs;
1053
1054 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1055 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1056 lp->linux_stats.tx_errors++;
1057 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1058 }
1059
1060 /* Transmit Retry Count (XMTRC, reg 4) */
1061 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1062 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1063 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1064
1065 if (
1066 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1067 MACE_XMTFS_XMTSV /* Transmit Status Valid */
1068 ) {
1069 lp->mace_stats.xmtsv++;
1070
1071 if (xmtfs & ~MACE_XMTFS_XMTSV) {
1072 if (xmtfs & MACE_XMTFS_UFLO) {
1073 /* Underflow. Indicates that the Transmit FIFO emptied before
1074 the end of frame was reached. */
1075 lp->mace_stats.uflo++;
1076 }
1077 if (xmtfs & MACE_XMTFS_LCOL) {
1078 /* Late Collision */
1079 lp->mace_stats.lcol++;
1080 }
1081 if (xmtfs & MACE_XMTFS_MORE) {
1082 /* MORE than one retry was needed */
1083 lp->mace_stats.more++;
1084 }
1085 if (xmtfs & MACE_XMTFS_ONE) {
1086 /* Exactly ONE retry occurred */
1087 lp->mace_stats.one++;
1088 }
1089 if (xmtfs & MACE_XMTFS_DEFER) {
1090 /* Transmission was defered */
1091 lp->mace_stats.defer++;
1092 }
1093 if (xmtfs & MACE_XMTFS_LCAR) {
1094 /* Loss of carrier */
1095 lp->mace_stats.lcar++;
1096 }
1097 if (xmtfs & MACE_XMTFS_RTRY) {
1098 /* Retry error: transmit aborted after 16 attempts */
1099 lp->mace_stats.rtry++;
1100 }
1101 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1102
1103 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1104
1105 lp->linux_stats.tx_packets++;
1106 lp->tx_free_frames++;
1107 netif_wake_queue(dev);
1108 } /* if (status & MACE_IR_XMTINT) */
1109
1110 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1111 if (status & MACE_IR_JAB) {
1112 /* Jabber Error. Excessive transmit duration (20-150ms). */
1113 lp->mace_stats.jab++;
1114 }
1115 if (status & MACE_IR_BABL) {
1116 /* Babble Error. >1518 bytes transmitted. */
1117 lp->mace_stats.babl++;
1118 }
1119 if (status & MACE_IR_CERR) {
1120 /* Collision Error. CERR indicates the absence of the
1121 Signal Quality Error Test message after a packet
1122 transmission. */
1123 lp->mace_stats.cerr++;
1124 }
1125 if (status & MACE_IR_RCVCCO) {
1126 /* Receive Collision Count Overflow; */
1127 lp->mace_stats.rcvcco++;
1128 }
1129 if (status & MACE_IR_RNTPCO) {
1130 /* Runt Packet Count Overflow */
1131 lp->mace_stats.rntpco++;
1132 }
1133 if (status & MACE_IR_MPCO) {
1134 /* Missed Packet Count Overflow */
1135 lp->mace_stats.mpco++;
1136 }
1137 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1138
1139 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1140
1141 return IRQ_HANDLED;
1142 } /* mace_interrupt */
1143
1144 /* ----------------------------------------------------------------------------
1145 mace_rx
1146 Receives packets.
1147 ---------------------------------------------------------------------------- */
1148 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1149 {
1150 mace_private *lp = netdev_priv(dev);
1151 kio_addr_t ioaddr = dev->base_addr;
1152 unsigned char rx_framecnt;
1153 unsigned short rx_status;
1154
1155 while (
1156 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1157 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1158 (RxCnt--)
1159 ) {
1160 rx_status = inw(ioaddr + AM2150_RCV);
1161
1162 DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1163 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1164
1165 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1166 lp->linux_stats.rx_errors++;
1167 if (rx_status & MACE_RCVFS_OFLO) {
1168 lp->mace_stats.oflo++;
1169 }
1170 if (rx_status & MACE_RCVFS_CLSN) {
1171 lp->mace_stats.clsn++;
1172 }
1173 if (rx_status & MACE_RCVFS_FRAM) {
1174 lp->mace_stats.fram++;
1175 }
1176 if (rx_status & MACE_RCVFS_FCS) {
1177 lp->mace_stats.fcs++;
1178 }
1179 } else {
1180 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1181 /* Auto Strip is off, always subtract 4 */
1182 struct sk_buff *skb;
1183
1184 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1185 /* runt packet count */
1186 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1187 /* rcv collision count */
1188
1189 DEBUG(3, " receiving packet size 0x%X rx_status"
1190 " 0x%X.\n", pkt_len, rx_status);
1191
1192 skb = dev_alloc_skb(pkt_len+2);
1193
1194 if (skb != NULL) {
1195 skb->dev = dev;
1196
1197 skb_reserve(skb, 2);
1198 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1199 if (pkt_len & 1)
1200 *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1201 skb->protocol = eth_type_trans(skb, dev);
1202
1203 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1204
1205 dev->last_rx = jiffies;
1206 lp->linux_stats.rx_packets++;
1207 lp->linux_stats.rx_bytes += pkt_len;
1208 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1209 continue;
1210 } else {
1211 DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1212 " %d.\n", dev->name, pkt_len);
1213 lp->linux_stats.rx_dropped++;
1214 }
1215 }
1216 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1217 } /* while */
1218
1219 return 0;
1220 } /* mace_rx */
1221
1222 /* ----------------------------------------------------------------------------
1223 pr_linux_stats
1224 ---------------------------------------------------------------------------- */
1225 static void pr_linux_stats(struct net_device_stats *pstats)
1226 {
1227 DEBUG(2, "pr_linux_stats\n");
1228 DEBUG(2, " rx_packets=%-7ld tx_packets=%ld\n",
1229 (long)pstats->rx_packets, (long)pstats->tx_packets);
1230 DEBUG(2, " rx_errors=%-7ld tx_errors=%ld\n",
1231 (long)pstats->rx_errors, (long)pstats->tx_errors);
1232 DEBUG(2, " rx_dropped=%-7ld tx_dropped=%ld\n",
1233 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1234 DEBUG(2, " multicast=%-7ld collisions=%ld\n",
1235 (long)pstats->multicast, (long)pstats->collisions);
1236
1237 DEBUG(2, " rx_length_errors=%-7ld rx_over_errors=%ld\n",
1238 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1239 DEBUG(2, " rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1240 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1241 DEBUG(2, " rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1242 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1243
1244 DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1245 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1246 DEBUG(2, " tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1247 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1248 DEBUG(2, " tx_window_errors=%ld\n",
1249 (long)pstats->tx_window_errors);
1250 } /* pr_linux_stats */
1251
1252 /* ----------------------------------------------------------------------------
1253 pr_mace_stats
1254 ---------------------------------------------------------------------------- */
1255 static void pr_mace_stats(mace_statistics *pstats)
1256 {
1257 DEBUG(2, "pr_mace_stats\n");
1258
1259 DEBUG(2, " xmtsv=%-7d uflo=%d\n",
1260 pstats->xmtsv, pstats->uflo);
1261 DEBUG(2, " lcol=%-7d more=%d\n",
1262 pstats->lcol, pstats->more);
1263 DEBUG(2, " one=%-7d defer=%d\n",
1264 pstats->one, pstats->defer);
1265 DEBUG(2, " lcar=%-7d rtry=%d\n",
1266 pstats->lcar, pstats->rtry);
1267
1268 /* MACE_XMTRC */
1269 DEBUG(2, " exdef=%-7d xmtrc=%d\n",
1270 pstats->exdef, pstats->xmtrc);
1271
1272 /* RFS1--Receive Status (RCVSTS) */
1273 DEBUG(2, " oflo=%-7d clsn=%d\n",
1274 pstats->oflo, pstats->clsn);
1275 DEBUG(2, " fram=%-7d fcs=%d\n",
1276 pstats->fram, pstats->fcs);
1277
1278 /* RFS2--Runt Packet Count (RNTPC) */
1279 /* RFS3--Receive Collision Count (RCVCC) */
1280 DEBUG(2, " rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1281 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1282
1283 /* MACE_IR */
1284 DEBUG(2, " jab=%-7d babl=%d\n",
1285 pstats->jab, pstats->babl);
1286 DEBUG(2, " cerr=%-7d rcvcco=%d\n",
1287 pstats->cerr, pstats->rcvcco);
1288 DEBUG(2, " rntpco=%-7d mpco=%d\n",
1289 pstats->rntpco, pstats->mpco);
1290
1291 /* MACE_MPC */
1292 DEBUG(2, " mpc=%d\n", pstats->mpc);
1293
1294 /* MACE_RNTPC */
1295 DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1296
1297 /* MACE_RCVCC */
1298 DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1299
1300 } /* pr_mace_stats */
1301
1302 /* ----------------------------------------------------------------------------
1303 update_stats
1304 Update statistics. We change to register window 1, so this
1305 should be run single-threaded if the device is active. This is
1306 expected to be a rare operation, and it's simpler for the rest
1307 of the driver to assume that window 0 is always valid rather
1308 than use a special window-state variable.
1309
1310 oflo & uflo should _never_ occur since it would mean the Xilinx
1311 was not able to transfer data between the MACE FIFO and the
1312 card's SRAM fast enough. If this happens, something is
1313 seriously wrong with the hardware.
1314 ---------------------------------------------------------------------------- */
1315 static void update_stats(kio_addr_t ioaddr, struct net_device *dev)
1316 {
1317 mace_private *lp = netdev_priv(dev);
1318
1319 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1320 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1321 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1322 /* At this point, mace_stats is fully updated for this call.
1323 We may now update the linux_stats. */
1324
1325 /* The MACE has no equivalent for linux_stats field which are commented
1326 out. */
1327
1328 /* lp->linux_stats.multicast; */
1329 lp->linux_stats.collisions =
1330 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1331 /* Collision: The MACE may retry sending a packet 15 times
1332 before giving up. The retry count is in XMTRC.
1333 Does each retry constitute a collision?
1334 If so, why doesn't the RCVCC record these collisions? */
1335
1336 /* detailed rx_errors: */
1337 lp->linux_stats.rx_length_errors =
1338 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1339 /* lp->linux_stats.rx_over_errors */
1340 lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1341 lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1342 lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1343 lp->linux_stats.rx_missed_errors =
1344 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1345
1346 /* detailed tx_errors */
1347 lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1348 lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1349 /* LCAR usually results from bad cabling. */
1350 lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1351 lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1352 /* lp->linux_stats.tx_window_errors; */
1353
1354 return;
1355 } /* update_stats */
1356
1357 /* ----------------------------------------------------------------------------
1358 mace_get_stats
1359 Gathers ethernet statistics from the MACE chip.
1360 ---------------------------------------------------------------------------- */
1361 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1362 {
1363 mace_private *lp = netdev_priv(dev);
1364
1365 update_stats(dev->base_addr, dev);
1366
1367 DEBUG(1, "%s: updating the statistics.\n", dev->name);
1368 pr_linux_stats(&lp->linux_stats);
1369 pr_mace_stats(&lp->mace_stats);
1370
1371 return &lp->linux_stats;
1372 } /* net_device_stats */
1373
1374 /* ----------------------------------------------------------------------------
1375 updateCRC
1376 Modified from Am79C90 data sheet.
1377 ---------------------------------------------------------------------------- */
1378
1379 #ifdef BROKEN_MULTICAST
1380
1381 static void updateCRC(int *CRC, int bit)
1382 {
1383 int poly[]={
1384 1,1,1,0, 1,1,0,1,
1385 1,0,1,1, 1,0,0,0,
1386 1,0,0,0, 0,0,1,1,
1387 0,0,1,0, 0,0,0,0
1388 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1389 CRC generator polynomial. */
1390
1391 int j;
1392
1393 /* shift CRC and control bit (CRC[32]) */
1394 for (j = 32; j > 0; j--)
1395 CRC[j] = CRC[j-1];
1396 CRC[0] = 0;
1397
1398 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1399 if (bit ^ CRC[32])
1400 for (j = 0; j < 32; j++)
1401 CRC[j] ^= poly[j];
1402 } /* updateCRC */
1403
1404 /* ----------------------------------------------------------------------------
1405 BuildLAF
1406 Build logical address filter.
1407 Modified from Am79C90 data sheet.
1408
1409 Input
1410 ladrf: logical address filter (contents initialized to 0)
1411 adr: ethernet address
1412 ---------------------------------------------------------------------------- */
1413 static void BuildLAF(int *ladrf, int *adr)
1414 {
1415 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1416
1417 int i, byte; /* temporary array indices */
1418 int hashcode; /* the output object */
1419
1420 CRC[32]=0;
1421
1422 for (byte = 0; byte < 6; byte++)
1423 for (i = 0; i < 8; i++)
1424 updateCRC(CRC, (adr[byte] >> i) & 1);
1425
1426 hashcode = 0;
1427 for (i = 0; i < 6; i++)
1428 hashcode = (hashcode << 1) + CRC[i];
1429
1430 byte = hashcode >> 3;
1431 ladrf[byte] |= (1 << (hashcode & 7));
1432
1433 #ifdef PCMCIA_DEBUG
1434 if (pc_debug > 2) {
1435 printk(KERN_DEBUG " adr =");
1436 for (i = 0; i < 6; i++)
1437 printk(" %02X", adr[i]);
1438 printk("\n" KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63]"
1439 " =", hashcode);
1440 for (i = 0; i < 8; i++)
1441 printk(" %02X", ladrf[i]);
1442 printk("\n");
1443 }
1444 #endif
1445 } /* BuildLAF */
1446
1447 /* ----------------------------------------------------------------------------
1448 restore_multicast_list
1449 Restores the multicast filter for MACE chip to the last
1450 set_multicast_list() call.
1451
1452 Input
1453 multicast_num_addrs
1454 multicast_ladrf[]
1455 ---------------------------------------------------------------------------- */
1456 static void restore_multicast_list(struct net_device *dev)
1457 {
1458 mace_private *lp = netdev_priv(dev);
1459 int num_addrs = lp->multicast_num_addrs;
1460 int *ladrf = lp->multicast_ladrf;
1461 kio_addr_t ioaddr = dev->base_addr;
1462 int i;
1463
1464 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1465 dev->name, num_addrs);
1466
1467 if (num_addrs > 0) {
1468
1469 DEBUG(1, "Attempt to restore multicast list detected.\n");
1470
1471 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1472 /* Poll ADDRCHG bit */
1473 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1474 ;
1475 /* Set LADRF register */
1476 for (i = 0; i < MACE_LADRF_LEN; i++)
1477 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1478
1479 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1480 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1481
1482 } else if (num_addrs < 0) {
1483
1484 /* Promiscuous mode: receive all packets */
1485 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1486 mace_write(lp, ioaddr, MACE_MACCC,
1487 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1488 );
1489
1490 } else {
1491
1492 /* Normal mode */
1493 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1494 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1495
1496 }
1497 } /* restore_multicast_list */
1498
1499 /* ----------------------------------------------------------------------------
1500 set_multicast_list
1501 Set or clear the multicast filter for this adaptor.
1502
1503 Input
1504 num_addrs == -1 Promiscuous mode, receive all packets
1505 num_addrs == 0 Normal mode, clear multicast list
1506 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1507 best-effort filtering.
1508 Output
1509 multicast_num_addrs
1510 multicast_ladrf[]
1511 ---------------------------------------------------------------------------- */
1512
1513 static void set_multicast_list(struct net_device *dev)
1514 {
1515 mace_private *lp = netdev_priv(dev);
1516 int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1517 int i;
1518 struct dev_mc_list *dmi = dev->mc_list;
1519
1520 #ifdef PCMCIA_DEBUG
1521 if (pc_debug > 1) {
1522 static int old;
1523 if (dev->mc_count != old) {
1524 old = dev->mc_count;
1525 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1526 dev->name, old);
1527 }
1528 }
1529 #endif
1530
1531 /* Set multicast_num_addrs. */
1532 lp->multicast_num_addrs = dev->mc_count;
1533
1534 /* Set multicast_ladrf. */
1535 if (num_addrs > 0) {
1536 /* Calculate multicast logical address filter */
1537 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1538 for (i = 0; i < dev->mc_count; i++) {
1539 memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1540 dmi = dmi->next;
1541 BuildLAF(lp->multicast_ladrf, adr);
1542 }
1543 }
1544
1545 restore_multicast_list(dev);
1546
1547 } /* set_multicast_list */
1548
1549 #endif /* BROKEN_MULTICAST */
1550
1551 static void restore_multicast_list(struct net_device *dev)
1552 {
1553 kio_addr_t ioaddr = dev->base_addr;
1554 mace_private *lp = netdev_priv(dev);
1555
1556 DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1557 lp->multicast_num_addrs);
1558
1559 if (dev->flags & IFF_PROMISC) {
1560 /* Promiscuous mode: receive all packets */
1561 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1562 mace_write(lp, ioaddr, MACE_MACCC,
1563 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1564 );
1565 } else {
1566 /* Normal mode */
1567 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1568 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1569 }
1570 } /* restore_multicast_list */
1571
1572 static void set_multicast_list(struct net_device *dev)
1573 {
1574 mace_private *lp = netdev_priv(dev);
1575
1576 #ifdef PCMCIA_DEBUG
1577 if (pc_debug > 1) {
1578 static int old;
1579 if (dev->mc_count != old) {
1580 old = dev->mc_count;
1581 DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1582 dev->name, old);
1583 }
1584 }
1585 #endif
1586
1587 lp->multicast_num_addrs = dev->mc_count;
1588 restore_multicast_list(dev);
1589
1590 } /* set_multicast_list */
1591
1592 static struct pcmcia_device_id nmclan_ids[] = {
1593 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1594 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1595 PCMCIA_DEVICE_NULL,
1596 };
1597 MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1598
1599 static struct pcmcia_driver nmclan_cs_driver = {
1600 .owner = THIS_MODULE,
1601 .drv = {
1602 .name = "nmclan_cs",
1603 },
1604 .probe = nmclan_probe,
1605 .remove = nmclan_detach,
1606 .id_table = nmclan_ids,
1607 .suspend = nmclan_suspend,
1608 .resume = nmclan_resume,
1609 };
1610
1611 static int __init init_nmclan_cs(void)
1612 {
1613 return pcmcia_register_driver(&nmclan_cs_driver);
1614 }
1615
1616 static void __exit exit_nmclan_cs(void)
1617 {
1618 pcmcia_unregister_driver(&nmclan_cs_driver);
1619 }
1620
1621 module_init(init_nmclan_cs);
1622 module_exit(exit_nmclan_cs);
Linux kernel - Deliverables
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