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Merge ../bleed-2.6
[deliverable/linux.git] / drivers / net / pcnet32.c
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.31a"
26 #define DRV_RELDATE "12.Sep.2005"
27 #define PFX DRV_NAME ": "
28
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
51
52 #include <asm/dma.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/irq.h>
56
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
62 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
63 /*
64 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
65 * the incorrect vendor id.
66 */
67 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID,
68 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 },
69 { 0, }
70 };
71
72 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
73
74 static int cards_found;
75
76 /*
77 * VLB I/O addresses
78 */
79 static unsigned int pcnet32_portlist[] __initdata =
80 { 0x300, 0x320, 0x340, 0x360, 0 };
81
82
83
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
87
88 static struct net_device *pcnet32_dev;
89
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
92
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
97
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
102
103 #define PCNET32_DMA_MASK 0xffffffff
104
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_ASEL /* 15 not supported */
129 };
130
131 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
132 "Loopback test (offline)"
133 };
134 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
135
136 #define PCNET32_NUM_REGS 168
137
138 #define MAX_UNITS 8 /* More are supported, limit only on options */
139 static int options[MAX_UNITS];
140 static int full_duplex[MAX_UNITS];
141 static int homepna[MAX_UNITS];
142
143 /*
144 * Theory of Operation
145 *
146 * This driver uses the same software structure as the normal lance
147 * driver. So look for a verbose description in lance.c. The differences
148 * to the normal lance driver is the use of the 32bit mode of PCnet32
149 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
150 * 16MB limitation and we don't need bounce buffers.
151 */
152
153 /*
154 * History:
155 * v0.01: Initial version
156 * only tested on Alpha Noname Board
157 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
158 * tested on a ASUS SP3G
159 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
160 * looks like the 974 doesn't like stopping and restarting in a
161 * short period of time; now we do a reinit of the lance; the
162 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
163 * and hangs the machine (thanks to Klaus Liedl for debugging)
164 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
165 * made it standalone (no need for lance.c)
166 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
167 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
168 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
169 * v0.15: added 79C965 (VLB) probe
170 * added interrupt sharing for PCI chips
171 * v0.16: fixed set_multicast_list on Alpha machines
172 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
173 * v0.19: changed setting of autoselect bit
174 * v0.20: removed additional Compaq PCI probe; there is now a working one
175 * in arch/i386/bios32.c
176 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
177 * v0.22: added printing of status to ring dump
178 * v0.23: changed enet_statistics to net_devive_stats
179 * v0.90: added multicast filter
180 * added module support
181 * changed irq probe to new style
182 * added PCnetFast chip id
183 * added fix for receive stalls with Intel saturn chipsets
184 * added in-place rx skbs like in the tulip driver
185 * minor cleanups
186 * v0.91: added PCnetFast+ chip id
187 * back port to 2.0.x
188 * v1.00: added some stuff from Donald Becker's 2.0.34 version
189 * added support for byte counters in net_dev_stats
190 * v1.01: do ring dumps, only when debugging the driver
191 * increased the transmit timeout
192 * v1.02: fixed memory leak in pcnet32_init_ring()
193 * v1.10: workaround for stopped transmitter
194 * added port selection for modules
195 * detect special T1/E1 WAN card and setup port selection
196 * v1.11: fixed wrong checking of Tx errors
197 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
198 * added save original kmalloc addr for freeing (mcr@solidum.com)
199 * added support for PCnetHome chip (joe@MIT.EDU)
200 * rewritten PCI card detection
201 * added dwio mode to get driver working on some PPC machines
202 * v1.21: added mii selection and mii ioctl
203 * v1.22: changed pci scanning code to make PPC people happy
204 * fixed switching to 32bit mode in pcnet32_open() (thanks
205 * to Michael Richard <mcr@solidum.com> for noticing this one)
206 * added sub vendor/device id matching (thanks again to
207 * Michael Richard <mcr@solidum.com>)
208 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
209 * v1.23 fixed small bug, when manual selecting MII speed/duplex
210 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
211 * underflows. Added tx_start_pt module parameter. Increased
212 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
213 * for FAST[+] chipsets. <kaf@fc.hp.com>
214 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
215 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
216 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
217 * <jamey@crl.dec.com>
218 * - Fixed a few bugs, related to running the controller in 32bit mode.
219 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
220 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
221 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
222 * v1.27 improved CSR/PROM address detection, lots of cleanups,
223 * new pcnet32vlb module option, HP-PARISC support,
224 * added module parameter descriptions,
225 * initial ethtool support - Helge Deller <deller@gmx.de>
226 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
227 * use alloc_etherdev and register_netdev
228 * fix pci probe not increment cards_found
229 * FD auto negotiate error workaround for xSeries250
230 * clean up and using new mii module
231 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
232 * Added timer for cable connection state changes.
233 * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com>
234 * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com>
235 * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl.
236 * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single
237 * length errors, and transmit hangs. Cleans up after errors in open.
238 * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test.
239 * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections.
240 * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical
241 * identification code (blink led's) and register dump.
242 * Don Fry added timer for 971/972 so skbufs don't remain on tx ring
243 * forever.
244 * v1.30 18 May 2004 Don Fry removed timer and Last Transmit Interrupt
245 * (ltint) as they added complexity and didn't give good throughput.
246 * v1.30a 22 May 2004 Don Fry limit frames received during interrupt.
247 * v1.30b 24 May 2004 Don Fry fix bogus tx carrier errors with 79c973,
248 * assisted by Bruce Penrod <bmpenrod@endruntechnologies.com>.
249 * v1.30c 25 May 2004 Don Fry added netif_wake_queue after pcnet32_restart.
250 * v1.30d 01 Jun 2004 Don Fry discard oversize rx packets.
251 * v1.30e 11 Jun 2004 Don Fry recover after fifo error and rx hang.
252 * v1.30f 16 Jun 2004 Don Fry cleanup IRQ to allow 0 and 1 for PCI,
253 * expanding on suggestions from Ralf Baechle <ralf@linux-mips.org>,
254 * and Brian Murphy <brian@murphy.dk>.
255 * v1.30g 22 Jun 2004 Patrick Simmons <psimmons@flash.net> added option
256 * homepna for selecting HomePNA mode for PCNet/Home 79C978.
257 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32.
258 * v1.30i 28 Jun 2004 Don Fry change to use module_param.
259 * v1.30j 29 Apr 2005 Don Fry fix skb/map leak with loopback test.
260 * v1.31 02 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> added set_ringparam().
261 * v1.31a 12 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> set min ring size to 4
262 * to allow loopback test to work unchanged.
263 */
264
265
266 /*
267 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
268 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
269 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
270 */
271 #ifndef PCNET32_LOG_TX_BUFFERS
272 #define PCNET32_LOG_TX_BUFFERS 4
273 #define PCNET32_LOG_RX_BUFFERS 5
274 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
275 #define PCNET32_LOG_MAX_RX_BUFFERS 9
276 #endif
277
278 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
279 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
280
281 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
282 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
283
284 #define PKT_BUF_SZ 1544
285
286 /* Offsets from base I/O address. */
287 #define PCNET32_WIO_RDP 0x10
288 #define PCNET32_WIO_RAP 0x12
289 #define PCNET32_WIO_RESET 0x14
290 #define PCNET32_WIO_BDP 0x16
291
292 #define PCNET32_DWIO_RDP 0x10
293 #define PCNET32_DWIO_RAP 0x14
294 #define PCNET32_DWIO_RESET 0x18
295 #define PCNET32_DWIO_BDP 0x1C
296
297 #define PCNET32_TOTAL_SIZE 0x20
298
299 /* The PCNET32 Rx and Tx ring descriptors. */
300 struct pcnet32_rx_head {
301 u32 base;
302 s16 buf_length;
303 s16 status;
304 u32 msg_length;
305 u32 reserved;
306 };
307
308 struct pcnet32_tx_head {
309 u32 base;
310 s16 length;
311 s16 status;
312 u32 misc;
313 u32 reserved;
314 };
315
316 /* The PCNET32 32-Bit initialization block, described in databook. */
317 struct pcnet32_init_block {
318 u16 mode;
319 u16 tlen_rlen;
320 u8 phys_addr[6];
321 u16 reserved;
322 u32 filter[2];
323 /* Receive and transmit ring base, along with extra bits. */
324 u32 rx_ring;
325 u32 tx_ring;
326 };
327
328 /* PCnet32 access functions */
329 struct pcnet32_access {
330 u16 (*read_csr)(unsigned long, int);
331 void (*write_csr)(unsigned long, int, u16);
332 u16 (*read_bcr)(unsigned long, int);
333 void (*write_bcr)(unsigned long, int, u16);
334 u16 (*read_rap)(unsigned long);
335 void (*write_rap)(unsigned long, u16);
336 void (*reset)(unsigned long);
337 };
338
339 /*
340 * The first field of pcnet32_private is read by the ethernet device
341 * so the structure should be allocated using pci_alloc_consistent().
342 */
343 struct pcnet32_private {
344 struct pcnet32_init_block init_block;
345 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
346 struct pcnet32_rx_head *rx_ring;
347 struct pcnet32_tx_head *tx_ring;
348 dma_addr_t dma_addr; /* DMA address of beginning of this
349 object, returned by
350 pci_alloc_consistent */
351 struct pci_dev *pci_dev; /* Pointer to the associated pci device
352 structure */
353 const char *name;
354 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
355 struct sk_buff **tx_skbuff;
356 struct sk_buff **rx_skbuff;
357 dma_addr_t *tx_dma_addr;
358 dma_addr_t *rx_dma_addr;
359 struct pcnet32_access a;
360 spinlock_t lock; /* Guard lock */
361 unsigned int cur_rx, cur_tx; /* The next free ring entry */
362 unsigned int rx_ring_size; /* current rx ring size */
363 unsigned int tx_ring_size; /* current tx ring size */
364 unsigned int rx_mod_mask; /* rx ring modular mask */
365 unsigned int tx_mod_mask; /* tx ring modular mask */
366 unsigned short rx_len_bits;
367 unsigned short tx_len_bits;
368 dma_addr_t rx_ring_dma_addr;
369 dma_addr_t tx_ring_dma_addr;
370 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
371 struct net_device_stats stats;
372 char tx_full;
373 int options;
374 unsigned int shared_irq:1, /* shared irq possible */
375 dxsuflo:1, /* disable transmit stop on uflo */
376 mii:1; /* mii port available */
377 struct net_device *next;
378 struct mii_if_info mii_if;
379 struct timer_list watchdog_timer;
380 struct timer_list blink_timer;
381 u32 msg_enable; /* debug message level */
382 };
383
384 static void pcnet32_probe_vlbus(void);
385 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
386 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
387 static int pcnet32_open(struct net_device *);
388 static int pcnet32_init_ring(struct net_device *);
389 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
390 static int pcnet32_rx(struct net_device *);
391 static void pcnet32_tx_timeout (struct net_device *dev);
392 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
393 static int pcnet32_close(struct net_device *);
394 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
395 static void pcnet32_load_multicast(struct net_device *dev);
396 static void pcnet32_set_multicast_list(struct net_device *);
397 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
398 static void pcnet32_watchdog(struct net_device *);
399 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
400 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
401 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
402 static void pcnet32_ethtool_test(struct net_device *dev,
403 struct ethtool_test *eth_test, u64 *data);
404 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1);
405 static int pcnet32_phys_id(struct net_device *dev, u32 data);
406 static void pcnet32_led_blink_callback(struct net_device *dev);
407 static int pcnet32_get_regs_len(struct net_device *dev);
408 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
409 void *ptr);
410 static void pcnet32_purge_tx_ring(struct net_device *dev);
411 static int pcnet32_alloc_ring(struct net_device *dev);
412 static void pcnet32_free_ring(struct net_device *dev);
413
414
415 enum pci_flags_bit {
416 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
417 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
418 };
419
420
421 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
422 {
423 outw (index, addr+PCNET32_WIO_RAP);
424 return inw (addr+PCNET32_WIO_RDP);
425 }
426
427 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
428 {
429 outw (index, addr+PCNET32_WIO_RAP);
430 outw (val, addr+PCNET32_WIO_RDP);
431 }
432
433 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
434 {
435 outw (index, addr+PCNET32_WIO_RAP);
436 return inw (addr+PCNET32_WIO_BDP);
437 }
438
439 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
440 {
441 outw (index, addr+PCNET32_WIO_RAP);
442 outw (val, addr+PCNET32_WIO_BDP);
443 }
444
445 static u16 pcnet32_wio_read_rap (unsigned long addr)
446 {
447 return inw (addr+PCNET32_WIO_RAP);
448 }
449
450 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
451 {
452 outw (val, addr+PCNET32_WIO_RAP);
453 }
454
455 static void pcnet32_wio_reset (unsigned long addr)
456 {
457 inw (addr+PCNET32_WIO_RESET);
458 }
459
460 static int pcnet32_wio_check (unsigned long addr)
461 {
462 outw (88, addr+PCNET32_WIO_RAP);
463 return (inw (addr+PCNET32_WIO_RAP) == 88);
464 }
465
466 static struct pcnet32_access pcnet32_wio = {
467 .read_csr = pcnet32_wio_read_csr,
468 .write_csr = pcnet32_wio_write_csr,
469 .read_bcr = pcnet32_wio_read_bcr,
470 .write_bcr = pcnet32_wio_write_bcr,
471 .read_rap = pcnet32_wio_read_rap,
472 .write_rap = pcnet32_wio_write_rap,
473 .reset = pcnet32_wio_reset
474 };
475
476 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
477 {
478 outl (index, addr+PCNET32_DWIO_RAP);
479 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
480 }
481
482 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
483 {
484 outl (index, addr+PCNET32_DWIO_RAP);
485 outl (val, addr+PCNET32_DWIO_RDP);
486 }
487
488 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
489 {
490 outl (index, addr+PCNET32_DWIO_RAP);
491 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
492 }
493
494 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
495 {
496 outl (index, addr+PCNET32_DWIO_RAP);
497 outl (val, addr+PCNET32_DWIO_BDP);
498 }
499
500 static u16 pcnet32_dwio_read_rap (unsigned long addr)
501 {
502 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
503 }
504
505 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
506 {
507 outl (val, addr+PCNET32_DWIO_RAP);
508 }
509
510 static void pcnet32_dwio_reset (unsigned long addr)
511 {
512 inl (addr+PCNET32_DWIO_RESET);
513 }
514
515 static int pcnet32_dwio_check (unsigned long addr)
516 {
517 outl (88, addr+PCNET32_DWIO_RAP);
518 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
519 }
520
521 static struct pcnet32_access pcnet32_dwio = {
522 .read_csr = pcnet32_dwio_read_csr,
523 .write_csr = pcnet32_dwio_write_csr,
524 .read_bcr = pcnet32_dwio_read_bcr,
525 .write_bcr = pcnet32_dwio_write_bcr,
526 .read_rap = pcnet32_dwio_read_rap,
527 .write_rap = pcnet32_dwio_write_rap,
528 .reset = pcnet32_dwio_reset
529 };
530
531 #ifdef CONFIG_NET_POLL_CONTROLLER
532 static void pcnet32_poll_controller(struct net_device *dev)
533 {
534 disable_irq(dev->irq);
535 pcnet32_interrupt(0, dev, NULL);
536 enable_irq(dev->irq);
537 }
538 #endif
539
540
541 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
542 {
543 struct pcnet32_private *lp = dev->priv;
544 unsigned long flags;
545 int r = -EOPNOTSUPP;
546
547 if (lp->mii) {
548 spin_lock_irqsave(&lp->lock, flags);
549 mii_ethtool_gset(&lp->mii_if, cmd);
550 spin_unlock_irqrestore(&lp->lock, flags);
551 r = 0;
552 }
553 return r;
554 }
555
556 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
557 {
558 struct pcnet32_private *lp = dev->priv;
559 unsigned long flags;
560 int r = -EOPNOTSUPP;
561
562 if (lp->mii) {
563 spin_lock_irqsave(&lp->lock, flags);
564 r = mii_ethtool_sset(&lp->mii_if, cmd);
565 spin_unlock_irqrestore(&lp->lock, flags);
566 }
567 return r;
568 }
569
570 static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
571 {
572 struct pcnet32_private *lp = dev->priv;
573
574 strcpy (info->driver, DRV_NAME);
575 strcpy (info->version, DRV_VERSION);
576 if (lp->pci_dev)
577 strcpy (info->bus_info, pci_name(lp->pci_dev));
578 else
579 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
580 }
581
582 static u32 pcnet32_get_link(struct net_device *dev)
583 {
584 struct pcnet32_private *lp = dev->priv;
585 unsigned long flags;
586 int r;
587
588 spin_lock_irqsave(&lp->lock, flags);
589 if (lp->mii) {
590 r = mii_link_ok(&lp->mii_if);
591 } else {
592 ulong ioaddr = dev->base_addr; /* card base I/O address */
593 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
594 }
595 spin_unlock_irqrestore(&lp->lock, flags);
596
597 return r;
598 }
599
600 static u32 pcnet32_get_msglevel(struct net_device *dev)
601 {
602 struct pcnet32_private *lp = dev->priv;
603 return lp->msg_enable;
604 }
605
606 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
607 {
608 struct pcnet32_private *lp = dev->priv;
609 lp->msg_enable = value;
610 }
611
612 static int pcnet32_nway_reset(struct net_device *dev)
613 {
614 struct pcnet32_private *lp = dev->priv;
615 unsigned long flags;
616 int r = -EOPNOTSUPP;
617
618 if (lp->mii) {
619 spin_lock_irqsave(&lp->lock, flags);
620 r = mii_nway_restart(&lp->mii_if);
621 spin_unlock_irqrestore(&lp->lock, flags);
622 }
623 return r;
624 }
625
626 static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
627 {
628 struct pcnet32_private *lp = dev->priv;
629
630 ering->tx_max_pending = TX_MAX_RING_SIZE - 1;
631 ering->tx_pending = lp->tx_ring_size - 1;
632 ering->rx_max_pending = RX_MAX_RING_SIZE - 1;
633 ering->rx_pending = lp->rx_ring_size - 1;
634 }
635
636 static int pcnet32_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
637 {
638 struct pcnet32_private *lp = dev->priv;
639 unsigned long flags;
640 int i;
641
642 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
643 return -EINVAL;
644
645 if (netif_running(dev))
646 pcnet32_close(dev);
647
648 spin_lock_irqsave(&lp->lock, flags);
649 pcnet32_free_ring(dev);
650 lp->tx_ring_size = min(ering->tx_pending, (unsigned int) TX_MAX_RING_SIZE);
651 lp->rx_ring_size = min(ering->rx_pending, (unsigned int) RX_MAX_RING_SIZE);
652
653 /* set the minimum ring size to 4, to allow the loopback test to work
654 * unchanged.
655 */
656 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
657 if (lp->tx_ring_size <= (1 << i))
658 break;
659 }
660 lp->tx_ring_size = (1 << i);
661 lp->tx_mod_mask = lp->tx_ring_size - 1;
662 lp->tx_len_bits = (i << 12);
663
664 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
665 if (lp->rx_ring_size <= (1 << i))
666 break;
667 }
668 lp->rx_ring_size = (1 << i);
669 lp->rx_mod_mask = lp->rx_ring_size - 1;
670 lp->rx_len_bits = (i << 4);
671
672 if (pcnet32_alloc_ring(dev)) {
673 pcnet32_free_ring(dev);
674 return -ENOMEM;
675 }
676
677 spin_unlock_irqrestore(&lp->lock, flags);
678
679 if (pcnet32_debug & NETIF_MSG_DRV)
680 printk(KERN_INFO PFX "Ring Param Settings: RX: %d, TX: %d\n", lp->rx_ring_size, lp->tx_ring_size);
681
682 if (netif_running(dev))
683 pcnet32_open(dev);
684
685 return 0;
686 }
687
688 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data)
689 {
690 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
691 }
692
693 static int pcnet32_self_test_count(struct net_device *dev)
694 {
695 return PCNET32_TEST_LEN;
696 }
697
698 static void pcnet32_ethtool_test(struct net_device *dev,
699 struct ethtool_test *test, u64 *data)
700 {
701 struct pcnet32_private *lp = dev->priv;
702 int rc;
703
704 if (test->flags == ETH_TEST_FL_OFFLINE) {
705 rc = pcnet32_loopback_test(dev, data);
706 if (rc) {
707 if (netif_msg_hw(lp))
708 printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name);
709 test->flags |= ETH_TEST_FL_FAILED;
710 } else if (netif_msg_hw(lp))
711 printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name);
712 } else if (netif_msg_hw(lp))
713 printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name);
714 } /* end pcnet32_ethtool_test */
715
716 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
717 {
718 struct pcnet32_private *lp = dev->priv;
719 struct pcnet32_access *a = &lp->a; /* access to registers */
720 ulong ioaddr = dev->base_addr; /* card base I/O address */
721 struct sk_buff *skb; /* sk buff */
722 int x, i; /* counters */
723 int numbuffs = 4; /* number of TX/RX buffers and descs */
724 u16 status = 0x8300; /* TX ring status */
725 u16 teststatus; /* test of ring status */
726 int rc; /* return code */
727 int size; /* size of packets */
728 unsigned char *packet; /* source packet data */
729 static int data_len = 60; /* length of source packets */
730 unsigned long flags;
731 unsigned long ticks;
732
733 *data1 = 1; /* status of test, default to fail */
734 rc = 1; /* default to fail */
735
736 if (netif_running(dev))
737 pcnet32_close(dev);
738
739 spin_lock_irqsave(&lp->lock, flags);
740
741 /* Reset the PCNET32 */
742 lp->a.reset (ioaddr);
743
744 /* switch pcnet32 to 32bit mode */
745 lp->a.write_bcr (ioaddr, 20, 2);
746
747 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
748 lp->init_block.filter[0] = 0;
749 lp->init_block.filter[1] = 0;
750
751 /* purge & init rings but don't actually restart */
752 pcnet32_restart(dev, 0x0000);
753
754 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
755
756 /* Initialize Transmit buffers. */
757 size = data_len + 15;
758 for (x=0; x<numbuffs; x++) {
759 if (!(skb = dev_alloc_skb(size))) {
760 if (netif_msg_hw(lp))
761 printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n",
762 dev->name, __LINE__);
763 goto clean_up;
764 } else {
765 packet = skb->data;
766 skb_put(skb, size); /* create space for data */
767 lp->tx_skbuff[x] = skb;
768 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
769 lp->tx_ring[x].misc = 0;
770
771 /* put DA and SA into the skb */
772 for (i=0; i<6; i++)
773 *packet++ = dev->dev_addr[i];
774 for (i=0; i<6; i++)
775 *packet++ = dev->dev_addr[i];
776 /* type */
777 *packet++ = 0x08;
778 *packet++ = 0x06;
779 /* packet number */
780 *packet++ = x;
781 /* fill packet with data */
782 for (i=0; i<data_len; i++)
783 *packet++ = i;
784
785 lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data,
786 skb->len, PCI_DMA_TODEVICE);
787 lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]);
788 wmb(); /* Make sure owner changes after all others are visible */
789 lp->tx_ring[x].status = le16_to_cpu(status);
790 }
791 }
792
793 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
794 x = x | 0x0002;
795 a->write_bcr(ioaddr, 32, x);
796
797 lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
798
799 teststatus = le16_to_cpu(0x8000);
800 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
801
802 /* Check status of descriptors */
803 for (x=0; x<numbuffs; x++) {
804 ticks = 0;
805 rmb();
806 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
807 spin_unlock_irqrestore(&lp->lock, flags);
808 mdelay(1);
809 spin_lock_irqsave(&lp->lock, flags);
810 rmb();
811 ticks++;
812 }
813 if (ticks == 200) {
814 if (netif_msg_hw(lp))
815 printk("%s: Desc %d failed to reset!\n",dev->name,x);
816 break;
817 }
818 }
819
820 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
821 wmb();
822 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
823 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
824
825 for (x=0; x<numbuffs; x++) {
826 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
827 skb = lp->rx_skbuff[x];
828 for (i=0; i<size; i++) {
829 printk("%02x ", *(skb->data+i));
830 }
831 printk("\n");
832 }
833 }
834
835 x = 0;
836 rc = 0;
837 while (x<numbuffs && !rc) {
838 skb = lp->rx_skbuff[x];
839 packet = lp->tx_skbuff[x]->data;
840 for (i=0; i<size; i++) {
841 if (*(skb->data+i) != packet[i]) {
842 if (netif_msg_hw(lp))
843 printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n",
844 dev->name, i, *(skb->data+i), packet[i]);
845 rc = 1;
846 break;
847 }
848 }
849 x++;
850 }
851 if (!rc) {
852 *data1 = 0;
853 }
854
855 clean_up:
856 pcnet32_purge_tx_ring(dev);
857 x = a->read_csr(ioaddr, 15) & 0xFFFF;
858 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
859
860 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
861 x = x & ~0x0002;
862 a->write_bcr(ioaddr, 32, x);
863
864 spin_unlock_irqrestore(&lp->lock, flags);
865
866 if (netif_running(dev)) {
867 pcnet32_open(dev);
868 } else {
869 lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */
870 }
871
872 return(rc);
873 } /* end pcnet32_loopback_test */
874
875 static void pcnet32_led_blink_callback(struct net_device *dev)
876 {
877 struct pcnet32_private *lp = dev->priv;
878 struct pcnet32_access *a = &lp->a;
879 ulong ioaddr = dev->base_addr;
880 unsigned long flags;
881 int i;
882
883 spin_lock_irqsave(&lp->lock, flags);
884 for (i=4; i<8; i++) {
885 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
886 }
887 spin_unlock_irqrestore(&lp->lock, flags);
888
889 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
890 }
891
892 static int pcnet32_phys_id(struct net_device *dev, u32 data)
893 {
894 struct pcnet32_private *lp = dev->priv;
895 struct pcnet32_access *a = &lp->a;
896 ulong ioaddr = dev->base_addr;
897 unsigned long flags;
898 int i, regs[4];
899
900 if (!lp->blink_timer.function) {
901 init_timer(&lp->blink_timer);
902 lp->blink_timer.function = (void *) pcnet32_led_blink_callback;
903 lp->blink_timer.data = (unsigned long) dev;
904 }
905
906 /* Save the current value of the bcrs */
907 spin_lock_irqsave(&lp->lock, flags);
908 for (i=4; i<8; i++) {
909 regs[i-4] = a->read_bcr(ioaddr, i);
910 }
911 spin_unlock_irqrestore(&lp->lock, flags);
912
913 mod_timer(&lp->blink_timer, jiffies);
914 set_current_state(TASK_INTERRUPTIBLE);
915
916 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
917 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
918
919 msleep_interruptible(data * 1000);
920 del_timer_sync(&lp->blink_timer);
921
922 /* Restore the original value of the bcrs */
923 spin_lock_irqsave(&lp->lock, flags);
924 for (i=4; i<8; i++) {
925 a->write_bcr(ioaddr, i, regs[i-4]);
926 }
927 spin_unlock_irqrestore(&lp->lock, flags);
928
929 return 0;
930 }
931
932 static int pcnet32_get_regs_len(struct net_device *dev)
933 {
934 return(PCNET32_NUM_REGS * sizeof(u16));
935 }
936
937 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
938 void *ptr)
939 {
940 int i, csr0;
941 u16 *buff = ptr;
942 struct pcnet32_private *lp = dev->priv;
943 struct pcnet32_access *a = &lp->a;
944 ulong ioaddr = dev->base_addr;
945 int ticks;
946 unsigned long flags;
947
948 spin_lock_irqsave(&lp->lock, flags);
949
950 csr0 = a->read_csr(ioaddr, 0);
951 if (!(csr0 & 0x0004)) { /* If not stopped */
952 /* set SUSPEND (SPND) - CSR5 bit 0 */
953 a->write_csr(ioaddr, 5, 0x0001);
954
955 /* poll waiting for bit to be set */
956 ticks = 0;
957 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
958 spin_unlock_irqrestore(&lp->lock, flags);
959 mdelay(1);
960 spin_lock_irqsave(&lp->lock, flags);
961 ticks++;
962 if (ticks > 200) {
963 if (netif_msg_hw(lp))
964 printk(KERN_DEBUG "%s: Error getting into suspend!\n",
965 dev->name);
966 break;
967 }
968 }
969 }
970
971 /* read address PROM */
972 for (i=0; i<16; i += 2)
973 *buff++ = inw(ioaddr + i);
974
975 /* read control and status registers */
976 for (i=0; i<90; i++) {
977 *buff++ = a->read_csr(ioaddr, i);
978 }
979
980 *buff++ = a->read_csr(ioaddr, 112);
981 *buff++ = a->read_csr(ioaddr, 114);
982
983 /* read bus configuration registers */
984 for (i=0; i<36; i++) {
985 *buff++ = a->read_bcr(ioaddr, i);
986 }
987
988 /* read mii phy registers */
989 if (lp->mii) {
990 for (i=0; i<32; i++) {
991 lp->a.write_bcr(ioaddr, 33, ((lp->mii_if.phy_id) << 5) | i);
992 *buff++ = lp->a.read_bcr(ioaddr, 34);
993 }
994 }
995
996 if (!(csr0 & 0x0004)) { /* If not stopped */
997 /* clear SUSPEND (SPND) - CSR5 bit 0 */
998 a->write_csr(ioaddr, 5, 0x0000);
999 }
1000
1001 i = buff - (u16 *)ptr;
1002 for (; i < PCNET32_NUM_REGS; i++)
1003 *buff++ = 0;
1004
1005 spin_unlock_irqrestore(&lp->lock, flags);
1006 }
1007
1008 static struct ethtool_ops pcnet32_ethtool_ops = {
1009 .get_settings = pcnet32_get_settings,
1010 .set_settings = pcnet32_set_settings,
1011 .get_drvinfo = pcnet32_get_drvinfo,
1012 .get_msglevel = pcnet32_get_msglevel,
1013 .set_msglevel = pcnet32_set_msglevel,
1014 .nway_reset = pcnet32_nway_reset,
1015 .get_link = pcnet32_get_link,
1016 .get_ringparam = pcnet32_get_ringparam,
1017 .set_ringparam = pcnet32_set_ringparam,
1018 .get_tx_csum = ethtool_op_get_tx_csum,
1019 .get_sg = ethtool_op_get_sg,
1020 .get_tso = ethtool_op_get_tso,
1021 .get_strings = pcnet32_get_strings,
1022 .self_test_count = pcnet32_self_test_count,
1023 .self_test = pcnet32_ethtool_test,
1024 .phys_id = pcnet32_phys_id,
1025 .get_regs_len = pcnet32_get_regs_len,
1026 .get_regs = pcnet32_get_regs,
1027 .get_perm_addr = ethtool_op_get_perm_addr,
1028 };
1029
1030 /* only probes for non-PCI devices, the rest are handled by
1031 * pci_register_driver via pcnet32_probe_pci */
1032
1033 static void __devinit
1034 pcnet32_probe_vlbus(void)
1035 {
1036 unsigned int *port, ioaddr;
1037
1038 /* search for PCnet32 VLB cards at known addresses */
1039 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1040 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1041 /* check if there is really a pcnet chip on that ioaddr */
1042 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
1043 pcnet32_probe1(ioaddr, 0, NULL);
1044 } else {
1045 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1046 }
1047 }
1048 }
1049 }
1050
1051
1052 static int __devinit
1053 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1054 {
1055 unsigned long ioaddr;
1056 int err;
1057
1058 err = pci_enable_device(pdev);
1059 if (err < 0) {
1060 if (pcnet32_debug & NETIF_MSG_PROBE)
1061 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
1062 return err;
1063 }
1064 pci_set_master(pdev);
1065
1066 ioaddr = pci_resource_start (pdev, 0);
1067 if (!ioaddr) {
1068 if (pcnet32_debug & NETIF_MSG_PROBE)
1069 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
1070 return -ENODEV;
1071 }
1072
1073 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1074 if (pcnet32_debug & NETIF_MSG_PROBE)
1075 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
1076 return -ENODEV;
1077 }
1078 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
1079 if (pcnet32_debug & NETIF_MSG_PROBE)
1080 printk(KERN_ERR PFX "io address range already allocated\n");
1081 return -EBUSY;
1082 }
1083
1084 err = pcnet32_probe1(ioaddr, 1, pdev);
1085 if (err < 0) {
1086 pci_disable_device(pdev);
1087 }
1088 return err;
1089 }
1090
1091
1092 /* pcnet32_probe1
1093 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1094 * pdev will be NULL when called from pcnet32_probe_vlbus.
1095 */
1096 static int __devinit
1097 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1098 {
1099 struct pcnet32_private *lp;
1100 dma_addr_t lp_dma_addr;
1101 int i, media;
1102 int fdx, mii, fset, dxsuflo;
1103 int chip_version;
1104 char *chipname;
1105 struct net_device *dev;
1106 struct pcnet32_access *a = NULL;
1107 u8 promaddr[6];
1108 int ret = -ENODEV;
1109
1110 /* reset the chip */
1111 pcnet32_wio_reset(ioaddr);
1112
1113 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1114 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1115 a = &pcnet32_wio;
1116 } else {
1117 pcnet32_dwio_reset(ioaddr);
1118 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
1119 a = &pcnet32_dwio;
1120 } else
1121 goto err_release_region;
1122 }
1123
1124 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
1125 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1126 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
1127 if ((chip_version & 0xfff) != 0x003) {
1128 if (pcnet32_debug & NETIF_MSG_PROBE)
1129 printk(KERN_INFO PFX "Unsupported chip version.\n");
1130 goto err_release_region;
1131 }
1132
1133 /* initialize variables */
1134 fdx = mii = fset = dxsuflo = 0;
1135 chip_version = (chip_version >> 12) & 0xffff;
1136
1137 switch (chip_version) {
1138 case 0x2420:
1139 chipname = "PCnet/PCI 79C970"; /* PCI */
1140 break;
1141 case 0x2430:
1142 if (shared)
1143 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1144 else
1145 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1146 break;
1147 case 0x2621:
1148 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1149 fdx = 1;
1150 break;
1151 case 0x2623:
1152 chipname = "PCnet/FAST 79C971"; /* PCI */
1153 fdx = 1; mii = 1; fset = 1;
1154 break;
1155 case 0x2624:
1156 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1157 fdx = 1; mii = 1; fset = 1;
1158 break;
1159 case 0x2625:
1160 chipname = "PCnet/FAST III 79C973"; /* PCI */
1161 fdx = 1; mii = 1;
1162 break;
1163 case 0x2626:
1164 chipname = "PCnet/Home 79C978"; /* PCI */
1165 fdx = 1;
1166 /*
1167 * This is based on specs published at www.amd.com. This section
1168 * assumes that a card with a 79C978 wants to go into standard
1169 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1170 * and the module option homepna=1 can select this instead.
1171 */
1172 media = a->read_bcr(ioaddr, 49);
1173 media &= ~3; /* default to 10Mb ethernet */
1174 if (cards_found < MAX_UNITS && homepna[cards_found])
1175 media |= 1; /* switch to home wiring mode */
1176 if (pcnet32_debug & NETIF_MSG_PROBE)
1177 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1178 (media & 1) ? "1" : "10");
1179 a->write_bcr(ioaddr, 49, media);
1180 break;
1181 case 0x2627:
1182 chipname = "PCnet/FAST III 79C975"; /* PCI */
1183 fdx = 1; mii = 1;
1184 break;
1185 case 0x2628:
1186 chipname = "PCnet/PRO 79C976";
1187 fdx = 1; mii = 1;
1188 break;
1189 default:
1190 if (pcnet32_debug & NETIF_MSG_PROBE)
1191 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
1192 chip_version);
1193 goto err_release_region;
1194 }
1195
1196 /*
1197 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1198 * starting until the packet is loaded. Strike one for reliability, lose
1199 * one for latency - although on PCI this isnt a big loss. Older chips
1200 * have FIFO's smaller than a packet, so you can't do this.
1201 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1202 */
1203
1204 if (fset) {
1205 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1206 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1207 dxsuflo = 1;
1208 }
1209
1210 dev = alloc_etherdev(0);
1211 if (!dev) {
1212 if (pcnet32_debug & NETIF_MSG_PROBE)
1213 printk(KERN_ERR PFX "Memory allocation failed.\n");
1214 ret = -ENOMEM;
1215 goto err_release_region;
1216 }
1217 SET_NETDEV_DEV(dev, &pdev->dev);
1218
1219 if (pcnet32_debug & NETIF_MSG_PROBE)
1220 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1221
1222 /* In most chips, after a chip reset, the ethernet address is read from the
1223 * station address PROM at the base address and programmed into the
1224 * "Physical Address Registers" CSR12-14.
1225 * As a precautionary measure, we read the PROM values and complain if
1226 * they disagree with the CSRs. Either way, we use the CSR values, and
1227 * double check that they are valid.
1228 */
1229 for (i = 0; i < 3; i++) {
1230 unsigned int val;
1231 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
1232 /* There may be endianness issues here. */
1233 dev->dev_addr[2*i] = val & 0x0ff;
1234 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
1235 }
1236
1237 /* read PROM address and compare with CSR address */
1238 for (i = 0; i < 6; i++)
1239 promaddr[i] = inb(ioaddr + i);
1240
1241 if (memcmp(promaddr, dev->dev_addr, 6)
1242 || !is_valid_ether_addr(dev->dev_addr)) {
1243 #ifndef __powerpc__
1244 if (is_valid_ether_addr(promaddr)) {
1245 #else
1246 if (!is_valid_ether_addr(dev->dev_addr)
1247 && is_valid_ether_addr(promaddr)) {
1248 #endif
1249 if (pcnet32_debug & NETIF_MSG_PROBE) {
1250 printk(" warning: CSR address invalid,\n");
1251 printk(KERN_INFO " using instead PROM address of");
1252 }
1253 memcpy(dev->dev_addr, promaddr, 6);
1254 }
1255 }
1256 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1257
1258 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1259 if (!is_valid_ether_addr(dev->perm_addr))
1260 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1261
1262 if (pcnet32_debug & NETIF_MSG_PROBE) {
1263 for (i = 0; i < 6; i++)
1264 printk(" %2.2x", dev->dev_addr[i]);
1265
1266 /* Version 0x2623 and 0x2624 */
1267 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1268 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1269 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
1270 switch(i>>10) {
1271 case 0: printk(" 20 bytes,"); break;
1272 case 1: printk(" 64 bytes,"); break;
1273 case 2: printk(" 128 bytes,"); break;
1274 case 3: printk("~220 bytes,"); break;
1275 }
1276 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1277 printk(" BCR18(%x):",i&0xffff);
1278 if (i & (1<<5)) printk("BurstWrEn ");
1279 if (i & (1<<6)) printk("BurstRdEn ");
1280 if (i & (1<<7)) printk("DWordIO ");
1281 if (i & (1<<11)) printk("NoUFlow ");
1282 i = a->read_bcr(ioaddr, 25);
1283 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
1284 i = a->read_bcr(ioaddr, 26);
1285 printk(" SRAM_BND=0x%04x,",i<<8);
1286 i = a->read_bcr(ioaddr, 27);
1287 if (i & (1<<14)) printk("LowLatRx");
1288 }
1289 }
1290
1291 dev->base_addr = ioaddr;
1292 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1293 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1294 if (pcnet32_debug & NETIF_MSG_PROBE)
1295 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1296 ret = -ENOMEM;
1297 goto err_free_netdev;
1298 }
1299
1300 memset(lp, 0, sizeof(*lp));
1301 lp->dma_addr = lp_dma_addr;
1302 lp->pci_dev = pdev;
1303
1304 spin_lock_init(&lp->lock);
1305
1306 SET_MODULE_OWNER(dev);
1307 SET_NETDEV_DEV(dev, &pdev->dev);
1308 dev->priv = lp;
1309 lp->name = chipname;
1310 lp->shared_irq = shared;
1311 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1312 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1313 lp->tx_mod_mask = lp->tx_ring_size - 1;
1314 lp->rx_mod_mask = lp->rx_ring_size - 1;
1315 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1316 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1317 lp->mii_if.full_duplex = fdx;
1318 lp->mii_if.phy_id_mask = 0x1f;
1319 lp->mii_if.reg_num_mask = 0x1f;
1320 lp->dxsuflo = dxsuflo;
1321 lp->mii = mii;
1322 lp->msg_enable = pcnet32_debug;
1323 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
1324 lp->options = PCNET32_PORT_ASEL;
1325 else
1326 lp->options = options_mapping[options[cards_found]];
1327 lp->mii_if.dev = dev;
1328 lp->mii_if.mdio_read = mdio_read;
1329 lp->mii_if.mdio_write = mdio_write;
1330
1331 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1332 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
1333 lp->options |= PCNET32_PORT_FD;
1334
1335 if (!a) {
1336 if (pcnet32_debug & NETIF_MSG_PROBE)
1337 printk(KERN_ERR PFX "No access methods\n");
1338 ret = -ENODEV;
1339 goto err_free_consistent;
1340 }
1341 lp->a = *a;
1342
1343 if (pcnet32_alloc_ring(dev)) {
1344 ret = -ENOMEM;
1345 goto err_free_ring;
1346 }
1347 /* detect special T1/E1 WAN card by checking for MAC address */
1348 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1349 && dev->dev_addr[2] == 0x75)
1350 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1351
1352 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1353 lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1354 for (i = 0; i < 6; i++)
1355 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1356 lp->init_block.filter[0] = 0x00000000;
1357 lp->init_block.filter[1] = 0x00000000;
1358 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr);
1359 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr);
1360
1361 /* switch pcnet32 to 32bit mode */
1362 a->write_bcr(ioaddr, 20, 2);
1363
1364 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1365 init_block)) & 0xffff);
1366 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1367 init_block)) >> 16);
1368
1369 if (pdev) { /* use the IRQ provided by PCI */
1370 dev->irq = pdev->irq;
1371 if (pcnet32_debug & NETIF_MSG_PROBE)
1372 printk(" assigned IRQ %d.\n", dev->irq);
1373 } else {
1374 unsigned long irq_mask = probe_irq_on();
1375
1376 /*
1377 * To auto-IRQ we enable the initialization-done and DMA error
1378 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1379 * boards will work.
1380 */
1381 /* Trigger an initialization just for the interrupt. */
1382 a->write_csr (ioaddr, 0, 0x41);
1383 mdelay (1);
1384
1385 dev->irq = probe_irq_off (irq_mask);
1386 if (!dev->irq) {
1387 if (pcnet32_debug & NETIF_MSG_PROBE)
1388 printk(", failed to detect IRQ line.\n");
1389 ret = -ENODEV;
1390 goto err_free_ring;
1391 }
1392 if (pcnet32_debug & NETIF_MSG_PROBE)
1393 printk(", probed IRQ %d.\n", dev->irq);
1394 }
1395
1396 /* Set the mii phy_id so that we can query the link state */
1397 if (lp->mii)
1398 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
1399
1400 init_timer (&lp->watchdog_timer);
1401 lp->watchdog_timer.data = (unsigned long) dev;
1402 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
1403
1404 /* The PCNET32-specific entries in the device structure. */
1405 dev->open = &pcnet32_open;
1406 dev->hard_start_xmit = &pcnet32_start_xmit;
1407 dev->stop = &pcnet32_close;
1408 dev->get_stats = &pcnet32_get_stats;
1409 dev->set_multicast_list = &pcnet32_set_multicast_list;
1410 dev->do_ioctl = &pcnet32_ioctl;
1411 dev->ethtool_ops = &pcnet32_ethtool_ops;
1412 dev->tx_timeout = pcnet32_tx_timeout;
1413 dev->watchdog_timeo = (5*HZ);
1414
1415 #ifdef CONFIG_NET_POLL_CONTROLLER
1416 dev->poll_controller = pcnet32_poll_controller;
1417 #endif
1418
1419 /* Fill in the generic fields of the device structure. */
1420 if (register_netdev(dev))
1421 goto err_free_ring;
1422
1423 if (pdev) {
1424 pci_set_drvdata(pdev, dev);
1425 } else {
1426 lp->next = pcnet32_dev;
1427 pcnet32_dev = dev;
1428 }
1429
1430 if (pcnet32_debug & NETIF_MSG_PROBE)
1431 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1432 cards_found++;
1433
1434 /* enable LED writes */
1435 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1436
1437 return 0;
1438
1439 err_free_ring:
1440 pcnet32_free_ring(dev);
1441 err_free_consistent:
1442 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1443 err_free_netdev:
1444 free_netdev(dev);
1445 err_release_region:
1446 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1447 return ret;
1448 }
1449
1450
1451 static int pcnet32_alloc_ring(struct net_device *dev)
1452 {
1453 struct pcnet32_private *lp = dev->priv;
1454
1455 if ((lp->tx_ring = pci_alloc_consistent(lp->pci_dev, sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
1456 &lp->tx_ring_dma_addr)) == NULL) {
1457 if (pcnet32_debug & NETIF_MSG_DRV)
1458 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1459 return -ENOMEM;
1460 }
1461
1462 if ((lp->rx_ring = pci_alloc_consistent(lp->pci_dev, sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
1463 &lp->rx_ring_dma_addr)) == NULL) {
1464 if (pcnet32_debug & NETIF_MSG_DRV)
1465 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1466 return -ENOMEM;
1467 }
1468
1469 if (!(lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size, GFP_ATOMIC))) {
1470 if (pcnet32_debug & NETIF_MSG_DRV)
1471 printk(KERN_ERR PFX "Memory allocation failed.\n");
1472 return -ENOMEM;
1473 }
1474 memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size);
1475
1476 if (!(lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size, GFP_ATOMIC))) {
1477 if (pcnet32_debug & NETIF_MSG_DRV)
1478 printk(KERN_ERR PFX "Memory allocation failed.\n");
1479 return -ENOMEM;
1480 }
1481 memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size);
1482
1483 if (!(lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size, GFP_ATOMIC))) {
1484 if (pcnet32_debug & NETIF_MSG_DRV)
1485 printk(KERN_ERR PFX "Memory allocation failed.\n");
1486 return -ENOMEM;
1487 }
1488 memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size);
1489
1490 if (!(lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size, GFP_ATOMIC))) {
1491 if (pcnet32_debug & NETIF_MSG_DRV)
1492 printk(KERN_ERR PFX "Memory allocation failed.\n");
1493 return -ENOMEM;
1494 }
1495 memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size);
1496
1497 return 0;
1498 }
1499
1500
1501 static void pcnet32_free_ring(struct net_device *dev)
1502 {
1503 struct pcnet32_private *lp = dev->priv;
1504
1505 kfree(lp->tx_skbuff);
1506 lp->tx_skbuff = NULL;
1507
1508 kfree(lp->rx_skbuff);
1509 lp->rx_skbuff = NULL;
1510
1511 kfree(lp->tx_dma_addr);
1512 lp->tx_dma_addr = NULL;
1513
1514 kfree(lp->rx_dma_addr);
1515 lp->rx_dma_addr = NULL;
1516
1517 if (lp->tx_ring) {
1518 pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
1519 lp->tx_ring, lp->tx_ring_dma_addr);
1520 lp->tx_ring = NULL;
1521 }
1522
1523 if (lp->rx_ring) {
1524 pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
1525 lp->rx_ring, lp->rx_ring_dma_addr);
1526 lp->rx_ring = NULL;
1527 }
1528 }
1529
1530
1531 static int
1532 pcnet32_open(struct net_device *dev)
1533 {
1534 struct pcnet32_private *lp = dev->priv;
1535 unsigned long ioaddr = dev->base_addr;
1536 u16 val;
1537 int i;
1538 int rc;
1539 unsigned long flags;
1540
1541 if (request_irq(dev->irq, &pcnet32_interrupt,
1542 lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {
1543 return -EAGAIN;
1544 }
1545
1546 spin_lock_irqsave(&lp->lock, flags);
1547 /* Check for a valid station address */
1548 if (!is_valid_ether_addr(dev->dev_addr)) {
1549 rc = -EINVAL;
1550 goto err_free_irq;
1551 }
1552
1553 /* Reset the PCNET32 */
1554 lp->a.reset (ioaddr);
1555
1556 /* switch pcnet32 to 32bit mode */
1557 lp->a.write_bcr (ioaddr, 20, 2);
1558
1559 if (netif_msg_ifup(lp))
1560 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1561 dev->name, dev->irq,
1562 (u32) (lp->tx_ring_dma_addr),
1563 (u32) (lp->rx_ring_dma_addr),
1564 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
1565
1566 /* set/reset autoselect bit */
1567 val = lp->a.read_bcr (ioaddr, 2) & ~2;
1568 if (lp->options & PCNET32_PORT_ASEL)
1569 val |= 2;
1570 lp->a.write_bcr (ioaddr, 2, val);
1571
1572 /* handle full duplex setting */
1573 if (lp->mii_if.full_duplex) {
1574 val = lp->a.read_bcr (ioaddr, 9) & ~3;
1575 if (lp->options & PCNET32_PORT_FD) {
1576 val |= 1;
1577 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1578 val |= 2;
1579 } else if (lp->options & PCNET32_PORT_ASEL) {
1580 /* workaround of xSeries250, turn on for 79C975 only */
1581 i = ((lp->a.read_csr(ioaddr, 88) |
1582 (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
1583 if (i == 0x2627)
1584 val |= 3;
1585 }
1586 lp->a.write_bcr (ioaddr, 9, val);
1587 }
1588
1589 /* set/reset GPSI bit in test register */
1590 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
1591 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1592 val |= 0x10;
1593 lp->a.write_csr (ioaddr, 124, val);
1594
1595 /* Allied Telesyn AT 2700/2701 FX looses the link, so skip that */
1596 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
1597 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1598 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
1599 printk(KERN_DEBUG "%s: Skipping PHY selection.\n", dev->name);
1600 } else {
1601 /*
1602 * 24 Jun 2004 according AMD, in order to change the PHY,
1603 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1604 * duplex, and/or enable auto negotiation, and clear DANAS
1605 */
1606 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1607 lp->a.write_bcr(ioaddr, 32,
1608 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1609 /* disable Auto Negotiation, set 10Mpbs, HD */
1610 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1611 if (lp->options & PCNET32_PORT_FD)
1612 val |= 0x10;
1613 if (lp->options & PCNET32_PORT_100)
1614 val |= 0x08;
1615 lp->a.write_bcr (ioaddr, 32, val);
1616 } else {
1617 if (lp->options & PCNET32_PORT_ASEL) {
1618 lp->a.write_bcr(ioaddr, 32,
1619 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1620 /* enable auto negotiate, setup, disable fd */
1621 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1622 val |= 0x20;
1623 lp->a.write_bcr(ioaddr, 32, val);
1624 }
1625 }
1626 }
1627
1628 #ifdef DO_DXSUFLO
1629 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1630 val = lp->a.read_csr (ioaddr, 3);
1631 val |= 0x40;
1632 lp->a.write_csr (ioaddr, 3, val);
1633 }
1634 #endif
1635
1636 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1637 pcnet32_load_multicast(dev);
1638
1639 if (pcnet32_init_ring(dev)) {
1640 rc = -ENOMEM;
1641 goto err_free_ring;
1642 }
1643
1644 /* Re-initialize the PCNET32, and start it when done. */
1645 lp->a.write_csr (ioaddr, 1, (lp->dma_addr +
1646 offsetof(struct pcnet32_private, init_block)) & 0xffff);
1647 lp->a.write_csr (ioaddr, 2, (lp->dma_addr +
1648 offsetof(struct pcnet32_private, init_block)) >> 16);
1649
1650 lp->a.write_csr (ioaddr, 4, 0x0915);
1651 lp->a.write_csr (ioaddr, 0, 0x0001);
1652
1653 netif_start_queue(dev);
1654
1655 /* If we have mii, print the link status and start the watchdog */
1656 if (lp->mii) {
1657 mii_check_media (&lp->mii_if, netif_msg_link(lp), 1);
1658 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1659 }
1660
1661 i = 0;
1662 while (i++ < 100)
1663 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1664 break;
1665 /*
1666 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1667 * reports that doing so triggers a bug in the '974.
1668 */
1669 lp->a.write_csr (ioaddr, 0, 0x0042);
1670
1671 if (netif_msg_ifup(lp))
1672 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1673 dev->name, i, (u32) (lp->dma_addr +
1674 offsetof(struct pcnet32_private, init_block)),
1675 lp->a.read_csr(ioaddr, 0));
1676
1677 spin_unlock_irqrestore(&lp->lock, flags);
1678
1679 return 0; /* Always succeed */
1680
1681 err_free_ring:
1682 /* free any allocated skbuffs */
1683 for (i = 0; i < lp->rx_ring_size; i++) {
1684 lp->rx_ring[i].status = 0;
1685 if (lp->rx_skbuff[i]) {
1686 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1687 PCI_DMA_FROMDEVICE);
1688 dev_kfree_skb(lp->rx_skbuff[i]);
1689 }
1690 lp->rx_skbuff[i] = NULL;
1691 lp->rx_dma_addr[i] = 0;
1692 }
1693
1694 pcnet32_free_ring(dev);
1695
1696 /*
1697 * Switch back to 16bit mode to avoid problems with dumb
1698 * DOS packet driver after a warm reboot
1699 */
1700 lp->a.write_bcr (ioaddr, 20, 4);
1701
1702 err_free_irq:
1703 spin_unlock_irqrestore(&lp->lock, flags);
1704 free_irq(dev->irq, dev);
1705 return rc;
1706 }
1707
1708 /*
1709 * The LANCE has been halted for one reason or another (busmaster memory
1710 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1711 * etc.). Modern LANCE variants always reload their ring-buffer
1712 * configuration when restarted, so we must reinitialize our ring
1713 * context before restarting. As part of this reinitialization,
1714 * find all packets still on the Tx ring and pretend that they had been
1715 * sent (in effect, drop the packets on the floor) - the higher-level
1716 * protocols will time out and retransmit. It'd be better to shuffle
1717 * these skbs to a temp list and then actually re-Tx them after
1718 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1719 */
1720
1721 static void
1722 pcnet32_purge_tx_ring(struct net_device *dev)
1723 {
1724 struct pcnet32_private *lp = dev->priv;
1725 int i;
1726
1727 for (i = 0; i < lp->tx_ring_size; i++) {
1728 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1729 wmb(); /* Make sure adapter sees owner change */
1730 if (lp->tx_skbuff[i]) {
1731 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1732 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1733 dev_kfree_skb_any(lp->tx_skbuff[i]);
1734 }
1735 lp->tx_skbuff[i] = NULL;
1736 lp->tx_dma_addr[i] = 0;
1737 }
1738 }
1739
1740
1741 /* Initialize the PCNET32 Rx and Tx rings. */
1742 static int
1743 pcnet32_init_ring(struct net_device *dev)
1744 {
1745 struct pcnet32_private *lp = dev->priv;
1746 int i;
1747
1748 lp->tx_full = 0;
1749 lp->cur_rx = lp->cur_tx = 0;
1750 lp->dirty_rx = lp->dirty_tx = 0;
1751
1752 for (i = 0; i < lp->rx_ring_size; i++) {
1753 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1754 if (rx_skbuff == NULL) {
1755 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1756 /* there is not much, we can do at this point */
1757 if (pcnet32_debug & NETIF_MSG_DRV)
1758 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1759 dev->name);
1760 return -1;
1761 }
1762 skb_reserve (rx_skbuff, 2);
1763 }
1764
1765 rmb();
1766 if (lp->rx_dma_addr[i] == 0)
1767 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->data,
1768 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1769 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1770 lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1771 wmb(); /* Make sure owner changes after all others are visible */
1772 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1773 }
1774 /* The Tx buffer address is filled in as needed, but we do need to clear
1775 * the upper ownership bit. */
1776 for (i = 0; i < lp->tx_ring_size; i++) {
1777 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1778 wmb(); /* Make sure adapter sees owner change */
1779 lp->tx_ring[i].base = 0;
1780 lp->tx_dma_addr[i] = 0;
1781 }
1782
1783 lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1784 for (i = 0; i < 6; i++)
1785 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1786 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr);
1787 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr);
1788 wmb(); /* Make sure all changes are visible */
1789 return 0;
1790 }
1791
1792 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1793 * then flush the pending transmit operations, re-initialize the ring,
1794 * and tell the chip to initialize.
1795 */
1796 static void
1797 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1798 {
1799 struct pcnet32_private *lp = dev->priv;
1800 unsigned long ioaddr = dev->base_addr;
1801 int i;
1802
1803 /* wait for stop */
1804 for (i=0; i<100; i++)
1805 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
1806 break;
1807
1808 if (i >= 100 && netif_msg_drv(lp))
1809 printk(KERN_ERR "%s: pcnet32_restart timed out waiting for stop.\n",
1810 dev->name);
1811
1812 pcnet32_purge_tx_ring(dev);
1813 if (pcnet32_init_ring(dev))
1814 return;
1815
1816 /* ReInit Ring */
1817 lp->a.write_csr (ioaddr, 0, 1);
1818 i = 0;
1819 while (i++ < 1000)
1820 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1821 break;
1822
1823 lp->a.write_csr (ioaddr, 0, csr0_bits);
1824 }
1825
1826
1827 static void
1828 pcnet32_tx_timeout (struct net_device *dev)
1829 {
1830 struct pcnet32_private *lp = dev->priv;
1831 unsigned long ioaddr = dev->base_addr, flags;
1832
1833 spin_lock_irqsave(&lp->lock, flags);
1834 /* Transmitter timeout, serious problems. */
1835 if (pcnet32_debug & NETIF_MSG_DRV)
1836 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1837 dev->name, lp->a.read_csr(ioaddr, 0));
1838 lp->a.write_csr (ioaddr, 0, 0x0004);
1839 lp->stats.tx_errors++;
1840 if (netif_msg_tx_err(lp)) {
1841 int i;
1842 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1843 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1844 lp->cur_rx);
1845 for (i = 0 ; i < lp->rx_ring_size; i++)
1846 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1847 le32_to_cpu(lp->rx_ring[i].base),
1848 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 0xffff,
1849 le32_to_cpu(lp->rx_ring[i].msg_length),
1850 le16_to_cpu(lp->rx_ring[i].status));
1851 for (i = 0 ; i < lp->tx_ring_size; i++)
1852 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1853 le32_to_cpu(lp->tx_ring[i].base),
1854 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
1855 le32_to_cpu(lp->tx_ring[i].misc),
1856 le16_to_cpu(lp->tx_ring[i].status));
1857 printk("\n");
1858 }
1859 pcnet32_restart(dev, 0x0042);
1860
1861 dev->trans_start = jiffies;
1862 netif_wake_queue(dev);
1863
1864 spin_unlock_irqrestore(&lp->lock, flags);
1865 }
1866
1867
1868 static int
1869 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1870 {
1871 struct pcnet32_private *lp = dev->priv;
1872 unsigned long ioaddr = dev->base_addr;
1873 u16 status;
1874 int entry;
1875 unsigned long flags;
1876
1877 spin_lock_irqsave(&lp->lock, flags);
1878
1879 if (netif_msg_tx_queued(lp)) {
1880 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1881 dev->name, lp->a.read_csr(ioaddr, 0));
1882 }
1883
1884 /* Default status -- will not enable Successful-TxDone
1885 * interrupt when that option is available to us.
1886 */
1887 status = 0x8300;
1888
1889 /* Fill in a Tx ring entry */
1890
1891 /* Mask to ring buffer boundary. */
1892 entry = lp->cur_tx & lp->tx_mod_mask;
1893
1894 /* Caution: the write order is important here, set the status
1895 * with the "ownership" bits last. */
1896
1897 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1898
1899 lp->tx_ring[entry].misc = 0x00000000;
1900
1901 lp->tx_skbuff[entry] = skb;
1902 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len,
1903 PCI_DMA_TODEVICE);
1904 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1905 wmb(); /* Make sure owner changes after all others are visible */
1906 lp->tx_ring[entry].status = le16_to_cpu(status);
1907
1908 lp->cur_tx++;
1909 lp->stats.tx_bytes += skb->len;
1910
1911 /* Trigger an immediate send poll. */
1912 lp->a.write_csr (ioaddr, 0, 0x0048);
1913
1914 dev->trans_start = jiffies;
1915
1916 if (lp->tx_ring[(entry+1) & lp->tx_mod_mask].base != 0) {
1917 lp->tx_full = 1;
1918 netif_stop_queue(dev);
1919 }
1920 spin_unlock_irqrestore(&lp->lock, flags);
1921 return 0;
1922 }
1923
1924 /* The PCNET32 interrupt handler. */
1925 static irqreturn_t
1926 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1927 {
1928 struct net_device *dev = dev_id;
1929 struct pcnet32_private *lp;
1930 unsigned long ioaddr;
1931 u16 csr0,rap;
1932 int boguscnt = max_interrupt_work;
1933 int must_restart;
1934
1935 if (!dev) {
1936 if (pcnet32_debug & NETIF_MSG_INTR)
1937 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1938 __FUNCTION__, irq);
1939 return IRQ_NONE;
1940 }
1941
1942 ioaddr = dev->base_addr;
1943 lp = dev->priv;
1944
1945 spin_lock(&lp->lock);
1946
1947 rap = lp->a.read_rap(ioaddr);
1948 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
1949 if (csr0 == 0xffff) {
1950 break; /* PCMCIA remove happened */
1951 }
1952 /* Acknowledge all of the current interrupt sources ASAP. */
1953 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1954
1955 must_restart = 0;
1956
1957 if (netif_msg_intr(lp))
1958 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1959 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1960
1961 if (csr0 & 0x0400) /* Rx interrupt */
1962 pcnet32_rx(dev);
1963
1964 if (csr0 & 0x0200) { /* Tx-done interrupt */
1965 unsigned int dirty_tx = lp->dirty_tx;
1966 int delta;
1967
1968 while (dirty_tx != lp->cur_tx) {
1969 int entry = dirty_tx & lp->tx_mod_mask;
1970 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1971
1972 if (status < 0)
1973 break; /* It still hasn't been Txed */
1974
1975 lp->tx_ring[entry].base = 0;
1976
1977 if (status & 0x4000) {
1978 /* There was an major error, log it. */
1979 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1980 lp->stats.tx_errors++;
1981 if (netif_msg_tx_err(lp))
1982 printk(KERN_ERR "%s: Tx error status=%04x err_status=%08x\n",
1983 dev->name, status, err_status);
1984 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1985 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1986 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1987 #ifndef DO_DXSUFLO
1988 if (err_status & 0x40000000) {
1989 lp->stats.tx_fifo_errors++;
1990 /* Ackk! On FIFO errors the Tx unit is turned off! */
1991 /* Remove this verbosity later! */
1992 if (netif_msg_tx_err(lp))
1993 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1994 dev->name, csr0);
1995 must_restart = 1;
1996 }
1997 #else
1998 if (err_status & 0x40000000) {
1999 lp->stats.tx_fifo_errors++;
2000 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
2001 /* Ackk! On FIFO errors the Tx unit is turned off! */
2002 /* Remove this verbosity later! */
2003 if (netif_msg_tx_err(lp))
2004 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
2005 dev->name, csr0);
2006 must_restart = 1;
2007 }
2008 }
2009 #endif
2010 } else {
2011 if (status & 0x1800)
2012 lp->stats.collisions++;
2013 lp->stats.tx_packets++;
2014 }
2015
2016 /* We must free the original skb */
2017 if (lp->tx_skbuff[entry]) {
2018 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
2019 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
2020 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2021 lp->tx_skbuff[entry] = NULL;
2022 lp->tx_dma_addr[entry] = 0;
2023 }
2024 dirty_tx++;
2025 }
2026
2027 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
2028 if (delta > lp->tx_ring_size) {
2029 if (netif_msg_drv(lp))
2030 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2031 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
2032 dirty_tx += lp->tx_ring_size;
2033 delta -= lp->tx_ring_size;
2034 }
2035
2036 if (lp->tx_full &&
2037 netif_queue_stopped(dev) &&
2038 delta < lp->tx_ring_size - 2) {
2039 /* The ring is no longer full, clear tbusy. */
2040 lp->tx_full = 0;
2041 netif_wake_queue (dev);
2042 }
2043 lp->dirty_tx = dirty_tx;
2044 }
2045
2046 /* Log misc errors. */
2047 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
2048 if (csr0 & 0x1000) {
2049 /*
2050 * this happens when our receive ring is full. This shouldn't
2051 * be a problem as we will see normal rx interrupts for the frames
2052 * in the receive ring. But there are some PCI chipsets (I can
2053 * reproduce this on SP3G with Intel saturn chipset) which have
2054 * sometimes problems and will fill up the receive ring with
2055 * error descriptors. In this situation we don't get a rx
2056 * interrupt, but a missed frame interrupt sooner or later.
2057 * So we try to clean up our receive ring here.
2058 */
2059 pcnet32_rx(dev);
2060 lp->stats.rx_errors++; /* Missed a Rx frame. */
2061 }
2062 if (csr0 & 0x0800) {
2063 if (netif_msg_drv(lp))
2064 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
2065 dev->name, csr0);
2066 /* unlike for the lance, there is no restart needed */
2067 }
2068
2069 if (must_restart) {
2070 /* reset the chip to clear the error condition, then restart */
2071 lp->a.reset(ioaddr);
2072 lp->a.write_csr(ioaddr, 4, 0x0915);
2073 pcnet32_restart(dev, 0x0002);
2074 netif_wake_queue(dev);
2075 }
2076 }
2077
2078 /* Set interrupt enable. */
2079 lp->a.write_csr (ioaddr, 0, 0x0040);
2080 lp->a.write_rap (ioaddr,rap);
2081
2082 if (netif_msg_intr(lp))
2083 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2084 dev->name, lp->a.read_csr (ioaddr, 0));
2085
2086 spin_unlock(&lp->lock);
2087
2088 return IRQ_HANDLED;
2089 }
2090
2091 static int
2092 pcnet32_rx(struct net_device *dev)
2093 {
2094 struct pcnet32_private *lp = dev->priv;
2095 int entry = lp->cur_rx & lp->rx_mod_mask;
2096 int boguscnt = lp->rx_ring_size / 2;
2097
2098 /* If we own the next entry, it's a new packet. Send it up. */
2099 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2100 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2101
2102 if (status != 0x03) { /* There was an error. */
2103 /*
2104 * There is a tricky error noted by John Murphy,
2105 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2106 * buffers it's possible for a jabber packet to use two
2107 * buffers, with only the last correctly noting the error.
2108 */
2109 if (status & 0x01) /* Only count a general error at the */
2110 lp->stats.rx_errors++; /* end of a packet.*/
2111 if (status & 0x20) lp->stats.rx_frame_errors++;
2112 if (status & 0x10) lp->stats.rx_over_errors++;
2113 if (status & 0x08) lp->stats.rx_crc_errors++;
2114 if (status & 0x04) lp->stats.rx_fifo_errors++;
2115 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
2116 } else {
2117 /* Malloc up new buffer, compatible with net-2e. */
2118 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
2119 struct sk_buff *skb;
2120
2121 /* Discard oversize frames. */
2122 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2123 if (netif_msg_drv(lp))
2124 printk(KERN_ERR "%s: Impossible packet size %d!\n",
2125 dev->name, pkt_len);
2126 lp->stats.rx_errors++;
2127 } else if (pkt_len < 60) {
2128 if (netif_msg_rx_err(lp))
2129 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
2130 lp->stats.rx_errors++;
2131 } else {
2132 int rx_in_place = 0;
2133
2134 if (pkt_len > rx_copybreak) {
2135 struct sk_buff *newskb;
2136
2137 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
2138 skb_reserve (newskb, 2);
2139 skb = lp->rx_skbuff[entry];
2140 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry],
2141 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
2142 skb_put (skb, pkt_len);
2143 lp->rx_skbuff[entry] = newskb;
2144 newskb->dev = dev;
2145 lp->rx_dma_addr[entry] =
2146 pci_map_single(lp->pci_dev, newskb->data,
2147 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
2148 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
2149 rx_in_place = 1;
2150 } else
2151 skb = NULL;
2152 } else {
2153 skb = dev_alloc_skb(pkt_len+2);
2154 }
2155
2156 if (skb == NULL) {
2157 int i;
2158 if (netif_msg_drv(lp))
2159 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n",
2160 dev->name);
2161 for (i = 0; i < lp->rx_ring_size; i++)
2162 if ((short)le16_to_cpu(lp->rx_ring[(entry+i)
2163 & lp->rx_mod_mask].status) < 0)
2164 break;
2165
2166 if (i > lp->rx_ring_size -2) {
2167 lp->stats.rx_dropped++;
2168 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2169 wmb(); /* Make sure adapter sees owner change */
2170 lp->cur_rx++;
2171 }
2172 break;
2173 }
2174 skb->dev = dev;
2175 if (!rx_in_place) {
2176 skb_reserve(skb,2); /* 16 byte align */
2177 skb_put(skb,pkt_len); /* Make room */
2178 pci_dma_sync_single_for_cpu(lp->pci_dev,
2179 lp->rx_dma_addr[entry],
2180 PKT_BUF_SZ-2,
2181 PCI_DMA_FROMDEVICE);
2182 eth_copy_and_sum(skb,
2183 (unsigned char *)(lp->rx_skbuff[entry]->data),
2184 pkt_len,0);
2185 pci_dma_sync_single_for_device(lp->pci_dev,
2186 lp->rx_dma_addr[entry],
2187 PKT_BUF_SZ-2,
2188 PCI_DMA_FROMDEVICE);
2189 }
2190 lp->stats.rx_bytes += skb->len;
2191 skb->protocol=eth_type_trans(skb,dev);
2192 netif_rx(skb);
2193 dev->last_rx = jiffies;
2194 lp->stats.rx_packets++;
2195 }
2196 }
2197 /*
2198 * The docs say that the buffer length isn't touched, but Andrew Boyd
2199 * of QNX reports that some revs of the 79C965 clear it.
2200 */
2201 lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
2202 wmb(); /* Make sure owner changes after all others are visible */
2203 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2204 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2205 if (--boguscnt <= 0) break; /* don't stay in loop forever */
2206 }
2207
2208 return 0;
2209 }
2210
2211 static int
2212 pcnet32_close(struct net_device *dev)
2213 {
2214 unsigned long ioaddr = dev->base_addr;
2215 struct pcnet32_private *lp = dev->priv;
2216 int i;
2217 unsigned long flags;
2218
2219 del_timer_sync(&lp->watchdog_timer);
2220
2221 netif_stop_queue(dev);
2222
2223 spin_lock_irqsave(&lp->lock, flags);
2224
2225 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2226
2227 if (netif_msg_ifdown(lp))
2228 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
2229 dev->name, lp->a.read_csr (ioaddr, 0));
2230
2231 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2232 lp->a.write_csr (ioaddr, 0, 0x0004);
2233
2234 /*
2235 * Switch back to 16bit mode to avoid problems with dumb
2236 * DOS packet driver after a warm reboot
2237 */
2238 lp->a.write_bcr (ioaddr, 20, 4);
2239
2240 spin_unlock_irqrestore(&lp->lock, flags);
2241
2242 free_irq(dev->irq, dev);
2243
2244 spin_lock_irqsave(&lp->lock, flags);
2245
2246 /* free all allocated skbuffs */
2247 for (i = 0; i < lp->rx_ring_size; i++) {
2248 lp->rx_ring[i].status = 0;
2249 wmb(); /* Make sure adapter sees owner change */
2250 if (lp->rx_skbuff[i]) {
2251 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
2252 PCI_DMA_FROMDEVICE);
2253 dev_kfree_skb(lp->rx_skbuff[i]);
2254 }
2255 lp->rx_skbuff[i] = NULL;
2256 lp->rx_dma_addr[i] = 0;
2257 }
2258
2259 for (i = 0; i < lp->tx_ring_size; i++) {
2260 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2261 wmb(); /* Make sure adapter sees owner change */
2262 if (lp->tx_skbuff[i]) {
2263 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2264 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
2265 dev_kfree_skb(lp->tx_skbuff[i]);
2266 }
2267 lp->tx_skbuff[i] = NULL;
2268 lp->tx_dma_addr[i] = 0;
2269 }
2270
2271 spin_unlock_irqrestore(&lp->lock, flags);
2272
2273 return 0;
2274 }
2275
2276 static struct net_device_stats *
2277 pcnet32_get_stats(struct net_device *dev)
2278 {
2279 struct pcnet32_private *lp = dev->priv;
2280 unsigned long ioaddr = dev->base_addr;
2281 u16 saved_addr;
2282 unsigned long flags;
2283
2284 spin_lock_irqsave(&lp->lock, flags);
2285 saved_addr = lp->a.read_rap(ioaddr);
2286 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2287 lp->a.write_rap(ioaddr, saved_addr);
2288 spin_unlock_irqrestore(&lp->lock, flags);
2289
2290 return &lp->stats;
2291 }
2292
2293 /* taken from the sunlance driver, which it took from the depca driver */
2294 static void pcnet32_load_multicast (struct net_device *dev)
2295 {
2296 struct pcnet32_private *lp = dev->priv;
2297 volatile struct pcnet32_init_block *ib = &lp->init_block;
2298 volatile u16 *mcast_table = (u16 *)&ib->filter;
2299 struct dev_mc_list *dmi=dev->mc_list;
2300 char *addrs;
2301 int i;
2302 u32 crc;
2303
2304 /* set all multicast bits */
2305 if (dev->flags & IFF_ALLMULTI) {
2306 ib->filter[0] = 0xffffffff;
2307 ib->filter[1] = 0xffffffff;
2308 return;
2309 }
2310 /* clear the multicast filter */
2311 ib->filter[0] = 0;
2312 ib->filter[1] = 0;
2313
2314 /* Add addresses */
2315 for (i = 0; i < dev->mc_count; i++) {
2316 addrs = dmi->dmi_addr;
2317 dmi = dmi->next;
2318
2319 /* multicast address? */
2320 if (!(*addrs & 1))
2321 continue;
2322
2323 crc = ether_crc_le(6, addrs);
2324 crc = crc >> 26;
2325 mcast_table [crc >> 4] = le16_to_cpu(
2326 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf)));
2327 }
2328 return;
2329 }
2330
2331
2332 /*
2333 * Set or clear the multicast filter for this adaptor.
2334 */
2335 static void pcnet32_set_multicast_list(struct net_device *dev)
2336 {
2337 unsigned long ioaddr = dev->base_addr, flags;
2338 struct pcnet32_private *lp = dev->priv;
2339
2340 spin_lock_irqsave(&lp->lock, flags);
2341 if (dev->flags&IFF_PROMISC) {
2342 /* Log any net taps. */
2343 if (netif_msg_hw(lp))
2344 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2345 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
2346 } else {
2347 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2348 pcnet32_load_multicast (dev);
2349 }
2350
2351 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2352 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2353 netif_wake_queue(dev);
2354
2355 spin_unlock_irqrestore(&lp->lock, flags);
2356 }
2357
2358 /* This routine assumes that the lp->lock is held */
2359 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2360 {
2361 struct pcnet32_private *lp = dev->priv;
2362 unsigned long ioaddr = dev->base_addr;
2363 u16 val_out;
2364
2365 if (!lp->mii)
2366 return 0;
2367
2368 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2369 val_out = lp->a.read_bcr(ioaddr, 34);
2370
2371 return val_out;
2372 }
2373
2374 /* This routine assumes that the lp->lock is held */
2375 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2376 {
2377 struct pcnet32_private *lp = dev->priv;
2378 unsigned long ioaddr = dev->base_addr;
2379
2380 if (!lp->mii)
2381 return;
2382
2383 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2384 lp->a.write_bcr(ioaddr, 34, val);
2385 }
2386
2387 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2388 {
2389 struct pcnet32_private *lp = dev->priv;
2390 int rc;
2391 unsigned long flags;
2392
2393 /* SIOC[GS]MIIxxx ioctls */
2394 if (lp->mii) {
2395 spin_lock_irqsave(&lp->lock, flags);
2396 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2397 spin_unlock_irqrestore(&lp->lock, flags);
2398 } else {
2399 rc = -EOPNOTSUPP;
2400 }
2401
2402 return rc;
2403 }
2404
2405 static void pcnet32_watchdog(struct net_device *dev)
2406 {
2407 struct pcnet32_private *lp = dev->priv;
2408 unsigned long flags;
2409
2410 /* Print the link status if it has changed */
2411 if (lp->mii) {
2412 spin_lock_irqsave(&lp->lock, flags);
2413 mii_check_media (&lp->mii_if, netif_msg_link(lp), 0);
2414 spin_unlock_irqrestore(&lp->lock, flags);
2415 }
2416
2417 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2418 }
2419
2420 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2421 {
2422 struct net_device *dev = pci_get_drvdata(pdev);
2423
2424 if (dev) {
2425 struct pcnet32_private *lp = dev->priv;
2426
2427 unregister_netdev(dev);
2428 pcnet32_free_ring(dev);
2429 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2430 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2431 free_netdev(dev);
2432 pci_disable_device(pdev);
2433 pci_set_drvdata(pdev, NULL);
2434 }
2435 }
2436
2437 static struct pci_driver pcnet32_driver = {
2438 .name = DRV_NAME,
2439 .probe = pcnet32_probe_pci,
2440 .remove = __devexit_p(pcnet32_remove_one),
2441 .id_table = pcnet32_pci_tbl,
2442 };
2443
2444 /* An additional parameter that may be passed in... */
2445 static int debug = -1;
2446 static int tx_start_pt = -1;
2447 static int pcnet32_have_pci;
2448
2449 module_param(debug, int, 0);
2450 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2451 module_param(max_interrupt_work, int, 0);
2452 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
2453 module_param(rx_copybreak, int, 0);
2454 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2455 module_param(tx_start_pt, int, 0);
2456 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2457 module_param(pcnet32vlb, int, 0);
2458 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2459 module_param_array(options, int, NULL, 0);
2460 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2461 module_param_array(full_duplex, int, NULL, 0);
2462 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2463 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2464 module_param_array(homepna, int, NULL, 0);
2465 MODULE_PARM_DESC(homepna, DRV_NAME " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2466
2467 MODULE_AUTHOR("Thomas Bogendoerfer");
2468 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2469 MODULE_LICENSE("GPL");
2470
2471 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2472
2473 static int __init pcnet32_init_module(void)
2474 {
2475 printk(KERN_INFO "%s", version);
2476
2477 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2478
2479 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2480 tx_start = tx_start_pt;
2481
2482 /* find the PCI devices */
2483 if (!pci_module_init(&pcnet32_driver))
2484 pcnet32_have_pci = 1;
2485
2486 /* should we find any remaining VLbus devices ? */
2487 if (pcnet32vlb)
2488 pcnet32_probe_vlbus();
2489
2490 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2491 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2492
2493 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2494 }
2495
2496 static void __exit pcnet32_cleanup_module(void)
2497 {
2498 struct net_device *next_dev;
2499
2500 while (pcnet32_dev) {
2501 struct pcnet32_private *lp = pcnet32_dev->priv;
2502 next_dev = lp->next;
2503 unregister_netdev(pcnet32_dev);
2504 pcnet32_free_ring(pcnet32_dev);
2505 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2506 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2507 free_netdev(pcnet32_dev);
2508 pcnet32_dev = next_dev;
2509 }
2510
2511 if (pcnet32_have_pci)
2512 pci_unregister_driver(&pcnet32_driver);
2513 }
2514
2515 module_init(pcnet32_init_module);
2516 module_exit(pcnet32_cleanup_module);
2517
2518 /*
2519 * Local variables:
2520 * c-indent-level: 4
2521 * tab-width: 8
2522 * End:
2523 */
Linux kernel - Deliverables
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