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[PATCH] pcnet32: support boards with multiple phys
[deliverable/linux.git] / drivers / net / pcnet32.c
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
28
29 static const char * const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
51
52 #include <asm/dma.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/irq.h>
56
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
62 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
63 /*
64 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
65 * the incorrect vendor id.
66 */
67 { PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID,
68 PCI_CLASS_NETWORK_ETHERNET << 8, 0xffff00, 0 },
69 { 0, }
70 };
71
72 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
73
74 static int cards_found;
75
76 /*
77 * VLB I/O addresses
78 */
79 static unsigned int pcnet32_portlist[] __initdata =
80 { 0x300, 0x320, 0x340, 0x360, 0 };
81
82
83
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
87
88 static struct net_device *pcnet32_dev;
89
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
92
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
97
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
102
103 #define PCNET32_DMA_MASK 0xffffffff
104
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_ASEL /* 15 not supported */
129 };
130
131 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
132 "Loopback test (offline)"
133 };
134 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
135
136 #define PCNET32_NUM_REGS 136
137
138 #define MAX_UNITS 8 /* More are supported, limit only on options */
139 static int options[MAX_UNITS];
140 static int full_duplex[MAX_UNITS];
141 static int homepna[MAX_UNITS];
142
143 /*
144 * Theory of Operation
145 *
146 * This driver uses the same software structure as the normal lance
147 * driver. So look for a verbose description in lance.c. The differences
148 * to the normal lance driver is the use of the 32bit mode of PCnet32
149 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
150 * 16MB limitation and we don't need bounce buffers.
151 */
152
153 /*
154 * History:
155 * v0.01: Initial version
156 * only tested on Alpha Noname Board
157 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
158 * tested on a ASUS SP3G
159 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
160 * looks like the 974 doesn't like stopping and restarting in a
161 * short period of time; now we do a reinit of the lance; the
162 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
163 * and hangs the machine (thanks to Klaus Liedl for debugging)
164 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
165 * made it standalone (no need for lance.c)
166 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
167 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
168 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
169 * v0.15: added 79C965 (VLB) probe
170 * added interrupt sharing for PCI chips
171 * v0.16: fixed set_multicast_list on Alpha machines
172 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
173 * v0.19: changed setting of autoselect bit
174 * v0.20: removed additional Compaq PCI probe; there is now a working one
175 * in arch/i386/bios32.c
176 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
177 * v0.22: added printing of status to ring dump
178 * v0.23: changed enet_statistics to net_devive_stats
179 * v0.90: added multicast filter
180 * added module support
181 * changed irq probe to new style
182 * added PCnetFast chip id
183 * added fix for receive stalls with Intel saturn chipsets
184 * added in-place rx skbs like in the tulip driver
185 * minor cleanups
186 * v0.91: added PCnetFast+ chip id
187 * back port to 2.0.x
188 * v1.00: added some stuff from Donald Becker's 2.0.34 version
189 * added support for byte counters in net_dev_stats
190 * v1.01: do ring dumps, only when debugging the driver
191 * increased the transmit timeout
192 * v1.02: fixed memory leak in pcnet32_init_ring()
193 * v1.10: workaround for stopped transmitter
194 * added port selection for modules
195 * detect special T1/E1 WAN card and setup port selection
196 * v1.11: fixed wrong checking of Tx errors
197 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
198 * added save original kmalloc addr for freeing (mcr@solidum.com)
199 * added support for PCnetHome chip (joe@MIT.EDU)
200 * rewritten PCI card detection
201 * added dwio mode to get driver working on some PPC machines
202 * v1.21: added mii selection and mii ioctl
203 * v1.22: changed pci scanning code to make PPC people happy
204 * fixed switching to 32bit mode in pcnet32_open() (thanks
205 * to Michael Richard <mcr@solidum.com> for noticing this one)
206 * added sub vendor/device id matching (thanks again to
207 * Michael Richard <mcr@solidum.com>)
208 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
209 * v1.23 fixed small bug, when manual selecting MII speed/duplex
210 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
211 * underflows. Added tx_start_pt module parameter. Increased
212 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
213 * for FAST[+] chipsets. <kaf@fc.hp.com>
214 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
215 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
216 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
217 * <jamey@crl.dec.com>
218 * - Fixed a few bugs, related to running the controller in 32bit mode.
219 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
220 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
221 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
222 * v1.27 improved CSR/PROM address detection, lots of cleanups,
223 * new pcnet32vlb module option, HP-PARISC support,
224 * added module parameter descriptions,
225 * initial ethtool support - Helge Deller <deller@gmx.de>
226 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
227 * use alloc_etherdev and register_netdev
228 * fix pci probe not increment cards_found
229 * FD auto negotiate error workaround for xSeries250
230 * clean up and using new mii module
231 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
232 * Added timer for cable connection state changes.
233 * v1.28 20 Feb 2004 Don Fry <brazilnut@us.ibm.com>
234 * Jon Mason <jonmason@us.ibm.com>, Chinmay Albal <albal@in.ibm.com>
235 * Now uses ethtool_ops, netif_msg_* and generic_mii_ioctl.
236 * Fixes bogus 'Bus master arbitration failure', pci_[un]map_single
237 * length errors, and transmit hangs. Cleans up after errors in open.
238 * Jim Lewis <jklewis@us.ibm.com> added ethernet loopback test.
239 * Thomas Munck Steenholdt <tmus@tmus.dk> non-mii ioctl corrections.
240 * v1.29 6 Apr 2004 Jim Lewis <jklewis@us.ibm.com> added physical
241 * identification code (blink led's) and register dump.
242 * Don Fry added timer for 971/972 so skbufs don't remain on tx ring
243 * forever.
244 * v1.30 18 May 2004 Don Fry removed timer and Last Transmit Interrupt
245 * (ltint) as they added complexity and didn't give good throughput.
246 * v1.30a 22 May 2004 Don Fry limit frames received during interrupt.
247 * v1.30b 24 May 2004 Don Fry fix bogus tx carrier errors with 79c973,
248 * assisted by Bruce Penrod <bmpenrod@endruntechnologies.com>.
249 * v1.30c 25 May 2004 Don Fry added netif_wake_queue after pcnet32_restart.
250 * v1.30d 01 Jun 2004 Don Fry discard oversize rx packets.
251 * v1.30e 11 Jun 2004 Don Fry recover after fifo error and rx hang.
252 * v1.30f 16 Jun 2004 Don Fry cleanup IRQ to allow 0 and 1 for PCI,
253 * expanding on suggestions from Ralf Baechle <ralf@linux-mips.org>,
254 * and Brian Murphy <brian@murphy.dk>.
255 * v1.30g 22 Jun 2004 Patrick Simmons <psimmons@flash.net> added option
256 * homepna for selecting HomePNA mode for PCNet/Home 79C978.
257 * v1.30h 24 Jun 2004 Don Fry correctly select auto, speed, duplex in bcr32.
258 * v1.30i 28 Jun 2004 Don Fry change to use module_param.
259 * v1.30j 29 Apr 2005 Don Fry fix skb/map leak with loopback test.
260 * v1.31 02 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> added set_ringparam().
261 * v1.31a 12 Sep 2005 Hubert WS Lin <wslin@tw.ibm.c0m> set min ring size to 4
262 * to allow loopback test to work unchanged.
263 * v1.31b 06 Oct 2005 Don Fry changed alloc_ring to show name of device
264 * if allocation fails
265 * v1.31c 01 Nov 2005 Don Fry Allied Telesyn 2700/2701 FX are 100Mbit only.
266 * Force 100Mbit FD if Auto (ASEL) is selected.
267 * See Bugzilla 2669 and 4551.
268 * v1.32 18 Mar2006 Thomas Bogendoerfer and Don Fry added Multi-Phy
269 * handling for supporting AT-270x FTX cards with FX and Tx PHYs.
270 * Philippe Seewer assisted with auto negotiation and testing.
271 */
272
273
274 /*
275 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
276 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
277 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
278 */
279 #ifndef PCNET32_LOG_TX_BUFFERS
280 #define PCNET32_LOG_TX_BUFFERS 4
281 #define PCNET32_LOG_RX_BUFFERS 5
282 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
283 #define PCNET32_LOG_MAX_RX_BUFFERS 9
284 #endif
285
286 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
287 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
288
289 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
290 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
291
292 #define PKT_BUF_SZ 1544
293
294 /* Offsets from base I/O address. */
295 #define PCNET32_WIO_RDP 0x10
296 #define PCNET32_WIO_RAP 0x12
297 #define PCNET32_WIO_RESET 0x14
298 #define PCNET32_WIO_BDP 0x16
299
300 #define PCNET32_DWIO_RDP 0x10
301 #define PCNET32_DWIO_RAP 0x14
302 #define PCNET32_DWIO_RESET 0x18
303 #define PCNET32_DWIO_BDP 0x1C
304
305 #define PCNET32_TOTAL_SIZE 0x20
306
307 /* The PCNET32 Rx and Tx ring descriptors. */
308 struct pcnet32_rx_head {
309 u32 base;
310 s16 buf_length;
311 s16 status;
312 u32 msg_length;
313 u32 reserved;
314 };
315
316 struct pcnet32_tx_head {
317 u32 base;
318 s16 length;
319 s16 status;
320 u32 misc;
321 u32 reserved;
322 };
323
324 /* The PCNET32 32-Bit initialization block, described in databook. */
325 struct pcnet32_init_block {
326 u16 mode;
327 u16 tlen_rlen;
328 u8 phys_addr[6];
329 u16 reserved;
330 u32 filter[2];
331 /* Receive and transmit ring base, along with extra bits. */
332 u32 rx_ring;
333 u32 tx_ring;
334 };
335
336 /* PCnet32 access functions */
337 struct pcnet32_access {
338 u16 (*read_csr)(unsigned long, int);
339 void (*write_csr)(unsigned long, int, u16);
340 u16 (*read_bcr)(unsigned long, int);
341 void (*write_bcr)(unsigned long, int, u16);
342 u16 (*read_rap)(unsigned long);
343 void (*write_rap)(unsigned long, u16);
344 void (*reset)(unsigned long);
345 };
346
347 /*
348 * The first field of pcnet32_private is read by the ethernet device
349 * so the structure should be allocated using pci_alloc_consistent().
350 */
351 struct pcnet32_private {
352 struct pcnet32_init_block init_block;
353 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
354 struct pcnet32_rx_head *rx_ring;
355 struct pcnet32_tx_head *tx_ring;
356 dma_addr_t dma_addr; /* DMA address of beginning of this
357 object, returned by
358 pci_alloc_consistent */
359 struct pci_dev *pci_dev; /* Pointer to the associated pci device
360 structure */
361 const char *name;
362 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
363 struct sk_buff **tx_skbuff;
364 struct sk_buff **rx_skbuff;
365 dma_addr_t *tx_dma_addr;
366 dma_addr_t *rx_dma_addr;
367 struct pcnet32_access a;
368 spinlock_t lock; /* Guard lock */
369 unsigned int cur_rx, cur_tx; /* The next free ring entry */
370 unsigned int rx_ring_size; /* current rx ring size */
371 unsigned int tx_ring_size; /* current tx ring size */
372 unsigned int rx_mod_mask; /* rx ring modular mask */
373 unsigned int tx_mod_mask; /* tx ring modular mask */
374 unsigned short rx_len_bits;
375 unsigned short tx_len_bits;
376 dma_addr_t rx_ring_dma_addr;
377 dma_addr_t tx_ring_dma_addr;
378 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
379 struct net_device_stats stats;
380 char tx_full;
381 char phycount; /* number of phys found */
382 int options;
383 unsigned int shared_irq:1, /* shared irq possible */
384 dxsuflo:1, /* disable transmit stop on uflo */
385 mii:1; /* mii port available */
386 struct net_device *next;
387 struct mii_if_info mii_if;
388 struct timer_list watchdog_timer;
389 struct timer_list blink_timer;
390 u32 msg_enable; /* debug message level */
391
392 /* each bit indicates an available PHY */
393 u32 phymask;
394 };
395
396 static void pcnet32_probe_vlbus(void);
397 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
398 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
399 static int pcnet32_open(struct net_device *);
400 static int pcnet32_init_ring(struct net_device *);
401 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
402 static int pcnet32_rx(struct net_device *);
403 static void pcnet32_tx_timeout (struct net_device *dev);
404 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
405 static int pcnet32_close(struct net_device *);
406 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
407 static void pcnet32_load_multicast(struct net_device *dev);
408 static void pcnet32_set_multicast_list(struct net_device *);
409 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
410 static void pcnet32_watchdog(struct net_device *);
411 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
412 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
413 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
414 static void pcnet32_ethtool_test(struct net_device *dev,
415 struct ethtool_test *eth_test, u64 *data);
416 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1);
417 static int pcnet32_phys_id(struct net_device *dev, u32 data);
418 static void pcnet32_led_blink_callback(struct net_device *dev);
419 static int pcnet32_get_regs_len(struct net_device *dev);
420 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
421 void *ptr);
422 static void pcnet32_purge_tx_ring(struct net_device *dev);
423 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
424 static void pcnet32_free_ring(struct net_device *dev);
425 static void pcnet32_check_media(struct net_device *dev, int verbose);
426
427
428 enum pci_flags_bit {
429 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
430 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
431 };
432
433
434 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
435 {
436 outw (index, addr+PCNET32_WIO_RAP);
437 return inw (addr+PCNET32_WIO_RDP);
438 }
439
440 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
441 {
442 outw (index, addr+PCNET32_WIO_RAP);
443 outw (val, addr+PCNET32_WIO_RDP);
444 }
445
446 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
447 {
448 outw (index, addr+PCNET32_WIO_RAP);
449 return inw (addr+PCNET32_WIO_BDP);
450 }
451
452 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
453 {
454 outw (index, addr+PCNET32_WIO_RAP);
455 outw (val, addr+PCNET32_WIO_BDP);
456 }
457
458 static u16 pcnet32_wio_read_rap (unsigned long addr)
459 {
460 return inw (addr+PCNET32_WIO_RAP);
461 }
462
463 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
464 {
465 outw (val, addr+PCNET32_WIO_RAP);
466 }
467
468 static void pcnet32_wio_reset (unsigned long addr)
469 {
470 inw (addr+PCNET32_WIO_RESET);
471 }
472
473 static int pcnet32_wio_check (unsigned long addr)
474 {
475 outw (88, addr+PCNET32_WIO_RAP);
476 return (inw (addr+PCNET32_WIO_RAP) == 88);
477 }
478
479 static struct pcnet32_access pcnet32_wio = {
480 .read_csr = pcnet32_wio_read_csr,
481 .write_csr = pcnet32_wio_write_csr,
482 .read_bcr = pcnet32_wio_read_bcr,
483 .write_bcr = pcnet32_wio_write_bcr,
484 .read_rap = pcnet32_wio_read_rap,
485 .write_rap = pcnet32_wio_write_rap,
486 .reset = pcnet32_wio_reset
487 };
488
489 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
490 {
491 outl (index, addr+PCNET32_DWIO_RAP);
492 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
493 }
494
495 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
496 {
497 outl (index, addr+PCNET32_DWIO_RAP);
498 outl (val, addr+PCNET32_DWIO_RDP);
499 }
500
501 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
502 {
503 outl (index, addr+PCNET32_DWIO_RAP);
504 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
505 }
506
507 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
508 {
509 outl (index, addr+PCNET32_DWIO_RAP);
510 outl (val, addr+PCNET32_DWIO_BDP);
511 }
512
513 static u16 pcnet32_dwio_read_rap (unsigned long addr)
514 {
515 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
516 }
517
518 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
519 {
520 outl (val, addr+PCNET32_DWIO_RAP);
521 }
522
523 static void pcnet32_dwio_reset (unsigned long addr)
524 {
525 inl (addr+PCNET32_DWIO_RESET);
526 }
527
528 static int pcnet32_dwio_check (unsigned long addr)
529 {
530 outl (88, addr+PCNET32_DWIO_RAP);
531 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
532 }
533
534 static struct pcnet32_access pcnet32_dwio = {
535 .read_csr = pcnet32_dwio_read_csr,
536 .write_csr = pcnet32_dwio_write_csr,
537 .read_bcr = pcnet32_dwio_read_bcr,
538 .write_bcr = pcnet32_dwio_write_bcr,
539 .read_rap = pcnet32_dwio_read_rap,
540 .write_rap = pcnet32_dwio_write_rap,
541 .reset = pcnet32_dwio_reset
542 };
543
544 #ifdef CONFIG_NET_POLL_CONTROLLER
545 static void pcnet32_poll_controller(struct net_device *dev)
546 {
547 disable_irq(dev->irq);
548 pcnet32_interrupt(0, dev, NULL);
549 enable_irq(dev->irq);
550 }
551 #endif
552
553
554 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
555 {
556 struct pcnet32_private *lp = dev->priv;
557 unsigned long flags;
558 int r = -EOPNOTSUPP;
559
560 if (lp->mii) {
561 spin_lock_irqsave(&lp->lock, flags);
562 mii_ethtool_gset(&lp->mii_if, cmd);
563 spin_unlock_irqrestore(&lp->lock, flags);
564 r = 0;
565 }
566 return r;
567 }
568
569 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
570 {
571 struct pcnet32_private *lp = dev->priv;
572 unsigned long flags;
573 int r = -EOPNOTSUPP;
574
575 if (lp->mii) {
576 spin_lock_irqsave(&lp->lock, flags);
577 r = mii_ethtool_sset(&lp->mii_if, cmd);
578 spin_unlock_irqrestore(&lp->lock, flags);
579 }
580 return r;
581 }
582
583 static void pcnet32_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
584 {
585 struct pcnet32_private *lp = dev->priv;
586
587 strcpy (info->driver, DRV_NAME);
588 strcpy (info->version, DRV_VERSION);
589 if (lp->pci_dev)
590 strcpy (info->bus_info, pci_name(lp->pci_dev));
591 else
592 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
593 }
594
595 static u32 pcnet32_get_link(struct net_device *dev)
596 {
597 struct pcnet32_private *lp = dev->priv;
598 unsigned long flags;
599 int r;
600
601 spin_lock_irqsave(&lp->lock, flags);
602 if (lp->mii) {
603 r = mii_link_ok(&lp->mii_if);
604 } else {
605 ulong ioaddr = dev->base_addr; /* card base I/O address */
606 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
607 }
608 spin_unlock_irqrestore(&lp->lock, flags);
609
610 return r;
611 }
612
613 static u32 pcnet32_get_msglevel(struct net_device *dev)
614 {
615 struct pcnet32_private *lp = dev->priv;
616 return lp->msg_enable;
617 }
618
619 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
620 {
621 struct pcnet32_private *lp = dev->priv;
622 lp->msg_enable = value;
623 }
624
625 static int pcnet32_nway_reset(struct net_device *dev)
626 {
627 struct pcnet32_private *lp = dev->priv;
628 unsigned long flags;
629 int r = -EOPNOTSUPP;
630
631 if (lp->mii) {
632 spin_lock_irqsave(&lp->lock, flags);
633 r = mii_nway_restart(&lp->mii_if);
634 spin_unlock_irqrestore(&lp->lock, flags);
635 }
636 return r;
637 }
638
639 static void pcnet32_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
640 {
641 struct pcnet32_private *lp = dev->priv;
642
643 ering->tx_max_pending = TX_MAX_RING_SIZE - 1;
644 ering->tx_pending = lp->tx_ring_size - 1;
645 ering->rx_max_pending = RX_MAX_RING_SIZE - 1;
646 ering->rx_pending = lp->rx_ring_size - 1;
647 }
648
649 static int pcnet32_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
650 {
651 struct pcnet32_private *lp = dev->priv;
652 unsigned long flags;
653 int i;
654
655 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
656 return -EINVAL;
657
658 if (netif_running(dev))
659 pcnet32_close(dev);
660
661 spin_lock_irqsave(&lp->lock, flags);
662 pcnet32_free_ring(dev);
663 lp->tx_ring_size = min(ering->tx_pending, (unsigned int) TX_MAX_RING_SIZE);
664 lp->rx_ring_size = min(ering->rx_pending, (unsigned int) RX_MAX_RING_SIZE);
665
666 /* set the minimum ring size to 4, to allow the loopback test to work
667 * unchanged.
668 */
669 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
670 if (lp->tx_ring_size <= (1 << i))
671 break;
672 }
673 lp->tx_ring_size = (1 << i);
674 lp->tx_mod_mask = lp->tx_ring_size - 1;
675 lp->tx_len_bits = (i << 12);
676
677 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
678 if (lp->rx_ring_size <= (1 << i))
679 break;
680 }
681 lp->rx_ring_size = (1 << i);
682 lp->rx_mod_mask = lp->rx_ring_size - 1;
683 lp->rx_len_bits = (i << 4);
684
685 if (pcnet32_alloc_ring(dev, dev->name)) {
686 pcnet32_free_ring(dev);
687 spin_unlock_irqrestore(&lp->lock, flags);
688 return -ENOMEM;
689 }
690
691 spin_unlock_irqrestore(&lp->lock, flags);
692
693 if (pcnet32_debug & NETIF_MSG_DRV)
694 printk(KERN_INFO PFX "%s: Ring Param Settings: RX: %d, TX: %d\n",
695 dev->name, lp->rx_ring_size, lp->tx_ring_size);
696
697 if (netif_running(dev))
698 pcnet32_open(dev);
699
700 return 0;
701 }
702
703 static void pcnet32_get_strings(struct net_device *dev, u32 stringset, u8 *data)
704 {
705 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
706 }
707
708 static int pcnet32_self_test_count(struct net_device *dev)
709 {
710 return PCNET32_TEST_LEN;
711 }
712
713 static void pcnet32_ethtool_test(struct net_device *dev,
714 struct ethtool_test *test, u64 *data)
715 {
716 struct pcnet32_private *lp = dev->priv;
717 int rc;
718
719 if (test->flags == ETH_TEST_FL_OFFLINE) {
720 rc = pcnet32_loopback_test(dev, data);
721 if (rc) {
722 if (netif_msg_hw(lp))
723 printk(KERN_DEBUG "%s: Loopback test failed.\n", dev->name);
724 test->flags |= ETH_TEST_FL_FAILED;
725 } else if (netif_msg_hw(lp))
726 printk(KERN_DEBUG "%s: Loopback test passed.\n", dev->name);
727 } else if (netif_msg_hw(lp))
728 printk(KERN_DEBUG "%s: No tests to run (specify 'Offline' on ethtool).", dev->name);
729 } /* end pcnet32_ethtool_test */
730
731 static int pcnet32_loopback_test(struct net_device *dev, uint64_t *data1)
732 {
733 struct pcnet32_private *lp = dev->priv;
734 struct pcnet32_access *a = &lp->a; /* access to registers */
735 ulong ioaddr = dev->base_addr; /* card base I/O address */
736 struct sk_buff *skb; /* sk buff */
737 int x, i; /* counters */
738 int numbuffs = 4; /* number of TX/RX buffers and descs */
739 u16 status = 0x8300; /* TX ring status */
740 u16 teststatus; /* test of ring status */
741 int rc; /* return code */
742 int size; /* size of packets */
743 unsigned char *packet; /* source packet data */
744 static const int data_len = 60; /* length of source packets */
745 unsigned long flags;
746 unsigned long ticks;
747
748 *data1 = 1; /* status of test, default to fail */
749 rc = 1; /* default to fail */
750
751 if (netif_running(dev))
752 pcnet32_close(dev);
753
754 spin_lock_irqsave(&lp->lock, flags);
755
756 /* Reset the PCNET32 */
757 lp->a.reset (ioaddr);
758
759 /* switch pcnet32 to 32bit mode */
760 lp->a.write_bcr (ioaddr, 20, 2);
761
762 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
763 lp->init_block.filter[0] = 0;
764 lp->init_block.filter[1] = 0;
765
766 /* purge & init rings but don't actually restart */
767 pcnet32_restart(dev, 0x0000);
768
769 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
770
771 /* Initialize Transmit buffers. */
772 size = data_len + 15;
773 for (x=0; x<numbuffs; x++) {
774 if (!(skb = dev_alloc_skb(size))) {
775 if (netif_msg_hw(lp))
776 printk(KERN_DEBUG "%s: Cannot allocate skb at line: %d!\n",
777 dev->name, __LINE__);
778 goto clean_up;
779 } else {
780 packet = skb->data;
781 skb_put(skb, size); /* create space for data */
782 lp->tx_skbuff[x] = skb;
783 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
784 lp->tx_ring[x].misc = 0;
785
786 /* put DA and SA into the skb */
787 for (i=0; i<6; i++)
788 *packet++ = dev->dev_addr[i];
789 for (i=0; i<6; i++)
790 *packet++ = dev->dev_addr[i];
791 /* type */
792 *packet++ = 0x08;
793 *packet++ = 0x06;
794 /* packet number */
795 *packet++ = x;
796 /* fill packet with data */
797 for (i=0; i<data_len; i++)
798 *packet++ = i;
799
800 lp->tx_dma_addr[x] = pci_map_single(lp->pci_dev, skb->data,
801 skb->len, PCI_DMA_TODEVICE);
802 lp->tx_ring[x].base = (u32)le32_to_cpu(lp->tx_dma_addr[x]);
803 wmb(); /* Make sure owner changes after all others are visible */
804 lp->tx_ring[x].status = le16_to_cpu(status);
805 }
806 }
807
808 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BSR32 */
809 x = x | 0x0002;
810 a->write_bcr(ioaddr, 32, x);
811
812 lp->a.write_csr (ioaddr, 15, 0x0044); /* set int loopback in CSR15 */
813
814 teststatus = le16_to_cpu(0x8000);
815 lp->a.write_csr(ioaddr, 0, 0x0002); /* Set STRT bit */
816
817 /* Check status of descriptors */
818 for (x=0; x<numbuffs; x++) {
819 ticks = 0;
820 rmb();
821 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
822 spin_unlock_irqrestore(&lp->lock, flags);
823 mdelay(1);
824 spin_lock_irqsave(&lp->lock, flags);
825 rmb();
826 ticks++;
827 }
828 if (ticks == 200) {
829 if (netif_msg_hw(lp))
830 printk("%s: Desc %d failed to reset!\n",dev->name,x);
831 break;
832 }
833 }
834
835 lp->a.write_csr(ioaddr, 0, 0x0004); /* Set STOP bit */
836 wmb();
837 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
838 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
839
840 for (x=0; x<numbuffs; x++) {
841 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
842 skb = lp->rx_skbuff[x];
843 for (i=0; i<size; i++) {
844 printk("%02x ", *(skb->data+i));
845 }
846 printk("\n");
847 }
848 }
849
850 x = 0;
851 rc = 0;
852 while (x<numbuffs && !rc) {
853 skb = lp->rx_skbuff[x];
854 packet = lp->tx_skbuff[x]->data;
855 for (i=0; i<size; i++) {
856 if (*(skb->data+i) != packet[i]) {
857 if (netif_msg_hw(lp))
858 printk(KERN_DEBUG "%s: Error in compare! %2x - %02x %02x\n",
859 dev->name, i, *(skb->data+i), packet[i]);
860 rc = 1;
861 break;
862 }
863 }
864 x++;
865 }
866 if (!rc) {
867 *data1 = 0;
868 }
869
870 clean_up:
871 pcnet32_purge_tx_ring(dev);
872 x = a->read_csr(ioaddr, 15) & 0xFFFF;
873 a->write_csr(ioaddr, 15, (x & ~0x0044)); /* reset bits 6 and 2 */
874
875 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
876 x = x & ~0x0002;
877 a->write_bcr(ioaddr, 32, x);
878
879 spin_unlock_irqrestore(&lp->lock, flags);
880
881 if (netif_running(dev)) {
882 pcnet32_open(dev);
883 } else {
884 lp->a.write_bcr (ioaddr, 20, 4); /* return to 16bit mode */
885 }
886
887 return(rc);
888 } /* end pcnet32_loopback_test */
889
890 static void pcnet32_led_blink_callback(struct net_device *dev)
891 {
892 struct pcnet32_private *lp = dev->priv;
893 struct pcnet32_access *a = &lp->a;
894 ulong ioaddr = dev->base_addr;
895 unsigned long flags;
896 int i;
897
898 spin_lock_irqsave(&lp->lock, flags);
899 for (i=4; i<8; i++) {
900 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
901 }
902 spin_unlock_irqrestore(&lp->lock, flags);
903
904 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
905 }
906
907 static int pcnet32_phys_id(struct net_device *dev, u32 data)
908 {
909 struct pcnet32_private *lp = dev->priv;
910 struct pcnet32_access *a = &lp->a;
911 ulong ioaddr = dev->base_addr;
912 unsigned long flags;
913 int i, regs[4];
914
915 if (!lp->blink_timer.function) {
916 init_timer(&lp->blink_timer);
917 lp->blink_timer.function = (void *) pcnet32_led_blink_callback;
918 lp->blink_timer.data = (unsigned long) dev;
919 }
920
921 /* Save the current value of the bcrs */
922 spin_lock_irqsave(&lp->lock, flags);
923 for (i=4; i<8; i++) {
924 regs[i-4] = a->read_bcr(ioaddr, i);
925 }
926 spin_unlock_irqrestore(&lp->lock, flags);
927
928 mod_timer(&lp->blink_timer, jiffies);
929 set_current_state(TASK_INTERRUPTIBLE);
930
931 if ((!data) || (data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
932 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
933
934 msleep_interruptible(data * 1000);
935 del_timer_sync(&lp->blink_timer);
936
937 /* Restore the original value of the bcrs */
938 spin_lock_irqsave(&lp->lock, flags);
939 for (i=4; i<8; i++) {
940 a->write_bcr(ioaddr, i, regs[i-4]);
941 }
942 spin_unlock_irqrestore(&lp->lock, flags);
943
944 return 0;
945 }
946
947 #define PCNET32_REGS_PER_PHY 32
948 #define PCNET32_MAX_PHYS 32
949 static int pcnet32_get_regs_len(struct net_device *dev)
950 {
951 struct pcnet32_private *lp = dev->priv;
952 int j = lp->phycount * PCNET32_REGS_PER_PHY;
953
954 return((PCNET32_NUM_REGS + j) * sizeof(u16));
955 }
956
957 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
958 void *ptr)
959 {
960 int i, csr0;
961 u16 *buff = ptr;
962 struct pcnet32_private *lp = dev->priv;
963 struct pcnet32_access *a = &lp->a;
964 ulong ioaddr = dev->base_addr;
965 int ticks;
966 unsigned long flags;
967
968 spin_lock_irqsave(&lp->lock, flags);
969
970 csr0 = a->read_csr(ioaddr, 0);
971 if (!(csr0 & 0x0004)) { /* If not stopped */
972 /* set SUSPEND (SPND) - CSR5 bit 0 */
973 a->write_csr(ioaddr, 5, 0x0001);
974
975 /* poll waiting for bit to be set */
976 ticks = 0;
977 while (!(a->read_csr(ioaddr, 5) & 0x0001)) {
978 spin_unlock_irqrestore(&lp->lock, flags);
979 mdelay(1);
980 spin_lock_irqsave(&lp->lock, flags);
981 ticks++;
982 if (ticks > 200) {
983 if (netif_msg_hw(lp))
984 printk(KERN_DEBUG "%s: Error getting into suspend!\n",
985 dev->name);
986 break;
987 }
988 }
989 }
990
991 /* read address PROM */
992 for (i=0; i<16; i += 2)
993 *buff++ = inw(ioaddr + i);
994
995 /* read control and status registers */
996 for (i=0; i<90; i++) {
997 *buff++ = a->read_csr(ioaddr, i);
998 }
999
1000 *buff++ = a->read_csr(ioaddr, 112);
1001 *buff++ = a->read_csr(ioaddr, 114);
1002
1003 /* read bus configuration registers */
1004 for (i=0; i<30; i++) {
1005 *buff++ = a->read_bcr(ioaddr, i);
1006 }
1007 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1008 for (i=31; i<36; i++) {
1009 *buff++ = a->read_bcr(ioaddr, i);
1010 }
1011
1012 /* read mii phy registers */
1013 if (lp->mii) {
1014 int j;
1015 for (j=0; j<PCNET32_MAX_PHYS; j++) {
1016 if (lp->phymask & (1 << j)) {
1017 for (i=0; i<PCNET32_REGS_PER_PHY; i++) {
1018 lp->a.write_bcr(ioaddr, 33, (j << 5) | i);
1019 *buff++ = lp->a.read_bcr(ioaddr, 34);
1020 }
1021 }
1022 }
1023 }
1024
1025 if (!(csr0 & 0x0004)) { /* If not stopped */
1026 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1027 a->write_csr(ioaddr, 5, 0x0000);
1028 }
1029
1030 spin_unlock_irqrestore(&lp->lock, flags);
1031 }
1032
1033 static struct ethtool_ops pcnet32_ethtool_ops = {
1034 .get_settings = pcnet32_get_settings,
1035 .set_settings = pcnet32_set_settings,
1036 .get_drvinfo = pcnet32_get_drvinfo,
1037 .get_msglevel = pcnet32_get_msglevel,
1038 .set_msglevel = pcnet32_set_msglevel,
1039 .nway_reset = pcnet32_nway_reset,
1040 .get_link = pcnet32_get_link,
1041 .get_ringparam = pcnet32_get_ringparam,
1042 .set_ringparam = pcnet32_set_ringparam,
1043 .get_tx_csum = ethtool_op_get_tx_csum,
1044 .get_sg = ethtool_op_get_sg,
1045 .get_tso = ethtool_op_get_tso,
1046 .get_strings = pcnet32_get_strings,
1047 .self_test_count = pcnet32_self_test_count,
1048 .self_test = pcnet32_ethtool_test,
1049 .phys_id = pcnet32_phys_id,
1050 .get_regs_len = pcnet32_get_regs_len,
1051 .get_regs = pcnet32_get_regs,
1052 .get_perm_addr = ethtool_op_get_perm_addr,
1053 };
1054
1055 /* only probes for non-PCI devices, the rest are handled by
1056 * pci_register_driver via pcnet32_probe_pci */
1057
1058 static void __devinit
1059 pcnet32_probe_vlbus(void)
1060 {
1061 unsigned int *port, ioaddr;
1062
1063 /* search for PCnet32 VLB cards at known addresses */
1064 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1065 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1066 /* check if there is really a pcnet chip on that ioaddr */
1067 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57)) {
1068 pcnet32_probe1(ioaddr, 0, NULL);
1069 } else {
1070 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1071 }
1072 }
1073 }
1074 }
1075
1076
1077 static int __devinit
1078 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1079 {
1080 unsigned long ioaddr;
1081 int err;
1082
1083 err = pci_enable_device(pdev);
1084 if (err < 0) {
1085 if (pcnet32_debug & NETIF_MSG_PROBE)
1086 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
1087 return err;
1088 }
1089 pci_set_master(pdev);
1090
1091 ioaddr = pci_resource_start (pdev, 0);
1092 if (!ioaddr) {
1093 if (pcnet32_debug & NETIF_MSG_PROBE)
1094 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
1095 return -ENODEV;
1096 }
1097
1098 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1099 if (pcnet32_debug & NETIF_MSG_PROBE)
1100 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
1101 return -ENODEV;
1102 }
1103 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") == NULL) {
1104 if (pcnet32_debug & NETIF_MSG_PROBE)
1105 printk(KERN_ERR PFX "io address range already allocated\n");
1106 return -EBUSY;
1107 }
1108
1109 err = pcnet32_probe1(ioaddr, 1, pdev);
1110 if (err < 0) {
1111 pci_disable_device(pdev);
1112 }
1113 return err;
1114 }
1115
1116
1117 /* pcnet32_probe1
1118 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1119 * pdev will be NULL when called from pcnet32_probe_vlbus.
1120 */
1121 static int __devinit
1122 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1123 {
1124 struct pcnet32_private *lp;
1125 dma_addr_t lp_dma_addr;
1126 int i, media;
1127 int fdx, mii, fset, dxsuflo;
1128 int chip_version;
1129 char *chipname;
1130 struct net_device *dev;
1131 struct pcnet32_access *a = NULL;
1132 u8 promaddr[6];
1133 int ret = -ENODEV;
1134
1135 /* reset the chip */
1136 pcnet32_wio_reset(ioaddr);
1137
1138 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1139 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1140 a = &pcnet32_wio;
1141 } else {
1142 pcnet32_dwio_reset(ioaddr);
1143 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
1144 a = &pcnet32_dwio;
1145 } else
1146 goto err_release_region;
1147 }
1148
1149 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
1150 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1151 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
1152 if ((chip_version & 0xfff) != 0x003) {
1153 if (pcnet32_debug & NETIF_MSG_PROBE)
1154 printk(KERN_INFO PFX "Unsupported chip version.\n");
1155 goto err_release_region;
1156 }
1157
1158 /* initialize variables */
1159 fdx = mii = fset = dxsuflo = 0;
1160 chip_version = (chip_version >> 12) & 0xffff;
1161
1162 switch (chip_version) {
1163 case 0x2420:
1164 chipname = "PCnet/PCI 79C970"; /* PCI */
1165 break;
1166 case 0x2430:
1167 if (shared)
1168 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1169 else
1170 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1171 break;
1172 case 0x2621:
1173 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1174 fdx = 1;
1175 break;
1176 case 0x2623:
1177 chipname = "PCnet/FAST 79C971"; /* PCI */
1178 fdx = 1; mii = 1; fset = 1;
1179 break;
1180 case 0x2624:
1181 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1182 fdx = 1; mii = 1; fset = 1;
1183 break;
1184 case 0x2625:
1185 chipname = "PCnet/FAST III 79C973"; /* PCI */
1186 fdx = 1; mii = 1;
1187 break;
1188 case 0x2626:
1189 chipname = "PCnet/Home 79C978"; /* PCI */
1190 fdx = 1;
1191 /*
1192 * This is based on specs published at www.amd.com. This section
1193 * assumes that a card with a 79C978 wants to go into standard
1194 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1195 * and the module option homepna=1 can select this instead.
1196 */
1197 media = a->read_bcr(ioaddr, 49);
1198 media &= ~3; /* default to 10Mb ethernet */
1199 if (cards_found < MAX_UNITS && homepna[cards_found])
1200 media |= 1; /* switch to home wiring mode */
1201 if (pcnet32_debug & NETIF_MSG_PROBE)
1202 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1203 (media & 1) ? "1" : "10");
1204 a->write_bcr(ioaddr, 49, media);
1205 break;
1206 case 0x2627:
1207 chipname = "PCnet/FAST III 79C975"; /* PCI */
1208 fdx = 1; mii = 1;
1209 break;
1210 case 0x2628:
1211 chipname = "PCnet/PRO 79C976";
1212 fdx = 1; mii = 1;
1213 break;
1214 default:
1215 if (pcnet32_debug & NETIF_MSG_PROBE)
1216 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
1217 chip_version);
1218 goto err_release_region;
1219 }
1220
1221 /*
1222 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1223 * starting until the packet is loaded. Strike one for reliability, lose
1224 * one for latency - although on PCI this isnt a big loss. Older chips
1225 * have FIFO's smaller than a packet, so you can't do this.
1226 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1227 */
1228
1229 if (fset) {
1230 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1231 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1232 dxsuflo = 1;
1233 }
1234
1235 dev = alloc_etherdev(0);
1236 if (!dev) {
1237 if (pcnet32_debug & NETIF_MSG_PROBE)
1238 printk(KERN_ERR PFX "Memory allocation failed.\n");
1239 ret = -ENOMEM;
1240 goto err_release_region;
1241 }
1242 SET_NETDEV_DEV(dev, &pdev->dev);
1243
1244 if (pcnet32_debug & NETIF_MSG_PROBE)
1245 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1246
1247 /* In most chips, after a chip reset, the ethernet address is read from the
1248 * station address PROM at the base address and programmed into the
1249 * "Physical Address Registers" CSR12-14.
1250 * As a precautionary measure, we read the PROM values and complain if
1251 * they disagree with the CSRs. Either way, we use the CSR values, and
1252 * double check that they are valid.
1253 */
1254 for (i = 0; i < 3; i++) {
1255 unsigned int val;
1256 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
1257 /* There may be endianness issues here. */
1258 dev->dev_addr[2*i] = val & 0x0ff;
1259 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
1260 }
1261
1262 /* read PROM address and compare with CSR address */
1263 for (i = 0; i < 6; i++)
1264 promaddr[i] = inb(ioaddr + i);
1265
1266 if (memcmp(promaddr, dev->dev_addr, 6)
1267 || !is_valid_ether_addr(dev->dev_addr)) {
1268 if (is_valid_ether_addr(promaddr)) {
1269 if (pcnet32_debug & NETIF_MSG_PROBE) {
1270 printk(" warning: CSR address invalid,\n");
1271 printk(KERN_INFO " using instead PROM address of");
1272 }
1273 memcpy(dev->dev_addr, promaddr, 6);
1274 }
1275 }
1276 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1277
1278 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1279 if (!is_valid_ether_addr(dev->perm_addr))
1280 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1281
1282 if (pcnet32_debug & NETIF_MSG_PROBE) {
1283 for (i = 0; i < 6; i++)
1284 printk(" %2.2x", dev->dev_addr[i]);
1285
1286 /* Version 0x2623 and 0x2624 */
1287 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1288 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1289 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
1290 switch(i>>10) {
1291 case 0: printk(" 20 bytes,"); break;
1292 case 1: printk(" 64 bytes,"); break;
1293 case 2: printk(" 128 bytes,"); break;
1294 case 3: printk("~220 bytes,"); break;
1295 }
1296 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1297 printk(" BCR18(%x):",i&0xffff);
1298 if (i & (1<<5)) printk("BurstWrEn ");
1299 if (i & (1<<6)) printk("BurstRdEn ");
1300 if (i & (1<<7)) printk("DWordIO ");
1301 if (i & (1<<11)) printk("NoUFlow ");
1302 i = a->read_bcr(ioaddr, 25);
1303 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
1304 i = a->read_bcr(ioaddr, 26);
1305 printk(" SRAM_BND=0x%04x,",i<<8);
1306 i = a->read_bcr(ioaddr, 27);
1307 if (i & (1<<14)) printk("LowLatRx");
1308 }
1309 }
1310
1311 dev->base_addr = ioaddr;
1312 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1313 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1314 if (pcnet32_debug & NETIF_MSG_PROBE)
1315 printk(KERN_ERR PFX "Consistent memory allocation failed.\n");
1316 ret = -ENOMEM;
1317 goto err_free_netdev;
1318 }
1319
1320 memset(lp, 0, sizeof(*lp));
1321 lp->dma_addr = lp_dma_addr;
1322 lp->pci_dev = pdev;
1323
1324 spin_lock_init(&lp->lock);
1325
1326 SET_MODULE_OWNER(dev);
1327 SET_NETDEV_DEV(dev, &pdev->dev);
1328 dev->priv = lp;
1329 lp->name = chipname;
1330 lp->shared_irq = shared;
1331 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1332 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1333 lp->tx_mod_mask = lp->tx_ring_size - 1;
1334 lp->rx_mod_mask = lp->rx_ring_size - 1;
1335 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1336 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1337 lp->mii_if.full_duplex = fdx;
1338 lp->mii_if.phy_id_mask = 0x1f;
1339 lp->mii_if.reg_num_mask = 0x1f;
1340 lp->dxsuflo = dxsuflo;
1341 lp->mii = mii;
1342 lp->msg_enable = pcnet32_debug;
1343 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
1344 lp->options = PCNET32_PORT_ASEL;
1345 else
1346 lp->options = options_mapping[options[cards_found]];
1347 lp->mii_if.dev = dev;
1348 lp->mii_if.mdio_read = mdio_read;
1349 lp->mii_if.mdio_write = mdio_write;
1350
1351 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1352 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
1353 lp->options |= PCNET32_PORT_FD;
1354
1355 if (!a) {
1356 if (pcnet32_debug & NETIF_MSG_PROBE)
1357 printk(KERN_ERR PFX "No access methods\n");
1358 ret = -ENODEV;
1359 goto err_free_consistent;
1360 }
1361 lp->a = *a;
1362
1363 /* prior to register_netdev, dev->name is not yet correct */
1364 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1365 ret = -ENOMEM;
1366 goto err_free_ring;
1367 }
1368 /* detect special T1/E1 WAN card by checking for MAC address */
1369 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1370 && dev->dev_addr[2] == 0x75)
1371 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1372
1373 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1374 lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1375 for (i = 0; i < 6; i++)
1376 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1377 lp->init_block.filter[0] = 0x00000000;
1378 lp->init_block.filter[1] = 0x00000000;
1379 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr);
1380 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr);
1381
1382 /* switch pcnet32 to 32bit mode */
1383 a->write_bcr(ioaddr, 20, 2);
1384
1385 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1386 init_block)) & 0xffff);
1387 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1388 init_block)) >> 16);
1389
1390 if (pdev) { /* use the IRQ provided by PCI */
1391 dev->irq = pdev->irq;
1392 if (pcnet32_debug & NETIF_MSG_PROBE)
1393 printk(" assigned IRQ %d.\n", dev->irq);
1394 } else {
1395 unsigned long irq_mask = probe_irq_on();
1396
1397 /*
1398 * To auto-IRQ we enable the initialization-done and DMA error
1399 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1400 * boards will work.
1401 */
1402 /* Trigger an initialization just for the interrupt. */
1403 a->write_csr (ioaddr, 0, 0x41);
1404 mdelay (1);
1405
1406 dev->irq = probe_irq_off (irq_mask);
1407 if (!dev->irq) {
1408 if (pcnet32_debug & NETIF_MSG_PROBE)
1409 printk(", failed to detect IRQ line.\n");
1410 ret = -ENODEV;
1411 goto err_free_ring;
1412 }
1413 if (pcnet32_debug & NETIF_MSG_PROBE)
1414 printk(", probed IRQ %d.\n", dev->irq);
1415 }
1416
1417 /* Set the mii phy_id so that we can query the link state */
1418 if (lp->mii) {
1419 /* lp->phycount and lp->phymask are set to 0 by memset above */
1420
1421 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
1422 /* scan for PHYs */
1423 for (i=0; i<PCNET32_MAX_PHYS; i++) {
1424 unsigned short id1, id2;
1425
1426 id1 = mdio_read(dev, i, MII_PHYSID1);
1427 if (id1 == 0xffff)
1428 continue;
1429 id2 = mdio_read(dev, i, MII_PHYSID2);
1430 if (id2 == 0xffff)
1431 continue;
1432 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1433 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1434 lp->phycount++;
1435 lp->phymask |= (1 << i);
1436 lp->mii_if.phy_id = i;
1437 if (pcnet32_debug & NETIF_MSG_PROBE)
1438 printk(KERN_INFO PFX "Found PHY %04x:%04x at address %d.\n",
1439 id1, id2, i);
1440 }
1441 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1442 if (lp->phycount > 1) {
1443 lp->options |= PCNET32_PORT_MII;
1444 }
1445 }
1446
1447 init_timer (&lp->watchdog_timer);
1448 lp->watchdog_timer.data = (unsigned long) dev;
1449 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
1450
1451 /* The PCNET32-specific entries in the device structure. */
1452 dev->open = &pcnet32_open;
1453 dev->hard_start_xmit = &pcnet32_start_xmit;
1454 dev->stop = &pcnet32_close;
1455 dev->get_stats = &pcnet32_get_stats;
1456 dev->set_multicast_list = &pcnet32_set_multicast_list;
1457 dev->do_ioctl = &pcnet32_ioctl;
1458 dev->ethtool_ops = &pcnet32_ethtool_ops;
1459 dev->tx_timeout = pcnet32_tx_timeout;
1460 dev->watchdog_timeo = (5*HZ);
1461
1462 #ifdef CONFIG_NET_POLL_CONTROLLER
1463 dev->poll_controller = pcnet32_poll_controller;
1464 #endif
1465
1466 /* Fill in the generic fields of the device structure. */
1467 if (register_netdev(dev))
1468 goto err_free_ring;
1469
1470 if (pdev) {
1471 pci_set_drvdata(pdev, dev);
1472 } else {
1473 lp->next = pcnet32_dev;
1474 pcnet32_dev = dev;
1475 }
1476
1477 if (pcnet32_debug & NETIF_MSG_PROBE)
1478 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1479 cards_found++;
1480
1481 /* enable LED writes */
1482 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1483
1484 return 0;
1485
1486 err_free_ring:
1487 pcnet32_free_ring(dev);
1488 err_free_consistent:
1489 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1490 err_free_netdev:
1491 free_netdev(dev);
1492 err_release_region:
1493 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1494 return ret;
1495 }
1496
1497
1498 /* if any allocation fails, caller must also call pcnet32_free_ring */
1499 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1500 {
1501 struct pcnet32_private *lp = dev->priv;
1502
1503 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1504 sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
1505 &lp->tx_ring_dma_addr);
1506 if (lp->tx_ring == NULL) {
1507 if (pcnet32_debug & NETIF_MSG_DRV)
1508 printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n",
1509 name);
1510 return -ENOMEM;
1511 }
1512
1513 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1514 sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
1515 &lp->rx_ring_dma_addr);
1516 if (lp->rx_ring == NULL) {
1517 if (pcnet32_debug & NETIF_MSG_DRV)
1518 printk("\n" KERN_ERR PFX "%s: Consistent memory allocation failed.\n",
1519 name);
1520 return -ENOMEM;
1521 }
1522
1523 lp->tx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->tx_ring_size,
1524 GFP_ATOMIC);
1525 if (!lp->tx_dma_addr) {
1526 if (pcnet32_debug & NETIF_MSG_DRV)
1527 printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
1528 return -ENOMEM;
1529 }
1530 memset(lp->tx_dma_addr, 0, sizeof(dma_addr_t) * lp->tx_ring_size);
1531
1532 lp->rx_dma_addr = kmalloc(sizeof(dma_addr_t) * lp->rx_ring_size,
1533 GFP_ATOMIC);
1534 if (!lp->rx_dma_addr) {
1535 if (pcnet32_debug & NETIF_MSG_DRV)
1536 printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
1537 return -ENOMEM;
1538 }
1539 memset(lp->rx_dma_addr, 0, sizeof(dma_addr_t) * lp->rx_ring_size);
1540
1541 lp->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->tx_ring_size,
1542 GFP_ATOMIC);
1543 if (!lp->tx_skbuff) {
1544 if (pcnet32_debug & NETIF_MSG_DRV)
1545 printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
1546 return -ENOMEM;
1547 }
1548 memset(lp->tx_skbuff, 0, sizeof(struct sk_buff *) * lp->tx_ring_size);
1549
1550 lp->rx_skbuff = kmalloc(sizeof(struct sk_buff *) * lp->rx_ring_size,
1551 GFP_ATOMIC);
1552 if (!lp->rx_skbuff) {
1553 if (pcnet32_debug & NETIF_MSG_DRV)
1554 printk("\n" KERN_ERR PFX "%s: Memory allocation failed.\n", name);
1555 return -ENOMEM;
1556 }
1557 memset(lp->rx_skbuff, 0, sizeof(struct sk_buff *) * lp->rx_ring_size);
1558
1559 return 0;
1560 }
1561
1562
1563 static void pcnet32_free_ring(struct net_device *dev)
1564 {
1565 struct pcnet32_private *lp = dev->priv;
1566
1567 kfree(lp->tx_skbuff);
1568 lp->tx_skbuff = NULL;
1569
1570 kfree(lp->rx_skbuff);
1571 lp->rx_skbuff = NULL;
1572
1573 kfree(lp->tx_dma_addr);
1574 lp->tx_dma_addr = NULL;
1575
1576 kfree(lp->rx_dma_addr);
1577 lp->rx_dma_addr = NULL;
1578
1579 if (lp->tx_ring) {
1580 pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_tx_head) * lp->tx_ring_size,
1581 lp->tx_ring, lp->tx_ring_dma_addr);
1582 lp->tx_ring = NULL;
1583 }
1584
1585 if (lp->rx_ring) {
1586 pci_free_consistent(lp->pci_dev, sizeof(struct pcnet32_rx_head) * lp->rx_ring_size,
1587 lp->rx_ring, lp->rx_ring_dma_addr);
1588 lp->rx_ring = NULL;
1589 }
1590 }
1591
1592
1593 static int
1594 pcnet32_open(struct net_device *dev)
1595 {
1596 struct pcnet32_private *lp = dev->priv;
1597 unsigned long ioaddr = dev->base_addr;
1598 u16 val;
1599 int i;
1600 int rc;
1601 unsigned long flags;
1602
1603 if (request_irq(dev->irq, &pcnet32_interrupt,
1604 lp->shared_irq ? SA_SHIRQ : 0, dev->name, (void *)dev)) {
1605 return -EAGAIN;
1606 }
1607
1608 spin_lock_irqsave(&lp->lock, flags);
1609 /* Check for a valid station address */
1610 if (!is_valid_ether_addr(dev->dev_addr)) {
1611 rc = -EINVAL;
1612 goto err_free_irq;
1613 }
1614
1615 /* Reset the PCNET32 */
1616 lp->a.reset (ioaddr);
1617
1618 /* switch pcnet32 to 32bit mode */
1619 lp->a.write_bcr (ioaddr, 20, 2);
1620
1621 if (netif_msg_ifup(lp))
1622 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
1623 dev->name, dev->irq,
1624 (u32) (lp->tx_ring_dma_addr),
1625 (u32) (lp->rx_ring_dma_addr),
1626 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
1627
1628 /* set/reset autoselect bit */
1629 val = lp->a.read_bcr (ioaddr, 2) & ~2;
1630 if (lp->options & PCNET32_PORT_ASEL)
1631 val |= 2;
1632 lp->a.write_bcr (ioaddr, 2, val);
1633
1634 /* handle full duplex setting */
1635 if (lp->mii_if.full_duplex) {
1636 val = lp->a.read_bcr (ioaddr, 9) & ~3;
1637 if (lp->options & PCNET32_PORT_FD) {
1638 val |= 1;
1639 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
1640 val |= 2;
1641 } else if (lp->options & PCNET32_PORT_ASEL) {
1642 /* workaround of xSeries250, turn on for 79C975 only */
1643 i = ((lp->a.read_csr(ioaddr, 88) |
1644 (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
1645 if (i == 0x2627)
1646 val |= 3;
1647 }
1648 lp->a.write_bcr (ioaddr, 9, val);
1649 }
1650
1651 /* set/reset GPSI bit in test register */
1652 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
1653 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
1654 val |= 0x10;
1655 lp->a.write_csr (ioaddr, 124, val);
1656
1657 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
1658 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
1659 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
1660 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
1661 if (lp->options & PCNET32_PORT_ASEL) {
1662 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
1663 if (netif_msg_link(lp))
1664 printk(KERN_DEBUG "%s: Setting 100Mb-Full Duplex.\n",
1665 dev->name);
1666 }
1667 }
1668 if (lp->phycount < 2) {
1669 /*
1670 * 24 Jun 2004 according AMD, in order to change the PHY,
1671 * DANAS (or DISPM for 79C976) must be set; then select the speed,
1672 * duplex, and/or enable auto negotiation, and clear DANAS
1673 */
1674 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
1675 lp->a.write_bcr(ioaddr, 32,
1676 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1677 /* disable Auto Negotiation, set 10Mpbs, HD */
1678 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
1679 if (lp->options & PCNET32_PORT_FD)
1680 val |= 0x10;
1681 if (lp->options & PCNET32_PORT_100)
1682 val |= 0x08;
1683 lp->a.write_bcr (ioaddr, 32, val);
1684 } else {
1685 if (lp->options & PCNET32_PORT_ASEL) {
1686 lp->a.write_bcr(ioaddr, 32,
1687 lp->a.read_bcr(ioaddr, 32) | 0x0080);
1688 /* enable auto negotiate, setup, disable fd */
1689 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
1690 val |= 0x20;
1691 lp->a.write_bcr(ioaddr, 32, val);
1692 }
1693 }
1694 } else {
1695 int first_phy = -1;
1696 u16 bmcr;
1697 u32 bcr9;
1698 struct ethtool_cmd ecmd;
1699
1700 /*
1701 * There is really no good other way to handle multiple PHYs
1702 * other than turning off all automatics
1703 */
1704 val = lp->a.read_bcr(ioaddr, 2);
1705 lp->a.write_bcr(ioaddr, 2, val & ~2);
1706 val = lp->a.read_bcr(ioaddr, 32);
1707 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
1708
1709 if (!(lp->options & PCNET32_PORT_ASEL)) {
1710 /* setup ecmd */
1711 ecmd.port = PORT_MII;
1712 ecmd.transceiver = XCVR_INTERNAL;
1713 ecmd.autoneg = AUTONEG_DISABLE;
1714 ecmd.speed = lp->options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
1715 bcr9 = lp->a.read_bcr(ioaddr, 9);
1716
1717 if (lp->options & PCNET32_PORT_FD) {
1718 ecmd.duplex = DUPLEX_FULL;
1719 bcr9 |= (1 << 0);
1720 } else {
1721 ecmd.duplex = DUPLEX_HALF;
1722 bcr9 |= ~(1 << 0);
1723 }
1724 lp->a.write_bcr(ioaddr, 9, bcr9);
1725 }
1726
1727 for (i=0; i<PCNET32_MAX_PHYS; i++) {
1728 if (lp->phymask & (1 << i)) {
1729 /* isolate all but the first PHY */
1730 bmcr = mdio_read(dev, i, MII_BMCR);
1731 if (first_phy == -1) {
1732 first_phy = i;
1733 mdio_write(dev, i, MII_BMCR, bmcr & ~BMCR_ISOLATE);
1734 } else {
1735 mdio_write(dev, i, MII_BMCR, bmcr | BMCR_ISOLATE);
1736 }
1737 /* use mii_ethtool_sset to setup PHY */
1738 lp->mii_if.phy_id = i;
1739 ecmd.phy_address = i;
1740 if (lp->options & PCNET32_PORT_ASEL) {
1741 mii_ethtool_gset(&lp->mii_if, &ecmd);
1742 ecmd.autoneg = AUTONEG_ENABLE;
1743 }
1744 mii_ethtool_sset(&lp->mii_if, &ecmd);
1745 }
1746 }
1747 lp->mii_if.phy_id = first_phy;
1748 if (netif_msg_link(lp))
1749 printk(KERN_INFO "%s: Using PHY number %d.\n", dev->name, first_phy);
1750 }
1751
1752 #ifdef DO_DXSUFLO
1753 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
1754 val = lp->a.read_csr (ioaddr, 3);
1755 val |= 0x40;
1756 lp->a.write_csr (ioaddr, 3, val);
1757 }
1758 #endif
1759
1760 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1761 pcnet32_load_multicast(dev);
1762
1763 if (pcnet32_init_ring(dev)) {
1764 rc = -ENOMEM;
1765 goto err_free_ring;
1766 }
1767
1768 /* Re-initialize the PCNET32, and start it when done. */
1769 lp->a.write_csr (ioaddr, 1, (lp->dma_addr +
1770 offsetof(struct pcnet32_private, init_block)) & 0xffff);
1771 lp->a.write_csr (ioaddr, 2, (lp->dma_addr +
1772 offsetof(struct pcnet32_private, init_block)) >> 16);
1773
1774 lp->a.write_csr (ioaddr, 4, 0x0915);
1775 lp->a.write_csr (ioaddr, 0, 0x0001);
1776
1777 netif_start_queue(dev);
1778
1779 /* Print the link status and start the watchdog */
1780 pcnet32_check_media (dev, 1);
1781 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1782
1783 i = 0;
1784 while (i++ < 100)
1785 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1786 break;
1787 /*
1788 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
1789 * reports that doing so triggers a bug in the '974.
1790 */
1791 lp->a.write_csr (ioaddr, 0, 0x0042);
1792
1793 if (netif_msg_ifup(lp))
1794 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
1795 dev->name, i, (u32) (lp->dma_addr +
1796 offsetof(struct pcnet32_private, init_block)),
1797 lp->a.read_csr(ioaddr, 0));
1798
1799 spin_unlock_irqrestore(&lp->lock, flags);
1800
1801 return 0; /* Always succeed */
1802
1803 err_free_ring:
1804 /* free any allocated skbuffs */
1805 for (i = 0; i < lp->rx_ring_size; i++) {
1806 lp->rx_ring[i].status = 0;
1807 if (lp->rx_skbuff[i]) {
1808 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
1809 PCI_DMA_FROMDEVICE);
1810 dev_kfree_skb(lp->rx_skbuff[i]);
1811 }
1812 lp->rx_skbuff[i] = NULL;
1813 lp->rx_dma_addr[i] = 0;
1814 }
1815
1816 pcnet32_free_ring(dev);
1817
1818 /*
1819 * Switch back to 16bit mode to avoid problems with dumb
1820 * DOS packet driver after a warm reboot
1821 */
1822 lp->a.write_bcr (ioaddr, 20, 4);
1823
1824 err_free_irq:
1825 spin_unlock_irqrestore(&lp->lock, flags);
1826 free_irq(dev->irq, dev);
1827 return rc;
1828 }
1829
1830 /*
1831 * The LANCE has been halted for one reason or another (busmaster memory
1832 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
1833 * etc.). Modern LANCE variants always reload their ring-buffer
1834 * configuration when restarted, so we must reinitialize our ring
1835 * context before restarting. As part of this reinitialization,
1836 * find all packets still on the Tx ring and pretend that they had been
1837 * sent (in effect, drop the packets on the floor) - the higher-level
1838 * protocols will time out and retransmit. It'd be better to shuffle
1839 * these skbs to a temp list and then actually re-Tx them after
1840 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
1841 */
1842
1843 static void
1844 pcnet32_purge_tx_ring(struct net_device *dev)
1845 {
1846 struct pcnet32_private *lp = dev->priv;
1847 int i;
1848
1849 for (i = 0; i < lp->tx_ring_size; i++) {
1850 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1851 wmb(); /* Make sure adapter sees owner change */
1852 if (lp->tx_skbuff[i]) {
1853 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
1854 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1855 dev_kfree_skb_any(lp->tx_skbuff[i]);
1856 }
1857 lp->tx_skbuff[i] = NULL;
1858 lp->tx_dma_addr[i] = 0;
1859 }
1860 }
1861
1862
1863 /* Initialize the PCNET32 Rx and Tx rings. */
1864 static int
1865 pcnet32_init_ring(struct net_device *dev)
1866 {
1867 struct pcnet32_private *lp = dev->priv;
1868 int i;
1869
1870 lp->tx_full = 0;
1871 lp->cur_rx = lp->cur_tx = 0;
1872 lp->dirty_rx = lp->dirty_tx = 0;
1873
1874 for (i = 0; i < lp->rx_ring_size; i++) {
1875 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1876 if (rx_skbuff == NULL) {
1877 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1878 /* there is not much, we can do at this point */
1879 if (pcnet32_debug & NETIF_MSG_DRV)
1880 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
1881 dev->name);
1882 return -1;
1883 }
1884 skb_reserve (rx_skbuff, 2);
1885 }
1886
1887 rmb();
1888 if (lp->rx_dma_addr[i] == 0)
1889 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->data,
1890 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
1891 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1892 lp->rx_ring[i].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
1893 wmb(); /* Make sure owner changes after all others are visible */
1894 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1895 }
1896 /* The Tx buffer address is filled in as needed, but we do need to clear
1897 * the upper ownership bit. */
1898 for (i = 0; i < lp->tx_ring_size; i++) {
1899 lp->tx_ring[i].status = 0; /* CPU owns buffer */
1900 wmb(); /* Make sure adapter sees owner change */
1901 lp->tx_ring[i].base = 0;
1902 lp->tx_dma_addr[i] = 0;
1903 }
1904
1905 lp->init_block.tlen_rlen = le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1906 for (i = 0; i < 6; i++)
1907 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1908 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->rx_ring_dma_addr);
1909 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->tx_ring_dma_addr);
1910 wmb(); /* Make sure all changes are visible */
1911 return 0;
1912 }
1913
1914 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
1915 * then flush the pending transmit operations, re-initialize the ring,
1916 * and tell the chip to initialize.
1917 */
1918 static void
1919 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1920 {
1921 struct pcnet32_private *lp = dev->priv;
1922 unsigned long ioaddr = dev->base_addr;
1923 int i;
1924
1925 /* wait for stop */
1926 for (i=0; i<100; i++)
1927 if (lp->a.read_csr(ioaddr, 0) & 0x0004)
1928 break;
1929
1930 if (i >= 100 && netif_msg_drv(lp))
1931 printk(KERN_ERR "%s: pcnet32_restart timed out waiting for stop.\n",
1932 dev->name);
1933
1934 pcnet32_purge_tx_ring(dev);
1935 if (pcnet32_init_ring(dev))
1936 return;
1937
1938 /* ReInit Ring */
1939 lp->a.write_csr (ioaddr, 0, 1);
1940 i = 0;
1941 while (i++ < 1000)
1942 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1943 break;
1944
1945 lp->a.write_csr (ioaddr, 0, csr0_bits);
1946 }
1947
1948
1949 static void
1950 pcnet32_tx_timeout (struct net_device *dev)
1951 {
1952 struct pcnet32_private *lp = dev->priv;
1953 unsigned long ioaddr = dev->base_addr, flags;
1954
1955 spin_lock_irqsave(&lp->lock, flags);
1956 /* Transmitter timeout, serious problems. */
1957 if (pcnet32_debug & NETIF_MSG_DRV)
1958 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1959 dev->name, lp->a.read_csr(ioaddr, 0));
1960 lp->a.write_csr (ioaddr, 0, 0x0004);
1961 lp->stats.tx_errors++;
1962 if (netif_msg_tx_err(lp)) {
1963 int i;
1964 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1965 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1966 lp->cur_rx);
1967 for (i = 0 ; i < lp->rx_ring_size; i++)
1968 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1969 le32_to_cpu(lp->rx_ring[i].base),
1970 (-le16_to_cpu(lp->rx_ring[i].buf_length)) & 0xffff,
1971 le32_to_cpu(lp->rx_ring[i].msg_length),
1972 le16_to_cpu(lp->rx_ring[i].status));
1973 for (i = 0 ; i < lp->tx_ring_size; i++)
1974 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1975 le32_to_cpu(lp->tx_ring[i].base),
1976 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
1977 le32_to_cpu(lp->tx_ring[i].misc),
1978 le16_to_cpu(lp->tx_ring[i].status));
1979 printk("\n");
1980 }
1981 pcnet32_restart(dev, 0x0042);
1982
1983 dev->trans_start = jiffies;
1984 netif_wake_queue(dev);
1985
1986 spin_unlock_irqrestore(&lp->lock, flags);
1987 }
1988
1989
1990 static int
1991 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1992 {
1993 struct pcnet32_private *lp = dev->priv;
1994 unsigned long ioaddr = dev->base_addr;
1995 u16 status;
1996 int entry;
1997 unsigned long flags;
1998
1999 spin_lock_irqsave(&lp->lock, flags);
2000
2001 if (netif_msg_tx_queued(lp)) {
2002 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2003 dev->name, lp->a.read_csr(ioaddr, 0));
2004 }
2005
2006 /* Default status -- will not enable Successful-TxDone
2007 * interrupt when that option is available to us.
2008 */
2009 status = 0x8300;
2010
2011 /* Fill in a Tx ring entry */
2012
2013 /* Mask to ring buffer boundary. */
2014 entry = lp->cur_tx & lp->tx_mod_mask;
2015
2016 /* Caution: the write order is important here, set the status
2017 * with the "ownership" bits last. */
2018
2019 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2020
2021 lp->tx_ring[entry].misc = 0x00000000;
2022
2023 lp->tx_skbuff[entry] = skb;
2024 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len,
2025 PCI_DMA_TODEVICE);
2026 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
2027 wmb(); /* Make sure owner changes after all others are visible */
2028 lp->tx_ring[entry].status = le16_to_cpu(status);
2029
2030 lp->cur_tx++;
2031 lp->stats.tx_bytes += skb->len;
2032
2033 /* Trigger an immediate send poll. */
2034 lp->a.write_csr (ioaddr, 0, 0x0048);
2035
2036 dev->trans_start = jiffies;
2037
2038 if (lp->tx_ring[(entry+1) & lp->tx_mod_mask].base != 0) {
2039 lp->tx_full = 1;
2040 netif_stop_queue(dev);
2041 }
2042 spin_unlock_irqrestore(&lp->lock, flags);
2043 return 0;
2044 }
2045
2046 /* The PCNET32 interrupt handler. */
2047 static irqreturn_t
2048 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2049 {
2050 struct net_device *dev = dev_id;
2051 struct pcnet32_private *lp;
2052 unsigned long ioaddr;
2053 u16 csr0,rap;
2054 int boguscnt = max_interrupt_work;
2055 int must_restart;
2056
2057 if (!dev) {
2058 if (pcnet32_debug & NETIF_MSG_INTR)
2059 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
2060 __FUNCTION__, irq);
2061 return IRQ_NONE;
2062 }
2063
2064 ioaddr = dev->base_addr;
2065 lp = dev->priv;
2066
2067 spin_lock(&lp->lock);
2068
2069 rap = lp->a.read_rap(ioaddr);
2070 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8f00 && --boguscnt >= 0) {
2071 if (csr0 == 0xffff) {
2072 break; /* PCMCIA remove happened */
2073 }
2074 /* Acknowledge all of the current interrupt sources ASAP. */
2075 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
2076
2077 must_restart = 0;
2078
2079 if (netif_msg_intr(lp))
2080 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2081 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
2082
2083 if (csr0 & 0x0400) /* Rx interrupt */
2084 pcnet32_rx(dev);
2085
2086 if (csr0 & 0x0200) { /* Tx-done interrupt */
2087 unsigned int dirty_tx = lp->dirty_tx;
2088 int delta;
2089
2090 while (dirty_tx != lp->cur_tx) {
2091 int entry = dirty_tx & lp->tx_mod_mask;
2092 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
2093
2094 if (status < 0)
2095 break; /* It still hasn't been Txed */
2096
2097 lp->tx_ring[entry].base = 0;
2098
2099 if (status & 0x4000) {
2100 /* There was an major error, log it. */
2101 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
2102 lp->stats.tx_errors++;
2103 if (netif_msg_tx_err(lp))
2104 printk(KERN_ERR "%s: Tx error status=%04x err_status=%08x\n",
2105 dev->name, status, err_status);
2106 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
2107 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
2108 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
2109 #ifndef DO_DXSUFLO
2110 if (err_status & 0x40000000) {
2111 lp->stats.tx_fifo_errors++;
2112 /* Ackk! On FIFO errors the Tx unit is turned off! */
2113 /* Remove this verbosity later! */
2114 if (netif_msg_tx_err(lp))
2115 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
2116 dev->name, csr0);
2117 must_restart = 1;
2118 }
2119 #else
2120 if (err_status & 0x40000000) {
2121 lp->stats.tx_fifo_errors++;
2122 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
2123 /* Ackk! On FIFO errors the Tx unit is turned off! */
2124 /* Remove this verbosity later! */
2125 if (netif_msg_tx_err(lp))
2126 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
2127 dev->name, csr0);
2128 must_restart = 1;
2129 }
2130 }
2131 #endif
2132 } else {
2133 if (status & 0x1800)
2134 lp->stats.collisions++;
2135 lp->stats.tx_packets++;
2136 }
2137
2138 /* We must free the original skb */
2139 if (lp->tx_skbuff[entry]) {
2140 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
2141 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
2142 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
2143 lp->tx_skbuff[entry] = NULL;
2144 lp->tx_dma_addr[entry] = 0;
2145 }
2146 dirty_tx++;
2147 }
2148
2149 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
2150 if (delta > lp->tx_ring_size) {
2151 if (netif_msg_drv(lp))
2152 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
2153 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
2154 dirty_tx += lp->tx_ring_size;
2155 delta -= lp->tx_ring_size;
2156 }
2157
2158 if (lp->tx_full &&
2159 netif_queue_stopped(dev) &&
2160 delta < lp->tx_ring_size - 2) {
2161 /* The ring is no longer full, clear tbusy. */
2162 lp->tx_full = 0;
2163 netif_wake_queue (dev);
2164 }
2165 lp->dirty_tx = dirty_tx;
2166 }
2167
2168 /* Log misc errors. */
2169 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
2170 if (csr0 & 0x1000) {
2171 /*
2172 * this happens when our receive ring is full. This shouldn't
2173 * be a problem as we will see normal rx interrupts for the frames
2174 * in the receive ring. But there are some PCI chipsets (I can
2175 * reproduce this on SP3G with Intel saturn chipset) which have
2176 * sometimes problems and will fill up the receive ring with
2177 * error descriptors. In this situation we don't get a rx
2178 * interrupt, but a missed frame interrupt sooner or later.
2179 * So we try to clean up our receive ring here.
2180 */
2181 pcnet32_rx(dev);
2182 lp->stats.rx_errors++; /* Missed a Rx frame. */
2183 }
2184 if (csr0 & 0x0800) {
2185 if (netif_msg_drv(lp))
2186 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
2187 dev->name, csr0);
2188 /* unlike for the lance, there is no restart needed */
2189 }
2190
2191 if (must_restart) {
2192 /* reset the chip to clear the error condition, then restart */
2193 lp->a.reset(ioaddr);
2194 lp->a.write_csr(ioaddr, 4, 0x0915);
2195 pcnet32_restart(dev, 0x0002);
2196 netif_wake_queue(dev);
2197 }
2198 }
2199
2200 /* Set interrupt enable. */
2201 lp->a.write_csr (ioaddr, 0, 0x0040);
2202 lp->a.write_rap (ioaddr,rap);
2203
2204 if (netif_msg_intr(lp))
2205 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2206 dev->name, lp->a.read_csr (ioaddr, 0));
2207
2208 spin_unlock(&lp->lock);
2209
2210 return IRQ_HANDLED;
2211 }
2212
2213 static int
2214 pcnet32_rx(struct net_device *dev)
2215 {
2216 struct pcnet32_private *lp = dev->priv;
2217 int entry = lp->cur_rx & lp->rx_mod_mask;
2218 int boguscnt = lp->rx_ring_size / 2;
2219
2220 /* If we own the next entry, it's a new packet. Send it up. */
2221 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
2222 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
2223
2224 if (status != 0x03) { /* There was an error. */
2225 /*
2226 * There is a tricky error noted by John Murphy,
2227 * <murf@perftech.com> to Russ Nelson: Even with full-sized
2228 * buffers it's possible for a jabber packet to use two
2229 * buffers, with only the last correctly noting the error.
2230 */
2231 if (status & 0x01) /* Only count a general error at the */
2232 lp->stats.rx_errors++; /* end of a packet.*/
2233 if (status & 0x20) lp->stats.rx_frame_errors++;
2234 if (status & 0x10) lp->stats.rx_over_errors++;
2235 if (status & 0x08) lp->stats.rx_crc_errors++;
2236 if (status & 0x04) lp->stats.rx_fifo_errors++;
2237 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
2238 } else {
2239 /* Malloc up new buffer, compatible with net-2e. */
2240 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
2241 struct sk_buff *skb;
2242
2243 /* Discard oversize frames. */
2244 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
2245 if (netif_msg_drv(lp))
2246 printk(KERN_ERR "%s: Impossible packet size %d!\n",
2247 dev->name, pkt_len);
2248 lp->stats.rx_errors++;
2249 } else if (pkt_len < 60) {
2250 if (netif_msg_rx_err(lp))
2251 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
2252 lp->stats.rx_errors++;
2253 } else {
2254 int rx_in_place = 0;
2255
2256 if (pkt_len > rx_copybreak) {
2257 struct sk_buff *newskb;
2258
2259 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
2260 skb_reserve (newskb, 2);
2261 skb = lp->rx_skbuff[entry];
2262 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry],
2263 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
2264 skb_put (skb, pkt_len);
2265 lp->rx_skbuff[entry] = newskb;
2266 newskb->dev = dev;
2267 lp->rx_dma_addr[entry] =
2268 pci_map_single(lp->pci_dev, newskb->data,
2269 PKT_BUF_SZ-2, PCI_DMA_FROMDEVICE);
2270 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
2271 rx_in_place = 1;
2272 } else
2273 skb = NULL;
2274 } else {
2275 skb = dev_alloc_skb(pkt_len+2);
2276 }
2277
2278 if (skb == NULL) {
2279 int i;
2280 if (netif_msg_drv(lp))
2281 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n",
2282 dev->name);
2283 for (i = 0; i < lp->rx_ring_size; i++)
2284 if ((short)le16_to_cpu(lp->rx_ring[(entry+i)
2285 & lp->rx_mod_mask].status) < 0)
2286 break;
2287
2288 if (i > lp->rx_ring_size -2) {
2289 lp->stats.rx_dropped++;
2290 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2291 wmb(); /* Make sure adapter sees owner change */
2292 lp->cur_rx++;
2293 }
2294 break;
2295 }
2296 skb->dev = dev;
2297 if (!rx_in_place) {
2298 skb_reserve(skb,2); /* 16 byte align */
2299 skb_put(skb,pkt_len); /* Make room */
2300 pci_dma_sync_single_for_cpu(lp->pci_dev,
2301 lp->rx_dma_addr[entry],
2302 PKT_BUF_SZ-2,
2303 PCI_DMA_FROMDEVICE);
2304 eth_copy_and_sum(skb,
2305 (unsigned char *)(lp->rx_skbuff[entry]->data),
2306 pkt_len,0);
2307 pci_dma_sync_single_for_device(lp->pci_dev,
2308 lp->rx_dma_addr[entry],
2309 PKT_BUF_SZ-2,
2310 PCI_DMA_FROMDEVICE);
2311 }
2312 lp->stats.rx_bytes += skb->len;
2313 skb->protocol=eth_type_trans(skb,dev);
2314 netif_rx(skb);
2315 dev->last_rx = jiffies;
2316 lp->stats.rx_packets++;
2317 }
2318 }
2319 /*
2320 * The docs say that the buffer length isn't touched, but Andrew Boyd
2321 * of QNX reports that some revs of the 79C965 clear it.
2322 */
2323 lp->rx_ring[entry].buf_length = le16_to_cpu(2-PKT_BUF_SZ);
2324 wmb(); /* Make sure owner changes after all others are visible */
2325 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
2326 entry = (++lp->cur_rx) & lp->rx_mod_mask;
2327 if (--boguscnt <= 0) break; /* don't stay in loop forever */
2328 }
2329
2330 return 0;
2331 }
2332
2333 static int
2334 pcnet32_close(struct net_device *dev)
2335 {
2336 unsigned long ioaddr = dev->base_addr;
2337 struct pcnet32_private *lp = dev->priv;
2338 int i;
2339 unsigned long flags;
2340
2341 del_timer_sync(&lp->watchdog_timer);
2342
2343 netif_stop_queue(dev);
2344
2345 spin_lock_irqsave(&lp->lock, flags);
2346
2347 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2348
2349 if (netif_msg_ifdown(lp))
2350 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
2351 dev->name, lp->a.read_csr (ioaddr, 0));
2352
2353 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2354 lp->a.write_csr (ioaddr, 0, 0x0004);
2355
2356 /*
2357 * Switch back to 16bit mode to avoid problems with dumb
2358 * DOS packet driver after a warm reboot
2359 */
2360 lp->a.write_bcr (ioaddr, 20, 4);
2361
2362 spin_unlock_irqrestore(&lp->lock, flags);
2363
2364 free_irq(dev->irq, dev);
2365
2366 spin_lock_irqsave(&lp->lock, flags);
2367
2368 /* free all allocated skbuffs */
2369 for (i = 0; i < lp->rx_ring_size; i++) {
2370 lp->rx_ring[i].status = 0;
2371 wmb(); /* Make sure adapter sees owner change */
2372 if (lp->rx_skbuff[i]) {
2373 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], PKT_BUF_SZ-2,
2374 PCI_DMA_FROMDEVICE);
2375 dev_kfree_skb(lp->rx_skbuff[i]);
2376 }
2377 lp->rx_skbuff[i] = NULL;
2378 lp->rx_dma_addr[i] = 0;
2379 }
2380
2381 for (i = 0; i < lp->tx_ring_size; i++) {
2382 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2383 wmb(); /* Make sure adapter sees owner change */
2384 if (lp->tx_skbuff[i]) {
2385 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2386 lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
2387 dev_kfree_skb(lp->tx_skbuff[i]);
2388 }
2389 lp->tx_skbuff[i] = NULL;
2390 lp->tx_dma_addr[i] = 0;
2391 }
2392
2393 spin_unlock_irqrestore(&lp->lock, flags);
2394
2395 return 0;
2396 }
2397
2398 static struct net_device_stats *
2399 pcnet32_get_stats(struct net_device *dev)
2400 {
2401 struct pcnet32_private *lp = dev->priv;
2402 unsigned long ioaddr = dev->base_addr;
2403 u16 saved_addr;
2404 unsigned long flags;
2405
2406 spin_lock_irqsave(&lp->lock, flags);
2407 saved_addr = lp->a.read_rap(ioaddr);
2408 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
2409 lp->a.write_rap(ioaddr, saved_addr);
2410 spin_unlock_irqrestore(&lp->lock, flags);
2411
2412 return &lp->stats;
2413 }
2414
2415 /* taken from the sunlance driver, which it took from the depca driver */
2416 static void pcnet32_load_multicast (struct net_device *dev)
2417 {
2418 struct pcnet32_private *lp = dev->priv;
2419 volatile struct pcnet32_init_block *ib = &lp->init_block;
2420 volatile u16 *mcast_table = (u16 *)&ib->filter;
2421 struct dev_mc_list *dmi=dev->mc_list;
2422 char *addrs;
2423 int i;
2424 u32 crc;
2425
2426 /* set all multicast bits */
2427 if (dev->flags & IFF_ALLMULTI) {
2428 ib->filter[0] = 0xffffffff;
2429 ib->filter[1] = 0xffffffff;
2430 return;
2431 }
2432 /* clear the multicast filter */
2433 ib->filter[0] = 0;
2434 ib->filter[1] = 0;
2435
2436 /* Add addresses */
2437 for (i = 0; i < dev->mc_count; i++) {
2438 addrs = dmi->dmi_addr;
2439 dmi = dmi->next;
2440
2441 /* multicast address? */
2442 if (!(*addrs & 1))
2443 continue;
2444
2445 crc = ether_crc_le(6, addrs);
2446 crc = crc >> 26;
2447 mcast_table [crc >> 4] = le16_to_cpu(
2448 le16_to_cpu(mcast_table [crc >> 4]) | (1 << (crc & 0xf)));
2449 }
2450 return;
2451 }
2452
2453
2454 /*
2455 * Set or clear the multicast filter for this adaptor.
2456 */
2457 static void pcnet32_set_multicast_list(struct net_device *dev)
2458 {
2459 unsigned long ioaddr = dev->base_addr, flags;
2460 struct pcnet32_private *lp = dev->priv;
2461
2462 spin_lock_irqsave(&lp->lock, flags);
2463 if (dev->flags&IFF_PROMISC) {
2464 /* Log any net taps. */
2465 if (netif_msg_hw(lp))
2466 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
2467 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
2468 } else {
2469 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2470 pcnet32_load_multicast (dev);
2471 }
2472
2473 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
2474 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
2475 netif_wake_queue(dev);
2476
2477 spin_unlock_irqrestore(&lp->lock, flags);
2478 }
2479
2480 /* This routine assumes that the lp->lock is held */
2481 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2482 {
2483 struct pcnet32_private *lp = dev->priv;
2484 unsigned long ioaddr = dev->base_addr;
2485 u16 val_out;
2486
2487 if (!lp->mii)
2488 return 0;
2489
2490 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2491 val_out = lp->a.read_bcr(ioaddr, 34);
2492
2493 return val_out;
2494 }
2495
2496 /* This routine assumes that the lp->lock is held */
2497 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2498 {
2499 struct pcnet32_private *lp = dev->priv;
2500 unsigned long ioaddr = dev->base_addr;
2501
2502 if (!lp->mii)
2503 return;
2504
2505 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2506 lp->a.write_bcr(ioaddr, 34, val);
2507 }
2508
2509 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2510 {
2511 struct pcnet32_private *lp = dev->priv;
2512 int rc;
2513 unsigned long flags;
2514
2515 /* SIOC[GS]MIIxxx ioctls */
2516 if (lp->mii) {
2517 spin_lock_irqsave(&lp->lock, flags);
2518 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2519 spin_unlock_irqrestore(&lp->lock, flags);
2520 } else {
2521 rc = -EOPNOTSUPP;
2522 }
2523
2524 return rc;
2525 }
2526
2527 static int pcnet32_check_otherphy(struct net_device *dev)
2528 {
2529 struct pcnet32_private *lp = dev->priv;
2530 struct mii_if_info mii = lp->mii_if;
2531 u16 bmcr;
2532 int i;
2533
2534 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2535 if (i == lp->mii_if.phy_id)
2536 continue; /* skip active phy */
2537 if (lp->phymask & (1 << i)) {
2538 mii.phy_id = i;
2539 if (mii_link_ok(&mii)) {
2540 /* found PHY with active link */
2541 if (netif_msg_link(lp))
2542 printk(KERN_INFO "%s: Using PHY number %d.\n", dev->name, i);
2543
2544 /* isolate inactive phy */
2545 bmcr = mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2546 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR, bmcr | BMCR_ISOLATE);
2547
2548 /* de-isolate new phy */
2549 bmcr = mdio_read(dev, i, MII_BMCR);
2550 mdio_write(dev, i, MII_BMCR, bmcr & ~BMCR_ISOLATE);
2551
2552 /* set new phy address */
2553 lp->mii_if.phy_id = i;
2554 return 1;
2555 }
2556 }
2557 }
2558 return 0;
2559 }
2560
2561 /*
2562 * Show the status of the media. Similar to mii_check_media however it
2563 * correctly shows the link speed for all (tested) pcnet32 variants.
2564 * Devices with no mii just report link state without speed.
2565 *
2566 * Caller is assumed to hold and release the lp->lock.
2567 */
2568
2569 static void pcnet32_check_media(struct net_device *dev, int verbose)
2570 {
2571 struct pcnet32_private *lp = dev->priv;
2572 int curr_link;
2573 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2574 u32 bcr9;
2575
2576 if (lp->mii) {
2577 curr_link = mii_link_ok(&lp->mii_if);
2578 } else {
2579 ulong ioaddr = dev->base_addr; /* card base I/O address */
2580 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2581 }
2582 if (!curr_link) {
2583 if (prev_link || verbose) {
2584 netif_carrier_off(dev);
2585 if (netif_msg_link(lp))
2586 printk(KERN_INFO "%s: link down\n", dev->name);
2587 }
2588 if (lp->phycount > 1) {
2589 curr_link = pcnet32_check_otherphy(dev);
2590 prev_link = 0;
2591 }
2592 } else if (verbose || !prev_link) {
2593 netif_carrier_on(dev);
2594 if (lp->mii) {
2595 if (netif_msg_link(lp)) {
2596 struct ethtool_cmd ecmd;
2597 mii_ethtool_gset(&lp->mii_if, &ecmd);
2598 printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n",
2599 dev->name,
2600 (ecmd.speed == SPEED_100) ? "100" : "10",
2601 (ecmd.duplex == DUPLEX_FULL) ? "full" : "half");
2602 }
2603 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2604 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2605 if (lp->mii_if.full_duplex)
2606 bcr9 |= (1 << 0);
2607 else
2608 bcr9 &= ~(1 << 0);
2609 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2610 }
2611 } else {
2612 if (netif_msg_link(lp))
2613 printk(KERN_INFO "%s: link up\n", dev->name);
2614 }
2615 }
2616 }
2617
2618 /*
2619 * Check for loss of link and link establishment.
2620 * Can not use mii_check_media because it does nothing if mode is forced.
2621 */
2622
2623 static void pcnet32_watchdog(struct net_device *dev)
2624 {
2625 struct pcnet32_private *lp = dev->priv;
2626 unsigned long flags;
2627
2628 /* Print the link status if it has changed */
2629 spin_lock_irqsave(&lp->lock, flags);
2630 pcnet32_check_media(dev, 0);
2631 spin_unlock_irqrestore(&lp->lock, flags);
2632
2633 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2634 }
2635
2636 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2637 {
2638 struct net_device *dev = pci_get_drvdata(pdev);
2639
2640 if (dev) {
2641 struct pcnet32_private *lp = dev->priv;
2642
2643 unregister_netdev(dev);
2644 pcnet32_free_ring(dev);
2645 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2646 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2647 free_netdev(dev);
2648 pci_disable_device(pdev);
2649 pci_set_drvdata(pdev, NULL);
2650 }
2651 }
2652
2653 static struct pci_driver pcnet32_driver = {
2654 .name = DRV_NAME,
2655 .probe = pcnet32_probe_pci,
2656 .remove = __devexit_p(pcnet32_remove_one),
2657 .id_table = pcnet32_pci_tbl,
2658 };
2659
2660 /* An additional parameter that may be passed in... */
2661 static int debug = -1;
2662 static int tx_start_pt = -1;
2663 static int pcnet32_have_pci;
2664
2665 module_param(debug, int, 0);
2666 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2667 module_param(max_interrupt_work, int, 0);
2668 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
2669 module_param(rx_copybreak, int, 0);
2670 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2671 module_param(tx_start_pt, int, 0);
2672 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2673 module_param(pcnet32vlb, int, 0);
2674 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2675 module_param_array(options, int, NULL, 0);
2676 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2677 module_param_array(full_duplex, int, NULL, 0);
2678 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2679 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2680 module_param_array(homepna, int, NULL, 0);
2681 MODULE_PARM_DESC(homepna, DRV_NAME " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2682
2683 MODULE_AUTHOR("Thomas Bogendoerfer");
2684 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2685 MODULE_LICENSE("GPL");
2686
2687 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2688
2689 static int __init pcnet32_init_module(void)
2690 {
2691 printk(KERN_INFO "%s", version);
2692
2693 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2694
2695 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2696 tx_start = tx_start_pt;
2697
2698 /* find the PCI devices */
2699 if (!pci_module_init(&pcnet32_driver))
2700 pcnet32_have_pci = 1;
2701
2702 /* should we find any remaining VLbus devices ? */
2703 if (pcnet32vlb)
2704 pcnet32_probe_vlbus();
2705
2706 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2707 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2708
2709 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2710 }
2711
2712 static void __exit pcnet32_cleanup_module(void)
2713 {
2714 struct net_device *next_dev;
2715
2716 while (pcnet32_dev) {
2717 struct pcnet32_private *lp = pcnet32_dev->priv;
2718 next_dev = lp->next;
2719 unregister_netdev(pcnet32_dev);
2720 pcnet32_free_ring(pcnet32_dev);
2721 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2722 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2723 free_netdev(pcnet32_dev);
2724 pcnet32_dev = next_dev;
2725 }
2726
2727 if (pcnet32_have_pci)
2728 pci_unregister_driver(&pcnet32_driver);
2729 }
2730
2731 module_init(pcnet32_init_module);
2732 module_exit(pcnet32_cleanup_module);
2733
2734 /*
2735 * Local variables:
2736 * c-indent-level: 4
2737 * tab-width: 8
2738 * End:
2739 */
Linux kernel - Deliverables
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