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pcnet32: fix non-napi packet reception
[deliverable/linux.git] / drivers / net / pcnet32.c
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #ifdef CONFIG_PCNET32_NAPI
26 #define DRV_VERSION "1.34-NAPI"
27 #else
28 #define DRV_VERSION "1.34"
29 #endif
30 #define DRV_RELDATE "14.Aug.2007"
31 #define PFX DRV_NAME ": "
32
33 static const char *const version =
34 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/string.h>
39 #include <linux/errno.h>
40 #include <linux/ioport.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <linux/ethtool.h>
47 #include <linux/mii.h>
48 #include <linux/crc32.h>
49 #include <linux/netdevice.h>
50 #include <linux/etherdevice.h>
51 #include <linux/skbuff.h>
52 #include <linux/spinlock.h>
53 #include <linux/moduleparam.h>
54 #include <linux/bitops.h>
55
56 #include <asm/dma.h>
57 #include <asm/io.h>
58 #include <asm/uaccess.h>
59 #include <asm/irq.h>
60
61 /*
62 * PCI device identifiers for "new style" Linux PCI Device Drivers
63 */
64 static struct pci_device_id pcnet32_pci_tbl[] = {
65 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
66 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
67
68 /*
69 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
70 * the incorrect vendor id.
71 */
72 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
73 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
74
75 { } /* terminate list */
76 };
77
78 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
79
80 static int cards_found;
81
82 /*
83 * VLB I/O addresses
84 */
85 static unsigned int pcnet32_portlist[] __initdata =
86 { 0x300, 0x320, 0x340, 0x360, 0 };
87
88 static int pcnet32_debug = 0;
89 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
90 static int pcnet32vlb; /* check for VLB cards ? */
91
92 static struct net_device *pcnet32_dev;
93
94 static int max_interrupt_work = 2;
95 static int rx_copybreak = 200;
96
97 #define PCNET32_PORT_AUI 0x00
98 #define PCNET32_PORT_10BT 0x01
99 #define PCNET32_PORT_GPSI 0x02
100 #define PCNET32_PORT_MII 0x03
101
102 #define PCNET32_PORT_PORTSEL 0x03
103 #define PCNET32_PORT_ASEL 0x04
104 #define PCNET32_PORT_100 0x40
105 #define PCNET32_PORT_FD 0x80
106
107 #define PCNET32_DMA_MASK 0xffffffff
108
109 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
110 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
111
112 /*
113 * table to translate option values from tulip
114 * to internal options
115 */
116 static const unsigned char options_mapping[] = {
117 PCNET32_PORT_ASEL, /* 0 Auto-select */
118 PCNET32_PORT_AUI, /* 1 BNC/AUI */
119 PCNET32_PORT_AUI, /* 2 AUI/BNC */
120 PCNET32_PORT_ASEL, /* 3 not supported */
121 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
122 PCNET32_PORT_ASEL, /* 5 not supported */
123 PCNET32_PORT_ASEL, /* 6 not supported */
124 PCNET32_PORT_ASEL, /* 7 not supported */
125 PCNET32_PORT_ASEL, /* 8 not supported */
126 PCNET32_PORT_MII, /* 9 MII 10baseT */
127 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
128 PCNET32_PORT_MII, /* 11 MII (autosel) */
129 PCNET32_PORT_10BT, /* 12 10BaseT */
130 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
131 /* 14 MII 100BaseTx-FD */
132 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
133 PCNET32_PORT_ASEL /* 15 not supported */
134 };
135
136 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
137 "Loopback test (offline)"
138 };
139
140 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
141
142 #define PCNET32_NUM_REGS 136
143
144 #define MAX_UNITS 8 /* More are supported, limit only on options */
145 static int options[MAX_UNITS];
146 static int full_duplex[MAX_UNITS];
147 static int homepna[MAX_UNITS];
148
149 /*
150 * Theory of Operation
151 *
152 * This driver uses the same software structure as the normal lance
153 * driver. So look for a verbose description in lance.c. The differences
154 * to the normal lance driver is the use of the 32bit mode of PCnet32
155 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
156 * 16MB limitation and we don't need bounce buffers.
157 */
158
159 /*
160 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
161 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
162 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
163 */
164 #ifndef PCNET32_LOG_TX_BUFFERS
165 #define PCNET32_LOG_TX_BUFFERS 4
166 #define PCNET32_LOG_RX_BUFFERS 5
167 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
168 #define PCNET32_LOG_MAX_RX_BUFFERS 9
169 #endif
170
171 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
172 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
173
174 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
175 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
176
177 #define PKT_BUF_SZ 1544
178
179 /* Offsets from base I/O address. */
180 #define PCNET32_WIO_RDP 0x10
181 #define PCNET32_WIO_RAP 0x12
182 #define PCNET32_WIO_RESET 0x14
183 #define PCNET32_WIO_BDP 0x16
184
185 #define PCNET32_DWIO_RDP 0x10
186 #define PCNET32_DWIO_RAP 0x14
187 #define PCNET32_DWIO_RESET 0x18
188 #define PCNET32_DWIO_BDP 0x1C
189
190 #define PCNET32_TOTAL_SIZE 0x20
191
192 #define CSR0 0
193 #define CSR0_INIT 0x1
194 #define CSR0_START 0x2
195 #define CSR0_STOP 0x4
196 #define CSR0_TXPOLL 0x8
197 #define CSR0_INTEN 0x40
198 #define CSR0_IDON 0x0100
199 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
200 #define PCNET32_INIT_LOW 1
201 #define PCNET32_INIT_HIGH 2
202 #define CSR3 3
203 #define CSR4 4
204 #define CSR5 5
205 #define CSR5_SUSPEND 0x0001
206 #define CSR15 15
207 #define PCNET32_MC_FILTER 8
208
209 #define PCNET32_79C970A 0x2621
210
211 /* The PCNET32 Rx and Tx ring descriptors. */
212 struct pcnet32_rx_head {
213 __le32 base;
214 __le16 buf_length; /* two`s complement of length */
215 __le16 status;
216 __le32 msg_length;
217 __le32 reserved;
218 };
219
220 struct pcnet32_tx_head {
221 __le32 base;
222 __le16 length; /* two`s complement of length */
223 __le16 status;
224 __le32 misc;
225 __le32 reserved;
226 };
227
228 /* The PCNET32 32-Bit initialization block, described in databook. */
229 struct pcnet32_init_block {
230 __le16 mode;
231 __le16 tlen_rlen;
232 u8 phys_addr[6];
233 __le16 reserved;
234 __le32 filter[2];
235 /* Receive and transmit ring base, along with extra bits. */
236 __le32 rx_ring;
237 __le32 tx_ring;
238 };
239
240 /* PCnet32 access functions */
241 struct pcnet32_access {
242 u16 (*read_csr) (unsigned long, int);
243 void (*write_csr) (unsigned long, int, u16);
244 u16 (*read_bcr) (unsigned long, int);
245 void (*write_bcr) (unsigned long, int, u16);
246 u16 (*read_rap) (unsigned long);
247 void (*write_rap) (unsigned long, u16);
248 void (*reset) (unsigned long);
249 };
250
251 /*
252 * The first field of pcnet32_private is read by the ethernet device
253 * so the structure should be allocated using pci_alloc_consistent().
254 */
255 struct pcnet32_private {
256 struct pcnet32_init_block *init_block;
257 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
258 struct pcnet32_rx_head *rx_ring;
259 struct pcnet32_tx_head *tx_ring;
260 dma_addr_t init_dma_addr;/* DMA address of beginning of the init block,
261 returned by pci_alloc_consistent */
262 struct pci_dev *pci_dev;
263 const char *name;
264 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
265 struct sk_buff **tx_skbuff;
266 struct sk_buff **rx_skbuff;
267 dma_addr_t *tx_dma_addr;
268 dma_addr_t *rx_dma_addr;
269 struct pcnet32_access a;
270 spinlock_t lock; /* Guard lock */
271 unsigned int cur_rx, cur_tx; /* The next free ring entry */
272 unsigned int rx_ring_size; /* current rx ring size */
273 unsigned int tx_ring_size; /* current tx ring size */
274 unsigned int rx_mod_mask; /* rx ring modular mask */
275 unsigned int tx_mod_mask; /* tx ring modular mask */
276 unsigned short rx_len_bits;
277 unsigned short tx_len_bits;
278 dma_addr_t rx_ring_dma_addr;
279 dma_addr_t tx_ring_dma_addr;
280 unsigned int dirty_rx, /* ring entries to be freed. */
281 dirty_tx;
282
283 struct net_device *dev;
284 struct napi_struct napi;
285 struct net_device_stats stats;
286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
297
298 /* each bit indicates an available PHY */
299 u32 phymask;
300 unsigned short chip_version; /* which variant this is */
301 };
302
303 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305 static int pcnet32_open(struct net_device *);
306 static int pcnet32_init_ring(struct net_device *);
307 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
308 static void pcnet32_tx_timeout(struct net_device *dev);
309 static irqreturn_t pcnet32_interrupt(int, void *);
310 static int pcnet32_close(struct net_device *);
311 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312 static void pcnet32_load_multicast(struct net_device *dev);
313 static void pcnet32_set_multicast_list(struct net_device *);
314 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
315 static void pcnet32_watchdog(struct net_device *);
316 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
317 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
319 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320 static void pcnet32_ethtool_test(struct net_device *dev,
321 struct ethtool_test *eth_test, u64 * data);
322 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
323 static int pcnet32_phys_id(struct net_device *dev, u32 data);
324 static void pcnet32_led_blink_callback(struct net_device *dev);
325 static int pcnet32_get_regs_len(struct net_device *dev);
326 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
327 void *ptr);
328 static void pcnet32_purge_tx_ring(struct net_device *dev);
329 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
330 static void pcnet32_free_ring(struct net_device *dev);
331 static void pcnet32_check_media(struct net_device *dev, int verbose);
332
333 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
334 {
335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
337 }
338
339 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
340 {
341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
343 }
344
345 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
346 {
347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
349 }
350
351 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
352 {
353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
355 }
356
357 static u16 pcnet32_wio_read_rap(unsigned long addr)
358 {
359 return inw(addr + PCNET32_WIO_RAP);
360 }
361
362 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
363 {
364 outw(val, addr + PCNET32_WIO_RAP);
365 }
366
367 static void pcnet32_wio_reset(unsigned long addr)
368 {
369 inw(addr + PCNET32_WIO_RESET);
370 }
371
372 static int pcnet32_wio_check(unsigned long addr)
373 {
374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
376 }
377
378 static struct pcnet32_access pcnet32_wio = {
379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
386 };
387
388 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
389 {
390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
392 }
393
394 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
395 {
396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
398 }
399
400 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
401 {
402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
404 }
405
406 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
407 {
408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
410 }
411
412 static u16 pcnet32_dwio_read_rap(unsigned long addr)
413 {
414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
415 }
416
417 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
418 {
419 outl(val, addr + PCNET32_DWIO_RAP);
420 }
421
422 static void pcnet32_dwio_reset(unsigned long addr)
423 {
424 inl(addr + PCNET32_DWIO_RESET);
425 }
426
427 static int pcnet32_dwio_check(unsigned long addr)
428 {
429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
431 }
432
433 static struct pcnet32_access pcnet32_dwio = {
434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
441 };
442
443 static void pcnet32_netif_stop(struct net_device *dev)
444 {
445 struct pcnet32_private *lp = netdev_priv(dev);
446 dev->trans_start = jiffies;
447 #ifdef CONFIG_PCNET32_NAPI
448 napi_disable(&lp->napi);
449 #endif
450 netif_tx_disable(dev);
451 }
452
453 static void pcnet32_netif_start(struct net_device *dev)
454 {
455 struct pcnet32_private *lp = netdev_priv(dev);
456 netif_wake_queue(dev);
457 #ifdef CONFIG_PCNET32_NAPI
458 napi_enable(&lp->napi);
459 #endif
460 }
461
462 /*
463 * Allocate space for the new sized tx ring.
464 * Free old resources
465 * Save new resources.
466 * Any failure keeps old resources.
467 * Must be called with lp->lock held.
468 */
469 static void pcnet32_realloc_tx_ring(struct net_device *dev,
470 struct pcnet32_private *lp,
471 unsigned int size)
472 {
473 dma_addr_t new_ring_dma_addr;
474 dma_addr_t *new_dma_addr_list;
475 struct pcnet32_tx_head *new_tx_ring;
476 struct sk_buff **new_skb_list;
477
478 pcnet32_purge_tx_ring(dev);
479
480 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
481 sizeof(struct pcnet32_tx_head) *
482 (1 << size),
483 &new_ring_dma_addr);
484 if (new_tx_ring == NULL) {
485 if (netif_msg_drv(lp))
486 printk("\n" KERN_ERR
487 "%s: Consistent memory allocation failed.\n",
488 dev->name);
489 return;
490 }
491 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
492
493 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
494 GFP_ATOMIC);
495 if (!new_dma_addr_list) {
496 if (netif_msg_drv(lp))
497 printk("\n" KERN_ERR
498 "%s: Memory allocation failed.\n", dev->name);
499 goto free_new_tx_ring;
500 }
501
502 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
503 GFP_ATOMIC);
504 if (!new_skb_list) {
505 if (netif_msg_drv(lp))
506 printk("\n" KERN_ERR
507 "%s: Memory allocation failed.\n", dev->name);
508 goto free_new_lists;
509 }
510
511 kfree(lp->tx_skbuff);
512 kfree(lp->tx_dma_addr);
513 pci_free_consistent(lp->pci_dev,
514 sizeof(struct pcnet32_tx_head) *
515 lp->tx_ring_size, lp->tx_ring,
516 lp->tx_ring_dma_addr);
517
518 lp->tx_ring_size = (1 << size);
519 lp->tx_mod_mask = lp->tx_ring_size - 1;
520 lp->tx_len_bits = (size << 12);
521 lp->tx_ring = new_tx_ring;
522 lp->tx_ring_dma_addr = new_ring_dma_addr;
523 lp->tx_dma_addr = new_dma_addr_list;
524 lp->tx_skbuff = new_skb_list;
525 return;
526
527 free_new_lists:
528 kfree(new_dma_addr_list);
529 free_new_tx_ring:
530 pci_free_consistent(lp->pci_dev,
531 sizeof(struct pcnet32_tx_head) *
532 (1 << size),
533 new_tx_ring,
534 new_ring_dma_addr);
535 return;
536 }
537
538 /*
539 * Allocate space for the new sized rx ring.
540 * Re-use old receive buffers.
541 * alloc extra buffers
542 * free unneeded buffers
543 * free unneeded buffers
544 * Save new resources.
545 * Any failure keeps old resources.
546 * Must be called with lp->lock held.
547 */
548 static void pcnet32_realloc_rx_ring(struct net_device *dev,
549 struct pcnet32_private *lp,
550 unsigned int size)
551 {
552 dma_addr_t new_ring_dma_addr;
553 dma_addr_t *new_dma_addr_list;
554 struct pcnet32_rx_head *new_rx_ring;
555 struct sk_buff **new_skb_list;
556 int new, overlap;
557
558 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
559 sizeof(struct pcnet32_rx_head) *
560 (1 << size),
561 &new_ring_dma_addr);
562 if (new_rx_ring == NULL) {
563 if (netif_msg_drv(lp))
564 printk("\n" KERN_ERR
565 "%s: Consistent memory allocation failed.\n",
566 dev->name);
567 return;
568 }
569 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
570
571 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
572 GFP_ATOMIC);
573 if (!new_dma_addr_list) {
574 if (netif_msg_drv(lp))
575 printk("\n" KERN_ERR
576 "%s: Memory allocation failed.\n", dev->name);
577 goto free_new_rx_ring;
578 }
579
580 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
581 GFP_ATOMIC);
582 if (!new_skb_list) {
583 if (netif_msg_drv(lp))
584 printk("\n" KERN_ERR
585 "%s: Memory allocation failed.\n", dev->name);
586 goto free_new_lists;
587 }
588
589 /* first copy the current receive buffers */
590 overlap = min(size, lp->rx_ring_size);
591 for (new = 0; new < overlap; new++) {
592 new_rx_ring[new] = lp->rx_ring[new];
593 new_dma_addr_list[new] = lp->rx_dma_addr[new];
594 new_skb_list[new] = lp->rx_skbuff[new];
595 }
596 /* now allocate any new buffers needed */
597 for (; new < size; new++ ) {
598 struct sk_buff *rx_skbuff;
599 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
600 if (!(rx_skbuff = new_skb_list[new])) {
601 /* keep the original lists and buffers */
602 if (netif_msg_drv(lp))
603 printk(KERN_ERR
604 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
605 dev->name);
606 goto free_all_new;
607 }
608 skb_reserve(rx_skbuff, 2);
609
610 new_dma_addr_list[new] =
611 pci_map_single(lp->pci_dev, rx_skbuff->data,
612 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
613 new_rx_ring[new].base = cpu_to_le32(new_dma_addr_list[new]);
614 new_rx_ring[new].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
615 new_rx_ring[new].status = cpu_to_le16(0x8000);
616 }
617 /* and free any unneeded buffers */
618 for (; new < lp->rx_ring_size; new++) {
619 if (lp->rx_skbuff[new]) {
620 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
621 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
622 dev_kfree_skb(lp->rx_skbuff[new]);
623 }
624 }
625
626 kfree(lp->rx_skbuff);
627 kfree(lp->rx_dma_addr);
628 pci_free_consistent(lp->pci_dev,
629 sizeof(struct pcnet32_rx_head) *
630 lp->rx_ring_size, lp->rx_ring,
631 lp->rx_ring_dma_addr);
632
633 lp->rx_ring_size = (1 << size);
634 lp->rx_mod_mask = lp->rx_ring_size - 1;
635 lp->rx_len_bits = (size << 4);
636 lp->rx_ring = new_rx_ring;
637 lp->rx_ring_dma_addr = new_ring_dma_addr;
638 lp->rx_dma_addr = new_dma_addr_list;
639 lp->rx_skbuff = new_skb_list;
640 return;
641
642 free_all_new:
643 for (; --new >= lp->rx_ring_size; ) {
644 if (new_skb_list[new]) {
645 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
646 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
647 dev_kfree_skb(new_skb_list[new]);
648 }
649 }
650 kfree(new_skb_list);
651 free_new_lists:
652 kfree(new_dma_addr_list);
653 free_new_rx_ring:
654 pci_free_consistent(lp->pci_dev,
655 sizeof(struct pcnet32_rx_head) *
656 (1 << size),
657 new_rx_ring,
658 new_ring_dma_addr);
659 return;
660 }
661
662 static void pcnet32_purge_rx_ring(struct net_device *dev)
663 {
664 struct pcnet32_private *lp = netdev_priv(dev);
665 int i;
666
667 /* free all allocated skbuffs */
668 for (i = 0; i < lp->rx_ring_size; i++) {
669 lp->rx_ring[i].status = 0; /* CPU owns buffer */
670 wmb(); /* Make sure adapter sees owner change */
671 if (lp->rx_skbuff[i]) {
672 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
673 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
674 dev_kfree_skb_any(lp->rx_skbuff[i]);
675 }
676 lp->rx_skbuff[i] = NULL;
677 lp->rx_dma_addr[i] = 0;
678 }
679 }
680
681 #ifdef CONFIG_NET_POLL_CONTROLLER
682 static void pcnet32_poll_controller(struct net_device *dev)
683 {
684 disable_irq(dev->irq);
685 pcnet32_interrupt(0, dev);
686 enable_irq(dev->irq);
687 }
688 #endif
689
690 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
691 {
692 struct pcnet32_private *lp = netdev_priv(dev);
693 unsigned long flags;
694 int r = -EOPNOTSUPP;
695
696 if (lp->mii) {
697 spin_lock_irqsave(&lp->lock, flags);
698 mii_ethtool_gset(&lp->mii_if, cmd);
699 spin_unlock_irqrestore(&lp->lock, flags);
700 r = 0;
701 }
702 return r;
703 }
704
705 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
706 {
707 struct pcnet32_private *lp = netdev_priv(dev);
708 unsigned long flags;
709 int r = -EOPNOTSUPP;
710
711 if (lp->mii) {
712 spin_lock_irqsave(&lp->lock, flags);
713 r = mii_ethtool_sset(&lp->mii_if, cmd);
714 spin_unlock_irqrestore(&lp->lock, flags);
715 }
716 return r;
717 }
718
719 static void pcnet32_get_drvinfo(struct net_device *dev,
720 struct ethtool_drvinfo *info)
721 {
722 struct pcnet32_private *lp = netdev_priv(dev);
723
724 strcpy(info->driver, DRV_NAME);
725 strcpy(info->version, DRV_VERSION);
726 if (lp->pci_dev)
727 strcpy(info->bus_info, pci_name(lp->pci_dev));
728 else
729 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
730 }
731
732 static u32 pcnet32_get_link(struct net_device *dev)
733 {
734 struct pcnet32_private *lp = netdev_priv(dev);
735 unsigned long flags;
736 int r;
737
738 spin_lock_irqsave(&lp->lock, flags);
739 if (lp->mii) {
740 r = mii_link_ok(&lp->mii_if);
741 } else if (lp->chip_version >= PCNET32_79C970A) {
742 ulong ioaddr = dev->base_addr; /* card base I/O address */
743 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
744 } else { /* can not detect link on really old chips */
745 r = 1;
746 }
747 spin_unlock_irqrestore(&lp->lock, flags);
748
749 return r;
750 }
751
752 static u32 pcnet32_get_msglevel(struct net_device *dev)
753 {
754 struct pcnet32_private *lp = netdev_priv(dev);
755 return lp->msg_enable;
756 }
757
758 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
759 {
760 struct pcnet32_private *lp = netdev_priv(dev);
761 lp->msg_enable = value;
762 }
763
764 static int pcnet32_nway_reset(struct net_device *dev)
765 {
766 struct pcnet32_private *lp = netdev_priv(dev);
767 unsigned long flags;
768 int r = -EOPNOTSUPP;
769
770 if (lp->mii) {
771 spin_lock_irqsave(&lp->lock, flags);
772 r = mii_nway_restart(&lp->mii_if);
773 spin_unlock_irqrestore(&lp->lock, flags);
774 }
775 return r;
776 }
777
778 static void pcnet32_get_ringparam(struct net_device *dev,
779 struct ethtool_ringparam *ering)
780 {
781 struct pcnet32_private *lp = netdev_priv(dev);
782
783 ering->tx_max_pending = TX_MAX_RING_SIZE;
784 ering->tx_pending = lp->tx_ring_size;
785 ering->rx_max_pending = RX_MAX_RING_SIZE;
786 ering->rx_pending = lp->rx_ring_size;
787 }
788
789 static int pcnet32_set_ringparam(struct net_device *dev,
790 struct ethtool_ringparam *ering)
791 {
792 struct pcnet32_private *lp = netdev_priv(dev);
793 unsigned long flags;
794 unsigned int size;
795 ulong ioaddr = dev->base_addr;
796 int i;
797
798 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
799 return -EINVAL;
800
801 if (netif_running(dev))
802 pcnet32_netif_stop(dev);
803
804 spin_lock_irqsave(&lp->lock, flags);
805 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
806
807 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
808
809 /* set the minimum ring size to 4, to allow the loopback test to work
810 * unchanged.
811 */
812 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
813 if (size <= (1 << i))
814 break;
815 }
816 if ((1 << i) != lp->tx_ring_size)
817 pcnet32_realloc_tx_ring(dev, lp, i);
818
819 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
820 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
821 if (size <= (1 << i))
822 break;
823 }
824 if ((1 << i) != lp->rx_ring_size)
825 pcnet32_realloc_rx_ring(dev, lp, i);
826
827 lp->napi.weight = lp->rx_ring_size / 2;
828
829 if (netif_running(dev)) {
830 pcnet32_netif_start(dev);
831 pcnet32_restart(dev, CSR0_NORMAL);
832 }
833
834 spin_unlock_irqrestore(&lp->lock, flags);
835
836 if (netif_msg_drv(lp))
837 printk(KERN_INFO
838 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
839 lp->rx_ring_size, lp->tx_ring_size);
840
841 return 0;
842 }
843
844 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
845 u8 * data)
846 {
847 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
848 }
849
850 static int pcnet32_get_sset_count(struct net_device *dev, int sset)
851 {
852 switch (sset) {
853 case ETH_SS_TEST:
854 return PCNET32_TEST_LEN;
855 default:
856 return -EOPNOTSUPP;
857 }
858 }
859
860 static void pcnet32_ethtool_test(struct net_device *dev,
861 struct ethtool_test *test, u64 * data)
862 {
863 struct pcnet32_private *lp = netdev_priv(dev);
864 int rc;
865
866 if (test->flags == ETH_TEST_FL_OFFLINE) {
867 rc = pcnet32_loopback_test(dev, data);
868 if (rc) {
869 if (netif_msg_hw(lp))
870 printk(KERN_DEBUG "%s: Loopback test failed.\n",
871 dev->name);
872 test->flags |= ETH_TEST_FL_FAILED;
873 } else if (netif_msg_hw(lp))
874 printk(KERN_DEBUG "%s: Loopback test passed.\n",
875 dev->name);
876 } else if (netif_msg_hw(lp))
877 printk(KERN_DEBUG
878 "%s: No tests to run (specify 'Offline' on ethtool).",
879 dev->name);
880 } /* end pcnet32_ethtool_test */
881
882 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
883 {
884 struct pcnet32_private *lp = netdev_priv(dev);
885 struct pcnet32_access *a = &lp->a; /* access to registers */
886 ulong ioaddr = dev->base_addr; /* card base I/O address */
887 struct sk_buff *skb; /* sk buff */
888 int x, i; /* counters */
889 int numbuffs = 4; /* number of TX/RX buffers and descs */
890 u16 status = 0x8300; /* TX ring status */
891 __le16 teststatus; /* test of ring status */
892 int rc; /* return code */
893 int size; /* size of packets */
894 unsigned char *packet; /* source packet data */
895 static const int data_len = 60; /* length of source packets */
896 unsigned long flags;
897 unsigned long ticks;
898
899 rc = 1; /* default to fail */
900
901 if (netif_running(dev))
902 #ifdef CONFIG_PCNET32_NAPI
903 pcnet32_netif_stop(dev);
904 #else
905 pcnet32_close(dev);
906 #endif
907
908 spin_lock_irqsave(&lp->lock, flags);
909 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
910
911 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
912
913 /* Reset the PCNET32 */
914 lp->a.reset(ioaddr);
915 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
916
917 /* switch pcnet32 to 32bit mode */
918 lp->a.write_bcr(ioaddr, 20, 2);
919
920 /* purge & init rings but don't actually restart */
921 pcnet32_restart(dev, 0x0000);
922
923 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
924
925 /* Initialize Transmit buffers. */
926 size = data_len + 15;
927 for (x = 0; x < numbuffs; x++) {
928 if (!(skb = dev_alloc_skb(size))) {
929 if (netif_msg_hw(lp))
930 printk(KERN_DEBUG
931 "%s: Cannot allocate skb at line: %d!\n",
932 dev->name, __LINE__);
933 goto clean_up;
934 } else {
935 packet = skb->data;
936 skb_put(skb, size); /* create space for data */
937 lp->tx_skbuff[x] = skb;
938 lp->tx_ring[x].length = cpu_to_le16(-skb->len);
939 lp->tx_ring[x].misc = 0;
940
941 /* put DA and SA into the skb */
942 for (i = 0; i < 6; i++)
943 *packet++ = dev->dev_addr[i];
944 for (i = 0; i < 6; i++)
945 *packet++ = dev->dev_addr[i];
946 /* type */
947 *packet++ = 0x08;
948 *packet++ = 0x06;
949 /* packet number */
950 *packet++ = x;
951 /* fill packet with data */
952 for (i = 0; i < data_len; i++)
953 *packet++ = i;
954
955 lp->tx_dma_addr[x] =
956 pci_map_single(lp->pci_dev, skb->data, skb->len,
957 PCI_DMA_TODEVICE);
958 lp->tx_ring[x].base = cpu_to_le32(lp->tx_dma_addr[x]);
959 wmb(); /* Make sure owner changes after all others are visible */
960 lp->tx_ring[x].status = cpu_to_le16(status);
961 }
962 }
963
964 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
965 a->write_bcr(ioaddr, 32, x | 0x0002);
966
967 /* set int loopback in CSR15 */
968 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
969 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
970
971 teststatus = cpu_to_le16(0x8000);
972 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
973
974 /* Check status of descriptors */
975 for (x = 0; x < numbuffs; x++) {
976 ticks = 0;
977 rmb();
978 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
979 spin_unlock_irqrestore(&lp->lock, flags);
980 msleep(1);
981 spin_lock_irqsave(&lp->lock, flags);
982 rmb();
983 ticks++;
984 }
985 if (ticks == 200) {
986 if (netif_msg_hw(lp))
987 printk("%s: Desc %d failed to reset!\n",
988 dev->name, x);
989 break;
990 }
991 }
992
993 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
994 wmb();
995 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
996 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
997
998 for (x = 0; x < numbuffs; x++) {
999 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
1000 skb = lp->rx_skbuff[x];
1001 for (i = 0; i < size; i++) {
1002 printk("%02x ", *(skb->data + i));
1003 }
1004 printk("\n");
1005 }
1006 }
1007
1008 x = 0;
1009 rc = 0;
1010 while (x < numbuffs && !rc) {
1011 skb = lp->rx_skbuff[x];
1012 packet = lp->tx_skbuff[x]->data;
1013 for (i = 0; i < size; i++) {
1014 if (*(skb->data + i) != packet[i]) {
1015 if (netif_msg_hw(lp))
1016 printk(KERN_DEBUG
1017 "%s: Error in compare! %2x - %02x %02x\n",
1018 dev->name, i, *(skb->data + i),
1019 packet[i]);
1020 rc = 1;
1021 break;
1022 }
1023 }
1024 x++;
1025 }
1026
1027 clean_up:
1028 *data1 = rc;
1029 pcnet32_purge_tx_ring(dev);
1030
1031 x = a->read_csr(ioaddr, CSR15);
1032 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1033
1034 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1035 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1036
1037 #ifdef CONFIG_PCNET32_NAPI
1038 if (netif_running(dev)) {
1039 pcnet32_netif_start(dev);
1040 pcnet32_restart(dev, CSR0_NORMAL);
1041 } else {
1042 pcnet32_purge_rx_ring(dev);
1043 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1044 }
1045 spin_unlock_irqrestore(&lp->lock, flags);
1046 #else
1047 if (netif_running(dev)) {
1048 spin_unlock_irqrestore(&lp->lock, flags);
1049 pcnet32_open(dev);
1050 } else {
1051 pcnet32_purge_rx_ring(dev);
1052 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1053 spin_unlock_irqrestore(&lp->lock, flags);
1054 }
1055 #endif
1056
1057 return (rc);
1058 } /* end pcnet32_loopback_test */
1059
1060 static void pcnet32_led_blink_callback(struct net_device *dev)
1061 {
1062 struct pcnet32_private *lp = netdev_priv(dev);
1063 struct pcnet32_access *a = &lp->a;
1064 ulong ioaddr = dev->base_addr;
1065 unsigned long flags;
1066 int i;
1067
1068 spin_lock_irqsave(&lp->lock, flags);
1069 for (i = 4; i < 8; i++) {
1070 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1071 }
1072 spin_unlock_irqrestore(&lp->lock, flags);
1073
1074 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1075 }
1076
1077 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1078 {
1079 struct pcnet32_private *lp = netdev_priv(dev);
1080 struct pcnet32_access *a = &lp->a;
1081 ulong ioaddr = dev->base_addr;
1082 unsigned long flags;
1083 int i, regs[4];
1084
1085 if (!lp->blink_timer.function) {
1086 init_timer(&lp->blink_timer);
1087 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1088 lp->blink_timer.data = (unsigned long)dev;
1089 }
1090
1091 /* Save the current value of the bcrs */
1092 spin_lock_irqsave(&lp->lock, flags);
1093 for (i = 4; i < 8; i++) {
1094 regs[i - 4] = a->read_bcr(ioaddr, i);
1095 }
1096 spin_unlock_irqrestore(&lp->lock, flags);
1097
1098 mod_timer(&lp->blink_timer, jiffies);
1099 set_current_state(TASK_INTERRUPTIBLE);
1100
1101 /* AV: the limit here makes no sense whatsoever */
1102 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1103 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1104
1105 msleep_interruptible(data * 1000);
1106 del_timer_sync(&lp->blink_timer);
1107
1108 /* Restore the original value of the bcrs */
1109 spin_lock_irqsave(&lp->lock, flags);
1110 for (i = 4; i < 8; i++) {
1111 a->write_bcr(ioaddr, i, regs[i - 4]);
1112 }
1113 spin_unlock_irqrestore(&lp->lock, flags);
1114
1115 return 0;
1116 }
1117
1118 /*
1119 * lp->lock must be held.
1120 */
1121 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1122 int can_sleep)
1123 {
1124 int csr5;
1125 struct pcnet32_private *lp = netdev_priv(dev);
1126 struct pcnet32_access *a = &lp->a;
1127 ulong ioaddr = dev->base_addr;
1128 int ticks;
1129
1130 /* really old chips have to be stopped. */
1131 if (lp->chip_version < PCNET32_79C970A)
1132 return 0;
1133
1134 /* set SUSPEND (SPND) - CSR5 bit 0 */
1135 csr5 = a->read_csr(ioaddr, CSR5);
1136 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1137
1138 /* poll waiting for bit to be set */
1139 ticks = 0;
1140 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1141 spin_unlock_irqrestore(&lp->lock, *flags);
1142 if (can_sleep)
1143 msleep(1);
1144 else
1145 mdelay(1);
1146 spin_lock_irqsave(&lp->lock, *flags);
1147 ticks++;
1148 if (ticks > 200) {
1149 if (netif_msg_hw(lp))
1150 printk(KERN_DEBUG
1151 "%s: Error getting into suspend!\n",
1152 dev->name);
1153 return 0;
1154 }
1155 }
1156 return 1;
1157 }
1158
1159 /*
1160 * process one receive descriptor entry
1161 */
1162
1163 static void pcnet32_rx_entry(struct net_device *dev,
1164 struct pcnet32_private *lp,
1165 struct pcnet32_rx_head *rxp,
1166 int entry)
1167 {
1168 int status = (short)le16_to_cpu(rxp->status) >> 8;
1169 int rx_in_place = 0;
1170 struct sk_buff *skb;
1171 short pkt_len;
1172
1173 if (status != 0x03) { /* There was an error. */
1174 /*
1175 * There is a tricky error noted by John Murphy,
1176 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1177 * buffers it's possible for a jabber packet to use two
1178 * buffers, with only the last correctly noting the error.
1179 */
1180 if (status & 0x01) /* Only count a general error at the */
1181 lp->stats.rx_errors++; /* end of a packet. */
1182 if (status & 0x20)
1183 lp->stats.rx_frame_errors++;
1184 if (status & 0x10)
1185 lp->stats.rx_over_errors++;
1186 if (status & 0x08)
1187 lp->stats.rx_crc_errors++;
1188 if (status & 0x04)
1189 lp->stats.rx_fifo_errors++;
1190 return;
1191 }
1192
1193 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1194
1195 /* Discard oversize frames. */
1196 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1197 if (netif_msg_drv(lp))
1198 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1199 dev->name, pkt_len);
1200 lp->stats.rx_errors++;
1201 return;
1202 }
1203 if (pkt_len < 60) {
1204 if (netif_msg_rx_err(lp))
1205 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1206 lp->stats.rx_errors++;
1207 return;
1208 }
1209
1210 if (pkt_len > rx_copybreak) {
1211 struct sk_buff *newskb;
1212
1213 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1214 skb_reserve(newskb, 2);
1215 skb = lp->rx_skbuff[entry];
1216 pci_unmap_single(lp->pci_dev,
1217 lp->rx_dma_addr[entry],
1218 PKT_BUF_SZ - 2,
1219 PCI_DMA_FROMDEVICE);
1220 skb_put(skb, pkt_len);
1221 lp->rx_skbuff[entry] = newskb;
1222 lp->rx_dma_addr[entry] =
1223 pci_map_single(lp->pci_dev,
1224 newskb->data,
1225 PKT_BUF_SZ - 2,
1226 PCI_DMA_FROMDEVICE);
1227 rxp->base = cpu_to_le32(lp->rx_dma_addr[entry]);
1228 rx_in_place = 1;
1229 } else
1230 skb = NULL;
1231 } else {
1232 skb = dev_alloc_skb(pkt_len + 2);
1233 }
1234
1235 if (skb == NULL) {
1236 if (netif_msg_drv(lp))
1237 printk(KERN_ERR
1238 "%s: Memory squeeze, dropping packet.\n",
1239 dev->name);
1240 lp->stats.rx_dropped++;
1241 return;
1242 }
1243 skb->dev = dev;
1244 if (!rx_in_place) {
1245 skb_reserve(skb, 2); /* 16 byte align */
1246 skb_put(skb, pkt_len); /* Make room */
1247 pci_dma_sync_single_for_cpu(lp->pci_dev,
1248 lp->rx_dma_addr[entry],
1249 pkt_len,
1250 PCI_DMA_FROMDEVICE);
1251 skb_copy_to_linear_data(skb,
1252 (unsigned char *)(lp->rx_skbuff[entry]->data),
1253 pkt_len);
1254 pci_dma_sync_single_for_device(lp->pci_dev,
1255 lp->rx_dma_addr[entry],
1256 pkt_len,
1257 PCI_DMA_FROMDEVICE);
1258 }
1259 lp->stats.rx_bytes += skb->len;
1260 skb->protocol = eth_type_trans(skb, dev);
1261 #ifdef CONFIG_PCNET32_NAPI
1262 netif_receive_skb(skb);
1263 #else
1264 netif_rx(skb);
1265 #endif
1266 dev->last_rx = jiffies;
1267 lp->stats.rx_packets++;
1268 return;
1269 }
1270
1271 static int pcnet32_rx(struct net_device *dev, int budget)
1272 {
1273 struct pcnet32_private *lp = netdev_priv(dev);
1274 int entry = lp->cur_rx & lp->rx_mod_mask;
1275 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1276 int npackets = 0;
1277
1278 /* If we own the next entry, it's a new packet. Send it up. */
1279 while (npackets < budget && (short)le16_to_cpu(rxp->status) >= 0) {
1280 pcnet32_rx_entry(dev, lp, rxp, entry);
1281 npackets += 1;
1282 /*
1283 * The docs say that the buffer length isn't touched, but Andrew
1284 * Boyd of QNX reports that some revs of the 79C965 clear it.
1285 */
1286 rxp->buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
1287 wmb(); /* Make sure owner changes after others are visible */
1288 rxp->status = cpu_to_le16(0x8000);
1289 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1290 rxp = &lp->rx_ring[entry];
1291 }
1292
1293 return npackets;
1294 }
1295
1296 static int pcnet32_tx(struct net_device *dev)
1297 {
1298 struct pcnet32_private *lp = netdev_priv(dev);
1299 unsigned int dirty_tx = lp->dirty_tx;
1300 int delta;
1301 int must_restart = 0;
1302
1303 while (dirty_tx != lp->cur_tx) {
1304 int entry = dirty_tx & lp->tx_mod_mask;
1305 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1306
1307 if (status < 0)
1308 break; /* It still hasn't been Txed */
1309
1310 lp->tx_ring[entry].base = 0;
1311
1312 if (status & 0x4000) {
1313 /* There was a major error, log it. */
1314 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1315 lp->stats.tx_errors++;
1316 if (netif_msg_tx_err(lp))
1317 printk(KERN_ERR
1318 "%s: Tx error status=%04x err_status=%08x\n",
1319 dev->name, status,
1320 err_status);
1321 if (err_status & 0x04000000)
1322 lp->stats.tx_aborted_errors++;
1323 if (err_status & 0x08000000)
1324 lp->stats.tx_carrier_errors++;
1325 if (err_status & 0x10000000)
1326 lp->stats.tx_window_errors++;
1327 #ifndef DO_DXSUFLO
1328 if (err_status & 0x40000000) {
1329 lp->stats.tx_fifo_errors++;
1330 /* Ackk! On FIFO errors the Tx unit is turned off! */
1331 /* Remove this verbosity later! */
1332 if (netif_msg_tx_err(lp))
1333 printk(KERN_ERR
1334 "%s: Tx FIFO error!\n",
1335 dev->name);
1336 must_restart = 1;
1337 }
1338 #else
1339 if (err_status & 0x40000000) {
1340 lp->stats.tx_fifo_errors++;
1341 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1342 /* Ackk! On FIFO errors the Tx unit is turned off! */
1343 /* Remove this verbosity later! */
1344 if (netif_msg_tx_err(lp))
1345 printk(KERN_ERR
1346 "%s: Tx FIFO error!\n",
1347 dev->name);
1348 must_restart = 1;
1349 }
1350 }
1351 #endif
1352 } else {
1353 if (status & 0x1800)
1354 lp->stats.collisions++;
1355 lp->stats.tx_packets++;
1356 }
1357
1358 /* We must free the original skb */
1359 if (lp->tx_skbuff[entry]) {
1360 pci_unmap_single(lp->pci_dev,
1361 lp->tx_dma_addr[entry],
1362 lp->tx_skbuff[entry]->
1363 len, PCI_DMA_TODEVICE);
1364 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1365 lp->tx_skbuff[entry] = NULL;
1366 lp->tx_dma_addr[entry] = 0;
1367 }
1368 dirty_tx++;
1369 }
1370
1371 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1372 if (delta > lp->tx_ring_size) {
1373 if (netif_msg_drv(lp))
1374 printk(KERN_ERR
1375 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1376 dev->name, dirty_tx, lp->cur_tx,
1377 lp->tx_full);
1378 dirty_tx += lp->tx_ring_size;
1379 delta -= lp->tx_ring_size;
1380 }
1381
1382 if (lp->tx_full &&
1383 netif_queue_stopped(dev) &&
1384 delta < lp->tx_ring_size - 2) {
1385 /* The ring is no longer full, clear tbusy. */
1386 lp->tx_full = 0;
1387 netif_wake_queue(dev);
1388 }
1389 lp->dirty_tx = dirty_tx;
1390
1391 return must_restart;
1392 }
1393
1394 #ifdef CONFIG_PCNET32_NAPI
1395 static int pcnet32_poll(struct napi_struct *napi, int budget)
1396 {
1397 struct pcnet32_private *lp = container_of(napi, struct pcnet32_private, napi);
1398 struct net_device *dev = lp->dev;
1399 unsigned long ioaddr = dev->base_addr;
1400 unsigned long flags;
1401 int work_done;
1402 u16 val;
1403
1404 work_done = pcnet32_rx(dev, budget);
1405
1406 spin_lock_irqsave(&lp->lock, flags);
1407 if (pcnet32_tx(dev)) {
1408 /* reset the chip to clear the error condition, then restart */
1409 lp->a.reset(ioaddr);
1410 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1411 pcnet32_restart(dev, CSR0_START);
1412 netif_wake_queue(dev);
1413 }
1414 spin_unlock_irqrestore(&lp->lock, flags);
1415
1416 if (work_done < budget) {
1417 spin_lock_irqsave(&lp->lock, flags);
1418
1419 __netif_rx_complete(dev, napi);
1420
1421 /* clear interrupt masks */
1422 val = lp->a.read_csr(ioaddr, CSR3);
1423 val &= 0x00ff;
1424 lp->a.write_csr(ioaddr, CSR3, val);
1425
1426 /* Set interrupt enable. */
1427 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1428 mmiowb();
1429 spin_unlock_irqrestore(&lp->lock, flags);
1430 }
1431 return work_done;
1432 }
1433 #endif
1434
1435 #define PCNET32_REGS_PER_PHY 32
1436 #define PCNET32_MAX_PHYS 32
1437 static int pcnet32_get_regs_len(struct net_device *dev)
1438 {
1439 struct pcnet32_private *lp = netdev_priv(dev);
1440 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1441
1442 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1443 }
1444
1445 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1446 void *ptr)
1447 {
1448 int i, csr0;
1449 u16 *buff = ptr;
1450 struct pcnet32_private *lp = netdev_priv(dev);
1451 struct pcnet32_access *a = &lp->a;
1452 ulong ioaddr = dev->base_addr;
1453 unsigned long flags;
1454
1455 spin_lock_irqsave(&lp->lock, flags);
1456
1457 csr0 = a->read_csr(ioaddr, CSR0);
1458 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1459 pcnet32_suspend(dev, &flags, 1);
1460
1461 /* read address PROM */
1462 for (i = 0; i < 16; i += 2)
1463 *buff++ = inw(ioaddr + i);
1464
1465 /* read control and status registers */
1466 for (i = 0; i < 90; i++) {
1467 *buff++ = a->read_csr(ioaddr, i);
1468 }
1469
1470 *buff++ = a->read_csr(ioaddr, 112);
1471 *buff++ = a->read_csr(ioaddr, 114);
1472
1473 /* read bus configuration registers */
1474 for (i = 0; i < 30; i++) {
1475 *buff++ = a->read_bcr(ioaddr, i);
1476 }
1477 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1478 for (i = 31; i < 36; i++) {
1479 *buff++ = a->read_bcr(ioaddr, i);
1480 }
1481
1482 /* read mii phy registers */
1483 if (lp->mii) {
1484 int j;
1485 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1486 if (lp->phymask & (1 << j)) {
1487 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1488 lp->a.write_bcr(ioaddr, 33,
1489 (j << 5) | i);
1490 *buff++ = lp->a.read_bcr(ioaddr, 34);
1491 }
1492 }
1493 }
1494 }
1495
1496 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1497 int csr5;
1498
1499 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1500 csr5 = a->read_csr(ioaddr, CSR5);
1501 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1502 }
1503
1504 spin_unlock_irqrestore(&lp->lock, flags);
1505 }
1506
1507 static const struct ethtool_ops pcnet32_ethtool_ops = {
1508 .get_settings = pcnet32_get_settings,
1509 .set_settings = pcnet32_set_settings,
1510 .get_drvinfo = pcnet32_get_drvinfo,
1511 .get_msglevel = pcnet32_get_msglevel,
1512 .set_msglevel = pcnet32_set_msglevel,
1513 .nway_reset = pcnet32_nway_reset,
1514 .get_link = pcnet32_get_link,
1515 .get_ringparam = pcnet32_get_ringparam,
1516 .set_ringparam = pcnet32_set_ringparam,
1517 .get_strings = pcnet32_get_strings,
1518 .self_test = pcnet32_ethtool_test,
1519 .phys_id = pcnet32_phys_id,
1520 .get_regs_len = pcnet32_get_regs_len,
1521 .get_regs = pcnet32_get_regs,
1522 .get_sset_count = pcnet32_get_sset_count,
1523 };
1524
1525 /* only probes for non-PCI devices, the rest are handled by
1526 * pci_register_driver via pcnet32_probe_pci */
1527
1528 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1529 {
1530 unsigned int *port, ioaddr;
1531
1532 /* search for PCnet32 VLB cards at known addresses */
1533 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1534 if (request_region
1535 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1536 /* check if there is really a pcnet chip on that ioaddr */
1537 if ((inb(ioaddr + 14) == 0x57)
1538 && (inb(ioaddr + 15) == 0x57)) {
1539 pcnet32_probe1(ioaddr, 0, NULL);
1540 } else {
1541 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1542 }
1543 }
1544 }
1545 }
1546
1547 static int __devinit
1548 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1549 {
1550 unsigned long ioaddr;
1551 int err;
1552
1553 err = pci_enable_device(pdev);
1554 if (err < 0) {
1555 if (pcnet32_debug & NETIF_MSG_PROBE)
1556 printk(KERN_ERR PFX
1557 "failed to enable device -- err=%d\n", err);
1558 return err;
1559 }
1560 pci_set_master(pdev);
1561
1562 ioaddr = pci_resource_start(pdev, 0);
1563 if (!ioaddr) {
1564 if (pcnet32_debug & NETIF_MSG_PROBE)
1565 printk(KERN_ERR PFX
1566 "card has no PCI IO resources, aborting\n");
1567 return -ENODEV;
1568 }
1569
1570 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1571 if (pcnet32_debug & NETIF_MSG_PROBE)
1572 printk(KERN_ERR PFX
1573 "architecture does not support 32bit PCI busmaster DMA\n");
1574 return -ENODEV;
1575 }
1576 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1577 NULL) {
1578 if (pcnet32_debug & NETIF_MSG_PROBE)
1579 printk(KERN_ERR PFX
1580 "io address range already allocated\n");
1581 return -EBUSY;
1582 }
1583
1584 err = pcnet32_probe1(ioaddr, 1, pdev);
1585 if (err < 0) {
1586 pci_disable_device(pdev);
1587 }
1588 return err;
1589 }
1590
1591 /* pcnet32_probe1
1592 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1593 * pdev will be NULL when called from pcnet32_probe_vlbus.
1594 */
1595 static int __devinit
1596 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1597 {
1598 struct pcnet32_private *lp;
1599 int i, media;
1600 int fdx, mii, fset, dxsuflo;
1601 int chip_version;
1602 char *chipname;
1603 struct net_device *dev;
1604 struct pcnet32_access *a = NULL;
1605 u8 promaddr[6];
1606 int ret = -ENODEV;
1607
1608 /* reset the chip */
1609 pcnet32_wio_reset(ioaddr);
1610
1611 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1612 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1613 a = &pcnet32_wio;
1614 } else {
1615 pcnet32_dwio_reset(ioaddr);
1616 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1617 && pcnet32_dwio_check(ioaddr)) {
1618 a = &pcnet32_dwio;
1619 } else
1620 goto err_release_region;
1621 }
1622
1623 chip_version =
1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1626 printk(KERN_INFO " PCnet chip version is %#x.\n",
1627 chip_version);
1628 if ((chip_version & 0xfff) != 0x003) {
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 printk(KERN_INFO PFX "Unsupported chip version.\n");
1631 goto err_release_region;
1632 }
1633
1634 /* initialize variables */
1635 fdx = mii = fset = dxsuflo = 0;
1636 chip_version = (chip_version >> 12) & 0xffff;
1637
1638 switch (chip_version) {
1639 case 0x2420:
1640 chipname = "PCnet/PCI 79C970"; /* PCI */
1641 break;
1642 case 0x2430:
1643 if (shared)
1644 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1645 else
1646 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1647 break;
1648 case 0x2621:
1649 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1650 fdx = 1;
1651 break;
1652 case 0x2623:
1653 chipname = "PCnet/FAST 79C971"; /* PCI */
1654 fdx = 1;
1655 mii = 1;
1656 fset = 1;
1657 break;
1658 case 0x2624:
1659 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1660 fdx = 1;
1661 mii = 1;
1662 fset = 1;
1663 break;
1664 case 0x2625:
1665 chipname = "PCnet/FAST III 79C973"; /* PCI */
1666 fdx = 1;
1667 mii = 1;
1668 break;
1669 case 0x2626:
1670 chipname = "PCnet/Home 79C978"; /* PCI */
1671 fdx = 1;
1672 /*
1673 * This is based on specs published at www.amd.com. This section
1674 * assumes that a card with a 79C978 wants to go into standard
1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1676 * and the module option homepna=1 can select this instead.
1677 */
1678 media = a->read_bcr(ioaddr, 49);
1679 media &= ~3; /* default to 10Mb ethernet */
1680 if (cards_found < MAX_UNITS && homepna[cards_found])
1681 media |= 1; /* switch to home wiring mode */
1682 if (pcnet32_debug & NETIF_MSG_PROBE)
1683 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1684 (media & 1) ? "1" : "10");
1685 a->write_bcr(ioaddr, 49, media);
1686 break;
1687 case 0x2627:
1688 chipname = "PCnet/FAST III 79C975"; /* PCI */
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 case 0x2628:
1693 chipname = "PCnet/PRO 79C976";
1694 fdx = 1;
1695 mii = 1;
1696 break;
1697 default:
1698 if (pcnet32_debug & NETIF_MSG_PROBE)
1699 printk(KERN_INFO PFX
1700 "PCnet version %#x, no PCnet32 chip.\n",
1701 chip_version);
1702 goto err_release_region;
1703 }
1704
1705 /*
1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1707 * starting until the packet is loaded. Strike one for reliability, lose
1708 * one for latency - although on PCI this isnt a big loss. Older chips
1709 * have FIFO's smaller than a packet, so you can't do this.
1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1711 */
1712
1713 if (fset) {
1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1715 a->write_csr(ioaddr, 80,
1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1717 dxsuflo = 1;
1718 }
1719
1720 dev = alloc_etherdev(sizeof(*lp));
1721 if (!dev) {
1722 if (pcnet32_debug & NETIF_MSG_PROBE)
1723 printk(KERN_ERR PFX "Memory allocation failed.\n");
1724 ret = -ENOMEM;
1725 goto err_release_region;
1726 }
1727 SET_NETDEV_DEV(dev, &pdev->dev);
1728
1729 if (pcnet32_debug & NETIF_MSG_PROBE)
1730 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1731
1732 /* In most chips, after a chip reset, the ethernet address is read from the
1733 * station address PROM at the base address and programmed into the
1734 * "Physical Address Registers" CSR12-14.
1735 * As a precautionary measure, we read the PROM values and complain if
1736 * they disagree with the CSRs. If they miscompare, and the PROM addr
1737 * is valid, then the PROM addr is used.
1738 */
1739 for (i = 0; i < 3; i++) {
1740 unsigned int val;
1741 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1742 /* There may be endianness issues here. */
1743 dev->dev_addr[2 * i] = val & 0x0ff;
1744 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1745 }
1746
1747 /* read PROM address and compare with CSR address */
1748 for (i = 0; i < 6; i++)
1749 promaddr[i] = inb(ioaddr + i);
1750
1751 if (memcmp(promaddr, dev->dev_addr, 6)
1752 || !is_valid_ether_addr(dev->dev_addr)) {
1753 if (is_valid_ether_addr(promaddr)) {
1754 if (pcnet32_debug & NETIF_MSG_PROBE) {
1755 printk(" warning: CSR address invalid,\n");
1756 printk(KERN_INFO
1757 " using instead PROM address of");
1758 }
1759 memcpy(dev->dev_addr, promaddr, 6);
1760 }
1761 }
1762 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1763
1764 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1765 if (!is_valid_ether_addr(dev->perm_addr))
1766 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1767
1768 if (pcnet32_debug & NETIF_MSG_PROBE) {
1769 for (i = 0; i < 6; i++)
1770 printk(" %2.2x", dev->dev_addr[i]);
1771
1772 /* Version 0x2623 and 0x2624 */
1773 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1774 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1775 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1776 switch (i >> 10) {
1777 case 0:
1778 printk(" 20 bytes,");
1779 break;
1780 case 1:
1781 printk(" 64 bytes,");
1782 break;
1783 case 2:
1784 printk(" 128 bytes,");
1785 break;
1786 case 3:
1787 printk("~220 bytes,");
1788 break;
1789 }
1790 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1791 printk(" BCR18(%x):", i & 0xffff);
1792 if (i & (1 << 5))
1793 printk("BurstWrEn ");
1794 if (i & (1 << 6))
1795 printk("BurstRdEn ");
1796 if (i & (1 << 7))
1797 printk("DWordIO ");
1798 if (i & (1 << 11))
1799 printk("NoUFlow ");
1800 i = a->read_bcr(ioaddr, 25);
1801 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1802 i = a->read_bcr(ioaddr, 26);
1803 printk(" SRAM_BND=0x%04x,", i << 8);
1804 i = a->read_bcr(ioaddr, 27);
1805 if (i & (1 << 14))
1806 printk("LowLatRx");
1807 }
1808 }
1809
1810 dev->base_addr = ioaddr;
1811 lp = netdev_priv(dev);
1812 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1813 if ((lp->init_block =
1814 pci_alloc_consistent(pdev, sizeof(*lp->init_block), &lp->init_dma_addr)) == NULL) {
1815 if (pcnet32_debug & NETIF_MSG_PROBE)
1816 printk(KERN_ERR PFX
1817 "Consistent memory allocation failed.\n");
1818 ret = -ENOMEM;
1819 goto err_free_netdev;
1820 }
1821 lp->pci_dev = pdev;
1822
1823 lp->dev = dev;
1824
1825 spin_lock_init(&lp->lock);
1826
1827 SET_NETDEV_DEV(dev, &pdev->dev);
1828 lp->name = chipname;
1829 lp->shared_irq = shared;
1830 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1831 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1832 lp->tx_mod_mask = lp->tx_ring_size - 1;
1833 lp->rx_mod_mask = lp->rx_ring_size - 1;
1834 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1835 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1836 lp->mii_if.full_duplex = fdx;
1837 lp->mii_if.phy_id_mask = 0x1f;
1838 lp->mii_if.reg_num_mask = 0x1f;
1839 lp->dxsuflo = dxsuflo;
1840 lp->mii = mii;
1841 lp->chip_version = chip_version;
1842 lp->msg_enable = pcnet32_debug;
1843 if ((cards_found >= MAX_UNITS)
1844 || (options[cards_found] > sizeof(options_mapping)))
1845 lp->options = PCNET32_PORT_ASEL;
1846 else
1847 lp->options = options_mapping[options[cards_found]];
1848 lp->mii_if.dev = dev;
1849 lp->mii_if.mdio_read = mdio_read;
1850 lp->mii_if.mdio_write = mdio_write;
1851
1852 /* napi.weight is used in both the napi and non-napi cases */
1853 lp->napi.weight = lp->rx_ring_size / 2;
1854
1855 #ifdef CONFIG_PCNET32_NAPI
1856 netif_napi_add(dev, &lp->napi, pcnet32_poll, lp->rx_ring_size / 2);
1857 #endif
1858
1859 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1860 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1861 lp->options |= PCNET32_PORT_FD;
1862
1863 if (!a) {
1864 if (pcnet32_debug & NETIF_MSG_PROBE)
1865 printk(KERN_ERR PFX "No access methods\n");
1866 ret = -ENODEV;
1867 goto err_free_consistent;
1868 }
1869 lp->a = *a;
1870
1871 /* prior to register_netdev, dev->name is not yet correct */
1872 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1873 ret = -ENOMEM;
1874 goto err_free_ring;
1875 }
1876 /* detect special T1/E1 WAN card by checking for MAC address */
1877 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1878 && dev->dev_addr[2] == 0x75)
1879 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1880
1881 lp->init_block->mode = cpu_to_le16(0x0003); /* Disable Rx and Tx. */
1882 lp->init_block->tlen_rlen =
1883 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
1884 for (i = 0; i < 6; i++)
1885 lp->init_block->phys_addr[i] = dev->dev_addr[i];
1886 lp->init_block->filter[0] = 0x00000000;
1887 lp->init_block->filter[1] = 0x00000000;
1888 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
1889 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
1890
1891 /* switch pcnet32 to 32bit mode */
1892 a->write_bcr(ioaddr, 20, 2);
1893
1894 a->write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
1895 a->write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
1896
1897 if (pdev) { /* use the IRQ provided by PCI */
1898 dev->irq = pdev->irq;
1899 if (pcnet32_debug & NETIF_MSG_PROBE)
1900 printk(" assigned IRQ %d.\n", dev->irq);
1901 } else {
1902 unsigned long irq_mask = probe_irq_on();
1903
1904 /*
1905 * To auto-IRQ we enable the initialization-done and DMA error
1906 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1907 * boards will work.
1908 */
1909 /* Trigger an initialization just for the interrupt. */
1910 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1911 mdelay(1);
1912
1913 dev->irq = probe_irq_off(irq_mask);
1914 if (!dev->irq) {
1915 if (pcnet32_debug & NETIF_MSG_PROBE)
1916 printk(", failed to detect IRQ line.\n");
1917 ret = -ENODEV;
1918 goto err_free_ring;
1919 }
1920 if (pcnet32_debug & NETIF_MSG_PROBE)
1921 printk(", probed IRQ %d.\n", dev->irq);
1922 }
1923
1924 /* Set the mii phy_id so that we can query the link state */
1925 if (lp->mii) {
1926 /* lp->phycount and lp->phymask are set to 0 by memset above */
1927
1928 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1929 /* scan for PHYs */
1930 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1931 unsigned short id1, id2;
1932
1933 id1 = mdio_read(dev, i, MII_PHYSID1);
1934 if (id1 == 0xffff)
1935 continue;
1936 id2 = mdio_read(dev, i, MII_PHYSID2);
1937 if (id2 == 0xffff)
1938 continue;
1939 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1940 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1941 lp->phycount++;
1942 lp->phymask |= (1 << i);
1943 lp->mii_if.phy_id = i;
1944 if (pcnet32_debug & NETIF_MSG_PROBE)
1945 printk(KERN_INFO PFX
1946 "Found PHY %04x:%04x at address %d.\n",
1947 id1, id2, i);
1948 }
1949 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1950 if (lp->phycount > 1) {
1951 lp->options |= PCNET32_PORT_MII;
1952 }
1953 }
1954
1955 init_timer(&lp->watchdog_timer);
1956 lp->watchdog_timer.data = (unsigned long)dev;
1957 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1958
1959 /* The PCNET32-specific entries in the device structure. */
1960 dev->open = &pcnet32_open;
1961 dev->hard_start_xmit = &pcnet32_start_xmit;
1962 dev->stop = &pcnet32_close;
1963 dev->get_stats = &pcnet32_get_stats;
1964 dev->set_multicast_list = &pcnet32_set_multicast_list;
1965 dev->do_ioctl = &pcnet32_ioctl;
1966 dev->ethtool_ops = &pcnet32_ethtool_ops;
1967 dev->tx_timeout = pcnet32_tx_timeout;
1968 dev->watchdog_timeo = (5 * HZ);
1969
1970 #ifdef CONFIG_NET_POLL_CONTROLLER
1971 dev->poll_controller = pcnet32_poll_controller;
1972 #endif
1973
1974 /* Fill in the generic fields of the device structure. */
1975 if (register_netdev(dev))
1976 goto err_free_ring;
1977
1978 if (pdev) {
1979 pci_set_drvdata(pdev, dev);
1980 } else {
1981 lp->next = pcnet32_dev;
1982 pcnet32_dev = dev;
1983 }
1984
1985 if (pcnet32_debug & NETIF_MSG_PROBE)
1986 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1987 cards_found++;
1988
1989 /* enable LED writes */
1990 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1991
1992 return 0;
1993
1994 err_free_ring:
1995 pcnet32_free_ring(dev);
1996 err_free_consistent:
1997 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
1998 lp->init_block, lp->init_dma_addr);
1999 err_free_netdev:
2000 free_netdev(dev);
2001 err_release_region:
2002 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2003 return ret;
2004 }
2005
2006 /* if any allocation fails, caller must also call pcnet32_free_ring */
2007 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2008 {
2009 struct pcnet32_private *lp = netdev_priv(dev);
2010
2011 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2012 sizeof(struct pcnet32_tx_head) *
2013 lp->tx_ring_size,
2014 &lp->tx_ring_dma_addr);
2015 if (lp->tx_ring == NULL) {
2016 if (netif_msg_drv(lp))
2017 printk("\n" KERN_ERR PFX
2018 "%s: Consistent memory allocation failed.\n",
2019 name);
2020 return -ENOMEM;
2021 }
2022
2023 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2024 sizeof(struct pcnet32_rx_head) *
2025 lp->rx_ring_size,
2026 &lp->rx_ring_dma_addr);
2027 if (lp->rx_ring == NULL) {
2028 if (netif_msg_drv(lp))
2029 printk("\n" KERN_ERR PFX
2030 "%s: Consistent memory allocation failed.\n",
2031 name);
2032 return -ENOMEM;
2033 }
2034
2035 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2036 GFP_ATOMIC);
2037 if (!lp->tx_dma_addr) {
2038 if (netif_msg_drv(lp))
2039 printk("\n" KERN_ERR PFX
2040 "%s: Memory allocation failed.\n", name);
2041 return -ENOMEM;
2042 }
2043
2044 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2045 GFP_ATOMIC);
2046 if (!lp->rx_dma_addr) {
2047 if (netif_msg_drv(lp))
2048 printk("\n" KERN_ERR PFX
2049 "%s: Memory allocation failed.\n", name);
2050 return -ENOMEM;
2051 }
2052
2053 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2054 GFP_ATOMIC);
2055 if (!lp->tx_skbuff) {
2056 if (netif_msg_drv(lp))
2057 printk("\n" KERN_ERR PFX
2058 "%s: Memory allocation failed.\n", name);
2059 return -ENOMEM;
2060 }
2061
2062 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2063 GFP_ATOMIC);
2064 if (!lp->rx_skbuff) {
2065 if (netif_msg_drv(lp))
2066 printk("\n" KERN_ERR PFX
2067 "%s: Memory allocation failed.\n", name);
2068 return -ENOMEM;
2069 }
2070
2071 return 0;
2072 }
2073
2074 static void pcnet32_free_ring(struct net_device *dev)
2075 {
2076 struct pcnet32_private *lp = netdev_priv(dev);
2077
2078 kfree(lp->tx_skbuff);
2079 lp->tx_skbuff = NULL;
2080
2081 kfree(lp->rx_skbuff);
2082 lp->rx_skbuff = NULL;
2083
2084 kfree(lp->tx_dma_addr);
2085 lp->tx_dma_addr = NULL;
2086
2087 kfree(lp->rx_dma_addr);
2088 lp->rx_dma_addr = NULL;
2089
2090 if (lp->tx_ring) {
2091 pci_free_consistent(lp->pci_dev,
2092 sizeof(struct pcnet32_tx_head) *
2093 lp->tx_ring_size, lp->tx_ring,
2094 lp->tx_ring_dma_addr);
2095 lp->tx_ring = NULL;
2096 }
2097
2098 if (lp->rx_ring) {
2099 pci_free_consistent(lp->pci_dev,
2100 sizeof(struct pcnet32_rx_head) *
2101 lp->rx_ring_size, lp->rx_ring,
2102 lp->rx_ring_dma_addr);
2103 lp->rx_ring = NULL;
2104 }
2105 }
2106
2107 static int pcnet32_open(struct net_device *dev)
2108 {
2109 struct pcnet32_private *lp = netdev_priv(dev);
2110 unsigned long ioaddr = dev->base_addr;
2111 u16 val;
2112 int i;
2113 int rc;
2114 unsigned long flags;
2115
2116 if (request_irq(dev->irq, &pcnet32_interrupt,
2117 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2118 (void *)dev)) {
2119 return -EAGAIN;
2120 }
2121
2122 spin_lock_irqsave(&lp->lock, flags);
2123 /* Check for a valid station address */
2124 if (!is_valid_ether_addr(dev->dev_addr)) {
2125 rc = -EINVAL;
2126 goto err_free_irq;
2127 }
2128
2129 /* Reset the PCNET32 */
2130 lp->a.reset(ioaddr);
2131
2132 /* switch pcnet32 to 32bit mode */
2133 lp->a.write_bcr(ioaddr, 20, 2);
2134
2135 if (netif_msg_ifup(lp))
2136 printk(KERN_DEBUG
2137 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2138 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2139 (u32) (lp->rx_ring_dma_addr),
2140 (u32) (lp->init_dma_addr));
2141
2142 /* set/reset autoselect bit */
2143 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2144 if (lp->options & PCNET32_PORT_ASEL)
2145 val |= 2;
2146 lp->a.write_bcr(ioaddr, 2, val);
2147
2148 /* handle full duplex setting */
2149 if (lp->mii_if.full_duplex) {
2150 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2151 if (lp->options & PCNET32_PORT_FD) {
2152 val |= 1;
2153 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2154 val |= 2;
2155 } else if (lp->options & PCNET32_PORT_ASEL) {
2156 /* workaround of xSeries250, turn on for 79C975 only */
2157 if (lp->chip_version == 0x2627)
2158 val |= 3;
2159 }
2160 lp->a.write_bcr(ioaddr, 9, val);
2161 }
2162
2163 /* set/reset GPSI bit in test register */
2164 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2165 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2166 val |= 0x10;
2167 lp->a.write_csr(ioaddr, 124, val);
2168
2169 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2170 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2171 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2172 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2173 if (lp->options & PCNET32_PORT_ASEL) {
2174 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2175 if (netif_msg_link(lp))
2176 printk(KERN_DEBUG
2177 "%s: Setting 100Mb-Full Duplex.\n",
2178 dev->name);
2179 }
2180 }
2181 if (lp->phycount < 2) {
2182 /*
2183 * 24 Jun 2004 according AMD, in order to change the PHY,
2184 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2185 * duplex, and/or enable auto negotiation, and clear DANAS
2186 */
2187 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2188 lp->a.write_bcr(ioaddr, 32,
2189 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2190 /* disable Auto Negotiation, set 10Mpbs, HD */
2191 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2192 if (lp->options & PCNET32_PORT_FD)
2193 val |= 0x10;
2194 if (lp->options & PCNET32_PORT_100)
2195 val |= 0x08;
2196 lp->a.write_bcr(ioaddr, 32, val);
2197 } else {
2198 if (lp->options & PCNET32_PORT_ASEL) {
2199 lp->a.write_bcr(ioaddr, 32,
2200 lp->a.read_bcr(ioaddr,
2201 32) | 0x0080);
2202 /* enable auto negotiate, setup, disable fd */
2203 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2204 val |= 0x20;
2205 lp->a.write_bcr(ioaddr, 32, val);
2206 }
2207 }
2208 } else {
2209 int first_phy = -1;
2210 u16 bmcr;
2211 u32 bcr9;
2212 struct ethtool_cmd ecmd;
2213
2214 /*
2215 * There is really no good other way to handle multiple PHYs
2216 * other than turning off all automatics
2217 */
2218 val = lp->a.read_bcr(ioaddr, 2);
2219 lp->a.write_bcr(ioaddr, 2, val & ~2);
2220 val = lp->a.read_bcr(ioaddr, 32);
2221 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2222
2223 if (!(lp->options & PCNET32_PORT_ASEL)) {
2224 /* setup ecmd */
2225 ecmd.port = PORT_MII;
2226 ecmd.transceiver = XCVR_INTERNAL;
2227 ecmd.autoneg = AUTONEG_DISABLE;
2228 ecmd.speed =
2229 lp->
2230 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2231 bcr9 = lp->a.read_bcr(ioaddr, 9);
2232
2233 if (lp->options & PCNET32_PORT_FD) {
2234 ecmd.duplex = DUPLEX_FULL;
2235 bcr9 |= (1 << 0);
2236 } else {
2237 ecmd.duplex = DUPLEX_HALF;
2238 bcr9 |= ~(1 << 0);
2239 }
2240 lp->a.write_bcr(ioaddr, 9, bcr9);
2241 }
2242
2243 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2244 if (lp->phymask & (1 << i)) {
2245 /* isolate all but the first PHY */
2246 bmcr = mdio_read(dev, i, MII_BMCR);
2247 if (first_phy == -1) {
2248 first_phy = i;
2249 mdio_write(dev, i, MII_BMCR,
2250 bmcr & ~BMCR_ISOLATE);
2251 } else {
2252 mdio_write(dev, i, MII_BMCR,
2253 bmcr | BMCR_ISOLATE);
2254 }
2255 /* use mii_ethtool_sset to setup PHY */
2256 lp->mii_if.phy_id = i;
2257 ecmd.phy_address = i;
2258 if (lp->options & PCNET32_PORT_ASEL) {
2259 mii_ethtool_gset(&lp->mii_if, &ecmd);
2260 ecmd.autoneg = AUTONEG_ENABLE;
2261 }
2262 mii_ethtool_sset(&lp->mii_if, &ecmd);
2263 }
2264 }
2265 lp->mii_if.phy_id = first_phy;
2266 if (netif_msg_link(lp))
2267 printk(KERN_INFO "%s: Using PHY number %d.\n",
2268 dev->name, first_phy);
2269 }
2270
2271 #ifdef DO_DXSUFLO
2272 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2273 val = lp->a.read_csr(ioaddr, CSR3);
2274 val |= 0x40;
2275 lp->a.write_csr(ioaddr, CSR3, val);
2276 }
2277 #endif
2278
2279 lp->init_block->mode =
2280 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2281 pcnet32_load_multicast(dev);
2282
2283 if (pcnet32_init_ring(dev)) {
2284 rc = -ENOMEM;
2285 goto err_free_ring;
2286 }
2287
2288 #ifdef CONFIG_PCNET32_NAPI
2289 napi_enable(&lp->napi);
2290 #endif
2291
2292 /* Re-initialize the PCNET32, and start it when done. */
2293 lp->a.write_csr(ioaddr, 1, (lp->init_dma_addr & 0xffff));
2294 lp->a.write_csr(ioaddr, 2, (lp->init_dma_addr >> 16));
2295
2296 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2297 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2298
2299 netif_start_queue(dev);
2300
2301 if (lp->chip_version >= PCNET32_79C970A) {
2302 /* Print the link status and start the watchdog */
2303 pcnet32_check_media(dev, 1);
2304 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2305 }
2306
2307 i = 0;
2308 while (i++ < 100)
2309 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2310 break;
2311 /*
2312 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2313 * reports that doing so triggers a bug in the '974.
2314 */
2315 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2316
2317 if (netif_msg_ifup(lp))
2318 printk(KERN_DEBUG
2319 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2320 dev->name, i,
2321 (u32) (lp->init_dma_addr),
2322 lp->a.read_csr(ioaddr, CSR0));
2323
2324 spin_unlock_irqrestore(&lp->lock, flags);
2325
2326 return 0; /* Always succeed */
2327
2328 err_free_ring:
2329 /* free any allocated skbuffs */
2330 pcnet32_purge_rx_ring(dev);
2331
2332 /*
2333 * Switch back to 16bit mode to avoid problems with dumb
2334 * DOS packet driver after a warm reboot
2335 */
2336 lp->a.write_bcr(ioaddr, 20, 4);
2337
2338 err_free_irq:
2339 spin_unlock_irqrestore(&lp->lock, flags);
2340 free_irq(dev->irq, dev);
2341 return rc;
2342 }
2343
2344 /*
2345 * The LANCE has been halted for one reason or another (busmaster memory
2346 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2347 * etc.). Modern LANCE variants always reload their ring-buffer
2348 * configuration when restarted, so we must reinitialize our ring
2349 * context before restarting. As part of this reinitialization,
2350 * find all packets still on the Tx ring and pretend that they had been
2351 * sent (in effect, drop the packets on the floor) - the higher-level
2352 * protocols will time out and retransmit. It'd be better to shuffle
2353 * these skbs to a temp list and then actually re-Tx them after
2354 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2355 */
2356
2357 static void pcnet32_purge_tx_ring(struct net_device *dev)
2358 {
2359 struct pcnet32_private *lp = netdev_priv(dev);
2360 int i;
2361
2362 for (i = 0; i < lp->tx_ring_size; i++) {
2363 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2364 wmb(); /* Make sure adapter sees owner change */
2365 if (lp->tx_skbuff[i]) {
2366 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2367 lp->tx_skbuff[i]->len,
2368 PCI_DMA_TODEVICE);
2369 dev_kfree_skb_any(lp->tx_skbuff[i]);
2370 }
2371 lp->tx_skbuff[i] = NULL;
2372 lp->tx_dma_addr[i] = 0;
2373 }
2374 }
2375
2376 /* Initialize the PCNET32 Rx and Tx rings. */
2377 static int pcnet32_init_ring(struct net_device *dev)
2378 {
2379 struct pcnet32_private *lp = netdev_priv(dev);
2380 int i;
2381
2382 lp->tx_full = 0;
2383 lp->cur_rx = lp->cur_tx = 0;
2384 lp->dirty_rx = lp->dirty_tx = 0;
2385
2386 for (i = 0; i < lp->rx_ring_size; i++) {
2387 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2388 if (rx_skbuff == NULL) {
2389 if (!
2390 (rx_skbuff = lp->rx_skbuff[i] =
2391 dev_alloc_skb(PKT_BUF_SZ))) {
2392 /* there is not much, we can do at this point */
2393 if (netif_msg_drv(lp))
2394 printk(KERN_ERR
2395 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2396 dev->name);
2397 return -1;
2398 }
2399 skb_reserve(rx_skbuff, 2);
2400 }
2401
2402 rmb();
2403 if (lp->rx_dma_addr[i] == 0)
2404 lp->rx_dma_addr[i] =
2405 pci_map_single(lp->pci_dev, rx_skbuff->data,
2406 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2407 lp->rx_ring[i].base = cpu_to_le32(lp->rx_dma_addr[i]);
2408 lp->rx_ring[i].buf_length = cpu_to_le16(2 - PKT_BUF_SZ);
2409 wmb(); /* Make sure owner changes after all others are visible */
2410 lp->rx_ring[i].status = cpu_to_le16(0x8000);
2411 }
2412 /* The Tx buffer address is filled in as needed, but we do need to clear
2413 * the upper ownership bit. */
2414 for (i = 0; i < lp->tx_ring_size; i++) {
2415 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2416 wmb(); /* Make sure adapter sees owner change */
2417 lp->tx_ring[i].base = 0;
2418 lp->tx_dma_addr[i] = 0;
2419 }
2420
2421 lp->init_block->tlen_rlen =
2422 cpu_to_le16(lp->tx_len_bits | lp->rx_len_bits);
2423 for (i = 0; i < 6; i++)
2424 lp->init_block->phys_addr[i] = dev->dev_addr[i];
2425 lp->init_block->rx_ring = cpu_to_le32(lp->rx_ring_dma_addr);
2426 lp->init_block->tx_ring = cpu_to_le32(lp->tx_ring_dma_addr);
2427 wmb(); /* Make sure all changes are visible */
2428 return 0;
2429 }
2430
2431 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2432 * then flush the pending transmit operations, re-initialize the ring,
2433 * and tell the chip to initialize.
2434 */
2435 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2436 {
2437 struct pcnet32_private *lp = netdev_priv(dev);
2438 unsigned long ioaddr = dev->base_addr;
2439 int i;
2440
2441 /* wait for stop */
2442 for (i = 0; i < 100; i++)
2443 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2444 break;
2445
2446 if (i >= 100 && netif_msg_drv(lp))
2447 printk(KERN_ERR
2448 "%s: pcnet32_restart timed out waiting for stop.\n",
2449 dev->name);
2450
2451 pcnet32_purge_tx_ring(dev);
2452 if (pcnet32_init_ring(dev))
2453 return;
2454
2455 /* ReInit Ring */
2456 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2457 i = 0;
2458 while (i++ < 1000)
2459 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2460 break;
2461
2462 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2463 }
2464
2465 static void pcnet32_tx_timeout(struct net_device *dev)
2466 {
2467 struct pcnet32_private *lp = netdev_priv(dev);
2468 unsigned long ioaddr = dev->base_addr, flags;
2469
2470 spin_lock_irqsave(&lp->lock, flags);
2471 /* Transmitter timeout, serious problems. */
2472 if (pcnet32_debug & NETIF_MSG_DRV)
2473 printk(KERN_ERR
2474 "%s: transmit timed out, status %4.4x, resetting.\n",
2475 dev->name, lp->a.read_csr(ioaddr, CSR0));
2476 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2477 lp->stats.tx_errors++;
2478 if (netif_msg_tx_err(lp)) {
2479 int i;
2480 printk(KERN_DEBUG
2481 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2482 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2483 lp->cur_rx);
2484 for (i = 0; i < lp->rx_ring_size; i++)
2485 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2486 le32_to_cpu(lp->rx_ring[i].base),
2487 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2488 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2489 le16_to_cpu(lp->rx_ring[i].status));
2490 for (i = 0; i < lp->tx_ring_size; i++)
2491 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2492 le32_to_cpu(lp->tx_ring[i].base),
2493 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2494 le32_to_cpu(lp->tx_ring[i].misc),
2495 le16_to_cpu(lp->tx_ring[i].status));
2496 printk("\n");
2497 }
2498 pcnet32_restart(dev, CSR0_NORMAL);
2499
2500 dev->trans_start = jiffies;
2501 netif_wake_queue(dev);
2502
2503 spin_unlock_irqrestore(&lp->lock, flags);
2504 }
2505
2506 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2507 {
2508 struct pcnet32_private *lp = netdev_priv(dev);
2509 unsigned long ioaddr = dev->base_addr;
2510 u16 status;
2511 int entry;
2512 unsigned long flags;
2513
2514 spin_lock_irqsave(&lp->lock, flags);
2515
2516 if (netif_msg_tx_queued(lp)) {
2517 printk(KERN_DEBUG
2518 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2519 dev->name, lp->a.read_csr(ioaddr, CSR0));
2520 }
2521
2522 /* Default status -- will not enable Successful-TxDone
2523 * interrupt when that option is available to us.
2524 */
2525 status = 0x8300;
2526
2527 /* Fill in a Tx ring entry */
2528
2529 /* Mask to ring buffer boundary. */
2530 entry = lp->cur_tx & lp->tx_mod_mask;
2531
2532 /* Caution: the write order is important here, set the status
2533 * with the "ownership" bits last. */
2534
2535 lp->tx_ring[entry].length = cpu_to_le16(-skb->len);
2536
2537 lp->tx_ring[entry].misc = 0x00000000;
2538
2539 lp->tx_skbuff[entry] = skb;
2540 lp->tx_dma_addr[entry] =
2541 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2542 lp->tx_ring[entry].base = cpu_to_le32(lp->tx_dma_addr[entry]);
2543 wmb(); /* Make sure owner changes after all others are visible */
2544 lp->tx_ring[entry].status = cpu_to_le16(status);
2545
2546 lp->cur_tx++;
2547 lp->stats.tx_bytes += skb->len;
2548
2549 /* Trigger an immediate send poll. */
2550 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2551
2552 dev->trans_start = jiffies;
2553
2554 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2555 lp->tx_full = 1;
2556 netif_stop_queue(dev);
2557 }
2558 spin_unlock_irqrestore(&lp->lock, flags);
2559 return 0;
2560 }
2561
2562 /* The PCNET32 interrupt handler. */
2563 static irqreturn_t
2564 pcnet32_interrupt(int irq, void *dev_id)
2565 {
2566 struct net_device *dev = dev_id;
2567 struct pcnet32_private *lp;
2568 unsigned long ioaddr;
2569 u16 csr0;
2570 int boguscnt = max_interrupt_work;
2571
2572 ioaddr = dev->base_addr;
2573 lp = netdev_priv(dev);
2574
2575 spin_lock(&lp->lock);
2576
2577 csr0 = lp->a.read_csr(ioaddr, CSR0);
2578 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2579 if (csr0 == 0xffff) {
2580 break; /* PCMCIA remove happened */
2581 }
2582 /* Acknowledge all of the current interrupt sources ASAP. */
2583 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2584
2585 if (netif_msg_intr(lp))
2586 printk(KERN_DEBUG
2587 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2588 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2589
2590 /* Log misc errors. */
2591 if (csr0 & 0x4000)
2592 lp->stats.tx_errors++; /* Tx babble. */
2593 if (csr0 & 0x1000) {
2594 /*
2595 * This happens when our receive ring is full. This
2596 * shouldn't be a problem as we will see normal rx
2597 * interrupts for the frames in the receive ring. But
2598 * there are some PCI chipsets (I can reproduce this
2599 * on SP3G with Intel saturn chipset) which have
2600 * sometimes problems and will fill up the receive
2601 * ring with error descriptors. In this situation we
2602 * don't get a rx interrupt, but a missed frame
2603 * interrupt sooner or later.
2604 */
2605 lp->stats.rx_errors++; /* Missed a Rx frame. */
2606 }
2607 if (csr0 & 0x0800) {
2608 if (netif_msg_drv(lp))
2609 printk(KERN_ERR
2610 "%s: Bus master arbitration failure, status %4.4x.\n",
2611 dev->name, csr0);
2612 /* unlike for the lance, there is no restart needed */
2613 }
2614 #ifdef CONFIG_PCNET32_NAPI
2615 if (netif_rx_schedule_prep(dev, &lp->napi)) {
2616 u16 val;
2617 /* set interrupt masks */
2618 val = lp->a.read_csr(ioaddr, CSR3);
2619 val |= 0x5f00;
2620 lp->a.write_csr(ioaddr, CSR3, val);
2621 mmiowb();
2622 __netif_rx_schedule(dev, &lp->napi);
2623 break;
2624 }
2625 #else
2626 pcnet32_rx(dev, lp->napi.weight);
2627 if (pcnet32_tx(dev)) {
2628 /* reset the chip to clear the error condition, then restart */
2629 lp->a.reset(ioaddr);
2630 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2631 pcnet32_restart(dev, CSR0_START);
2632 netif_wake_queue(dev);
2633 }
2634 #endif
2635 csr0 = lp->a.read_csr(ioaddr, CSR0);
2636 }
2637
2638 #ifndef CONFIG_PCNET32_NAPI
2639 /* Set interrupt enable. */
2640 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2641 #endif
2642
2643 if (netif_msg_intr(lp))
2644 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2645 dev->name, lp->a.read_csr(ioaddr, CSR0));
2646
2647 spin_unlock(&lp->lock);
2648
2649 return IRQ_HANDLED;
2650 }
2651
2652 static int pcnet32_close(struct net_device *dev)
2653 {
2654 unsigned long ioaddr = dev->base_addr;
2655 struct pcnet32_private *lp = netdev_priv(dev);
2656 unsigned long flags;
2657
2658 del_timer_sync(&lp->watchdog_timer);
2659
2660 netif_stop_queue(dev);
2661 #ifdef CONFIG_PCNET32_NAPI
2662 napi_disable(&lp->napi);
2663 #endif
2664
2665 spin_lock_irqsave(&lp->lock, flags);
2666
2667 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2668
2669 if (netif_msg_ifdown(lp))
2670 printk(KERN_DEBUG
2671 "%s: Shutting down ethercard, status was %2.2x.\n",
2672 dev->name, lp->a.read_csr(ioaddr, CSR0));
2673
2674 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2675 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2676
2677 /*
2678 * Switch back to 16bit mode to avoid problems with dumb
2679 * DOS packet driver after a warm reboot
2680 */
2681 lp->a.write_bcr(ioaddr, 20, 4);
2682
2683 spin_unlock_irqrestore(&lp->lock, flags);
2684
2685 free_irq(dev->irq, dev);
2686
2687 spin_lock_irqsave(&lp->lock, flags);
2688
2689 pcnet32_purge_rx_ring(dev);
2690 pcnet32_purge_tx_ring(dev);
2691
2692 spin_unlock_irqrestore(&lp->lock, flags);
2693
2694 return 0;
2695 }
2696
2697 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2698 {
2699 struct pcnet32_private *lp = netdev_priv(dev);
2700 unsigned long ioaddr = dev->base_addr;
2701 unsigned long flags;
2702
2703 spin_lock_irqsave(&lp->lock, flags);
2704 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2705 spin_unlock_irqrestore(&lp->lock, flags);
2706
2707 return &lp->stats;
2708 }
2709
2710 /* taken from the sunlance driver, which it took from the depca driver */
2711 static void pcnet32_load_multicast(struct net_device *dev)
2712 {
2713 struct pcnet32_private *lp = netdev_priv(dev);
2714 volatile struct pcnet32_init_block *ib = lp->init_block;
2715 volatile __le16 *mcast_table = (__le16 *)ib->filter;
2716 struct dev_mc_list *dmi = dev->mc_list;
2717 unsigned long ioaddr = dev->base_addr;
2718 char *addrs;
2719 int i;
2720 u32 crc;
2721
2722 /* set all multicast bits */
2723 if (dev->flags & IFF_ALLMULTI) {
2724 ib->filter[0] = cpu_to_le32(~0U);
2725 ib->filter[1] = cpu_to_le32(~0U);
2726 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2727 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2728 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2729 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2730 return;
2731 }
2732 /* clear the multicast filter */
2733 ib->filter[0] = 0;
2734 ib->filter[1] = 0;
2735
2736 /* Add addresses */
2737 for (i = 0; i < dev->mc_count; i++) {
2738 addrs = dmi->dmi_addr;
2739 dmi = dmi->next;
2740
2741 /* multicast address? */
2742 if (!(*addrs & 1))
2743 continue;
2744
2745 crc = ether_crc_le(6, addrs);
2746 crc = crc >> 26;
2747 mcast_table[crc >> 4] |= cpu_to_le16(1 << (crc & 0xf));
2748 }
2749 for (i = 0; i < 4; i++)
2750 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2751 le16_to_cpu(mcast_table[i]));
2752 return;
2753 }
2754
2755 /*
2756 * Set or clear the multicast filter for this adaptor.
2757 */
2758 static void pcnet32_set_multicast_list(struct net_device *dev)
2759 {
2760 unsigned long ioaddr = dev->base_addr, flags;
2761 struct pcnet32_private *lp = netdev_priv(dev);
2762 int csr15, suspended;
2763
2764 spin_lock_irqsave(&lp->lock, flags);
2765 suspended = pcnet32_suspend(dev, &flags, 0);
2766 csr15 = lp->a.read_csr(ioaddr, CSR15);
2767 if (dev->flags & IFF_PROMISC) {
2768 /* Log any net taps. */
2769 if (netif_msg_hw(lp))
2770 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2771 dev->name);
2772 lp->init_block->mode =
2773 cpu_to_le16(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2774 7);
2775 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2776 } else {
2777 lp->init_block->mode =
2778 cpu_to_le16((lp->options & PCNET32_PORT_PORTSEL) << 7);
2779 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2780 pcnet32_load_multicast(dev);
2781 }
2782
2783 if (suspended) {
2784 int csr5;
2785 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2786 csr5 = lp->a.read_csr(ioaddr, CSR5);
2787 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2788 } else {
2789 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2790 pcnet32_restart(dev, CSR0_NORMAL);
2791 netif_wake_queue(dev);
2792 }
2793
2794 spin_unlock_irqrestore(&lp->lock, flags);
2795 }
2796
2797 /* This routine assumes that the lp->lock is held */
2798 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2799 {
2800 struct pcnet32_private *lp = netdev_priv(dev);
2801 unsigned long ioaddr = dev->base_addr;
2802 u16 val_out;
2803
2804 if (!lp->mii)
2805 return 0;
2806
2807 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2808 val_out = lp->a.read_bcr(ioaddr, 34);
2809
2810 return val_out;
2811 }
2812
2813 /* This routine assumes that the lp->lock is held */
2814 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2815 {
2816 struct pcnet32_private *lp = netdev_priv(dev);
2817 unsigned long ioaddr = dev->base_addr;
2818
2819 if (!lp->mii)
2820 return;
2821
2822 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2823 lp->a.write_bcr(ioaddr, 34, val);
2824 }
2825
2826 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2827 {
2828 struct pcnet32_private *lp = netdev_priv(dev);
2829 int rc;
2830 unsigned long flags;
2831
2832 /* SIOC[GS]MIIxxx ioctls */
2833 if (lp->mii) {
2834 spin_lock_irqsave(&lp->lock, flags);
2835 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2836 spin_unlock_irqrestore(&lp->lock, flags);
2837 } else {
2838 rc = -EOPNOTSUPP;
2839 }
2840
2841 return rc;
2842 }
2843
2844 static int pcnet32_check_otherphy(struct net_device *dev)
2845 {
2846 struct pcnet32_private *lp = netdev_priv(dev);
2847 struct mii_if_info mii = lp->mii_if;
2848 u16 bmcr;
2849 int i;
2850
2851 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2852 if (i == lp->mii_if.phy_id)
2853 continue; /* skip active phy */
2854 if (lp->phymask & (1 << i)) {
2855 mii.phy_id = i;
2856 if (mii_link_ok(&mii)) {
2857 /* found PHY with active link */
2858 if (netif_msg_link(lp))
2859 printk(KERN_INFO
2860 "%s: Using PHY number %d.\n",
2861 dev->name, i);
2862
2863 /* isolate inactive phy */
2864 bmcr =
2865 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2866 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2867 bmcr | BMCR_ISOLATE);
2868
2869 /* de-isolate new phy */
2870 bmcr = mdio_read(dev, i, MII_BMCR);
2871 mdio_write(dev, i, MII_BMCR,
2872 bmcr & ~BMCR_ISOLATE);
2873
2874 /* set new phy address */
2875 lp->mii_if.phy_id = i;
2876 return 1;
2877 }
2878 }
2879 }
2880 return 0;
2881 }
2882
2883 /*
2884 * Show the status of the media. Similar to mii_check_media however it
2885 * correctly shows the link speed for all (tested) pcnet32 variants.
2886 * Devices with no mii just report link state without speed.
2887 *
2888 * Caller is assumed to hold and release the lp->lock.
2889 */
2890
2891 static void pcnet32_check_media(struct net_device *dev, int verbose)
2892 {
2893 struct pcnet32_private *lp = netdev_priv(dev);
2894 int curr_link;
2895 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2896 u32 bcr9;
2897
2898 if (lp->mii) {
2899 curr_link = mii_link_ok(&lp->mii_if);
2900 } else {
2901 ulong ioaddr = dev->base_addr; /* card base I/O address */
2902 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2903 }
2904 if (!curr_link) {
2905 if (prev_link || verbose) {
2906 netif_carrier_off(dev);
2907 if (netif_msg_link(lp))
2908 printk(KERN_INFO "%s: link down\n", dev->name);
2909 }
2910 if (lp->phycount > 1) {
2911 curr_link = pcnet32_check_otherphy(dev);
2912 prev_link = 0;
2913 }
2914 } else if (verbose || !prev_link) {
2915 netif_carrier_on(dev);
2916 if (lp->mii) {
2917 if (netif_msg_link(lp)) {
2918 struct ethtool_cmd ecmd;
2919 mii_ethtool_gset(&lp->mii_if, &ecmd);
2920 printk(KERN_INFO
2921 "%s: link up, %sMbps, %s-duplex\n",
2922 dev->name,
2923 (ecmd.speed == SPEED_100) ? "100" : "10",
2924 (ecmd.duplex ==
2925 DUPLEX_FULL) ? "full" : "half");
2926 }
2927 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2928 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2929 if (lp->mii_if.full_duplex)
2930 bcr9 |= (1 << 0);
2931 else
2932 bcr9 &= ~(1 << 0);
2933 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2934 }
2935 } else {
2936 if (netif_msg_link(lp))
2937 printk(KERN_INFO "%s: link up\n", dev->name);
2938 }
2939 }
2940 }
2941
2942 /*
2943 * Check for loss of link and link establishment.
2944 * Can not use mii_check_media because it does nothing if mode is forced.
2945 */
2946
2947 static void pcnet32_watchdog(struct net_device *dev)
2948 {
2949 struct pcnet32_private *lp = netdev_priv(dev);
2950 unsigned long flags;
2951
2952 /* Print the link status if it has changed */
2953 spin_lock_irqsave(&lp->lock, flags);
2954 pcnet32_check_media(dev, 0);
2955 spin_unlock_irqrestore(&lp->lock, flags);
2956
2957 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2958 }
2959
2960 static int pcnet32_pm_suspend(struct pci_dev *pdev, pm_message_t state)
2961 {
2962 struct net_device *dev = pci_get_drvdata(pdev);
2963
2964 if (netif_running(dev)) {
2965 netif_device_detach(dev);
2966 pcnet32_close(dev);
2967 }
2968 pci_save_state(pdev);
2969 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2970 return 0;
2971 }
2972
2973 static int pcnet32_pm_resume(struct pci_dev *pdev)
2974 {
2975 struct net_device *dev = pci_get_drvdata(pdev);
2976
2977 pci_set_power_state(pdev, PCI_D0);
2978 pci_restore_state(pdev);
2979
2980 if (netif_running(dev)) {
2981 pcnet32_open(dev);
2982 netif_device_attach(dev);
2983 }
2984 return 0;
2985 }
2986
2987 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2988 {
2989 struct net_device *dev = pci_get_drvdata(pdev);
2990
2991 if (dev) {
2992 struct pcnet32_private *lp = netdev_priv(dev);
2993
2994 unregister_netdev(dev);
2995 pcnet32_free_ring(dev);
2996 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2997 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
2998 lp->init_block, lp->init_dma_addr);
2999 free_netdev(dev);
3000 pci_disable_device(pdev);
3001 pci_set_drvdata(pdev, NULL);
3002 }
3003 }
3004
3005 static struct pci_driver pcnet32_driver = {
3006 .name = DRV_NAME,
3007 .probe = pcnet32_probe_pci,
3008 .remove = __devexit_p(pcnet32_remove_one),
3009 .id_table = pcnet32_pci_tbl,
3010 .suspend = pcnet32_pm_suspend,
3011 .resume = pcnet32_pm_resume,
3012 };
3013
3014 /* An additional parameter that may be passed in... */
3015 static int debug = -1;
3016 static int tx_start_pt = -1;
3017 static int pcnet32_have_pci;
3018
3019 module_param(debug, int, 0);
3020 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
3021 module_param(max_interrupt_work, int, 0);
3022 MODULE_PARM_DESC(max_interrupt_work,
3023 DRV_NAME " maximum events handled per interrupt");
3024 module_param(rx_copybreak, int, 0);
3025 MODULE_PARM_DESC(rx_copybreak,
3026 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
3027 module_param(tx_start_pt, int, 0);
3028 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3029 module_param(pcnet32vlb, int, 0);
3030 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3031 module_param_array(options, int, NULL, 0);
3032 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3033 module_param_array(full_duplex, int, NULL, 0);
3034 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3035 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3036 module_param_array(homepna, int, NULL, 0);
3037 MODULE_PARM_DESC(homepna,
3038 DRV_NAME
3039 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3040
3041 MODULE_AUTHOR("Thomas Bogendoerfer");
3042 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3043 MODULE_LICENSE("GPL");
3044
3045 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3046
3047 static int __init pcnet32_init_module(void)
3048 {
3049 printk(KERN_INFO "%s", version);
3050
3051 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3052
3053 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3054 tx_start = tx_start_pt;
3055
3056 /* find the PCI devices */
3057 if (!pci_register_driver(&pcnet32_driver))
3058 pcnet32_have_pci = 1;
3059
3060 /* should we find any remaining VLbus devices ? */
3061 if (pcnet32vlb)
3062 pcnet32_probe_vlbus(pcnet32_portlist);
3063
3064 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3065 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3066
3067 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3068 }
3069
3070 static void __exit pcnet32_cleanup_module(void)
3071 {
3072 struct net_device *next_dev;
3073
3074 while (pcnet32_dev) {
3075 struct pcnet32_private *lp = netdev_priv(pcnet32_dev);
3076 next_dev = lp->next;
3077 unregister_netdev(pcnet32_dev);
3078 pcnet32_free_ring(pcnet32_dev);
3079 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3080 pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
3081 lp->init_block, lp->init_dma_addr);
3082 free_netdev(pcnet32_dev);
3083 pcnet32_dev = next_dev;
3084 }
3085
3086 if (pcnet32_have_pci)
3087 pci_unregister_driver(&pcnet32_driver);
3088 }
3089
3090 module_init(pcnet32_init_module);
3091 module_exit(pcnet32_cleanup_module);
3092
3093 /*
3094 * Local variables:
3095 * c-indent-level: 4
3096 * tab-width: 8
3097 * End:
3098 */
Linux kernel - Deliverables
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