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amd-xgbe-phy: Checkpatch fixes
[deliverable/linux.git] / drivers / net / phy / amd-xgbe-phy.c
1 /*
2 * AMD 10Gb Ethernet PHY driver
3 *
4 * This file is available to you under your choice of the following two
5 * licenses:
6 *
7 * License 1: GPLv2
8 *
9 * Copyright (c) 2014 Advanced Micro Devices, Inc.
10 *
11 * This file is free software; you may copy, redistribute and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation, either version 2 of the License, or (at
14 * your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program. If not, see <http://www.gnu.org/licenses/>.
23 *
24 *
25 * License 2: Modified BSD
26 *
27 * Copyright (c) 2014 Advanced Micro Devices, Inc.
28 * All rights reserved.
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in the
36 * documentation and/or other materials provided with the distribution.
37 * * Neither the name of Advanced Micro Devices, Inc. nor the
38 * names of its contributors may be used to endorse or promote products
39 * derived from this software without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
44 * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
45 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
46 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
47 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
48 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 #include <linux/kernel.h>
54 #include <linux/device.h>
55 #include <linux/platform_device.h>
56 #include <linux/string.h>
57 #include <linux/errno.h>
58 #include <linux/unistd.h>
59 #include <linux/slab.h>
60 #include <linux/interrupt.h>
61 #include <linux/init.h>
62 #include <linux/delay.h>
63 #include <linux/netdevice.h>
64 #include <linux/etherdevice.h>
65 #include <linux/skbuff.h>
66 #include <linux/mm.h>
67 #include <linux/module.h>
68 #include <linux/mii.h>
69 #include <linux/ethtool.h>
70 #include <linux/phy.h>
71 #include <linux/mdio.h>
72 #include <linux/io.h>
73 #include <linux/of.h>
74 #include <linux/of_platform.h>
75 #include <linux/of_device.h>
76 #include <linux/uaccess.h>
77 #include <linux/bitops.h>
78
79 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
80 MODULE_LICENSE("Dual BSD/GPL");
81 MODULE_VERSION("1.0.0-a");
82 MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
83
84 #define XGBE_PHY_ID 0x000162d0
85 #define XGBE_PHY_MASK 0xfffffff0
86
87 #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
88
89 #define XGBE_AN_INT_CMPLT 0x01
90 #define XGBE_AN_INC_LINK 0x02
91 #define XGBE_AN_PG_RCV 0x04
92
93 #define XNP_MCF_NULL_MESSAGE 0x001
94 #define XNP_ACK_PROCESSED BIT(12)
95 #define XNP_MP_FORMATTED BIT(13)
96 #define XNP_NP_EXCHANGE BIT(15)
97
98 #define XGBE_PHY_RATECHANGE_COUNT 500
99
100 #ifndef MDIO_PMA_10GBR_PMD_CTRL
101 #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
102 #endif
103
104 #ifndef MDIO_PMA_10GBR_FEC_CTRL
105 #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
106 #endif
107
108 #ifndef MDIO_AN_XNP
109 #define MDIO_AN_XNP 0x0016
110 #endif
111
112 #ifndef MDIO_AN_INTMASK
113 #define MDIO_AN_INTMASK 0x8001
114 #endif
115
116 #ifndef MDIO_AN_INT
117 #define MDIO_AN_INT 0x8002
118 #endif
119
120 #ifndef MDIO_AN_KR_CTRL
121 #define MDIO_AN_KR_CTRL 0x8003
122 #endif
123
124 #ifndef MDIO_CTRL1_SPEED1G
125 #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
126 #endif
127
128 #ifndef MDIO_KR_CTRL_PDETECT
129 #define MDIO_KR_CTRL_PDETECT 0x01
130 #endif
131
132 /* SerDes integration register offsets */
133 #define SIR0_KR_RT_1 0x002c
134 #define SIR0_STATUS 0x0040
135 #define SIR1_SPEED 0x0000
136
137 /* SerDes integration register entry bit positions and sizes */
138 #define SIR0_KR_RT_1_RESET_INDEX 11
139 #define SIR0_KR_RT_1_RESET_WIDTH 1
140 #define SIR0_STATUS_RX_READY_INDEX 0
141 #define SIR0_STATUS_RX_READY_WIDTH 1
142 #define SIR0_STATUS_TX_READY_INDEX 8
143 #define SIR0_STATUS_TX_READY_WIDTH 1
144 #define SIR1_SPEED_DATARATE_INDEX 4
145 #define SIR1_SPEED_DATARATE_WIDTH 2
146 #define SIR1_SPEED_PI_SPD_SEL_INDEX 12
147 #define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
148 #define SIR1_SPEED_PLLSEL_INDEX 3
149 #define SIR1_SPEED_PLLSEL_WIDTH 1
150 #define SIR1_SPEED_RATECHANGE_INDEX 6
151 #define SIR1_SPEED_RATECHANGE_WIDTH 1
152 #define SIR1_SPEED_TXAMP_INDEX 8
153 #define SIR1_SPEED_TXAMP_WIDTH 4
154 #define SIR1_SPEED_WORDMODE_INDEX 0
155 #define SIR1_SPEED_WORDMODE_WIDTH 3
156
157 #define SPEED_10000_CDR 0x7
158 #define SPEED_10000_PLL 0x1
159 #define SPEED_10000_RATE 0x0
160 #define SPEED_10000_TXAMP 0xa
161 #define SPEED_10000_WORD 0x7
162
163 #define SPEED_2500_CDR 0x2
164 #define SPEED_2500_PLL 0x0
165 #define SPEED_2500_RATE 0x1
166 #define SPEED_2500_TXAMP 0xf
167 #define SPEED_2500_WORD 0x1
168
169 #define SPEED_1000_CDR 0x2
170 #define SPEED_1000_PLL 0x0
171 #define SPEED_1000_RATE 0x3
172 #define SPEED_1000_TXAMP 0xf
173 #define SPEED_1000_WORD 0x1
174
175 /* SerDes RxTx register offsets */
176 #define RXTX_REG20 0x0050
177 #define RXTX_REG114 0x01c8
178
179 /* SerDes RxTx register entry bit positions and sizes */
180 #define RXTX_REG20_BLWC_ENA_INDEX 2
181 #define RXTX_REG20_BLWC_ENA_WIDTH 1
182 #define RXTX_REG114_PQ_REG_INDEX 9
183 #define RXTX_REG114_PQ_REG_WIDTH 7
184
185 #define RXTX_10000_BLWC 0
186 #define RXTX_10000_PQ 0x1e
187
188 #define RXTX_2500_BLWC 1
189 #define RXTX_2500_PQ 0xa
190
191 #define RXTX_1000_BLWC 1
192 #define RXTX_1000_PQ 0xa
193
194 /* Bit setting and getting macros
195 * The get macro will extract the current bit field value from within
196 * the variable
197 *
198 * The set macro will clear the current bit field value within the
199 * variable and then set the bit field of the variable to the
200 * specified value
201 */
202 #define GET_BITS(_var, _index, _width) \
203 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
204
205 #define SET_BITS(_var, _index, _width, _val) \
206 do { \
207 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
208 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
209 } while (0)
210
211 #define XSIR_GET_BITS(_var, _prefix, _field) \
212 GET_BITS((_var), \
213 _prefix##_##_field##_INDEX, \
214 _prefix##_##_field##_WIDTH)
215
216 #define XSIR_SET_BITS(_var, _prefix, _field, _val) \
217 SET_BITS((_var), \
218 _prefix##_##_field##_INDEX, \
219 _prefix##_##_field##_WIDTH, (_val))
220
221 /* Macros for reading or writing SerDes integration registers
222 * The ioread macros will get bit fields or full values using the
223 * register definitions formed using the input names
224 *
225 * The iowrite macros will set bit fields or full values using the
226 * register definitions formed using the input names
227 */
228 #define XSIR0_IOREAD(_priv, _reg) \
229 ioread16((_priv)->sir0_regs + _reg)
230
231 #define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
232 GET_BITS(XSIR0_IOREAD((_priv), _reg), \
233 _reg##_##_field##_INDEX, \
234 _reg##_##_field##_WIDTH)
235
236 #define XSIR0_IOWRITE(_priv, _reg, _val) \
237 iowrite16((_val), (_priv)->sir0_regs + _reg)
238
239 #define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
240 do { \
241 u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
242 SET_BITS(reg_val, \
243 _reg##_##_field##_INDEX, \
244 _reg##_##_field##_WIDTH, (_val)); \
245 XSIR0_IOWRITE((_priv), _reg, reg_val); \
246 } while (0)
247
248 #define XSIR1_IOREAD(_priv, _reg) \
249 ioread16((_priv)->sir1_regs + _reg)
250
251 #define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
252 GET_BITS(XSIR1_IOREAD((_priv), _reg), \
253 _reg##_##_field##_INDEX, \
254 _reg##_##_field##_WIDTH)
255
256 #define XSIR1_IOWRITE(_priv, _reg, _val) \
257 iowrite16((_val), (_priv)->sir1_regs + _reg)
258
259 #define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
260 do { \
261 u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
262 SET_BITS(reg_val, \
263 _reg##_##_field##_INDEX, \
264 _reg##_##_field##_WIDTH, (_val)); \
265 XSIR1_IOWRITE((_priv), _reg, reg_val); \
266 } while (0)
267
268 /* Macros for reading or writing SerDes RxTx registers
269 * The ioread macros will get bit fields or full values using the
270 * register definitions formed using the input names
271 *
272 * The iowrite macros will set bit fields or full values using the
273 * register definitions formed using the input names
274 */
275 #define XRXTX_IOREAD(_priv, _reg) \
276 ioread16((_priv)->rxtx_regs + _reg)
277
278 #define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
279 GET_BITS(XRXTX_IOREAD((_priv), _reg), \
280 _reg##_##_field##_INDEX, \
281 _reg##_##_field##_WIDTH)
282
283 #define XRXTX_IOWRITE(_priv, _reg, _val) \
284 iowrite16((_val), (_priv)->rxtx_regs + _reg)
285
286 #define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
287 do { \
288 u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
289 SET_BITS(reg_val, \
290 _reg##_##_field##_INDEX, \
291 _reg##_##_field##_WIDTH, (_val)); \
292 XRXTX_IOWRITE((_priv), _reg, reg_val); \
293 } while (0)
294
295 enum amd_xgbe_phy_an {
296 AMD_XGBE_AN_READY = 0,
297 AMD_XGBE_AN_START,
298 AMD_XGBE_AN_EVENT,
299 AMD_XGBE_AN_PAGE_RECEIVED,
300 AMD_XGBE_AN_INCOMPAT_LINK,
301 AMD_XGBE_AN_COMPLETE,
302 AMD_XGBE_AN_NO_LINK,
303 AMD_XGBE_AN_EXIT,
304 AMD_XGBE_AN_ERROR,
305 };
306
307 enum amd_xgbe_phy_rx {
308 AMD_XGBE_RX_READY = 0,
309 AMD_XGBE_RX_BPA,
310 AMD_XGBE_RX_XNP,
311 AMD_XGBE_RX_COMPLETE,
312 };
313
314 enum amd_xgbe_phy_mode {
315 AMD_XGBE_MODE_KR,
316 AMD_XGBE_MODE_KX,
317 };
318
319 enum amd_xgbe_phy_speedset {
320 AMD_XGBE_PHY_SPEEDSET_1000_10000,
321 AMD_XGBE_PHY_SPEEDSET_2500_10000,
322 };
323
324 struct amd_xgbe_phy_priv {
325 struct platform_device *pdev;
326 struct device *dev;
327
328 struct phy_device *phydev;
329
330 /* SerDes related mmio resources */
331 struct resource *rxtx_res;
332 struct resource *sir0_res;
333 struct resource *sir1_res;
334
335 /* SerDes related mmio registers */
336 void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
337 void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
338 void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
339
340 /* Maintain link status for re-starting auto-negotiation */
341 unsigned int link;
342 unsigned int speed_set;
343
344 /* Auto-negotiation state machine support */
345 struct mutex an_mutex;
346 enum amd_xgbe_phy_an an_result;
347 enum amd_xgbe_phy_an an_state;
348 enum amd_xgbe_phy_rx kr_state;
349 enum amd_xgbe_phy_rx kx_state;
350 struct work_struct an_work;
351 struct workqueue_struct *an_workqueue;
352 unsigned int parallel_detect;
353 };
354
355 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
356 {
357 int ret;
358
359 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
360 if (ret < 0)
361 return ret;
362
363 ret |= 0x02;
364 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
365
366 return 0;
367 }
368
369 static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
370 {
371 int ret;
372
373 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
374 if (ret < 0)
375 return ret;
376
377 ret &= ~0x02;
378 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
379
380 return 0;
381 }
382
383 static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
384 {
385 int ret;
386
387 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
388 if (ret < 0)
389 return ret;
390
391 ret |= MDIO_CTRL1_LPOWER;
392 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
393
394 usleep_range(75, 100);
395
396 ret &= ~MDIO_CTRL1_LPOWER;
397 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
398
399 return 0;
400 }
401
402 static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
403 {
404 struct amd_xgbe_phy_priv *priv = phydev->priv;
405
406 /* Assert Rx and Tx ratechange */
407 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
408 }
409
410 static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
411 {
412 struct amd_xgbe_phy_priv *priv = phydev->priv;
413 unsigned int wait;
414 u16 status;
415
416 /* Release Rx and Tx ratechange */
417 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
418
419 /* Wait for Rx and Tx ready */
420 wait = XGBE_PHY_RATECHANGE_COUNT;
421 while (wait--) {
422 usleep_range(50, 75);
423
424 status = XSIR0_IOREAD(priv, SIR0_STATUS);
425 if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
426 XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
427 return;
428 }
429
430 netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
431 status);
432 }
433
434 static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
435 {
436 struct amd_xgbe_phy_priv *priv = phydev->priv;
437 int ret;
438
439 /* Enable KR training */
440 ret = amd_xgbe_an_enable_kr_training(phydev);
441 if (ret < 0)
442 return ret;
443
444 /* Set PCS to KR/10G speed */
445 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
446 if (ret < 0)
447 return ret;
448
449 ret &= ~MDIO_PCS_CTRL2_TYPE;
450 ret |= MDIO_PCS_CTRL2_10GBR;
451 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
452
453 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
454 if (ret < 0)
455 return ret;
456
457 ret &= ~MDIO_CTRL1_SPEEDSEL;
458 ret |= MDIO_CTRL1_SPEED10G;
459 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
460
461 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
462 if (ret < 0)
463 return ret;
464
465 /* Set SerDes to 10G speed */
466 amd_xgbe_phy_serdes_start_ratechange(phydev);
467
468 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
469 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
470 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
471 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
472 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
473
474 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
475 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
476
477 amd_xgbe_phy_serdes_complete_ratechange(phydev);
478
479 return 0;
480 }
481
482 static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
483 {
484 struct amd_xgbe_phy_priv *priv = phydev->priv;
485 int ret;
486
487 /* Disable KR training */
488 ret = amd_xgbe_an_disable_kr_training(phydev);
489 if (ret < 0)
490 return ret;
491
492 /* Set PCS to KX/1G speed */
493 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
494 if (ret < 0)
495 return ret;
496
497 ret &= ~MDIO_PCS_CTRL2_TYPE;
498 ret |= MDIO_PCS_CTRL2_10GBX;
499 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
500
501 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
502 if (ret < 0)
503 return ret;
504
505 ret &= ~MDIO_CTRL1_SPEEDSEL;
506 ret |= MDIO_CTRL1_SPEED1G;
507 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
508
509 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
510 if (ret < 0)
511 return ret;
512
513 /* Set SerDes to 2.5G speed */
514 amd_xgbe_phy_serdes_start_ratechange(phydev);
515
516 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
517 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
518 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
519 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
520 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
521
522 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
523 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
524
525 amd_xgbe_phy_serdes_complete_ratechange(phydev);
526
527 return 0;
528 }
529
530 static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
531 {
532 struct amd_xgbe_phy_priv *priv = phydev->priv;
533 int ret;
534
535 /* Disable KR training */
536 ret = amd_xgbe_an_disable_kr_training(phydev);
537 if (ret < 0)
538 return ret;
539
540 /* Set PCS to KX/1G speed */
541 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
542 if (ret < 0)
543 return ret;
544
545 ret &= ~MDIO_PCS_CTRL2_TYPE;
546 ret |= MDIO_PCS_CTRL2_10GBX;
547 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
548
549 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
550 if (ret < 0)
551 return ret;
552
553 ret &= ~MDIO_CTRL1_SPEEDSEL;
554 ret |= MDIO_CTRL1_SPEED1G;
555 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
556
557 ret = amd_xgbe_phy_pcs_power_cycle(phydev);
558 if (ret < 0)
559 return ret;
560
561 /* Set SerDes to 1G speed */
562 amd_xgbe_phy_serdes_start_ratechange(phydev);
563
564 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
565 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
566 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
567 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
568 XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
569
570 XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
571 XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
572
573 amd_xgbe_phy_serdes_complete_ratechange(phydev);
574
575 return 0;
576 }
577
578 static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
579 enum amd_xgbe_phy_mode *mode)
580 {
581 int ret;
582
583 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
584 if (ret < 0)
585 return ret;
586
587 if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
588 *mode = AMD_XGBE_MODE_KR;
589 else
590 *mode = AMD_XGBE_MODE_KX;
591
592 return 0;
593 }
594
595 static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
596 {
597 enum amd_xgbe_phy_mode mode;
598
599 if (amd_xgbe_phy_cur_mode(phydev, &mode))
600 return false;
601
602 return (mode == AMD_XGBE_MODE_KR);
603 }
604
605 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
606 {
607 struct amd_xgbe_phy_priv *priv = phydev->priv;
608 int ret;
609
610 /* If we are in KR switch to KX, and vice-versa */
611 if (amd_xgbe_phy_in_kr_mode(phydev)) {
612 if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
613 ret = amd_xgbe_phy_gmii_mode(phydev);
614 else
615 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
616 } else {
617 ret = amd_xgbe_phy_xgmii_mode(phydev);
618 }
619
620 return ret;
621 }
622
623 static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
624 enum amd_xgbe_phy_mode mode)
625 {
626 enum amd_xgbe_phy_mode cur_mode;
627 int ret;
628
629 ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
630 if (ret)
631 return ret;
632
633 if (mode != cur_mode)
634 ret = amd_xgbe_phy_switch_mode(phydev);
635
636 return ret;
637 }
638
639 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
640 enum amd_xgbe_phy_rx *state)
641 {
642 struct amd_xgbe_phy_priv *priv = phydev->priv;
643 int ad_reg, lp_reg, ret;
644
645 *state = AMD_XGBE_RX_COMPLETE;
646
647 /* If we're not in KR mode then we're done */
648 if (!amd_xgbe_phy_in_kr_mode(phydev))
649 return AMD_XGBE_AN_EVENT;
650
651 /* Enable/Disable FEC */
652 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
653 if (ad_reg < 0)
654 return AMD_XGBE_AN_ERROR;
655
656 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
657 if (lp_reg < 0)
658 return AMD_XGBE_AN_ERROR;
659
660 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
661 if (ret < 0)
662 return AMD_XGBE_AN_ERROR;
663
664 if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
665 ret |= 0x01;
666 else
667 ret &= ~0x01;
668
669 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
670
671 /* Start KR training */
672 ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
673 if (ret < 0)
674 return AMD_XGBE_AN_ERROR;
675
676 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
677
678 ret |= 0x01;
679 phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
680
681 XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
682
683 return AMD_XGBE_AN_EVENT;
684 }
685
686 static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
687 enum amd_xgbe_phy_rx *state)
688 {
689 u16 msg;
690
691 *state = AMD_XGBE_RX_XNP;
692
693 msg = XNP_MCF_NULL_MESSAGE;
694 msg |= XNP_MP_FORMATTED;
695
696 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
697 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
698 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
699
700 return AMD_XGBE_AN_EVENT;
701 }
702
703 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
704 enum amd_xgbe_phy_rx *state)
705 {
706 unsigned int link_support;
707 int ret, ad_reg, lp_reg;
708
709 /* Read Base Ability register 2 first */
710 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
711 if (ret < 0)
712 return AMD_XGBE_AN_ERROR;
713
714 /* Check for a supported mode, otherwise restart in a different one */
715 link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
716 if (!(ret & link_support))
717 return AMD_XGBE_AN_INCOMPAT_LINK;
718
719 /* Check Extended Next Page support */
720 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
721 if (ad_reg < 0)
722 return AMD_XGBE_AN_ERROR;
723
724 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
725 if (lp_reg < 0)
726 return AMD_XGBE_AN_ERROR;
727
728 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
729 amd_xgbe_an_tx_xnp(phydev, state) :
730 amd_xgbe_an_tx_training(phydev, state);
731 }
732
733 static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
734 enum amd_xgbe_phy_rx *state)
735 {
736 int ad_reg, lp_reg;
737
738 /* Check Extended Next Page support */
739 ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
740 if (ad_reg < 0)
741 return AMD_XGBE_AN_ERROR;
742
743 lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
744 if (lp_reg < 0)
745 return AMD_XGBE_AN_ERROR;
746
747 return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
748 amd_xgbe_an_tx_xnp(phydev, state) :
749 amd_xgbe_an_tx_training(phydev, state);
750 }
751
752 static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
753 {
754 struct amd_xgbe_phy_priv *priv = phydev->priv;
755 int ret;
756
757 /* Be sure we aren't looping trying to negotiate */
758 if (amd_xgbe_phy_in_kr_mode(phydev)) {
759 if (priv->kr_state != AMD_XGBE_RX_READY)
760 return AMD_XGBE_AN_NO_LINK;
761 priv->kr_state = AMD_XGBE_RX_BPA;
762 } else {
763 if (priv->kx_state != AMD_XGBE_RX_READY)
764 return AMD_XGBE_AN_NO_LINK;
765 priv->kx_state = AMD_XGBE_RX_BPA;
766 }
767
768 /* Set up Advertisement register 3 first */
769 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
770 if (ret < 0)
771 return AMD_XGBE_AN_ERROR;
772
773 if (phydev->supported & SUPPORTED_10000baseR_FEC)
774 ret |= 0xc000;
775 else
776 ret &= ~0xc000;
777
778 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
779
780 /* Set up Advertisement register 2 next */
781 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
782 if (ret < 0)
783 return AMD_XGBE_AN_ERROR;
784
785 if (phydev->supported & SUPPORTED_10000baseKR_Full)
786 ret |= 0x80;
787 else
788 ret &= ~0x80;
789
790 if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
791 (phydev->supported & SUPPORTED_2500baseX_Full))
792 ret |= 0x20;
793 else
794 ret &= ~0x20;
795
796 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
797
798 /* Set up Advertisement register 1 last */
799 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
800 if (ret < 0)
801 return AMD_XGBE_AN_ERROR;
802
803 if (phydev->supported & SUPPORTED_Pause)
804 ret |= 0x400;
805 else
806 ret &= ~0x400;
807
808 if (phydev->supported & SUPPORTED_Asym_Pause)
809 ret |= 0x800;
810 else
811 ret &= ~0x800;
812
813 /* We don't intend to perform XNP */
814 ret &= ~XNP_NP_EXCHANGE;
815
816 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
817
818 /* Enable and start auto-negotiation */
819 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
820
821 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
822 if (ret < 0)
823 return AMD_XGBE_AN_ERROR;
824
825 ret |= MDIO_KR_CTRL_PDETECT;
826 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
827
828 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
829 if (ret < 0)
830 return AMD_XGBE_AN_ERROR;
831
832 ret |= MDIO_AN_CTRL1_ENABLE;
833 ret |= MDIO_AN_CTRL1_RESTART;
834 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
835
836 return AMD_XGBE_AN_EVENT;
837 }
838
839 static enum amd_xgbe_phy_an amd_xgbe_an_event(struct phy_device *phydev)
840 {
841 enum amd_xgbe_phy_an new_state;
842 int ret;
843
844 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
845 if (ret < 0)
846 return AMD_XGBE_AN_ERROR;
847
848 new_state = AMD_XGBE_AN_EVENT;
849 if (ret & XGBE_AN_PG_RCV)
850 new_state = AMD_XGBE_AN_PAGE_RECEIVED;
851 else if (ret & XGBE_AN_INC_LINK)
852 new_state = AMD_XGBE_AN_INCOMPAT_LINK;
853 else if (ret & XGBE_AN_INT_CMPLT)
854 new_state = AMD_XGBE_AN_COMPLETE;
855
856 if (new_state != AMD_XGBE_AN_EVENT)
857 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
858
859 return new_state;
860 }
861
862 static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
863 {
864 struct amd_xgbe_phy_priv *priv = phydev->priv;
865 enum amd_xgbe_phy_rx *state;
866 int ret;
867
868 state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
869 : &priv->kx_state;
870
871 switch (*state) {
872 case AMD_XGBE_RX_BPA:
873 ret = amd_xgbe_an_rx_bpa(phydev, state);
874 break;
875
876 case AMD_XGBE_RX_XNP:
877 ret = amd_xgbe_an_rx_xnp(phydev, state);
878 break;
879
880 default:
881 ret = AMD_XGBE_AN_ERROR;
882 }
883
884 return ret;
885 }
886
887 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
888 {
889 int ret;
890
891 ret = amd_xgbe_phy_switch_mode(phydev);
892 if (ret)
893 return AMD_XGBE_AN_ERROR;
894
895 return AMD_XGBE_AN_START;
896 }
897
898 static void amd_xgbe_an_state_machine(struct work_struct *work)
899 {
900 struct amd_xgbe_phy_priv *priv = container_of(work,
901 struct amd_xgbe_phy_priv,
902 an_work);
903 struct phy_device *phydev = priv->phydev;
904 enum amd_xgbe_phy_an cur_state;
905 int sleep;
906 unsigned int an_supported = 0;
907
908 /* Start in KX mode */
909 if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
910 priv->an_state = AMD_XGBE_AN_ERROR;
911
912 while (1) {
913 mutex_lock(&priv->an_mutex);
914
915 cur_state = priv->an_state;
916
917 switch (priv->an_state) {
918 case AMD_XGBE_AN_START:
919 an_supported = 0;
920 priv->parallel_detect = 0;
921 priv->an_state = amd_xgbe_an_start(phydev);
922 break;
923
924 case AMD_XGBE_AN_EVENT:
925 priv->an_state = amd_xgbe_an_event(phydev);
926 break;
927
928 case AMD_XGBE_AN_PAGE_RECEIVED:
929 priv->an_state = amd_xgbe_an_page_received(phydev);
930 an_supported++;
931 break;
932
933 case AMD_XGBE_AN_INCOMPAT_LINK:
934 priv->an_state = amd_xgbe_an_incompat_link(phydev);
935 break;
936
937 case AMD_XGBE_AN_COMPLETE:
938 priv->parallel_detect = an_supported ? 0 : 1;
939 netdev_info(phydev->attached_dev, "%s successful\n",
940 an_supported ? "Auto negotiation"
941 : "Parallel detection");
942 /* fall through */
943
944 case AMD_XGBE_AN_NO_LINK:
945 case AMD_XGBE_AN_EXIT:
946 goto exit_unlock;
947
948 default:
949 priv->an_state = AMD_XGBE_AN_ERROR;
950 }
951
952 if (priv->an_state == AMD_XGBE_AN_ERROR) {
953 netdev_err(phydev->attached_dev,
954 "error during auto-negotiation, state=%u\n",
955 cur_state);
956 goto exit_unlock;
957 }
958
959 sleep = (priv->an_state == AMD_XGBE_AN_EVENT) ? 1 : 0;
960
961 mutex_unlock(&priv->an_mutex);
962
963 if (sleep)
964 usleep_range(20, 50);
965 }
966
967 exit_unlock:
968 priv->an_result = priv->an_state;
969 priv->an_state = AMD_XGBE_AN_READY;
970
971 mutex_unlock(&priv->an_mutex);
972 }
973
974 static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
975 {
976 int count, ret;
977
978 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
979 if (ret < 0)
980 return ret;
981
982 ret |= MDIO_CTRL1_RESET;
983 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
984
985 count = 50;
986 do {
987 msleep(20);
988 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
989 if (ret < 0)
990 return ret;
991 } while ((ret & MDIO_CTRL1_RESET) && --count);
992
993 if (ret & MDIO_CTRL1_RESET)
994 return -ETIMEDOUT;
995
996 /* Make sure the XPCS and SerDes are in compatible states */
997 return amd_xgbe_phy_xgmii_mode(phydev);
998 }
999
1000 static int amd_xgbe_phy_config_init(struct phy_device *phydev)
1001 {
1002 struct amd_xgbe_phy_priv *priv = phydev->priv;
1003
1004 /* Initialize supported features */
1005 phydev->supported = SUPPORTED_Autoneg;
1006 phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
1007 phydev->supported |= SUPPORTED_Backplane;
1008 phydev->supported |= SUPPORTED_10000baseKR_Full |
1009 SUPPORTED_10000baseR_FEC;
1010 switch (priv->speed_set) {
1011 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1012 phydev->supported |= SUPPORTED_1000baseKX_Full;
1013 break;
1014 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1015 phydev->supported |= SUPPORTED_2500baseX_Full;
1016 break;
1017 }
1018 phydev->advertising = phydev->supported;
1019
1020 /* Turn off and clear interrupts */
1021 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0);
1022 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
1023
1024 return 0;
1025 }
1026
1027 static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
1028 {
1029 int ret;
1030
1031 /* Disable auto-negotiation */
1032 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
1033 if (ret < 0)
1034 return ret;
1035
1036 ret &= ~MDIO_AN_CTRL1_ENABLE;
1037 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
1038
1039 /* Validate/Set specified speed */
1040 switch (phydev->speed) {
1041 case SPEED_10000:
1042 ret = amd_xgbe_phy_xgmii_mode(phydev);
1043 break;
1044
1045 case SPEED_2500:
1046 ret = amd_xgbe_phy_gmii_2500_mode(phydev);
1047 break;
1048
1049 case SPEED_1000:
1050 ret = amd_xgbe_phy_gmii_mode(phydev);
1051 break;
1052
1053 default:
1054 ret = -EINVAL;
1055 }
1056
1057 if (ret < 0)
1058 return ret;
1059
1060 /* Validate duplex mode */
1061 if (phydev->duplex != DUPLEX_FULL)
1062 return -EINVAL;
1063
1064 phydev->pause = 0;
1065 phydev->asym_pause = 0;
1066
1067 return 0;
1068 }
1069
1070 static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
1071 {
1072 struct amd_xgbe_phy_priv *priv = phydev->priv;
1073 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1074
1075 if (phydev->autoneg != AUTONEG_ENABLE)
1076 return amd_xgbe_phy_setup_forced(phydev);
1077
1078 /* Make sure we have the AN MMD present */
1079 if (!(mmd_mask & MDIO_DEVS_AN))
1080 return -EINVAL;
1081
1082 /* Start/Restart the auto-negotiation state machine */
1083 mutex_lock(&priv->an_mutex);
1084 priv->an_result = AMD_XGBE_AN_READY;
1085 priv->an_state = AMD_XGBE_AN_START;
1086 priv->kr_state = AMD_XGBE_RX_READY;
1087 priv->kx_state = AMD_XGBE_RX_READY;
1088 mutex_unlock(&priv->an_mutex);
1089
1090 queue_work(priv->an_workqueue, &priv->an_work);
1091
1092 return 0;
1093 }
1094
1095 static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
1096 {
1097 struct amd_xgbe_phy_priv *priv = phydev->priv;
1098 enum amd_xgbe_phy_an state;
1099
1100 mutex_lock(&priv->an_mutex);
1101 state = priv->an_result;
1102 mutex_unlock(&priv->an_mutex);
1103
1104 return (state == AMD_XGBE_AN_COMPLETE);
1105 }
1106
1107 static int amd_xgbe_phy_update_link(struct phy_device *phydev)
1108 {
1109 struct amd_xgbe_phy_priv *priv = phydev->priv;
1110 enum amd_xgbe_phy_an state;
1111 unsigned int check_again, autoneg;
1112 int ret;
1113
1114 /* If we're doing auto-negotiation don't report link down */
1115 mutex_lock(&priv->an_mutex);
1116 state = priv->an_state;
1117 mutex_unlock(&priv->an_mutex);
1118
1119 if (state != AMD_XGBE_AN_READY) {
1120 phydev->link = 1;
1121 return 0;
1122 }
1123
1124 /* Since the device can be in the wrong mode when a link is
1125 * (re-)established (cable connected after the interface is
1126 * up, etc.), the link status may report no link. If there
1127 * is no link, try switching modes and checking the status
1128 * again if auto negotiation is enabled.
1129 */
1130 check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0;
1131 again:
1132 /* Link status is latched low, so read once to clear
1133 * and then read again to get current state
1134 */
1135 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1136 if (ret < 0)
1137 return ret;
1138
1139 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
1140 if (ret < 0)
1141 return ret;
1142
1143 phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
1144
1145 if (!phydev->link) {
1146 if (check_again) {
1147 ret = amd_xgbe_phy_switch_mode(phydev);
1148 if (ret < 0)
1149 return ret;
1150 check_again = 0;
1151 goto again;
1152 }
1153 }
1154
1155 autoneg = (phydev->link && !priv->link) ? 1 : 0;
1156 priv->link = phydev->link;
1157 if (autoneg) {
1158 /* Link is (back) up, re-start auto-negotiation */
1159 ret = amd_xgbe_phy_config_aneg(phydev);
1160 if (ret < 0)
1161 return ret;
1162 }
1163
1164 return 0;
1165 }
1166
1167 static int amd_xgbe_phy_read_status(struct phy_device *phydev)
1168 {
1169 struct amd_xgbe_phy_priv *priv = phydev->priv;
1170 u32 mmd_mask = phydev->c45_ids.devices_in_package;
1171 int ret, ad_ret, lp_ret;
1172
1173 ret = amd_xgbe_phy_update_link(phydev);
1174 if (ret)
1175 return ret;
1176
1177 if ((phydev->autoneg == AUTONEG_ENABLE) &&
1178 !priv->parallel_detect) {
1179 if (!(mmd_mask & MDIO_DEVS_AN))
1180 return -EINVAL;
1181
1182 if (!amd_xgbe_phy_aneg_done(phydev))
1183 return 0;
1184
1185 /* Compare Advertisement and Link Partner register 1 */
1186 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
1187 if (ad_ret < 0)
1188 return ad_ret;
1189 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
1190 if (lp_ret < 0)
1191 return lp_ret;
1192
1193 ad_ret &= lp_ret;
1194 phydev->pause = (ad_ret & 0x400) ? 1 : 0;
1195 phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
1196
1197 /* Compare Advertisement and Link Partner register 2 */
1198 ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
1199 MDIO_AN_ADVERTISE + 1);
1200 if (ad_ret < 0)
1201 return ad_ret;
1202 lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
1203 if (lp_ret < 0)
1204 return lp_ret;
1205
1206 ad_ret &= lp_ret;
1207 if (ad_ret & 0x80) {
1208 phydev->speed = SPEED_10000;
1209 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
1210 if (ret)
1211 return ret;
1212 } else {
1213 switch (priv->speed_set) {
1214 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1215 phydev->speed = SPEED_1000;
1216 break;
1217
1218 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1219 phydev->speed = SPEED_2500;
1220 break;
1221 }
1222
1223 ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
1224 if (ret)
1225 return ret;
1226 }
1227
1228 phydev->duplex = DUPLEX_FULL;
1229 } else {
1230 if (amd_xgbe_phy_in_kr_mode(phydev)) {
1231 phydev->speed = SPEED_10000;
1232 } else {
1233 switch (priv->speed_set) {
1234 case AMD_XGBE_PHY_SPEEDSET_1000_10000:
1235 phydev->speed = SPEED_1000;
1236 break;
1237
1238 case AMD_XGBE_PHY_SPEEDSET_2500_10000:
1239 phydev->speed = SPEED_2500;
1240 break;
1241 }
1242 }
1243 phydev->duplex = DUPLEX_FULL;
1244 phydev->pause = 0;
1245 phydev->asym_pause = 0;
1246 }
1247
1248 return 0;
1249 }
1250
1251 static int amd_xgbe_phy_suspend(struct phy_device *phydev)
1252 {
1253 int ret;
1254
1255 mutex_lock(&phydev->lock);
1256
1257 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1258 if (ret < 0)
1259 goto unlock;
1260
1261 ret |= MDIO_CTRL1_LPOWER;
1262 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1263
1264 ret = 0;
1265
1266 unlock:
1267 mutex_unlock(&phydev->lock);
1268
1269 return ret;
1270 }
1271
1272 static int amd_xgbe_phy_resume(struct phy_device *phydev)
1273 {
1274 int ret;
1275
1276 mutex_lock(&phydev->lock);
1277
1278 ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
1279 if (ret < 0)
1280 goto unlock;
1281
1282 ret &= ~MDIO_CTRL1_LPOWER;
1283 phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
1284
1285 ret = 0;
1286
1287 unlock:
1288 mutex_unlock(&phydev->lock);
1289
1290 return ret;
1291 }
1292
1293 static int amd_xgbe_phy_probe(struct phy_device *phydev)
1294 {
1295 struct amd_xgbe_phy_priv *priv;
1296 struct platform_device *pdev;
1297 struct device *dev;
1298 char *wq_name;
1299 const __be32 *property;
1300 unsigned int speed_set;
1301 int ret;
1302
1303 if (!phydev->dev.of_node)
1304 return -EINVAL;
1305
1306 pdev = of_find_device_by_node(phydev->dev.of_node);
1307 if (!pdev)
1308 return -EINVAL;
1309 dev = &pdev->dev;
1310
1311 wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
1312 if (!wq_name) {
1313 ret = -ENOMEM;
1314 goto err_pdev;
1315 }
1316
1317 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1318 if (!priv) {
1319 ret = -ENOMEM;
1320 goto err_name;
1321 }
1322
1323 priv->pdev = pdev;
1324 priv->dev = dev;
1325 priv->phydev = phydev;
1326
1327 /* Get the device mmio areas */
1328 priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1329 priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
1330 if (IS_ERR(priv->rxtx_regs)) {
1331 dev_err(dev, "rxtx ioremap failed\n");
1332 ret = PTR_ERR(priv->rxtx_regs);
1333 goto err_priv;
1334 }
1335
1336 priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1337 priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
1338 if (IS_ERR(priv->sir0_regs)) {
1339 dev_err(dev, "sir0 ioremap failed\n");
1340 ret = PTR_ERR(priv->sir0_regs);
1341 goto err_rxtx;
1342 }
1343
1344 priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
1345 priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
1346 if (IS_ERR(priv->sir1_regs)) {
1347 dev_err(dev, "sir1 ioremap failed\n");
1348 ret = PTR_ERR(priv->sir1_regs);
1349 goto err_sir0;
1350 }
1351
1352 /* Get the device speed set property */
1353 speed_set = 0;
1354 property = of_get_property(dev->of_node, XGBE_PHY_SPEEDSET_PROPERTY,
1355 NULL);
1356 if (property)
1357 speed_set = be32_to_cpu(*property);
1358
1359 switch (speed_set) {
1360 case 0:
1361 priv->speed_set = AMD_XGBE_PHY_SPEEDSET_1000_10000;
1362 break;
1363 case 1:
1364 priv->speed_set = AMD_XGBE_PHY_SPEEDSET_2500_10000;
1365 break;
1366 default:
1367 dev_err(dev, "invalid amd,speed-set property\n");
1368 ret = -EINVAL;
1369 goto err_sir1;
1370 }
1371
1372 priv->link = 1;
1373
1374 mutex_init(&priv->an_mutex);
1375 INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
1376 priv->an_workqueue = create_singlethread_workqueue(wq_name);
1377 if (!priv->an_workqueue) {
1378 ret = -ENOMEM;
1379 goto err_sir1;
1380 }
1381
1382 phydev->priv = priv;
1383
1384 kfree(wq_name);
1385 of_dev_put(pdev);
1386
1387 return 0;
1388
1389 err_sir1:
1390 devm_iounmap(dev, priv->sir1_regs);
1391 devm_release_mem_region(dev, priv->sir1_res->start,
1392 resource_size(priv->sir1_res));
1393
1394 err_sir0:
1395 devm_iounmap(dev, priv->sir0_regs);
1396 devm_release_mem_region(dev, priv->sir0_res->start,
1397 resource_size(priv->sir0_res));
1398
1399 err_rxtx:
1400 devm_iounmap(dev, priv->rxtx_regs);
1401 devm_release_mem_region(dev, priv->rxtx_res->start,
1402 resource_size(priv->rxtx_res));
1403
1404 err_priv:
1405 devm_kfree(dev, priv);
1406
1407 err_name:
1408 kfree(wq_name);
1409
1410 err_pdev:
1411 of_dev_put(pdev);
1412
1413 return ret;
1414 }
1415
1416 static void amd_xgbe_phy_remove(struct phy_device *phydev)
1417 {
1418 struct amd_xgbe_phy_priv *priv = phydev->priv;
1419 struct device *dev = priv->dev;
1420
1421 /* Stop any in process auto-negotiation */
1422 mutex_lock(&priv->an_mutex);
1423 priv->an_state = AMD_XGBE_AN_EXIT;
1424 mutex_unlock(&priv->an_mutex);
1425
1426 flush_workqueue(priv->an_workqueue);
1427 destroy_workqueue(priv->an_workqueue);
1428
1429 /* Release resources */
1430 devm_iounmap(dev, priv->sir1_regs);
1431 devm_release_mem_region(dev, priv->sir1_res->start,
1432 resource_size(priv->sir1_res));
1433
1434 devm_iounmap(dev, priv->sir0_regs);
1435 devm_release_mem_region(dev, priv->sir0_res->start,
1436 resource_size(priv->sir0_res));
1437
1438 devm_iounmap(dev, priv->rxtx_regs);
1439 devm_release_mem_region(dev, priv->rxtx_res->start,
1440 resource_size(priv->rxtx_res));
1441
1442 devm_kfree(dev, priv);
1443 }
1444
1445 static int amd_xgbe_match_phy_device(struct phy_device *phydev)
1446 {
1447 return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
1448 }
1449
1450 static struct phy_driver amd_xgbe_phy_driver[] = {
1451 {
1452 .phy_id = XGBE_PHY_ID,
1453 .phy_id_mask = XGBE_PHY_MASK,
1454 .name = "AMD XGBE PHY",
1455 .features = 0,
1456 .probe = amd_xgbe_phy_probe,
1457 .remove = amd_xgbe_phy_remove,
1458 .soft_reset = amd_xgbe_phy_soft_reset,
1459 .config_init = amd_xgbe_phy_config_init,
1460 .suspend = amd_xgbe_phy_suspend,
1461 .resume = amd_xgbe_phy_resume,
1462 .config_aneg = amd_xgbe_phy_config_aneg,
1463 .aneg_done = amd_xgbe_phy_aneg_done,
1464 .read_status = amd_xgbe_phy_read_status,
1465 .match_phy_device = amd_xgbe_match_phy_device,
1466 .driver = {
1467 .owner = THIS_MODULE,
1468 },
1469 },
1470 };
1471
1472 module_phy_driver(amd_xgbe_phy_driver);
1473
1474 static struct mdio_device_id __maybe_unused amd_xgbe_phy_ids[] = {
1475 { XGBE_PHY_ID, XGBE_PHY_MASK },
1476 { }
1477 };
1478 MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_ids);
Linux kernel - Deliverables
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