2 * Broadcom BCM7xxx internal transceivers support.
4 * Copyright (C) 2014, Broadcom Corporation
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/module.h>
13 #include <linux/phy.h>
14 #include <linux/delay.h>
15 #include <linux/bitops.h>
16 #include <linux/brcmphy.h>
17 #include <linux/mdio.h>
19 /* Broadcom BCM7xxx internal PHY registers */
20 #define MII_BCM7XXX_CHANNEL_WIDTH 0x2000
22 /* 40nm only register definitions */
23 #define MII_BCM7XXX_100TX_AUX_CTL 0x10
24 #define MII_BCM7XXX_100TX_FALSE_CAR 0x13
25 #define MII_BCM7XXX_100TX_DISC 0x14
26 #define MII_BCM7XXX_AUX_MODE 0x1d
27 #define MII_BCM7XX_64CLK_MDIO BIT(12)
28 #define MII_BCM7XXX_CORE_BASE1E 0x1e
29 #define MII_BCM7XXX_TEST 0x1f
30 #define MII_BCM7XXX_SHD_MODE_2 BIT(2)
32 /* 28nm only register definitions */
33 #define MISC_ADDR(base, channel) base, channel
35 #define DSP_TAP10 MISC_ADDR(0x0a, 0)
36 #define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
37 #define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
38 #define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
40 #define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
41 #define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
42 #define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
43 #define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
44 #define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
46 #define CORE_EXPB0 0xb0
48 static int bcm7445_config_init(struct phy_device
*phydev
)
51 const struct bcm7445_regs
{
54 } bcm7445_regs_cfg
[] = {
55 /* increases ADC latency by 24ns */
56 { MII_BCM54XX_EXP_SEL
, 0x0038 },
57 { MII_BCM54XX_EXP_DATA
, 0xAB95 },
58 /* increases internal 1V LDO voltage by 5% */
59 { MII_BCM54XX_EXP_SEL
, 0x2038 },
60 { MII_BCM54XX_EXP_DATA
, 0xBB22 },
61 /* reduce RX low pass filter corner frequency */
62 { MII_BCM54XX_EXP_SEL
, 0x6038 },
63 { MII_BCM54XX_EXP_DATA
, 0xFFC5 },
64 /* reduce RX high pass filter corner frequency */
65 { MII_BCM54XX_EXP_SEL
, 0x003a },
66 { MII_BCM54XX_EXP_DATA
, 0x2002 },
70 for (i
= 0; i
< ARRAY_SIZE(bcm7445_regs_cfg
); i
++) {
71 ret
= phy_write(phydev
,
72 bcm7445_regs_cfg
[i
].reg
,
73 bcm7445_regs_cfg
[i
].value
);
81 static void phy_write_exp(struct phy_device
*phydev
,
84 phy_write(phydev
, MII_BCM54XX_EXP_SEL
, MII_BCM54XX_EXP_SEL_ER
| reg
);
85 phy_write(phydev
, MII_BCM54XX_EXP_DATA
, value
);
88 static void phy_write_misc(struct phy_device
*phydev
,
89 u16 reg
, u16 chl
, u16 value
)
93 phy_write(phydev
, MII_BCM54XX_AUX_CTL
, MII_BCM54XX_AUXCTL_SHDWSEL_MISC
);
95 tmp
= phy_read(phydev
, MII_BCM54XX_AUX_CTL
);
96 tmp
|= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA
;
97 phy_write(phydev
, MII_BCM54XX_AUX_CTL
, tmp
);
99 tmp
= (chl
* MII_BCM7XXX_CHANNEL_WIDTH
) | reg
;
100 phy_write(phydev
, MII_BCM54XX_EXP_SEL
, tmp
);
102 phy_write(phydev
, MII_BCM54XX_EXP_DATA
, value
);
105 static int bcm7xxx_28nm_afe_config_init(struct phy_device
*phydev
)
107 /* Increase VCO range to prevent unlocking problem of PLL at low
110 phy_write_misc(phydev
, PLL_PLLCTRL_1
, 0x0048);
112 /* Change Ki to 011 */
113 phy_write_misc(phydev
, PLL_PLLCTRL_2
, 0x021b);
115 /* Disable loading of TVCO buffer to bandgap, set bandgap trim
118 phy_write_misc(phydev
, PLL_PLLCTRL_4
, 0x0e20);
120 /* Adjust bias current trim by -3 */
121 phy_write_misc(phydev
, DSP_TAP10
, 0x690b);
123 /* Switch to CORE_BASE1E */
124 phy_write(phydev
, MII_BCM7XXX_CORE_BASE1E
, 0xd);
126 /* Reset R_CAL/RC_CAL Engine */
127 phy_write_exp(phydev
, CORE_EXPB0
, 0x0010);
129 /* Disable Reset R_CAL/RC_CAL Engine */
130 phy_write_exp(phydev
, CORE_EXPB0
, 0x0000);
132 /* write AFE_RXCONFIG_0 */
133 phy_write_misc(phydev
, AFE_RXCONFIG_0
, 0xeb19);
135 /* write AFE_RXCONFIG_1 */
136 phy_write_misc(phydev
, AFE_RXCONFIG_1
, 0x9a3f);
138 /* write AFE_RX_LP_COUNTER */
139 phy_write_misc(phydev
, AFE_RX_LP_COUNTER
, 0x7fc0);
141 /* write AFE_HPF_TRIM_OTHERS */
142 phy_write_misc(phydev
, AFE_HPF_TRIM_OTHERS
, 0x000b);
144 /* write AFTE_TX_CONFIG */
145 phy_write_misc(phydev
, AFE_TX_CONFIG
, 0x0800);
150 static int bcm7xxx_apd_enable(struct phy_device
*phydev
)
154 /* Enable powering down of the DLL during auto-power down */
155 val
= bcm54xx_shadow_read(phydev
, BCM54XX_SHD_SCR3
);
159 val
|= BCM54XX_SHD_SCR3_DLLAPD_DIS
;
160 bcm54xx_shadow_write(phydev
, BCM54XX_SHD_SCR3
, val
);
162 /* Enable auto-power down */
163 val
= bcm54xx_shadow_read(phydev
, BCM54XX_SHD_APD
);
167 val
|= BCM54XX_SHD_APD_EN
;
168 return bcm54xx_shadow_write(phydev
, BCM54XX_SHD_APD
, val
);
171 static int bcm7xxx_eee_enable(struct phy_device
*phydev
)
175 val
= phy_read_mmd_indirect(phydev
, BRCM_CL45VEN_EEE_CONTROL
,
176 MDIO_MMD_AN
, phydev
->addr
);
180 /* Enable general EEE feature at the PHY level */
181 val
|= LPI_FEATURE_EN
| LPI_FEATURE_EN_DIG1000X
;
183 phy_write_mmd_indirect(phydev
, BRCM_CL45VEN_EEE_CONTROL
,
184 MDIO_MMD_AN
, phydev
->addr
, val
);
186 /* Advertise supported modes */
187 val
= phy_read_mmd_indirect(phydev
, MDIO_AN_EEE_ADV
,
188 MDIO_MMD_AN
, phydev
->addr
);
190 val
|= (MDIO_AN_EEE_ADV_100TX
| MDIO_AN_EEE_ADV_1000T
);
191 phy_write_mmd_indirect(phydev
, MDIO_AN_EEE_ADV
,
192 MDIO_MMD_AN
, phydev
->addr
, val
);
197 static int bcm7xxx_28nm_config_init(struct phy_device
*phydev
)
201 ret
= bcm7445_config_init(phydev
);
205 ret
= bcm7xxx_28nm_afe_config_init(phydev
);
209 ret
= bcm7xxx_eee_enable(phydev
);
213 return bcm7xxx_apd_enable(phydev
);
216 static int bcm7xxx_28nm_resume(struct phy_device
*phydev
)
220 /* Re-apply workarounds coming out suspend/resume */
221 ret
= bcm7xxx_28nm_config_init(phydev
);
225 /* 28nm Gigabit PHYs come out of reset without any half-duplex
226 * or "hub" compliant advertised mode, fix that. This does not
227 * cause any problems with the PHY library since genphy_config_aneg()
228 * gracefully handles auto-negotiated and forced modes.
230 return genphy_config_aneg(phydev
);
233 static int phy_set_clr_bits(struct phy_device
*dev
, int location
,
234 int set_mask
, int clr_mask
)
238 v
= phy_read(dev
, location
);
245 ret
= phy_write(dev
, location
, v
);
252 static int bcm7xxx_config_init(struct phy_device
*phydev
)
256 /* Enable 64 clock MDIO */
257 phy_write(phydev
, MII_BCM7XXX_AUX_MODE
, MII_BCM7XX_64CLK_MDIO
);
258 phy_read(phydev
, MII_BCM7XXX_AUX_MODE
);
260 /* Workaround only required for 100Mbits/sec */
261 if (!(phydev
->dev_flags
& PHY_BRCM_100MBPS_WAR
))
264 /* set shadow mode 2 */
265 ret
= phy_set_clr_bits(phydev
, MII_BCM7XXX_TEST
,
266 MII_BCM7XXX_SHD_MODE_2
, MII_BCM7XXX_SHD_MODE_2
);
270 /* set iddq_clkbias */
271 phy_write(phydev
, MII_BCM7XXX_100TX_DISC
, 0x0F00);
274 /* reset iddq_clkbias */
275 phy_write(phydev
, MII_BCM7XXX_100TX_DISC
, 0x0C00);
277 phy_write(phydev
, MII_BCM7XXX_100TX_FALSE_CAR
, 0x7555);
279 /* reset shadow mode 2 */
280 ret
= phy_set_clr_bits(phydev
, MII_BCM7XXX_TEST
, MII_BCM7XXX_SHD_MODE_2
, 0);
287 /* Workaround for putting the PHY in IDDQ mode, required
288 * for all BCM7XXX 40nm and 65nm PHYs
290 static int bcm7xxx_suspend(struct phy_device
*phydev
)
293 const struct bcm7xxx_regs
{
296 } bcm7xxx_suspend_cfg
[] = {
297 { MII_BCM7XXX_TEST
, 0x008b },
298 { MII_BCM7XXX_100TX_AUX_CTL
, 0x01c0 },
299 { MII_BCM7XXX_100TX_DISC
, 0x7000 },
300 { MII_BCM7XXX_TEST
, 0x000f },
301 { MII_BCM7XXX_100TX_AUX_CTL
, 0x20d0 },
302 { MII_BCM7XXX_TEST
, 0x000b },
306 for (i
= 0; i
< ARRAY_SIZE(bcm7xxx_suspend_cfg
); i
++) {
307 ret
= phy_write(phydev
,
308 bcm7xxx_suspend_cfg
[i
].reg
,
309 bcm7xxx_suspend_cfg
[i
].value
);
317 static int bcm7xxx_dummy_config_init(struct phy_device
*phydev
)
322 #define BCM7XXX_28NM_GPHY(_oui, _name) \
325 .phy_id_mask = 0xfffffff0, \
327 .features = PHY_GBIT_FEATURES | \
328 SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
329 .flags = PHY_IS_INTERNAL, \
330 .config_init = bcm7xxx_28nm_afe_config_init, \
331 .config_aneg = genphy_config_aneg, \
332 .read_status = genphy_read_status, \
333 .resume = bcm7xxx_28nm_resume, \
334 .driver = { .owner = THIS_MODULE }, \
337 static struct phy_driver bcm7xxx_driver
[] = {
338 BCM7XXX_28NM_GPHY(PHY_ID_BCM7366
, "Broadcom BCM7366"),
339 BCM7XXX_28NM_GPHY(PHY_ID_BCM7439
, "Broadcom BCM7439"),
340 BCM7XXX_28NM_GPHY(PHY_ID_BCM7445
, "Broadcom BCM7445"),
342 .phy_id
= PHY_BCM_OUI_4
,
343 .phy_id_mask
= 0xffff0000,
344 .name
= "Broadcom BCM7XXX 40nm",
345 .features
= PHY_GBIT_FEATURES
|
346 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
,
347 .flags
= PHY_IS_INTERNAL
,
348 .config_init
= bcm7xxx_config_init
,
349 .config_aneg
= genphy_config_aneg
,
350 .read_status
= genphy_read_status
,
351 .suspend
= bcm7xxx_suspend
,
352 .resume
= bcm7xxx_config_init
,
353 .driver
= { .owner
= THIS_MODULE
},
355 .phy_id
= PHY_BCM_OUI_5
,
356 .phy_id_mask
= 0xffffff00,
357 .name
= "Broadcom BCM7XXX 65nm",
358 .features
= PHY_BASIC_FEATURES
|
359 SUPPORTED_Pause
| SUPPORTED_Asym_Pause
,
360 .flags
= PHY_IS_INTERNAL
,
361 .config_init
= bcm7xxx_dummy_config_init
,
362 .config_aneg
= genphy_config_aneg
,
363 .read_status
= genphy_read_status
,
364 .suspend
= bcm7xxx_suspend
,
365 .resume
= bcm7xxx_config_init
,
366 .driver
= { .owner
= THIS_MODULE
},
369 static struct mdio_device_id __maybe_unused bcm7xxx_tbl
[] = {
370 { PHY_ID_BCM7366
, 0xfffffff0, },
371 { PHY_ID_BCM7439
, 0xfffffff0, },
372 { PHY_ID_BCM7445
, 0xfffffff0, },
373 { PHY_BCM_OUI_4
, 0xffff0000 },
374 { PHY_BCM_OUI_5
, 0xffffff00 },
378 static int __init
bcm7xxx_phy_init(void)
380 return phy_drivers_register(bcm7xxx_driver
,
381 ARRAY_SIZE(bcm7xxx_driver
));
384 static void __exit
bcm7xxx_phy_exit(void)
386 phy_drivers_unregister(bcm7xxx_driver
,
387 ARRAY_SIZE(bcm7xxx_driver
));
390 module_init(bcm7xxx_phy_init
);
391 module_exit(bcm7xxx_phy_exit
);
393 MODULE_DEVICE_TABLE(mdio
, bcm7xxx_tbl
);
395 MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
396 MODULE_LICENSE("GPL");
397 MODULE_AUTHOR("Broadcom Corporation");