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Merge branch 'for-linus-for-3.6-rc1' of git://git.linaro.org/people/mszyprowski/linux...
[deliverable/linux.git] / drivers / net / phy / dp83640.c
1 /*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23 #include <linux/ethtool.h>
24 #include <linux/kernel.h>
25 #include <linux/list.h>
26 #include <linux/mii.h>
27 #include <linux/module.h>
28 #include <linux/net_tstamp.h>
29 #include <linux/netdevice.h>
30 #include <linux/phy.h>
31 #include <linux/ptp_classify.h>
32 #include <linux/ptp_clock_kernel.h>
33
34 #include "dp83640_reg.h"
35
36 #define DP83640_PHY_ID 0x20005ce1
37 #define PAGESEL 0x13
38 #define LAYER4 0x02
39 #define LAYER2 0x01
40 #define MAX_RXTS 64
41 #define N_EXT_TS 6
42 #define PSF_PTPVER 2
43 #define PSF_EVNT 0x4000
44 #define PSF_RX 0x2000
45 #define PSF_TX 0x1000
46 #define EXT_EVENT 1
47 #define CAL_EVENT 7
48 #define CAL_TRIGGER 7
49 #define PER_TRIGGER 6
50
51 /* phyter seems to miss the mark by 16 ns */
52 #define ADJTIME_FIX 16
53
54 #if defined(__BIG_ENDIAN)
55 #define ENDIAN_FLAG 0
56 #elif defined(__LITTLE_ENDIAN)
57 #define ENDIAN_FLAG PSF_ENDIAN
58 #endif
59
60 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
61
62 struct phy_rxts {
63 u16 ns_lo; /* ns[15:0] */
64 u16 ns_hi; /* overflow[1:0], ns[29:16] */
65 u16 sec_lo; /* sec[15:0] */
66 u16 sec_hi; /* sec[31:16] */
67 u16 seqid; /* sequenceId[15:0] */
68 u16 msgtype; /* messageType[3:0], hash[11:0] */
69 };
70
71 struct phy_txts {
72 u16 ns_lo; /* ns[15:0] */
73 u16 ns_hi; /* overflow[1:0], ns[29:16] */
74 u16 sec_lo; /* sec[15:0] */
75 u16 sec_hi; /* sec[31:16] */
76 };
77
78 struct rxts {
79 struct list_head list;
80 unsigned long tmo;
81 u64 ns;
82 u16 seqid;
83 u8 msgtype;
84 u16 hash;
85 };
86
87 struct dp83640_clock;
88
89 struct dp83640_private {
90 struct list_head list;
91 struct dp83640_clock *clock;
92 struct phy_device *phydev;
93 struct work_struct ts_work;
94 int hwts_tx_en;
95 int hwts_rx_en;
96 int layer;
97 int version;
98 /* remember state of cfg0 during calibration */
99 int cfg0;
100 /* remember the last event time stamp */
101 struct phy_txts edata;
102 /* list of rx timestamps */
103 struct list_head rxts;
104 struct list_head rxpool;
105 struct rxts rx_pool_data[MAX_RXTS];
106 /* protects above three fields from concurrent access */
107 spinlock_t rx_lock;
108 /* queues of incoming and outgoing packets */
109 struct sk_buff_head rx_queue;
110 struct sk_buff_head tx_queue;
111 };
112
113 struct dp83640_clock {
114 /* keeps the instance in the 'phyter_clocks' list */
115 struct list_head list;
116 /* we create one clock instance per MII bus */
117 struct mii_bus *bus;
118 /* protects extended registers from concurrent access */
119 struct mutex extreg_lock;
120 /* remembers which page was last selected */
121 int page;
122 /* our advertised capabilities */
123 struct ptp_clock_info caps;
124 /* protects the three fields below from concurrent access */
125 struct mutex clock_lock;
126 /* the one phyter from which we shall read */
127 struct dp83640_private *chosen;
128 /* list of the other attached phyters, not chosen */
129 struct list_head phylist;
130 /* reference to our PTP hardware clock */
131 struct ptp_clock *ptp_clock;
132 };
133
134 /* globals */
135
136 enum {
137 CALIBRATE_GPIO,
138 PEROUT_GPIO,
139 EXTTS0_GPIO,
140 EXTTS1_GPIO,
141 EXTTS2_GPIO,
142 EXTTS3_GPIO,
143 EXTTS4_GPIO,
144 EXTTS5_GPIO,
145 GPIO_TABLE_SIZE
146 };
147
148 static int chosen_phy = -1;
149 static ushort gpio_tab[GPIO_TABLE_SIZE] = {
150 1, 2, 3, 4, 8, 9, 10, 11
151 };
152
153 module_param(chosen_phy, int, 0444);
154 module_param_array(gpio_tab, ushort, NULL, 0444);
155
156 MODULE_PARM_DESC(chosen_phy, \
157 "The address of the PHY to use for the ancillary clock features");
158 MODULE_PARM_DESC(gpio_tab, \
159 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
160
161 /* a list of clocks and a mutex to protect it */
162 static LIST_HEAD(phyter_clocks);
163 static DEFINE_MUTEX(phyter_clocks_lock);
164
165 static void rx_timestamp_work(struct work_struct *work);
166
167 /* extended register access functions */
168
169 #define BROADCAST_ADDR 31
170
171 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
172 {
173 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
174 }
175
176 /* Caller must hold extreg_lock. */
177 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
178 {
179 struct dp83640_private *dp83640 = phydev->priv;
180 int val;
181
182 if (dp83640->clock->page != page) {
183 broadcast_write(phydev->bus, PAGESEL, page);
184 dp83640->clock->page = page;
185 }
186 val = phy_read(phydev, regnum);
187
188 return val;
189 }
190
191 /* Caller must hold extreg_lock. */
192 static void ext_write(int broadcast, struct phy_device *phydev,
193 int page, u32 regnum, u16 val)
194 {
195 struct dp83640_private *dp83640 = phydev->priv;
196
197 if (dp83640->clock->page != page) {
198 broadcast_write(phydev->bus, PAGESEL, page);
199 dp83640->clock->page = page;
200 }
201 if (broadcast)
202 broadcast_write(phydev->bus, regnum, val);
203 else
204 phy_write(phydev, regnum, val);
205 }
206
207 /* Caller must hold extreg_lock. */
208 static int tdr_write(int bc, struct phy_device *dev,
209 const struct timespec *ts, u16 cmd)
210 {
211 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
212 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
213 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
214 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
215
216 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
217
218 return 0;
219 }
220
221 /* convert phy timestamps into driver timestamps */
222
223 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
224 {
225 u32 sec;
226
227 sec = p->sec_lo;
228 sec |= p->sec_hi << 16;
229
230 rxts->ns = p->ns_lo;
231 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
232 rxts->ns += ((u64)sec) * 1000000000ULL;
233 rxts->seqid = p->seqid;
234 rxts->msgtype = (p->msgtype >> 12) & 0xf;
235 rxts->hash = p->msgtype & 0x0fff;
236 rxts->tmo = jiffies + 2;
237 }
238
239 static u64 phy2txts(struct phy_txts *p)
240 {
241 u64 ns;
242 u32 sec;
243
244 sec = p->sec_lo;
245 sec |= p->sec_hi << 16;
246
247 ns = p->ns_lo;
248 ns |= (p->ns_hi & 0x3fff) << 16;
249 ns += ((u64)sec) * 1000000000ULL;
250
251 return ns;
252 }
253
254 static void periodic_output(struct dp83640_clock *clock,
255 struct ptp_clock_request *clkreq, bool on)
256 {
257 struct dp83640_private *dp83640 = clock->chosen;
258 struct phy_device *phydev = dp83640->phydev;
259 u32 sec, nsec, period;
260 u16 gpio, ptp_trig, trigger, val;
261
262 gpio = on ? gpio_tab[PEROUT_GPIO] : 0;
263 trigger = PER_TRIGGER;
264
265 ptp_trig = TRIG_WR |
266 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
267 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
268 TRIG_PER |
269 TRIG_PULSE;
270
271 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
272
273 if (!on) {
274 val |= TRIG_DIS;
275 mutex_lock(&clock->extreg_lock);
276 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
277 ext_write(0, phydev, PAGE4, PTP_CTL, val);
278 mutex_unlock(&clock->extreg_lock);
279 return;
280 }
281
282 sec = clkreq->perout.start.sec;
283 nsec = clkreq->perout.start.nsec;
284 period = clkreq->perout.period.sec * 1000000000UL;
285 period += clkreq->perout.period.nsec;
286
287 mutex_lock(&clock->extreg_lock);
288
289 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
290
291 /*load trigger*/
292 val |= TRIG_LOAD;
293 ext_write(0, phydev, PAGE4, PTP_CTL, val);
294 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
295 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
296 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
297 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
298 ext_write(0, phydev, PAGE4, PTP_TDR, period & 0xffff); /* ns[15:0] */
299 ext_write(0, phydev, PAGE4, PTP_TDR, period >> 16); /* ns[31:16] */
300
301 /*enable trigger*/
302 val &= ~TRIG_LOAD;
303 val |= TRIG_EN;
304 ext_write(0, phydev, PAGE4, PTP_CTL, val);
305
306 mutex_unlock(&clock->extreg_lock);
307 }
308
309 /* ptp clock methods */
310
311 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
312 {
313 struct dp83640_clock *clock =
314 container_of(ptp, struct dp83640_clock, caps);
315 struct phy_device *phydev = clock->chosen->phydev;
316 u64 rate;
317 int neg_adj = 0;
318 u16 hi, lo;
319
320 if (ppb < 0) {
321 neg_adj = 1;
322 ppb = -ppb;
323 }
324 rate = ppb;
325 rate <<= 26;
326 rate = div_u64(rate, 1953125);
327
328 hi = (rate >> 16) & PTP_RATE_HI_MASK;
329 if (neg_adj)
330 hi |= PTP_RATE_DIR;
331
332 lo = rate & 0xffff;
333
334 mutex_lock(&clock->extreg_lock);
335
336 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
337 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
338
339 mutex_unlock(&clock->extreg_lock);
340
341 return 0;
342 }
343
344 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
345 {
346 struct dp83640_clock *clock =
347 container_of(ptp, struct dp83640_clock, caps);
348 struct phy_device *phydev = clock->chosen->phydev;
349 struct timespec ts;
350 int err;
351
352 delta += ADJTIME_FIX;
353
354 ts = ns_to_timespec(delta);
355
356 mutex_lock(&clock->extreg_lock);
357
358 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
359
360 mutex_unlock(&clock->extreg_lock);
361
362 return err;
363 }
364
365 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
366 {
367 struct dp83640_clock *clock =
368 container_of(ptp, struct dp83640_clock, caps);
369 struct phy_device *phydev = clock->chosen->phydev;
370 unsigned int val[4];
371
372 mutex_lock(&clock->extreg_lock);
373
374 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
375
376 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
377 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
378 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
379 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
380
381 mutex_unlock(&clock->extreg_lock);
382
383 ts->tv_nsec = val[0] | (val[1] << 16);
384 ts->tv_sec = val[2] | (val[3] << 16);
385
386 return 0;
387 }
388
389 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
390 const struct timespec *ts)
391 {
392 struct dp83640_clock *clock =
393 container_of(ptp, struct dp83640_clock, caps);
394 struct phy_device *phydev = clock->chosen->phydev;
395 int err;
396
397 mutex_lock(&clock->extreg_lock);
398
399 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
400
401 mutex_unlock(&clock->extreg_lock);
402
403 return err;
404 }
405
406 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
407 struct ptp_clock_request *rq, int on)
408 {
409 struct dp83640_clock *clock =
410 container_of(ptp, struct dp83640_clock, caps);
411 struct phy_device *phydev = clock->chosen->phydev;
412 int index;
413 u16 evnt, event_num, gpio_num;
414
415 switch (rq->type) {
416 case PTP_CLK_REQ_EXTTS:
417 index = rq->extts.index;
418 if (index < 0 || index >= N_EXT_TS)
419 return -EINVAL;
420 event_num = EXT_EVENT + index;
421 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
422 if (on) {
423 gpio_num = gpio_tab[EXTTS0_GPIO + index];
424 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
425 evnt |= EVNT_RISE;
426 }
427 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
428 return 0;
429
430 case PTP_CLK_REQ_PEROUT:
431 if (rq->perout.index != 0)
432 return -EINVAL;
433 periodic_output(clock, rq, on);
434 return 0;
435
436 default:
437 break;
438 }
439
440 return -EOPNOTSUPP;
441 }
442
443 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
444 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
445
446 static void enable_status_frames(struct phy_device *phydev, bool on)
447 {
448 u16 cfg0 = 0, ver;
449
450 if (on)
451 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
452
453 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
454
455 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
456 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
457
458 if (!phydev->attached_dev) {
459 pr_warn("expected to find an attached netdevice\n");
460 return;
461 }
462
463 if (on) {
464 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
465 pr_warn("failed to add mc address\n");
466 } else {
467 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
468 pr_warn("failed to delete mc address\n");
469 }
470 }
471
472 static bool is_status_frame(struct sk_buff *skb, int type)
473 {
474 struct ethhdr *h = eth_hdr(skb);
475
476 if (PTP_CLASS_V2_L2 == type &&
477 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
478 return true;
479 else
480 return false;
481 }
482
483 static int expired(struct rxts *rxts)
484 {
485 return time_after(jiffies, rxts->tmo);
486 }
487
488 /* Caller must hold rx_lock. */
489 static void prune_rx_ts(struct dp83640_private *dp83640)
490 {
491 struct list_head *this, *next;
492 struct rxts *rxts;
493
494 list_for_each_safe(this, next, &dp83640->rxts) {
495 rxts = list_entry(this, struct rxts, list);
496 if (expired(rxts)) {
497 list_del_init(&rxts->list);
498 list_add(&rxts->list, &dp83640->rxpool);
499 }
500 }
501 }
502
503 /* synchronize the phyters so they act as one clock */
504
505 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
506 {
507 int val;
508 phy_write(phydev, PAGESEL, 0);
509 val = phy_read(phydev, PHYCR2);
510 if (on)
511 val |= BC_WRITE;
512 else
513 val &= ~BC_WRITE;
514 phy_write(phydev, PHYCR2, val);
515 phy_write(phydev, PAGESEL, init_page);
516 }
517
518 static void recalibrate(struct dp83640_clock *clock)
519 {
520 s64 now, diff;
521 struct phy_txts event_ts;
522 struct timespec ts;
523 struct list_head *this;
524 struct dp83640_private *tmp;
525 struct phy_device *master = clock->chosen->phydev;
526 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
527
528 trigger = CAL_TRIGGER;
529 cal_gpio = gpio_tab[CALIBRATE_GPIO];
530
531 mutex_lock(&clock->extreg_lock);
532
533 /*
534 * enable broadcast, disable status frames, enable ptp clock
535 */
536 list_for_each(this, &clock->phylist) {
537 tmp = list_entry(this, struct dp83640_private, list);
538 enable_broadcast(tmp->phydev, clock->page, 1);
539 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
540 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
541 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
542 }
543 enable_broadcast(master, clock->page, 1);
544 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
545 ext_write(0, master, PAGE5, PSF_CFG0, 0);
546 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
547
548 /*
549 * enable an event timestamp
550 */
551 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
552 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
553 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
554
555 list_for_each(this, &clock->phylist) {
556 tmp = list_entry(this, struct dp83640_private, list);
557 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
558 }
559 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
560
561 /*
562 * configure a trigger
563 */
564 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
565 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
566 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
567 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
568
569 /* load trigger */
570 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
571 val |= TRIG_LOAD;
572 ext_write(0, master, PAGE4, PTP_CTL, val);
573
574 /* enable trigger */
575 val &= ~TRIG_LOAD;
576 val |= TRIG_EN;
577 ext_write(0, master, PAGE4, PTP_CTL, val);
578
579 /* disable trigger */
580 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
581 val |= TRIG_DIS;
582 ext_write(0, master, PAGE4, PTP_CTL, val);
583
584 /*
585 * read out and correct offsets
586 */
587 val = ext_read(master, PAGE4, PTP_STS);
588 pr_info("master PTP_STS 0x%04hx\n", val);
589 val = ext_read(master, PAGE4, PTP_ESTS);
590 pr_info("master PTP_ESTS 0x%04hx\n", val);
591 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
592 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
593 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
594 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
595 now = phy2txts(&event_ts);
596
597 list_for_each(this, &clock->phylist) {
598 tmp = list_entry(this, struct dp83640_private, list);
599 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
600 pr_info("slave PTP_STS 0x%04hx\n", val);
601 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
602 pr_info("slave PTP_ESTS 0x%04hx\n", val);
603 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
604 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
605 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
606 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
607 diff = now - (s64) phy2txts(&event_ts);
608 pr_info("slave offset %lld nanoseconds\n", diff);
609 diff += ADJTIME_FIX;
610 ts = ns_to_timespec(diff);
611 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
612 }
613
614 /*
615 * restore status frames
616 */
617 list_for_each(this, &clock->phylist) {
618 tmp = list_entry(this, struct dp83640_private, list);
619 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
620 }
621 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
622
623 mutex_unlock(&clock->extreg_lock);
624 }
625
626 /* time stamping methods */
627
628 static inline u16 exts_chan_to_edata(int ch)
629 {
630 return 1 << ((ch + EXT_EVENT) * 2);
631 }
632
633 static int decode_evnt(struct dp83640_private *dp83640,
634 void *data, u16 ests)
635 {
636 struct phy_txts *phy_txts;
637 struct ptp_clock_event event;
638 int i, parsed;
639 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
640 u16 ext_status = 0;
641
642 if (ests & MULT_EVNT) {
643 ext_status = *(u16 *) data;
644 data += sizeof(ext_status);
645 }
646
647 phy_txts = data;
648
649 switch (words) { /* fall through in every case */
650 case 3:
651 dp83640->edata.sec_hi = phy_txts->sec_hi;
652 case 2:
653 dp83640->edata.sec_lo = phy_txts->sec_lo;
654 case 1:
655 dp83640->edata.ns_hi = phy_txts->ns_hi;
656 case 0:
657 dp83640->edata.ns_lo = phy_txts->ns_lo;
658 }
659
660 if (ext_status) {
661 parsed = words + 2;
662 } else {
663 parsed = words + 1;
664 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
665 ext_status = exts_chan_to_edata(i);
666 }
667
668 event.type = PTP_CLOCK_EXTTS;
669 event.timestamp = phy2txts(&dp83640->edata);
670
671 for (i = 0; i < N_EXT_TS; i++) {
672 if (ext_status & exts_chan_to_edata(i)) {
673 event.index = i;
674 ptp_clock_event(dp83640->clock->ptp_clock, &event);
675 }
676 }
677
678 return parsed * sizeof(u16);
679 }
680
681 static void decode_rxts(struct dp83640_private *dp83640,
682 struct phy_rxts *phy_rxts)
683 {
684 struct rxts *rxts;
685 unsigned long flags;
686
687 spin_lock_irqsave(&dp83640->rx_lock, flags);
688
689 prune_rx_ts(dp83640);
690
691 if (list_empty(&dp83640->rxpool)) {
692 pr_debug("rx timestamp pool is empty\n");
693 goto out;
694 }
695 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
696 list_del_init(&rxts->list);
697 phy2rxts(phy_rxts, rxts);
698 list_add_tail(&rxts->list, &dp83640->rxts);
699 out:
700 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
701 }
702
703 static void decode_txts(struct dp83640_private *dp83640,
704 struct phy_txts *phy_txts)
705 {
706 struct skb_shared_hwtstamps shhwtstamps;
707 struct sk_buff *skb;
708 u64 ns;
709
710 /* We must already have the skb that triggered this. */
711
712 skb = skb_dequeue(&dp83640->tx_queue);
713
714 if (!skb) {
715 pr_debug("have timestamp but tx_queue empty\n");
716 return;
717 }
718 ns = phy2txts(phy_txts);
719 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
720 shhwtstamps.hwtstamp = ns_to_ktime(ns);
721 skb_complete_tx_timestamp(skb, &shhwtstamps);
722 }
723
724 static void decode_status_frame(struct dp83640_private *dp83640,
725 struct sk_buff *skb)
726 {
727 struct phy_rxts *phy_rxts;
728 struct phy_txts *phy_txts;
729 u8 *ptr;
730 int len, size;
731 u16 ests, type;
732
733 ptr = skb->data + 2;
734
735 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
736
737 type = *(u16 *)ptr;
738 ests = type & 0x0fff;
739 type = type & 0xf000;
740 len -= sizeof(type);
741 ptr += sizeof(type);
742
743 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
744
745 phy_rxts = (struct phy_rxts *) ptr;
746 decode_rxts(dp83640, phy_rxts);
747 size = sizeof(*phy_rxts);
748
749 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
750
751 phy_txts = (struct phy_txts *) ptr;
752 decode_txts(dp83640, phy_txts);
753 size = sizeof(*phy_txts);
754
755 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
756
757 size = decode_evnt(dp83640, ptr, ests);
758
759 } else {
760 size = 0;
761 break;
762 }
763 ptr += size;
764 }
765 }
766
767 static int is_sync(struct sk_buff *skb, int type)
768 {
769 u8 *data = skb->data, *msgtype;
770 unsigned int offset = 0;
771
772 switch (type) {
773 case PTP_CLASS_V1_IPV4:
774 case PTP_CLASS_V2_IPV4:
775 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
776 break;
777 case PTP_CLASS_V1_IPV6:
778 case PTP_CLASS_V2_IPV6:
779 offset = OFF_PTP6;
780 break;
781 case PTP_CLASS_V2_L2:
782 offset = ETH_HLEN;
783 break;
784 case PTP_CLASS_V2_VLAN:
785 offset = ETH_HLEN + VLAN_HLEN;
786 break;
787 default:
788 return 0;
789 }
790
791 if (type & PTP_CLASS_V1)
792 offset += OFF_PTP_CONTROL;
793
794 if (skb->len < offset + 1)
795 return 0;
796
797 msgtype = data + offset;
798
799 return (*msgtype & 0xf) == 0;
800 }
801
802 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
803 {
804 u16 *seqid;
805 unsigned int offset;
806 u8 *msgtype, *data = skb_mac_header(skb);
807
808 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
809
810 switch (type) {
811 case PTP_CLASS_V1_IPV4:
812 case PTP_CLASS_V2_IPV4:
813 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
814 break;
815 case PTP_CLASS_V1_IPV6:
816 case PTP_CLASS_V2_IPV6:
817 offset = OFF_PTP6;
818 break;
819 case PTP_CLASS_V2_L2:
820 offset = ETH_HLEN;
821 break;
822 case PTP_CLASS_V2_VLAN:
823 offset = ETH_HLEN + VLAN_HLEN;
824 break;
825 default:
826 return 0;
827 }
828
829 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
830 return 0;
831
832 if (unlikely(type & PTP_CLASS_V1))
833 msgtype = data + offset + OFF_PTP_CONTROL;
834 else
835 msgtype = data + offset;
836
837 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
838
839 return (rxts->msgtype == (*msgtype & 0xf) &&
840 rxts->seqid == ntohs(*seqid));
841 }
842
843 static void dp83640_free_clocks(void)
844 {
845 struct dp83640_clock *clock;
846 struct list_head *this, *next;
847
848 mutex_lock(&phyter_clocks_lock);
849
850 list_for_each_safe(this, next, &phyter_clocks) {
851 clock = list_entry(this, struct dp83640_clock, list);
852 if (!list_empty(&clock->phylist)) {
853 pr_warn("phy list non-empty while unloading\n");
854 BUG();
855 }
856 list_del(&clock->list);
857 mutex_destroy(&clock->extreg_lock);
858 mutex_destroy(&clock->clock_lock);
859 put_device(&clock->bus->dev);
860 kfree(clock);
861 }
862
863 mutex_unlock(&phyter_clocks_lock);
864 }
865
866 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
867 {
868 INIT_LIST_HEAD(&clock->list);
869 clock->bus = bus;
870 mutex_init(&clock->extreg_lock);
871 mutex_init(&clock->clock_lock);
872 INIT_LIST_HEAD(&clock->phylist);
873 clock->caps.owner = THIS_MODULE;
874 sprintf(clock->caps.name, "dp83640 timer");
875 clock->caps.max_adj = 1953124;
876 clock->caps.n_alarm = 0;
877 clock->caps.n_ext_ts = N_EXT_TS;
878 clock->caps.n_per_out = 1;
879 clock->caps.pps = 0;
880 clock->caps.adjfreq = ptp_dp83640_adjfreq;
881 clock->caps.adjtime = ptp_dp83640_adjtime;
882 clock->caps.gettime = ptp_dp83640_gettime;
883 clock->caps.settime = ptp_dp83640_settime;
884 clock->caps.enable = ptp_dp83640_enable;
885 /*
886 * Get a reference to this bus instance.
887 */
888 get_device(&bus->dev);
889 }
890
891 static int choose_this_phy(struct dp83640_clock *clock,
892 struct phy_device *phydev)
893 {
894 if (chosen_phy == -1 && !clock->chosen)
895 return 1;
896
897 if (chosen_phy == phydev->addr)
898 return 1;
899
900 return 0;
901 }
902
903 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
904 {
905 if (clock)
906 mutex_lock(&clock->clock_lock);
907 return clock;
908 }
909
910 /*
911 * Look up and lock a clock by bus instance.
912 * If there is no clock for this bus, then create it first.
913 */
914 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
915 {
916 struct dp83640_clock *clock = NULL, *tmp;
917 struct list_head *this;
918
919 mutex_lock(&phyter_clocks_lock);
920
921 list_for_each(this, &phyter_clocks) {
922 tmp = list_entry(this, struct dp83640_clock, list);
923 if (tmp->bus == bus) {
924 clock = tmp;
925 break;
926 }
927 }
928 if (clock)
929 goto out;
930
931 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
932 if (!clock)
933 goto out;
934
935 dp83640_clock_init(clock, bus);
936 list_add_tail(&phyter_clocks, &clock->list);
937 out:
938 mutex_unlock(&phyter_clocks_lock);
939
940 return dp83640_clock_get(clock);
941 }
942
943 static void dp83640_clock_put(struct dp83640_clock *clock)
944 {
945 mutex_unlock(&clock->clock_lock);
946 }
947
948 static int dp83640_probe(struct phy_device *phydev)
949 {
950 struct dp83640_clock *clock;
951 struct dp83640_private *dp83640;
952 int err = -ENOMEM, i;
953
954 if (phydev->addr == BROADCAST_ADDR)
955 return 0;
956
957 clock = dp83640_clock_get_bus(phydev->bus);
958 if (!clock)
959 goto no_clock;
960
961 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
962 if (!dp83640)
963 goto no_memory;
964
965 dp83640->phydev = phydev;
966 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
967
968 INIT_LIST_HEAD(&dp83640->rxts);
969 INIT_LIST_HEAD(&dp83640->rxpool);
970 for (i = 0; i < MAX_RXTS; i++)
971 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
972
973 phydev->priv = dp83640;
974
975 spin_lock_init(&dp83640->rx_lock);
976 skb_queue_head_init(&dp83640->rx_queue);
977 skb_queue_head_init(&dp83640->tx_queue);
978
979 dp83640->clock = clock;
980
981 if (choose_this_phy(clock, phydev)) {
982 clock->chosen = dp83640;
983 clock->ptp_clock = ptp_clock_register(&clock->caps);
984 if (IS_ERR(clock->ptp_clock)) {
985 err = PTR_ERR(clock->ptp_clock);
986 goto no_register;
987 }
988 } else
989 list_add_tail(&dp83640->list, &clock->phylist);
990
991 if (clock->chosen && !list_empty(&clock->phylist))
992 recalibrate(clock);
993 else
994 enable_broadcast(dp83640->phydev, clock->page, 1);
995
996 dp83640_clock_put(clock);
997 return 0;
998
999 no_register:
1000 clock->chosen = NULL;
1001 kfree(dp83640);
1002 no_memory:
1003 dp83640_clock_put(clock);
1004 no_clock:
1005 return err;
1006 }
1007
1008 static void dp83640_remove(struct phy_device *phydev)
1009 {
1010 struct dp83640_clock *clock;
1011 struct list_head *this, *next;
1012 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1013 struct sk_buff *skb;
1014
1015 if (phydev->addr == BROADCAST_ADDR)
1016 return;
1017
1018 enable_status_frames(phydev, false);
1019 cancel_work_sync(&dp83640->ts_work);
1020
1021 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL)
1022 kfree_skb(skb);
1023
1024 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL)
1025 skb_complete_tx_timestamp(skb, NULL);
1026
1027 clock = dp83640_clock_get(dp83640->clock);
1028
1029 if (dp83640 == clock->chosen) {
1030 ptp_clock_unregister(clock->ptp_clock);
1031 clock->chosen = NULL;
1032 } else {
1033 list_for_each_safe(this, next, &clock->phylist) {
1034 tmp = list_entry(this, struct dp83640_private, list);
1035 if (tmp == dp83640) {
1036 list_del_init(&tmp->list);
1037 break;
1038 }
1039 }
1040 }
1041
1042 dp83640_clock_put(clock);
1043 kfree(dp83640);
1044 }
1045
1046 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1047 {
1048 struct dp83640_private *dp83640 = phydev->priv;
1049 struct hwtstamp_config cfg;
1050 u16 txcfg0, rxcfg0;
1051
1052 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1053 return -EFAULT;
1054
1055 if (cfg.flags) /* reserved for future extensions */
1056 return -EINVAL;
1057
1058 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1059 return -ERANGE;
1060
1061 dp83640->hwts_tx_en = cfg.tx_type;
1062
1063 switch (cfg.rx_filter) {
1064 case HWTSTAMP_FILTER_NONE:
1065 dp83640->hwts_rx_en = 0;
1066 dp83640->layer = 0;
1067 dp83640->version = 0;
1068 break;
1069 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1070 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1071 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1072 dp83640->hwts_rx_en = 1;
1073 dp83640->layer = LAYER4;
1074 dp83640->version = 1;
1075 break;
1076 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1077 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1078 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1079 dp83640->hwts_rx_en = 1;
1080 dp83640->layer = LAYER4;
1081 dp83640->version = 2;
1082 break;
1083 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1084 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1085 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1086 dp83640->hwts_rx_en = 1;
1087 dp83640->layer = LAYER2;
1088 dp83640->version = 2;
1089 break;
1090 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1091 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1092 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1093 dp83640->hwts_rx_en = 1;
1094 dp83640->layer = LAYER4|LAYER2;
1095 dp83640->version = 2;
1096 break;
1097 default:
1098 return -ERANGE;
1099 }
1100
1101 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1102 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1103
1104 if (dp83640->layer & LAYER2) {
1105 txcfg0 |= TX_L2_EN;
1106 rxcfg0 |= RX_L2_EN;
1107 }
1108 if (dp83640->layer & LAYER4) {
1109 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1110 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1111 }
1112
1113 if (dp83640->hwts_tx_en)
1114 txcfg0 |= TX_TS_EN;
1115
1116 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1117 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1118
1119 if (dp83640->hwts_rx_en)
1120 rxcfg0 |= RX_TS_EN;
1121
1122 mutex_lock(&dp83640->clock->extreg_lock);
1123
1124 if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
1125 enable_status_frames(phydev, true);
1126 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1127 }
1128
1129 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1130 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1131
1132 mutex_unlock(&dp83640->clock->extreg_lock);
1133
1134 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1135 }
1136
1137 static void rx_timestamp_work(struct work_struct *work)
1138 {
1139 struct dp83640_private *dp83640 =
1140 container_of(work, struct dp83640_private, ts_work);
1141 struct list_head *this, *next;
1142 struct rxts *rxts;
1143 struct skb_shared_hwtstamps *shhwtstamps;
1144 struct sk_buff *skb;
1145 unsigned int type;
1146 unsigned long flags;
1147
1148 /* Deliver each deferred packet, with or without a time stamp. */
1149
1150 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1151 type = SKB_PTP_TYPE(skb);
1152 spin_lock_irqsave(&dp83640->rx_lock, flags);
1153 list_for_each_safe(this, next, &dp83640->rxts) {
1154 rxts = list_entry(this, struct rxts, list);
1155 if (match(skb, type, rxts)) {
1156 shhwtstamps = skb_hwtstamps(skb);
1157 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1158 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1159 list_del_init(&rxts->list);
1160 list_add(&rxts->list, &dp83640->rxpool);
1161 break;
1162 }
1163 }
1164 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1165 netif_rx_ni(skb);
1166 }
1167
1168 /* Clear out expired time stamps. */
1169
1170 spin_lock_irqsave(&dp83640->rx_lock, flags);
1171 prune_rx_ts(dp83640);
1172 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1173 }
1174
1175 static bool dp83640_rxtstamp(struct phy_device *phydev,
1176 struct sk_buff *skb, int type)
1177 {
1178 struct dp83640_private *dp83640 = phydev->priv;
1179
1180 if (!dp83640->hwts_rx_en)
1181 return false;
1182
1183 if (is_status_frame(skb, type)) {
1184 decode_status_frame(dp83640, skb);
1185 kfree_skb(skb);
1186 return true;
1187 }
1188
1189 SKB_PTP_TYPE(skb) = type;
1190 skb_queue_tail(&dp83640->rx_queue, skb);
1191 schedule_work(&dp83640->ts_work);
1192
1193 return true;
1194 }
1195
1196 static void dp83640_txtstamp(struct phy_device *phydev,
1197 struct sk_buff *skb, int type)
1198 {
1199 struct dp83640_private *dp83640 = phydev->priv;
1200
1201 switch (dp83640->hwts_tx_en) {
1202
1203 case HWTSTAMP_TX_ONESTEP_SYNC:
1204 if (is_sync(skb, type)) {
1205 skb_complete_tx_timestamp(skb, NULL);
1206 return;
1207 }
1208 /* fall through */
1209 case HWTSTAMP_TX_ON:
1210 skb_queue_tail(&dp83640->tx_queue, skb);
1211 schedule_work(&dp83640->ts_work);
1212 break;
1213
1214 case HWTSTAMP_TX_OFF:
1215 default:
1216 skb_complete_tx_timestamp(skb, NULL);
1217 break;
1218 }
1219 }
1220
1221 static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1222 {
1223 struct dp83640_private *dp83640 = dev->priv;
1224
1225 info->so_timestamping =
1226 SOF_TIMESTAMPING_TX_HARDWARE |
1227 SOF_TIMESTAMPING_RX_HARDWARE |
1228 SOF_TIMESTAMPING_RAW_HARDWARE;
1229 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1230 info->tx_types =
1231 (1 << HWTSTAMP_TX_OFF) |
1232 (1 << HWTSTAMP_TX_ON) |
1233 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1234 info->rx_filters =
1235 (1 << HWTSTAMP_FILTER_NONE) |
1236 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1237 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1238 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1239 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1240 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1241 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1242 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1243 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
1244 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
1245 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1246 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1247 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
1248 return 0;
1249 }
1250
1251 static struct phy_driver dp83640_driver = {
1252 .phy_id = DP83640_PHY_ID,
1253 .phy_id_mask = 0xfffffff0,
1254 .name = "NatSemi DP83640",
1255 .features = PHY_BASIC_FEATURES,
1256 .flags = 0,
1257 .probe = dp83640_probe,
1258 .remove = dp83640_remove,
1259 .config_aneg = genphy_config_aneg,
1260 .read_status = genphy_read_status,
1261 .ts_info = dp83640_ts_info,
1262 .hwtstamp = dp83640_hwtstamp,
1263 .rxtstamp = dp83640_rxtstamp,
1264 .txtstamp = dp83640_txtstamp,
1265 .driver = {.owner = THIS_MODULE,}
1266 };
1267
1268 static int __init dp83640_init(void)
1269 {
1270 return phy_driver_register(&dp83640_driver);
1271 }
1272
1273 static void __exit dp83640_exit(void)
1274 {
1275 dp83640_free_clocks();
1276 phy_driver_unregister(&dp83640_driver);
1277 }
1278
1279 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1280 MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.at>");
1281 MODULE_LICENSE("GPL");
1282
1283 module_init(dp83640_init);
1284 module_exit(dp83640_exit);
1285
1286 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1287 { DP83640_PHY_ID, 0xfffffff0 },
1288 { }
1289 };
1290
1291 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
Linux kernel - Deliverables
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