2 * PS3 Platfom gelic network driver.
4 * Copyright (C) 2007 Sony Computer Entertainment Inc.
5 * Copyright 2006, 2007 Sony Corporation.
7 * This file is based on: spider_net.h
9 * (C) Copyright IBM Corp. 2005
11 * Authors : Utz Bacher <utz.bacher@de.ibm.com>
12 * Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2, or (at your option)
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
32 #define GELIC_NET_RX_DESCRIPTORS 128 /* num of descriptors */
33 #define GELIC_NET_TX_DESCRIPTORS 128 /* num of descriptors */
35 #define GELIC_NET_MAX_MTU VLAN_ETH_FRAME_LEN
36 #define GELIC_NET_MIN_MTU VLAN_ETH_ZLEN
37 #define GELIC_NET_RXBUF_ALIGN 128
38 #define GELIC_NET_RX_CSUM_DEFAULT 1 /* hw chksum */
39 #define GELIC_NET_WATCHDOG_TIMEOUT 5*HZ
40 #define GELIC_NET_NAPI_WEIGHT (GELIC_NET_RX_DESCRIPTORS)
41 #define GELIC_NET_BROADCAST_ADDR 0xffffffffffffL
42 #define GELIC_NET_VLAN_POS (VLAN_ETH_ALEN * 2)
43 #define GELIC_NET_VLAN_MAX 4
44 #define GELIC_NET_MC_COUNT_MAX 32 /* multicast address list */
46 /* virtual interrupt status register bits */
48 #define GELIC_CARD_TX_RAM_FULL_ERR 0x0000000000000001L
49 #define GELIC_CARD_RX_RAM_FULL_ERR 0x0000000000000002L
50 #define GELIC_CARD_TX_SHORT_FRAME_ERR 0x0000000000000004L
51 #define GELIC_CARD_TX_INVALID_DESCR_ERR 0x0000000000000008L
52 #define GELIC_CARD_RX_FIFO_FULL_ERR 0x0000000000002000L
53 #define GELIC_CARD_RX_DESCR_CHAIN_END 0x0000000000004000L
54 #define GELIC_CARD_RX_INVALID_DESCR_ERR 0x0000000000008000L
55 #define GELIC_CARD_TX_RESPONCE_ERR 0x0000000000010000L
56 #define GELIC_CARD_RX_RESPONCE_ERR 0x0000000000100000L
57 #define GELIC_CARD_TX_PROTECTION_ERR 0x0000000000400000L
58 #define GELIC_CARD_RX_PROTECTION_ERR 0x0000000004000000L
59 #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR 0x0000000008000000L
60 #define GELIC_CARD_PORT_STATUS_CHANGED 0x0000000020000000L
62 #define GELIC_CARD_TX_FLAGGED_DESCR 0x0004000000000000L
63 #define GELIC_CARD_RX_FLAGGED_DESCR 0x0040000000000000L
64 #define GELIC_CARD_TX_TRANSFER_END 0x0080000000000000L
65 #define GELIC_CARD_TX_DESCR_CHAIN_END 0x0100000000000000L
66 #define GELIC_CARD_NUMBER_OF_RX_FRAME 0x1000000000000000L
67 #define GELIC_CARD_ONE_TIME_COUNT_TIMER 0x4000000000000000L
68 #define GELIC_CARD_FREE_RUN_COUNT_TIMER 0x8000000000000000L
70 /* initial interrupt mask */
71 #define GELIC_CARD_TXINT GELIC_CARD_TX_DESCR_CHAIN_END
73 #define GELIC_CARD_RXINT (GELIC_CARD_RX_DESCR_CHAIN_END | \
74 GELIC_CARD_NUMBER_OF_RX_FRAME)
76 /* RX descriptor data_status bits */
77 enum gelic_descr_rx_status
{
78 GELIC_DESCR_RXDMADU
= 0x80000000, /* destination MAC addr unknown */
79 GELIC_DESCR_RXLSTFBF
= 0x40000000, /* last frame buffer */
80 GELIC_DESCR_RXIPCHK
= 0x20000000, /* IP checksum performed */
81 GELIC_DESCR_RXTCPCHK
= 0x10000000, /* TCP/UDP checksup performed */
82 GELIC_DESCR_RXWTPKT
= 0x00C00000, /*
83 * wakeup trigger packet
84 * 01: Magic Packet (TM)
86 * 11: Multicast MAC addr
88 GELIC_DESCR_RXVLNPKT
= 0x00200000, /* VLAN packet */
89 /* bit 20..16 reserved */
90 GELIC_DESCR_RXRRECNUM
= 0x0000ff00, /* reception receipt number */
91 /* bit 7..0 reserved */
94 #define GELIC_DESCR_DATA_STATUS_CHK_MASK \
95 (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
97 /* TX descriptor data_status bits */
98 enum gelic_descr_tx_status
{
99 GELIC_DESCR_TX_TAIL
= 0x00000001, /* gelic treated this
100 * descriptor was end of
105 /* RX descriptor data error bits */
106 enum gelic_descr_rx_error
{
107 /* bit 31 reserved */
108 GELIC_DESCR_RXALNERR
= 0x40000000, /* alignement error 10/100M */
109 GELIC_DESCR_RXOVERERR
= 0x20000000, /* oversize error */
110 GELIC_DESCR_RXRNTERR
= 0x10000000, /* Runt error */
111 GELIC_DESCR_RXIPCHKERR
= 0x08000000, /* IP checksum error */
112 GELIC_DESCR_RXTCPCHKERR
= 0x04000000, /* TCP/UDP checksum error */
113 GELIC_DESCR_RXDRPPKT
= 0x00100000, /* drop packet */
114 GELIC_DESCR_RXIPFMTERR
= 0x00080000, /* IP packet format error */
115 /* bit 18 reserved */
116 GELIC_DESCR_RXDATAERR
= 0x00020000, /* IP packet format error */
117 GELIC_DESCR_RXCALERR
= 0x00010000, /* cariier extension length
119 GELIC_DESCR_RXCREXERR
= 0x00008000, /* carrier extention error */
120 GELIC_DESCR_RXMLTCST
= 0x00004000, /* multicast address frame */
121 /* bit 13..0 reserved */
123 #define GELIC_DESCR_DATA_ERROR_CHK_MASK \
124 (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
126 /* DMA command and status (RX and TX)*/
127 enum gelic_descr_dma_status
{
128 GELIC_DESCR_DMA_COMPLETE
= 0x00000000, /* used in tx */
129 GELIC_DESCR_DMA_BUFFER_FULL
= 0x00000000, /* used in rx */
130 GELIC_DESCR_DMA_RESPONSE_ERROR
= 0x10000000, /* used in rx, tx */
131 GELIC_DESCR_DMA_PROTECTION_ERROR
= 0x20000000, /* used in rx, tx */
132 GELIC_DESCR_DMA_FRAME_END
= 0x40000000, /* used in rx */
133 GELIC_DESCR_DMA_FORCE_END
= 0x50000000, /* used in rx, tx */
134 GELIC_DESCR_DMA_CARDOWNED
= 0xa0000000, /* used in rx, tx */
135 GELIC_DESCR_DMA_NOT_IN_USE
= 0xb0000000, /* any other value */
138 #define GELIC_DESCR_DMA_STAT_MASK (0xf0000000)
140 /* tx descriptor command and status */
141 enum gelic_descr_tx_dma_status
{
143 GELIC_DESCR_TX_DMA_IKE
= 0x00080000, /* IPSEC off */
145 GELIC_DESCR_TX_DMA_FRAME_TAIL
= 0x00040000, /* last descriptor of
149 GELIC_DESCR_TX_DMA_TCP_CHKSUM
= 0x00020000, /* TCP packet */
150 GELIC_DESCR_TX_DMA_UDP_CHKSUM
= 0x00030000, /* UDP packet */
151 GELIC_DESCR_TX_DMA_NO_CHKSUM
= 0x00000000, /* no checksum */
154 GELIC_DESCR_TX_DMA_CHAIN_END
= 0x00000002, /* DMA terminated
159 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM \
160 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
161 GELIC_DESCR_TX_DMA_NO_CHKSUM)
163 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM \
164 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
165 GELIC_DESCR_TX_DMA_TCP_CHKSUM)
167 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM \
168 (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
169 GELIC_DESCR_TX_DMA_UDP_CHKSUM)
171 enum gelic_descr_rx_dma_status
{
173 GELIC_DESCR_RX_DMA_CHAIN_END
= 0x00000002, /* DMA terminated
178 /* for lv1_net_control */
179 enum gelic_lv1_net_control_code
{
180 GELIC_LV1_GET_MAC_ADDRESS
= 1,
181 GELIC_LV1_GET_ETH_PORT_STATUS
= 2,
182 GELIC_LV1_SET_NEGOTIATION_MODE
= 3,
183 GELIC_LV1_GET_VLAN_ID
= 4,
186 /* status returened from GET_ETH_PORT_STATUS */
187 enum gelic_lv1_ether_port_status
{
188 GELIC_LV1_ETHER_LINK_UP
= 0x0000000000000001L
,
189 GELIC_LV1_ETHER_FULL_DUPLEX
= 0x0000000000000002L
,
190 GELIC_LV1_ETHER_AUTO_NEG
= 0x0000000000000004L
,
192 GELIC_LV1_ETHER_SPEED_10
= 0x0000000000000010L
,
193 GELIC_LV1_ETHER_SPEED_100
= 0x0000000000000020L
,
194 GELIC_LV1_ETHER_SPEED_1000
= 0x0000000000000040L
,
195 GELIC_LV1_ETHER_SPEED_MASK
= 0x0000000000000070L
198 enum gelic_lv1_vlan_index
{
199 /* for outgoing packets */
200 GELIC_LV1_VLAN_TX_ETHERNET
= 0x0000000000000002L
,
201 GELIC_LV1_VLAN_TX_WIRELESS
= 0x0000000000000003L
,
202 /* for incoming packets */
203 GELIC_LV1_VLAN_RX_ETHERNET
= 0x0000000000000012L
,
204 GELIC_LV1_VLAN_RX_WIRELESS
= 0x0000000000000013L
207 /* size of hardware part of gelic descriptor */
208 #define GELIC_DESCR_SIZE (32)
210 /* as defined by the hardware */
213 __be32 next_descr_addr
;
214 __be32 dmac_cmd_status
;
216 __be32 valid_size
; /* all zeroes for tx */
218 __be32 data_error
; /* all zeroes for tx */
220 /* used in the driver */
223 struct gelic_descr
*next
;
224 struct gelic_descr
*prev
;
225 struct vlan_ethhdr vlan
;
226 } __attribute__((aligned(32)));
228 struct gelic_descr_chain
{
229 /* we walk from tail to head */
230 struct gelic_descr
*head
;
231 struct gelic_descr
*tail
;
235 struct net_device
*netdev
;
236 struct napi_struct napi
;
238 * hypervisor requires irq_status should be
239 * 8 bytes aligned, but u64 member is
240 * always disposed in that manner
245 struct ps3_system_bus_device
*dev
;
246 u32 vlan_id
[GELIC_NET_VLAN_MAX
];
249 struct gelic_descr_chain tx_chain
;
250 struct gelic_descr_chain rx_chain
;
251 int rx_dma_restart_required
;
252 /* gurad dmac descriptor chain*/
253 spinlock_t chain_lock
;
256 /* guard tx_dma_progress */
257 spinlock_t tx_dma_lock
;
260 struct work_struct tx_timeout_task
;
261 atomic_t tx_timeout_task_counter
;
262 wait_queue_head_t waitq
;
264 struct gelic_descr
*tx_top
, *rx_top
;
265 struct gelic_descr descr
[0];
269 extern unsigned long p_to_lp(long pa
);
271 #endif /* _GELIC_NET_H */