drivers/net/ps3_gelic_net.h

   1 /*
   2  *  PS3 Platfom gelic network driver.
   3  *
   4  * Copyright (C) 2007 Sony Computer Entertainment Inc.
   5  * Copyright 2006, 2007 Sony Corporation.
   6  *
   7  * This file is based on: spider_net.h
   8  *
   9  * (C) Copyright IBM Corp. 2005
  10  *
  11  * Authors : Utz Bacher <utz.bacher@de.ibm.com>
  12  *           Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License as published by
  16  * the Free Software Foundation; either version 2, or (at your option)
  17  * any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  27  */
  28 #ifndef _GELIC_NET_H
  29 #define _GELIC_NET_H
  30
  31 /* descriptors */
  32 #define GELIC_NET_RX_DESCRIPTORS        128 /* num of descriptors */
  33 #define GELIC_NET_TX_DESCRIPTORS        128 /* num of descriptors */
  34
  35 #define GELIC_NET_MAX_MTU               VLAN_ETH_FRAME_LEN
  36 #define GELIC_NET_MIN_MTU               VLAN_ETH_ZLEN
  37 #define GELIC_NET_RXBUF_ALIGN           128
  38 #define GELIC_CARD_RX_CSUM_DEFAULT      1 /* hw chksum */
  39 #define GELIC_NET_WATCHDOG_TIMEOUT      5*HZ
  40 #define GELIC_NET_NAPI_WEIGHT           (GELIC_NET_RX_DESCRIPTORS)
  41 #define GELIC_NET_BROADCAST_ADDR        0xffffffffffffL
  42
  43 #define GELIC_NET_MC_COUNT_MAX          32 /* multicast address list */
  44
  45 /* virtual interrupt status register bits */
  46         /* INT1 */
  47 #define GELIC_CARD_TX_RAM_FULL_ERR           0x0000000000000001L
  48 #define GELIC_CARD_RX_RAM_FULL_ERR           0x0000000000000002L
  49 #define GELIC_CARD_TX_SHORT_FRAME_ERR        0x0000000000000004L
  50 #define GELIC_CARD_TX_INVALID_DESCR_ERR      0x0000000000000008L
  51 #define GELIC_CARD_RX_FIFO_FULL_ERR          0x0000000000002000L
  52 #define GELIC_CARD_RX_DESCR_CHAIN_END        0x0000000000004000L
  53 #define GELIC_CARD_RX_INVALID_DESCR_ERR      0x0000000000008000L
  54 #define GELIC_CARD_TX_RESPONCE_ERR           0x0000000000010000L
  55 #define GELIC_CARD_RX_RESPONCE_ERR           0x0000000000100000L
  56 #define GELIC_CARD_TX_PROTECTION_ERR         0x0000000000400000L
  57 #define GELIC_CARD_RX_PROTECTION_ERR         0x0000000004000000L
  58 #define GELIC_CARD_TX_TCP_UDP_CHECKSUM_ERR   0x0000000008000000L
  59 #define GELIC_CARD_PORT_STATUS_CHANGED       0x0000000020000000L
  60         /* INT 0 */
  61 #define GELIC_CARD_TX_FLAGGED_DESCR          0x0004000000000000L
  62 #define GELIC_CARD_RX_FLAGGED_DESCR          0x0040000000000000L
  63 #define GELIC_CARD_TX_TRANSFER_END           0x0080000000000000L
  64 #define GELIC_CARD_TX_DESCR_CHAIN_END        0x0100000000000000L
  65 #define GELIC_CARD_NUMBER_OF_RX_FRAME        0x1000000000000000L
  66 #define GELIC_CARD_ONE_TIME_COUNT_TIMER      0x4000000000000000L
  67 #define GELIC_CARD_FREE_RUN_COUNT_TIMER      0x8000000000000000L
  68
  69 /* initial interrupt mask */
  70 #define GELIC_CARD_TXINT        GELIC_CARD_TX_DESCR_CHAIN_END
  71
  72 #define GELIC_CARD_RXINT        (GELIC_CARD_RX_DESCR_CHAIN_END | \
  73                                  GELIC_CARD_NUMBER_OF_RX_FRAME)
  74
  75  /* RX descriptor data_status bits */
  76 enum gelic_descr_rx_status {
  77         GELIC_DESCR_RXDMADU     = 0x80000000, /* destination MAC addr unknown */
  78         GELIC_DESCR_RXLSTFBF    = 0x40000000, /* last frame buffer            */
  79         GELIC_DESCR_RXIPCHK     = 0x20000000, /* IP checksum performed        */
  80         GELIC_DESCR_RXTCPCHK    = 0x10000000, /* TCP/UDP checksup performed   */
  81         GELIC_DESCR_RXWTPKT     = 0x00C00000, /*
  82                                                * wakeup trigger packet
  83                                                * 01: Magic Packet (TM)
  84                                                * 10: ARP packet
  85                                                * 11: Multicast MAC addr
  86                                                */
  87         GELIC_DESCR_RXVLNPKT    = 0x00200000, /* VLAN packet */
  88         /* bit 20..16 reserved */
  89         GELIC_DESCR_RXRRECNUM   = 0x0000ff00, /* reception receipt number */
  90         /* bit 7..0 reserved */
  91 };
  92
  93 #define GELIC_DESCR_DATA_STATUS_CHK_MASK        \
  94         (GELIC_DESCR_RXIPCHK | GELIC_DESCR_RXTCPCHK)
  95
  96  /* TX descriptor data_status bits */
  97 enum gelic_descr_tx_status {
  98         GELIC_DESCR_TX_TAIL     = 0x00000001, /* gelic treated this
  99                                                * descriptor was end of
 100                                                * a tx frame
 101                                                */
 102 };
 103
 104 /* RX descriptor data error bits */
 105 enum gelic_descr_rx_error {
 106         /* bit 31 reserved */
 107         GELIC_DESCR_RXALNERR    = 0x40000000, /* alignement error 10/100M */
 108         GELIC_DESCR_RXOVERERR   = 0x20000000, /* oversize error */
 109         GELIC_DESCR_RXRNTERR    = 0x10000000, /* Runt error */
 110         GELIC_DESCR_RXIPCHKERR  = 0x08000000, /* IP checksum  error */
 111         GELIC_DESCR_RXTCPCHKERR = 0x04000000, /* TCP/UDP checksum  error */
 112         GELIC_DESCR_RXDRPPKT    = 0x00100000, /* drop packet */
 113         GELIC_DESCR_RXIPFMTERR  = 0x00080000, /* IP packet format error */
 114         /* bit 18 reserved */
 115         GELIC_DESCR_RXDATAERR   = 0x00020000, /* IP packet format error */
 116         GELIC_DESCR_RXCALERR    = 0x00010000, /* cariier extension length
 117                                               * error */
 118         GELIC_DESCR_RXCREXERR   = 0x00008000, /* carrier extention error */
 119         GELIC_DESCR_RXMLTCST    = 0x00004000, /* multicast address frame */
 120         /* bit 13..0 reserved */
 121 };
 122 #define GELIC_DESCR_DATA_ERROR_CHK_MASK         \
 123         (GELIC_DESCR_RXIPCHKERR | GELIC_DESCR_RXTCPCHKERR)
 124
 125 /* DMA command and status (RX and TX)*/
 126 enum gelic_descr_dma_status {
 127         GELIC_DESCR_DMA_COMPLETE            = 0x00000000, /* used in tx */
 128         GELIC_DESCR_DMA_BUFFER_FULL         = 0x00000000, /* used in rx */
 129         GELIC_DESCR_DMA_RESPONSE_ERROR      = 0x10000000, /* used in rx, tx */
 130         GELIC_DESCR_DMA_PROTECTION_ERROR    = 0x20000000, /* used in rx, tx */
 131         GELIC_DESCR_DMA_FRAME_END           = 0x40000000, /* used in rx */
 132         GELIC_DESCR_DMA_FORCE_END           = 0x50000000, /* used in rx, tx */
 133         GELIC_DESCR_DMA_CARDOWNED           = 0xa0000000, /* used in rx, tx */
 134         GELIC_DESCR_DMA_NOT_IN_USE          = 0xb0000000, /* any other value */
 135 };
 136
 137 #define GELIC_DESCR_DMA_STAT_MASK       (0xf0000000)
 138
 139 /* tx descriptor command and status */
 140 enum gelic_descr_tx_dma_status {
 141         /* [19] */
 142         GELIC_DESCR_TX_DMA_IKE          = 0x00080000, /* IPSEC off */
 143         /* [18] */
 144         GELIC_DESCR_TX_DMA_FRAME_TAIL   = 0x00040000, /* last descriptor of
 145                                                        * the packet
 146                                                        */
 147         /* [17..16] */
 148         GELIC_DESCR_TX_DMA_TCP_CHKSUM   = 0x00020000, /* TCP packet */
 149         GELIC_DESCR_TX_DMA_UDP_CHKSUM   = 0x00030000, /* UDP packet */
 150         GELIC_DESCR_TX_DMA_NO_CHKSUM    = 0x00000000, /* no checksum */
 151
 152         /* [1] */
 153         GELIC_DESCR_TX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 154                                                        * due to chain end
 155                                                        */
 156 };
 157
 158 #define GELIC_DESCR_DMA_CMD_NO_CHKSUM   \
 159         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 160         GELIC_DESCR_TX_DMA_NO_CHKSUM)
 161
 162 #define GELIC_DESCR_DMA_CMD_TCP_CHKSUM  \
 163         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 164         GELIC_DESCR_TX_DMA_TCP_CHKSUM)
 165
 166 #define GELIC_DESCR_DMA_CMD_UDP_CHKSUM  \
 167         (GELIC_DESCR_DMA_CARDOWNED | GELIC_DESCR_TX_DMA_IKE | \
 168         GELIC_DESCR_TX_DMA_UDP_CHKSUM)
 169
 170 enum gelic_descr_rx_dma_status {
 171         /* [ 1 ] */
 172         GELIC_DESCR_RX_DMA_CHAIN_END    = 0x00000002, /* DMA terminated
 173                                                        * due to chain end
 174                                                        */
 175 };
 176
 177 /* for lv1_net_control */
 178 enum gelic_lv1_net_control_code {
 179         GELIC_LV1_GET_MAC_ADDRESS       = 1,
 180         GELIC_LV1_GET_ETH_PORT_STATUS   = 2,
 181         GELIC_LV1_SET_NEGOTIATION_MODE  = 3,
 182         GELIC_LV1_GET_VLAN_ID           = 4,
 183 };
 184
 185 /* status returened from GET_ETH_PORT_STATUS */
 186 enum gelic_lv1_ether_port_status {
 187         GELIC_LV1_ETHER_LINK_UP         = 0x0000000000000001L,
 188         GELIC_LV1_ETHER_FULL_DUPLEX     = 0x0000000000000002L,
 189         GELIC_LV1_ETHER_AUTO_NEG        = 0x0000000000000004L,
 190
 191         GELIC_LV1_ETHER_SPEED_10        = 0x0000000000000010L,
 192         GELIC_LV1_ETHER_SPEED_100       = 0x0000000000000020L,
 193         GELIC_LV1_ETHER_SPEED_1000      = 0x0000000000000040L,
 194         GELIC_LV1_ETHER_SPEED_MASK      = 0x0000000000000070L
 195 };
 196
 197 enum gelic_lv1_vlan_index {
 198         /* for outgoing packets */
 199         GELIC_LV1_VLAN_TX_ETHERNET      = 0x0000000000000002L,
 200         GELIC_LV1_VLAN_TX_WIRELESS      = 0x0000000000000003L,
 201         /* for incoming packets */
 202         GELIC_LV1_VLAN_RX_ETHERNET      = 0x0000000000000012L,
 203         GELIC_LV1_VLAN_RX_WIRELESS      = 0x0000000000000013L
 204 };
 205
 206 /* size of hardware part of gelic descriptor */
 207 #define GELIC_DESCR_SIZE        (32)
 208
 209 enum gelic_port_type {
 210         GELIC_PORT_ETHERNET = 0,
 211         GELIC_PORT_WIRELESS = 1,
 212         GELIC_PORT_MAX
 213 };
 214
 215 struct gelic_descr {
 216         /* as defined by the hardware */
 217         __be32 buf_addr;
 218         __be32 buf_size;
 219         __be32 next_descr_addr;
 220         __be32 dmac_cmd_status;
 221         __be32 result_size;
 222         __be32 valid_size;      /* all zeroes for tx */
 223         __be32 data_status;
 224         __be32 data_error;      /* all zeroes for tx */
 225
 226         /* used in the driver */
 227         struct sk_buff *skb;
 228         dma_addr_t bus_addr;
 229         struct gelic_descr *next;
 230         struct gelic_descr *prev;
 231 } __attribute__((aligned(32)));
 232
 233 struct gelic_descr_chain {
 234         /* we walk from tail to head */
 235         struct gelic_descr *head;
 236         struct gelic_descr *tail;
 237 };
 238
 239 struct gelic_vlan_id {
 240         u16 tx;
 241         u16 rx;
 242 };
 243
 244 struct gelic_card {
 245         struct napi_struct napi;
 246         struct net_device *netdev[GELIC_PORT_MAX];
 247         /*
 248          * hypervisor requires irq_status should be
 249          * 8 bytes aligned, but u64 member is
 250          * always disposed in that manner
 251          */
 252         u64 irq_status;
 253         u64 irq_mask;
 254
 255         struct ps3_system_bus_device *dev;
 256         struct gelic_vlan_id vlan[GELIC_PORT_MAX];
 257         int vlan_required;
 258
 259         struct gelic_descr_chain tx_chain;
 260         struct gelic_descr_chain rx_chain;
 261         int rx_dma_restart_required;
 262         int rx_csum;
 263         /*
 264          * tx_lock guards tx descriptor list and
 265          * tx_dma_progress.
 266          */
 267         spinlock_t tx_lock;
 268         int tx_dma_progress;
 269
 270         struct work_struct tx_timeout_task;
 271         atomic_t tx_timeout_task_counter;
 272         wait_queue_head_t waitq;
 273
 274         /* only first user should up the card */
 275         struct semaphore updown_lock;
 276         atomic_t users;
 277
 278         u64 ether_port_status;
 279         /* original address returned by kzalloc */
 280         void *unalign;
 281
 282         /*
 283          * each netdevice has copy of irq
 284          */
 285         unsigned int irq;
 286         struct gelic_descr *tx_top, *rx_top;
 287         struct gelic_descr descr[0]; /* must be the last */
 288 };
 289
 290 struct gelic_port {
 291         struct gelic_card *card;
 292         struct net_device *netdev;
 293         enum gelic_port_type type;
 294         long priv[0]; /* long for alignment */
 295 };
 296
 297 static inline struct gelic_card *port_to_card(struct gelic_port *p)
 298 {
 299         return p->card;
 300 }
 301 static inline struct net_device *port_to_netdev(struct gelic_port *p)
 302 {
 303         return p->netdev;
 304 }
 305 static inline struct gelic_card *netdev_card(struct net_device *d)
 306 {
 307         return ((struct gelic_port *)netdev_priv(d))->card;
 308 }
 309 static inline struct gelic_port *netdev_port(struct net_device *d)
 310 {
 311         return (struct gelic_port *)netdev_priv(d);
 312 }
 313 static inline struct device *ctodev(struct gelic_card *card)
 314 {
 315         return &card->dev->core;
 316 }
 317 static inline u64 bus_id(struct gelic_card *card)
 318 {
 319         return card->dev->bus_id;
 320 }
 321 static inline u64 dev_id(struct gelic_card *card)
 322 {
 323         return card->dev->dev_id;
 324 }
 325
 326 static inline void *port_priv(struct gelic_port *port)
 327 {
 328         return port->priv;
 329 }
 330
 331 extern int gelic_card_set_irq_mask(struct gelic_card *card, u64 mask);
 332 /* shared netdev ops */
 333 extern void gelic_card_up(struct gelic_card *card);
 334 extern void gelic_card_down(struct gelic_card *card);
 335 extern int gelic_net_open(struct net_device *netdev);
 336 extern int gelic_net_stop(struct net_device *netdev);
 337 extern int gelic_net_xmit(struct sk_buff *skb, struct net_device *netdev);
 338 extern void gelic_net_set_multi(struct net_device *netdev);
 339 extern void gelic_net_tx_timeout(struct net_device *netdev);
 340 extern int gelic_net_change_mtu(struct net_device *netdev, int new_mtu);
 341 extern int gelic_net_setup_netdev(struct net_device *netdev,
 342                                   struct gelic_card *card);
 343
 344 /* shared ethtool ops */
 345 extern void gelic_net_get_drvinfo(struct net_device *netdev,
 346                                   struct ethtool_drvinfo *info);
 347 extern u32 gelic_net_get_rx_csum(struct net_device *netdev);
 348 extern int gelic_net_set_rx_csum(struct net_device *netdev, u32 data);
 349 extern void gelic_net_poll_controller(struct net_device *netdev);
 350
 351 #endif /* _GELIC_NET_H */