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qla3xxx: bugfix: Multi segment sends were getting whacked.
[deliverable/linux.git] / drivers / net / qla3xxx.c
1 /*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
24 #include <linux/ip.h>
25 #include <linux/in.h>
26 #include <linux/if_arp.h>
27 #include <linux/if_ether.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/skbuff.h>
32 #include <linux/rtnetlink.h>
33 #include <linux/if_vlan.h>
34 #include <linux/init.h>
35 #include <linux/delay.h>
36 #include <linux/mm.h>
37
38 #include "qla3xxx.h"
39
40 #define DRV_NAME "qla3xxx"
41 #define DRV_STRING "QLogic ISP3XXX Network Driver"
42 #define DRV_VERSION "v2.03.00-k3"
43 #define PFX DRV_NAME " "
44
45 static const char ql3xxx_driver_name[] = DRV_NAME;
46 static const char ql3xxx_driver_version[] = DRV_VERSION;
47
48 MODULE_AUTHOR("QLogic Corporation");
49 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
50 MODULE_LICENSE("GPL");
51 MODULE_VERSION(DRV_VERSION);
52
53 static const u32 default_msg
54 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
55 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
56
57 static int debug = -1; /* defaults above */
58 module_param(debug, int, 0);
59 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
60
61 static int msi;
62 module_param(msi, int, 0);
63 MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
64
65 static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = {
66 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
67 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
68 /* required last entry */
69 {0,}
70 };
71
72 MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
73
74 /*
75 * Caller must take hw_lock.
76 */
77 static int ql_sem_spinlock(struct ql3_adapter *qdev,
78 u32 sem_mask, u32 sem_bits)
79 {
80 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
81 u32 value;
82 unsigned int seconds = 3;
83
84 do {
85 writel((sem_mask | sem_bits),
86 &port_regs->CommonRegs.semaphoreReg);
87 value = readl(&port_regs->CommonRegs.semaphoreReg);
88 if ((value & (sem_mask >> 16)) == sem_bits)
89 return 0;
90 ssleep(1);
91 } while(--seconds);
92 return -1;
93 }
94
95 static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
96 {
97 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
98 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
99 readl(&port_regs->CommonRegs.semaphoreReg);
100 }
101
102 static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
103 {
104 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
105 u32 value;
106
107 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
108 value = readl(&port_regs->CommonRegs.semaphoreReg);
109 return ((value & (sem_mask >> 16)) == sem_bits);
110 }
111
112 /*
113 * Caller holds hw_lock.
114 */
115 static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
116 {
117 int i = 0;
118
119 while (1) {
120 if (!ql_sem_lock(qdev,
121 QL_DRVR_SEM_MASK,
122 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
123 * 2) << 1)) {
124 if (i < 10) {
125 ssleep(1);
126 i++;
127 } else {
128 printk(KERN_ERR PFX "%s: Timed out waiting for "
129 "driver lock...\n",
130 qdev->ndev->name);
131 return 0;
132 }
133 } else {
134 printk(KERN_DEBUG PFX
135 "%s: driver lock acquired.\n",
136 qdev->ndev->name);
137 return 1;
138 }
139 }
140 }
141
142 static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
143 {
144 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
145
146 writel(((ISP_CONTROL_NP_MASK << 16) | page),
147 &port_regs->CommonRegs.ispControlStatus);
148 readl(&port_regs->CommonRegs.ispControlStatus);
149 qdev->current_page = page;
150 }
151
152 static u32 ql_read_common_reg_l(struct ql3_adapter *qdev,
153 u32 __iomem * reg)
154 {
155 u32 value;
156 unsigned long hw_flags;
157
158 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
159 value = readl(reg);
160 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
161
162 return value;
163 }
164
165 static u32 ql_read_common_reg(struct ql3_adapter *qdev,
166 u32 __iomem * reg)
167 {
168 return readl(reg);
169 }
170
171 static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
172 {
173 u32 value;
174 unsigned long hw_flags;
175
176 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
177
178 if (qdev->current_page != 0)
179 ql_set_register_page(qdev,0);
180 value = readl(reg);
181
182 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
183 return value;
184 }
185
186 static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
187 {
188 if (qdev->current_page != 0)
189 ql_set_register_page(qdev,0);
190 return readl(reg);
191 }
192
193 static void ql_write_common_reg_l(struct ql3_adapter *qdev,
194 u32 __iomem *reg, u32 value)
195 {
196 unsigned long hw_flags;
197
198 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
199 writel(value, reg);
200 readl(reg);
201 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
202 return;
203 }
204
205 static void ql_write_common_reg(struct ql3_adapter *qdev,
206 u32 __iomem *reg, u32 value)
207 {
208 writel(value, reg);
209 readl(reg);
210 return;
211 }
212
213 static void ql_write_nvram_reg(struct ql3_adapter *qdev,
214 u32 __iomem *reg, u32 value)
215 {
216 writel(value, reg);
217 readl(reg);
218 udelay(1);
219 return;
220 }
221
222 static void ql_write_page0_reg(struct ql3_adapter *qdev,
223 u32 __iomem *reg, u32 value)
224 {
225 if (qdev->current_page != 0)
226 ql_set_register_page(qdev,0);
227 writel(value, reg);
228 readl(reg);
229 return;
230 }
231
232 /*
233 * Caller holds hw_lock. Only called during init.
234 */
235 static void ql_write_page1_reg(struct ql3_adapter *qdev,
236 u32 __iomem *reg, u32 value)
237 {
238 if (qdev->current_page != 1)
239 ql_set_register_page(qdev,1);
240 writel(value, reg);
241 readl(reg);
242 return;
243 }
244
245 /*
246 * Caller holds hw_lock. Only called during init.
247 */
248 static void ql_write_page2_reg(struct ql3_adapter *qdev,
249 u32 __iomem *reg, u32 value)
250 {
251 if (qdev->current_page != 2)
252 ql_set_register_page(qdev,2);
253 writel(value, reg);
254 readl(reg);
255 return;
256 }
257
258 static void ql_disable_interrupts(struct ql3_adapter *qdev)
259 {
260 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
261
262 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
263 (ISP_IMR_ENABLE_INT << 16));
264
265 }
266
267 static void ql_enable_interrupts(struct ql3_adapter *qdev)
268 {
269 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
270
271 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
272 ((0xff << 16) | ISP_IMR_ENABLE_INT));
273
274 }
275
276 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
277 struct ql_rcv_buf_cb *lrg_buf_cb)
278 {
279 dma_addr_t map;
280 int err;
281 lrg_buf_cb->next = NULL;
282
283 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
284 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
285 } else {
286 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
287 qdev->lrg_buf_free_tail = lrg_buf_cb;
288 }
289
290 if (!lrg_buf_cb->skb) {
291 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
292 qdev->lrg_buffer_len);
293 if (unlikely(!lrg_buf_cb->skb)) {
294 printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n",
295 qdev->ndev->name);
296 qdev->lrg_buf_skb_check++;
297 } else {
298 /*
299 * We save some space to copy the ethhdr from first
300 * buffer
301 */
302 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
303 map = pci_map_single(qdev->pdev,
304 lrg_buf_cb->skb->data,
305 qdev->lrg_buffer_len -
306 QL_HEADER_SPACE,
307 PCI_DMA_FROMDEVICE);
308 err = pci_dma_mapping_error(map);
309 if(err) {
310 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
311 qdev->ndev->name, err);
312 dev_kfree_skb(lrg_buf_cb->skb);
313 lrg_buf_cb->skb = NULL;
314
315 qdev->lrg_buf_skb_check++;
316 return;
317 }
318
319 lrg_buf_cb->buf_phy_addr_low =
320 cpu_to_le32(LS_64BITS(map));
321 lrg_buf_cb->buf_phy_addr_high =
322 cpu_to_le32(MS_64BITS(map));
323 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
324 pci_unmap_len_set(lrg_buf_cb, maplen,
325 qdev->lrg_buffer_len -
326 QL_HEADER_SPACE);
327 }
328 }
329
330 qdev->lrg_buf_free_count++;
331 }
332
333 static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
334 *qdev)
335 {
336 struct ql_rcv_buf_cb *lrg_buf_cb;
337
338 if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) {
339 if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL)
340 qdev->lrg_buf_free_tail = NULL;
341 qdev->lrg_buf_free_count--;
342 }
343
344 return lrg_buf_cb;
345 }
346
347 static u32 addrBits = EEPROM_NO_ADDR_BITS;
348 static u32 dataBits = EEPROM_NO_DATA_BITS;
349
350 static void fm93c56a_deselect(struct ql3_adapter *qdev);
351 static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
352 unsigned short *value);
353
354 /*
355 * Caller holds hw_lock.
356 */
357 static void fm93c56a_select(struct ql3_adapter *qdev)
358 {
359 struct ql3xxx_port_registers __iomem *port_regs =
360 qdev->mem_map_registers;
361
362 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
363 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
364 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
365 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
366 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
367 }
368
369 /*
370 * Caller holds hw_lock.
371 */
372 static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
373 {
374 int i;
375 u32 mask;
376 u32 dataBit;
377 u32 previousBit;
378 struct ql3xxx_port_registers __iomem *port_regs =
379 qdev->mem_map_registers;
380
381 /* Clock in a zero, then do the start bit */
382 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
383 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
384 AUBURN_EEPROM_DO_1);
385 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
386 ISP_NVRAM_MASK | qdev->
387 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
388 AUBURN_EEPROM_CLK_RISE);
389 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
390 ISP_NVRAM_MASK | qdev->
391 eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
392 AUBURN_EEPROM_CLK_FALL);
393
394 mask = 1 << (FM93C56A_CMD_BITS - 1);
395 /* Force the previous data bit to be different */
396 previousBit = 0xffff;
397 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
398 dataBit =
399 (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0;
400 if (previousBit != dataBit) {
401 /*
402 * If the bit changed, then change the DO state to
403 * match
404 */
405 ql_write_nvram_reg(qdev,
406 &port_regs->CommonRegs.
407 serialPortInterfaceReg,
408 ISP_NVRAM_MASK | qdev->
409 eeprom_cmd_data | dataBit);
410 previousBit = dataBit;
411 }
412 ql_write_nvram_reg(qdev,
413 &port_regs->CommonRegs.
414 serialPortInterfaceReg,
415 ISP_NVRAM_MASK | qdev->
416 eeprom_cmd_data | dataBit |
417 AUBURN_EEPROM_CLK_RISE);
418 ql_write_nvram_reg(qdev,
419 &port_regs->CommonRegs.
420 serialPortInterfaceReg,
421 ISP_NVRAM_MASK | qdev->
422 eeprom_cmd_data | dataBit |
423 AUBURN_EEPROM_CLK_FALL);
424 cmd = cmd << 1;
425 }
426
427 mask = 1 << (addrBits - 1);
428 /* Force the previous data bit to be different */
429 previousBit = 0xffff;
430 for (i = 0; i < addrBits; i++) {
431 dataBit =
432 (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 :
433 AUBURN_EEPROM_DO_0;
434 if (previousBit != dataBit) {
435 /*
436 * If the bit changed, then change the DO state to
437 * match
438 */
439 ql_write_nvram_reg(qdev,
440 &port_regs->CommonRegs.
441 serialPortInterfaceReg,
442 ISP_NVRAM_MASK | qdev->
443 eeprom_cmd_data | dataBit);
444 previousBit = dataBit;
445 }
446 ql_write_nvram_reg(qdev,
447 &port_regs->CommonRegs.
448 serialPortInterfaceReg,
449 ISP_NVRAM_MASK | qdev->
450 eeprom_cmd_data | dataBit |
451 AUBURN_EEPROM_CLK_RISE);
452 ql_write_nvram_reg(qdev,
453 &port_regs->CommonRegs.
454 serialPortInterfaceReg,
455 ISP_NVRAM_MASK | qdev->
456 eeprom_cmd_data | dataBit |
457 AUBURN_EEPROM_CLK_FALL);
458 eepromAddr = eepromAddr << 1;
459 }
460 }
461
462 /*
463 * Caller holds hw_lock.
464 */
465 static void fm93c56a_deselect(struct ql3_adapter *qdev)
466 {
467 struct ql3xxx_port_registers __iomem *port_regs =
468 qdev->mem_map_registers;
469 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
470 ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
471 ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
472 }
473
474 /*
475 * Caller holds hw_lock.
476 */
477 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
478 {
479 int i;
480 u32 data = 0;
481 u32 dataBit;
482 struct ql3xxx_port_registers __iomem *port_regs =
483 qdev->mem_map_registers;
484
485 /* Read the data bits */
486 /* The first bit is a dummy. Clock right over it. */
487 for (i = 0; i < dataBits; i++) {
488 ql_write_nvram_reg(qdev,
489 &port_regs->CommonRegs.
490 serialPortInterfaceReg,
491 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
492 AUBURN_EEPROM_CLK_RISE);
493 ql_write_nvram_reg(qdev,
494 &port_regs->CommonRegs.
495 serialPortInterfaceReg,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit =
499 (ql_read_common_reg
500 (qdev,
501 &port_regs->CommonRegs.
502 serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0;
503 data = (data << 1) | dataBit;
504 }
505 *value = (u16) data;
506 }
507
508 /*
509 * Caller holds hw_lock.
510 */
511 static void eeprom_readword(struct ql3_adapter *qdev,
512 u32 eepromAddr, unsigned short *value)
513 {
514 fm93c56a_select(qdev);
515 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
516 fm93c56a_datain(qdev, value);
517 fm93c56a_deselect(qdev);
518 }
519
520 static void ql_swap_mac_addr(u8 * macAddress)
521 {
522 #ifdef __BIG_ENDIAN
523 u8 temp;
524 temp = macAddress[0];
525 macAddress[0] = macAddress[1];
526 macAddress[1] = temp;
527 temp = macAddress[2];
528 macAddress[2] = macAddress[3];
529 macAddress[3] = temp;
530 temp = macAddress[4];
531 macAddress[4] = macAddress[5];
532 macAddress[5] = temp;
533 #endif
534 }
535
536 static int ql_get_nvram_params(struct ql3_adapter *qdev)
537 {
538 u16 *pEEPROMData;
539 u16 checksum = 0;
540 u32 index;
541 unsigned long hw_flags;
542
543 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
544
545 pEEPROMData = (u16 *) & qdev->nvram_data;
546 qdev->eeprom_cmd_data = 0;
547 if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
548 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
549 2) << 10)) {
550 printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n",
551 __func__);
552 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
553 return -1;
554 }
555
556 for (index = 0; index < EEPROM_SIZE; index++) {
557 eeprom_readword(qdev, index, pEEPROMData);
558 checksum += *pEEPROMData;
559 pEEPROMData++;
560 }
561 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
562
563 if (checksum != 0) {
564 printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n",
565 qdev->ndev->name, checksum);
566 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
567 return -1;
568 }
569
570 /*
571 * We have a problem with endianness for the MAC addresses
572 * and the two 8-bit values version, and numPorts. We
573 * have to swap them on big endian systems.
574 */
575 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress);
576 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress);
577 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress);
578 ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress);
579 pEEPROMData = (u16 *) & qdev->nvram_data.version;
580 *pEEPROMData = le16_to_cpu(*pEEPROMData);
581
582 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
583 return checksum;
584 }
585
586 static const u32 PHYAddr[2] = {
587 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
588 };
589
590 static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
591 {
592 struct ql3xxx_port_registers __iomem *port_regs =
593 qdev->mem_map_registers;
594 u32 temp;
595 int count = 1000;
596
597 while (count) {
598 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
599 if (!(temp & MAC_MII_STATUS_BSY))
600 return 0;
601 udelay(10);
602 count--;
603 }
604 return -1;
605 }
606
607 static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
608 {
609 struct ql3xxx_port_registers __iomem *port_regs =
610 qdev->mem_map_registers;
611 u32 scanControl;
612
613 if (qdev->numPorts > 1) {
614 /* Auto scan will cycle through multiple ports */
615 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
616 } else {
617 scanControl = MAC_MII_CONTROL_SC;
618 }
619
620 /*
621 * Scan register 1 of PHY/PETBI,
622 * Set up to scan both devices
623 * The autoscan starts from the first register, completes
624 * the last one before rolling over to the first
625 */
626 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
627 PHYAddr[0] | MII_SCAN_REGISTER);
628
629 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
630 (scanControl) |
631 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
632 }
633
634 static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
635 {
636 u8 ret;
637 struct ql3xxx_port_registers __iomem *port_regs =
638 qdev->mem_map_registers;
639
640 /* See if scan mode is enabled before we turn it off */
641 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
642 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
643 /* Scan is enabled */
644 ret = 1;
645 } else {
646 /* Scan is disabled */
647 ret = 0;
648 }
649
650 /*
651 * When disabling scan mode you must first change the MII register
652 * address
653 */
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
655 PHYAddr[0] | MII_SCAN_REGISTER);
656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
658 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
659 MAC_MII_CONTROL_RC) << 16));
660
661 return ret;
662 }
663
664 static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
665 u16 regAddr, u16 value, u32 mac_index)
666 {
667 struct ql3xxx_port_registers __iomem *port_regs =
668 qdev->mem_map_registers;
669 u8 scanWasEnabled;
670
671 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
672
673 if (ql_wait_for_mii_ready(qdev)) {
674 if (netif_msg_link(qdev))
675 printk(KERN_WARNING PFX
676 "%s Timed out waiting for management port to "
677 "get free before issuing command.\n",
678 qdev->ndev->name);
679 return -1;
680 }
681
682 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
683 PHYAddr[mac_index] | regAddr);
684
685 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
686
687 /* Wait for write to complete 9/10/04 SJP */
688 if (ql_wait_for_mii_ready(qdev)) {
689 if (netif_msg_link(qdev))
690 printk(KERN_WARNING PFX
691 "%s: Timed out waiting for management port to"
692 "get free before issuing command.\n",
693 qdev->ndev->name);
694 return -1;
695 }
696
697 if (scanWasEnabled)
698 ql_mii_enable_scan_mode(qdev);
699
700 return 0;
701 }
702
703 static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
704 u16 * value, u32 mac_index)
705 {
706 struct ql3xxx_port_registers __iomem *port_regs =
707 qdev->mem_map_registers;
708 u8 scanWasEnabled;
709 u32 temp;
710
711 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
712
713 if (ql_wait_for_mii_ready(qdev)) {
714 if (netif_msg_link(qdev))
715 printk(KERN_WARNING PFX
716 "%s: Timed out waiting for management port to "
717 "get free before issuing command.\n",
718 qdev->ndev->name);
719 return -1;
720 }
721
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 PHYAddr[mac_index] | regAddr);
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
726 (MAC_MII_CONTROL_RC << 16));
727
728 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
729 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
730
731 /* Wait for the read to complete */
732 if (ql_wait_for_mii_ready(qdev)) {
733 if (netif_msg_link(qdev))
734 printk(KERN_WARNING PFX
735 "%s: Timed out waiting for management port to "
736 "get free after issuing command.\n",
737 qdev->ndev->name);
738 return -1;
739 }
740
741 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
742 *value = (u16) temp;
743
744 if (scanWasEnabled)
745 ql_mii_enable_scan_mode(qdev);
746
747 return 0;
748 }
749
750 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
751 {
752 struct ql3xxx_port_registers __iomem *port_regs =
753 qdev->mem_map_registers;
754
755 ql_mii_disable_scan_mode(qdev);
756
757 if (ql_wait_for_mii_ready(qdev)) {
758 if (netif_msg_link(qdev))
759 printk(KERN_WARNING PFX
760 "%s: Timed out waiting for management port to "
761 "get free before issuing command.\n",
762 qdev->ndev->name);
763 return -1;
764 }
765
766 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
767 qdev->PHYAddr | regAddr);
768
769 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
770
771 /* Wait for write to complete. */
772 if (ql_wait_for_mii_ready(qdev)) {
773 if (netif_msg_link(qdev))
774 printk(KERN_WARNING PFX
775 "%s: Timed out waiting for management port to "
776 "get free before issuing command.\n",
777 qdev->ndev->name);
778 return -1;
779 }
780
781 ql_mii_enable_scan_mode(qdev);
782
783 return 0;
784 }
785
786 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
787 {
788 u32 temp;
789 struct ql3xxx_port_registers __iomem *port_regs =
790 qdev->mem_map_registers;
791
792 ql_mii_disable_scan_mode(qdev);
793
794 if (ql_wait_for_mii_ready(qdev)) {
795 if (netif_msg_link(qdev))
796 printk(KERN_WARNING PFX
797 "%s: Timed out waiting for management port to "
798 "get free before issuing command.\n",
799 qdev->ndev->name);
800 return -1;
801 }
802
803 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
804 qdev->PHYAddr | regAddr);
805
806 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
807 (MAC_MII_CONTROL_RC << 16));
808
809 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
810 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
811
812 /* Wait for the read to complete */
813 if (ql_wait_for_mii_ready(qdev)) {
814 if (netif_msg_link(qdev))
815 printk(KERN_WARNING PFX
816 "%s: Timed out waiting for management port to "
817 "get free before issuing command.\n",
818 qdev->ndev->name);
819 return -1;
820 }
821
822 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
823 *value = (u16) temp;
824
825 ql_mii_enable_scan_mode(qdev);
826
827 return 0;
828 }
829
830 static void ql_petbi_reset(struct ql3_adapter *qdev)
831 {
832 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
833 }
834
835 static void ql_petbi_start_neg(struct ql3_adapter *qdev)
836 {
837 u16 reg;
838
839 /* Enable Auto-negotiation sense */
840 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
841 reg |= PETBI_TBI_AUTO_SENSE;
842 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
843
844 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
845 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
846
847 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
848 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
849 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
850
851 }
852
853 static void ql_petbi_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
854 {
855 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
856 mac_index);
857 }
858
859 static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
860 {
861 u16 reg;
862
863 /* Enable Auto-negotiation sense */
864 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg, mac_index);
865 reg |= PETBI_TBI_AUTO_SENSE;
866 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, mac_index);
867
868 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
869 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, mac_index);
870
871 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
872 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
873 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
874 mac_index);
875 }
876
877 static void ql_petbi_init(struct ql3_adapter *qdev)
878 {
879 ql_petbi_reset(qdev);
880 ql_petbi_start_neg(qdev);
881 }
882
883 static void ql_petbi_init_ex(struct ql3_adapter *qdev, u32 mac_index)
884 {
885 ql_petbi_reset_ex(qdev, mac_index);
886 ql_petbi_start_neg_ex(qdev, mac_index);
887 }
888
889 static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
890 {
891 u16 reg;
892
893 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
894 return 0;
895
896 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
897 }
898
899 static int ql_phy_get_speed(struct ql3_adapter *qdev)
900 {
901 u16 reg;
902
903 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
904 return 0;
905
906 reg = (((reg & 0x18) >> 3) & 3);
907
908 if (reg == 2)
909 return SPEED_1000;
910 else if (reg == 1)
911 return SPEED_100;
912 else if (reg == 0)
913 return SPEED_10;
914 else
915 return -1;
916 }
917
918 static int ql_is_full_dup(struct ql3_adapter *qdev)
919 {
920 u16 reg;
921
922 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
923 return 0;
924
925 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
926 }
927
928 static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
929 {
930 u16 reg;
931
932 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
933 return 0;
934
935 return (reg & PHY_NEG_PAUSE) != 0;
936 }
937
938 /*
939 * Caller holds hw_lock.
940 */
941 static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
942 {
943 struct ql3xxx_port_registers __iomem *port_regs =
944 qdev->mem_map_registers;
945 u32 value;
946
947 if (enable)
948 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
949 else
950 value = (MAC_CONFIG_REG_PE << 16);
951
952 if (qdev->mac_index)
953 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
954 else
955 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
956 }
957
958 /*
959 * Caller holds hw_lock.
960 */
961 static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
962 {
963 struct ql3xxx_port_registers __iomem *port_regs =
964 qdev->mem_map_registers;
965 u32 value;
966
967 if (enable)
968 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
969 else
970 value = (MAC_CONFIG_REG_SR << 16);
971
972 if (qdev->mac_index)
973 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
974 else
975 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
976 }
977
978 /*
979 * Caller holds hw_lock.
980 */
981 static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
982 {
983 struct ql3xxx_port_registers __iomem *port_regs =
984 qdev->mem_map_registers;
985 u32 value;
986
987 if (enable)
988 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
989 else
990 value = (MAC_CONFIG_REG_GM << 16);
991
992 if (qdev->mac_index)
993 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
994 else
995 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
996 }
997
998 /*
999 * Caller holds hw_lock.
1000 */
1001 static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1002 {
1003 struct ql3xxx_port_registers __iomem *port_regs =
1004 qdev->mem_map_registers;
1005 u32 value;
1006
1007 if (enable)
1008 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1009 else
1010 value = (MAC_CONFIG_REG_FD << 16);
1011
1012 if (qdev->mac_index)
1013 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1014 else
1015 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1016 }
1017
1018 /*
1019 * Caller holds hw_lock.
1020 */
1021 static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1022 {
1023 struct ql3xxx_port_registers __iomem *port_regs =
1024 qdev->mem_map_registers;
1025 u32 value;
1026
1027 if (enable)
1028 value =
1029 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1030 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1031 else
1032 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1033
1034 if (qdev->mac_index)
1035 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1036 else
1037 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1038 }
1039
1040 /*
1041 * Caller holds hw_lock.
1042 */
1043 static int ql_is_fiber(struct ql3_adapter *qdev)
1044 {
1045 struct ql3xxx_port_registers __iomem *port_regs =
1046 qdev->mem_map_registers;
1047 u32 bitToCheck = 0;
1048 u32 temp;
1049
1050 switch (qdev->mac_index) {
1051 case 0:
1052 bitToCheck = PORT_STATUS_SM0;
1053 break;
1054 case 1:
1055 bitToCheck = PORT_STATUS_SM1;
1056 break;
1057 }
1058
1059 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1060 return (temp & bitToCheck) != 0;
1061 }
1062
1063 static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1064 {
1065 u16 reg;
1066 ql_mii_read_reg(qdev, 0x00, &reg);
1067 return (reg & 0x1000) != 0;
1068 }
1069
1070 /*
1071 * Caller holds hw_lock.
1072 */
1073 static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1074 {
1075 struct ql3xxx_port_registers __iomem *port_regs =
1076 qdev->mem_map_registers;
1077 u32 bitToCheck = 0;
1078 u32 temp;
1079
1080 switch (qdev->mac_index) {
1081 case 0:
1082 bitToCheck = PORT_STATUS_AC0;
1083 break;
1084 case 1:
1085 bitToCheck = PORT_STATUS_AC1;
1086 break;
1087 }
1088
1089 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1090 if (temp & bitToCheck) {
1091 if (netif_msg_link(qdev))
1092 printk(KERN_INFO PFX
1093 "%s: Auto-Negotiate complete.\n",
1094 qdev->ndev->name);
1095 return 1;
1096 } else {
1097 if (netif_msg_link(qdev))
1098 printk(KERN_WARNING PFX
1099 "%s: Auto-Negotiate incomplete.\n",
1100 qdev->ndev->name);
1101 return 0;
1102 }
1103 }
1104
1105 /*
1106 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1107 */
1108 static int ql_is_neg_pause(struct ql3_adapter *qdev)
1109 {
1110 if (ql_is_fiber(qdev))
1111 return ql_is_petbi_neg_pause(qdev);
1112 else
1113 return ql_is_phy_neg_pause(qdev);
1114 }
1115
1116 static int ql_auto_neg_error(struct ql3_adapter *qdev)
1117 {
1118 struct ql3xxx_port_registers __iomem *port_regs =
1119 qdev->mem_map_registers;
1120 u32 bitToCheck = 0;
1121 u32 temp;
1122
1123 switch (qdev->mac_index) {
1124 case 0:
1125 bitToCheck = PORT_STATUS_AE0;
1126 break;
1127 case 1:
1128 bitToCheck = PORT_STATUS_AE1;
1129 break;
1130 }
1131 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1132 return (temp & bitToCheck) != 0;
1133 }
1134
1135 static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1136 {
1137 if (ql_is_fiber(qdev))
1138 return SPEED_1000;
1139 else
1140 return ql_phy_get_speed(qdev);
1141 }
1142
1143 static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1144 {
1145 if (ql_is_fiber(qdev))
1146 return 1;
1147 else
1148 return ql_is_full_dup(qdev);
1149 }
1150
1151 /*
1152 * Caller holds hw_lock.
1153 */
1154 static int ql_link_down_detect(struct ql3_adapter *qdev)
1155 {
1156 struct ql3xxx_port_registers __iomem *port_regs =
1157 qdev->mem_map_registers;
1158 u32 bitToCheck = 0;
1159 u32 temp;
1160
1161 switch (qdev->mac_index) {
1162 case 0:
1163 bitToCheck = ISP_CONTROL_LINK_DN_0;
1164 break;
1165 case 1:
1166 bitToCheck = ISP_CONTROL_LINK_DN_1;
1167 break;
1168 }
1169
1170 temp =
1171 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1172 return (temp & bitToCheck) != 0;
1173 }
1174
1175 /*
1176 * Caller holds hw_lock.
1177 */
1178 static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1179 {
1180 struct ql3xxx_port_registers __iomem *port_regs =
1181 qdev->mem_map_registers;
1182
1183 switch (qdev->mac_index) {
1184 case 0:
1185 ql_write_common_reg(qdev,
1186 &port_regs->CommonRegs.ispControlStatus,
1187 (ISP_CONTROL_LINK_DN_0) |
1188 (ISP_CONTROL_LINK_DN_0 << 16));
1189 break;
1190
1191 case 1:
1192 ql_write_common_reg(qdev,
1193 &port_regs->CommonRegs.ispControlStatus,
1194 (ISP_CONTROL_LINK_DN_1) |
1195 (ISP_CONTROL_LINK_DN_1 << 16));
1196 break;
1197
1198 default:
1199 return 1;
1200 }
1201
1202 return 0;
1203 }
1204
1205 /*
1206 * Caller holds hw_lock.
1207 */
1208 static int ql_this_adapter_controls_port(struct ql3_adapter *qdev,
1209 u32 mac_index)
1210 {
1211 struct ql3xxx_port_registers __iomem *port_regs =
1212 qdev->mem_map_registers;
1213 u32 bitToCheck = 0;
1214 u32 temp;
1215
1216 switch (mac_index) {
1217 case 0:
1218 bitToCheck = PORT_STATUS_F1_ENABLED;
1219 break;
1220 case 1:
1221 bitToCheck = PORT_STATUS_F3_ENABLED;
1222 break;
1223 default:
1224 break;
1225 }
1226
1227 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1228 if (temp & bitToCheck) {
1229 if (netif_msg_link(qdev))
1230 printk(KERN_DEBUG PFX
1231 "%s: is not link master.\n", qdev->ndev->name);
1232 return 0;
1233 } else {
1234 if (netif_msg_link(qdev))
1235 printk(KERN_DEBUG PFX
1236 "%s: is link master.\n", qdev->ndev->name);
1237 return 1;
1238 }
1239 }
1240
1241 static void ql_phy_reset_ex(struct ql3_adapter *qdev, u32 mac_index)
1242 {
1243 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, mac_index);
1244 }
1245
1246 static void ql_phy_start_neg_ex(struct ql3_adapter *qdev, u32 mac_index)
1247 {
1248 u16 reg;
1249
1250 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER,
1251 PHY_NEG_PAUSE | PHY_NEG_ADV_SPEED | 1, mac_index);
1252
1253 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, mac_index);
1254 ql_mii_write_reg_ex(qdev, CONTROL_REG, reg | PHY_CTRL_RESTART_NEG,
1255 mac_index);
1256 }
1257
1258 static void ql_phy_init_ex(struct ql3_adapter *qdev, u32 mac_index)
1259 {
1260 ql_phy_reset_ex(qdev, mac_index);
1261 ql_phy_start_neg_ex(qdev, mac_index);
1262 }
1263
1264 /*
1265 * Caller holds hw_lock.
1266 */
1267 static u32 ql_get_link_state(struct ql3_adapter *qdev)
1268 {
1269 struct ql3xxx_port_registers __iomem *port_regs =
1270 qdev->mem_map_registers;
1271 u32 bitToCheck = 0;
1272 u32 temp, linkState;
1273
1274 switch (qdev->mac_index) {
1275 case 0:
1276 bitToCheck = PORT_STATUS_UP0;
1277 break;
1278 case 1:
1279 bitToCheck = PORT_STATUS_UP1;
1280 break;
1281 }
1282 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1283 if (temp & bitToCheck) {
1284 linkState = LS_UP;
1285 } else {
1286 linkState = LS_DOWN;
1287 if (netif_msg_link(qdev))
1288 printk(KERN_WARNING PFX
1289 "%s: Link is down.\n", qdev->ndev->name);
1290 }
1291 return linkState;
1292 }
1293
1294 static int ql_port_start(struct ql3_adapter *qdev)
1295 {
1296 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1297 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1298 2) << 7))
1299 return -1;
1300
1301 if (ql_is_fiber(qdev)) {
1302 ql_petbi_init(qdev);
1303 } else {
1304 /* Copper port */
1305 ql_phy_init_ex(qdev, qdev->mac_index);
1306 }
1307
1308 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1309 return 0;
1310 }
1311
1312 static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1313 {
1314
1315 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1316 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1317 2) << 7))
1318 return -1;
1319
1320 if (!ql_auto_neg_error(qdev)) {
1321 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1322 /* configure the MAC */
1323 if (netif_msg_link(qdev))
1324 printk(KERN_DEBUG PFX
1325 "%s: Configuring link.\n",
1326 qdev->ndev->
1327 name);
1328 ql_mac_cfg_soft_reset(qdev, 1);
1329 ql_mac_cfg_gig(qdev,
1330 (ql_get_link_speed
1331 (qdev) ==
1332 SPEED_1000));
1333 ql_mac_cfg_full_dup(qdev,
1334 ql_is_link_full_dup
1335 (qdev));
1336 ql_mac_cfg_pause(qdev,
1337 ql_is_neg_pause
1338 (qdev));
1339 ql_mac_cfg_soft_reset(qdev, 0);
1340
1341 /* enable the MAC */
1342 if (netif_msg_link(qdev))
1343 printk(KERN_DEBUG PFX
1344 "%s: Enabling mac.\n",
1345 qdev->ndev->
1346 name);
1347 ql_mac_enable(qdev, 1);
1348 }
1349
1350 if (netif_msg_link(qdev))
1351 printk(KERN_DEBUG PFX
1352 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1353 qdev->ndev->name);
1354 qdev->port_link_state = LS_UP;
1355 netif_start_queue(qdev->ndev);
1356 netif_carrier_on(qdev->ndev);
1357 if (netif_msg_link(qdev))
1358 printk(KERN_INFO PFX
1359 "%s: Link is up at %d Mbps, %s duplex.\n",
1360 qdev->ndev->name,
1361 ql_get_link_speed(qdev),
1362 ql_is_link_full_dup(qdev)
1363 ? "full" : "half");
1364
1365 } else { /* Remote error detected */
1366
1367 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1368 if (netif_msg_link(qdev))
1369 printk(KERN_DEBUG PFX
1370 "%s: Remote error detected. "
1371 "Calling ql_port_start().\n",
1372 qdev->ndev->
1373 name);
1374 /*
1375 * ql_port_start() is shared code and needs
1376 * to lock the PHY on it's own.
1377 */
1378 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1379 if(ql_port_start(qdev)) {/* Restart port */
1380 return -1;
1381 } else
1382 return 0;
1383 }
1384 }
1385 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1386 return 0;
1387 }
1388
1389 static void ql_link_state_machine(struct ql3_adapter *qdev)
1390 {
1391 u32 curr_link_state;
1392 unsigned long hw_flags;
1393
1394 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1395
1396 curr_link_state = ql_get_link_state(qdev);
1397
1398 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
1399 if (netif_msg_link(qdev))
1400 printk(KERN_INFO PFX
1401 "%s: Reset in progress, skip processing link "
1402 "state.\n", qdev->ndev->name);
1403
1404 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1405 return;
1406 }
1407
1408 switch (qdev->port_link_state) {
1409 default:
1410 if (test_bit(QL_LINK_MASTER,&qdev->flags)) {
1411 ql_port_start(qdev);
1412 }
1413 qdev->port_link_state = LS_DOWN;
1414 /* Fall Through */
1415
1416 case LS_DOWN:
1417 if (netif_msg_link(qdev))
1418 printk(KERN_DEBUG PFX
1419 "%s: port_link_state = LS_DOWN.\n",
1420 qdev->ndev->name);
1421 if (curr_link_state == LS_UP) {
1422 if (netif_msg_link(qdev))
1423 printk(KERN_DEBUG PFX
1424 "%s: curr_link_state = LS_UP.\n",
1425 qdev->ndev->name);
1426 if (ql_is_auto_neg_complete(qdev))
1427 ql_finish_auto_neg(qdev);
1428
1429 if (qdev->port_link_state == LS_UP)
1430 ql_link_down_detect_clear(qdev);
1431
1432 }
1433 break;
1434
1435 case LS_UP:
1436 /*
1437 * See if the link is currently down or went down and came
1438 * back up
1439 */
1440 if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) {
1441 if (netif_msg_link(qdev))
1442 printk(KERN_INFO PFX "%s: Link is down.\n",
1443 qdev->ndev->name);
1444 qdev->port_link_state = LS_DOWN;
1445 }
1446 break;
1447 }
1448 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1449 }
1450
1451 /*
1452 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1453 */
1454 static void ql_get_phy_owner(struct ql3_adapter *qdev)
1455 {
1456 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1457 set_bit(QL_LINK_MASTER,&qdev->flags);
1458 else
1459 clear_bit(QL_LINK_MASTER,&qdev->flags);
1460 }
1461
1462 /*
1463 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1464 */
1465 static void ql_init_scan_mode(struct ql3_adapter *qdev)
1466 {
1467 ql_mii_enable_scan_mode(qdev);
1468
1469 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1470 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1471 ql_petbi_init_ex(qdev, qdev->mac_index);
1472 } else {
1473 if (ql_this_adapter_controls_port(qdev, qdev->mac_index))
1474 ql_phy_init_ex(qdev, qdev->mac_index);
1475 }
1476 }
1477
1478 /*
1479 * MII_Setup needs to be called before taking the PHY out of reset so that the
1480 * management interface clock speed can be set properly. It would be better if
1481 * we had a way to disable MDC until after the PHY is out of reset, but we
1482 * don't have that capability.
1483 */
1484 static int ql_mii_setup(struct ql3_adapter *qdev)
1485 {
1486 u32 reg;
1487 struct ql3xxx_port_registers __iomem *port_regs =
1488 qdev->mem_map_registers;
1489
1490 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1491 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1492 2) << 7))
1493 return -1;
1494
1495 if (qdev->device_id == QL3032_DEVICE_ID)
1496 ql_write_page0_reg(qdev,
1497 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1498
1499 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1500 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1501
1502 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1503 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1504
1505 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1506 return 0;
1507 }
1508
1509 static u32 ql_supported_modes(struct ql3_adapter *qdev)
1510 {
1511 u32 supported;
1512
1513 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1514 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
1515 | SUPPORTED_Autoneg;
1516 } else {
1517 supported = SUPPORTED_10baseT_Half
1518 | SUPPORTED_10baseT_Full
1519 | SUPPORTED_100baseT_Half
1520 | SUPPORTED_100baseT_Full
1521 | SUPPORTED_1000baseT_Half
1522 | SUPPORTED_1000baseT_Full
1523 | SUPPORTED_Autoneg | SUPPORTED_TP;
1524 }
1525
1526 return supported;
1527 }
1528
1529 static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1530 {
1531 int status;
1532 unsigned long hw_flags;
1533 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1534 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1535 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1536 2) << 7)) {
1537 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1538 return 0;
1539 }
1540 status = ql_is_auto_cfg(qdev);
1541 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1542 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1543 return status;
1544 }
1545
1546 static u32 ql_get_speed(struct ql3_adapter *qdev)
1547 {
1548 u32 status;
1549 unsigned long hw_flags;
1550 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1551 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1552 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1553 2) << 7)) {
1554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1555 return 0;
1556 }
1557 status = ql_get_link_speed(qdev);
1558 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1559 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1560 return status;
1561 }
1562
1563 static int ql_get_full_dup(struct ql3_adapter *qdev)
1564 {
1565 int status;
1566 unsigned long hw_flags;
1567 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1568 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1569 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1570 2) << 7)) {
1571 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1572 return 0;
1573 }
1574 status = ql_is_link_full_dup(qdev);
1575 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1576 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1577 return status;
1578 }
1579
1580
1581 static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1582 {
1583 struct ql3_adapter *qdev = netdev_priv(ndev);
1584
1585 ecmd->transceiver = XCVR_INTERNAL;
1586 ecmd->supported = ql_supported_modes(qdev);
1587
1588 if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) {
1589 ecmd->port = PORT_FIBRE;
1590 } else {
1591 ecmd->port = PORT_TP;
1592 ecmd->phy_address = qdev->PHYAddr;
1593 }
1594 ecmd->advertising = ql_supported_modes(qdev);
1595 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
1596 ecmd->speed = ql_get_speed(qdev);
1597 ecmd->duplex = ql_get_full_dup(qdev);
1598 return 0;
1599 }
1600
1601 static void ql_get_drvinfo(struct net_device *ndev,
1602 struct ethtool_drvinfo *drvinfo)
1603 {
1604 struct ql3_adapter *qdev = netdev_priv(ndev);
1605 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1606 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1607 strncpy(drvinfo->fw_version, "N/A", 32);
1608 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
1609 drvinfo->n_stats = 0;
1610 drvinfo->testinfo_len = 0;
1611 drvinfo->regdump_len = 0;
1612 drvinfo->eedump_len = 0;
1613 }
1614
1615 static u32 ql_get_msglevel(struct net_device *ndev)
1616 {
1617 struct ql3_adapter *qdev = netdev_priv(ndev);
1618 return qdev->msg_enable;
1619 }
1620
1621 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1622 {
1623 struct ql3_adapter *qdev = netdev_priv(ndev);
1624 qdev->msg_enable = value;
1625 }
1626
1627 static const struct ethtool_ops ql3xxx_ethtool_ops = {
1628 .get_settings = ql_get_settings,
1629 .get_drvinfo = ql_get_drvinfo,
1630 .get_perm_addr = ethtool_op_get_perm_addr,
1631 .get_link = ethtool_op_get_link,
1632 .get_msglevel = ql_get_msglevel,
1633 .set_msglevel = ql_set_msglevel,
1634 };
1635
1636 static int ql_populate_free_queue(struct ql3_adapter *qdev)
1637 {
1638 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
1639 dma_addr_t map;
1640 int err;
1641
1642 while (lrg_buf_cb) {
1643 if (!lrg_buf_cb->skb) {
1644 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
1645 qdev->lrg_buffer_len);
1646 if (unlikely(!lrg_buf_cb->skb)) {
1647 printk(KERN_DEBUG PFX
1648 "%s: Failed netdev_alloc_skb().\n",
1649 qdev->ndev->name);
1650 break;
1651 } else {
1652 /*
1653 * We save some space to copy the ethhdr from
1654 * first buffer
1655 */
1656 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1657 map = pci_map_single(qdev->pdev,
1658 lrg_buf_cb->skb->data,
1659 qdev->lrg_buffer_len -
1660 QL_HEADER_SPACE,
1661 PCI_DMA_FROMDEVICE);
1662
1663 err = pci_dma_mapping_error(map);
1664 if(err) {
1665 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
1666 qdev->ndev->name, err);
1667 dev_kfree_skb(lrg_buf_cb->skb);
1668 lrg_buf_cb->skb = NULL;
1669 break;
1670 }
1671
1672
1673 lrg_buf_cb->buf_phy_addr_low =
1674 cpu_to_le32(LS_64BITS(map));
1675 lrg_buf_cb->buf_phy_addr_high =
1676 cpu_to_le32(MS_64BITS(map));
1677 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1678 pci_unmap_len_set(lrg_buf_cb, maplen,
1679 qdev->lrg_buffer_len -
1680 QL_HEADER_SPACE);
1681 --qdev->lrg_buf_skb_check;
1682 if (!qdev->lrg_buf_skb_check)
1683 return 1;
1684 }
1685 }
1686 lrg_buf_cb = lrg_buf_cb->next;
1687 }
1688 return 0;
1689 }
1690
1691 /*
1692 * Caller holds hw_lock.
1693 */
1694 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1695 {
1696 struct bufq_addr_element *lrg_buf_q_ele;
1697 int i;
1698 struct ql_rcv_buf_cb *lrg_buf_cb;
1699 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1700
1701 if ((qdev->lrg_buf_free_count >= 8)
1702 && (qdev->lrg_buf_release_cnt >= 16)) {
1703
1704 if (qdev->lrg_buf_skb_check)
1705 if (!ql_populate_free_queue(qdev))
1706 return;
1707
1708 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1709
1710 while ((qdev->lrg_buf_release_cnt >= 16)
1711 && (qdev->lrg_buf_free_count >= 8)) {
1712
1713 for (i = 0; i < 8; i++) {
1714 lrg_buf_cb =
1715 ql_get_from_lrg_buf_free_list(qdev);
1716 lrg_buf_q_ele->addr_high =
1717 lrg_buf_cb->buf_phy_addr_high;
1718 lrg_buf_q_ele->addr_low =
1719 lrg_buf_cb->buf_phy_addr_low;
1720 lrg_buf_q_ele++;
1721
1722 qdev->lrg_buf_release_cnt--;
1723 }
1724
1725 qdev->lrg_buf_q_producer_index++;
1726
1727 if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries)
1728 qdev->lrg_buf_q_producer_index = 0;
1729
1730 if (qdev->lrg_buf_q_producer_index ==
1731 (qdev->num_lbufq_entries - 1)) {
1732 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1733 }
1734 }
1735
1736 qdev->lrg_buf_next_free = lrg_buf_q_ele;
1737
1738 ql_write_common_reg(qdev,
1739 &port_regs->CommonRegs.
1740 rxLargeQProducerIndex,
1741 qdev->lrg_buf_q_producer_index);
1742 }
1743 }
1744
1745 static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1746 struct ob_mac_iocb_rsp *mac_rsp)
1747 {
1748 struct ql_tx_buf_cb *tx_cb;
1749 int i;
1750 int retval = 0;
1751
1752 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1753 printk(KERN_WARNING "Frame short but, frame was padded and sent.\n");
1754 }
1755
1756 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
1757
1758 /* Check the transmit response flags for any errors */
1759 if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
1760 printk(KERN_ERR "Frame too short to be legal, frame not sent.\n");
1761
1762 qdev->stats.tx_errors++;
1763 retval = -EIO;
1764 goto frame_not_sent;
1765 }
1766
1767 if(tx_cb->seg_count == 0) {
1768 printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id);
1769
1770 qdev->stats.tx_errors++;
1771 retval = -EIO;
1772 goto invalid_seg_count;
1773 }
1774
1775 pci_unmap_single(qdev->pdev,
1776 pci_unmap_addr(&tx_cb->map[0], mapaddr),
1777 pci_unmap_len(&tx_cb->map[0], maplen),
1778 PCI_DMA_TODEVICE);
1779 tx_cb->seg_count--;
1780 if (tx_cb->seg_count) {
1781 for (i = 1; i < tx_cb->seg_count; i++) {
1782 pci_unmap_page(qdev->pdev,
1783 pci_unmap_addr(&tx_cb->map[i],
1784 mapaddr),
1785 pci_unmap_len(&tx_cb->map[i], maplen),
1786 PCI_DMA_TODEVICE);
1787 }
1788 }
1789 qdev->stats.tx_packets++;
1790 qdev->stats.tx_bytes += tx_cb->skb->len;
1791
1792 frame_not_sent:
1793 dev_kfree_skb_irq(tx_cb->skb);
1794 tx_cb->skb = NULL;
1795
1796 invalid_seg_count:
1797 atomic_inc(&qdev->tx_count);
1798 }
1799
1800 void ql_get_sbuf(struct ql3_adapter *qdev)
1801 {
1802 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1803 qdev->small_buf_index = 0;
1804 qdev->small_buf_release_cnt++;
1805 }
1806
1807 struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
1808 {
1809 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1810 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1811 qdev->lrg_buf_release_cnt++;
1812 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1813 qdev->lrg_buf_index = 0;
1814 return(lrg_buf_cb);
1815 }
1816
1817 /*
1818 * The difference between 3022 and 3032 for inbound completions:
1819 * 3022 uses two buffers per completion. The first buffer contains
1820 * (some) header info, the second the remainder of the headers plus
1821 * the data. For this chip we reserve some space at the top of the
1822 * receive buffer so that the header info in buffer one can be
1823 * prepended to the buffer two. Buffer two is the sent up while
1824 * buffer one is returned to the hardware to be reused.
1825 * 3032 receives all of it's data and headers in one buffer for a
1826 * simpler process. 3032 also supports checksum verification as
1827 * can be seen in ql_process_macip_rx_intr().
1828 */
1829 static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
1830 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
1831 {
1832 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1833 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1834 struct sk_buff *skb;
1835 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
1836
1837 /*
1838 * Get the inbound address list (small buffer).
1839 */
1840 ql_get_sbuf(qdev);
1841
1842 if (qdev->device_id == QL3022_DEVICE_ID)
1843 lrg_buf_cb1 = ql_get_lbuf(qdev);
1844
1845 /* start of second buffer */
1846 lrg_buf_cb2 = ql_get_lbuf(qdev);
1847 skb = lrg_buf_cb2->skb;
1848
1849 qdev->stats.rx_packets++;
1850 qdev->stats.rx_bytes += length;
1851
1852 skb_put(skb, length);
1853 pci_unmap_single(qdev->pdev,
1854 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1855 pci_unmap_len(lrg_buf_cb2, maplen),
1856 PCI_DMA_FROMDEVICE);
1857 prefetch(skb->data);
1858 skb->dev = qdev->ndev;
1859 skb->ip_summed = CHECKSUM_NONE;
1860 skb->protocol = eth_type_trans(skb, qdev->ndev);
1861
1862 netif_receive_skb(skb);
1863 qdev->ndev->last_rx = jiffies;
1864 lrg_buf_cb2->skb = NULL;
1865
1866 if (qdev->device_id == QL3022_DEVICE_ID)
1867 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1868 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1869 }
1870
1871 static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
1872 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
1873 {
1874 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
1875 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
1876 struct sk_buff *skb1 = NULL, *skb2;
1877 struct net_device *ndev = qdev->ndev;
1878 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
1879 u16 size = 0;
1880
1881 /*
1882 * Get the inbound address list (small buffer).
1883 */
1884
1885 ql_get_sbuf(qdev);
1886
1887 if (qdev->device_id == QL3022_DEVICE_ID) {
1888 /* start of first buffer on 3022 */
1889 lrg_buf_cb1 = ql_get_lbuf(qdev);
1890 skb1 = lrg_buf_cb1->skb;
1891 size = ETH_HLEN;
1892 if (*((u16 *) skb1->data) != 0xFFFF)
1893 size += VLAN_ETH_HLEN - ETH_HLEN;
1894 }
1895
1896 /* start of second buffer */
1897 lrg_buf_cb2 = ql_get_lbuf(qdev);
1898 skb2 = lrg_buf_cb2->skb;
1899
1900 skb_put(skb2, length); /* Just the second buffer length here. */
1901 pci_unmap_single(qdev->pdev,
1902 pci_unmap_addr(lrg_buf_cb2, mapaddr),
1903 pci_unmap_len(lrg_buf_cb2, maplen),
1904 PCI_DMA_FROMDEVICE);
1905 prefetch(skb2->data);
1906
1907 skb2->ip_summed = CHECKSUM_NONE;
1908 if (qdev->device_id == QL3022_DEVICE_ID) {
1909 /*
1910 * Copy the ethhdr from first buffer to second. This
1911 * is necessary for 3022 IP completions.
1912 */
1913 memcpy(skb_push(skb2, size), skb1->data + VLAN_ID_LEN, size);
1914 } else {
1915 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
1916 if (checksum &
1917 (IB_IP_IOCB_RSP_3032_ICE |
1918 IB_IP_IOCB_RSP_3032_CE |
1919 IB_IP_IOCB_RSP_3032_NUC)) {
1920 printk(KERN_ERR
1921 "%s: Bad checksum for this %s packet, checksum = %x.\n",
1922 __func__,
1923 ((checksum &
1924 IB_IP_IOCB_RSP_3032_TCP) ? "TCP" :
1925 "UDP"),checksum);
1926 } else if (checksum & IB_IP_IOCB_RSP_3032_TCP) {
1927 skb2->ip_summed = CHECKSUM_UNNECESSARY;
1928 }
1929 }
1930 skb2->dev = qdev->ndev;
1931 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
1932
1933 netif_receive_skb(skb2);
1934 qdev->stats.rx_packets++;
1935 qdev->stats.rx_bytes += length;
1936 ndev->last_rx = jiffies;
1937 lrg_buf_cb2->skb = NULL;
1938
1939 if (qdev->device_id == QL3022_DEVICE_ID)
1940 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
1941 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
1942 }
1943
1944 static int ql_tx_rx_clean(struct ql3_adapter *qdev,
1945 int *tx_cleaned, int *rx_cleaned, int work_to_do)
1946 {
1947 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
1948 struct net_rsp_iocb *net_rsp;
1949 struct net_device *ndev = qdev->ndev;
1950 unsigned long hw_flags;
1951 int work_done = 0;
1952
1953 u32 rsp_producer_index = le32_to_cpu(*(qdev->prsp_producer_index));
1954
1955 /* While there are entries in the completion queue. */
1956 while ((rsp_producer_index !=
1957 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
1958
1959 net_rsp = qdev->rsp_current;
1960 switch (net_rsp->opcode) {
1961
1962 case OPCODE_OB_MAC_IOCB_FN0:
1963 case OPCODE_OB_MAC_IOCB_FN2:
1964 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
1965 net_rsp);
1966 (*tx_cleaned)++;
1967 break;
1968
1969 case OPCODE_IB_MAC_IOCB:
1970 case OPCODE_IB_3032_MAC_IOCB:
1971 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
1972 net_rsp);
1973 (*rx_cleaned)++;
1974 break;
1975
1976 case OPCODE_IB_IP_IOCB:
1977 case OPCODE_IB_3032_IP_IOCB:
1978 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
1979 net_rsp);
1980 (*rx_cleaned)++;
1981 break;
1982 default:
1983 {
1984 u32 *tmp = (u32 *) net_rsp;
1985 printk(KERN_ERR PFX
1986 "%s: Hit default case, not "
1987 "handled!\n"
1988 " dropping the packet, opcode = "
1989 "%x.\n",
1990 ndev->name, net_rsp->opcode);
1991 printk(KERN_ERR PFX
1992 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1993 (unsigned long int)tmp[0],
1994 (unsigned long int)tmp[1],
1995 (unsigned long int)tmp[2],
1996 (unsigned long int)tmp[3]);
1997 }
1998 }
1999
2000 qdev->rsp_consumer_index++;
2001
2002 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2003 qdev->rsp_consumer_index = 0;
2004 qdev->rsp_current = qdev->rsp_q_virt_addr;
2005 } else {
2006 qdev->rsp_current++;
2007 }
2008
2009 work_done = *tx_cleaned + *rx_cleaned;
2010 }
2011
2012 if(work_done) {
2013 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2014
2015 ql_update_lrg_bufq_prod_index(qdev);
2016
2017 if (qdev->small_buf_release_cnt >= 16) {
2018 while (qdev->small_buf_release_cnt >= 16) {
2019 qdev->small_buf_q_producer_index++;
2020
2021 if (qdev->small_buf_q_producer_index ==
2022 NUM_SBUFQ_ENTRIES)
2023 qdev->small_buf_q_producer_index = 0;
2024 qdev->small_buf_release_cnt -= 8;
2025 }
2026
2027 wmb();
2028 ql_write_common_reg(qdev,
2029 &port_regs->CommonRegs.
2030 rxSmallQProducerIndex,
2031 qdev->small_buf_q_producer_index);
2032
2033 }
2034
2035 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2036 }
2037
2038 return *tx_cleaned + *rx_cleaned;
2039 }
2040
2041 static int ql_poll(struct net_device *ndev, int *budget)
2042 {
2043 struct ql3_adapter *qdev = netdev_priv(ndev);
2044 int work_to_do = min(*budget, ndev->quota);
2045 int rx_cleaned = 0, tx_cleaned = 0;
2046 unsigned long hw_flags;
2047 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2048
2049 if (!netif_carrier_ok(ndev))
2050 goto quit_polling;
2051
2052 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, work_to_do);
2053 *budget -= rx_cleaned;
2054 ndev->quota -= rx_cleaned;
2055
2056 if( tx_cleaned + rx_cleaned != work_to_do ||
2057 !netif_running(ndev)) {
2058 quit_polling:
2059 netif_rx_complete(ndev);
2060
2061 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
2062 ql_write_common_reg(qdev,
2063 &port_regs->CommonRegs.rspQConsumerIndex,
2064 qdev->rsp_consumer_index);
2065 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2066
2067 ql_enable_interrupts(qdev);
2068 return 0;
2069 }
2070 return 1;
2071 }
2072
2073 static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
2074 {
2075
2076 struct net_device *ndev = dev_id;
2077 struct ql3_adapter *qdev = netdev_priv(ndev);
2078 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2079 u32 value;
2080 int handled = 1;
2081 u32 var;
2082
2083 port_regs = qdev->mem_map_registers;
2084
2085 value =
2086 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
2087
2088 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2089 spin_lock(&qdev->adapter_lock);
2090 netif_stop_queue(qdev->ndev);
2091 netif_carrier_off(qdev->ndev);
2092 ql_disable_interrupts(qdev);
2093 qdev->port_link_state = LS_DOWN;
2094 set_bit(QL_RESET_ACTIVE,&qdev->flags) ;
2095
2096 if (value & ISP_CONTROL_FE) {
2097 /*
2098 * Chip Fatal Error.
2099 */
2100 var =
2101 ql_read_page0_reg_l(qdev,
2102 &port_regs->PortFatalErrStatus);
2103 printk(KERN_WARNING PFX
2104 "%s: Resetting chip. PortFatalErrStatus "
2105 "register = 0x%x\n", ndev->name, var);
2106 set_bit(QL_RESET_START,&qdev->flags) ;
2107 } else {
2108 /*
2109 * Soft Reset Requested.
2110 */
2111 set_bit(QL_RESET_PER_SCSI,&qdev->flags) ;
2112 printk(KERN_ERR PFX
2113 "%s: Another function issued a reset to the "
2114 "chip. ISR value = %x.\n", ndev->name, value);
2115 }
2116 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
2117 spin_unlock(&qdev->adapter_lock);
2118 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2119 ql_disable_interrupts(qdev);
2120 if (likely(netif_rx_schedule_prep(ndev))) {
2121 __netif_rx_schedule(ndev);
2122 }
2123 } else {
2124 return IRQ_NONE;
2125 }
2126
2127 return IRQ_RETVAL(handled);
2128 }
2129
2130 /*
2131 * Get the total number of segments needed for the
2132 * given number of fragments. This is necessary because
2133 * outbound address lists (OAL) will be used when more than
2134 * two frags are given. Each address list has 5 addr/len
2135 * pairs. The 5th pair in each AOL is used to point to
2136 * the next AOL if more frags are coming.
2137 * That is why the frags:segment count ratio is not linear.
2138 */
2139 static int ql_get_seg_count(struct ql3_adapter *qdev,
2140 unsigned short frags)
2141 {
2142 if (qdev->device_id == QL3022_DEVICE_ID)
2143 return 1;
2144
2145 switch(frags) {
2146 case 0: return 1; /* just the skb->data seg */
2147 case 1: return 2; /* skb->data + 1 frag */
2148 case 2: return 3; /* skb->data + 2 frags */
2149 case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */
2150 case 4: return 6;
2151 case 5: return 7;
2152 case 6: return 8;
2153 case 7: return 10;
2154 case 8: return 11;
2155 case 9: return 12;
2156 case 10: return 13;
2157 case 11: return 15;
2158 case 12: return 16;
2159 case 13: return 17;
2160 case 14: return 18;
2161 case 15: return 20;
2162 case 16: return 21;
2163 case 17: return 22;
2164 case 18: return 23;
2165 }
2166 return -1;
2167 }
2168
2169 static void ql_hw_csum_setup(struct sk_buff *skb,
2170 struct ob_mac_iocb_req *mac_iocb_ptr)
2171 {
2172 struct ethhdr *eth;
2173 struct iphdr *ip = NULL;
2174 u8 offset = ETH_HLEN;
2175
2176 eth = (struct ethhdr *)(skb->data);
2177
2178 if (eth->h_proto == __constant_htons(ETH_P_IP)) {
2179 ip = (struct iphdr *)&skb->data[ETH_HLEN];
2180 } else if (eth->h_proto == htons(ETH_P_8021Q) &&
2181 ((struct vlan_ethhdr *)skb->data)->
2182 h_vlan_encapsulated_proto == __constant_htons(ETH_P_IP)) {
2183 ip = (struct iphdr *)&skb->data[VLAN_ETH_HLEN];
2184 offset = VLAN_ETH_HLEN;
2185 }
2186
2187 if (ip) {
2188 if (ip->protocol == IPPROTO_TCP) {
2189 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
2190 OB_3032MAC_IOCB_REQ_IC;
2191 mac_iocb_ptr->ip_hdr_off = offset;
2192 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2193 } else if (ip->protocol == IPPROTO_UDP) {
2194 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
2195 OB_3032MAC_IOCB_REQ_IC;
2196 mac_iocb_ptr->ip_hdr_off = offset;
2197 mac_iocb_ptr->ip_hdr_len = ip->ihl;
2198 }
2199 }
2200 }
2201
2202 /*
2203 * Map the buffers for this transmit. This will return
2204 * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
2205 */
2206 static int ql_send_map(struct ql3_adapter *qdev,
2207 struct ob_mac_iocb_req *mac_iocb_ptr,
2208 struct ql_tx_buf_cb *tx_cb,
2209 struct sk_buff *skb)
2210 {
2211 struct oal *oal;
2212 struct oal_entry *oal_entry;
2213 int len = skb_headlen(skb);
2214 dma_addr_t map;
2215 int err;
2216 int completed_segs, i;
2217 int seg_cnt, seg = 0;
2218 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
2219
2220 seg_cnt = tx_cb->seg_count;
2221 /*
2222 * Map the skb buffer first.
2223 */
2224 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
2225
2226 err = pci_dma_mapping_error(map);
2227 if(err) {
2228 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2229 qdev->ndev->name, err);
2230
2231 return NETDEV_TX_BUSY;
2232 }
2233
2234 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2235 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2236 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2237 oal_entry->len = cpu_to_le32(len);
2238 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2239 pci_unmap_len_set(&tx_cb->map[seg], maplen, len);
2240 seg++;
2241
2242 if (seg_cnt == 1) {
2243 /* Terminate the last segment. */
2244 oal_entry->len =
2245 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2246 } else {
2247 oal = tx_cb->oal;
2248 for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) {
2249 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2250 oal_entry++;
2251 if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2252 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2253 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2254 (seg == 17 && seg_cnt > 18)) {
2255 /* Continuation entry points to outbound address list. */
2256 map = pci_map_single(qdev->pdev, oal,
2257 sizeof(struct oal),
2258 PCI_DMA_TODEVICE);
2259
2260 err = pci_dma_mapping_error(map);
2261 if(err) {
2262
2263 printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n",
2264 qdev->ndev->name, err);
2265 goto map_error;
2266 }
2267
2268 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2269 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2270 oal_entry->len =
2271 cpu_to_le32(sizeof(struct oal) |
2272 OAL_CONT_ENTRY);
2273 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr,
2274 map);
2275 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2276 sizeof(struct oal));
2277 oal_entry = (struct oal_entry *)oal;
2278 oal++;
2279 seg++;
2280 }
2281
2282 map =
2283 pci_map_page(qdev->pdev, frag->page,
2284 frag->page_offset, frag->size,
2285 PCI_DMA_TODEVICE);
2286
2287 err = pci_dma_mapping_error(map);
2288 if(err) {
2289 printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n",
2290 qdev->ndev->name, err);
2291 goto map_error;
2292 }
2293
2294 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2295 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2296 oal_entry->len = cpu_to_le32(frag->size);
2297 pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2298 pci_unmap_len_set(&tx_cb->map[seg], maplen,
2299 frag->size);
2300 }
2301 /* Terminate the last segment. */
2302 oal_entry->len =
2303 cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY);
2304 }
2305
2306 return NETDEV_TX_OK;
2307
2308 map_error:
2309 /* A PCI mapping failed and now we will need to back out
2310 * We need to traverse through the oal's and associated pages which
2311 * have been mapped and now we must unmap them to clean up properly
2312 */
2313
2314 seg = 1;
2315 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2316 oal = tx_cb->oal;
2317 for (i=0; i<completed_segs; i++,seg++) {
2318 oal_entry++;
2319
2320 if((seg == 2 && seg_cnt > 3) || /* Check for continuation */
2321 (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */
2322 (seg == 12 && seg_cnt > 13) || /* but necessary. */
2323 (seg == 17 && seg_cnt > 18)) {
2324 pci_unmap_single(qdev->pdev,
2325 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2326 pci_unmap_len(&tx_cb->map[seg], maplen),
2327 PCI_DMA_TODEVICE);
2328 oal++;
2329 seg++;
2330 }
2331
2332 pci_unmap_page(qdev->pdev,
2333 pci_unmap_addr(&tx_cb->map[seg], mapaddr),
2334 pci_unmap_len(&tx_cb->map[seg], maplen),
2335 PCI_DMA_TODEVICE);
2336 }
2337
2338 pci_unmap_single(qdev->pdev,
2339 pci_unmap_addr(&tx_cb->map[0], mapaddr),
2340 pci_unmap_addr(&tx_cb->map[0], maplen),
2341 PCI_DMA_TODEVICE);
2342
2343 return NETDEV_TX_BUSY;
2344
2345 }
2346
2347 /*
2348 * The difference between 3022 and 3032 sends:
2349 * 3022 only supports a simple single segment transmission.
2350 * 3032 supports checksumming and scatter/gather lists (fragments).
2351 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2352 * in the IOCB plus a chain of outbound address lists (OAL) that
2353 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
2354 * will used to point to an OAL when more ALP entries are required.
2355 * The IOCB is always the top of the chain followed by one or more
2356 * OALs (when necessary).
2357 */
2358 static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev)
2359 {
2360 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
2361 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2362 struct ql_tx_buf_cb *tx_cb;
2363 u32 tot_len = skb->len;
2364 struct ob_mac_iocb_req *mac_iocb_ptr;
2365
2366 if (unlikely(atomic_read(&qdev->tx_count) < 2)) {
2367 return NETDEV_TX_BUSY;
2368 }
2369
2370 tx_cb = &qdev->tx_buf[qdev->req_producer_index] ;
2371 if((tx_cb->seg_count = ql_get_seg_count(qdev,
2372 (skb_shinfo(skb)->nr_frags))) == -1) {
2373 printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__);
2374 return NETDEV_TX_OK;
2375 }
2376
2377 mac_iocb_ptr = tx_cb->queue_entry;
2378 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
2379 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2380 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2381 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2382 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2383 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2384 tx_cb->skb = skb;
2385 if (qdev->device_id == QL3032_DEVICE_ID &&
2386 skb->ip_summed == CHECKSUM_PARTIAL)
2387 ql_hw_csum_setup(skb, mac_iocb_ptr);
2388
2389 if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) {
2390 printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__);
2391 return NETDEV_TX_BUSY;
2392 }
2393
2394 wmb();
2395 qdev->req_producer_index++;
2396 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2397 qdev->req_producer_index = 0;
2398 wmb();
2399 ql_write_common_reg_l(qdev,
2400 &port_regs->CommonRegs.reqQProducerIndex,
2401 qdev->req_producer_index);
2402
2403 ndev->trans_start = jiffies;
2404 if (netif_msg_tx_queued(qdev))
2405 printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n",
2406 ndev->name, qdev->req_producer_index, skb->len);
2407
2408 atomic_dec(&qdev->tx_count);
2409 return NETDEV_TX_OK;
2410 }
2411
2412 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2413 {
2414 qdev->req_q_size =
2415 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2416
2417 qdev->req_q_virt_addr =
2418 pci_alloc_consistent(qdev->pdev,
2419 (size_t) qdev->req_q_size,
2420 &qdev->req_q_phy_addr);
2421
2422 if ((qdev->req_q_virt_addr == NULL) ||
2423 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
2424 printk(KERN_ERR PFX "%s: reqQ failed.\n",
2425 qdev->ndev->name);
2426 return -ENOMEM;
2427 }
2428
2429 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2430
2431 qdev->rsp_q_virt_addr =
2432 pci_alloc_consistent(qdev->pdev,
2433 (size_t) qdev->rsp_q_size,
2434 &qdev->rsp_q_phy_addr);
2435
2436 if ((qdev->rsp_q_virt_addr == NULL) ||
2437 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
2438 printk(KERN_ERR PFX
2439 "%s: rspQ allocation failed\n",
2440 qdev->ndev->name);
2441 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2442 qdev->req_q_virt_addr,
2443 qdev->req_q_phy_addr);
2444 return -ENOMEM;
2445 }
2446
2447 set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2448
2449 return 0;
2450 }
2451
2452 static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2453 {
2454 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) {
2455 printk(KERN_INFO PFX
2456 "%s: Already done.\n", qdev->ndev->name);
2457 return;
2458 }
2459
2460 pci_free_consistent(qdev->pdev,
2461 qdev->req_q_size,
2462 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2463
2464 qdev->req_q_virt_addr = NULL;
2465
2466 pci_free_consistent(qdev->pdev,
2467 qdev->rsp_q_size,
2468 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2469
2470 qdev->rsp_q_virt_addr = NULL;
2471
2472 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags);
2473 }
2474
2475 static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2476 {
2477 /* Create Large Buffer Queue */
2478 qdev->lrg_buf_q_size =
2479 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
2480 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2481 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2482 else
2483 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2484
2485 qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL);
2486 if (qdev->lrg_buf == NULL) {
2487 printk(KERN_ERR PFX
2488 "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name);
2489 return -ENOMEM;
2490 }
2491
2492 qdev->lrg_buf_q_alloc_virt_addr =
2493 pci_alloc_consistent(qdev->pdev,
2494 qdev->lrg_buf_q_alloc_size,
2495 &qdev->lrg_buf_q_alloc_phy_addr);
2496
2497 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
2498 printk(KERN_ERR PFX
2499 "%s: lBufQ failed\n", qdev->ndev->name);
2500 return -ENOMEM;
2501 }
2502 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2503 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2504
2505 /* Create Small Buffer Queue */
2506 qdev->small_buf_q_size =
2507 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
2508 if (qdev->small_buf_q_size < PAGE_SIZE)
2509 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2510 else
2511 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2512
2513 qdev->small_buf_q_alloc_virt_addr =
2514 pci_alloc_consistent(qdev->pdev,
2515 qdev->small_buf_q_alloc_size,
2516 &qdev->small_buf_q_alloc_phy_addr);
2517
2518 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
2519 printk(KERN_ERR PFX
2520 "%s: Small Buffer Queue allocation failed.\n",
2521 qdev->ndev->name);
2522 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2523 qdev->lrg_buf_q_alloc_virt_addr,
2524 qdev->lrg_buf_q_alloc_phy_addr);
2525 return -ENOMEM;
2526 }
2527
2528 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2529 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
2530 set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2531 return 0;
2532 }
2533
2534 static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2535 {
2536 if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) {
2537 printk(KERN_INFO PFX
2538 "%s: Already done.\n", qdev->ndev->name);
2539 return;
2540 }
2541 if(qdev->lrg_buf) kfree(qdev->lrg_buf);
2542 pci_free_consistent(qdev->pdev,
2543 qdev->lrg_buf_q_alloc_size,
2544 qdev->lrg_buf_q_alloc_virt_addr,
2545 qdev->lrg_buf_q_alloc_phy_addr);
2546
2547 qdev->lrg_buf_q_virt_addr = NULL;
2548
2549 pci_free_consistent(qdev->pdev,
2550 qdev->small_buf_q_alloc_size,
2551 qdev->small_buf_q_alloc_virt_addr,
2552 qdev->small_buf_q_alloc_phy_addr);
2553
2554 qdev->small_buf_q_virt_addr = NULL;
2555
2556 clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags);
2557 }
2558
2559 static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2560 {
2561 int i;
2562 struct bufq_addr_element *small_buf_q_entry;
2563
2564 /* Currently we allocate on one of memory and use it for smallbuffers */
2565 qdev->small_buf_total_size =
2566 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2567 QL_SMALL_BUFFER_SIZE);
2568
2569 qdev->small_buf_virt_addr =
2570 pci_alloc_consistent(qdev->pdev,
2571 qdev->small_buf_total_size,
2572 &qdev->small_buf_phy_addr);
2573
2574 if (qdev->small_buf_virt_addr == NULL) {
2575 printk(KERN_ERR PFX
2576 "%s: Failed to get small buffer memory.\n",
2577 qdev->ndev->name);
2578 return -ENOMEM;
2579 }
2580
2581 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2582 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2583
2584 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2585
2586 /* Initialize the small buffer queue. */
2587 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2588 small_buf_q_entry->addr_high =
2589 cpu_to_le32(qdev->small_buf_phy_addr_high);
2590 small_buf_q_entry->addr_low =
2591 cpu_to_le32(qdev->small_buf_phy_addr_low +
2592 (i * QL_SMALL_BUFFER_SIZE));
2593 small_buf_q_entry++;
2594 }
2595 qdev->small_buf_index = 0;
2596 set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags);
2597 return 0;
2598 }
2599
2600 static void ql_free_small_buffers(struct ql3_adapter *qdev)
2601 {
2602 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) {
2603 printk(KERN_INFO PFX
2604 "%s: Already done.\n", qdev->ndev->name);
2605 return;
2606 }
2607 if (qdev->small_buf_virt_addr != NULL) {
2608 pci_free_consistent(qdev->pdev,
2609 qdev->small_buf_total_size,
2610 qdev->small_buf_virt_addr,
2611 qdev->small_buf_phy_addr);
2612
2613 qdev->small_buf_virt_addr = NULL;
2614 }
2615 }
2616
2617 static void ql_free_large_buffers(struct ql3_adapter *qdev)
2618 {
2619 int i = 0;
2620 struct ql_rcv_buf_cb *lrg_buf_cb;
2621
2622 for (i = 0; i < qdev->num_large_buffers; i++) {
2623 lrg_buf_cb = &qdev->lrg_buf[i];
2624 if (lrg_buf_cb->skb) {
2625 dev_kfree_skb(lrg_buf_cb->skb);
2626 pci_unmap_single(qdev->pdev,
2627 pci_unmap_addr(lrg_buf_cb, mapaddr),
2628 pci_unmap_len(lrg_buf_cb, maplen),
2629 PCI_DMA_FROMDEVICE);
2630 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2631 } else {
2632 break;
2633 }
2634 }
2635 }
2636
2637 static void ql_init_large_buffers(struct ql3_adapter *qdev)
2638 {
2639 int i;
2640 struct ql_rcv_buf_cb *lrg_buf_cb;
2641 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2642
2643 for (i = 0; i < qdev->num_large_buffers; i++) {
2644 lrg_buf_cb = &qdev->lrg_buf[i];
2645 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2646 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2647 buf_addr_ele++;
2648 }
2649 qdev->lrg_buf_index = 0;
2650 qdev->lrg_buf_skb_check = 0;
2651 }
2652
2653 static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2654 {
2655 int i;
2656 struct ql_rcv_buf_cb *lrg_buf_cb;
2657 struct sk_buff *skb;
2658 dma_addr_t map;
2659 int err;
2660
2661 for (i = 0; i < qdev->num_large_buffers; i++) {
2662 skb = netdev_alloc_skb(qdev->ndev,
2663 qdev->lrg_buffer_len);
2664 if (unlikely(!skb)) {
2665 /* Better luck next round */
2666 printk(KERN_ERR PFX
2667 "%s: large buff alloc failed, "
2668 "for %d bytes at index %d.\n",
2669 qdev->ndev->name,
2670 qdev->lrg_buffer_len * 2, i);
2671 ql_free_large_buffers(qdev);
2672 return -ENOMEM;
2673 } else {
2674
2675 lrg_buf_cb = &qdev->lrg_buf[i];
2676 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2677 lrg_buf_cb->index = i;
2678 lrg_buf_cb->skb = skb;
2679 /*
2680 * We save some space to copy the ethhdr from first
2681 * buffer
2682 */
2683 skb_reserve(skb, QL_HEADER_SPACE);
2684 map = pci_map_single(qdev->pdev,
2685 skb->data,
2686 qdev->lrg_buffer_len -
2687 QL_HEADER_SPACE,
2688 PCI_DMA_FROMDEVICE);
2689
2690 err = pci_dma_mapping_error(map);
2691 if(err) {
2692 printk(KERN_ERR "%s: PCI mapping failed with error: %d\n",
2693 qdev->ndev->name, err);
2694 ql_free_large_buffers(qdev);
2695 return -ENOMEM;
2696 }
2697
2698 pci_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2699 pci_unmap_len_set(lrg_buf_cb, maplen,
2700 qdev->lrg_buffer_len -
2701 QL_HEADER_SPACE);
2702 lrg_buf_cb->buf_phy_addr_low =
2703 cpu_to_le32(LS_64BITS(map));
2704 lrg_buf_cb->buf_phy_addr_high =
2705 cpu_to_le32(MS_64BITS(map));
2706 }
2707 }
2708 return 0;
2709 }
2710
2711 static void ql_free_send_free_list(struct ql3_adapter *qdev)
2712 {
2713 struct ql_tx_buf_cb *tx_cb;
2714 int i;
2715
2716 tx_cb = &qdev->tx_buf[0];
2717 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2718 if (tx_cb->oal) {
2719 kfree(tx_cb->oal);
2720 tx_cb->oal = NULL;
2721 }
2722 tx_cb++;
2723 }
2724 }
2725
2726 static int ql_create_send_free_list(struct ql3_adapter *qdev)
2727 {
2728 struct ql_tx_buf_cb *tx_cb;
2729 int i;
2730 struct ob_mac_iocb_req *req_q_curr =
2731 qdev->req_q_virt_addr;
2732
2733 /* Create free list of transmit buffers */
2734 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
2735
2736 tx_cb = &qdev->tx_buf[i];
2737 tx_cb->skb = NULL;
2738 tx_cb->queue_entry = req_q_curr;
2739 req_q_curr++;
2740 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2741 if (tx_cb->oal == NULL)
2742 return -1;
2743 }
2744 return 0;
2745 }
2746
2747 static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2748 {
2749 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2750 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
2751 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
2752 }
2753 else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
2754 /*
2755 * Bigger buffers, so less of them.
2756 */
2757 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
2758 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2759 } else {
2760 printk(KERN_ERR PFX
2761 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2762 qdev->ndev->name);
2763 return -ENOMEM;
2764 }
2765 qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
2766 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2767 qdev->max_frame_size =
2768 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
2769
2770 /*
2771 * First allocate a page of shared memory and use it for shadow
2772 * locations of Network Request Queue Consumer Address Register and
2773 * Network Completion Queue Producer Index Register
2774 */
2775 qdev->shadow_reg_virt_addr =
2776 pci_alloc_consistent(qdev->pdev,
2777 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
2778
2779 if (qdev->shadow_reg_virt_addr != NULL) {
2780 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2781 qdev->req_consumer_index_phy_addr_high =
2782 MS_64BITS(qdev->shadow_reg_phy_addr);
2783 qdev->req_consumer_index_phy_addr_low =
2784 LS_64BITS(qdev->shadow_reg_phy_addr);
2785
2786 qdev->prsp_producer_index =
2787 (u32 *) (((u8 *) qdev->preq_consumer_index) + 8);
2788 qdev->rsp_producer_index_phy_addr_high =
2789 qdev->req_consumer_index_phy_addr_high;
2790 qdev->rsp_producer_index_phy_addr_low =
2791 qdev->req_consumer_index_phy_addr_low + 8;
2792 } else {
2793 printk(KERN_ERR PFX
2794 "%s: shadowReg Alloc failed.\n", qdev->ndev->name);
2795 return -ENOMEM;
2796 }
2797
2798 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
2799 printk(KERN_ERR PFX
2800 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2801 qdev->ndev->name);
2802 goto err_req_rsp;
2803 }
2804
2805 if (ql_alloc_buffer_queues(qdev) != 0) {
2806 printk(KERN_ERR PFX
2807 "%s: ql_alloc_buffer_queues failed.\n",
2808 qdev->ndev->name);
2809 goto err_buffer_queues;
2810 }
2811
2812 if (ql_alloc_small_buffers(qdev) != 0) {
2813 printk(KERN_ERR PFX
2814 "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name);
2815 goto err_small_buffers;
2816 }
2817
2818 if (ql_alloc_large_buffers(qdev) != 0) {
2819 printk(KERN_ERR PFX
2820 "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name);
2821 goto err_small_buffers;
2822 }
2823
2824 /* Initialize the large buffer queue. */
2825 ql_init_large_buffers(qdev);
2826 if (ql_create_send_free_list(qdev))
2827 goto err_free_list;
2828
2829 qdev->rsp_current = qdev->rsp_q_virt_addr;
2830
2831 return 0;
2832 err_free_list:
2833 ql_free_send_free_list(qdev);
2834 err_small_buffers:
2835 ql_free_buffer_queues(qdev);
2836 err_buffer_queues:
2837 ql_free_net_req_rsp_queues(qdev);
2838 err_req_rsp:
2839 pci_free_consistent(qdev->pdev,
2840 PAGE_SIZE,
2841 qdev->shadow_reg_virt_addr,
2842 qdev->shadow_reg_phy_addr);
2843
2844 return -ENOMEM;
2845 }
2846
2847 static void ql_free_mem_resources(struct ql3_adapter *qdev)
2848 {
2849 ql_free_send_free_list(qdev);
2850 ql_free_large_buffers(qdev);
2851 ql_free_small_buffers(qdev);
2852 ql_free_buffer_queues(qdev);
2853 ql_free_net_req_rsp_queues(qdev);
2854 if (qdev->shadow_reg_virt_addr != NULL) {
2855 pci_free_consistent(qdev->pdev,
2856 PAGE_SIZE,
2857 qdev->shadow_reg_virt_addr,
2858 qdev->shadow_reg_phy_addr);
2859 qdev->shadow_reg_virt_addr = NULL;
2860 }
2861 }
2862
2863 static int ql_init_misc_registers(struct ql3_adapter *qdev)
2864 {
2865 struct ql3xxx_local_ram_registers __iomem *local_ram =
2866 (void __iomem *)qdev->mem_map_registers;
2867
2868 if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
2869 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2870 2) << 4))
2871 return -1;
2872
2873 ql_write_page2_reg(qdev,
2874 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2875
2876 ql_write_page2_reg(qdev,
2877 &local_ram->maxBufletCount,
2878 qdev->nvram_data.bufletCount);
2879
2880 ql_write_page2_reg(qdev,
2881 &local_ram->freeBufletThresholdLow,
2882 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2883 (qdev->nvram_data.tcpWindowThreshold0));
2884
2885 ql_write_page2_reg(qdev,
2886 &local_ram->freeBufletThresholdHigh,
2887 qdev->nvram_data.tcpWindowThreshold50);
2888
2889 ql_write_page2_reg(qdev,
2890 &local_ram->ipHashTableBase,
2891 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2892 qdev->nvram_data.ipHashTableBaseLo);
2893 ql_write_page2_reg(qdev,
2894 &local_ram->ipHashTableCount,
2895 qdev->nvram_data.ipHashTableSize);
2896 ql_write_page2_reg(qdev,
2897 &local_ram->tcpHashTableBase,
2898 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2899 qdev->nvram_data.tcpHashTableBaseLo);
2900 ql_write_page2_reg(qdev,
2901 &local_ram->tcpHashTableCount,
2902 qdev->nvram_data.tcpHashTableSize);
2903 ql_write_page2_reg(qdev,
2904 &local_ram->ncbBase,
2905 (qdev->nvram_data.ncbTableBaseHi << 16) |
2906 qdev->nvram_data.ncbTableBaseLo);
2907 ql_write_page2_reg(qdev,
2908 &local_ram->maxNcbCount,
2909 qdev->nvram_data.ncbTableSize);
2910 ql_write_page2_reg(qdev,
2911 &local_ram->drbBase,
2912 (qdev->nvram_data.drbTableBaseHi << 16) |
2913 qdev->nvram_data.drbTableBaseLo);
2914 ql_write_page2_reg(qdev,
2915 &local_ram->maxDrbCount,
2916 qdev->nvram_data.drbTableSize);
2917 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
2918 return 0;
2919 }
2920
2921 static int ql_adapter_initialize(struct ql3_adapter *qdev)
2922 {
2923 u32 value;
2924 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
2925 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
2926 (void __iomem *)port_regs;
2927 u32 delay = 10;
2928 int status = 0;
2929
2930 if(ql_mii_setup(qdev))
2931 return -1;
2932
2933 /* Bring out PHY out of reset */
2934 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2935 (ISP_SERIAL_PORT_IF_WE |
2936 (ISP_SERIAL_PORT_IF_WE << 16)));
2937
2938 qdev->port_link_state = LS_DOWN;
2939 netif_carrier_off(qdev->ndev);
2940
2941 /* V2 chip fix for ARS-39168. */
2942 ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
2943 (ISP_SERIAL_PORT_IF_SDE |
2944 (ISP_SERIAL_PORT_IF_SDE << 16)));
2945
2946 /* Request Queue Registers */
2947 *((u32 *) (qdev->preq_consumer_index)) = 0;
2948 atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES);
2949 qdev->req_producer_index = 0;
2950
2951 ql_write_page1_reg(qdev,
2952 &hmem_regs->reqConsumerIndexAddrHigh,
2953 qdev->req_consumer_index_phy_addr_high);
2954 ql_write_page1_reg(qdev,
2955 &hmem_regs->reqConsumerIndexAddrLow,
2956 qdev->req_consumer_index_phy_addr_low);
2957
2958 ql_write_page1_reg(qdev,
2959 &hmem_regs->reqBaseAddrHigh,
2960 MS_64BITS(qdev->req_q_phy_addr));
2961 ql_write_page1_reg(qdev,
2962 &hmem_regs->reqBaseAddrLow,
2963 LS_64BITS(qdev->req_q_phy_addr));
2964 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
2965
2966 /* Response Queue Registers */
2967 *((u16 *) (qdev->prsp_producer_index)) = 0;
2968 qdev->rsp_consumer_index = 0;
2969 qdev->rsp_current = qdev->rsp_q_virt_addr;
2970
2971 ql_write_page1_reg(qdev,
2972 &hmem_regs->rspProducerIndexAddrHigh,
2973 qdev->rsp_producer_index_phy_addr_high);
2974
2975 ql_write_page1_reg(qdev,
2976 &hmem_regs->rspProducerIndexAddrLow,
2977 qdev->rsp_producer_index_phy_addr_low);
2978
2979 ql_write_page1_reg(qdev,
2980 &hmem_regs->rspBaseAddrHigh,
2981 MS_64BITS(qdev->rsp_q_phy_addr));
2982
2983 ql_write_page1_reg(qdev,
2984 &hmem_regs->rspBaseAddrLow,
2985 LS_64BITS(qdev->rsp_q_phy_addr));
2986
2987 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
2988
2989 /* Large Buffer Queue */
2990 ql_write_page1_reg(qdev,
2991 &hmem_regs->rxLargeQBaseAddrHigh,
2992 MS_64BITS(qdev->lrg_buf_q_phy_addr));
2993
2994 ql_write_page1_reg(qdev,
2995 &hmem_regs->rxLargeQBaseAddrLow,
2996 LS_64BITS(qdev->lrg_buf_q_phy_addr));
2997
2998 ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries);
2999
3000 ql_write_page1_reg(qdev,
3001 &hmem_regs->rxLargeBufferLength,
3002 qdev->lrg_buffer_len);
3003
3004 /* Small Buffer Queue */
3005 ql_write_page1_reg(qdev,
3006 &hmem_regs->rxSmallQBaseAddrHigh,
3007 MS_64BITS(qdev->small_buf_q_phy_addr));
3008
3009 ql_write_page1_reg(qdev,
3010 &hmem_regs->rxSmallQBaseAddrLow,
3011 LS_64BITS(qdev->small_buf_q_phy_addr));
3012
3013 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3014 ql_write_page1_reg(qdev,
3015 &hmem_regs->rxSmallBufferLength,
3016 QL_SMALL_BUFFER_SIZE);
3017
3018 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3019 qdev->small_buf_release_cnt = 8;
3020 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
3021 qdev->lrg_buf_release_cnt = 8;
3022 qdev->lrg_buf_next_free =
3023 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3024 qdev->small_buf_index = 0;
3025 qdev->lrg_buf_index = 0;
3026 qdev->lrg_buf_free_count = 0;
3027 qdev->lrg_buf_free_head = NULL;
3028 qdev->lrg_buf_free_tail = NULL;
3029
3030 ql_write_common_reg(qdev,
3031 &port_regs->CommonRegs.
3032 rxSmallQProducerIndex,
3033 qdev->small_buf_q_producer_index);
3034 ql_write_common_reg(qdev,
3035 &port_regs->CommonRegs.
3036 rxLargeQProducerIndex,
3037 qdev->lrg_buf_q_producer_index);
3038
3039 /*
3040 * Find out if the chip has already been initialized. If it has, then
3041 * we skip some of the initialization.
3042 */
3043 clear_bit(QL_LINK_MASTER, &qdev->flags);
3044 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3045 if ((value & PORT_STATUS_IC) == 0) {
3046
3047 /* Chip has not been configured yet, so let it rip. */
3048 if(ql_init_misc_registers(qdev)) {
3049 status = -1;
3050 goto out;
3051 }
3052
3053 if (qdev->mac_index)
3054 ql_write_page0_reg(qdev,
3055 &port_regs->mac1MaxFrameLengthReg,
3056 qdev->max_frame_size);
3057 else
3058 ql_write_page0_reg(qdev,
3059 &port_regs->mac0MaxFrameLengthReg,
3060 qdev->max_frame_size);
3061
3062 value = qdev->nvram_data.tcpMaxWindowSize;
3063 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3064
3065 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3066
3067 if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
3068 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3069 * 2) << 13)) {
3070 status = -1;
3071 goto out;
3072 }
3073 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3074 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3075 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3076 16) | (INTERNAL_CHIP_SD |
3077 INTERNAL_CHIP_WE)));
3078 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3079 }
3080
3081
3082 if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
3083 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3084 2) << 7)) {
3085 status = -1;
3086 goto out;
3087 }
3088
3089 ql_init_scan_mode(qdev);
3090 ql_get_phy_owner(qdev);
3091
3092 /* Load the MAC Configuration */
3093
3094 /* Program lower 32 bits of the MAC address */
3095 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3096 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3097 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3098 ((qdev->ndev->dev_addr[2] << 24)
3099 | (qdev->ndev->dev_addr[3] << 16)
3100 | (qdev->ndev->dev_addr[4] << 8)
3101 | qdev->ndev->dev_addr[5]));
3102
3103 /* Program top 16 bits of the MAC address */
3104 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3105 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3106 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3107 ((qdev->ndev->dev_addr[0] << 8)
3108 | qdev->ndev->dev_addr[1]));
3109
3110 /* Enable Primary MAC */
3111 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3112 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3113 MAC_ADDR_INDIRECT_PTR_REG_PE));
3114
3115 /* Clear Primary and Secondary IP addresses */
3116 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3117 ((IP_ADDR_INDEX_REG_MASK << 16) |
3118 (qdev->mac_index << 2)));
3119 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3120
3121 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3122 ((IP_ADDR_INDEX_REG_MASK << 16) |
3123 ((qdev->mac_index << 2) + 1)));
3124 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3125
3126 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3127
3128 /* Indicate Configuration Complete */
3129 ql_write_page0_reg(qdev,
3130 &port_regs->portControl,
3131 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3132
3133 do {
3134 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3135 if (value & PORT_STATUS_IC)
3136 break;
3137 msleep(500);
3138 } while (--delay);
3139
3140 if (delay == 0) {
3141 printk(KERN_ERR PFX
3142 "%s: Hw Initialization timeout.\n", qdev->ndev->name);
3143 status = -1;
3144 goto out;
3145 }
3146
3147 /* Enable Ethernet Function */
3148 if (qdev->device_id == QL3032_DEVICE_ID) {
3149 value =
3150 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
3151 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4);
3152 ql_write_page0_reg(qdev, &port_regs->functionControl,
3153 ((value << 16) | value));
3154 } else {
3155 value =
3156 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3157 PORT_CONTROL_HH);
3158 ql_write_page0_reg(qdev, &port_regs->portControl,
3159 ((value << 16) | value));
3160 }
3161
3162
3163 out:
3164 return status;
3165 }
3166
3167 /*
3168 * Caller holds hw_lock.
3169 */
3170 static int ql_adapter_reset(struct ql3_adapter *qdev)
3171 {
3172 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3173 int status = 0;
3174 u16 value;
3175 int max_wait_time;
3176
3177 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3178 clear_bit(QL_RESET_DONE, &qdev->flags);
3179
3180 /*
3181 * Issue soft reset to chip.
3182 */
3183 printk(KERN_DEBUG PFX
3184 "%s: Issue soft reset to chip.\n",
3185 qdev->ndev->name);
3186 ql_write_common_reg(qdev,
3187 &port_regs->CommonRegs.ispControlStatus,
3188 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3189
3190 /* Wait 3 seconds for reset to complete. */
3191 printk(KERN_DEBUG PFX
3192 "%s: Wait 10 milliseconds for reset to complete.\n",
3193 qdev->ndev->name);
3194
3195 /* Wait until the firmware tells us the Soft Reset is done */
3196 max_wait_time = 5;
3197 do {
3198 value =
3199 ql_read_common_reg(qdev,
3200 &port_regs->CommonRegs.ispControlStatus);
3201 if ((value & ISP_CONTROL_SR) == 0)
3202 break;
3203
3204 ssleep(1);
3205 } while ((--max_wait_time));
3206
3207 /*
3208 * Also, make sure that the Network Reset Interrupt bit has been
3209 * cleared after the soft reset has taken place.
3210 */
3211 value =
3212 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3213 if (value & ISP_CONTROL_RI) {
3214 printk(KERN_DEBUG PFX
3215 "ql_adapter_reset: clearing RI after reset.\n");
3216 ql_write_common_reg(qdev,
3217 &port_regs->CommonRegs.
3218 ispControlStatus,
3219 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3220 }
3221
3222 if (max_wait_time == 0) {
3223 /* Issue Force Soft Reset */
3224 ql_write_common_reg(qdev,
3225 &port_regs->CommonRegs.
3226 ispControlStatus,
3227 ((ISP_CONTROL_FSR << 16) |
3228 ISP_CONTROL_FSR));
3229 /*
3230 * Wait until the firmware tells us the Force Soft Reset is
3231 * done
3232 */
3233 max_wait_time = 5;
3234 do {
3235 value =
3236 ql_read_common_reg(qdev,
3237 &port_regs->CommonRegs.
3238 ispControlStatus);
3239 if ((value & ISP_CONTROL_FSR) == 0) {
3240 break;
3241 }
3242 ssleep(1);
3243 } while ((--max_wait_time));
3244 }
3245 if (max_wait_time == 0)
3246 status = 1;
3247
3248 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3249 set_bit(QL_RESET_DONE, &qdev->flags);
3250 return status;
3251 }
3252
3253 static void ql_set_mac_info(struct ql3_adapter *qdev)
3254 {
3255 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3256 u32 value, port_status;
3257 u8 func_number;
3258
3259 /* Get the function number */
3260 value =
3261 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3262 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3263 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3264 switch (value & ISP_CONTROL_FN_MASK) {
3265 case ISP_CONTROL_FN0_NET:
3266 qdev->mac_index = 0;
3267 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3268 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3269 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3270 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3271 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3272 if (port_status & PORT_STATUS_SM0)
3273 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3274 else
3275 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3276 break;
3277
3278 case ISP_CONTROL_FN1_NET:
3279 qdev->mac_index = 1;
3280 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
3281 qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number;
3282 qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number;
3283 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3284 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3285 if (port_status & PORT_STATUS_SM1)
3286 set_bit(QL_LINK_OPTICAL,&qdev->flags);
3287 else
3288 clear_bit(QL_LINK_OPTICAL,&qdev->flags);
3289 break;
3290
3291 case ISP_CONTROL_FN0_SCSI:
3292 case ISP_CONTROL_FN1_SCSI:
3293 default:
3294 printk(KERN_DEBUG PFX
3295 "%s: Invalid function number, ispControlStatus = 0x%x\n",
3296 qdev->ndev->name,value);
3297 break;
3298 }
3299 qdev->numPorts = qdev->nvram_data.numPorts;
3300 }
3301
3302 static void ql_display_dev_info(struct net_device *ndev)
3303 {
3304 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3305 struct pci_dev *pdev = qdev->pdev;
3306
3307 printk(KERN_INFO PFX
3308 "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n",
3309 DRV_NAME, qdev->index, qdev->chip_rev_id,
3310 (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022",
3311 qdev->pci_slot);
3312 printk(KERN_INFO PFX
3313 "%s Interface.\n",
3314 test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER");
3315
3316 /*
3317 * Print PCI bus width/type.
3318 */
3319 printk(KERN_INFO PFX
3320 "Bus interface is %s %s.\n",
3321 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3322 ((qdev->pci_x) ? "PCI-X" : "PCI"));
3323
3324 printk(KERN_INFO PFX
3325 "mem IO base address adjusted = 0x%p\n",
3326 qdev->mem_map_registers);
3327 printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq);
3328
3329 if (netif_msg_probe(qdev))
3330 printk(KERN_INFO PFX
3331 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
3332 ndev->name, ndev->dev_addr[0], ndev->dev_addr[1],
3333 ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4],
3334 ndev->dev_addr[5]);
3335 }
3336
3337 static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3338 {
3339 struct net_device *ndev = qdev->ndev;
3340 int retval = 0;
3341
3342 netif_stop_queue(ndev);
3343 netif_carrier_off(ndev);
3344
3345 clear_bit(QL_ADAPTER_UP,&qdev->flags);
3346 clear_bit(QL_LINK_MASTER,&qdev->flags);
3347
3348 ql_disable_interrupts(qdev);
3349
3350 free_irq(qdev->pdev->irq, ndev);
3351
3352 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3353 printk(KERN_INFO PFX
3354 "%s: calling pci_disable_msi().\n", qdev->ndev->name);
3355 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3356 pci_disable_msi(qdev->pdev);
3357 }
3358
3359 del_timer_sync(&qdev->adapter_timer);
3360
3361 netif_poll_disable(ndev);
3362
3363 if (do_reset) {
3364 int soft_reset;
3365 unsigned long hw_flags;
3366
3367 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3368 if (ql_wait_for_drvr_lock(qdev)) {
3369 if ((soft_reset = ql_adapter_reset(qdev))) {
3370 printk(KERN_ERR PFX
3371 "%s: ql_adapter_reset(%d) FAILED!\n",
3372 ndev->name, qdev->index);
3373 }
3374 printk(KERN_ERR PFX
3375 "%s: Releaseing driver lock via chip reset.\n",ndev->name);
3376 } else {
3377 printk(KERN_ERR PFX
3378 "%s: Could not acquire driver lock to do "
3379 "reset!\n", ndev->name);
3380 retval = -1;
3381 }
3382 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3383 }
3384 ql_free_mem_resources(qdev);
3385 return retval;
3386 }
3387
3388 static int ql_adapter_up(struct ql3_adapter *qdev)
3389 {
3390 struct net_device *ndev = qdev->ndev;
3391 int err;
3392 unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED;
3393 unsigned long hw_flags;
3394
3395 if (ql_alloc_mem_resources(qdev)) {
3396 printk(KERN_ERR PFX
3397 "%s Unable to allocate buffers.\n", ndev->name);
3398 return -ENOMEM;
3399 }
3400
3401 if (qdev->msi) {
3402 if (pci_enable_msi(qdev->pdev)) {
3403 printk(KERN_ERR PFX
3404 "%s: User requested MSI, but MSI failed to "
3405 "initialize. Continuing without MSI.\n",
3406 qdev->ndev->name);
3407 qdev->msi = 0;
3408 } else {
3409 printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name);
3410 set_bit(QL_MSI_ENABLED,&qdev->flags);
3411 irq_flags &= ~IRQF_SHARED;
3412 }
3413 }
3414
3415 if ((err = request_irq(qdev->pdev->irq,
3416 ql3xxx_isr,
3417 irq_flags, ndev->name, ndev))) {
3418 printk(KERN_ERR PFX
3419 "%s: Failed to reserve interrupt %d already in use.\n",
3420 ndev->name, qdev->pdev->irq);
3421 goto err_irq;
3422 }
3423
3424 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3425
3426 if ((err = ql_wait_for_drvr_lock(qdev))) {
3427 if ((err = ql_adapter_initialize(qdev))) {
3428 printk(KERN_ERR PFX
3429 "%s: Unable to initialize adapter.\n",
3430 ndev->name);
3431 goto err_init;
3432 }
3433 printk(KERN_ERR PFX
3434 "%s: Releaseing driver lock.\n",ndev->name);
3435 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3436 } else {
3437 printk(KERN_ERR PFX
3438 "%s: Could not aquire driver lock.\n",
3439 ndev->name);
3440 goto err_lock;
3441 }
3442
3443 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3444
3445 set_bit(QL_ADAPTER_UP,&qdev->flags);
3446
3447 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3448
3449 netif_poll_enable(ndev);
3450 ql_enable_interrupts(qdev);
3451 return 0;
3452
3453 err_init:
3454 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3455 err_lock:
3456 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3457 free_irq(qdev->pdev->irq, ndev);
3458 err_irq:
3459 if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) {
3460 printk(KERN_INFO PFX
3461 "%s: calling pci_disable_msi().\n",
3462 qdev->ndev->name);
3463 clear_bit(QL_MSI_ENABLED,&qdev->flags);
3464 pci_disable_msi(qdev->pdev);
3465 }
3466 return err;
3467 }
3468
3469 static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3470 {
3471 if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) {
3472 printk(KERN_ERR PFX
3473 "%s: Driver up/down cycle failed, "
3474 "closing device\n",qdev->ndev->name);
3475 dev_close(qdev->ndev);
3476 return -1;
3477 }
3478 return 0;
3479 }
3480
3481 static int ql3xxx_close(struct net_device *ndev)
3482 {
3483 struct ql3_adapter *qdev = netdev_priv(ndev);
3484
3485 /*
3486 * Wait for device to recover from a reset.
3487 * (Rarely happens, but possible.)
3488 */
3489 while (!test_bit(QL_ADAPTER_UP,&qdev->flags))
3490 msleep(50);
3491
3492 ql_adapter_down(qdev,QL_DO_RESET);
3493 return 0;
3494 }
3495
3496 static int ql3xxx_open(struct net_device *ndev)
3497 {
3498 struct ql3_adapter *qdev = netdev_priv(ndev);
3499 return (ql_adapter_up(qdev));
3500 }
3501
3502 static struct net_device_stats *ql3xxx_get_stats(struct net_device *dev)
3503 {
3504 struct ql3_adapter *qdev = (struct ql3_adapter *)dev->priv;
3505 return &qdev->stats;
3506 }
3507
3508 static void ql3xxx_set_multicast_list(struct net_device *ndev)
3509 {
3510 /*
3511 * We are manually parsing the list in the net_device structure.
3512 */
3513 return;
3514 }
3515
3516 static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3517 {
3518 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3519 struct ql3xxx_port_registers __iomem *port_regs =
3520 qdev->mem_map_registers;
3521 struct sockaddr *addr = p;
3522 unsigned long hw_flags;
3523
3524 if (netif_running(ndev))
3525 return -EBUSY;
3526
3527 if (!is_valid_ether_addr(addr->sa_data))
3528 return -EADDRNOTAVAIL;
3529
3530 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3531
3532 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3533 /* Program lower 32 bits of the MAC address */
3534 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3535 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3536 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3537 ((ndev->dev_addr[2] << 24) | (ndev->
3538 dev_addr[3] << 16) |
3539 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3540
3541 /* Program top 16 bits of the MAC address */
3542 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3543 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3544 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3545 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3546 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3547
3548 return 0;
3549 }
3550
3551 static void ql3xxx_tx_timeout(struct net_device *ndev)
3552 {
3553 struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev);
3554
3555 printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name);
3556 /*
3557 * Stop the queues, we've got a problem.
3558 */
3559 netif_stop_queue(ndev);
3560
3561 /*
3562 * Wake up the worker to process this event.
3563 */
3564 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
3565 }
3566
3567 static void ql_reset_work(struct work_struct *work)
3568 {
3569 struct ql3_adapter *qdev =
3570 container_of(work, struct ql3_adapter, reset_work.work);
3571 struct net_device *ndev = qdev->ndev;
3572 u32 value;
3573 struct ql_tx_buf_cb *tx_cb;
3574 int max_wait_time, i;
3575 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3576 unsigned long hw_flags;
3577
3578 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) {
3579 clear_bit(QL_LINK_MASTER,&qdev->flags);
3580
3581 /*
3582 * Loop through the active list and return the skb.
3583 */
3584 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
3585 int j;
3586 tx_cb = &qdev->tx_buf[i];
3587 if (tx_cb->skb) {
3588 printk(KERN_DEBUG PFX
3589 "%s: Freeing lost SKB.\n",
3590 qdev->ndev->name);
3591 pci_unmap_single(qdev->pdev,
3592 pci_unmap_addr(&tx_cb->map[0], mapaddr),
3593 pci_unmap_len(&tx_cb->map[0], maplen),
3594 PCI_DMA_TODEVICE);
3595 for(j=1;j<tx_cb->seg_count;j++) {
3596 pci_unmap_page(qdev->pdev,
3597 pci_unmap_addr(&tx_cb->map[j],mapaddr),
3598 pci_unmap_len(&tx_cb->map[j],maplen),
3599 PCI_DMA_TODEVICE);
3600 }
3601 dev_kfree_skb(tx_cb->skb);
3602 tx_cb->skb = NULL;
3603 }
3604 }
3605
3606 printk(KERN_ERR PFX
3607 "%s: Clearing NRI after reset.\n", qdev->ndev->name);
3608 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3609 ql_write_common_reg(qdev,
3610 &port_regs->CommonRegs.
3611 ispControlStatus,
3612 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3613 /*
3614 * Wait the for Soft Reset to Complete.
3615 */
3616 max_wait_time = 10;
3617 do {
3618 value = ql_read_common_reg(qdev,
3619 &port_regs->CommonRegs.
3620
3621 ispControlStatus);
3622 if ((value & ISP_CONTROL_SR) == 0) {
3623 printk(KERN_DEBUG PFX
3624 "%s: reset completed.\n",
3625 qdev->ndev->name);
3626 break;
3627 }
3628
3629 if (value & ISP_CONTROL_RI) {
3630 printk(KERN_DEBUG PFX
3631 "%s: clearing NRI after reset.\n",
3632 qdev->ndev->name);
3633 ql_write_common_reg(qdev,
3634 &port_regs->
3635 CommonRegs.
3636 ispControlStatus,
3637 ((ISP_CONTROL_RI <<
3638 16) | ISP_CONTROL_RI));
3639 }
3640
3641 ssleep(1);
3642 } while (--max_wait_time);
3643 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3644
3645 if (value & ISP_CONTROL_SR) {
3646
3647 /*
3648 * Set the reset flags and clear the board again.
3649 * Nothing else to do...
3650 */
3651 printk(KERN_ERR PFX
3652 "%s: Timed out waiting for reset to "
3653 "complete.\n", ndev->name);
3654 printk(KERN_ERR PFX
3655 "%s: Do a reset.\n", ndev->name);
3656 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3657 clear_bit(QL_RESET_START,&qdev->flags);
3658 ql_cycle_adapter(qdev,QL_DO_RESET);
3659 return;
3660 }
3661
3662 clear_bit(QL_RESET_ACTIVE,&qdev->flags);
3663 clear_bit(QL_RESET_PER_SCSI,&qdev->flags);
3664 clear_bit(QL_RESET_START,&qdev->flags);
3665 ql_cycle_adapter(qdev,QL_NO_RESET);
3666 }
3667 }
3668
3669 static void ql_tx_timeout_work(struct work_struct *work)
3670 {
3671 struct ql3_adapter *qdev =
3672 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3673
3674 ql_cycle_adapter(qdev, QL_DO_RESET);
3675 }
3676
3677 static void ql_get_board_info(struct ql3_adapter *qdev)
3678 {
3679 struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
3680 u32 value;
3681
3682 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3683
3684 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3685 if (value & PORT_STATUS_64)
3686 qdev->pci_width = 64;
3687 else
3688 qdev->pci_width = 32;
3689 if (value & PORT_STATUS_X)
3690 qdev->pci_x = 1;
3691 else
3692 qdev->pci_x = 0;
3693 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3694 }
3695
3696 static void ql3xxx_timer(unsigned long ptr)
3697 {
3698 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3699
3700 if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) {
3701 printk(KERN_DEBUG PFX
3702 "%s: Reset in progress.\n",
3703 qdev->ndev->name);
3704 goto end;
3705 }
3706
3707 ql_link_state_machine(qdev);
3708
3709 /* Restart timer on 2 second interval. */
3710 end:
3711 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3712 }
3713
3714 static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3715 const struct pci_device_id *pci_entry)
3716 {
3717 struct net_device *ndev = NULL;
3718 struct ql3_adapter *qdev = NULL;
3719 static int cards_found = 0;
3720 int pci_using_dac, err;
3721
3722 err = pci_enable_device(pdev);
3723 if (err) {
3724 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3725 pci_name(pdev));
3726 goto err_out;
3727 }
3728
3729 err = pci_request_regions(pdev, DRV_NAME);
3730 if (err) {
3731 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3732 pci_name(pdev));
3733 goto err_out_disable_pdev;
3734 }
3735
3736 pci_set_master(pdev);
3737
3738 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3739 pci_using_dac = 1;
3740 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3741 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3742 pci_using_dac = 0;
3743 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3744 }
3745
3746 if (err) {
3747 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3748 pci_name(pdev));
3749 goto err_out_free_regions;
3750 }
3751
3752 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
3753 if (!ndev) {
3754 printk(KERN_ERR PFX "%s could not alloc etherdev\n",
3755 pci_name(pdev));
3756 err = -ENOMEM;
3757 goto err_out_free_regions;
3758 }
3759
3760 SET_MODULE_OWNER(ndev);
3761 SET_NETDEV_DEV(ndev, &pdev->dev);
3762
3763 pci_set_drvdata(pdev, ndev);
3764
3765 qdev = netdev_priv(ndev);
3766 qdev->index = cards_found;
3767 qdev->ndev = ndev;
3768 qdev->pdev = pdev;
3769 qdev->device_id = pci_entry->device;
3770 qdev->port_link_state = LS_DOWN;
3771 if (msi)
3772 qdev->msi = 1;
3773
3774 qdev->msg_enable = netif_msg_init(debug, default_msg);
3775
3776 if (pci_using_dac)
3777 ndev->features |= NETIF_F_HIGHDMA;
3778 if (qdev->device_id == QL3032_DEVICE_ID)
3779 ndev->features |= (NETIF_F_HW_CSUM | NETIF_F_SG);
3780
3781 qdev->mem_map_registers =
3782 ioremap_nocache(pci_resource_start(pdev, 1),
3783 pci_resource_len(qdev->pdev, 1));
3784 if (!qdev->mem_map_registers) {
3785 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3786 pci_name(pdev));
3787 err = -EIO;
3788 goto err_out_free_ndev;
3789 }
3790
3791 spin_lock_init(&qdev->adapter_lock);
3792 spin_lock_init(&qdev->hw_lock);
3793
3794 /* Set driver entry points */
3795 ndev->open = ql3xxx_open;
3796 ndev->hard_start_xmit = ql3xxx_send;
3797 ndev->stop = ql3xxx_close;
3798 ndev->get_stats = ql3xxx_get_stats;
3799 ndev->set_multicast_list = ql3xxx_set_multicast_list;
3800 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
3801 ndev->set_mac_address = ql3xxx_set_mac_address;
3802 ndev->tx_timeout = ql3xxx_tx_timeout;
3803 ndev->watchdog_timeo = 5 * HZ;
3804
3805 ndev->poll = &ql_poll;
3806 ndev->weight = 64;
3807
3808 ndev->irq = pdev->irq;
3809
3810 /* make sure the EEPROM is good */
3811 if (ql_get_nvram_params(qdev)) {
3812 printk(KERN_ALERT PFX
3813 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3814 qdev->index);
3815 err = -EIO;
3816 goto err_out_iounmap;
3817 }
3818
3819 ql_set_mac_info(qdev);
3820
3821 /* Validate and set parameters */
3822 if (qdev->mac_index) {
3823 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
3824 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress,
3825 ETH_ALEN);
3826 } else {
3827 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
3828 memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress,
3829 ETH_ALEN);
3830 }
3831 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3832
3833 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3834
3835 /* Turn off support for multicasting */
3836 ndev->flags &= ~IFF_MULTICAST;
3837
3838 /* Record PCI bus information. */
3839 ql_get_board_info(qdev);
3840
3841 /*
3842 * Set the Maximum Memory Read Byte Count value. We do this to handle
3843 * jumbo frames.
3844 */
3845 if (qdev->pci_x) {
3846 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
3847 }
3848
3849 err = register_netdev(ndev);
3850 if (err) {
3851 printk(KERN_ERR PFX "%s: cannot register net device\n",
3852 pci_name(pdev));
3853 goto err_out_iounmap;
3854 }
3855
3856 /* we're going to reset, so assume we have no link for now */
3857
3858 netif_carrier_off(ndev);
3859 netif_stop_queue(ndev);
3860
3861 qdev->workqueue = create_singlethread_workqueue(ndev->name);
3862 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3863 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3864
3865 init_timer(&qdev->adapter_timer);
3866 qdev->adapter_timer.function = ql3xxx_timer;
3867 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3868 qdev->adapter_timer.data = (unsigned long)qdev;
3869
3870 if(!cards_found) {
3871 printk(KERN_ALERT PFX "%s\n", DRV_STRING);
3872 printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n",
3873 DRV_NAME, DRV_VERSION);
3874 }
3875 ql_display_dev_info(ndev);
3876
3877 cards_found++;
3878 return 0;
3879
3880 err_out_iounmap:
3881 iounmap(qdev->mem_map_registers);
3882 err_out_free_ndev:
3883 free_netdev(ndev);
3884 err_out_free_regions:
3885 pci_release_regions(pdev);
3886 err_out_disable_pdev:
3887 pci_disable_device(pdev);
3888 pci_set_drvdata(pdev, NULL);
3889 err_out:
3890 return err;
3891 }
3892
3893 static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3894 {
3895 struct net_device *ndev = pci_get_drvdata(pdev);
3896 struct ql3_adapter *qdev = netdev_priv(ndev);
3897
3898 unregister_netdev(ndev);
3899 qdev = netdev_priv(ndev);
3900
3901 ql_disable_interrupts(qdev);
3902
3903 if (qdev->workqueue) {
3904 cancel_delayed_work(&qdev->reset_work);
3905 cancel_delayed_work(&qdev->tx_timeout_work);
3906 destroy_workqueue(qdev->workqueue);
3907 qdev->workqueue = NULL;
3908 }
3909
3910 iounmap(qdev->mem_map_registers);
3911 pci_release_regions(pdev);
3912 pci_set_drvdata(pdev, NULL);
3913 free_netdev(ndev);
3914 }
3915
3916 static struct pci_driver ql3xxx_driver = {
3917
3918 .name = DRV_NAME,
3919 .id_table = ql3xxx_pci_tbl,
3920 .probe = ql3xxx_probe,
3921 .remove = __devexit_p(ql3xxx_remove),
3922 };
3923
3924 static int __init ql3xxx_init_module(void)
3925 {
3926 return pci_register_driver(&ql3xxx_driver);
3927 }
3928
3929 static void __exit ql3xxx_exit(void)
3930 {
3931 pci_unregister_driver(&ql3xxx_driver);
3932 }
3933
3934 module_init(ql3xxx_init_module);
3935 module_exit(ql3xxx_exit);
Linux kernel - Deliverables
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