2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
5 * See LICENSE.qla3xxx for copyright and licensing details.
8 #include <linux/kernel.h>
9 #include <linux/init.h>
10 #include <linux/types.h>
11 #include <linux/module.h>
12 #include <linux/list.h>
13 #include <linux/pci.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/sched.h>
16 #include <linux/slab.h>
17 #include <linux/dmapool.h>
18 #include <linux/mempool.h>
19 #include <linux/spinlock.h>
20 #include <linux/kthread.h>
21 #include <linux/interrupt.h>
22 #include <linux/errno.h>
23 #include <linux/ioport.h>
25 #include <linux/if_arp.h>
26 #include <linux/if_ether.h>
27 #include <linux/netdevice.h>
28 #include <linux/etherdevice.h>
29 #include <linux/ethtool.h>
30 #include <linux/skbuff.h>
31 #include <linux/rtnetlink.h>
32 #include <linux/if_vlan.h>
33 #include <linux/init.h>
34 #include <linux/delay.h>
39 #define DRV_NAME "qla3xxx"
40 #define DRV_STRING "QLogic ISP3XXX Network Driver"
41 #define DRV_VERSION "v2.02.00-k36"
42 #define PFX DRV_NAME " "
44 static const char ql3xxx_driver_name
[] = DRV_NAME
;
45 static const char ql3xxx_driver_version
[] = DRV_VERSION
;
47 MODULE_AUTHOR("QLogic Corporation");
48 MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION
" ");
49 MODULE_LICENSE("GPL");
50 MODULE_VERSION(DRV_VERSION
);
52 static const u32 default_msg
53 = NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
54 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
56 static int debug
= -1; /* defaults above */
57 module_param(debug
, int, 0);
58 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
61 module_param(msi
, int, 0);
62 MODULE_PARM_DESC(msi
, "Turn on Message Signaled Interrupts.");
64 static struct pci_device_id ql3xxx_pci_tbl
[] __devinitdata
= {
65 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC
, QL3022_DEVICE_ID
)},
66 /* required last entry */
70 MODULE_DEVICE_TABLE(pci
, ql3xxx_pci_tbl
);
73 * Caller must take hw_lock.
75 static int ql_sem_spinlock(struct ql3_adapter
*qdev
,
76 u32 sem_mask
, u32 sem_bits
)
78 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
80 unsigned int seconds
= 3;
83 writel((sem_mask
| sem_bits
),
84 &port_regs
->CommonRegs
.semaphoreReg
);
85 value
= readl(&port_regs
->CommonRegs
.semaphoreReg
);
86 if ((value
& (sem_mask
>> 16)) == sem_bits
)
93 static void ql_sem_unlock(struct ql3_adapter
*qdev
, u32 sem_mask
)
95 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
96 writel(sem_mask
, &port_regs
->CommonRegs
.semaphoreReg
);
97 readl(&port_regs
->CommonRegs
.semaphoreReg
);
100 static int ql_sem_lock(struct ql3_adapter
*qdev
, u32 sem_mask
, u32 sem_bits
)
102 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
105 writel((sem_mask
| sem_bits
), &port_regs
->CommonRegs
.semaphoreReg
);
106 value
= readl(&port_regs
->CommonRegs
.semaphoreReg
);
107 return ((value
& (sem_mask
>> 16)) == sem_bits
);
111 * Caller holds hw_lock.
113 static int ql_wait_for_drvr_lock(struct ql3_adapter
*qdev
)
118 if (!ql_sem_lock(qdev
,
120 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
)
126 printk(KERN_ERR PFX
"%s: Timed out waiting for "
132 printk(KERN_DEBUG PFX
133 "%s: driver lock acquired.\n",
140 static void ql_set_register_page(struct ql3_adapter
*qdev
, u32 page
)
142 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
144 writel(((ISP_CONTROL_NP_MASK
<< 16) | page
),
145 &port_regs
->CommonRegs
.ispControlStatus
);
146 readl(&port_regs
->CommonRegs
.ispControlStatus
);
147 qdev
->current_page
= page
;
150 static u32
ql_read_common_reg_l(struct ql3_adapter
*qdev
,
154 unsigned long hw_flags
;
156 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
158 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
163 static u32
ql_read_common_reg(struct ql3_adapter
*qdev
,
169 static u32
ql_read_page0_reg_l(struct ql3_adapter
*qdev
, u32 __iomem
*reg
)
172 unsigned long hw_flags
;
174 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
176 if (qdev
->current_page
!= 0)
177 ql_set_register_page(qdev
,0);
180 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
184 static u32
ql_read_page0_reg(struct ql3_adapter
*qdev
, u32 __iomem
*reg
)
186 if (qdev
->current_page
!= 0)
187 ql_set_register_page(qdev
,0);
191 static void ql_write_common_reg_l(struct ql3_adapter
*qdev
,
192 u32 __iomem
*reg
, u32 value
)
194 unsigned long hw_flags
;
196 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
199 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
203 static void ql_write_common_reg(struct ql3_adapter
*qdev
,
204 u32 __iomem
*reg
, u32 value
)
211 static void ql_write_page0_reg(struct ql3_adapter
*qdev
,
212 u32 __iomem
*reg
, u32 value
)
214 if (qdev
->current_page
!= 0)
215 ql_set_register_page(qdev
,0);
222 * Caller holds hw_lock. Only called during init.
224 static void ql_write_page1_reg(struct ql3_adapter
*qdev
,
225 u32 __iomem
*reg
, u32 value
)
227 if (qdev
->current_page
!= 1)
228 ql_set_register_page(qdev
,1);
235 * Caller holds hw_lock. Only called during init.
237 static void ql_write_page2_reg(struct ql3_adapter
*qdev
,
238 u32 __iomem
*reg
, u32 value
)
240 if (qdev
->current_page
!= 2)
241 ql_set_register_page(qdev
,2);
247 static void ql_disable_interrupts(struct ql3_adapter
*qdev
)
249 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
251 ql_write_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispInterruptMaskReg
,
252 (ISP_IMR_ENABLE_INT
<< 16));
256 static void ql_enable_interrupts(struct ql3_adapter
*qdev
)
258 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
260 ql_write_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispInterruptMaskReg
,
261 ((0xff << 16) | ISP_IMR_ENABLE_INT
));
265 static void ql_release_to_lrg_buf_free_list(struct ql3_adapter
*qdev
,
266 struct ql_rcv_buf_cb
*lrg_buf_cb
)
269 lrg_buf_cb
->next
= NULL
;
271 if (qdev
->lrg_buf_free_tail
== NULL
) { /* The list is empty */
272 qdev
->lrg_buf_free_head
= qdev
->lrg_buf_free_tail
= lrg_buf_cb
;
274 qdev
->lrg_buf_free_tail
->next
= lrg_buf_cb
;
275 qdev
->lrg_buf_free_tail
= lrg_buf_cb
;
278 if (!lrg_buf_cb
->skb
) {
279 lrg_buf_cb
->skb
= dev_alloc_skb(qdev
->lrg_buffer_len
);
280 if (unlikely(!lrg_buf_cb
->skb
)) {
281 printk(KERN_ERR PFX
"%s: failed dev_alloc_skb().\n",
283 qdev
->lrg_buf_skb_check
++;
286 * We save some space to copy the ethhdr from first
289 skb_reserve(lrg_buf_cb
->skb
, QL_HEADER_SPACE
);
290 map
= pci_map_single(qdev
->pdev
,
291 lrg_buf_cb
->skb
->data
,
292 qdev
->lrg_buffer_len
-
295 lrg_buf_cb
->buf_phy_addr_low
=
296 cpu_to_le32(LS_64BITS(map
));
297 lrg_buf_cb
->buf_phy_addr_high
=
298 cpu_to_le32(MS_64BITS(map
));
299 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
300 pci_unmap_len_set(lrg_buf_cb
, maplen
,
301 qdev
->lrg_buffer_len
-
306 qdev
->lrg_buf_free_count
++;
309 static struct ql_rcv_buf_cb
*ql_get_from_lrg_buf_free_list(struct ql3_adapter
312 struct ql_rcv_buf_cb
*lrg_buf_cb
;
314 if ((lrg_buf_cb
= qdev
->lrg_buf_free_head
) != NULL
) {
315 if ((qdev
->lrg_buf_free_head
= lrg_buf_cb
->next
) == NULL
)
316 qdev
->lrg_buf_free_tail
= NULL
;
317 qdev
->lrg_buf_free_count
--;
323 static u32 addrBits
= EEPROM_NO_ADDR_BITS
;
324 static u32 dataBits
= EEPROM_NO_DATA_BITS
;
326 static void fm93c56a_deselect(struct ql3_adapter
*qdev
);
327 static void eeprom_readword(struct ql3_adapter
*qdev
, u32 eepromAddr
,
328 unsigned short *value
);
331 * Caller holds hw_lock.
333 static void fm93c56a_select(struct ql3_adapter
*qdev
)
335 struct ql3xxx_port_registers __iomem
*port_regs
=
336 qdev
->mem_map_registers
;
338 qdev
->eeprom_cmd_data
= AUBURN_EEPROM_CS_1
;
339 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
340 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
);
341 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
342 ((ISP_NVRAM_MASK
<< 16) | qdev
->eeprom_cmd_data
));
346 * Caller holds hw_lock.
348 static void fm93c56a_cmd(struct ql3_adapter
*qdev
, u32 cmd
, u32 eepromAddr
)
354 struct ql3xxx_port_registers __iomem
*port_regs
=
355 qdev
->mem_map_registers
;
357 /* Clock in a zero, then do the start bit */
358 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
359 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
361 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
362 ISP_NVRAM_MASK
| qdev
->
363 eeprom_cmd_data
| AUBURN_EEPROM_DO_1
|
364 AUBURN_EEPROM_CLK_RISE
);
365 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
366 ISP_NVRAM_MASK
| qdev
->
367 eeprom_cmd_data
| AUBURN_EEPROM_DO_1
|
368 AUBURN_EEPROM_CLK_FALL
);
370 mask
= 1 << (FM93C56A_CMD_BITS
- 1);
371 /* Force the previous data bit to be different */
372 previousBit
= 0xffff;
373 for (i
= 0; i
< FM93C56A_CMD_BITS
; i
++) {
375 (cmd
& mask
) ? AUBURN_EEPROM_DO_1
: AUBURN_EEPROM_DO_0
;
376 if (previousBit
!= dataBit
) {
378 * If the bit changed, then change the DO state to
381 ql_write_common_reg(qdev
,
382 &port_regs
->CommonRegs
.
383 serialPortInterfaceReg
,
384 ISP_NVRAM_MASK
| qdev
->
385 eeprom_cmd_data
| dataBit
);
386 previousBit
= dataBit
;
388 ql_write_common_reg(qdev
,
389 &port_regs
->CommonRegs
.
390 serialPortInterfaceReg
,
391 ISP_NVRAM_MASK
| qdev
->
392 eeprom_cmd_data
| dataBit
|
393 AUBURN_EEPROM_CLK_RISE
);
394 ql_write_common_reg(qdev
,
395 &port_regs
->CommonRegs
.
396 serialPortInterfaceReg
,
397 ISP_NVRAM_MASK
| qdev
->
398 eeprom_cmd_data
| dataBit
|
399 AUBURN_EEPROM_CLK_FALL
);
403 mask
= 1 << (addrBits
- 1);
404 /* Force the previous data bit to be different */
405 previousBit
= 0xffff;
406 for (i
= 0; i
< addrBits
; i
++) {
408 (eepromAddr
& mask
) ? AUBURN_EEPROM_DO_1
:
410 if (previousBit
!= dataBit
) {
412 * If the bit changed, then change the DO state to
415 ql_write_common_reg(qdev
,
416 &port_regs
->CommonRegs
.
417 serialPortInterfaceReg
,
418 ISP_NVRAM_MASK
| qdev
->
419 eeprom_cmd_data
| dataBit
);
420 previousBit
= dataBit
;
422 ql_write_common_reg(qdev
,
423 &port_regs
->CommonRegs
.
424 serialPortInterfaceReg
,
425 ISP_NVRAM_MASK
| qdev
->
426 eeprom_cmd_data
| dataBit
|
427 AUBURN_EEPROM_CLK_RISE
);
428 ql_write_common_reg(qdev
,
429 &port_regs
->CommonRegs
.
430 serialPortInterfaceReg
,
431 ISP_NVRAM_MASK
| qdev
->
432 eeprom_cmd_data
| dataBit
|
433 AUBURN_EEPROM_CLK_FALL
);
434 eepromAddr
= eepromAddr
<< 1;
439 * Caller holds hw_lock.
441 static void fm93c56a_deselect(struct ql3_adapter
*qdev
)
443 struct ql3xxx_port_registers __iomem
*port_regs
=
444 qdev
->mem_map_registers
;
445 qdev
->eeprom_cmd_data
= AUBURN_EEPROM_CS_0
;
446 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
447 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
);
451 * Caller holds hw_lock.
453 static void fm93c56a_datain(struct ql3_adapter
*qdev
, unsigned short *value
)
458 struct ql3xxx_port_registers __iomem
*port_regs
=
459 qdev
->mem_map_registers
;
461 /* Read the data bits */
462 /* The first bit is a dummy. Clock right over it. */
463 for (i
= 0; i
< dataBits
; i
++) {
464 ql_write_common_reg(qdev
,
465 &port_regs
->CommonRegs
.
466 serialPortInterfaceReg
,
467 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
468 AUBURN_EEPROM_CLK_RISE
);
469 ql_write_common_reg(qdev
,
470 &port_regs
->CommonRegs
.
471 serialPortInterfaceReg
,
472 ISP_NVRAM_MASK
| qdev
->eeprom_cmd_data
|
473 AUBURN_EEPROM_CLK_FALL
);
477 &port_regs
->CommonRegs
.
478 serialPortInterfaceReg
) & AUBURN_EEPROM_DI_1
) ? 1 : 0;
479 data
= (data
<< 1) | dataBit
;
485 * Caller holds hw_lock.
487 static void eeprom_readword(struct ql3_adapter
*qdev
,
488 u32 eepromAddr
, unsigned short *value
)
490 fm93c56a_select(qdev
);
491 fm93c56a_cmd(qdev
, (int)FM93C56A_READ
, eepromAddr
);
492 fm93c56a_datain(qdev
, value
);
493 fm93c56a_deselect(qdev
);
496 static void ql_swap_mac_addr(u8
* macAddress
)
500 temp
= macAddress
[0];
501 macAddress
[0] = macAddress
[1];
502 macAddress
[1] = temp
;
503 temp
= macAddress
[2];
504 macAddress
[2] = macAddress
[3];
505 macAddress
[3] = temp
;
506 temp
= macAddress
[4];
507 macAddress
[4] = macAddress
[5];
508 macAddress
[5] = temp
;
512 static int ql_get_nvram_params(struct ql3_adapter
*qdev
)
517 unsigned long hw_flags
;
519 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
521 pEEPROMData
= (u16
*) & qdev
->nvram_data
;
522 qdev
->eeprom_cmd_data
= 0;
523 if(ql_sem_spinlock(qdev
, QL_NVRAM_SEM_MASK
,
524 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
526 printk(KERN_ERR PFX
"%s: Failed ql_sem_spinlock().\n",
528 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
532 for (index
= 0; index
< EEPROM_SIZE
; index
++) {
533 eeprom_readword(qdev
, index
, pEEPROMData
);
534 checksum
+= *pEEPROMData
;
537 ql_sem_unlock(qdev
, QL_NVRAM_SEM_MASK
);
540 printk(KERN_ERR PFX
"%s: checksum should be zero, is %x!!\n",
541 qdev
->ndev
->name
, checksum
);
542 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
547 * We have a problem with endianness for the MAC addresses
548 * and the two 8-bit values version, and numPorts. We
549 * have to swap them on big endian systems.
551 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn0
.macAddress
);
552 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn1
.macAddress
);
553 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn2
.macAddress
);
554 ql_swap_mac_addr(qdev
->nvram_data
.funcCfg_fn3
.macAddress
);
555 pEEPROMData
= (u16
*) & qdev
->nvram_data
.version
;
556 *pEEPROMData
= le16_to_cpu(*pEEPROMData
);
558 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
562 static const u32 PHYAddr
[2] = {
563 PORT0_PHY_ADDRESS
, PORT1_PHY_ADDRESS
566 static int ql_wait_for_mii_ready(struct ql3_adapter
*qdev
)
568 struct ql3xxx_port_registers __iomem
*port_regs
=
569 qdev
->mem_map_registers
;
574 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIStatusReg
);
575 if (!(temp
& MAC_MII_STATUS_BSY
))
583 static void ql_mii_enable_scan_mode(struct ql3_adapter
*qdev
)
585 struct ql3xxx_port_registers __iomem
*port_regs
=
586 qdev
->mem_map_registers
;
589 if (qdev
->numPorts
> 1) {
590 /* Auto scan will cycle through multiple ports */
591 scanControl
= MAC_MII_CONTROL_AS
| MAC_MII_CONTROL_SC
;
593 scanControl
= MAC_MII_CONTROL_SC
;
597 * Scan register 1 of PHY/PETBI,
598 * Set up to scan both devices
599 * The autoscan starts from the first register, completes
600 * the last one before rolling over to the first
602 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
603 PHYAddr
[0] | MII_SCAN_REGISTER
);
605 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
607 ((MAC_MII_CONTROL_SC
| MAC_MII_CONTROL_AS
) << 16));
610 static u8
ql_mii_disable_scan_mode(struct ql3_adapter
*qdev
)
613 struct ql3xxx_port_registers __iomem
*port_regs
=
614 qdev
->mem_map_registers
;
616 /* See if scan mode is enabled before we turn it off */
617 if (ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
) &
618 (MAC_MII_CONTROL_AS
| MAC_MII_CONTROL_SC
)) {
619 /* Scan is enabled */
622 /* Scan is disabled */
627 * When disabling scan mode you must first change the MII register
630 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
631 PHYAddr
[0] | MII_SCAN_REGISTER
);
633 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
634 ((MAC_MII_CONTROL_SC
| MAC_MII_CONTROL_AS
|
635 MAC_MII_CONTROL_RC
) << 16));
640 static int ql_mii_write_reg_ex(struct ql3_adapter
*qdev
,
641 u16 regAddr
, u16 value
, u32 mac_index
)
643 struct ql3xxx_port_registers __iomem
*port_regs
=
644 qdev
->mem_map_registers
;
647 scanWasEnabled
= ql_mii_disable_scan_mode(qdev
);
649 if (ql_wait_for_mii_ready(qdev
)) {
650 if (netif_msg_link(qdev
))
651 printk(KERN_WARNING PFX
652 "%s Timed out waiting for management port to "
653 "get free before issuing command.\n",
658 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
659 PHYAddr
[mac_index
] | regAddr
);
661 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
, value
);
663 /* Wait for write to complete 9/10/04 SJP */
664 if (ql_wait_for_mii_ready(qdev
)) {
665 if (netif_msg_link(qdev
))
666 printk(KERN_WARNING PFX
667 "%s: Timed out waiting for management port to"
668 "get free before issuing command.\n",
674 ql_mii_enable_scan_mode(qdev
);
679 static int ql_mii_read_reg_ex(struct ql3_adapter
*qdev
, u16 regAddr
,
680 u16
* value
, u32 mac_index
)
682 struct ql3xxx_port_registers __iomem
*port_regs
=
683 qdev
->mem_map_registers
;
687 scanWasEnabled
= ql_mii_disable_scan_mode(qdev
);
689 if (ql_wait_for_mii_ready(qdev
)) {
690 if (netif_msg_link(qdev
))
691 printk(KERN_WARNING PFX
692 "%s: Timed out waiting for management port to "
693 "get free before issuing command.\n",
698 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
699 PHYAddr
[mac_index
] | regAddr
);
701 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
702 (MAC_MII_CONTROL_RC
<< 16));
704 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
705 (MAC_MII_CONTROL_RC
<< 16) | MAC_MII_CONTROL_RC
);
707 /* Wait for the read to complete */
708 if (ql_wait_for_mii_ready(qdev
)) {
709 if (netif_msg_link(qdev
))
710 printk(KERN_WARNING PFX
711 "%s: Timed out waiting for management port to "
712 "get free after issuing command.\n",
717 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
);
721 ql_mii_enable_scan_mode(qdev
);
726 static int ql_mii_write_reg(struct ql3_adapter
*qdev
, u16 regAddr
, u16 value
)
728 struct ql3xxx_port_registers __iomem
*port_regs
=
729 qdev
->mem_map_registers
;
731 ql_mii_disable_scan_mode(qdev
);
733 if (ql_wait_for_mii_ready(qdev
)) {
734 if (netif_msg_link(qdev
))
735 printk(KERN_WARNING PFX
736 "%s: Timed out waiting for management port to "
737 "get free before issuing command.\n",
742 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
743 qdev
->PHYAddr
| regAddr
);
745 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
, value
);
747 /* Wait for write to complete. */
748 if (ql_wait_for_mii_ready(qdev
)) {
749 if (netif_msg_link(qdev
))
750 printk(KERN_WARNING PFX
751 "%s: Timed out waiting for management port to "
752 "get free before issuing command.\n",
757 ql_mii_enable_scan_mode(qdev
);
762 static int ql_mii_read_reg(struct ql3_adapter
*qdev
, u16 regAddr
, u16
*value
)
765 struct ql3xxx_port_registers __iomem
*port_regs
=
766 qdev
->mem_map_registers
;
768 ql_mii_disable_scan_mode(qdev
);
770 if (ql_wait_for_mii_ready(qdev
)) {
771 if (netif_msg_link(qdev
))
772 printk(KERN_WARNING PFX
773 "%s: Timed out waiting for management port to "
774 "get free before issuing command.\n",
779 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtAddrReg
,
780 qdev
->PHYAddr
| regAddr
);
782 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
783 (MAC_MII_CONTROL_RC
<< 16));
785 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
786 (MAC_MII_CONTROL_RC
<< 16) | MAC_MII_CONTROL_RC
);
788 /* Wait for the read to complete */
789 if (ql_wait_for_mii_ready(qdev
)) {
790 if (netif_msg_link(qdev
))
791 printk(KERN_WARNING PFX
792 "%s: Timed out waiting for management port to "
793 "get free before issuing command.\n",
798 temp
= ql_read_page0_reg(qdev
, &port_regs
->macMIIMgmtDataReg
);
801 ql_mii_enable_scan_mode(qdev
);
806 static void ql_petbi_reset(struct ql3_adapter
*qdev
)
808 ql_mii_write_reg(qdev
, PETBI_CONTROL_REG
, PETBI_CTRL_SOFT_RESET
);
811 static void ql_petbi_start_neg(struct ql3_adapter
*qdev
)
815 /* Enable Auto-negotiation sense */
816 ql_mii_read_reg(qdev
, PETBI_TBI_CTRL
, ®
);
817 reg
|= PETBI_TBI_AUTO_SENSE
;
818 ql_mii_write_reg(qdev
, PETBI_TBI_CTRL
, reg
);
820 ql_mii_write_reg(qdev
, PETBI_NEG_ADVER
,
821 PETBI_NEG_PAUSE
| PETBI_NEG_DUPLEX
);
823 ql_mii_write_reg(qdev
, PETBI_CONTROL_REG
,
824 PETBI_CTRL_AUTO_NEG
| PETBI_CTRL_RESTART_NEG
|
825 PETBI_CTRL_FULL_DUPLEX
| PETBI_CTRL_SPEED_1000
);
829 static void ql_petbi_reset_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
831 ql_mii_write_reg_ex(qdev
, PETBI_CONTROL_REG
, PETBI_CTRL_SOFT_RESET
,
835 static void ql_petbi_start_neg_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
839 /* Enable Auto-negotiation sense */
840 ql_mii_read_reg_ex(qdev
, PETBI_TBI_CTRL
, ®
, mac_index
);
841 reg
|= PETBI_TBI_AUTO_SENSE
;
842 ql_mii_write_reg_ex(qdev
, PETBI_TBI_CTRL
, reg
, mac_index
);
844 ql_mii_write_reg_ex(qdev
, PETBI_NEG_ADVER
,
845 PETBI_NEG_PAUSE
| PETBI_NEG_DUPLEX
, mac_index
);
847 ql_mii_write_reg_ex(qdev
, PETBI_CONTROL_REG
,
848 PETBI_CTRL_AUTO_NEG
| PETBI_CTRL_RESTART_NEG
|
849 PETBI_CTRL_FULL_DUPLEX
| PETBI_CTRL_SPEED_1000
,
853 static void ql_petbi_init(struct ql3_adapter
*qdev
)
855 ql_petbi_reset(qdev
);
856 ql_petbi_start_neg(qdev
);
859 static void ql_petbi_init_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
861 ql_petbi_reset_ex(qdev
, mac_index
);
862 ql_petbi_start_neg_ex(qdev
, mac_index
);
865 static int ql_is_petbi_neg_pause(struct ql3_adapter
*qdev
)
869 if (ql_mii_read_reg(qdev
, PETBI_NEG_PARTNER
, ®
) < 0)
872 return (reg
& PETBI_NEG_PAUSE_MASK
) == PETBI_NEG_PAUSE
;
875 static int ql_phy_get_speed(struct ql3_adapter
*qdev
)
879 if (ql_mii_read_reg(qdev
, AUX_CONTROL_STATUS
, ®
) < 0)
882 reg
= (((reg
& 0x18) >> 3) & 3);
894 static int ql_is_full_dup(struct ql3_adapter
*qdev
)
898 if (ql_mii_read_reg(qdev
, AUX_CONTROL_STATUS
, ®
) < 0)
901 return (reg
& PHY_AUX_DUPLEX_STAT
) != 0;
904 static int ql_is_phy_neg_pause(struct ql3_adapter
*qdev
)
908 if (ql_mii_read_reg(qdev
, PHY_NEG_PARTNER
, ®
) < 0)
911 return (reg
& PHY_NEG_PAUSE
) != 0;
915 * Caller holds hw_lock.
917 static void ql_mac_enable(struct ql3_adapter
*qdev
, u32 enable
)
919 struct ql3xxx_port_registers __iomem
*port_regs
=
920 qdev
->mem_map_registers
;
924 value
= (MAC_CONFIG_REG_PE
| (MAC_CONFIG_REG_PE
<< 16));
926 value
= (MAC_CONFIG_REG_PE
<< 16);
929 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
931 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
935 * Caller holds hw_lock.
937 static void ql_mac_cfg_soft_reset(struct ql3_adapter
*qdev
, u32 enable
)
939 struct ql3xxx_port_registers __iomem
*port_regs
=
940 qdev
->mem_map_registers
;
944 value
= (MAC_CONFIG_REG_SR
| (MAC_CONFIG_REG_SR
<< 16));
946 value
= (MAC_CONFIG_REG_SR
<< 16);
949 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
951 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
955 * Caller holds hw_lock.
957 static void ql_mac_cfg_gig(struct ql3_adapter
*qdev
, u32 enable
)
959 struct ql3xxx_port_registers __iomem
*port_regs
=
960 qdev
->mem_map_registers
;
964 value
= (MAC_CONFIG_REG_GM
| (MAC_CONFIG_REG_GM
<< 16));
966 value
= (MAC_CONFIG_REG_GM
<< 16);
969 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
971 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
975 * Caller holds hw_lock.
977 static void ql_mac_cfg_full_dup(struct ql3_adapter
*qdev
, u32 enable
)
979 struct ql3xxx_port_registers __iomem
*port_regs
=
980 qdev
->mem_map_registers
;
984 value
= (MAC_CONFIG_REG_FD
| (MAC_CONFIG_REG_FD
<< 16));
986 value
= (MAC_CONFIG_REG_FD
<< 16);
989 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
991 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
995 * Caller holds hw_lock.
997 static void ql_mac_cfg_pause(struct ql3_adapter
*qdev
, u32 enable
)
999 struct ql3xxx_port_registers __iomem
*port_regs
=
1000 qdev
->mem_map_registers
;
1005 ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) |
1006 ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) << 16));
1008 value
= ((MAC_CONFIG_REG_TF
| MAC_CONFIG_REG_RF
) << 16);
1010 if (qdev
->mac_index
)
1011 ql_write_page0_reg(qdev
, &port_regs
->mac1ConfigReg
, value
);
1013 ql_write_page0_reg(qdev
, &port_regs
->mac0ConfigReg
, value
);
1017 * Caller holds hw_lock.
1019 static int ql_is_fiber(struct ql3_adapter
*qdev
)
1021 struct ql3xxx_port_registers __iomem
*port_regs
=
1022 qdev
->mem_map_registers
;
1026 switch (qdev
->mac_index
) {
1028 bitToCheck
= PORT_STATUS_SM0
;
1031 bitToCheck
= PORT_STATUS_SM1
;
1035 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1036 return (temp
& bitToCheck
) != 0;
1039 static int ql_is_auto_cfg(struct ql3_adapter
*qdev
)
1042 ql_mii_read_reg(qdev
, 0x00, ®
);
1043 return (reg
& 0x1000) != 0;
1047 * Caller holds hw_lock.
1049 static int ql_is_auto_neg_complete(struct ql3_adapter
*qdev
)
1051 struct ql3xxx_port_registers __iomem
*port_regs
=
1052 qdev
->mem_map_registers
;
1056 switch (qdev
->mac_index
) {
1058 bitToCheck
= PORT_STATUS_AC0
;
1061 bitToCheck
= PORT_STATUS_AC1
;
1065 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1066 if (temp
& bitToCheck
) {
1067 if (netif_msg_link(qdev
))
1068 printk(KERN_INFO PFX
1069 "%s: Auto-Negotiate complete.\n",
1073 if (netif_msg_link(qdev
))
1074 printk(KERN_WARNING PFX
1075 "%s: Auto-Negotiate incomplete.\n",
1082 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1084 static int ql_is_neg_pause(struct ql3_adapter
*qdev
)
1086 if (ql_is_fiber(qdev
))
1087 return ql_is_petbi_neg_pause(qdev
);
1089 return ql_is_phy_neg_pause(qdev
);
1092 static int ql_auto_neg_error(struct ql3_adapter
*qdev
)
1094 struct ql3xxx_port_registers __iomem
*port_regs
=
1095 qdev
->mem_map_registers
;
1099 switch (qdev
->mac_index
) {
1101 bitToCheck
= PORT_STATUS_AE0
;
1104 bitToCheck
= PORT_STATUS_AE1
;
1107 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1108 return (temp
& bitToCheck
) != 0;
1111 static u32
ql_get_link_speed(struct ql3_adapter
*qdev
)
1113 if (ql_is_fiber(qdev
))
1116 return ql_phy_get_speed(qdev
);
1119 static int ql_is_link_full_dup(struct ql3_adapter
*qdev
)
1121 if (ql_is_fiber(qdev
))
1124 return ql_is_full_dup(qdev
);
1128 * Caller holds hw_lock.
1130 static int ql_link_down_detect(struct ql3_adapter
*qdev
)
1132 struct ql3xxx_port_registers __iomem
*port_regs
=
1133 qdev
->mem_map_registers
;
1137 switch (qdev
->mac_index
) {
1139 bitToCheck
= ISP_CONTROL_LINK_DN_0
;
1142 bitToCheck
= ISP_CONTROL_LINK_DN_1
;
1147 ql_read_common_reg(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
1148 return (temp
& bitToCheck
) != 0;
1152 * Caller holds hw_lock.
1154 static int ql_link_down_detect_clear(struct ql3_adapter
*qdev
)
1156 struct ql3xxx_port_registers __iomem
*port_regs
=
1157 qdev
->mem_map_registers
;
1159 switch (qdev
->mac_index
) {
1161 ql_write_common_reg(qdev
,
1162 &port_regs
->CommonRegs
.ispControlStatus
,
1163 (ISP_CONTROL_LINK_DN_0
) |
1164 (ISP_CONTROL_LINK_DN_0
<< 16));
1168 ql_write_common_reg(qdev
,
1169 &port_regs
->CommonRegs
.ispControlStatus
,
1170 (ISP_CONTROL_LINK_DN_1
) |
1171 (ISP_CONTROL_LINK_DN_1
<< 16));
1182 * Caller holds hw_lock.
1184 static int ql_this_adapter_controls_port(struct ql3_adapter
*qdev
,
1187 struct ql3xxx_port_registers __iomem
*port_regs
=
1188 qdev
->mem_map_registers
;
1192 switch (mac_index
) {
1194 bitToCheck
= PORT_STATUS_F1_ENABLED
;
1197 bitToCheck
= PORT_STATUS_F3_ENABLED
;
1203 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1204 if (temp
& bitToCheck
) {
1205 if (netif_msg_link(qdev
))
1206 printk(KERN_DEBUG PFX
1207 "%s: is not link master.\n", qdev
->ndev
->name
);
1210 if (netif_msg_link(qdev
))
1211 printk(KERN_DEBUG PFX
1212 "%s: is link master.\n", qdev
->ndev
->name
);
1217 static void ql_phy_reset_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1219 ql_mii_write_reg_ex(qdev
, CONTROL_REG
, PHY_CTRL_SOFT_RESET
, mac_index
);
1222 static void ql_phy_start_neg_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1226 ql_mii_write_reg_ex(qdev
, PHY_NEG_ADVER
,
1227 PHY_NEG_PAUSE
| PHY_NEG_ADV_SPEED
| 1, mac_index
);
1229 ql_mii_read_reg_ex(qdev
, CONTROL_REG
, ®
, mac_index
);
1230 ql_mii_write_reg_ex(qdev
, CONTROL_REG
, reg
| PHY_CTRL_RESTART_NEG
,
1234 static void ql_phy_init_ex(struct ql3_adapter
*qdev
, u32 mac_index
)
1236 ql_phy_reset_ex(qdev
, mac_index
);
1237 ql_phy_start_neg_ex(qdev
, mac_index
);
1241 * Caller holds hw_lock.
1243 static u32
ql_get_link_state(struct ql3_adapter
*qdev
)
1245 struct ql3xxx_port_registers __iomem
*port_regs
=
1246 qdev
->mem_map_registers
;
1248 u32 temp
, linkState
;
1250 switch (qdev
->mac_index
) {
1252 bitToCheck
= PORT_STATUS_UP0
;
1255 bitToCheck
= PORT_STATUS_UP1
;
1258 temp
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
1259 if (temp
& bitToCheck
) {
1262 linkState
= LS_DOWN
;
1263 if (netif_msg_link(qdev
))
1264 printk(KERN_WARNING PFX
1265 "%s: Link is down.\n", qdev
->ndev
->name
);
1270 static int ql_port_start(struct ql3_adapter
*qdev
)
1272 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1273 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1277 if (ql_is_fiber(qdev
)) {
1278 ql_petbi_init(qdev
);
1281 ql_phy_init_ex(qdev
, qdev
->mac_index
);
1284 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1288 static int ql_finish_auto_neg(struct ql3_adapter
*qdev
)
1291 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1292 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1296 if (!ql_auto_neg_error(qdev
)) {
1297 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1298 /* configure the MAC */
1299 if (netif_msg_link(qdev
))
1300 printk(KERN_DEBUG PFX
1301 "%s: Configuring link.\n",
1304 ql_mac_cfg_soft_reset(qdev
, 1);
1305 ql_mac_cfg_gig(qdev
,
1309 ql_mac_cfg_full_dup(qdev
,
1312 ql_mac_cfg_pause(qdev
,
1315 ql_mac_cfg_soft_reset(qdev
, 0);
1317 /* enable the MAC */
1318 if (netif_msg_link(qdev
))
1319 printk(KERN_DEBUG PFX
1320 "%s: Enabling mac.\n",
1323 ql_mac_enable(qdev
, 1);
1326 if (netif_msg_link(qdev
))
1327 printk(KERN_DEBUG PFX
1328 "%s: Change port_link_state LS_DOWN to LS_UP.\n",
1330 qdev
->port_link_state
= LS_UP
;
1331 netif_start_queue(qdev
->ndev
);
1332 netif_carrier_on(qdev
->ndev
);
1333 if (netif_msg_link(qdev
))
1334 printk(KERN_INFO PFX
1335 "%s: Link is up at %d Mbps, %s duplex.\n",
1337 ql_get_link_speed(qdev
),
1338 ql_is_link_full_dup(qdev
)
1341 } else { /* Remote error detected */
1343 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1344 if (netif_msg_link(qdev
))
1345 printk(KERN_DEBUG PFX
1346 "%s: Remote error detected. "
1347 "Calling ql_port_start().\n",
1351 * ql_port_start() is shared code and needs
1352 * to lock the PHY on it's own.
1354 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1355 if(ql_port_start(qdev
)) {/* Restart port */
1361 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1365 static void ql_link_state_machine(struct ql3_adapter
*qdev
)
1367 u32 curr_link_state
;
1368 unsigned long hw_flags
;
1370 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1372 curr_link_state
= ql_get_link_state(qdev
);
1374 if (test_bit(QL_RESET_ACTIVE
,&qdev
->flags
)) {
1375 if (netif_msg_link(qdev
))
1376 printk(KERN_INFO PFX
1377 "%s: Reset in progress, skip processing link "
1378 "state.\n", qdev
->ndev
->name
);
1382 switch (qdev
->port_link_state
) {
1384 if (test_bit(QL_LINK_MASTER
,&qdev
->flags
)) {
1385 ql_port_start(qdev
);
1387 qdev
->port_link_state
= LS_DOWN
;
1391 if (netif_msg_link(qdev
))
1392 printk(KERN_DEBUG PFX
1393 "%s: port_link_state = LS_DOWN.\n",
1395 if (curr_link_state
== LS_UP
) {
1396 if (netif_msg_link(qdev
))
1397 printk(KERN_DEBUG PFX
1398 "%s: curr_link_state = LS_UP.\n",
1400 if (ql_is_auto_neg_complete(qdev
))
1401 ql_finish_auto_neg(qdev
);
1403 if (qdev
->port_link_state
== LS_UP
)
1404 ql_link_down_detect_clear(qdev
);
1411 * See if the link is currently down or went down and came
1414 if ((curr_link_state
== LS_DOWN
) || ql_link_down_detect(qdev
)) {
1415 if (netif_msg_link(qdev
))
1416 printk(KERN_INFO PFX
"%s: Link is down.\n",
1418 qdev
->port_link_state
= LS_DOWN
;
1422 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1426 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1428 static void ql_get_phy_owner(struct ql3_adapter
*qdev
)
1430 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1431 set_bit(QL_LINK_MASTER
,&qdev
->flags
);
1433 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
1437 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1439 static void ql_init_scan_mode(struct ql3_adapter
*qdev
)
1441 ql_mii_enable_scan_mode(qdev
);
1443 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1444 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1445 ql_petbi_init_ex(qdev
, qdev
->mac_index
);
1447 if (ql_this_adapter_controls_port(qdev
, qdev
->mac_index
))
1448 ql_phy_init_ex(qdev
, qdev
->mac_index
);
1453 * MII_Setup needs to be called before taking the PHY out of reset so that the
1454 * management interface clock speed can be set properly. It would be better if
1455 * we had a way to disable MDC until after the PHY is out of reset, but we
1456 * don't have that capability.
1458 static int ql_mii_setup(struct ql3_adapter
*qdev
)
1461 struct ql3xxx_port_registers __iomem
*port_regs
=
1462 qdev
->mem_map_registers
;
1464 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1465 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1469 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1470 reg
= MAC_MII_CONTROL_CLK_SEL_DIV28
;
1472 ql_write_page0_reg(qdev
, &port_regs
->macMIIMgmtControlReg
,
1473 reg
| ((MAC_MII_CONTROL_CLK_SEL_MASK
) << 16));
1475 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1479 static u32
ql_supported_modes(struct ql3_adapter
*qdev
)
1483 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1484 supported
= SUPPORTED_1000baseT_Full
| SUPPORTED_FIBRE
1485 | SUPPORTED_Autoneg
;
1487 supported
= SUPPORTED_10baseT_Half
1488 | SUPPORTED_10baseT_Full
1489 | SUPPORTED_100baseT_Half
1490 | SUPPORTED_100baseT_Full
1491 | SUPPORTED_1000baseT_Half
1492 | SUPPORTED_1000baseT_Full
1493 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
1499 static int ql_get_auto_cfg_status(struct ql3_adapter
*qdev
)
1502 unsigned long hw_flags
;
1503 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1504 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1505 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1508 status
= ql_is_auto_cfg(qdev
);
1509 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1510 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1514 static u32
ql_get_speed(struct ql3_adapter
*qdev
)
1517 unsigned long hw_flags
;
1518 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1519 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1520 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1523 status
= ql_get_link_speed(qdev
);
1524 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1525 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1529 static int ql_get_full_dup(struct ql3_adapter
*qdev
)
1532 unsigned long hw_flags
;
1533 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1534 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
1535 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
1538 status
= ql_is_link_full_dup(qdev
);
1539 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
1540 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1545 static int ql_get_settings(struct net_device
*ndev
, struct ethtool_cmd
*ecmd
)
1547 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1549 ecmd
->transceiver
= XCVR_INTERNAL
;
1550 ecmd
->supported
= ql_supported_modes(qdev
);
1552 if (test_bit(QL_LINK_OPTICAL
,&qdev
->flags
)) {
1553 ecmd
->port
= PORT_FIBRE
;
1555 ecmd
->port
= PORT_TP
;
1556 ecmd
->phy_address
= qdev
->PHYAddr
;
1558 ecmd
->advertising
= ql_supported_modes(qdev
);
1559 ecmd
->autoneg
= ql_get_auto_cfg_status(qdev
);
1560 ecmd
->speed
= ql_get_speed(qdev
);
1561 ecmd
->duplex
= ql_get_full_dup(qdev
);
1565 static void ql_get_drvinfo(struct net_device
*ndev
,
1566 struct ethtool_drvinfo
*drvinfo
)
1568 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1569 strncpy(drvinfo
->driver
, ql3xxx_driver_name
, 32);
1570 strncpy(drvinfo
->version
, ql3xxx_driver_version
, 32);
1571 strncpy(drvinfo
->fw_version
, "N/A", 32);
1572 strncpy(drvinfo
->bus_info
, pci_name(qdev
->pdev
), 32);
1573 drvinfo
->n_stats
= 0;
1574 drvinfo
->testinfo_len
= 0;
1575 drvinfo
->regdump_len
= 0;
1576 drvinfo
->eedump_len
= 0;
1579 static u32
ql_get_msglevel(struct net_device
*ndev
)
1581 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1582 return qdev
->msg_enable
;
1585 static void ql_set_msglevel(struct net_device
*ndev
, u32 value
)
1587 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1588 qdev
->msg_enable
= value
;
1591 static const struct ethtool_ops ql3xxx_ethtool_ops
= {
1592 .get_settings
= ql_get_settings
,
1593 .get_drvinfo
= ql_get_drvinfo
,
1594 .get_perm_addr
= ethtool_op_get_perm_addr
,
1595 .get_link
= ethtool_op_get_link
,
1596 .get_msglevel
= ql_get_msglevel
,
1597 .set_msglevel
= ql_set_msglevel
,
1600 static int ql_populate_free_queue(struct ql3_adapter
*qdev
)
1602 struct ql_rcv_buf_cb
*lrg_buf_cb
= qdev
->lrg_buf_free_head
;
1605 while (lrg_buf_cb
) {
1606 if (!lrg_buf_cb
->skb
) {
1607 lrg_buf_cb
->skb
= dev_alloc_skb(qdev
->lrg_buffer_len
);
1608 if (unlikely(!lrg_buf_cb
->skb
)) {
1609 printk(KERN_DEBUG PFX
1610 "%s: Failed dev_alloc_skb().\n",
1615 * We save some space to copy the ethhdr from
1618 skb_reserve(lrg_buf_cb
->skb
, QL_HEADER_SPACE
);
1619 map
= pci_map_single(qdev
->pdev
,
1620 lrg_buf_cb
->skb
->data
,
1621 qdev
->lrg_buffer_len
-
1623 PCI_DMA_FROMDEVICE
);
1624 lrg_buf_cb
->buf_phy_addr_low
=
1625 cpu_to_le32(LS_64BITS(map
));
1626 lrg_buf_cb
->buf_phy_addr_high
=
1627 cpu_to_le32(MS_64BITS(map
));
1628 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
1629 pci_unmap_len_set(lrg_buf_cb
, maplen
,
1630 qdev
->lrg_buffer_len
-
1632 --qdev
->lrg_buf_skb_check
;
1633 if (!qdev
->lrg_buf_skb_check
)
1637 lrg_buf_cb
= lrg_buf_cb
->next
;
1643 * Caller holds hw_lock.
1645 static void ql_update_lrg_bufq_prod_index(struct ql3_adapter
*qdev
)
1647 struct bufq_addr_element
*lrg_buf_q_ele
;
1649 struct ql_rcv_buf_cb
*lrg_buf_cb
;
1650 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
1652 if ((qdev
->lrg_buf_free_count
>= 8)
1653 && (qdev
->lrg_buf_release_cnt
>= 16)) {
1655 if (qdev
->lrg_buf_skb_check
)
1656 if (!ql_populate_free_queue(qdev
))
1659 lrg_buf_q_ele
= qdev
->lrg_buf_next_free
;
1661 while ((qdev
->lrg_buf_release_cnt
>= 16)
1662 && (qdev
->lrg_buf_free_count
>= 8)) {
1664 for (i
= 0; i
< 8; i
++) {
1666 ql_get_from_lrg_buf_free_list(qdev
);
1667 lrg_buf_q_ele
->addr_high
=
1668 lrg_buf_cb
->buf_phy_addr_high
;
1669 lrg_buf_q_ele
->addr_low
=
1670 lrg_buf_cb
->buf_phy_addr_low
;
1673 qdev
->lrg_buf_release_cnt
--;
1676 qdev
->lrg_buf_q_producer_index
++;
1678 if (qdev
->lrg_buf_q_producer_index
== NUM_LBUFQ_ENTRIES
)
1679 qdev
->lrg_buf_q_producer_index
= 0;
1681 if (qdev
->lrg_buf_q_producer_index
==
1682 (NUM_LBUFQ_ENTRIES
- 1)) {
1683 lrg_buf_q_ele
= qdev
->lrg_buf_q_virt_addr
;
1687 qdev
->lrg_buf_next_free
= lrg_buf_q_ele
;
1689 ql_write_common_reg(qdev
,
1690 &port_regs
->CommonRegs
.
1691 rxLargeQProducerIndex
,
1692 qdev
->lrg_buf_q_producer_index
);
1696 static void ql_process_mac_tx_intr(struct ql3_adapter
*qdev
,
1697 struct ob_mac_iocb_rsp
*mac_rsp
)
1699 struct ql_tx_buf_cb
*tx_cb
;
1701 tx_cb
= &qdev
->tx_buf
[mac_rsp
->transaction_id
];
1702 pci_unmap_single(qdev
->pdev
,
1703 pci_unmap_addr(tx_cb
, mapaddr
),
1704 pci_unmap_len(tx_cb
, maplen
), PCI_DMA_TODEVICE
);
1705 dev_kfree_skb_irq(tx_cb
->skb
);
1706 qdev
->stats
.tx_packets
++;
1707 qdev
->stats
.tx_bytes
+= tx_cb
->skb
->len
;
1709 atomic_inc(&qdev
->tx_count
);
1712 static void ql_process_mac_rx_intr(struct ql3_adapter
*qdev
,
1713 struct ib_mac_iocb_rsp
*ib_mac_rsp_ptr
)
1716 u32 lrg_buf_phy_addr_low
= 0;
1717 struct ql_rcv_buf_cb
*lrg_buf_cb1
= NULL
;
1718 struct ql_rcv_buf_cb
*lrg_buf_cb2
= NULL
;
1720 struct sk_buff
*skb
;
1721 u16 length
= le16_to_cpu(ib_mac_rsp_ptr
->length
);
1724 * Get the inbound address list (small buffer).
1726 offset
= qdev
->small_buf_index
* QL_SMALL_BUFFER_SIZE
;
1727 if (++qdev
->small_buf_index
== NUM_SMALL_BUFFERS
)
1728 qdev
->small_buf_index
= 0;
1730 curr_ial_ptr
= (u32
*) (qdev
->small_buf_virt_addr
+ offset
);
1731 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
+ offset
;
1732 qdev
->small_buf_release_cnt
++;
1734 /* start of first buffer */
1735 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1736 lrg_buf_cb1
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1737 qdev
->lrg_buf_release_cnt
++;
1738 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1739 qdev
->lrg_buf_index
= 0;
1740 curr_ial_ptr
++; /* 64-bit pointers require two incs. */
1743 /* start of second buffer */
1744 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1745 lrg_buf_cb2
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1748 * Second buffer gets sent up the stack.
1750 qdev
->lrg_buf_release_cnt
++;
1751 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1752 qdev
->lrg_buf_index
= 0;
1753 skb
= lrg_buf_cb2
->skb
;
1755 qdev
->stats
.rx_packets
++;
1756 qdev
->stats
.rx_bytes
+= length
;
1758 skb_put(skb
, length
);
1759 pci_unmap_single(qdev
->pdev
,
1760 pci_unmap_addr(lrg_buf_cb2
, mapaddr
),
1761 pci_unmap_len(lrg_buf_cb2
, maplen
),
1762 PCI_DMA_FROMDEVICE
);
1763 prefetch(skb
->data
);
1764 skb
->dev
= qdev
->ndev
;
1765 skb
->ip_summed
= CHECKSUM_NONE
;
1766 skb
->protocol
= eth_type_trans(skb
, qdev
->ndev
);
1768 netif_receive_skb(skb
);
1769 qdev
->ndev
->last_rx
= jiffies
;
1770 lrg_buf_cb2
->skb
= NULL
;
1772 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb1
);
1773 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb2
);
1776 static void ql_process_macip_rx_intr(struct ql3_adapter
*qdev
,
1777 struct ib_ip_iocb_rsp
*ib_ip_rsp_ptr
)
1780 u32 lrg_buf_phy_addr_low
= 0;
1781 struct ql_rcv_buf_cb
*lrg_buf_cb1
= NULL
;
1782 struct ql_rcv_buf_cb
*lrg_buf_cb2
= NULL
;
1784 struct sk_buff
*skb1
, *skb2
;
1785 struct net_device
*ndev
= qdev
->ndev
;
1786 u16 length
= le16_to_cpu(ib_ip_rsp_ptr
->length
);
1790 * Get the inbound address list (small buffer).
1793 offset
= qdev
->small_buf_index
* QL_SMALL_BUFFER_SIZE
;
1794 if (++qdev
->small_buf_index
== NUM_SMALL_BUFFERS
)
1795 qdev
->small_buf_index
= 0;
1796 curr_ial_ptr
= (u32
*) (qdev
->small_buf_virt_addr
+ offset
);
1797 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
+ offset
;
1798 qdev
->small_buf_release_cnt
++;
1800 /* start of first buffer */
1801 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1802 lrg_buf_cb1
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1804 qdev
->lrg_buf_release_cnt
++;
1805 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1806 qdev
->lrg_buf_index
= 0;
1807 skb1
= lrg_buf_cb1
->skb
;
1808 curr_ial_ptr
++; /* 64-bit pointers require two incs. */
1811 /* start of second buffer */
1812 lrg_buf_phy_addr_low
= le32_to_cpu(*curr_ial_ptr
);
1813 lrg_buf_cb2
= &qdev
->lrg_buf
[qdev
->lrg_buf_index
];
1814 skb2
= lrg_buf_cb2
->skb
;
1815 qdev
->lrg_buf_release_cnt
++;
1816 if (++qdev
->lrg_buf_index
== NUM_LARGE_BUFFERS
)
1817 qdev
->lrg_buf_index
= 0;
1819 qdev
->stats
.rx_packets
++;
1820 qdev
->stats
.rx_bytes
+= length
;
1823 * Copy the ethhdr from first buffer to second. This
1824 * is necessary for IP completions.
1826 if (*((u16
*) skb1
->data
) != 0xFFFF)
1827 size
= VLAN_ETH_HLEN
;
1831 skb_put(skb2
, length
); /* Just the second buffer length here. */
1832 pci_unmap_single(qdev
->pdev
,
1833 pci_unmap_addr(lrg_buf_cb2
, mapaddr
),
1834 pci_unmap_len(lrg_buf_cb2
, maplen
),
1835 PCI_DMA_FROMDEVICE
);
1836 prefetch(skb2
->data
);
1838 memcpy(skb_push(skb2
, size
), skb1
->data
+ VLAN_ID_LEN
, size
);
1839 skb2
->dev
= qdev
->ndev
;
1840 skb2
->ip_summed
= CHECKSUM_NONE
;
1841 skb2
->protocol
= eth_type_trans(skb2
, qdev
->ndev
);
1843 netif_receive_skb(skb2
);
1844 ndev
->last_rx
= jiffies
;
1845 lrg_buf_cb2
->skb
= NULL
;
1847 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb1
);
1848 ql_release_to_lrg_buf_free_list(qdev
, lrg_buf_cb2
);
1851 static int ql_tx_rx_clean(struct ql3_adapter
*qdev
,
1852 int *tx_cleaned
, int *rx_cleaned
, int work_to_do
)
1854 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
1855 struct net_rsp_iocb
*net_rsp
;
1856 struct net_device
*ndev
= qdev
->ndev
;
1857 unsigned long hw_flags
;
1859 /* While there are entries in the completion queue. */
1860 while ((cpu_to_le32(*(qdev
->prsp_producer_index
)) !=
1861 qdev
->rsp_consumer_index
) && (*rx_cleaned
< work_to_do
)) {
1863 net_rsp
= qdev
->rsp_current
;
1864 switch (net_rsp
->opcode
) {
1866 case OPCODE_OB_MAC_IOCB_FN0
:
1867 case OPCODE_OB_MAC_IOCB_FN2
:
1868 ql_process_mac_tx_intr(qdev
, (struct ob_mac_iocb_rsp
*)
1873 case OPCODE_IB_MAC_IOCB
:
1874 ql_process_mac_rx_intr(qdev
, (struct ib_mac_iocb_rsp
*)
1879 case OPCODE_IB_IP_IOCB
:
1880 ql_process_macip_rx_intr(qdev
, (struct ib_ip_iocb_rsp
*)
1886 u32
*tmp
= (u32
*) net_rsp
;
1888 "%s: Hit default case, not "
1890 " dropping the packet, opcode = "
1892 ndev
->name
, net_rsp
->opcode
);
1894 "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n",
1895 (unsigned long int)tmp
[0],
1896 (unsigned long int)tmp
[1],
1897 (unsigned long int)tmp
[2],
1898 (unsigned long int)tmp
[3]);
1902 qdev
->rsp_consumer_index
++;
1904 if (qdev
->rsp_consumer_index
== NUM_RSP_Q_ENTRIES
) {
1905 qdev
->rsp_consumer_index
= 0;
1906 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
1908 qdev
->rsp_current
++;
1912 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
1914 ql_update_lrg_bufq_prod_index(qdev
);
1916 if (qdev
->small_buf_release_cnt
>= 16) {
1917 while (qdev
->small_buf_release_cnt
>= 16) {
1918 qdev
->small_buf_q_producer_index
++;
1920 if (qdev
->small_buf_q_producer_index
==
1922 qdev
->small_buf_q_producer_index
= 0;
1923 qdev
->small_buf_release_cnt
-= 8;
1926 ql_write_common_reg(qdev
,
1927 &port_regs
->CommonRegs
.
1928 rxSmallQProducerIndex
,
1929 qdev
->small_buf_q_producer_index
);
1932 ql_write_common_reg(qdev
,
1933 &port_regs
->CommonRegs
.rspQConsumerIndex
,
1934 qdev
->rsp_consumer_index
);
1935 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
1937 if (unlikely(netif_queue_stopped(qdev
->ndev
))) {
1938 if (netif_queue_stopped(qdev
->ndev
) &&
1939 (atomic_read(&qdev
->tx_count
) > (NUM_REQ_Q_ENTRIES
/ 4)))
1940 netif_wake_queue(qdev
->ndev
);
1943 return *tx_cleaned
+ *rx_cleaned
;
1946 static int ql_poll(struct net_device
*ndev
, int *budget
)
1948 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1949 int work_to_do
= min(*budget
, ndev
->quota
);
1950 int rx_cleaned
= 0, tx_cleaned
= 0;
1952 if (!netif_carrier_ok(ndev
))
1955 ql_tx_rx_clean(qdev
, &tx_cleaned
, &rx_cleaned
, work_to_do
);
1956 *budget
-= rx_cleaned
;
1957 ndev
->quota
-= rx_cleaned
;
1959 if ((!tx_cleaned
&& !rx_cleaned
) || !netif_running(ndev
)) {
1961 netif_rx_complete(ndev
);
1962 ql_enable_interrupts(qdev
);
1968 static irqreturn_t
ql3xxx_isr(int irq
, void *dev_id
)
1971 struct net_device
*ndev
= dev_id
;
1972 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
1973 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
1978 port_regs
= qdev
->mem_map_registers
;
1981 ql_read_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
1983 if (value
& (ISP_CONTROL_FE
| ISP_CONTROL_RI
)) {
1984 spin_lock(&qdev
->adapter_lock
);
1985 netif_stop_queue(qdev
->ndev
);
1986 netif_carrier_off(qdev
->ndev
);
1987 ql_disable_interrupts(qdev
);
1988 qdev
->port_link_state
= LS_DOWN
;
1989 set_bit(QL_RESET_ACTIVE
,&qdev
->flags
) ;
1991 if (value
& ISP_CONTROL_FE
) {
1996 ql_read_page0_reg_l(qdev
,
1997 &port_regs
->PortFatalErrStatus
);
1998 printk(KERN_WARNING PFX
1999 "%s: Resetting chip. PortFatalErrStatus "
2000 "register = 0x%x\n", ndev
->name
, var
);
2001 set_bit(QL_RESET_START
,&qdev
->flags
) ;
2004 * Soft Reset Requested.
2006 set_bit(QL_RESET_PER_SCSI
,&qdev
->flags
) ;
2008 "%s: Another function issued a reset to the "
2009 "chip. ISR value = %x.\n", ndev
->name
, value
);
2011 queue_work(qdev
->workqueue
, &qdev
->reset_work
);
2012 spin_unlock(&qdev
->adapter_lock
);
2013 } else if (value
& ISP_IMR_DISABLE_CMPL_INT
) {
2014 ql_disable_interrupts(qdev
);
2015 if (likely(netif_rx_schedule_prep(ndev
)))
2016 __netif_rx_schedule(ndev
);
2018 ql_enable_interrupts(qdev
);
2023 return IRQ_RETVAL(handled
);
2026 static int ql3xxx_send(struct sk_buff
*skb
, struct net_device
*ndev
)
2028 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
2029 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2030 struct ql_tx_buf_cb
*tx_cb
;
2031 struct ob_mac_iocb_req
*mac_iocb_ptr
;
2034 if (unlikely(atomic_read(&qdev
->tx_count
) < 2)) {
2035 if (!netif_queue_stopped(ndev
))
2036 netif_stop_queue(ndev
);
2037 return NETDEV_TX_BUSY
;
2039 tx_cb
= &qdev
->tx_buf
[qdev
->req_producer_index
] ;
2040 mac_iocb_ptr
= tx_cb
->queue_entry
;
2041 memset((void *)mac_iocb_ptr
, 0, sizeof(struct ob_mac_iocb_req
));
2042 mac_iocb_ptr
->opcode
= qdev
->mac_ob_opcode
;
2043 mac_iocb_ptr
->flags
|= qdev
->mb_bit_mask
;
2044 mac_iocb_ptr
->transaction_id
= qdev
->req_producer_index
;
2045 mac_iocb_ptr
->data_len
= cpu_to_le16((u16
) skb
->len
);
2047 map
= pci_map_single(qdev
->pdev
, skb
->data
, skb
->len
, PCI_DMA_TODEVICE
);
2048 mac_iocb_ptr
->buf_addr0_low
= cpu_to_le32(LS_64BITS(map
));
2049 mac_iocb_ptr
->buf_addr0_high
= cpu_to_le32(MS_64BITS(map
));
2050 mac_iocb_ptr
->buf_0_len
= cpu_to_le32(skb
->len
| OB_MAC_IOCB_REQ_E
);
2051 pci_unmap_addr_set(tx_cb
, mapaddr
, map
);
2052 pci_unmap_len_set(tx_cb
, maplen
, skb
->len
);
2053 atomic_dec(&qdev
->tx_count
);
2055 qdev
->req_producer_index
++;
2056 if (qdev
->req_producer_index
== NUM_REQ_Q_ENTRIES
)
2057 qdev
->req_producer_index
= 0;
2059 ql_write_common_reg_l(qdev
,
2060 &port_regs
->CommonRegs
.reqQProducerIndex
,
2061 qdev
->req_producer_index
);
2063 ndev
->trans_start
= jiffies
;
2064 if (netif_msg_tx_queued(qdev
))
2065 printk(KERN_DEBUG PFX
"%s: tx queued, slot %d, len %d\n",
2066 ndev
->name
, qdev
->req_producer_index
, skb
->len
);
2068 return NETDEV_TX_OK
;
2070 static int ql_alloc_net_req_rsp_queues(struct ql3_adapter
*qdev
)
2073 (u32
) (NUM_REQ_Q_ENTRIES
* sizeof(struct ob_mac_iocb_req
));
2075 qdev
->req_q_virt_addr
=
2076 pci_alloc_consistent(qdev
->pdev
,
2077 (size_t) qdev
->req_q_size
,
2078 &qdev
->req_q_phy_addr
);
2080 if ((qdev
->req_q_virt_addr
== NULL
) ||
2081 LS_64BITS(qdev
->req_q_phy_addr
) & (qdev
->req_q_size
- 1)) {
2082 printk(KERN_ERR PFX
"%s: reqQ failed.\n",
2087 qdev
->rsp_q_size
= NUM_RSP_Q_ENTRIES
* sizeof(struct net_rsp_iocb
);
2089 qdev
->rsp_q_virt_addr
=
2090 pci_alloc_consistent(qdev
->pdev
,
2091 (size_t) qdev
->rsp_q_size
,
2092 &qdev
->rsp_q_phy_addr
);
2094 if ((qdev
->rsp_q_virt_addr
== NULL
) ||
2095 LS_64BITS(qdev
->rsp_q_phy_addr
) & (qdev
->rsp_q_size
- 1)) {
2097 "%s: rspQ allocation failed\n",
2099 pci_free_consistent(qdev
->pdev
, (size_t) qdev
->req_q_size
,
2100 qdev
->req_q_virt_addr
,
2101 qdev
->req_q_phy_addr
);
2105 set_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
);
2110 static void ql_free_net_req_rsp_queues(struct ql3_adapter
*qdev
)
2112 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
)) {
2113 printk(KERN_INFO PFX
2114 "%s: Already done.\n", qdev
->ndev
->name
);
2118 pci_free_consistent(qdev
->pdev
,
2120 qdev
->req_q_virt_addr
, qdev
->req_q_phy_addr
);
2122 qdev
->req_q_virt_addr
= NULL
;
2124 pci_free_consistent(qdev
->pdev
,
2126 qdev
->rsp_q_virt_addr
, qdev
->rsp_q_phy_addr
);
2128 qdev
->rsp_q_virt_addr
= NULL
;
2130 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE
,&qdev
->flags
);
2133 static int ql_alloc_buffer_queues(struct ql3_adapter
*qdev
)
2135 /* Create Large Buffer Queue */
2136 qdev
->lrg_buf_q_size
=
2137 NUM_LBUFQ_ENTRIES
* sizeof(struct lrg_buf_q_entry
);
2138 if (qdev
->lrg_buf_q_size
< PAGE_SIZE
)
2139 qdev
->lrg_buf_q_alloc_size
= PAGE_SIZE
;
2141 qdev
->lrg_buf_q_alloc_size
= qdev
->lrg_buf_q_size
* 2;
2143 qdev
->lrg_buf_q_alloc_virt_addr
=
2144 pci_alloc_consistent(qdev
->pdev
,
2145 qdev
->lrg_buf_q_alloc_size
,
2146 &qdev
->lrg_buf_q_alloc_phy_addr
);
2148 if (qdev
->lrg_buf_q_alloc_virt_addr
== NULL
) {
2150 "%s: lBufQ failed\n", qdev
->ndev
->name
);
2153 qdev
->lrg_buf_q_virt_addr
= qdev
->lrg_buf_q_alloc_virt_addr
;
2154 qdev
->lrg_buf_q_phy_addr
= qdev
->lrg_buf_q_alloc_phy_addr
;
2156 /* Create Small Buffer Queue */
2157 qdev
->small_buf_q_size
=
2158 NUM_SBUFQ_ENTRIES
* sizeof(struct lrg_buf_q_entry
);
2159 if (qdev
->small_buf_q_size
< PAGE_SIZE
)
2160 qdev
->small_buf_q_alloc_size
= PAGE_SIZE
;
2162 qdev
->small_buf_q_alloc_size
= qdev
->small_buf_q_size
* 2;
2164 qdev
->small_buf_q_alloc_virt_addr
=
2165 pci_alloc_consistent(qdev
->pdev
,
2166 qdev
->small_buf_q_alloc_size
,
2167 &qdev
->small_buf_q_alloc_phy_addr
);
2169 if (qdev
->small_buf_q_alloc_virt_addr
== NULL
) {
2171 "%s: Small Buffer Queue allocation failed.\n",
2173 pci_free_consistent(qdev
->pdev
, qdev
->lrg_buf_q_alloc_size
,
2174 qdev
->lrg_buf_q_alloc_virt_addr
,
2175 qdev
->lrg_buf_q_alloc_phy_addr
);
2179 qdev
->small_buf_q_virt_addr
= qdev
->small_buf_q_alloc_virt_addr
;
2180 qdev
->small_buf_q_phy_addr
= qdev
->small_buf_q_alloc_phy_addr
;
2181 set_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
);
2185 static void ql_free_buffer_queues(struct ql3_adapter
*qdev
)
2187 if (!test_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
)) {
2188 printk(KERN_INFO PFX
2189 "%s: Already done.\n", qdev
->ndev
->name
);
2193 pci_free_consistent(qdev
->pdev
,
2194 qdev
->lrg_buf_q_alloc_size
,
2195 qdev
->lrg_buf_q_alloc_virt_addr
,
2196 qdev
->lrg_buf_q_alloc_phy_addr
);
2198 qdev
->lrg_buf_q_virt_addr
= NULL
;
2200 pci_free_consistent(qdev
->pdev
,
2201 qdev
->small_buf_q_alloc_size
,
2202 qdev
->small_buf_q_alloc_virt_addr
,
2203 qdev
->small_buf_q_alloc_phy_addr
);
2205 qdev
->small_buf_q_virt_addr
= NULL
;
2207 clear_bit(QL_ALLOC_BUFQS_DONE
,&qdev
->flags
);
2210 static int ql_alloc_small_buffers(struct ql3_adapter
*qdev
)
2213 struct bufq_addr_element
*small_buf_q_entry
;
2215 /* Currently we allocate on one of memory and use it for smallbuffers */
2216 qdev
->small_buf_total_size
=
2217 (QL_ADDR_ELE_PER_BUFQ_ENTRY
* NUM_SBUFQ_ENTRIES
*
2218 QL_SMALL_BUFFER_SIZE
);
2220 qdev
->small_buf_virt_addr
=
2221 pci_alloc_consistent(qdev
->pdev
,
2222 qdev
->small_buf_total_size
,
2223 &qdev
->small_buf_phy_addr
);
2225 if (qdev
->small_buf_virt_addr
== NULL
) {
2227 "%s: Failed to get small buffer memory.\n",
2232 qdev
->small_buf_phy_addr_low
= LS_64BITS(qdev
->small_buf_phy_addr
);
2233 qdev
->small_buf_phy_addr_high
= MS_64BITS(qdev
->small_buf_phy_addr
);
2235 small_buf_q_entry
= qdev
->small_buf_q_virt_addr
;
2237 qdev
->last_rsp_offset
= qdev
->small_buf_phy_addr_low
;
2239 /* Initialize the small buffer queue. */
2240 for (i
= 0; i
< (QL_ADDR_ELE_PER_BUFQ_ENTRY
* NUM_SBUFQ_ENTRIES
); i
++) {
2241 small_buf_q_entry
->addr_high
=
2242 cpu_to_le32(qdev
->small_buf_phy_addr_high
);
2243 small_buf_q_entry
->addr_low
=
2244 cpu_to_le32(qdev
->small_buf_phy_addr_low
+
2245 (i
* QL_SMALL_BUFFER_SIZE
));
2246 small_buf_q_entry
++;
2248 qdev
->small_buf_index
= 0;
2249 set_bit(QL_ALLOC_SMALL_BUF_DONE
,&qdev
->flags
);
2253 static void ql_free_small_buffers(struct ql3_adapter
*qdev
)
2255 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE
,&qdev
->flags
)) {
2256 printk(KERN_INFO PFX
2257 "%s: Already done.\n", qdev
->ndev
->name
);
2260 if (qdev
->small_buf_virt_addr
!= NULL
) {
2261 pci_free_consistent(qdev
->pdev
,
2262 qdev
->small_buf_total_size
,
2263 qdev
->small_buf_virt_addr
,
2264 qdev
->small_buf_phy_addr
);
2266 qdev
->small_buf_virt_addr
= NULL
;
2270 static void ql_free_large_buffers(struct ql3_adapter
*qdev
)
2273 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2275 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2276 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2277 if (lrg_buf_cb
->skb
) {
2278 dev_kfree_skb(lrg_buf_cb
->skb
);
2279 pci_unmap_single(qdev
->pdev
,
2280 pci_unmap_addr(lrg_buf_cb
, mapaddr
),
2281 pci_unmap_len(lrg_buf_cb
, maplen
),
2282 PCI_DMA_FROMDEVICE
);
2283 memset(lrg_buf_cb
, 0, sizeof(struct ql_rcv_buf_cb
));
2290 static void ql_init_large_buffers(struct ql3_adapter
*qdev
)
2293 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2294 struct bufq_addr_element
*buf_addr_ele
= qdev
->lrg_buf_q_virt_addr
;
2296 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2297 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2298 buf_addr_ele
->addr_high
= lrg_buf_cb
->buf_phy_addr_high
;
2299 buf_addr_ele
->addr_low
= lrg_buf_cb
->buf_phy_addr_low
;
2302 qdev
->lrg_buf_index
= 0;
2303 qdev
->lrg_buf_skb_check
= 0;
2306 static int ql_alloc_large_buffers(struct ql3_adapter
*qdev
)
2309 struct ql_rcv_buf_cb
*lrg_buf_cb
;
2310 struct sk_buff
*skb
;
2313 for (i
= 0; i
< NUM_LARGE_BUFFERS
; i
++) {
2314 skb
= dev_alloc_skb(qdev
->lrg_buffer_len
);
2315 if (unlikely(!skb
)) {
2316 /* Better luck next round */
2318 "%s: large buff alloc failed, "
2319 "for %d bytes at index %d.\n",
2321 qdev
->lrg_buffer_len
* 2, i
);
2322 ql_free_large_buffers(qdev
);
2326 lrg_buf_cb
= &qdev
->lrg_buf
[i
];
2327 memset(lrg_buf_cb
, 0, sizeof(struct ql_rcv_buf_cb
));
2328 lrg_buf_cb
->index
= i
;
2329 lrg_buf_cb
->skb
= skb
;
2331 * We save some space to copy the ethhdr from first
2334 skb_reserve(skb
, QL_HEADER_SPACE
);
2335 map
= pci_map_single(qdev
->pdev
,
2337 qdev
->lrg_buffer_len
-
2339 PCI_DMA_FROMDEVICE
);
2340 pci_unmap_addr_set(lrg_buf_cb
, mapaddr
, map
);
2341 pci_unmap_len_set(lrg_buf_cb
, maplen
,
2342 qdev
->lrg_buffer_len
-
2344 lrg_buf_cb
->buf_phy_addr_low
=
2345 cpu_to_le32(LS_64BITS(map
));
2346 lrg_buf_cb
->buf_phy_addr_high
=
2347 cpu_to_le32(MS_64BITS(map
));
2353 static void ql_create_send_free_list(struct ql3_adapter
*qdev
)
2355 struct ql_tx_buf_cb
*tx_cb
;
2357 struct ob_mac_iocb_req
*req_q_curr
=
2358 qdev
->req_q_virt_addr
;
2360 /* Create free list of transmit buffers */
2361 for (i
= 0; i
< NUM_REQ_Q_ENTRIES
; i
++) {
2362 tx_cb
= &qdev
->tx_buf
[i
];
2364 tx_cb
->queue_entry
= req_q_curr
;
2369 static int ql_alloc_mem_resources(struct ql3_adapter
*qdev
)
2371 if (qdev
->ndev
->mtu
== NORMAL_MTU_SIZE
)
2372 qdev
->lrg_buffer_len
= NORMAL_MTU_SIZE
;
2373 else if (qdev
->ndev
->mtu
== JUMBO_MTU_SIZE
) {
2374 qdev
->lrg_buffer_len
= JUMBO_MTU_SIZE
;
2377 "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n",
2381 qdev
->lrg_buffer_len
+= VLAN_ETH_HLEN
+ VLAN_ID_LEN
+ QL_HEADER_SPACE
;
2382 qdev
->max_frame_size
=
2383 (qdev
->lrg_buffer_len
- QL_HEADER_SPACE
) + ETHERNET_CRC_SIZE
;
2386 * First allocate a page of shared memory and use it for shadow
2387 * locations of Network Request Queue Consumer Address Register and
2388 * Network Completion Queue Producer Index Register
2390 qdev
->shadow_reg_virt_addr
=
2391 pci_alloc_consistent(qdev
->pdev
,
2392 PAGE_SIZE
, &qdev
->shadow_reg_phy_addr
);
2394 if (qdev
->shadow_reg_virt_addr
!= NULL
) {
2395 qdev
->preq_consumer_index
= (u16
*) qdev
->shadow_reg_virt_addr
;
2396 qdev
->req_consumer_index_phy_addr_high
=
2397 MS_64BITS(qdev
->shadow_reg_phy_addr
);
2398 qdev
->req_consumer_index_phy_addr_low
=
2399 LS_64BITS(qdev
->shadow_reg_phy_addr
);
2401 qdev
->prsp_producer_index
=
2402 (u32
*) (((u8
*) qdev
->preq_consumer_index
) + 8);
2403 qdev
->rsp_producer_index_phy_addr_high
=
2404 qdev
->req_consumer_index_phy_addr_high
;
2405 qdev
->rsp_producer_index_phy_addr_low
=
2406 qdev
->req_consumer_index_phy_addr_low
+ 8;
2409 "%s: shadowReg Alloc failed.\n", qdev
->ndev
->name
);
2413 if (ql_alloc_net_req_rsp_queues(qdev
) != 0) {
2415 "%s: ql_alloc_net_req_rsp_queues failed.\n",
2420 if (ql_alloc_buffer_queues(qdev
) != 0) {
2422 "%s: ql_alloc_buffer_queues failed.\n",
2424 goto err_buffer_queues
;
2427 if (ql_alloc_small_buffers(qdev
) != 0) {
2429 "%s: ql_alloc_small_buffers failed\n", qdev
->ndev
->name
);
2430 goto err_small_buffers
;
2433 if (ql_alloc_large_buffers(qdev
) != 0) {
2435 "%s: ql_alloc_large_buffers failed\n", qdev
->ndev
->name
);
2436 goto err_small_buffers
;
2439 /* Initialize the large buffer queue. */
2440 ql_init_large_buffers(qdev
);
2441 ql_create_send_free_list(qdev
);
2443 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
2448 ql_free_buffer_queues(qdev
);
2450 ql_free_net_req_rsp_queues(qdev
);
2452 pci_free_consistent(qdev
->pdev
,
2454 qdev
->shadow_reg_virt_addr
,
2455 qdev
->shadow_reg_phy_addr
);
2460 static void ql_free_mem_resources(struct ql3_adapter
*qdev
)
2462 ql_free_large_buffers(qdev
);
2463 ql_free_small_buffers(qdev
);
2464 ql_free_buffer_queues(qdev
);
2465 ql_free_net_req_rsp_queues(qdev
);
2466 if (qdev
->shadow_reg_virt_addr
!= NULL
) {
2467 pci_free_consistent(qdev
->pdev
,
2469 qdev
->shadow_reg_virt_addr
,
2470 qdev
->shadow_reg_phy_addr
);
2471 qdev
->shadow_reg_virt_addr
= NULL
;
2475 static int ql_init_misc_registers(struct ql3_adapter
*qdev
)
2477 struct ql3xxx_local_ram_registers __iomem
*local_ram
=
2478 (void __iomem
*)qdev
->mem_map_registers
;
2480 if(ql_sem_spinlock(qdev
, QL_DDR_RAM_SEM_MASK
,
2481 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
2485 ql_write_page2_reg(qdev
,
2486 &local_ram
->bufletSize
, qdev
->nvram_data
.bufletSize
);
2488 ql_write_page2_reg(qdev
,
2489 &local_ram
->maxBufletCount
,
2490 qdev
->nvram_data
.bufletCount
);
2492 ql_write_page2_reg(qdev
,
2493 &local_ram
->freeBufletThresholdLow
,
2494 (qdev
->nvram_data
.tcpWindowThreshold25
<< 16) |
2495 (qdev
->nvram_data
.tcpWindowThreshold0
));
2497 ql_write_page2_reg(qdev
,
2498 &local_ram
->freeBufletThresholdHigh
,
2499 qdev
->nvram_data
.tcpWindowThreshold50
);
2501 ql_write_page2_reg(qdev
,
2502 &local_ram
->ipHashTableBase
,
2503 (qdev
->nvram_data
.ipHashTableBaseHi
<< 16) |
2504 qdev
->nvram_data
.ipHashTableBaseLo
);
2505 ql_write_page2_reg(qdev
,
2506 &local_ram
->ipHashTableCount
,
2507 qdev
->nvram_data
.ipHashTableSize
);
2508 ql_write_page2_reg(qdev
,
2509 &local_ram
->tcpHashTableBase
,
2510 (qdev
->nvram_data
.tcpHashTableBaseHi
<< 16) |
2511 qdev
->nvram_data
.tcpHashTableBaseLo
);
2512 ql_write_page2_reg(qdev
,
2513 &local_ram
->tcpHashTableCount
,
2514 qdev
->nvram_data
.tcpHashTableSize
);
2515 ql_write_page2_reg(qdev
,
2516 &local_ram
->ncbBase
,
2517 (qdev
->nvram_data
.ncbTableBaseHi
<< 16) |
2518 qdev
->nvram_data
.ncbTableBaseLo
);
2519 ql_write_page2_reg(qdev
,
2520 &local_ram
->maxNcbCount
,
2521 qdev
->nvram_data
.ncbTableSize
);
2522 ql_write_page2_reg(qdev
,
2523 &local_ram
->drbBase
,
2524 (qdev
->nvram_data
.drbTableBaseHi
<< 16) |
2525 qdev
->nvram_data
.drbTableBaseLo
);
2526 ql_write_page2_reg(qdev
,
2527 &local_ram
->maxDrbCount
,
2528 qdev
->nvram_data
.drbTableSize
);
2529 ql_sem_unlock(qdev
, QL_DDR_RAM_SEM_MASK
);
2533 static int ql_adapter_initialize(struct ql3_adapter
*qdev
)
2536 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2537 struct ql3xxx_host_memory_registers __iomem
*hmem_regs
=
2538 (void __iomem
*)port_regs
;
2542 if(ql_mii_setup(qdev
))
2545 /* Bring out PHY out of reset */
2546 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
2547 (ISP_SERIAL_PORT_IF_WE
|
2548 (ISP_SERIAL_PORT_IF_WE
<< 16)));
2550 qdev
->port_link_state
= LS_DOWN
;
2551 netif_carrier_off(qdev
->ndev
);
2553 /* V2 chip fix for ARS-39168. */
2554 ql_write_common_reg(qdev
, &port_regs
->CommonRegs
.serialPortInterfaceReg
,
2555 (ISP_SERIAL_PORT_IF_SDE
|
2556 (ISP_SERIAL_PORT_IF_SDE
<< 16)));
2558 /* Request Queue Registers */
2559 *((u32
*) (qdev
->preq_consumer_index
)) = 0;
2560 atomic_set(&qdev
->tx_count
,NUM_REQ_Q_ENTRIES
);
2561 qdev
->req_producer_index
= 0;
2563 ql_write_page1_reg(qdev
,
2564 &hmem_regs
->reqConsumerIndexAddrHigh
,
2565 qdev
->req_consumer_index_phy_addr_high
);
2566 ql_write_page1_reg(qdev
,
2567 &hmem_regs
->reqConsumerIndexAddrLow
,
2568 qdev
->req_consumer_index_phy_addr_low
);
2570 ql_write_page1_reg(qdev
,
2571 &hmem_regs
->reqBaseAddrHigh
,
2572 MS_64BITS(qdev
->req_q_phy_addr
));
2573 ql_write_page1_reg(qdev
,
2574 &hmem_regs
->reqBaseAddrLow
,
2575 LS_64BITS(qdev
->req_q_phy_addr
));
2576 ql_write_page1_reg(qdev
, &hmem_regs
->reqLength
, NUM_REQ_Q_ENTRIES
);
2578 /* Response Queue Registers */
2579 *((u16
*) (qdev
->prsp_producer_index
)) = 0;
2580 qdev
->rsp_consumer_index
= 0;
2581 qdev
->rsp_current
= qdev
->rsp_q_virt_addr
;
2583 ql_write_page1_reg(qdev
,
2584 &hmem_regs
->rspProducerIndexAddrHigh
,
2585 qdev
->rsp_producer_index_phy_addr_high
);
2587 ql_write_page1_reg(qdev
,
2588 &hmem_regs
->rspProducerIndexAddrLow
,
2589 qdev
->rsp_producer_index_phy_addr_low
);
2591 ql_write_page1_reg(qdev
,
2592 &hmem_regs
->rspBaseAddrHigh
,
2593 MS_64BITS(qdev
->rsp_q_phy_addr
));
2595 ql_write_page1_reg(qdev
,
2596 &hmem_regs
->rspBaseAddrLow
,
2597 LS_64BITS(qdev
->rsp_q_phy_addr
));
2599 ql_write_page1_reg(qdev
, &hmem_regs
->rspLength
, NUM_RSP_Q_ENTRIES
);
2601 /* Large Buffer Queue */
2602 ql_write_page1_reg(qdev
,
2603 &hmem_regs
->rxLargeQBaseAddrHigh
,
2604 MS_64BITS(qdev
->lrg_buf_q_phy_addr
));
2606 ql_write_page1_reg(qdev
,
2607 &hmem_regs
->rxLargeQBaseAddrLow
,
2608 LS_64BITS(qdev
->lrg_buf_q_phy_addr
));
2610 ql_write_page1_reg(qdev
, &hmem_regs
->rxLargeQLength
, NUM_LBUFQ_ENTRIES
);
2612 ql_write_page1_reg(qdev
,
2613 &hmem_regs
->rxLargeBufferLength
,
2614 qdev
->lrg_buffer_len
);
2616 /* Small Buffer Queue */
2617 ql_write_page1_reg(qdev
,
2618 &hmem_regs
->rxSmallQBaseAddrHigh
,
2619 MS_64BITS(qdev
->small_buf_q_phy_addr
));
2621 ql_write_page1_reg(qdev
,
2622 &hmem_regs
->rxSmallQBaseAddrLow
,
2623 LS_64BITS(qdev
->small_buf_q_phy_addr
));
2625 ql_write_page1_reg(qdev
, &hmem_regs
->rxSmallQLength
, NUM_SBUFQ_ENTRIES
);
2626 ql_write_page1_reg(qdev
,
2627 &hmem_regs
->rxSmallBufferLength
,
2628 QL_SMALL_BUFFER_SIZE
);
2630 qdev
->small_buf_q_producer_index
= NUM_SBUFQ_ENTRIES
- 1;
2631 qdev
->small_buf_release_cnt
= 8;
2632 qdev
->lrg_buf_q_producer_index
= NUM_LBUFQ_ENTRIES
- 1;
2633 qdev
->lrg_buf_release_cnt
= 8;
2634 qdev
->lrg_buf_next_free
=
2635 (struct bufq_addr_element
*)qdev
->lrg_buf_q_virt_addr
;
2636 qdev
->small_buf_index
= 0;
2637 qdev
->lrg_buf_index
= 0;
2638 qdev
->lrg_buf_free_count
= 0;
2639 qdev
->lrg_buf_free_head
= NULL
;
2640 qdev
->lrg_buf_free_tail
= NULL
;
2642 ql_write_common_reg(qdev
,
2643 &port_regs
->CommonRegs
.
2644 rxSmallQProducerIndex
,
2645 qdev
->small_buf_q_producer_index
);
2646 ql_write_common_reg(qdev
,
2647 &port_regs
->CommonRegs
.
2648 rxLargeQProducerIndex
,
2649 qdev
->lrg_buf_q_producer_index
);
2652 * Find out if the chip has already been initialized. If it has, then
2653 * we skip some of the initialization.
2655 clear_bit(QL_LINK_MASTER
, &qdev
->flags
);
2656 value
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
2657 if ((value
& PORT_STATUS_IC
) == 0) {
2659 /* Chip has not been configured yet, so let it rip. */
2660 if(ql_init_misc_registers(qdev
)) {
2665 if (qdev
->mac_index
)
2666 ql_write_page0_reg(qdev
,
2667 &port_regs
->mac1MaxFrameLengthReg
,
2668 qdev
->max_frame_size
);
2670 ql_write_page0_reg(qdev
,
2671 &port_regs
->mac0MaxFrameLengthReg
,
2672 qdev
->max_frame_size
);
2674 value
= qdev
->nvram_data
.tcpMaxWindowSize
;
2675 ql_write_page0_reg(qdev
, &port_regs
->tcpMaxWindow
, value
);
2677 value
= (0xFFFF << 16) | qdev
->nvram_data
.extHwConfig
;
2679 if(ql_sem_spinlock(qdev
, QL_FLASH_SEM_MASK
,
2680 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
)
2685 ql_write_page0_reg(qdev
, &port_regs
->ExternalHWConfig
, value
);
2686 ql_write_page0_reg(qdev
, &port_regs
->InternalChipConfig
,
2687 (((INTERNAL_CHIP_SD
| INTERNAL_CHIP_WE
) <<
2688 16) | (INTERNAL_CHIP_SD
|
2689 INTERNAL_CHIP_WE
)));
2690 ql_sem_unlock(qdev
, QL_FLASH_SEM_MASK
);
2694 if(ql_sem_spinlock(qdev
, QL_PHY_GIO_SEM_MASK
,
2695 (QL_RESOURCE_BITS_BASE_CODE
| (qdev
->mac_index
) *
2701 ql_init_scan_mode(qdev
);
2702 ql_get_phy_owner(qdev
);
2704 /* Load the MAC Configuration */
2706 /* Program lower 32 bits of the MAC address */
2707 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2708 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16));
2709 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
2710 ((qdev
->ndev
->dev_addr
[2] << 24)
2711 | (qdev
->ndev
->dev_addr
[3] << 16)
2712 | (qdev
->ndev
->dev_addr
[4] << 8)
2713 | qdev
->ndev
->dev_addr
[5]));
2715 /* Program top 16 bits of the MAC address */
2716 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2717 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16) | 1));
2718 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
2719 ((qdev
->ndev
->dev_addr
[0] << 8)
2720 | qdev
->ndev
->dev_addr
[1]));
2722 /* Enable Primary MAC */
2723 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
2724 ((MAC_ADDR_INDIRECT_PTR_REG_PE
<< 16) |
2725 MAC_ADDR_INDIRECT_PTR_REG_PE
));
2727 /* Clear Primary and Secondary IP addresses */
2728 ql_write_page0_reg(qdev
, &port_regs
->ipAddrIndexReg
,
2729 ((IP_ADDR_INDEX_REG_MASK
<< 16) |
2730 (qdev
->mac_index
<< 2)));
2731 ql_write_page0_reg(qdev
, &port_regs
->ipAddrDataReg
, 0);
2733 ql_write_page0_reg(qdev
, &port_regs
->ipAddrIndexReg
,
2734 ((IP_ADDR_INDEX_REG_MASK
<< 16) |
2735 ((qdev
->mac_index
<< 2) + 1)));
2736 ql_write_page0_reg(qdev
, &port_regs
->ipAddrDataReg
, 0);
2738 ql_sem_unlock(qdev
, QL_PHY_GIO_SEM_MASK
);
2740 /* Indicate Configuration Complete */
2741 ql_write_page0_reg(qdev
,
2742 &port_regs
->portControl
,
2743 ((PORT_CONTROL_CC
<< 16) | PORT_CONTROL_CC
));
2746 value
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
2747 if (value
& PORT_STATUS_IC
)
2754 "%s: Hw Initialization timeout.\n", qdev
->ndev
->name
);
2759 /* Enable Ethernet Function */
2761 (PORT_CONTROL_EF
| PORT_CONTROL_ET
| PORT_CONTROL_EI
|
2763 ql_write_page0_reg(qdev
, &port_regs
->portControl
,
2764 ((value
<< 16) | value
));
2771 * Caller holds hw_lock.
2773 static int ql_adapter_reset(struct ql3_adapter
*qdev
)
2775 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2780 set_bit(QL_RESET_ACTIVE
, &qdev
->flags
);
2781 clear_bit(QL_RESET_DONE
, &qdev
->flags
);
2784 * Issue soft reset to chip.
2786 printk(KERN_DEBUG PFX
2787 "%s: Issue soft reset to chip.\n",
2789 ql_write_common_reg(qdev
,
2790 &port_regs
->CommonRegs
.ispControlStatus
,
2791 ((ISP_CONTROL_SR
<< 16) | ISP_CONTROL_SR
));
2793 /* Wait 3 seconds for reset to complete. */
2794 printk(KERN_DEBUG PFX
2795 "%s: Wait 10 milliseconds for reset to complete.\n",
2798 /* Wait until the firmware tells us the Soft Reset is done */
2802 ql_read_common_reg(qdev
,
2803 &port_regs
->CommonRegs
.ispControlStatus
);
2804 if ((value
& ISP_CONTROL_SR
) == 0)
2808 } while ((--max_wait_time
));
2811 * Also, make sure that the Network Reset Interrupt bit has been
2812 * cleared after the soft reset has taken place.
2815 ql_read_common_reg(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
2816 if (value
& ISP_CONTROL_RI
) {
2817 printk(KERN_DEBUG PFX
2818 "ql_adapter_reset: clearing RI after reset.\n");
2819 ql_write_common_reg(qdev
,
2820 &port_regs
->CommonRegs
.
2822 ((ISP_CONTROL_RI
<< 16) | ISP_CONTROL_RI
));
2825 if (max_wait_time
== 0) {
2826 /* Issue Force Soft Reset */
2827 ql_write_common_reg(qdev
,
2828 &port_regs
->CommonRegs
.
2830 ((ISP_CONTROL_FSR
<< 16) |
2833 * Wait until the firmware tells us the Force Soft Reset is
2839 ql_read_common_reg(qdev
,
2840 &port_regs
->CommonRegs
.
2842 if ((value
& ISP_CONTROL_FSR
) == 0) {
2846 } while ((--max_wait_time
));
2848 if (max_wait_time
== 0)
2851 clear_bit(QL_RESET_ACTIVE
, &qdev
->flags
);
2852 set_bit(QL_RESET_DONE
, &qdev
->flags
);
2856 static void ql_set_mac_info(struct ql3_adapter
*qdev
)
2858 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
2859 u32 value
, port_status
;
2862 /* Get the function number */
2864 ql_read_common_reg_l(qdev
, &port_regs
->CommonRegs
.ispControlStatus
);
2865 func_number
= (u8
) ((value
>> 4) & OPCODE_FUNC_ID_MASK
);
2866 port_status
= ql_read_page0_reg(qdev
, &port_regs
->portStatus
);
2867 switch (value
& ISP_CONTROL_FN_MASK
) {
2868 case ISP_CONTROL_FN0_NET
:
2869 qdev
->mac_index
= 0;
2870 qdev
->mac_ob_opcode
= OUTBOUND_MAC_IOCB
| func_number
;
2871 qdev
->tcp_ob_opcode
= OUTBOUND_TCP_IOCB
| func_number
;
2872 qdev
->update_ob_opcode
= UPDATE_NCB_IOCB
| func_number
;
2873 qdev
->mb_bit_mask
= FN0_MA_BITS_MASK
;
2874 qdev
->PHYAddr
= PORT0_PHY_ADDRESS
;
2875 if (port_status
& PORT_STATUS_SM0
)
2876 set_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
2878 clear_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
2881 case ISP_CONTROL_FN1_NET
:
2882 qdev
->mac_index
= 1;
2883 qdev
->mac_ob_opcode
= OUTBOUND_MAC_IOCB
| func_number
;
2884 qdev
->tcp_ob_opcode
= OUTBOUND_TCP_IOCB
| func_number
;
2885 qdev
->update_ob_opcode
= UPDATE_NCB_IOCB
| func_number
;
2886 qdev
->mb_bit_mask
= FN1_MA_BITS_MASK
;
2887 qdev
->PHYAddr
= PORT1_PHY_ADDRESS
;
2888 if (port_status
& PORT_STATUS_SM1
)
2889 set_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
2891 clear_bit(QL_LINK_OPTICAL
,&qdev
->flags
);
2894 case ISP_CONTROL_FN0_SCSI
:
2895 case ISP_CONTROL_FN1_SCSI
:
2897 printk(KERN_DEBUG PFX
2898 "%s: Invalid function number, ispControlStatus = 0x%x\n",
2899 qdev
->ndev
->name
,value
);
2902 qdev
->numPorts
= qdev
->nvram_data
.numPorts
;
2905 static void ql_display_dev_info(struct net_device
*ndev
)
2907 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
2908 struct pci_dev
*pdev
= qdev
->pdev
;
2910 printk(KERN_INFO PFX
2911 "\n%s Adapter %d RevisionID %d found on PCI slot %d.\n",
2912 DRV_NAME
, qdev
->index
, qdev
->chip_rev_id
, qdev
->pci_slot
);
2913 printk(KERN_INFO PFX
2915 test_bit(QL_LINK_OPTICAL
,&qdev
->flags
) ? "OPTICAL" : "COPPER");
2918 * Print PCI bus width/type.
2920 printk(KERN_INFO PFX
2921 "Bus interface is %s %s.\n",
2922 ((qdev
->pci_width
== 64) ? "64-bit" : "32-bit"),
2923 ((qdev
->pci_x
) ? "PCI-X" : "PCI"));
2925 printk(KERN_INFO PFX
2926 "mem IO base address adjusted = 0x%p\n",
2927 qdev
->mem_map_registers
);
2928 printk(KERN_INFO PFX
"Interrupt number = %d\n", pdev
->irq
);
2930 if (netif_msg_probe(qdev
))
2931 printk(KERN_INFO PFX
2932 "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n",
2933 ndev
->name
, ndev
->dev_addr
[0], ndev
->dev_addr
[1],
2934 ndev
->dev_addr
[2], ndev
->dev_addr
[3], ndev
->dev_addr
[4],
2938 static int ql_adapter_down(struct ql3_adapter
*qdev
, int do_reset
)
2940 struct net_device
*ndev
= qdev
->ndev
;
2943 netif_stop_queue(ndev
);
2944 netif_carrier_off(ndev
);
2946 clear_bit(QL_ADAPTER_UP
,&qdev
->flags
);
2947 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
2949 ql_disable_interrupts(qdev
);
2951 free_irq(qdev
->pdev
->irq
, ndev
);
2953 if (qdev
->msi
&& test_bit(QL_MSI_ENABLED
,&qdev
->flags
)) {
2954 printk(KERN_INFO PFX
2955 "%s: calling pci_disable_msi().\n", qdev
->ndev
->name
);
2956 clear_bit(QL_MSI_ENABLED
,&qdev
->flags
);
2957 pci_disable_msi(qdev
->pdev
);
2960 del_timer_sync(&qdev
->adapter_timer
);
2962 netif_poll_disable(ndev
);
2966 unsigned long hw_flags
;
2968 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
2969 if (ql_wait_for_drvr_lock(qdev
)) {
2970 if ((soft_reset
= ql_adapter_reset(qdev
))) {
2972 "%s: ql_adapter_reset(%d) FAILED!\n",
2973 ndev
->name
, qdev
->index
);
2976 "%s: Releaseing driver lock via chip reset.\n",ndev
->name
);
2979 "%s: Could not acquire driver lock to do "
2980 "reset!\n", ndev
->name
);
2983 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
2985 ql_free_mem_resources(qdev
);
2989 static int ql_adapter_up(struct ql3_adapter
*qdev
)
2991 struct net_device
*ndev
= qdev
->ndev
;
2993 unsigned long irq_flags
= SA_SAMPLE_RANDOM
| SA_SHIRQ
;
2994 unsigned long hw_flags
;
2996 if (ql_alloc_mem_resources(qdev
)) {
2998 "%s Unable to allocate buffers.\n", ndev
->name
);
3003 if (pci_enable_msi(qdev
->pdev
)) {
3005 "%s: User requested MSI, but MSI failed to "
3006 "initialize. Continuing without MSI.\n",
3010 printk(KERN_INFO PFX
"%s: MSI Enabled...\n", qdev
->ndev
->name
);
3011 set_bit(QL_MSI_ENABLED
,&qdev
->flags
);
3012 irq_flags
&= ~SA_SHIRQ
;
3016 if ((err
= request_irq(qdev
->pdev
->irq
,
3018 irq_flags
, ndev
->name
, ndev
))) {
3020 "%s: Failed to reserve interrupt %d already in use.\n",
3021 ndev
->name
, qdev
->pdev
->irq
);
3025 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3027 if ((err
= ql_wait_for_drvr_lock(qdev
))) {
3028 if ((err
= ql_adapter_initialize(qdev
))) {
3030 "%s: Unable to initialize adapter.\n",
3035 "%s: Releaseing driver lock.\n",ndev
->name
);
3036 ql_sem_unlock(qdev
, QL_DRVR_SEM_MASK
);
3039 "%s: Could not aquire driver lock.\n",
3044 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3046 set_bit(QL_ADAPTER_UP
,&qdev
->flags
);
3048 mod_timer(&qdev
->adapter_timer
, jiffies
+ HZ
* 1);
3050 netif_poll_enable(ndev
);
3051 ql_enable_interrupts(qdev
);
3055 ql_sem_unlock(qdev
, QL_DRVR_SEM_MASK
);
3057 free_irq(qdev
->pdev
->irq
, ndev
);
3059 if (qdev
->msi
&& test_bit(QL_MSI_ENABLED
,&qdev
->flags
)) {
3060 printk(KERN_INFO PFX
3061 "%s: calling pci_disable_msi().\n",
3063 clear_bit(QL_MSI_ENABLED
,&qdev
->flags
);
3064 pci_disable_msi(qdev
->pdev
);
3069 static int ql_cycle_adapter(struct ql3_adapter
*qdev
, int reset
)
3071 if( ql_adapter_down(qdev
,reset
) || ql_adapter_up(qdev
)) {
3073 "%s: Driver up/down cycle failed, "
3074 "closing device\n",qdev
->ndev
->name
);
3075 dev_close(qdev
->ndev
);
3081 static int ql3xxx_close(struct net_device
*ndev
)
3083 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3086 * Wait for device to recover from a reset.
3087 * (Rarely happens, but possible.)
3089 while (!test_bit(QL_ADAPTER_UP
,&qdev
->flags
))
3092 ql_adapter_down(qdev
,QL_DO_RESET
);
3096 static int ql3xxx_open(struct net_device
*ndev
)
3098 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3099 return (ql_adapter_up(qdev
));
3102 static struct net_device_stats
*ql3xxx_get_stats(struct net_device
*dev
)
3104 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)dev
->priv
;
3105 return &qdev
->stats
;
3108 static int ql3xxx_change_mtu(struct net_device
*ndev
, int new_mtu
)
3110 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3111 printk(KERN_ERR PFX
"%s: new mtu size = %d.\n", ndev
->name
, new_mtu
);
3112 if (new_mtu
!= NORMAL_MTU_SIZE
&& new_mtu
!= JUMBO_MTU_SIZE
) {
3114 "%s: mtu size of %d is not valid. Use exactly %d or "
3115 "%d.\n", ndev
->name
, new_mtu
, NORMAL_MTU_SIZE
,
3120 if (!netif_running(ndev
)) {
3121 ndev
->mtu
= new_mtu
;
3125 ndev
->mtu
= new_mtu
;
3126 return ql_cycle_adapter(qdev
,QL_DO_RESET
);
3129 static void ql3xxx_set_multicast_list(struct net_device
*ndev
)
3132 * We are manually parsing the list in the net_device structure.
3137 static int ql3xxx_set_mac_address(struct net_device
*ndev
, void *p
)
3139 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
3140 struct ql3xxx_port_registers __iomem
*port_regs
=
3141 qdev
->mem_map_registers
;
3142 struct sockaddr
*addr
= p
;
3143 unsigned long hw_flags
;
3145 if (netif_running(ndev
))
3148 if (!is_valid_ether_addr(addr
->sa_data
))
3149 return -EADDRNOTAVAIL
;
3151 memcpy(ndev
->dev_addr
, addr
->sa_data
, ndev
->addr_len
);
3153 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3154 /* Program lower 32 bits of the MAC address */
3155 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
3156 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16));
3157 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
3158 ((ndev
->dev_addr
[2] << 24) | (ndev
->
3159 dev_addr
[3] << 16) |
3160 (ndev
->dev_addr
[4] << 8) | ndev
->dev_addr
[5]));
3162 /* Program top 16 bits of the MAC address */
3163 ql_write_page0_reg(qdev
, &port_regs
->macAddrIndirectPtrReg
,
3164 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK
<< 16) | 1));
3165 ql_write_page0_reg(qdev
, &port_regs
->macAddrDataReg
,
3166 ((ndev
->dev_addr
[0] << 8) | ndev
->dev_addr
[1]));
3167 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3172 static void ql3xxx_tx_timeout(struct net_device
*ndev
)
3174 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)netdev_priv(ndev
);
3176 printk(KERN_ERR PFX
"%s: Resetting...\n", ndev
->name
);
3178 * Stop the queues, we've got a problem.
3180 netif_stop_queue(ndev
);
3183 * Wake up the worker to process this event.
3185 queue_work(qdev
->workqueue
, &qdev
->tx_timeout_work
);
3188 static void ql_reset_work(struct ql3_adapter
*qdev
)
3190 struct net_device
*ndev
= qdev
->ndev
;
3192 struct ql_tx_buf_cb
*tx_cb
;
3193 int max_wait_time
, i
;
3194 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3195 unsigned long hw_flags
;
3197 if (test_bit((QL_RESET_PER_SCSI
| QL_RESET_START
),&qdev
->flags
)) {
3198 clear_bit(QL_LINK_MASTER
,&qdev
->flags
);
3201 * Loop through the active list and return the skb.
3203 for (i
= 0; i
< NUM_REQ_Q_ENTRIES
; i
++) {
3204 tx_cb
= &qdev
->tx_buf
[i
];
3207 printk(KERN_DEBUG PFX
3208 "%s: Freeing lost SKB.\n",
3210 pci_unmap_single(qdev
->pdev
,
3211 pci_unmap_addr(tx_cb
, mapaddr
),
3212 pci_unmap_len(tx_cb
, maplen
), PCI_DMA_TODEVICE
);
3213 dev_kfree_skb(tx_cb
->skb
);
3219 "%s: Clearing NRI after reset.\n", qdev
->ndev
->name
);
3220 spin_lock_irqsave(&qdev
->hw_lock
, hw_flags
);
3221 ql_write_common_reg(qdev
,
3222 &port_regs
->CommonRegs
.
3224 ((ISP_CONTROL_RI
<< 16) | ISP_CONTROL_RI
));
3226 * Wait the for Soft Reset to Complete.
3230 value
= ql_read_common_reg(qdev
,
3231 &port_regs
->CommonRegs
.
3234 if ((value
& ISP_CONTROL_SR
) == 0) {
3235 printk(KERN_DEBUG PFX
3236 "%s: reset completed.\n",
3241 if (value
& ISP_CONTROL_RI
) {
3242 printk(KERN_DEBUG PFX
3243 "%s: clearing NRI after reset.\n",
3245 ql_write_common_reg(qdev
,
3250 16) | ISP_CONTROL_RI
));
3254 } while (--max_wait_time
);
3255 spin_unlock_irqrestore(&qdev
->hw_lock
, hw_flags
);
3257 if (value
& ISP_CONTROL_SR
) {
3260 * Set the reset flags and clear the board again.
3261 * Nothing else to do...
3264 "%s: Timed out waiting for reset to "
3265 "complete.\n", ndev
->name
);
3267 "%s: Do a reset.\n", ndev
->name
);
3268 clear_bit(QL_RESET_PER_SCSI
,&qdev
->flags
);
3269 clear_bit(QL_RESET_START
,&qdev
->flags
);
3270 ql_cycle_adapter(qdev
,QL_DO_RESET
);
3274 clear_bit(QL_RESET_ACTIVE
,&qdev
->flags
);
3275 clear_bit(QL_RESET_PER_SCSI
,&qdev
->flags
);
3276 clear_bit(QL_RESET_START
,&qdev
->flags
);
3277 ql_cycle_adapter(qdev
,QL_NO_RESET
);
3281 static void ql_tx_timeout_work(struct ql3_adapter
*qdev
)
3283 ql_cycle_adapter(qdev
,QL_DO_RESET
);
3286 static void ql_get_board_info(struct ql3_adapter
*qdev
)
3288 struct ql3xxx_port_registers __iomem
*port_regs
= qdev
->mem_map_registers
;
3291 value
= ql_read_page0_reg_l(qdev
, &port_regs
->portStatus
);
3293 qdev
->chip_rev_id
= ((value
& PORT_STATUS_REV_ID_MASK
) >> 12);
3294 if (value
& PORT_STATUS_64
)
3295 qdev
->pci_width
= 64;
3297 qdev
->pci_width
= 32;
3298 if (value
& PORT_STATUS_X
)
3302 qdev
->pci_slot
= (u8
) PCI_SLOT(qdev
->pdev
->devfn
);
3305 static void ql3xxx_timer(unsigned long ptr
)
3307 struct ql3_adapter
*qdev
= (struct ql3_adapter
*)ptr
;
3309 if (test_bit(QL_RESET_ACTIVE
,&qdev
->flags
)) {
3310 printk(KERN_DEBUG PFX
3311 "%s: Reset in progress.\n",
3316 ql_link_state_machine(qdev
);
3318 /* Restart timer on 2 second interval. */
3320 mod_timer(&qdev
->adapter_timer
, jiffies
+ HZ
* 1);
3323 static int __devinit
ql3xxx_probe(struct pci_dev
*pdev
,
3324 const struct pci_device_id
*pci_entry
)
3326 struct net_device
*ndev
= NULL
;
3327 struct ql3_adapter
*qdev
= NULL
;
3328 static int cards_found
= 0;
3329 int pci_using_dac
, err
;
3331 err
= pci_enable_device(pdev
);
3333 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3338 err
= pci_request_regions(pdev
, DRV_NAME
);
3340 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3342 goto err_out_disable_pdev
;
3345 pci_set_master(pdev
);
3347 if (!pci_set_dma_mask(pdev
, DMA_64BIT_MASK
)) {
3349 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3350 } else if (!(err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
))) {
3352 err
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
3356 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3358 goto err_out_free_regions
;
3361 ndev
= alloc_etherdev(sizeof(struct ql3_adapter
));
3363 goto err_out_free_regions
;
3365 SET_MODULE_OWNER(ndev
);
3366 SET_NETDEV_DEV(ndev
, &pdev
->dev
);
3368 ndev
->features
= NETIF_F_LLTX
;
3370 ndev
->features
|= NETIF_F_HIGHDMA
;
3372 pci_set_drvdata(pdev
, ndev
);
3374 qdev
= netdev_priv(ndev
);
3375 qdev
->index
= cards_found
;
3378 qdev
->port_link_state
= LS_DOWN
;
3382 qdev
->msg_enable
= netif_msg_init(debug
, default_msg
);
3384 qdev
->mem_map_registers
=
3385 ioremap_nocache(pci_resource_start(pdev
, 1),
3386 pci_resource_len(qdev
->pdev
, 1));
3387 if (!qdev
->mem_map_registers
) {
3388 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3390 goto err_out_free_ndev
;
3393 spin_lock_init(&qdev
->adapter_lock
);
3394 spin_lock_init(&qdev
->hw_lock
);
3396 /* Set driver entry points */
3397 ndev
->open
= ql3xxx_open
;
3398 ndev
->hard_start_xmit
= ql3xxx_send
;
3399 ndev
->stop
= ql3xxx_close
;
3400 ndev
->get_stats
= ql3xxx_get_stats
;
3401 ndev
->change_mtu
= ql3xxx_change_mtu
;
3402 ndev
->set_multicast_list
= ql3xxx_set_multicast_list
;
3403 SET_ETHTOOL_OPS(ndev
, &ql3xxx_ethtool_ops
);
3404 ndev
->set_mac_address
= ql3xxx_set_mac_address
;
3405 ndev
->tx_timeout
= ql3xxx_tx_timeout
;
3406 ndev
->watchdog_timeo
= 5 * HZ
;
3408 ndev
->poll
= &ql_poll
;
3411 ndev
->irq
= pdev
->irq
;
3413 /* make sure the EEPROM is good */
3414 if (ql_get_nvram_params(qdev
)) {
3415 printk(KERN_ALERT PFX
3416 "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n",
3418 goto err_out_iounmap
;
3421 ql_set_mac_info(qdev
);
3423 /* Validate and set parameters */
3424 if (qdev
->mac_index
) {
3425 memcpy(ndev
->dev_addr
, &qdev
->nvram_data
.funcCfg_fn2
.macAddress
,
3428 memcpy(ndev
->dev_addr
, &qdev
->nvram_data
.funcCfg_fn0
.macAddress
,
3431 memcpy(ndev
->perm_addr
, ndev
->dev_addr
, ndev
->addr_len
);
3433 ndev
->tx_queue_len
= NUM_REQ_Q_ENTRIES
;
3435 /* Turn off support for multicasting */
3436 ndev
->flags
&= ~IFF_MULTICAST
;
3438 /* Record PCI bus information. */
3439 ql_get_board_info(qdev
);
3442 * Set the Maximum Memory Read Byte Count value. We do this to handle
3446 pci_write_config_word(pdev
, (int)0x4e, (u16
) 0x0036);
3449 err
= register_netdev(ndev
);
3451 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3453 goto err_out_iounmap
;
3456 /* we're going to reset, so assume we have no link for now */
3458 netif_carrier_off(ndev
);
3459 netif_stop_queue(ndev
);
3461 qdev
->workqueue
= create_singlethread_workqueue(ndev
->name
);
3462 INIT_WORK(&qdev
->reset_work
, (void (*)(void *))ql_reset_work
, qdev
);
3463 INIT_WORK(&qdev
->tx_timeout_work
,
3464 (void (*)(void *))ql_tx_timeout_work
, qdev
);
3466 init_timer(&qdev
->adapter_timer
);
3467 qdev
->adapter_timer
.function
= ql3xxx_timer
;
3468 qdev
->adapter_timer
.expires
= jiffies
+ HZ
* 2; /* two second delay */
3469 qdev
->adapter_timer
.data
= (unsigned long)qdev
;
3472 printk(KERN_ALERT PFX
"%s\n", DRV_STRING
);
3473 printk(KERN_ALERT PFX
"Driver name: %s, Version: %s.\n",
3474 DRV_NAME
, DRV_VERSION
);
3476 ql_display_dev_info(ndev
);
3482 iounmap(qdev
->mem_map_registers
);
3485 err_out_free_regions
:
3486 pci_release_regions(pdev
);
3487 err_out_disable_pdev
:
3488 pci_disable_device(pdev
);
3489 pci_set_drvdata(pdev
, NULL
);
3494 static void __devexit
ql3xxx_remove(struct pci_dev
*pdev
)
3496 struct net_device
*ndev
= pci_get_drvdata(pdev
);
3497 struct ql3_adapter
*qdev
= netdev_priv(ndev
);
3499 unregister_netdev(ndev
);
3500 qdev
= netdev_priv(ndev
);
3502 ql_disable_interrupts(qdev
);
3504 if (qdev
->workqueue
) {
3505 cancel_delayed_work(&qdev
->reset_work
);
3506 cancel_delayed_work(&qdev
->tx_timeout_work
);
3507 destroy_workqueue(qdev
->workqueue
);
3508 qdev
->workqueue
= NULL
;
3511 iounmap(qdev
->mem_map_registers
);
3512 pci_release_regions(pdev
);
3513 pci_set_drvdata(pdev
, NULL
);
3517 static struct pci_driver ql3xxx_driver
= {
3520 .id_table
= ql3xxx_pci_tbl
,
3521 .probe
= ql3xxx_probe
,
3522 .remove
= __devexit_p(ql3xxx_remove
),
3525 static int __init
ql3xxx_init_module(void)
3527 return pci_register_driver(&ql3xxx_driver
);
3530 static void __exit
ql3xxx_exit(void)
3532 pci_unregister_driver(&ql3xxx_driver
);
3535 module_init(ql3xxx_init_module
);
3536 module_exit(ql3xxx_exit
);